| 1 | /* |
|---|---|
| 2 | * PowerPC emulation cpu definitions for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef PPC_CPU_H |
| 21 | #define PPC_CPU_H |
| 22 | |
| 23 | #include "qemu/int128.h" |
| 24 | #include "exec/cpu-defs.h" |
| 25 | #include "cpu-qom.h" |
| 26 | #include "exec/cpu-defs.h" |
| 27 | #include "cpu-qom.h" |
| 28 | |
| 29 | /* #define PPC_EMULATE_32BITS_HYPV */ |
| 30 | |
| 31 | #define TCG_GUEST_DEFAULT_MO 0 |
| 32 | |
| 33 | #define TARGET_PAGE_BITS_64K 16 |
| 34 | #define TARGET_PAGE_BITS_16M 24 |
| 35 | |
| 36 | #if defined(TARGET_PPC64) |
| 37 | #define PPC_ELF_MACHINE EM_PPC64 |
| 38 | #else |
| 39 | #define PPC_ELF_MACHINE EM_PPC |
| 40 | #endif |
| 41 | |
| 42 | #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) |
| 43 | #define PPC_BIT32(bit) (0x80000000 >> (bit)) |
| 44 | #define PPC_BIT8(bit) (0x80 >> (bit)) |
| 45 | #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) |
| 46 | #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ |
| 47 | PPC_BIT32(bs)) |
| 48 | #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs)) |
| 49 | |
| 50 | /*****************************************************************************/ |
| 51 | /* Exception vectors definitions */ |
| 52 | enum { |
| 53 | POWERPC_EXCP_NONE = -1, |
| 54 | /* The 64 first entries are used by the PowerPC embedded specification */ |
| 55 | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
| 56 | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
| 57 | POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
| 58 | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
| 59 | POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
| 60 | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
| 61 | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
| 62 | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
| 63 | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
| 64 | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
| 65 | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
| 66 | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
| 67 | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
| 68 | POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
| 69 | POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ |
| 70 | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
| 71 | /* Vectors 16 to 31 are reserved */ |
| 72 | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
| 73 | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
| 74 | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
| 75 | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
| 76 | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
| 77 | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
| 78 | POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */ |
| 79 | POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/ |
| 80 | POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */ |
| 81 | /* Vectors 42 to 63 are reserved */ |
| 82 | /* Exceptions defined in the PowerPC server specification */ |
| 83 | POWERPC_EXCP_RESET = 64, /* System reset exception */ |
| 84 | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
| 85 | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
| 86 | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
| 87 | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
| 88 | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
| 89 | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
| 90 | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
| 91 | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
| 92 | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
| 93 | /* 40x specific exceptions */ |
| 94 | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
| 95 | /* 601 specific exceptions */ |
| 96 | POWERPC_EXCP_IO = 75, /* IO error exception */ |
| 97 | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
| 98 | /* 602 specific exceptions */ |
| 99 | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
| 100 | /* 602/603 specific exceptions */ |
| 101 | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
| 102 | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
| 103 | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
| 104 | /* Exceptions available on most PowerPC */ |
| 105 | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
| 106 | POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
| 107 | POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ |
| 108 | POWERPC_EXCP_SMI = 84, /* System management interrupt */ |
| 109 | POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ |
| 110 | /* 7xx/74xx specific exceptions */ |
| 111 | POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
| 112 | /* 74xx specific exceptions */ |
| 113 | POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
| 114 | /* 970FX specific exceptions */ |
| 115 | POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
| 116 | POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ |
| 117 | /* Freescale embedded cores specific exceptions */ |
| 118 | POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ |
| 119 | POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ |
| 120 | POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ |
| 121 | POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ |
| 122 | /* VSX Unavailable (Power ISA 2.06 and later) */ |
| 123 | POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */ |
| 124 | POWERPC_EXCP_FU = 95, /* Facility Unavailable */ |
| 125 | /* Additional ISA 2.06 and later server exceptions */ |
| 126 | POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */ |
| 127 | POWERPC_EXCP_HV_MAINT = 97, /* HMI */ |
| 128 | POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */ |
| 129 | /* Server doorbell variants */ |
| 130 | POWERPC_EXCP_SDOOR = 99, |
| 131 | POWERPC_EXCP_SDOOR_HV = 100, |
| 132 | /* ISA 3.00 additions */ |
| 133 | POWERPC_EXCP_HVIRT = 101, |
| 134 | /* EOL */ |
| 135 | POWERPC_EXCP_NB = 102, |
| 136 | /* QEMU exceptions: used internally during code translation */ |
| 137 | POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
| 138 | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
| 139 | /* QEMU exceptions: special cases we want to stop translation */ |
| 140 | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
| 141 | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
| 142 | }; |
| 143 | |
| 144 | /* Exceptions error codes */ |
| 145 | enum { |
| 146 | /* Exception subtypes for POWERPC_EXCP_ALIGN */ |
| 147 | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
| 148 | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
| 149 | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
| 150 | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
| 151 | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
| 152 | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
| 153 | /* Exception subtypes for POWERPC_EXCP_PROGRAM */ |
| 154 | /* FP exceptions */ |
| 155 | POWERPC_EXCP_FP = 0x10, |
| 156 | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
| 157 | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
| 158 | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
| 159 | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
| 160 | POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
| 161 | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
| 162 | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
| 163 | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
| 164 | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
| 165 | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
| 166 | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
| 167 | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
| 168 | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
| 169 | /* Invalid instruction */ |
| 170 | POWERPC_EXCP_INVAL = 0x20, |
| 171 | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
| 172 | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
| 173 | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
| 174 | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
| 175 | /* Privileged instruction */ |
| 176 | POWERPC_EXCP_PRIV = 0x30, |
| 177 | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
| 178 | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
| 179 | /* Trap */ |
| 180 | POWERPC_EXCP_TRAP = 0x40, |
| 181 | }; |
| 182 | |
| 183 | #define PPC_INPUT(env) (env->bus_model) |
| 184 | |
| 185 | /*****************************************************************************/ |
| 186 | typedef struct opc_handler_t opc_handler_t; |
| 187 | |
| 188 | /*****************************************************************************/ |
| 189 | /* Types used to describe some PowerPC registers etc. */ |
| 190 | typedef struct DisasContext DisasContext; |
| 191 | typedef struct ppc_spr_t ppc_spr_t; |
| 192 | typedef union ppc_tlb_t ppc_tlb_t; |
| 193 | typedef struct ppc_hash_pte64 ppc_hash_pte64_t; |
| 194 | |
| 195 | /* SPR access micro-ops generations callbacks */ |
| 196 | struct ppc_spr_t { |
| 197 | void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); |
| 198 | void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); |
| 199 | #if !defined(CONFIG_USER_ONLY) |
| 200 | void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); |
| 201 | void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); |
| 202 | void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); |
| 203 | void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); |
| 204 | unsigned int gdb_id; |
| 205 | #endif |
| 206 | const char *name; |
| 207 | target_ulong default_value; |
| 208 | #ifdef CONFIG_KVM |
| 209 | /* |
| 210 | * We (ab)use the fact that all the SPRs will have ids for the |
| 211 | * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, |
| 212 | * don't sync this |
| 213 | */ |
| 214 | uint64_t one_reg_id; |
| 215 | #endif |
| 216 | }; |
| 217 | |
| 218 | /* VSX/Altivec registers (128 bits) */ |
| 219 | typedef union _ppc_vsr_t { |
| 220 | uint8_t u8[16]; |
| 221 | uint16_t u16[8]; |
| 222 | uint32_t u32[4]; |
| 223 | uint64_t u64[2]; |
| 224 | int8_t s8[16]; |
| 225 | int16_t s16[8]; |
| 226 | int32_t s32[4]; |
| 227 | int64_t s64[2]; |
| 228 | float32 f32[4]; |
| 229 | float64 f64[2]; |
| 230 | float128 f128; |
| 231 | #ifdef CONFIG_INT128 |
| 232 | __uint128_t u128; |
| 233 | #endif |
| 234 | Int128 s128; |
| 235 | } ppc_vsr_t; |
| 236 | |
| 237 | typedef ppc_vsr_t ppc_avr_t; |
| 238 | |
| 239 | #if !defined(CONFIG_USER_ONLY) |
| 240 | /* Software TLB cache */ |
| 241 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
| 242 | struct ppc6xx_tlb_t { |
| 243 | target_ulong pte0; |
| 244 | target_ulong pte1; |
| 245 | target_ulong EPN; |
| 246 | }; |
| 247 | |
| 248 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
| 249 | struct ppcemb_tlb_t { |
| 250 | uint64_t RPN; |
| 251 | target_ulong EPN; |
| 252 | target_ulong PID; |
| 253 | target_ulong size; |
| 254 | uint32_t prot; |
| 255 | uint32_t attr; /* Storage attributes */ |
| 256 | }; |
| 257 | |
| 258 | typedef struct ppcmas_tlb_t { |
| 259 | uint32_t mas8; |
| 260 | uint32_t mas1; |
| 261 | uint64_t mas2; |
| 262 | uint64_t mas7_3; |
| 263 | } ppcmas_tlb_t; |
| 264 | |
| 265 | union ppc_tlb_t { |
| 266 | ppc6xx_tlb_t *tlb6; |
| 267 | ppcemb_tlb_t *tlbe; |
| 268 | ppcmas_tlb_t *tlbm; |
| 269 | }; |
| 270 | |
| 271 | /* possible TLB variants */ |
| 272 | #define TLB_NONE 0 |
| 273 | #define TLB_6XX 1 |
| 274 | #define TLB_EMB 2 |
| 275 | #define TLB_MAS 3 |
| 276 | #endif |
| 277 | |
| 278 | typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes; |
| 279 | |
| 280 | typedef struct ppc_slb_t ppc_slb_t; |
| 281 | struct ppc_slb_t { |
| 282 | uint64_t esid; |
| 283 | uint64_t vsid; |
| 284 | const PPCHash64SegmentPageSizes *sps; |
| 285 | }; |
| 286 | |
| 287 | #define MAX_SLB_ENTRIES 64 |
| 288 | #define SEGMENT_SHIFT_256M 28 |
| 289 | #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) |
| 290 | |
| 291 | #define SEGMENT_SHIFT_1T 40 |
| 292 | #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) |
| 293 | |
| 294 | typedef struct ppc_v3_pate_t { |
| 295 | uint64_t dw0; |
| 296 | uint64_t dw1; |
| 297 | } ppc_v3_pate_t; |
| 298 | |
| 299 | /*****************************************************************************/ |
| 300 | /* Machine state register bits definition */ |
| 301 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
| 302 | #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
| 303 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
| 304 | #define MSR_SHV 60 /* hypervisor state hflags */ |
| 305 | #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ |
| 306 | #define MSR_TS1 33 |
| 307 | #define MSR_TM 32 /* Transactional Memory Available (Book3s) */ |
| 308 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
| 309 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
| 310 | #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
| 311 | #define MSR_GS 28 /* guest state for BookE */ |
| 312 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
| 313 | #define MSR_VR 25 /* altivec available x hflags */ |
| 314 | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
| 315 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
| 316 | #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */ |
| 317 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
| 318 | #define MSR_KEY 19 /* key bit on 603e */ |
| 319 | #define MSR_POW 18 /* Power management */ |
| 320 | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
| 321 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
| 322 | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
| 323 | #define MSR_EE 15 /* External interrupt enable */ |
| 324 | #define MSR_PR 14 /* Problem state hflags */ |
| 325 | #define MSR_FP 13 /* Floating point available hflags */ |
| 326 | #define MSR_ME 12 /* Machine check interrupt enable */ |
| 327 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
| 328 | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
| 329 | #define MSR_DWE 10 /* Debug wait enable on 405 x */ |
| 330 | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
| 331 | #define MSR_BE 9 /* Branch trace enable x hflags */ |
| 332 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
| 333 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
| 334 | #define MSR_AL 7 /* AL bit on POWER */ |
| 335 | #define MSR_EP 6 /* Exception prefix on 601 */ |
| 336 | #define MSR_IR 5 /* Instruction relocate */ |
| 337 | #define MSR_DR 4 /* Data relocate */ |
| 338 | #define MSR_IS 5 /* Instruction address space (BookE) */ |
| 339 | #define MSR_DS 4 /* Data address space (BookE) */ |
| 340 | #define MSR_PE 3 /* Protection enable on 403 */ |
| 341 | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
| 342 | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
| 343 | #define MSR_RI 1 /* Recoverable interrupt 1 */ |
| 344 | #define MSR_LE 0 /* Little-endian mode 1 hflags */ |
| 345 | |
| 346 | /* LPCR bits */ |
| 347 | #define LPCR_VPM0 PPC_BIT(0) |
| 348 | #define LPCR_VPM1 PPC_BIT(1) |
| 349 | #define LPCR_ISL PPC_BIT(2) |
| 350 | #define LPCR_KBV PPC_BIT(3) |
| 351 | #define LPCR_DPFD_SHIFT (63 - 11) |
| 352 | #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) |
| 353 | #define LPCR_VRMASD_SHIFT (63 - 16) |
| 354 | #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) |
| 355 | /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ |
| 356 | #define LPCR_PECE_U_SHIFT (63 - 19) |
| 357 | #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) |
| 358 | #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ |
| 359 | #define LPCR_RMLS_SHIFT (63 - 37) |
| 360 | #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) |
| 361 | #define LPCR_ILE PPC_BIT(38) |
| 362 | #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ |
| 363 | #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) |
| 364 | #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ |
| 365 | #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ |
| 366 | #define LPCR_HR PPC_BIT(43) /* Host Radix */ |
| 367 | #define LPCR_ONL PPC_BIT(45) |
| 368 | #define LPCR_LD PPC_BIT(46) /* Large Decrementer */ |
| 369 | #define LPCR_P7_PECE0 PPC_BIT(49) |
| 370 | #define LPCR_P7_PECE1 PPC_BIT(50) |
| 371 | #define LPCR_P7_PECE2 PPC_BIT(51) |
| 372 | #define LPCR_P8_PECE0 PPC_BIT(47) |
| 373 | #define LPCR_P8_PECE1 PPC_BIT(48) |
| 374 | #define LPCR_P8_PECE2 PPC_BIT(49) |
| 375 | #define LPCR_P8_PECE3 PPC_BIT(50) |
| 376 | #define LPCR_P8_PECE4 PPC_BIT(51) |
| 377 | /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ |
| 378 | #define LPCR_PECE_L_SHIFT (63 - 51) |
| 379 | #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) |
| 380 | #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */ |
| 381 | #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */ |
| 382 | #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */ |
| 383 | #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */ |
| 384 | #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */ |
| 385 | #define LPCR_MER PPC_BIT(52) |
| 386 | #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */ |
| 387 | #define LPCR_TC PPC_BIT(54) |
| 388 | #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */ |
| 389 | #define LPCR_LPES0 PPC_BIT(60) |
| 390 | #define LPCR_LPES1 PPC_BIT(61) |
| 391 | #define LPCR_RMI PPC_BIT(62) |
| 392 | #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */ |
| 393 | #define LPCR_HDICE PPC_BIT(63) |
| 394 | |
| 395 | /* PSSCR bits */ |
| 396 | #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ |
| 397 | #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ |
| 398 | |
| 399 | #define msr_sf ((env->msr >> MSR_SF) & 1) |
| 400 | #define msr_isf ((env->msr >> MSR_ISF) & 1) |
| 401 | #define msr_shv ((env->msr >> MSR_SHV) & 1) |
| 402 | #define msr_cm ((env->msr >> MSR_CM) & 1) |
| 403 | #define msr_icm ((env->msr >> MSR_ICM) & 1) |
| 404 | #define msr_thv ((env->msr >> MSR_THV) & 1) |
| 405 | #define msr_gs ((env->msr >> MSR_GS) & 1) |
| 406 | #define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
| 407 | #define msr_vr ((env->msr >> MSR_VR) & 1) |
| 408 | #define msr_spe ((env->msr >> MSR_SPE) & 1) |
| 409 | #define msr_ap ((env->msr >> MSR_AP) & 1) |
| 410 | #define msr_vsx ((env->msr >> MSR_VSX) & 1) |
| 411 | #define msr_sa ((env->msr >> MSR_SA) & 1) |
| 412 | #define msr_key ((env->msr >> MSR_KEY) & 1) |
| 413 | #define msr_pow ((env->msr >> MSR_POW) & 1) |
| 414 | #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) |
| 415 | #define msr_ce ((env->msr >> MSR_CE) & 1) |
| 416 | #define msr_ile ((env->msr >> MSR_ILE) & 1) |
| 417 | #define msr_ee ((env->msr >> MSR_EE) & 1) |
| 418 | #define msr_pr ((env->msr >> MSR_PR) & 1) |
| 419 | #define msr_fp ((env->msr >> MSR_FP) & 1) |
| 420 | #define msr_me ((env->msr >> MSR_ME) & 1) |
| 421 | #define msr_fe0 ((env->msr >> MSR_FE0) & 1) |
| 422 | #define msr_se ((env->msr >> MSR_SE) & 1) |
| 423 | #define msr_dwe ((env->msr >> MSR_DWE) & 1) |
| 424 | #define msr_uble ((env->msr >> MSR_UBLE) & 1) |
| 425 | #define msr_be ((env->msr >> MSR_BE) & 1) |
| 426 | #define msr_de ((env->msr >> MSR_DE) & 1) |
| 427 | #define msr_fe1 ((env->msr >> MSR_FE1) & 1) |
| 428 | #define msr_al ((env->msr >> MSR_AL) & 1) |
| 429 | #define msr_ep ((env->msr >> MSR_EP) & 1) |
| 430 | #define msr_ir ((env->msr >> MSR_IR) & 1) |
| 431 | #define msr_dr ((env->msr >> MSR_DR) & 1) |
| 432 | #define msr_is ((env->msr >> MSR_IS) & 1) |
| 433 | #define msr_ds ((env->msr >> MSR_DS) & 1) |
| 434 | #define msr_pe ((env->msr >> MSR_PE) & 1) |
| 435 | #define msr_px ((env->msr >> MSR_PX) & 1) |
| 436 | #define msr_pmm ((env->msr >> MSR_PMM) & 1) |
| 437 | #define msr_ri ((env->msr >> MSR_RI) & 1) |
| 438 | #define msr_le ((env->msr >> MSR_LE) & 1) |
| 439 | #define msr_ts ((env->msr >> MSR_TS1) & 3) |
| 440 | #define msr_tm ((env->msr >> MSR_TM) & 1) |
| 441 | |
| 442 | #define DBCR0_ICMP (1 << 27) |
| 443 | #define DBCR0_BRT (1 << 26) |
| 444 | #define DBSR_ICMP (1 << 27) |
| 445 | #define DBSR_BRT (1 << 26) |
| 446 | |
| 447 | /* Hypervisor bit is more specific */ |
| 448 | #if defined(TARGET_PPC64) |
| 449 | #define MSR_HVB (1ULL << MSR_SHV) |
| 450 | #define msr_hv msr_shv |
| 451 | #else |
| 452 | #if defined(PPC_EMULATE_32BITS_HYPV) |
| 453 | #define MSR_HVB (1ULL << MSR_THV) |
| 454 | #define msr_hv msr_thv |
| 455 | #else |
| 456 | #define MSR_HVB (0ULL) |
| 457 | #define msr_hv (0) |
| 458 | #endif |
| 459 | #endif |
| 460 | |
| 461 | /* DSISR */ |
| 462 | #define DSISR_NOPTE 0x40000000 |
| 463 | /* Not permitted by access authority of encoded access authority */ |
| 464 | #define DSISR_PROTFAULT 0x08000000 |
| 465 | #define DSISR_ISSTORE 0x02000000 |
| 466 | /* Not permitted by virtual page class key protection */ |
| 467 | #define DSISR_AMR 0x00200000 |
| 468 | /* Unsupported Radix Tree Configuration */ |
| 469 | #define DSISR_R_BADCONFIG 0x00080000 |
| 470 | |
| 471 | /* SRR1 error code fields */ |
| 472 | |
| 473 | #define SRR1_NOPTE DSISR_NOPTE |
| 474 | /* Not permitted due to no-execute or guard bit set */ |
| 475 | #define SRR1_NOEXEC_GUARD 0x10000000 |
| 476 | #define SRR1_PROTFAULT DSISR_PROTFAULT |
| 477 | #define SRR1_IAMR DSISR_AMR |
| 478 | |
| 479 | /* Facility Status and Control (FSCR) bits */ |
| 480 | #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ |
| 481 | #define FSCR_TAR (63 - 55) /* Target Address Register */ |
| 482 | /* Interrupt cause mask and position in FSCR. HFSCR has the same format */ |
| 483 | #define FSCR_IC_MASK (0xFFULL) |
| 484 | #define FSCR_IC_POS (63 - 7) |
| 485 | #define FSCR_IC_DSCR_SPR3 2 |
| 486 | #define FSCR_IC_PMU 3 |
| 487 | #define FSCR_IC_BHRB 4 |
| 488 | #define FSCR_IC_TM 5 |
| 489 | #define FSCR_IC_EBB 7 |
| 490 | #define FSCR_IC_TAR 8 |
| 491 | |
| 492 | /* Exception state register bits definition */ |
| 493 | #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */ |
| 494 | #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */ |
| 495 | #define ESR_PTR PPC_BIT(38) /* Trap */ |
| 496 | #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */ |
| 497 | #define ESR_ST PPC_BIT(40) /* Store Operation */ |
| 498 | #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */ |
| 499 | #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */ |
| 500 | #define ESR_BO PPC_BIT(46) /* Byte Ordering */ |
| 501 | #define ESR_PIE PPC_BIT(47) /* Imprecise exception */ |
| 502 | #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */ |
| 503 | #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */ |
| 504 | #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */ |
| 505 | #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */ |
| 506 | #define ESR_EPID PPC_BIT(57) /* External Process ID operation */ |
| 507 | #define ESR_VLEMI PPC_BIT(58) /* VLE operation */ |
| 508 | #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */ |
| 509 | |
| 510 | /* Transaction EXception And Summary Register bits */ |
| 511 | #define TEXASR_FAILURE_PERSISTENT (63 - 7) |
| 512 | #define TEXASR_DISALLOWED (63 - 8) |
| 513 | #define TEXASR_NESTING_OVERFLOW (63 - 9) |
| 514 | #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) |
| 515 | #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) |
| 516 | #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) |
| 517 | #define TEXASR_TRANSACTION_CONFLICT (63 - 13) |
| 518 | #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) |
| 519 | #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) |
| 520 | #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) |
| 521 | #define TEXASR_ABORT (63 - 31) |
| 522 | #define TEXASR_SUSPENDED (63 - 32) |
| 523 | #define TEXASR_PRIVILEGE_HV (63 - 34) |
| 524 | #define TEXASR_PRIVILEGE_PR (63 - 35) |
| 525 | #define TEXASR_FAILURE_SUMMARY (63 - 36) |
| 526 | #define TEXASR_TFIAR_EXACT (63 - 37) |
| 527 | #define TEXASR_ROT (63 - 38) |
| 528 | #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ |
| 529 | |
| 530 | enum { |
| 531 | POWERPC_FLAG_NONE = 0x00000000, |
| 532 | /* Flag for MSR bit 25 signification (VRE/SPE) */ |
| 533 | POWERPC_FLAG_SPE = 0x00000001, |
| 534 | POWERPC_FLAG_VRE = 0x00000002, |
| 535 | /* Flag for MSR bit 17 signification (TGPR/CE) */ |
| 536 | POWERPC_FLAG_TGPR = 0x00000004, |
| 537 | POWERPC_FLAG_CE = 0x00000008, |
| 538 | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ |
| 539 | POWERPC_FLAG_SE = 0x00000010, |
| 540 | POWERPC_FLAG_DWE = 0x00000020, |
| 541 | POWERPC_FLAG_UBLE = 0x00000040, |
| 542 | /* Flag for MSR bit 9 signification (BE/DE) */ |
| 543 | POWERPC_FLAG_BE = 0x00000080, |
| 544 | POWERPC_FLAG_DE = 0x00000100, |
| 545 | /* Flag for MSR bit 2 signification (PX/PMM) */ |
| 546 | POWERPC_FLAG_PX = 0x00000200, |
| 547 | POWERPC_FLAG_PMM = 0x00000400, |
| 548 | /* Flag for special features */ |
| 549 | /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ |
| 550 | POWERPC_FLAG_RTC_CLK = 0x00010000, |
| 551 | POWERPC_FLAG_BUS_CLK = 0x00020000, |
| 552 | /* Has CFAR */ |
| 553 | POWERPC_FLAG_CFAR = 0x00040000, |
| 554 | /* Has VSX */ |
| 555 | POWERPC_FLAG_VSX = 0x00080000, |
| 556 | /* Has Transaction Memory (ISA 2.07) */ |
| 557 | POWERPC_FLAG_TM = 0x00100000, |
| 558 | }; |
| 559 | |
| 560 | /*****************************************************************************/ |
| 561 | /* Floating point status and control register */ |
| 562 | #define FPSCR_FX 31 /* Floating-point exception summary */ |
| 563 | #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ |
| 564 | #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ |
| 565 | #define FPSCR_OX 28 /* Floating-point overflow exception */ |
| 566 | #define FPSCR_UX 27 /* Floating-point underflow exception */ |
| 567 | #define FPSCR_ZX 26 /* Floating-point zero divide exception */ |
| 568 | #define FPSCR_XX 25 /* Floating-point inexact exception */ |
| 569 | #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ |
| 570 | #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ |
| 571 | #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ |
| 572 | #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ |
| 573 | #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ |
| 574 | #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ |
| 575 | #define FPSCR_FR 18 /* Floating-point fraction rounded */ |
| 576 | #define FPSCR_FI 17 /* Floating-point fraction inexact */ |
| 577 | #define FPSCR_C 16 /* Floating-point result class descriptor */ |
| 578 | #define FPSCR_FL 15 /* Floating-point less than or negative */ |
| 579 | #define FPSCR_FG 14 /* Floating-point greater than or negative */ |
| 580 | #define FPSCR_FE 13 /* Floating-point equal or zero */ |
| 581 | #define FPSCR_FU 12 /* Floating-point unordered or NaN */ |
| 582 | #define FPSCR_FPCC 12 /* Floating-point condition code */ |
| 583 | #define FPSCR_FPRF 12 /* Floating-point result flags */ |
| 584 | #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ |
| 585 | #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ |
| 586 | #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ |
| 587 | #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ |
| 588 | #define FPSCR_OE 6 /* Floating-point overflow exception enable */ |
| 589 | #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ |
| 590 | #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ |
| 591 | #define FPSCR_XE 3 /* Floating-point inexact exception enable */ |
| 592 | #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ |
| 593 | #define FPSCR_RN1 1 |
| 594 | #define FPSCR_RN0 0 /* Floating-point rounding control */ |
| 595 | #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) |
| 596 | #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) |
| 597 | #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) |
| 598 | #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) |
| 599 | #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) |
| 600 | #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) |
| 601 | #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) |
| 602 | #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) |
| 603 | #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) |
| 604 | #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) |
| 605 | #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) |
| 606 | #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) |
| 607 | #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) |
| 608 | #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) |
| 609 | #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) |
| 610 | #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) |
| 611 | #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) |
| 612 | #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) |
| 613 | #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) |
| 614 | #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) |
| 615 | #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) |
| 616 | #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) |
| 617 | #define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3) |
| 618 | /* Invalid operation exception summary */ |
| 619 | #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ |
| 620 | (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ |
| 621 | (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ |
| 622 | (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ |
| 623 | (1 << FPSCR_VXCVI))) |
| 624 | /* exception summary */ |
| 625 | #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) |
| 626 | /* enabled exception summary */ |
| 627 | #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ |
| 628 | 0x1F) |
| 629 | |
| 630 | #define FP_FX (1ull << FPSCR_FX) |
| 631 | #define FP_FEX (1ull << FPSCR_FEX) |
| 632 | #define FP_VX (1ull << FPSCR_VX) |
| 633 | #define FP_OX (1ull << FPSCR_OX) |
| 634 | #define FP_UX (1ull << FPSCR_UX) |
| 635 | #define FP_ZX (1ull << FPSCR_ZX) |
| 636 | #define FP_XX (1ull << FPSCR_XX) |
| 637 | #define FP_VXSNAN (1ull << FPSCR_VXSNAN) |
| 638 | #define FP_VXISI (1ull << FPSCR_VXISI) |
| 639 | #define FP_VXIDI (1ull << FPSCR_VXIDI) |
| 640 | #define FP_VXZDZ (1ull << FPSCR_VXZDZ) |
| 641 | #define FP_VXIMZ (1ull << FPSCR_VXIMZ) |
| 642 | #define FP_VXVC (1ull << FPSCR_VXVC) |
| 643 | #define FP_FR (1ull << FPSCR_FR) |
| 644 | #define FP_FI (1ull << FPSCR_FI) |
| 645 | #define FP_C (1ull << FPSCR_C) |
| 646 | #define FP_FL (1ull << FPSCR_FL) |
| 647 | #define FP_FG (1ull << FPSCR_FG) |
| 648 | #define FP_FE (1ull << FPSCR_FE) |
| 649 | #define FP_FU (1ull << FPSCR_FU) |
| 650 | #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU) |
| 651 | #define FP_FPRF (FP_C | FP_FPCC) |
| 652 | #define FP_VXSOFT (1ull << FPSCR_VXSOFT) |
| 653 | #define FP_VXSQRT (1ull << FPSCR_VXSQRT) |
| 654 | #define FP_VXCVI (1ull << FPSCR_VXCVI) |
| 655 | #define FP_VE (1ull << FPSCR_VE) |
| 656 | #define FP_OE (1ull << FPSCR_OE) |
| 657 | #define FP_UE (1ull << FPSCR_UE) |
| 658 | #define FP_ZE (1ull << FPSCR_ZE) |
| 659 | #define FP_XE (1ull << FPSCR_XE) |
| 660 | #define FP_NI (1ull << FPSCR_NI) |
| 661 | #define FP_RN1 (1ull << FPSCR_RN1) |
| 662 | #define FP_RN0 (1ull << FPSCR_RN0) |
| 663 | #define FP_RN (FP_RN1 | FP_RN0) |
| 664 | |
| 665 | #define FP_MODE FP_RN |
| 666 | #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE) |
| 667 | #define FP_STATUS (FP_FR | FP_FI | FP_FPRF) |
| 668 | |
| 669 | /* the exception bits which can be cleared by mcrfs - includes FX */ |
| 670 | #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \ |
| 671 | FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \ |
| 672 | FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ |
| 673 | FP_VXSQRT | FP_VXCVI) |
| 674 | |
| 675 | /*****************************************************************************/ |
| 676 | /* Vector status and control register */ |
| 677 | #define VSCR_NJ 16 /* Vector non-java */ |
| 678 | #define VSCR_SAT 0 /* Vector saturation */ |
| 679 | |
| 680 | /*****************************************************************************/ |
| 681 | /* BookE e500 MMU registers */ |
| 682 | |
| 683 | #define MAS0_NV_SHIFT 0 |
| 684 | #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) |
| 685 | |
| 686 | #define MAS0_WQ_SHIFT 12 |
| 687 | #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) |
| 688 | /* Write TLB entry regardless of reservation */ |
| 689 | #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) |
| 690 | /* Write TLB entry only already in use */ |
| 691 | #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) |
| 692 | /* Clear TLB entry */ |
| 693 | #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) |
| 694 | |
| 695 | #define MAS0_HES_SHIFT 14 |
| 696 | #define MAS0_HES (1 << MAS0_HES_SHIFT) |
| 697 | |
| 698 | #define MAS0_ESEL_SHIFT 16 |
| 699 | #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) |
| 700 | |
| 701 | #define MAS0_TLBSEL_SHIFT 28 |
| 702 | #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) |
| 703 | #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) |
| 704 | #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) |
| 705 | #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) |
| 706 | #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) |
| 707 | |
| 708 | #define MAS0_ATSEL_SHIFT 31 |
| 709 | #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) |
| 710 | #define MAS0_ATSEL_TLB 0 |
| 711 | #define MAS0_ATSEL_LRAT MAS0_ATSEL |
| 712 | |
| 713 | #define MAS1_TSIZE_SHIFT 7 |
| 714 | #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) |
| 715 | |
| 716 | #define MAS1_TS_SHIFT 12 |
| 717 | #define MAS1_TS (1 << MAS1_TS_SHIFT) |
| 718 | |
| 719 | #define MAS1_IND_SHIFT 13 |
| 720 | #define MAS1_IND (1 << MAS1_IND_SHIFT) |
| 721 | |
| 722 | #define MAS1_TID_SHIFT 16 |
| 723 | #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) |
| 724 | |
| 725 | #define MAS1_IPROT_SHIFT 30 |
| 726 | #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) |
| 727 | |
| 728 | #define MAS1_VALID_SHIFT 31 |
| 729 | #define MAS1_VALID 0x80000000 |
| 730 | |
| 731 | #define MAS2_EPN_SHIFT 12 |
| 732 | #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT) |
| 733 | |
| 734 | #define MAS2_ACM_SHIFT 6 |
| 735 | #define MAS2_ACM (1 << MAS2_ACM_SHIFT) |
| 736 | |
| 737 | #define MAS2_VLE_SHIFT 5 |
| 738 | #define MAS2_VLE (1 << MAS2_VLE_SHIFT) |
| 739 | |
| 740 | #define MAS2_W_SHIFT 4 |
| 741 | #define MAS2_W (1 << MAS2_W_SHIFT) |
| 742 | |
| 743 | #define MAS2_I_SHIFT 3 |
| 744 | #define MAS2_I (1 << MAS2_I_SHIFT) |
| 745 | |
| 746 | #define MAS2_M_SHIFT 2 |
| 747 | #define MAS2_M (1 << MAS2_M_SHIFT) |
| 748 | |
| 749 | #define MAS2_G_SHIFT 1 |
| 750 | #define MAS2_G (1 << MAS2_G_SHIFT) |
| 751 | |
| 752 | #define MAS2_E_SHIFT 0 |
| 753 | #define MAS2_E (1 << MAS2_E_SHIFT) |
| 754 | |
| 755 | #define MAS3_RPN_SHIFT 12 |
| 756 | #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) |
| 757 | |
| 758 | #define MAS3_U0 0x00000200 |
| 759 | #define MAS3_U1 0x00000100 |
| 760 | #define MAS3_U2 0x00000080 |
| 761 | #define MAS3_U3 0x00000040 |
| 762 | #define MAS3_UX 0x00000020 |
| 763 | #define MAS3_SX 0x00000010 |
| 764 | #define MAS3_UW 0x00000008 |
| 765 | #define MAS3_SW 0x00000004 |
| 766 | #define MAS3_UR 0x00000002 |
| 767 | #define MAS3_SR 0x00000001 |
| 768 | #define MAS3_SPSIZE_SHIFT 1 |
| 769 | #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) |
| 770 | |
| 771 | #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT |
| 772 | #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK |
| 773 | #define MAS4_TIDSELD_MASK 0x00030000 |
| 774 | #define MAS4_TIDSELD_PID0 0x00000000 |
| 775 | #define MAS4_TIDSELD_PID1 0x00010000 |
| 776 | #define MAS4_TIDSELD_PID2 0x00020000 |
| 777 | #define MAS4_TIDSELD_PIDZ 0x00030000 |
| 778 | #define MAS4_INDD 0x00008000 /* Default IND */ |
| 779 | #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT |
| 780 | #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK |
| 781 | #define MAS4_ACMD 0x00000040 |
| 782 | #define MAS4_VLED 0x00000020 |
| 783 | #define MAS4_WD 0x00000010 |
| 784 | #define MAS4_ID 0x00000008 |
| 785 | #define MAS4_MD 0x00000004 |
| 786 | #define MAS4_GD 0x00000002 |
| 787 | #define MAS4_ED 0x00000001 |
| 788 | #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ |
| 789 | #define MAS4_WIMGED_SHIFT 0 |
| 790 | |
| 791 | #define MAS5_SGS 0x80000000 |
| 792 | #define MAS5_SLPID_MASK 0x00000fff |
| 793 | |
| 794 | #define MAS6_SPID0 0x3fff0000 |
| 795 | #define MAS6_SPID1 0x00007ffe |
| 796 | #define MAS6_ISIZE(x) MAS1_TSIZE(x) |
| 797 | #define MAS6_SAS 0x00000001 |
| 798 | #define MAS6_SPID MAS6_SPID0 |
| 799 | #define MAS6_SIND 0x00000002 /* Indirect page */ |
| 800 | #define MAS6_SIND_SHIFT 1 |
| 801 | #define MAS6_SPID_MASK 0x3fff0000 |
| 802 | #define MAS6_SPID_SHIFT 16 |
| 803 | #define MAS6_ISIZE_MASK 0x00000f80 |
| 804 | #define MAS6_ISIZE_SHIFT 7 |
| 805 | |
| 806 | #define MAS7_RPN 0xffffffff |
| 807 | |
| 808 | #define MAS8_TGS 0x80000000 |
| 809 | #define MAS8_VF 0x40000000 |
| 810 | #define MAS8_TLBPID 0x00000fff |
| 811 | |
| 812 | /* Bit definitions for MMUCFG */ |
| 813 | #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ |
| 814 | #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ |
| 815 | #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ |
| 816 | #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ |
| 817 | #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ |
| 818 | #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ |
| 819 | #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ |
| 820 | #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ |
| 821 | #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ |
| 822 | |
| 823 | /* Bit definitions for MMUCSR0 */ |
| 824 | #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ |
| 825 | #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ |
| 826 | #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ |
| 827 | #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ |
| 828 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ |
| 829 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) |
| 830 | #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ |
| 831 | #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ |
| 832 | #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ |
| 833 | #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ |
| 834 | |
| 835 | /* TLBnCFG encoding */ |
| 836 | #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ |
| 837 | #define TLBnCFG_HES 0x00002000 /* HW select supported */ |
| 838 | #define TLBnCFG_AVAIL 0x00004000 /* variable page size */ |
| 839 | #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ |
| 840 | #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ |
| 841 | #define TLBnCFG_IND 0x00020000 /* IND entries supported */ |
| 842 | #define TLBnCFG_PT 0x00040000 /* Can load from page table */ |
| 843 | #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ |
| 844 | #define TLBnCFG_MINSIZE_SHIFT 20 |
| 845 | #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ |
| 846 | #define TLBnCFG_MAXSIZE_SHIFT 16 |
| 847 | #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ |
| 848 | #define TLBnCFG_ASSOC_SHIFT 24 |
| 849 | |
| 850 | /* TLBnPS encoding */ |
| 851 | #define TLBnPS_4K 0x00000004 |
| 852 | #define TLBnPS_8K 0x00000008 |
| 853 | #define TLBnPS_16K 0x00000010 |
| 854 | #define TLBnPS_32K 0x00000020 |
| 855 | #define TLBnPS_64K 0x00000040 |
| 856 | #define TLBnPS_128K 0x00000080 |
| 857 | #define TLBnPS_256K 0x00000100 |
| 858 | #define TLBnPS_512K 0x00000200 |
| 859 | #define TLBnPS_1M 0x00000400 |
| 860 | #define TLBnPS_2M 0x00000800 |
| 861 | #define TLBnPS_4M 0x00001000 |
| 862 | #define TLBnPS_8M 0x00002000 |
| 863 | #define TLBnPS_16M 0x00004000 |
| 864 | #define TLBnPS_32M 0x00008000 |
| 865 | #define TLBnPS_64M 0x00010000 |
| 866 | #define TLBnPS_128M 0x00020000 |
| 867 | #define TLBnPS_256M 0x00040000 |
| 868 | #define TLBnPS_512M 0x00080000 |
| 869 | #define TLBnPS_1G 0x00100000 |
| 870 | #define TLBnPS_2G 0x00200000 |
| 871 | #define TLBnPS_4G 0x00400000 |
| 872 | #define TLBnPS_8G 0x00800000 |
| 873 | #define TLBnPS_16G 0x01000000 |
| 874 | #define TLBnPS_32G 0x02000000 |
| 875 | #define TLBnPS_64G 0x04000000 |
| 876 | #define TLBnPS_128G 0x08000000 |
| 877 | #define TLBnPS_256G 0x10000000 |
| 878 | |
| 879 | /* tlbilx action encoding */ |
| 880 | #define TLBILX_T_ALL 0 |
| 881 | #define TLBILX_T_TID 1 |
| 882 | #define TLBILX_T_FULLMATCH 3 |
| 883 | #define TLBILX_T_CLASS0 4 |
| 884 | #define TLBILX_T_CLASS1 5 |
| 885 | #define TLBILX_T_CLASS2 6 |
| 886 | #define TLBILX_T_CLASS3 7 |
| 887 | |
| 888 | /* BookE 2.06 helper defines */ |
| 889 | |
| 890 | #define BOOKE206_FLUSH_TLB0 (1 << 0) |
| 891 | #define BOOKE206_FLUSH_TLB1 (1 << 1) |
| 892 | #define BOOKE206_FLUSH_TLB2 (1 << 2) |
| 893 | #define BOOKE206_FLUSH_TLB3 (1 << 3) |
| 894 | |
| 895 | /* number of possible TLBs */ |
| 896 | #define BOOKE206_MAX_TLBN 4 |
| 897 | |
| 898 | #define EPID_EPID_SHIFT 0x0 |
| 899 | #define EPID_EPID 0xFF |
| 900 | #define EPID_ELPID_SHIFT 0x10 |
| 901 | #define EPID_ELPID 0x3F0000 |
| 902 | #define EPID_EGS 0x20000000 |
| 903 | #define EPID_EGS_SHIFT 29 |
| 904 | #define EPID_EAS 0x40000000 |
| 905 | #define EPID_EAS_SHIFT 30 |
| 906 | #define EPID_EPR 0x80000000 |
| 907 | #define EPID_EPR_SHIFT 31 |
| 908 | /* We don't support EGS and ELPID */ |
| 909 | #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR) |
| 910 | |
| 911 | /*****************************************************************************/ |
| 912 | /* Server and Embedded Processor Control */ |
| 913 | |
| 914 | #define DBELL_TYPE_SHIFT 27 |
| 915 | #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT) |
| 916 | #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT) |
| 917 | #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT) |
| 918 | #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT) |
| 919 | #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT) |
| 920 | #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT) |
| 921 | |
| 922 | #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT) |
| 923 | |
| 924 | #define DBELL_BRDCAST PPC_BIT(37) |
| 925 | #define DBELL_LPIDTAG_SHIFT 14 |
| 926 | #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) |
| 927 | #define DBELL_PIRTAG_MASK 0x3fff |
| 928 | |
| 929 | #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63) |
| 930 | |
| 931 | #define PPC_PAGE_SIZES_MAX_SZ 8 |
| 932 | |
| 933 | struct ppc_radix_page_info { |
| 934 | uint32_t count; |
| 935 | uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; |
| 936 | }; |
| 937 | |
| 938 | /*****************************************************************************/ |
| 939 | /* The whole PowerPC CPU context */ |
| 940 | |
| 941 | /* |
| 942 | * PowerPC needs eight modes for different hypervisor/supervisor/guest |
| 943 | * + real/paged mode combinations. The other two modes are for |
| 944 | * external PID load/store. |
| 945 | */ |
| 946 | #define MMU_MODE8_SUFFIX _epl |
| 947 | #define MMU_MODE9_SUFFIX _eps |
| 948 | #define PPC_TLB_EPID_LOAD 8 |
| 949 | #define PPC_TLB_EPID_STORE 9 |
| 950 | |
| 951 | #define PPC_CPU_OPCODES_LEN 0x40 |
| 952 | #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 |
| 953 | |
| 954 | struct CPUPPCState { |
| 955 | /* |
| 956 | * First are the most commonly used resources during translated |
| 957 | * code execution |
| 958 | */ |
| 959 | /* general purpose registers */ |
| 960 | target_ulong gpr[32]; |
| 961 | /* Storage for GPR MSB, used by the SPE extension */ |
| 962 | target_ulong gprh[32]; |
| 963 | /* LR */ |
| 964 | target_ulong lr; |
| 965 | /* CTR */ |
| 966 | target_ulong ctr; |
| 967 | /* condition register */ |
| 968 | uint32_t crf[8]; |
| 969 | #if defined(TARGET_PPC64) |
| 970 | /* CFAR */ |
| 971 | target_ulong cfar; |
| 972 | #endif |
| 973 | /* XER (with SO, OV, CA split out) */ |
| 974 | target_ulong xer; |
| 975 | target_ulong so; |
| 976 | target_ulong ov; |
| 977 | target_ulong ca; |
| 978 | target_ulong ov32; |
| 979 | target_ulong ca32; |
| 980 | /* Reservation address */ |
| 981 | target_ulong reserve_addr; |
| 982 | /* Reservation value */ |
| 983 | target_ulong reserve_val; |
| 984 | target_ulong reserve_val2; |
| 985 | |
| 986 | /* Those ones are used in supervisor mode only */ |
| 987 | /* machine state register */ |
| 988 | target_ulong msr; |
| 989 | /* temporary general purpose registers */ |
| 990 | target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
| 991 | |
| 992 | /* Floating point execution context */ |
| 993 | float_status fp_status; |
| 994 | /* floating point status and control register */ |
| 995 | target_ulong fpscr; |
| 996 | |
| 997 | /* Next instruction pointer */ |
| 998 | target_ulong nip; |
| 999 | |
| 1000 | /* High part of 128-bit helper return. */ |
| 1001 | uint64_t retxh; |
| 1002 | |
| 1003 | /* when a memory exception occurs, the access type is stored here */ |
| 1004 | int access_type; |
| 1005 | |
| 1006 | /* MMU context - only relevant for full system emulation */ |
| 1007 | #if !defined(CONFIG_USER_ONLY) |
| 1008 | #if defined(TARGET_PPC64) |
| 1009 | /* PowerPC 64 SLB area */ |
| 1010 | ppc_slb_t slb[MAX_SLB_ENTRIES]; |
| 1011 | /* tcg TLB needs flush (deferred slb inval instruction typically) */ |
| 1012 | #endif |
| 1013 | /* segment registers */ |
| 1014 | target_ulong sr[32]; |
| 1015 | /* BATs */ |
| 1016 | uint32_t nb_BATs; |
| 1017 | target_ulong DBAT[2][8]; |
| 1018 | target_ulong IBAT[2][8]; |
| 1019 | /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ |
| 1020 | int32_t nb_tlb; /* Total number of TLB */ |
| 1021 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
| 1022 | int nb_ways; /* Number of ways in the TLB set */ |
| 1023 | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 1024 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
| 1025 | int nb_pids; /* Number of available PID registers */ |
| 1026 | int tlb_type; /* Type of TLB we're dealing with */ |
| 1027 | ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ |
| 1028 | /* 403 dedicated access protection registers */ |
| 1029 | target_ulong pb[4]; |
| 1030 | bool tlb_dirty; /* Set to non-zero when modifying TLB */ |
| 1031 | bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ |
| 1032 | uint32_t tlb_need_flush; /* Delayed flush needed */ |
| 1033 | #define TLB_NEED_LOCAL_FLUSH 0x1 |
| 1034 | #define TLB_NEED_GLOBAL_FLUSH 0x2 |
| 1035 | #endif |
| 1036 | |
| 1037 | /* Other registers */ |
| 1038 | /* Special purpose registers */ |
| 1039 | target_ulong spr[1024]; |
| 1040 | ppc_spr_t spr_cb[1024]; |
| 1041 | /* Vector status and control register, minus VSCR_SAT. */ |
| 1042 | uint32_t vscr; |
| 1043 | /* VSX registers (including FP and AVR) */ |
| 1044 | ppc_vsr_t vsr[64] QEMU_ALIGNED(16); |
| 1045 | /* Non-zero if and only if VSCR_SAT should be set. */ |
| 1046 | ppc_vsr_t vscr_sat QEMU_ALIGNED(16); |
| 1047 | /* SPE registers */ |
| 1048 | uint64_t spe_acc; |
| 1049 | uint32_t spe_fscr; |
| 1050 | /* |
| 1051 | * SPE and Altivec can share a status since they will never be |
| 1052 | * used simultaneously |
| 1053 | */ |
| 1054 | float_status vec_status; |
| 1055 | |
| 1056 | /* Internal devices resources */ |
| 1057 | /* Time base and decrementer */ |
| 1058 | ppc_tb_t *tb_env; |
| 1059 | /* Device control registers */ |
| 1060 | ppc_dcr_t *dcr_env; |
| 1061 | |
| 1062 | int dcache_line_size; |
| 1063 | int icache_line_size; |
| 1064 | |
| 1065 | /* Those resources are used during exception processing */ |
| 1066 | /* CPU model definition */ |
| 1067 | target_ulong msr_mask; |
| 1068 | powerpc_mmu_t mmu_model; |
| 1069 | powerpc_excp_t excp_model; |
| 1070 | powerpc_input_t bus_model; |
| 1071 | int bfd_mach; |
| 1072 | uint32_t flags; |
| 1073 | uint64_t insns_flags; |
| 1074 | uint64_t insns_flags2; |
| 1075 | #if defined(TARGET_PPC64) |
| 1076 | ppc_slb_t vrma_slb; |
| 1077 | target_ulong rmls; |
| 1078 | #endif |
| 1079 | |
| 1080 | int error_code; |
| 1081 | uint32_t pending_interrupts; |
| 1082 | #if !defined(CONFIG_USER_ONLY) |
| 1083 | /* |
| 1084 | * This is the IRQ controller, which is implementation dependent |
| 1085 | * and only relevant when emulating a complete machine. |
| 1086 | */ |
| 1087 | uint32_t irq_input_state; |
| 1088 | void **irq_inputs; |
| 1089 | /* Exception vectors */ |
| 1090 | target_ulong excp_vectors[POWERPC_EXCP_NB]; |
| 1091 | target_ulong excp_prefix; |
| 1092 | target_ulong ivor_mask; |
| 1093 | target_ulong ivpr_mask; |
| 1094 | target_ulong hreset_vector; |
| 1095 | hwaddr mpic_iack; |
| 1096 | /* true when the external proxy facility mode is enabled */ |
| 1097 | bool mpic_proxy; |
| 1098 | /* |
| 1099 | * set when the processor has an HV mode, thus HV priv |
| 1100 | * instructions and SPRs are diallowed if MSR:HV is 0 |
| 1101 | */ |
| 1102 | bool has_hv_mode; |
| 1103 | |
| 1104 | /* |
| 1105 | * On P7/P8/P9, set when in PM state, we need to handle resume in |
| 1106 | * a special way (such as routing some resume causes to 0x100, ie, |
| 1107 | * sreset), so flag this here. |
| 1108 | */ |
| 1109 | bool resume_as_sreset; |
| 1110 | #endif |
| 1111 | |
| 1112 | /* Those resources are used only in QEMU core */ |
| 1113 | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
| 1114 | target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ |
| 1115 | int immu_idx; /* precomputed MMU index to speed up insn access */ |
| 1116 | int dmmu_idx; /* precomputed MMU index to speed up data accesses */ |
| 1117 | |
| 1118 | /* Power management */ |
| 1119 | int (*check_pow)(CPUPPCState *env); |
| 1120 | |
| 1121 | #if !defined(CONFIG_USER_ONLY) |
| 1122 | void *load_info; /* Holds boot loading state. */ |
| 1123 | #endif |
| 1124 | |
| 1125 | /* booke timers */ |
| 1126 | |
| 1127 | /* |
| 1128 | * Specifies bit locations of the Time Base used to signal a fixed |
| 1129 | * timer exception on a transition from 0 to 1. (watchdog or |
| 1130 | * fixed-interval timer) |
| 1131 | * |
| 1132 | * 0 selects the least significant bit. |
| 1133 | * 63 selects the most significant bit. |
| 1134 | */ |
| 1135 | uint8_t fit_period[4]; |
| 1136 | uint8_t wdt_period[4]; |
| 1137 | |
| 1138 | /* Transactional memory state */ |
| 1139 | target_ulong tm_gpr[32]; |
| 1140 | ppc_avr_t tm_vsr[64]; |
| 1141 | uint64_t tm_cr; |
| 1142 | uint64_t tm_lr; |
| 1143 | uint64_t tm_ctr; |
| 1144 | uint64_t tm_fpscr; |
| 1145 | uint64_t tm_amr; |
| 1146 | uint64_t tm_ppr; |
| 1147 | uint64_t tm_vrsave; |
| 1148 | uint32_t tm_vscr; |
| 1149 | uint64_t tm_dscr; |
| 1150 | uint64_t tm_tar; |
| 1151 | }; |
| 1152 | |
| 1153 | #define SET_FIT_PERIOD(a_, b_, c_, d_) \ |
| 1154 | do { \ |
| 1155 | env->fit_period[0] = (a_); \ |
| 1156 | env->fit_period[1] = (b_); \ |
| 1157 | env->fit_period[2] = (c_); \ |
| 1158 | env->fit_period[3] = (d_); \ |
| 1159 | } while (0) |
| 1160 | |
| 1161 | #define SET_WDT_PERIOD(a_, b_, c_, d_) \ |
| 1162 | do { \ |
| 1163 | env->wdt_period[0] = (a_); \ |
| 1164 | env->wdt_period[1] = (b_); \ |
| 1165 | env->wdt_period[2] = (c_); \ |
| 1166 | env->wdt_period[3] = (d_); \ |
| 1167 | } while (0) |
| 1168 | |
| 1169 | typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; |
| 1170 | typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; |
| 1171 | |
| 1172 | /** |
| 1173 | * PowerPCCPU: |
| 1174 | * @env: #CPUPPCState |
| 1175 | * @vcpu_id: vCPU identifier given to KVM |
| 1176 | * @compat_pvr: Current logical PVR, zero if in "raw" mode |
| 1177 | * |
| 1178 | * A PowerPC CPU. |
| 1179 | */ |
| 1180 | struct PowerPCCPU { |
| 1181 | /*< private >*/ |
| 1182 | CPUState parent_obj; |
| 1183 | /*< public >*/ |
| 1184 | |
| 1185 | CPUNegativeOffsetState neg; |
| 1186 | CPUPPCState env; |
| 1187 | |
| 1188 | int vcpu_id; |
| 1189 | uint32_t compat_pvr; |
| 1190 | PPCVirtualHypervisor *vhyp; |
| 1191 | void *machine_data; |
| 1192 | int32_t node_id; /* NUMA node this CPU belongs to */ |
| 1193 | PPCHash64Options *hash64_opts; |
| 1194 | |
| 1195 | /* Those resources are used only during code translation */ |
| 1196 | /* opcode handlers */ |
| 1197 | opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; |
| 1198 | |
| 1199 | /* Fields related to migration compatibility hacks */ |
| 1200 | bool pre_2_8_migration; |
| 1201 | target_ulong mig_msr_mask; |
| 1202 | uint64_t mig_insns_flags; |
| 1203 | uint64_t mig_insns_flags2; |
| 1204 | uint32_t mig_nb_BATs; |
| 1205 | bool pre_2_10_migration; |
| 1206 | bool pre_3_0_migration; |
| 1207 | int32_t mig_slb_nr; |
| 1208 | }; |
| 1209 | |
| 1210 | |
| 1211 | PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); |
| 1212 | PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); |
| 1213 | PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc); |
| 1214 | |
| 1215 | struct PPCVirtualHypervisor { |
| 1216 | Object parent; |
| 1217 | }; |
| 1218 | |
| 1219 | struct PPCVirtualHypervisorClass { |
| 1220 | InterfaceClass parent; |
| 1221 | void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); |
| 1222 | hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp); |
| 1223 | const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp, |
| 1224 | hwaddr ptex, int n); |
| 1225 | void (*unmap_hptes)(PPCVirtualHypervisor *vhyp, |
| 1226 | const ppc_hash_pte64_t *hptes, |
| 1227 | hwaddr ptex, int n); |
| 1228 | void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1); |
| 1229 | void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1); |
| 1230 | void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry); |
| 1231 | target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp); |
| 1232 | #ifndef CONFIG_USER_ONLY |
| 1233 | void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); |
| 1234 | void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); |
| 1235 | #endif |
| 1236 | }; |
| 1237 | |
| 1238 | #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor" |
| 1239 | #define PPC_VIRTUAL_HYPERVISOR(obj) \ |
| 1240 | OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR) |
| 1241 | #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \ |
| 1242 | OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \ |
| 1243 | TYPE_PPC_VIRTUAL_HYPERVISOR) |
| 1244 | #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \ |
| 1245 | OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \ |
| 1246 | TYPE_PPC_VIRTUAL_HYPERVISOR) |
| 1247 | |
| 1248 | void ppc_cpu_do_interrupt(CPUState *cpu); |
| 1249 | bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 1250 | void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 1251 | void ppc_cpu_dump_statistics(CPUState *cpu, int flags); |
| 1252 | hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
| 1253 | int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
| 1254 | int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); |
| 1255 | int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 1256 | int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); |
| 1257 | #ifndef CONFIG_USER_ONLY |
| 1258 | void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); |
| 1259 | const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); |
| 1260 | #endif |
| 1261 | int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
| 1262 | int cpuid, void *opaque); |
| 1263 | int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
| 1264 | int cpuid, void *opaque); |
| 1265 | #ifndef CONFIG_USER_ONLY |
| 1266 | void ppc_cpu_do_system_reset(CPUState *cs); |
| 1267 | extern const VMStateDescription vmstate_ppc_cpu; |
| 1268 | #endif |
| 1269 | |
| 1270 | /*****************************************************************************/ |
| 1271 | void ppc_translate_init(void); |
| 1272 | /* |
| 1273 | * you can call this signal handler from your SIGBUS and SIGSEGV |
| 1274 | * signal handlers to inform the virtual CPU of exceptions. non zero |
| 1275 | * is returned if the signal was handled by the virtual CPU. |
| 1276 | */ |
| 1277 | int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); |
| 1278 | bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 1279 | MMUAccessType access_type, int mmu_idx, |
| 1280 | bool probe, uintptr_t retaddr); |
| 1281 | |
| 1282 | #if !defined(CONFIG_USER_ONLY) |
| 1283 | void ppc_store_sdr1(CPUPPCState *env, target_ulong value); |
| 1284 | void ppc_store_ptcr(CPUPPCState *env, target_ulong value); |
| 1285 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 1286 | void ppc_store_msr(CPUPPCState *env, target_ulong value); |
| 1287 | |
| 1288 | void ppc_cpu_list(void); |
| 1289 | |
| 1290 | /* Time-base and decrementer management */ |
| 1291 | #ifndef NO_CPU_IO_DEFS |
| 1292 | uint64_t cpu_ppc_load_tbl(CPUPPCState *env); |
| 1293 | uint32_t cpu_ppc_load_tbu(CPUPPCState *env); |
| 1294 | void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value); |
| 1295 | void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value); |
| 1296 | uint64_t cpu_ppc_load_atbl(CPUPPCState *env); |
| 1297 | uint32_t cpu_ppc_load_atbu(CPUPPCState *env); |
| 1298 | void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value); |
| 1299 | void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value); |
| 1300 | bool ppc_decr_clear_on_delivery(CPUPPCState *env); |
| 1301 | target_ulong cpu_ppc_load_decr(CPUPPCState *env); |
| 1302 | void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); |
| 1303 | target_ulong cpu_ppc_load_hdecr(CPUPPCState *env); |
| 1304 | void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value); |
| 1305 | uint64_t cpu_ppc_load_purr(CPUPPCState *env); |
| 1306 | uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env); |
| 1307 | uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env); |
| 1308 | #if !defined(CONFIG_USER_ONLY) |
| 1309 | void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value); |
| 1310 | void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value); |
| 1311 | target_ulong load_40x_pit(CPUPPCState *env); |
| 1312 | void store_40x_pit(CPUPPCState *env, target_ulong val); |
| 1313 | void store_40x_dbcr0(CPUPPCState *env, uint32_t val); |
| 1314 | void store_40x_sler(CPUPPCState *env, uint32_t val); |
| 1315 | void store_booke_tcr(CPUPPCState *env, target_ulong val); |
| 1316 | void store_booke_tsr(CPUPPCState *env, target_ulong val); |
| 1317 | void ppc_tlb_invalidate_all(CPUPPCState *env); |
| 1318 | void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr); |
| 1319 | void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); |
| 1320 | #endif |
| 1321 | #endif |
| 1322 | |
| 1323 | void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); |
| 1324 | |
| 1325 | static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) |
| 1326 | { |
| 1327 | uint64_t gprv; |
| 1328 | |
| 1329 | gprv = env->gpr[gprn]; |
| 1330 | if (env->flags & POWERPC_FLAG_SPE) { |
| 1331 | /* |
| 1332 | * If the CPU implements the SPE extension, we have to get the |
| 1333 | * high bits of the GPR from the gprh storage area |
| 1334 | */ |
| 1335 | gprv &= 0xFFFFFFFFULL; |
| 1336 | gprv |= (uint64_t)env->gprh[gprn] << 32; |
| 1337 | } |
| 1338 | |
| 1339 | return gprv; |
| 1340 | } |
| 1341 | |
| 1342 | /* Device control registers */ |
| 1343 | int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); |
| 1344 | int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); |
| 1345 | |
| 1346 | #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU |
| 1347 | #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX |
| 1348 | #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU |
| 1349 | |
| 1350 | #define cpu_signal_handler cpu_ppc_signal_handler |
| 1351 | #define cpu_list ppc_cpu_list |
| 1352 | |
| 1353 | /* MMU modes definitions */ |
| 1354 | #define MMU_USER_IDX 0 |
| 1355 | static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) |
| 1356 | { |
| 1357 | return ifetch ? env->immu_idx : env->dmmu_idx; |
| 1358 | } |
| 1359 | |
| 1360 | /* Compatibility modes */ |
| 1361 | #if defined(TARGET_PPC64) |
| 1362 | bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, |
| 1363 | uint32_t min_compat_pvr, uint32_t max_compat_pvr); |
| 1364 | bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr, |
| 1365 | uint32_t min_compat_pvr, uint32_t max_compat_pvr); |
| 1366 | |
| 1367 | void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp); |
| 1368 | |
| 1369 | #if !defined(CONFIG_USER_ONLY) |
| 1370 | void ppc_set_compat_all(uint32_t compat_pvr, Error **errp); |
| 1371 | #endif |
| 1372 | int ppc_compat_max_vthreads(PowerPCCPU *cpu); |
| 1373 | void ppc_compat_add_property(Object *obj, const char *name, |
| 1374 | uint32_t *compat_pvr, const char *basedesc, |
| 1375 | Error **errp); |
| 1376 | #endif /* defined(TARGET_PPC64) */ |
| 1377 | |
| 1378 | typedef CPUPPCState CPUArchState; |
| 1379 | typedef PowerPCCPU ArchCPU; |
| 1380 | |
| 1381 | #include "exec/cpu-all.h" |
| 1382 | |
| 1383 | /*****************************************************************************/ |
| 1384 | /* CRF definitions */ |
| 1385 | #define CRF_LT_BIT 3 |
| 1386 | #define CRF_GT_BIT 2 |
| 1387 | #define CRF_EQ_BIT 1 |
| 1388 | #define CRF_SO_BIT 0 |
| 1389 | #define CRF_LT (1 << CRF_LT_BIT) |
| 1390 | #define CRF_GT (1 << CRF_GT_BIT) |
| 1391 | #define CRF_EQ (1 << CRF_EQ_BIT) |
| 1392 | #define CRF_SO (1 << CRF_SO_BIT) |
| 1393 | /* For SPE extensions */ |
| 1394 | #define CRF_CH (1 << CRF_LT_BIT) |
| 1395 | #define CRF_CL (1 << CRF_GT_BIT) |
| 1396 | #define CRF_CH_OR_CL (1 << CRF_EQ_BIT) |
| 1397 | #define CRF_CH_AND_CL (1 << CRF_SO_BIT) |
| 1398 | |
| 1399 | /* XER definitions */ |
| 1400 | #define XER_SO 31 |
| 1401 | #define XER_OV 30 |
| 1402 | #define XER_CA 29 |
| 1403 | #define XER_OV32 19 |
| 1404 | #define XER_CA32 18 |
| 1405 | #define XER_CMP 8 |
| 1406 | #define XER_BC 0 |
| 1407 | #define xer_so (env->so) |
| 1408 | #define xer_ov (env->ov) |
| 1409 | #define xer_ca (env->ca) |
| 1410 | #define xer_ov32 (env->ov) |
| 1411 | #define xer_ca32 (env->ca) |
| 1412 | #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) |
| 1413 | #define xer_bc ((env->xer >> XER_BC) & 0x7F) |
| 1414 | |
| 1415 | /* SPR definitions */ |
| 1416 | #define SPR_MQ (0x000) |
| 1417 | #define SPR_XER (0x001) |
| 1418 | #define SPR_601_VRTCU (0x004) |
| 1419 | #define SPR_601_VRTCL (0x005) |
| 1420 | #define SPR_601_UDECR (0x006) |
| 1421 | #define SPR_LR (0x008) |
| 1422 | #define SPR_CTR (0x009) |
| 1423 | #define SPR_UAMR (0x00D) |
| 1424 | #define SPR_DSCR (0x011) |
| 1425 | #define SPR_DSISR (0x012) |
| 1426 | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
| 1427 | #define SPR_601_RTCU (0x014) |
| 1428 | #define SPR_601_RTCL (0x015) |
| 1429 | #define SPR_DECR (0x016) |
| 1430 | #define SPR_SDR1 (0x019) |
| 1431 | #define SPR_SRR0 (0x01A) |
| 1432 | #define SPR_SRR1 (0x01B) |
| 1433 | #define SPR_CFAR (0x01C) |
| 1434 | #define SPR_AMR (0x01D) |
| 1435 | #define SPR_ACOP (0x01F) |
| 1436 | #define SPR_BOOKE_PID (0x030) |
| 1437 | #define SPR_BOOKS_PID (0x030) |
| 1438 | #define SPR_BOOKE_DECAR (0x036) |
| 1439 | #define SPR_BOOKE_CSRR0 (0x03A) |
| 1440 | #define SPR_BOOKE_CSRR1 (0x03B) |
| 1441 | #define SPR_BOOKE_DEAR (0x03D) |
| 1442 | #define SPR_IAMR (0x03D) |
| 1443 | #define SPR_BOOKE_ESR (0x03E) |
| 1444 | #define SPR_BOOKE_IVPR (0x03F) |
| 1445 | #define SPR_MPC_EIE (0x050) |
| 1446 | #define SPR_MPC_EID (0x051) |
| 1447 | #define SPR_MPC_NRI (0x052) |
| 1448 | #define SPR_TFHAR (0x080) |
| 1449 | #define SPR_TFIAR (0x081) |
| 1450 | #define SPR_TEXASR (0x082) |
| 1451 | #define SPR_TEXASRU (0x083) |
| 1452 | #define SPR_UCTRL (0x088) |
| 1453 | #define SPR_TIDR (0x090) |
| 1454 | #define SPR_MPC_CMPA (0x090) |
| 1455 | #define SPR_MPC_CMPB (0x091) |
| 1456 | #define SPR_MPC_CMPC (0x092) |
| 1457 | #define SPR_MPC_CMPD (0x093) |
| 1458 | #define SPR_MPC_ECR (0x094) |
| 1459 | #define SPR_MPC_DER (0x095) |
| 1460 | #define SPR_MPC_COUNTA (0x096) |
| 1461 | #define SPR_MPC_COUNTB (0x097) |
| 1462 | #define SPR_CTRL (0x098) |
| 1463 | #define SPR_MPC_CMPE (0x098) |
| 1464 | #define SPR_MPC_CMPF (0x099) |
| 1465 | #define SPR_FSCR (0x099) |
| 1466 | #define SPR_MPC_CMPG (0x09A) |
| 1467 | #define SPR_MPC_CMPH (0x09B) |
| 1468 | #define SPR_MPC_LCTRL1 (0x09C) |
| 1469 | #define SPR_MPC_LCTRL2 (0x09D) |
| 1470 | #define SPR_UAMOR (0x09D) |
| 1471 | #define SPR_MPC_ICTRL (0x09E) |
| 1472 | #define SPR_MPC_BAR (0x09F) |
| 1473 | #define SPR_PSPB (0x09F) |
| 1474 | #define SPR_DPDES (0x0B0) |
| 1475 | #define SPR_DAWR (0x0B4) |
| 1476 | #define SPR_RPR (0x0BA) |
| 1477 | #define SPR_CIABR (0x0BB) |
| 1478 | #define SPR_DAWRX (0x0BC) |
| 1479 | #define SPR_HFSCR (0x0BE) |
| 1480 | #define SPR_VRSAVE (0x100) |
| 1481 | #define SPR_USPRG0 (0x100) |
| 1482 | #define SPR_USPRG1 (0x101) |
| 1483 | #define SPR_USPRG2 (0x102) |
| 1484 | #define SPR_USPRG3 (0x103) |
| 1485 | #define SPR_USPRG4 (0x104) |
| 1486 | #define SPR_USPRG5 (0x105) |
| 1487 | #define SPR_USPRG6 (0x106) |
| 1488 | #define SPR_USPRG7 (0x107) |
| 1489 | #define SPR_VTBL (0x10C) |
| 1490 | #define SPR_VTBU (0x10D) |
| 1491 | #define SPR_SPRG0 (0x110) |
| 1492 | #define SPR_SPRG1 (0x111) |
| 1493 | #define SPR_SPRG2 (0x112) |
| 1494 | #define SPR_SPRG3 (0x113) |
| 1495 | #define SPR_SPRG4 (0x114) |
| 1496 | #define SPR_SCOMC (0x114) |
| 1497 | #define SPR_SPRG5 (0x115) |
| 1498 | #define SPR_SCOMD (0x115) |
| 1499 | #define SPR_SPRG6 (0x116) |
| 1500 | #define SPR_SPRG7 (0x117) |
| 1501 | #define SPR_ASR (0x118) |
| 1502 | #define SPR_EAR (0x11A) |
| 1503 | #define SPR_TBL (0x11C) |
| 1504 | #define SPR_TBU (0x11D) |
| 1505 | #define SPR_TBU40 (0x11E) |
| 1506 | #define SPR_SVR (0x11E) |
| 1507 | #define SPR_BOOKE_PIR (0x11E) |
| 1508 | #define SPR_PVR (0x11F) |
| 1509 | #define SPR_HSPRG0 (0x130) |
| 1510 | #define SPR_BOOKE_DBSR (0x130) |
| 1511 | #define SPR_HSPRG1 (0x131) |
| 1512 | #define SPR_HDSISR (0x132) |
| 1513 | #define SPR_HDAR (0x133) |
| 1514 | #define SPR_BOOKE_EPCR (0x133) |
| 1515 | #define SPR_SPURR (0x134) |
| 1516 | #define SPR_BOOKE_DBCR0 (0x134) |
| 1517 | #define SPR_IBCR (0x135) |
| 1518 | #define SPR_PURR (0x135) |
| 1519 | #define SPR_BOOKE_DBCR1 (0x135) |
| 1520 | #define SPR_DBCR (0x136) |
| 1521 | #define SPR_HDEC (0x136) |
| 1522 | #define SPR_BOOKE_DBCR2 (0x136) |
| 1523 | #define SPR_HIOR (0x137) |
| 1524 | #define SPR_MBAR (0x137) |
| 1525 | #define SPR_RMOR (0x138) |
| 1526 | #define SPR_BOOKE_IAC1 (0x138) |
| 1527 | #define SPR_HRMOR (0x139) |
| 1528 | #define SPR_BOOKE_IAC2 (0x139) |
| 1529 | #define SPR_HSRR0 (0x13A) |
| 1530 | #define SPR_BOOKE_IAC3 (0x13A) |
| 1531 | #define SPR_HSRR1 (0x13B) |
| 1532 | #define SPR_BOOKE_IAC4 (0x13B) |
| 1533 | #define SPR_BOOKE_DAC1 (0x13C) |
| 1534 | #define SPR_MMCRH (0x13C) |
| 1535 | #define SPR_DABR2 (0x13D) |
| 1536 | #define SPR_BOOKE_DAC2 (0x13D) |
| 1537 | #define SPR_TFMR (0x13D) |
| 1538 | #define SPR_BOOKE_DVC1 (0x13E) |
| 1539 | #define SPR_LPCR (0x13E) |
| 1540 | #define SPR_BOOKE_DVC2 (0x13F) |
| 1541 | #define SPR_LPIDR (0x13F) |
| 1542 | #define SPR_BOOKE_TSR (0x150) |
| 1543 | #define SPR_HMER (0x150) |
| 1544 | #define SPR_HMEER (0x151) |
| 1545 | #define SPR_PCR (0x152) |
| 1546 | #define SPR_BOOKE_LPIDR (0x152) |
| 1547 | #define SPR_BOOKE_TCR (0x154) |
| 1548 | #define SPR_BOOKE_TLB0PS (0x158) |
| 1549 | #define SPR_BOOKE_TLB1PS (0x159) |
| 1550 | #define SPR_BOOKE_TLB2PS (0x15A) |
| 1551 | #define SPR_BOOKE_TLB3PS (0x15B) |
| 1552 | #define SPR_AMOR (0x15D) |
| 1553 | #define SPR_BOOKE_MAS7_MAS3 (0x174) |
| 1554 | #define SPR_BOOKE_IVOR0 (0x190) |
| 1555 | #define SPR_BOOKE_IVOR1 (0x191) |
| 1556 | #define SPR_BOOKE_IVOR2 (0x192) |
| 1557 | #define SPR_BOOKE_IVOR3 (0x193) |
| 1558 | #define SPR_BOOKE_IVOR4 (0x194) |
| 1559 | #define SPR_BOOKE_IVOR5 (0x195) |
| 1560 | #define SPR_BOOKE_IVOR6 (0x196) |
| 1561 | #define SPR_BOOKE_IVOR7 (0x197) |
| 1562 | #define SPR_BOOKE_IVOR8 (0x198) |
| 1563 | #define SPR_BOOKE_IVOR9 (0x199) |
| 1564 | #define SPR_BOOKE_IVOR10 (0x19A) |
| 1565 | #define SPR_BOOKE_IVOR11 (0x19B) |
| 1566 | #define SPR_BOOKE_IVOR12 (0x19C) |
| 1567 | #define SPR_BOOKE_IVOR13 (0x19D) |
| 1568 | #define SPR_BOOKE_IVOR14 (0x19E) |
| 1569 | #define SPR_BOOKE_IVOR15 (0x19F) |
| 1570 | #define SPR_BOOKE_IVOR38 (0x1B0) |
| 1571 | #define SPR_BOOKE_IVOR39 (0x1B1) |
| 1572 | #define SPR_BOOKE_IVOR40 (0x1B2) |
| 1573 | #define SPR_BOOKE_IVOR41 (0x1B3) |
| 1574 | #define SPR_BOOKE_IVOR42 (0x1B4) |
| 1575 | #define SPR_BOOKE_GIVOR2 (0x1B8) |
| 1576 | #define SPR_BOOKE_GIVOR3 (0x1B9) |
| 1577 | #define SPR_BOOKE_GIVOR4 (0x1BA) |
| 1578 | #define SPR_BOOKE_GIVOR8 (0x1BB) |
| 1579 | #define SPR_BOOKE_GIVOR13 (0x1BC) |
| 1580 | #define SPR_BOOKE_GIVOR14 (0x1BD) |
| 1581 | #define SPR_TIR (0x1BE) |
| 1582 | #define SPR_PTCR (0x1D0) |
| 1583 | #define SPR_BOOKE_SPEFSCR (0x200) |
| 1584 | #define SPR_Exxx_BBEAR (0x201) |
| 1585 | #define SPR_Exxx_BBTAR (0x202) |
| 1586 | #define SPR_Exxx_L1CFG0 (0x203) |
| 1587 | #define SPR_Exxx_L1CFG1 (0x204) |
| 1588 | #define SPR_Exxx_NPIDR (0x205) |
| 1589 | #define SPR_ATBL (0x20E) |
| 1590 | #define SPR_ATBU (0x20F) |
| 1591 | #define SPR_IBAT0U (0x210) |
| 1592 | #define SPR_BOOKE_IVOR32 (0x210) |
| 1593 | #define SPR_RCPU_MI_GRA (0x210) |
| 1594 | #define SPR_IBAT0L (0x211) |
| 1595 | #define SPR_BOOKE_IVOR33 (0x211) |
| 1596 | #define SPR_IBAT1U (0x212) |
| 1597 | #define SPR_BOOKE_IVOR34 (0x212) |
| 1598 | #define SPR_IBAT1L (0x213) |
| 1599 | #define SPR_BOOKE_IVOR35 (0x213) |
| 1600 | #define SPR_IBAT2U (0x214) |
| 1601 | #define SPR_BOOKE_IVOR36 (0x214) |
| 1602 | #define SPR_IBAT2L (0x215) |
| 1603 | #define SPR_BOOKE_IVOR37 (0x215) |
| 1604 | #define SPR_IBAT3U (0x216) |
| 1605 | #define SPR_IBAT3L (0x217) |
| 1606 | #define SPR_DBAT0U (0x218) |
| 1607 | #define SPR_RCPU_L2U_GRA (0x218) |
| 1608 | #define SPR_DBAT0L (0x219) |
| 1609 | #define SPR_DBAT1U (0x21A) |
| 1610 | #define SPR_DBAT1L (0x21B) |
| 1611 | #define SPR_DBAT2U (0x21C) |
| 1612 | #define SPR_DBAT2L (0x21D) |
| 1613 | #define SPR_DBAT3U (0x21E) |
| 1614 | #define SPR_DBAT3L (0x21F) |
| 1615 | #define SPR_IBAT4U (0x230) |
| 1616 | #define SPR_RPCU_BBCMCR (0x230) |
| 1617 | #define SPR_MPC_IC_CST (0x230) |
| 1618 | #define SPR_Exxx_CTXCR (0x230) |
| 1619 | #define SPR_IBAT4L (0x231) |
| 1620 | #define SPR_MPC_IC_ADR (0x231) |
| 1621 | #define SPR_Exxx_DBCR3 (0x231) |
| 1622 | #define SPR_IBAT5U (0x232) |
| 1623 | #define SPR_MPC_IC_DAT (0x232) |
| 1624 | #define SPR_Exxx_DBCNT (0x232) |
| 1625 | #define SPR_IBAT5L (0x233) |
| 1626 | #define SPR_IBAT6U (0x234) |
| 1627 | #define SPR_IBAT6L (0x235) |
| 1628 | #define SPR_IBAT7U (0x236) |
| 1629 | #define SPR_IBAT7L (0x237) |
| 1630 | #define SPR_DBAT4U (0x238) |
| 1631 | #define SPR_RCPU_L2U_MCR (0x238) |
| 1632 | #define SPR_MPC_DC_CST (0x238) |
| 1633 | #define SPR_Exxx_ALTCTXCR (0x238) |
| 1634 | #define SPR_DBAT4L (0x239) |
| 1635 | #define SPR_MPC_DC_ADR (0x239) |
| 1636 | #define SPR_DBAT5U (0x23A) |
| 1637 | #define SPR_BOOKE_MCSRR0 (0x23A) |
| 1638 | #define SPR_MPC_DC_DAT (0x23A) |
| 1639 | #define SPR_DBAT5L (0x23B) |
| 1640 | #define SPR_BOOKE_MCSRR1 (0x23B) |
| 1641 | #define SPR_DBAT6U (0x23C) |
| 1642 | #define SPR_BOOKE_MCSR (0x23C) |
| 1643 | #define SPR_DBAT6L (0x23D) |
| 1644 | #define SPR_Exxx_MCAR (0x23D) |
| 1645 | #define SPR_DBAT7U (0x23E) |
| 1646 | #define SPR_BOOKE_DSRR0 (0x23E) |
| 1647 | #define SPR_DBAT7L (0x23F) |
| 1648 | #define SPR_BOOKE_DSRR1 (0x23F) |
| 1649 | #define SPR_BOOKE_SPRG8 (0x25C) |
| 1650 | #define SPR_BOOKE_SPRG9 (0x25D) |
| 1651 | #define SPR_BOOKE_MAS0 (0x270) |
| 1652 | #define SPR_BOOKE_MAS1 (0x271) |
| 1653 | #define SPR_BOOKE_MAS2 (0x272) |
| 1654 | #define SPR_BOOKE_MAS3 (0x273) |
| 1655 | #define SPR_BOOKE_MAS4 (0x274) |
| 1656 | #define SPR_BOOKE_MAS5 (0x275) |
| 1657 | #define SPR_BOOKE_MAS6 (0x276) |
| 1658 | #define SPR_BOOKE_PID1 (0x279) |
| 1659 | #define SPR_BOOKE_PID2 (0x27A) |
| 1660 | #define SPR_MPC_DPDR (0x280) |
| 1661 | #define SPR_MPC_IMMR (0x288) |
| 1662 | #define SPR_BOOKE_TLB0CFG (0x2B0) |
| 1663 | #define SPR_BOOKE_TLB1CFG (0x2B1) |
| 1664 | #define SPR_BOOKE_TLB2CFG (0x2B2) |
| 1665 | #define SPR_BOOKE_TLB3CFG (0x2B3) |
| 1666 | #define SPR_BOOKE_EPR (0x2BE) |
| 1667 | #define SPR_PERF0 (0x300) |
| 1668 | #define SPR_RCPU_MI_RBA0 (0x300) |
| 1669 | #define SPR_MPC_MI_CTR (0x300) |
| 1670 | #define SPR_POWER_USIER (0x300) |
| 1671 | #define SPR_PERF1 (0x301) |
| 1672 | #define SPR_RCPU_MI_RBA1 (0x301) |
| 1673 | #define SPR_POWER_UMMCR2 (0x301) |
| 1674 | #define SPR_PERF2 (0x302) |
| 1675 | #define SPR_RCPU_MI_RBA2 (0x302) |
| 1676 | #define SPR_MPC_MI_AP (0x302) |
| 1677 | #define SPR_POWER_UMMCRA (0x302) |
| 1678 | #define SPR_PERF3 (0x303) |
| 1679 | #define SPR_RCPU_MI_RBA3 (0x303) |
| 1680 | #define SPR_MPC_MI_EPN (0x303) |
| 1681 | #define SPR_POWER_UPMC1 (0x303) |
| 1682 | #define SPR_PERF4 (0x304) |
| 1683 | #define SPR_POWER_UPMC2 (0x304) |
| 1684 | #define SPR_PERF5 (0x305) |
| 1685 | #define SPR_MPC_MI_TWC (0x305) |
| 1686 | #define SPR_POWER_UPMC3 (0x305) |
| 1687 | #define SPR_PERF6 (0x306) |
| 1688 | #define SPR_MPC_MI_RPN (0x306) |
| 1689 | #define SPR_POWER_UPMC4 (0x306) |
| 1690 | #define SPR_PERF7 (0x307) |
| 1691 | #define SPR_POWER_UPMC5 (0x307) |
| 1692 | #define SPR_PERF8 (0x308) |
| 1693 | #define SPR_RCPU_L2U_RBA0 (0x308) |
| 1694 | #define SPR_MPC_MD_CTR (0x308) |
| 1695 | #define SPR_POWER_UPMC6 (0x308) |
| 1696 | #define SPR_PERF9 (0x309) |
| 1697 | #define SPR_RCPU_L2U_RBA1 (0x309) |
| 1698 | #define SPR_MPC_MD_CASID (0x309) |
| 1699 | #define SPR_970_UPMC7 (0X309) |
| 1700 | #define SPR_PERFA (0x30A) |
| 1701 | #define SPR_RCPU_L2U_RBA2 (0x30A) |
| 1702 | #define SPR_MPC_MD_AP (0x30A) |
| 1703 | #define SPR_970_UPMC8 (0X30A) |
| 1704 | #define SPR_PERFB (0x30B) |
| 1705 | #define SPR_RCPU_L2U_RBA3 (0x30B) |
| 1706 | #define SPR_MPC_MD_EPN (0x30B) |
| 1707 | #define SPR_POWER_UMMCR0 (0X30B) |
| 1708 | #define SPR_PERFC (0x30C) |
| 1709 | #define SPR_MPC_MD_TWB (0x30C) |
| 1710 | #define SPR_POWER_USIAR (0X30C) |
| 1711 | #define SPR_PERFD (0x30D) |
| 1712 | #define SPR_MPC_MD_TWC (0x30D) |
| 1713 | #define SPR_POWER_USDAR (0X30D) |
| 1714 | #define SPR_PERFE (0x30E) |
| 1715 | #define SPR_MPC_MD_RPN (0x30E) |
| 1716 | #define SPR_POWER_UMMCR1 (0X30E) |
| 1717 | #define SPR_PERFF (0x30F) |
| 1718 | #define SPR_MPC_MD_TW (0x30F) |
| 1719 | #define SPR_UPERF0 (0x310) |
| 1720 | #define SPR_POWER_SIER (0x310) |
| 1721 | #define SPR_UPERF1 (0x311) |
| 1722 | #define SPR_POWER_MMCR2 (0x311) |
| 1723 | #define SPR_UPERF2 (0x312) |
| 1724 | #define SPR_POWER_MMCRA (0X312) |
| 1725 | #define SPR_UPERF3 (0x313) |
| 1726 | #define SPR_POWER_PMC1 (0X313) |
| 1727 | #define SPR_UPERF4 (0x314) |
| 1728 | #define SPR_POWER_PMC2 (0X314) |
| 1729 | #define SPR_UPERF5 (0x315) |
| 1730 | #define SPR_POWER_PMC3 (0X315) |
| 1731 | #define SPR_UPERF6 (0x316) |
| 1732 | #define SPR_POWER_PMC4 (0X316) |
| 1733 | #define SPR_UPERF7 (0x317) |
| 1734 | #define SPR_POWER_PMC5 (0X317) |
| 1735 | #define SPR_UPERF8 (0x318) |
| 1736 | #define SPR_POWER_PMC6 (0X318) |
| 1737 | #define SPR_UPERF9 (0x319) |
| 1738 | #define SPR_970_PMC7 (0X319) |
| 1739 | #define SPR_UPERFA (0x31A) |
| 1740 | #define SPR_970_PMC8 (0X31A) |
| 1741 | #define SPR_UPERFB (0x31B) |
| 1742 | #define SPR_POWER_MMCR0 (0X31B) |
| 1743 | #define SPR_UPERFC (0x31C) |
| 1744 | #define SPR_POWER_SIAR (0X31C) |
| 1745 | #define SPR_UPERFD (0x31D) |
| 1746 | #define SPR_POWER_SDAR (0X31D) |
| 1747 | #define SPR_UPERFE (0x31E) |
| 1748 | #define SPR_POWER_MMCR1 (0X31E) |
| 1749 | #define SPR_UPERFF (0x31F) |
| 1750 | #define SPR_RCPU_MI_RA0 (0x320) |
| 1751 | #define SPR_MPC_MI_DBCAM (0x320) |
| 1752 | #define SPR_BESCRS (0x320) |
| 1753 | #define SPR_RCPU_MI_RA1 (0x321) |
| 1754 | #define SPR_MPC_MI_DBRAM0 (0x321) |
| 1755 | #define SPR_BESCRSU (0x321) |
| 1756 | #define SPR_RCPU_MI_RA2 (0x322) |
| 1757 | #define SPR_MPC_MI_DBRAM1 (0x322) |
| 1758 | #define SPR_BESCRR (0x322) |
| 1759 | #define SPR_RCPU_MI_RA3 (0x323) |
| 1760 | #define SPR_BESCRRU (0x323) |
| 1761 | #define SPR_EBBHR (0x324) |
| 1762 | #define SPR_EBBRR (0x325) |
| 1763 | #define SPR_BESCR (0x326) |
| 1764 | #define SPR_RCPU_L2U_RA0 (0x328) |
| 1765 | #define SPR_MPC_MD_DBCAM (0x328) |
| 1766 | #define SPR_RCPU_L2U_RA1 (0x329) |
| 1767 | #define SPR_MPC_MD_DBRAM0 (0x329) |
| 1768 | #define SPR_RCPU_L2U_RA2 (0x32A) |
| 1769 | #define SPR_MPC_MD_DBRAM1 (0x32A) |
| 1770 | #define SPR_RCPU_L2U_RA3 (0x32B) |
| 1771 | #define SPR_TAR (0x32F) |
| 1772 | #define SPR_IC (0x350) |
| 1773 | #define SPR_VTB (0x351) |
| 1774 | #define SPR_MMCRC (0x353) |
| 1775 | #define SPR_PSSCR (0x357) |
| 1776 | #define SPR_440_INV0 (0x370) |
| 1777 | #define SPR_440_INV1 (0x371) |
| 1778 | #define SPR_440_INV2 (0x372) |
| 1779 | #define SPR_440_INV3 (0x373) |
| 1780 | #define SPR_440_ITV0 (0x374) |
| 1781 | #define SPR_440_ITV1 (0x375) |
| 1782 | #define SPR_440_ITV2 (0x376) |
| 1783 | #define SPR_440_ITV3 (0x377) |
| 1784 | #define SPR_440_CCR1 (0x378) |
| 1785 | #define SPR_TACR (0x378) |
| 1786 | #define SPR_TCSCR (0x379) |
| 1787 | #define SPR_CSIGR (0x37a) |
| 1788 | #define SPR_DCRIPR (0x37B) |
| 1789 | #define SPR_POWER_SPMC1 (0x37C) |
| 1790 | #define SPR_POWER_SPMC2 (0x37D) |
| 1791 | #define SPR_POWER_MMCRS (0x37E) |
| 1792 | #define SPR_WORT (0x37F) |
| 1793 | #define SPR_PPR (0x380) |
| 1794 | #define SPR_750_GQR0 (0x390) |
| 1795 | #define SPR_440_DNV0 (0x390) |
| 1796 | #define SPR_750_GQR1 (0x391) |
| 1797 | #define SPR_440_DNV1 (0x391) |
| 1798 | #define SPR_750_GQR2 (0x392) |
| 1799 | #define SPR_440_DNV2 (0x392) |
| 1800 | #define SPR_750_GQR3 (0x393) |
| 1801 | #define SPR_440_DNV3 (0x393) |
| 1802 | #define SPR_750_GQR4 (0x394) |
| 1803 | #define SPR_440_DTV0 (0x394) |
| 1804 | #define SPR_750_GQR5 (0x395) |
| 1805 | #define SPR_440_DTV1 (0x395) |
| 1806 | #define SPR_750_GQR6 (0x396) |
| 1807 | #define SPR_440_DTV2 (0x396) |
| 1808 | #define SPR_750_GQR7 (0x397) |
| 1809 | #define SPR_440_DTV3 (0x397) |
| 1810 | #define SPR_750_THRM4 (0x398) |
| 1811 | #define SPR_750CL_HID2 (0x398) |
| 1812 | #define SPR_440_DVLIM (0x398) |
| 1813 | #define SPR_750_WPAR (0x399) |
| 1814 | #define SPR_440_IVLIM (0x399) |
| 1815 | #define SPR_TSCR (0x399) |
| 1816 | #define SPR_750_DMAU (0x39A) |
| 1817 | #define SPR_750_DMAL (0x39B) |
| 1818 | #define SPR_440_RSTCFG (0x39B) |
| 1819 | #define SPR_BOOKE_DCDBTRL (0x39C) |
| 1820 | #define SPR_BOOKE_DCDBTRH (0x39D) |
| 1821 | #define SPR_BOOKE_ICDBTRL (0x39E) |
| 1822 | #define SPR_BOOKE_ICDBTRH (0x39F) |
| 1823 | #define SPR_74XX_UMMCR2 (0x3A0) |
| 1824 | #define SPR_7XX_UPMC5 (0x3A1) |
| 1825 | #define SPR_7XX_UPMC6 (0x3A2) |
| 1826 | #define SPR_UBAMR (0x3A7) |
| 1827 | #define SPR_7XX_UMMCR0 (0x3A8) |
| 1828 | #define SPR_7XX_UPMC1 (0x3A9) |
| 1829 | #define SPR_7XX_UPMC2 (0x3AA) |
| 1830 | #define SPR_7XX_USIAR (0x3AB) |
| 1831 | #define SPR_7XX_UMMCR1 (0x3AC) |
| 1832 | #define SPR_7XX_UPMC3 (0x3AD) |
| 1833 | #define SPR_7XX_UPMC4 (0x3AE) |
| 1834 | #define SPR_USDA (0x3AF) |
| 1835 | #define SPR_40x_ZPR (0x3B0) |
| 1836 | #define SPR_BOOKE_MAS7 (0x3B0) |
| 1837 | #define SPR_74XX_MMCR2 (0x3B0) |
| 1838 | #define SPR_7XX_PMC5 (0x3B1) |
| 1839 | #define SPR_40x_PID (0x3B1) |
| 1840 | #define SPR_7XX_PMC6 (0x3B2) |
| 1841 | #define SPR_440_MMUCR (0x3B2) |
| 1842 | #define SPR_4xx_CCR0 (0x3B3) |
| 1843 | #define SPR_BOOKE_EPLC (0x3B3) |
| 1844 | #define SPR_405_IAC3 (0x3B4) |
| 1845 | #define SPR_BOOKE_EPSC (0x3B4) |
| 1846 | #define SPR_405_IAC4 (0x3B5) |
| 1847 | #define SPR_405_DVC1 (0x3B6) |
| 1848 | #define SPR_405_DVC2 (0x3B7) |
| 1849 | #define SPR_BAMR (0x3B7) |
| 1850 | #define SPR_7XX_MMCR0 (0x3B8) |
| 1851 | #define SPR_7XX_PMC1 (0x3B9) |
| 1852 | #define SPR_40x_SGR (0x3B9) |
| 1853 | #define SPR_7XX_PMC2 (0x3BA) |
| 1854 | #define SPR_40x_DCWR (0x3BA) |
| 1855 | #define SPR_7XX_SIAR (0x3BB) |
| 1856 | #define SPR_405_SLER (0x3BB) |
| 1857 | #define SPR_7XX_MMCR1 (0x3BC) |
| 1858 | #define SPR_405_SU0R (0x3BC) |
| 1859 | #define SPR_401_SKR (0x3BC) |
| 1860 | #define SPR_7XX_PMC3 (0x3BD) |
| 1861 | #define SPR_405_DBCR1 (0x3BD) |
| 1862 | #define SPR_7XX_PMC4 (0x3BE) |
| 1863 | #define SPR_SDA (0x3BF) |
| 1864 | #define SPR_403_VTBL (0x3CC) |
| 1865 | #define SPR_403_VTBU (0x3CD) |
| 1866 | #define SPR_DMISS (0x3D0) |
| 1867 | #define SPR_DCMP (0x3D1) |
| 1868 | #define SPR_HASH1 (0x3D2) |
| 1869 | #define SPR_HASH2 (0x3D3) |
| 1870 | #define SPR_BOOKE_ICDBDR (0x3D3) |
| 1871 | #define SPR_TLBMISS (0x3D4) |
| 1872 | #define SPR_IMISS (0x3D4) |
| 1873 | #define SPR_40x_ESR (0x3D4) |
| 1874 | #define SPR_PTEHI (0x3D5) |
| 1875 | #define SPR_ICMP (0x3D5) |
| 1876 | #define SPR_40x_DEAR (0x3D5) |
| 1877 | #define SPR_PTELO (0x3D6) |
| 1878 | #define SPR_RPA (0x3D6) |
| 1879 | #define SPR_40x_EVPR (0x3D6) |
| 1880 | #define SPR_L3PM (0x3D7) |
| 1881 | #define SPR_403_CDBCR (0x3D7) |
| 1882 | #define SPR_L3ITCR0 (0x3D8) |
| 1883 | #define SPR_TCR (0x3D8) |
| 1884 | #define SPR_40x_TSR (0x3D8) |
| 1885 | #define SPR_IBR (0x3DA) |
| 1886 | #define SPR_40x_TCR (0x3DA) |
| 1887 | #define SPR_ESASRR (0x3DB) |
| 1888 | #define SPR_40x_PIT (0x3DB) |
| 1889 | #define SPR_403_TBL (0x3DC) |
| 1890 | #define SPR_403_TBU (0x3DD) |
| 1891 | #define SPR_SEBR (0x3DE) |
| 1892 | #define SPR_40x_SRR2 (0x3DE) |
| 1893 | #define SPR_SER (0x3DF) |
| 1894 | #define SPR_40x_SRR3 (0x3DF) |
| 1895 | #define SPR_L3OHCR (0x3E8) |
| 1896 | #define SPR_L3ITCR1 (0x3E9) |
| 1897 | #define SPR_L3ITCR2 (0x3EA) |
| 1898 | #define SPR_L3ITCR3 (0x3EB) |
| 1899 | #define SPR_HID0 (0x3F0) |
| 1900 | #define SPR_40x_DBSR (0x3F0) |
| 1901 | #define SPR_HID1 (0x3F1) |
| 1902 | #define SPR_IABR (0x3F2) |
| 1903 | #define SPR_40x_DBCR0 (0x3F2) |
| 1904 | #define SPR_601_HID2 (0x3F2) |
| 1905 | #define SPR_Exxx_L1CSR0 (0x3F2) |
| 1906 | #define SPR_ICTRL (0x3F3) |
| 1907 | #define SPR_HID2 (0x3F3) |
| 1908 | #define SPR_750CL_HID4 (0x3F3) |
| 1909 | #define SPR_Exxx_L1CSR1 (0x3F3) |
| 1910 | #define SPR_440_DBDR (0x3F3) |
| 1911 | #define SPR_LDSTDB (0x3F4) |
| 1912 | #define SPR_750_TDCL (0x3F4) |
| 1913 | #define SPR_40x_IAC1 (0x3F4) |
| 1914 | #define SPR_MMUCSR0 (0x3F4) |
| 1915 | #define SPR_970_HID4 (0x3F4) |
| 1916 | #define SPR_DABR (0x3F5) |
| 1917 | #define DABR_MASK (~(target_ulong)0x7) |
| 1918 | #define SPR_Exxx_BUCSR (0x3F5) |
| 1919 | #define SPR_40x_IAC2 (0x3F5) |
| 1920 | #define SPR_601_HID5 (0x3F5) |
| 1921 | #define SPR_40x_DAC1 (0x3F6) |
| 1922 | #define SPR_MSSCR0 (0x3F6) |
| 1923 | #define SPR_970_HID5 (0x3F6) |
| 1924 | #define SPR_MSSSR0 (0x3F7) |
| 1925 | #define SPR_MSSCR1 (0x3F7) |
| 1926 | #define SPR_DABRX (0x3F7) |
| 1927 | #define SPR_40x_DAC2 (0x3F7) |
| 1928 | #define SPR_MMUCFG (0x3F7) |
| 1929 | #define SPR_LDSTCR (0x3F8) |
| 1930 | #define SPR_L2PMCR (0x3F8) |
| 1931 | #define SPR_750FX_HID2 (0x3F8) |
| 1932 | #define SPR_Exxx_L1FINV0 (0x3F8) |
| 1933 | #define SPR_L2CR (0x3F9) |
| 1934 | #define SPR_L3CR (0x3FA) |
| 1935 | #define SPR_750_TDCH (0x3FA) |
| 1936 | #define SPR_IABR2 (0x3FA) |
| 1937 | #define SPR_40x_DCCR (0x3FA) |
| 1938 | #define SPR_ICTC (0x3FB) |
| 1939 | #define SPR_40x_ICCR (0x3FB) |
| 1940 | #define SPR_THRM1 (0x3FC) |
| 1941 | #define SPR_403_PBL1 (0x3FC) |
| 1942 | #define SPR_SP (0x3FD) |
| 1943 | #define SPR_THRM2 (0x3FD) |
| 1944 | #define SPR_403_PBU1 (0x3FD) |
| 1945 | #define SPR_604_HID13 (0x3FD) |
| 1946 | #define SPR_LT (0x3FE) |
| 1947 | #define SPR_THRM3 (0x3FE) |
| 1948 | #define SPR_RCPU_FPECR (0x3FE) |
| 1949 | #define SPR_403_PBL2 (0x3FE) |
| 1950 | #define SPR_PIR (0x3FF) |
| 1951 | #define SPR_403_PBU2 (0x3FF) |
| 1952 | #define SPR_601_HID15 (0x3FF) |
| 1953 | #define SPR_604_HID15 (0x3FF) |
| 1954 | #define SPR_E500_SVR (0x3FF) |
| 1955 | |
| 1956 | /* Disable MAS Interrupt Updates for Hypervisor */ |
| 1957 | #define EPCR_DMIUH (1 << 22) |
| 1958 | /* Disable Guest TLB Management Instructions */ |
| 1959 | #define EPCR_DGTMI (1 << 23) |
| 1960 | /* Guest Interrupt Computation Mode */ |
| 1961 | #define EPCR_GICM (1 << 24) |
| 1962 | /* Interrupt Computation Mode */ |
| 1963 | #define EPCR_ICM (1 << 25) |
| 1964 | /* Disable Embedded Hypervisor Debug */ |
| 1965 | #define EPCR_DUVD (1 << 26) |
| 1966 | /* Instruction Storage Interrupt Directed to Guest State */ |
| 1967 | #define EPCR_ISIGS (1 << 27) |
| 1968 | /* Data Storage Interrupt Directed to Guest State */ |
| 1969 | #define EPCR_DSIGS (1 << 28) |
| 1970 | /* Instruction TLB Error Interrupt Directed to Guest State */ |
| 1971 | #define EPCR_ITLBGS (1 << 29) |
| 1972 | /* Data TLB Error Interrupt Directed to Guest State */ |
| 1973 | #define EPCR_DTLBGS (1 << 30) |
| 1974 | /* External Input Interrupt Directed to Guest State */ |
| 1975 | #define EPCR_EXTGS (1 << 31) |
| 1976 | |
| 1977 | #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ |
| 1978 | #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ |
| 1979 | #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ |
| 1980 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
| 1981 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
| 1982 | |
| 1983 | #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ |
| 1984 | #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ |
| 1985 | #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ |
| 1986 | #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ |
| 1987 | #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ |
| 1988 | |
| 1989 | /* HID0 bits */ |
| 1990 | #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ |
| 1991 | #define HID0_DOZE (1 << 23) /* pre-2.06 */ |
| 1992 | #define HID0_NAP (1 << 22) /* pre-2.06 */ |
| 1993 | #define HID0_HILE PPC_BIT(19) /* POWER8 */ |
| 1994 | #define HID0_POWER9_HILE PPC_BIT(4) |
| 1995 | |
| 1996 | /*****************************************************************************/ |
| 1997 | /* PowerPC Instructions types definitions */ |
| 1998 | enum { |
| 1999 | PPC_NONE = 0x0000000000000000ULL, |
| 2000 | /* PowerPC base instructions set */ |
| 2001 | PPC_INSNS_BASE = 0x0000000000000001ULL, |
| 2002 | /* integer operations instructions */ |
| 2003 | #define PPC_INTEGER PPC_INSNS_BASE |
| 2004 | /* flow control instructions */ |
| 2005 | #define PPC_FLOW PPC_INSNS_BASE |
| 2006 | /* virtual memory instructions */ |
| 2007 | #define PPC_MEM PPC_INSNS_BASE |
| 2008 | /* ld/st with reservation instructions */ |
| 2009 | #define PPC_RES PPC_INSNS_BASE |
| 2010 | /* spr/msr access instructions */ |
| 2011 | #define PPC_MISC PPC_INSNS_BASE |
| 2012 | /* Deprecated instruction sets */ |
| 2013 | /* Original POWER instruction set */ |
| 2014 | PPC_POWER = 0x0000000000000002ULL, |
| 2015 | /* POWER2 instruction set extension */ |
| 2016 | PPC_POWER2 = 0x0000000000000004ULL, |
| 2017 | /* Power RTC support */ |
| 2018 | PPC_POWER_RTC = 0x0000000000000008ULL, |
| 2019 | /* Power-to-PowerPC bridge (601) */ |
| 2020 | PPC_POWER_BR = 0x0000000000000010ULL, |
| 2021 | /* 64 bits PowerPC instruction set */ |
| 2022 | PPC_64B = 0x0000000000000020ULL, |
| 2023 | /* New 64 bits extensions (PowerPC 2.0x) */ |
| 2024 | PPC_64BX = 0x0000000000000040ULL, |
| 2025 | /* 64 bits hypervisor extensions */ |
| 2026 | PPC_64H = 0x0000000000000080ULL, |
| 2027 | /* New wait instruction (PowerPC 2.0x) */ |
| 2028 | PPC_WAIT = 0x0000000000000100ULL, |
| 2029 | /* Time base mftb instruction */ |
| 2030 | PPC_MFTB = 0x0000000000000200ULL, |
| 2031 | |
| 2032 | /* Fixed-point unit extensions */ |
| 2033 | /* PowerPC 602 specific */ |
| 2034 | PPC_602_SPEC = 0x0000000000000400ULL, |
| 2035 | /* isel instruction */ |
| 2036 | PPC_ISEL = 0x0000000000000800ULL, |
| 2037 | /* popcntb instruction */ |
| 2038 | PPC_POPCNTB = 0x0000000000001000ULL, |
| 2039 | /* string load / store */ |
| 2040 | PPC_STRING = 0x0000000000002000ULL, |
| 2041 | /* real mode cache inhibited load / store */ |
| 2042 | PPC_CILDST = 0x0000000000004000ULL, |
| 2043 | |
| 2044 | /* Floating-point unit extensions */ |
| 2045 | /* Optional floating point instructions */ |
| 2046 | PPC_FLOAT = 0x0000000000010000ULL, |
| 2047 | /* New floating-point extensions (PowerPC 2.0x) */ |
| 2048 | PPC_FLOAT_EXT = 0x0000000000020000ULL, |
| 2049 | PPC_FLOAT_FSQRT = 0x0000000000040000ULL, |
| 2050 | PPC_FLOAT_FRES = 0x0000000000080000ULL, |
| 2051 | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, |
| 2052 | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, |
| 2053 | PPC_FLOAT_FSEL = 0x0000000000400000ULL, |
| 2054 | PPC_FLOAT_STFIWX = 0x0000000000800000ULL, |
| 2055 | |
| 2056 | /* Vector/SIMD extensions */ |
| 2057 | /* Altivec support */ |
| 2058 | PPC_ALTIVEC = 0x0000000001000000ULL, |
| 2059 | /* PowerPC 2.03 SPE extension */ |
| 2060 | PPC_SPE = 0x0000000002000000ULL, |
| 2061 | /* PowerPC 2.03 SPE single-precision floating-point extension */ |
| 2062 | PPC_SPE_SINGLE = 0x0000000004000000ULL, |
| 2063 | /* PowerPC 2.03 SPE double-precision floating-point extension */ |
| 2064 | PPC_SPE_DOUBLE = 0x0000000008000000ULL, |
| 2065 | |
| 2066 | /* Optional memory control instructions */ |
| 2067 | PPC_MEM_TLBIA = 0x0000000010000000ULL, |
| 2068 | PPC_MEM_TLBIE = 0x0000000020000000ULL, |
| 2069 | PPC_MEM_TLBSYNC = 0x0000000040000000ULL, |
| 2070 | /* sync instruction */ |
| 2071 | PPC_MEM_SYNC = 0x0000000080000000ULL, |
| 2072 | /* eieio instruction */ |
| 2073 | PPC_MEM_EIEIO = 0x0000000100000000ULL, |
| 2074 | |
| 2075 | /* Cache control instructions */ |
| 2076 | PPC_CACHE = 0x0000000200000000ULL, |
| 2077 | /* icbi instruction */ |
| 2078 | PPC_CACHE_ICBI = 0x0000000400000000ULL, |
| 2079 | /* dcbz instruction */ |
| 2080 | PPC_CACHE_DCBZ = 0x0000000800000000ULL, |
| 2081 | /* dcba instruction */ |
| 2082 | PPC_CACHE_DCBA = 0x0000002000000000ULL, |
| 2083 | /* Freescale cache locking instructions */ |
| 2084 | PPC_CACHE_LOCK = 0x0000004000000000ULL, |
| 2085 | |
| 2086 | /* MMU related extensions */ |
| 2087 | /* external control instructions */ |
| 2088 | PPC_EXTERN = 0x0000010000000000ULL, |
| 2089 | /* segment register access instructions */ |
| 2090 | PPC_SEGMENT = 0x0000020000000000ULL, |
| 2091 | /* PowerPC 6xx TLB management instructions */ |
| 2092 | PPC_6xx_TLB = 0x0000040000000000ULL, |
| 2093 | /* PowerPC 74xx TLB management instructions */ |
| 2094 | PPC_74xx_TLB = 0x0000080000000000ULL, |
| 2095 | /* PowerPC 40x TLB management instructions */ |
| 2096 | PPC_40x_TLB = 0x0000100000000000ULL, |
| 2097 | /* segment register access instructions for PowerPC 64 "bridge" */ |
| 2098 | PPC_SEGMENT_64B = 0x0000200000000000ULL, |
| 2099 | /* SLB management */ |
| 2100 | PPC_SLBI = 0x0000400000000000ULL, |
| 2101 | |
| 2102 | /* Embedded PowerPC dedicated instructions */ |
| 2103 | PPC_WRTEE = 0x0001000000000000ULL, |
| 2104 | /* PowerPC 40x exception model */ |
| 2105 | PPC_40x_EXCP = 0x0002000000000000ULL, |
| 2106 | /* PowerPC 405 Mac instructions */ |
| 2107 | PPC_405_MAC = 0x0004000000000000ULL, |
| 2108 | /* PowerPC 440 specific instructions */ |
| 2109 | PPC_440_SPEC = 0x0008000000000000ULL, |
| 2110 | /* BookE (embedded) PowerPC specification */ |
| 2111 | PPC_BOOKE = 0x0010000000000000ULL, |
| 2112 | /* mfapidi instruction */ |
| 2113 | PPC_MFAPIDI = 0x0020000000000000ULL, |
| 2114 | /* tlbiva instruction */ |
| 2115 | PPC_TLBIVA = 0x0040000000000000ULL, |
| 2116 | /* tlbivax instruction */ |
| 2117 | PPC_TLBIVAX = 0x0080000000000000ULL, |
| 2118 | /* PowerPC 4xx dedicated instructions */ |
| 2119 | PPC_4xx_COMMON = 0x0100000000000000ULL, |
| 2120 | /* PowerPC 40x ibct instructions */ |
| 2121 | PPC_40x_ICBT = 0x0200000000000000ULL, |
| 2122 | /* rfmci is not implemented in all BookE PowerPC */ |
| 2123 | PPC_RFMCI = 0x0400000000000000ULL, |
| 2124 | /* rfdi instruction */ |
| 2125 | PPC_RFDI = 0x0800000000000000ULL, |
| 2126 | /* DCR accesses */ |
| 2127 | PPC_DCR = 0x1000000000000000ULL, |
| 2128 | /* DCR extended accesse */ |
| 2129 | PPC_DCRX = 0x2000000000000000ULL, |
| 2130 | /* user-mode DCR access, implemented in PowerPC 460 */ |
| 2131 | PPC_DCRUX = 0x4000000000000000ULL, |
| 2132 | /* popcntw and popcntd instructions */ |
| 2133 | PPC_POPCNTWD = 0x8000000000000000ULL, |
| 2134 | |
| 2135 | #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \ |
| 2136 | | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \ |
| 2137 | | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ |
| 2138 | | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \ |
| 2139 | | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ |
| 2140 | | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ |
| 2141 | | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ |
| 2142 | | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \ |
| 2143 | | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \ |
| 2144 | | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \ |
| 2145 | | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ |
| 2146 | | PPC_MEM_SYNC | PPC_MEM_EIEIO \ |
| 2147 | | PPC_CACHE | PPC_CACHE_ICBI \ |
| 2148 | | PPC_CACHE_DCBZ \ |
| 2149 | | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ |
| 2150 | | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ |
| 2151 | | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ |
| 2152 | | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ |
| 2153 | | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ |
| 2154 | | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ |
| 2155 | | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ |
| 2156 | | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ |
| 2157 | | PPC_POPCNTWD | PPC_CILDST) |
| 2158 | |
| 2159 | /* extended type values */ |
| 2160 | |
| 2161 | /* BookE 2.06 PowerPC specification */ |
| 2162 | PPC2_BOOKE206 = 0x0000000000000001ULL, |
| 2163 | /* VSX (extensions to Altivec / VMX) */ |
| 2164 | PPC2_VSX = 0x0000000000000002ULL, |
| 2165 | /* Decimal Floating Point (DFP) */ |
| 2166 | PPC2_DFP = 0x0000000000000004ULL, |
| 2167 | /* Embedded.Processor Control */ |
| 2168 | PPC2_PRCNTL = 0x0000000000000008ULL, |
| 2169 | /* Byte-reversed, indexed, double-word load and store */ |
| 2170 | PPC2_DBRX = 0x0000000000000010ULL, |
| 2171 | /* Book I 2.05 PowerPC specification */ |
| 2172 | PPC2_ISA205 = 0x0000000000000020ULL, |
| 2173 | /* VSX additions in ISA 2.07 */ |
| 2174 | PPC2_VSX207 = 0x0000000000000040ULL, |
| 2175 | /* ISA 2.06B bpermd */ |
| 2176 | PPC2_PERM_ISA206 = 0x0000000000000080ULL, |
| 2177 | /* ISA 2.06B divide extended variants */ |
| 2178 | PPC2_DIVE_ISA206 = 0x0000000000000100ULL, |
| 2179 | /* ISA 2.06B larx/stcx. instructions */ |
| 2180 | PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, |
| 2181 | /* ISA 2.06B floating point integer conversion */ |
| 2182 | PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, |
| 2183 | /* ISA 2.06B floating point test instructions */ |
| 2184 | PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, |
| 2185 | /* ISA 2.07 bctar instruction */ |
| 2186 | PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, |
| 2187 | /* ISA 2.07 load/store quadword */ |
| 2188 | PPC2_LSQ_ISA207 = 0x0000000000002000ULL, |
| 2189 | /* ISA 2.07 Altivec */ |
| 2190 | PPC2_ALTIVEC_207 = 0x0000000000004000ULL, |
| 2191 | /* PowerISA 2.07 Book3s specification */ |
| 2192 | PPC2_ISA207S = 0x0000000000008000ULL, |
| 2193 | /* Double precision floating point conversion for signed integer 64 */ |
| 2194 | PPC2_FP_CVT_S64 = 0x0000000000010000ULL, |
| 2195 | /* Transactional Memory (ISA 2.07, Book II) */ |
| 2196 | PPC2_TM = 0x0000000000020000ULL, |
| 2197 | /* Server PM instructgions (ISA 2.06, Book III) */ |
| 2198 | PPC2_PM_ISA206 = 0x0000000000040000ULL, |
| 2199 | /* POWER ISA 3.0 */ |
| 2200 | PPC2_ISA300 = 0x0000000000080000ULL, |
| 2201 | |
| 2202 | #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ |
| 2203 | PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ |
| 2204 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ |
| 2205 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ |
| 2206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ |
| 2207 | PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ |
| 2208 | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ |
| 2209 | PPC2_ISA300) |
| 2210 | }; |
| 2211 | |
| 2212 | /*****************************************************************************/ |
| 2213 | /* |
| 2214 | * Memory access type : |
| 2215 | * may be needed for precise access rights control and precise exceptions. |
| 2216 | */ |
| 2217 | enum { |
| 2218 | /* 1 bit to define user level / supervisor access */ |
| 2219 | ACCESS_USER = 0x00, |
| 2220 | ACCESS_SUPER = 0x01, |
| 2221 | /* Type of instruction that generated the access */ |
| 2222 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 2223 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 2224 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 2225 | ACCESS_RES = 0x40, /* load/store with reservation */ |
| 2226 | ACCESS_EXT = 0x50, /* external access */ |
| 2227 | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 2228 | }; |
| 2229 | |
| 2230 | /* |
| 2231 | * Hardware interrupt sources: |
| 2232 | * all those exception can be raised simulteaneously |
| 2233 | */ |
| 2234 | /* Input pins definitions */ |
| 2235 | enum { |
| 2236 | /* 6xx bus input pins */ |
| 2237 | PPC6xx_INPUT_HRESET = 0, |
| 2238 | PPC6xx_INPUT_SRESET = 1, |
| 2239 | PPC6xx_INPUT_CKSTP_IN = 2, |
| 2240 | PPC6xx_INPUT_MCP = 3, |
| 2241 | PPC6xx_INPUT_SMI = 4, |
| 2242 | PPC6xx_INPUT_INT = 5, |
| 2243 | PPC6xx_INPUT_TBEN = 6, |
| 2244 | PPC6xx_INPUT_WAKEUP = 7, |
| 2245 | PPC6xx_INPUT_NB, |
| 2246 | }; |
| 2247 | |
| 2248 | enum { |
| 2249 | /* Embedded PowerPC input pins */ |
| 2250 | PPCBookE_INPUT_HRESET = 0, |
| 2251 | PPCBookE_INPUT_SRESET = 1, |
| 2252 | PPCBookE_INPUT_CKSTP_IN = 2, |
| 2253 | PPCBookE_INPUT_MCP = 3, |
| 2254 | PPCBookE_INPUT_SMI = 4, |
| 2255 | PPCBookE_INPUT_INT = 5, |
| 2256 | PPCBookE_INPUT_CINT = 6, |
| 2257 | PPCBookE_INPUT_NB, |
| 2258 | }; |
| 2259 | |
| 2260 | enum { |
| 2261 | /* PowerPC E500 input pins */ |
| 2262 | PPCE500_INPUT_RESET_CORE = 0, |
| 2263 | PPCE500_INPUT_MCK = 1, |
| 2264 | PPCE500_INPUT_CINT = 3, |
| 2265 | PPCE500_INPUT_INT = 4, |
| 2266 | PPCE500_INPUT_DEBUG = 6, |
| 2267 | PPCE500_INPUT_NB, |
| 2268 | }; |
| 2269 | |
| 2270 | enum { |
| 2271 | /* PowerPC 40x input pins */ |
| 2272 | PPC40x_INPUT_RESET_CORE = 0, |
| 2273 | PPC40x_INPUT_RESET_CHIP = 1, |
| 2274 | PPC40x_INPUT_RESET_SYS = 2, |
| 2275 | PPC40x_INPUT_CINT = 3, |
| 2276 | PPC40x_INPUT_INT = 4, |
| 2277 | PPC40x_INPUT_HALT = 5, |
| 2278 | PPC40x_INPUT_DEBUG = 6, |
| 2279 | PPC40x_INPUT_NB, |
| 2280 | }; |
| 2281 | |
| 2282 | enum { |
| 2283 | /* RCPU input pins */ |
| 2284 | PPCRCPU_INPUT_PORESET = 0, |
| 2285 | PPCRCPU_INPUT_HRESET = 1, |
| 2286 | PPCRCPU_INPUT_SRESET = 2, |
| 2287 | PPCRCPU_INPUT_IRQ0 = 3, |
| 2288 | PPCRCPU_INPUT_IRQ1 = 4, |
| 2289 | PPCRCPU_INPUT_IRQ2 = 5, |
| 2290 | PPCRCPU_INPUT_IRQ3 = 6, |
| 2291 | PPCRCPU_INPUT_IRQ4 = 7, |
| 2292 | PPCRCPU_INPUT_IRQ5 = 8, |
| 2293 | PPCRCPU_INPUT_IRQ6 = 9, |
| 2294 | PPCRCPU_INPUT_IRQ7 = 10, |
| 2295 | PPCRCPU_INPUT_NB, |
| 2296 | }; |
| 2297 | |
| 2298 | #if defined(TARGET_PPC64) |
| 2299 | enum { |
| 2300 | /* PowerPC 970 input pins */ |
| 2301 | PPC970_INPUT_HRESET = 0, |
| 2302 | PPC970_INPUT_SRESET = 1, |
| 2303 | PPC970_INPUT_CKSTP = 2, |
| 2304 | PPC970_INPUT_TBEN = 3, |
| 2305 | PPC970_INPUT_MCP = 4, |
| 2306 | PPC970_INPUT_INT = 5, |
| 2307 | PPC970_INPUT_THINT = 6, |
| 2308 | PPC970_INPUT_NB, |
| 2309 | }; |
| 2310 | |
| 2311 | enum { |
| 2312 | /* POWER7 input pins */ |
| 2313 | POWER7_INPUT_INT = 0, |
| 2314 | /* |
| 2315 | * POWER7 probably has other inputs, but we don't care about them |
| 2316 | * for any existing machine. We can wire these up when we need |
| 2317 | * them |
| 2318 | */ |
| 2319 | POWER7_INPUT_NB, |
| 2320 | }; |
| 2321 | |
| 2322 | enum { |
| 2323 | /* POWER9 input pins */ |
| 2324 | POWER9_INPUT_INT = 0, |
| 2325 | POWER9_INPUT_HINT = 1, |
| 2326 | POWER9_INPUT_NB, |
| 2327 | }; |
| 2328 | #endif |
| 2329 | |
| 2330 | /* Hardware exceptions definitions */ |
| 2331 | enum { |
| 2332 | /* External hardware exception sources */ |
| 2333 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
| 2334 | PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ |
| 2335 | PPC_INTERRUPT_MCK, /* Machine check exception */ |
| 2336 | PPC_INTERRUPT_EXT, /* External interrupt */ |
| 2337 | PPC_INTERRUPT_SMI, /* System management interrupt */ |
| 2338 | PPC_INTERRUPT_CEXT, /* Critical external interrupt */ |
| 2339 | PPC_INTERRUPT_DEBUG, /* External debug exception */ |
| 2340 | PPC_INTERRUPT_THERM, /* Thermal exception */ |
| 2341 | /* Internal hardware exception sources */ |
| 2342 | PPC_INTERRUPT_DECR, /* Decrementer exception */ |
| 2343 | PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ |
| 2344 | PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ |
| 2345 | PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ |
| 2346 | PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ |
| 2347 | PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ |
| 2348 | PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ |
| 2349 | PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ |
| 2350 | PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */ |
| 2351 | PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ |
| 2352 | PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */ |
| 2353 | }; |
| 2354 | |
| 2355 | /* Processor Compatibility mask (PCR) */ |
| 2356 | enum { |
| 2357 | PCR_COMPAT_2_05 = PPC_BIT(62), |
| 2358 | PCR_COMPAT_2_06 = PPC_BIT(61), |
| 2359 | PCR_COMPAT_2_07 = PPC_BIT(60), |
| 2360 | PCR_COMPAT_3_00 = PPC_BIT(59), |
| 2361 | PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */ |
| 2362 | PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */ |
| 2363 | PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */ |
| 2364 | }; |
| 2365 | |
| 2366 | /* HMER/HMEER */ |
| 2367 | enum { |
| 2368 | HMER_MALFUNCTION_ALERT = PPC_BIT(0), |
| 2369 | HMER_PROC_RECV_DONE = PPC_BIT(2), |
| 2370 | HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3), |
| 2371 | HMER_TFAC_ERROR = PPC_BIT(4), |
| 2372 | HMER_TFMR_PARITY_ERROR = PPC_BIT(5), |
| 2373 | HMER_XSCOM_FAIL = PPC_BIT(8), |
| 2374 | HMER_XSCOM_DONE = PPC_BIT(9), |
| 2375 | HMER_PROC_RECV_AGAIN = PPC_BIT(11), |
| 2376 | HMER_WARN_RISE = PPC_BIT(14), |
| 2377 | HMER_WARN_FALL = PPC_BIT(15), |
| 2378 | HMER_SCOM_FIR_HMI = PPC_BIT(16), |
| 2379 | HMER_TRIG_FIR_HMI = PPC_BIT(17), |
| 2380 | HMER_HYP_RESOURCE_ERR = PPC_BIT(20), |
| 2381 | HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23), |
| 2382 | }; |
| 2383 | |
| 2384 | /* Alternate Interrupt Location (AIL) */ |
| 2385 | enum { |
| 2386 | AIL_NONE = 0, |
| 2387 | AIL_RESERVED = 1, |
| 2388 | AIL_0001_8000 = 2, |
| 2389 | AIL_C000_0000_0000_4000 = 3, |
| 2390 | }; |
| 2391 | |
| 2392 | /*****************************************************************************/ |
| 2393 | |
| 2394 | #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) |
| 2395 | target_ulong cpu_read_xer(CPUPPCState *env); |
| 2396 | void cpu_write_xer(CPUPPCState *env, target_ulong xer); |
| 2397 | |
| 2398 | /* |
| 2399 | * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer, |
| 2400 | * have PPC_SEGMENT_64B. |
| 2401 | */ |
| 2402 | #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) |
| 2403 | |
| 2404 | static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, |
| 2405 | target_ulong *cs_base, uint32_t *flags) |
| 2406 | { |
| 2407 | *pc = env->nip; |
| 2408 | *cs_base = 0; |
| 2409 | *flags = env->hflags; |
| 2410 | } |
| 2411 | |
| 2412 | void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); |
| 2413 | void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, |
| 2414 | uintptr_t raddr); |
| 2415 | void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception, |
| 2416 | uint32_t error_code); |
| 2417 | void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception, |
| 2418 | uint32_t error_code, uintptr_t raddr); |
| 2419 | |
| 2420 | #if !defined(CONFIG_USER_ONLY) |
| 2421 | static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) |
| 2422 | { |
| 2423 | uintptr_t tlbml = (uintptr_t)tlbm; |
| 2424 | uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; |
| 2425 | |
| 2426 | return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); |
| 2427 | } |
| 2428 | |
| 2429 | static inline int booke206_tlb_size(CPUPPCState *env, int tlbn) |
| 2430 | { |
| 2431 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2432 | int r = tlbncfg & TLBnCFG_N_ENTRY; |
| 2433 | return r; |
| 2434 | } |
| 2435 | |
| 2436 | static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn) |
| 2437 | { |
| 2438 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2439 | int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT; |
| 2440 | return r; |
| 2441 | } |
| 2442 | |
| 2443 | static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) |
| 2444 | { |
| 2445 | int id = booke206_tlbm_id(env, tlbm); |
| 2446 | int end = 0; |
| 2447 | int i; |
| 2448 | |
| 2449 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
| 2450 | end += booke206_tlb_size(env, i); |
| 2451 | if (id < end) { |
| 2452 | return i; |
| 2453 | } |
| 2454 | } |
| 2455 | |
| 2456 | cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id); |
| 2457 | return 0; |
| 2458 | } |
| 2459 | |
| 2460 | static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb) |
| 2461 | { |
| 2462 | int tlbn = booke206_tlbm_to_tlbn(env, tlb); |
| 2463 | int tlbid = booke206_tlbm_id(env, tlb); |
| 2464 | return tlbid & (booke206_tlb_ways(env, tlbn) - 1); |
| 2465 | } |
| 2466 | |
| 2467 | static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn, |
| 2468 | target_ulong ea, int way) |
| 2469 | { |
| 2470 | int r; |
| 2471 | uint32_t ways = booke206_tlb_ways(env, tlbn); |
| 2472 | int ways_bits = ctz32(ways); |
| 2473 | int tlb_bits = ctz32(booke206_tlb_size(env, tlbn)); |
| 2474 | int i; |
| 2475 | |
| 2476 | way &= ways - 1; |
| 2477 | ea >>= MAS2_EPN_SHIFT; |
| 2478 | ea &= (1 << (tlb_bits - ways_bits)) - 1; |
| 2479 | r = (ea << ways_bits) | way; |
| 2480 | |
| 2481 | if (r >= booke206_tlb_size(env, tlbn)) { |
| 2482 | return NULL; |
| 2483 | } |
| 2484 | |
| 2485 | /* bump up to tlbn index */ |
| 2486 | for (i = 0; i < tlbn; i++) { |
| 2487 | r += booke206_tlb_size(env, i); |
| 2488 | } |
| 2489 | |
| 2490 | return &env->tlb.tlbm[r]; |
| 2491 | } |
| 2492 | |
| 2493 | /* returns bitmap of supported page sizes for a given TLB */ |
| 2494 | static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) |
| 2495 | { |
| 2496 | uint32_t ret = 0; |
| 2497 | |
| 2498 | if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { |
| 2499 | /* MAV2 */ |
| 2500 | ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; |
| 2501 | } else { |
| 2502 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2503 | uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; |
| 2504 | uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; |
| 2505 | int i; |
| 2506 | for (i = min; i <= max; i++) { |
| 2507 | ret |= (1 << (i << 1)); |
| 2508 | } |
| 2509 | } |
| 2510 | |
| 2511 | return ret; |
| 2512 | } |
| 2513 | |
| 2514 | static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn, |
| 2515 | ppcmas_tlb_t *tlb) |
| 2516 | { |
| 2517 | uint8_t i; |
| 2518 | int32_t tsize = -1; |
| 2519 | |
| 2520 | for (i = 0; i < 32; i++) { |
| 2521 | if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { |
| 2522 | if (tsize == -1) { |
| 2523 | tsize = i; |
| 2524 | } else { |
| 2525 | return; |
| 2526 | } |
| 2527 | } |
| 2528 | } |
| 2529 | |
| 2530 | /* TLBnPS unimplemented? Odd.. */ |
| 2531 | assert(tsize != -1); |
| 2532 | tlb->mas1 &= ~MAS1_TSIZE_MASK; |
| 2533 | tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; |
| 2534 | } |
| 2535 | |
| 2536 | #endif |
| 2537 | |
| 2538 | static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) |
| 2539 | { |
| 2540 | if (env->mmu_model == POWERPC_MMU_BOOKE206) { |
| 2541 | return msr & (1ULL << MSR_CM); |
| 2542 | } |
| 2543 | |
| 2544 | return msr & (1ULL << MSR_SF); |
| 2545 | } |
| 2546 | |
| 2547 | /** |
| 2548 | * Check whether register rx is in the range between start and |
| 2549 | * start + nregs (as needed by the LSWX and LSWI instructions) |
| 2550 | */ |
| 2551 | static inline bool lsw_reg_in_range(int start, int nregs, int rx) |
| 2552 | { |
| 2553 | return (start + nregs <= 32 && rx >= start && rx < start + nregs) || |
| 2554 | (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); |
| 2555 | } |
| 2556 | |
| 2557 | /* Accessors for FP, VMX and VSX registers */ |
| 2558 | #if defined(HOST_WORDS_BIGENDIAN) |
| 2559 | #define VsrB(i) u8[i] |
| 2560 | #define VsrSB(i) s8[i] |
| 2561 | #define VsrH(i) u16[i] |
| 2562 | #define VsrSH(i) s16[i] |
| 2563 | #define VsrW(i) u32[i] |
| 2564 | #define VsrSW(i) s32[i] |
| 2565 | #define VsrD(i) u64[i] |
| 2566 | #define VsrSD(i) s64[i] |
| 2567 | #else |
| 2568 | #define VsrB(i) u8[15 - (i)] |
| 2569 | #define VsrSB(i) s8[15 - (i)] |
| 2570 | #define VsrH(i) u16[7 - (i)] |
| 2571 | #define VsrSH(i) s16[7 - (i)] |
| 2572 | #define VsrW(i) u32[3 - (i)] |
| 2573 | #define VsrSW(i) s32[3 - (i)] |
| 2574 | #define VsrD(i) u64[1 - (i)] |
| 2575 | #define VsrSD(i) s64[1 - (i)] |
| 2576 | #endif |
| 2577 | |
| 2578 | static inline int vsr64_offset(int i, bool high) |
| 2579 | { |
| 2580 | return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1)); |
| 2581 | } |
| 2582 | |
| 2583 | static inline int vsr_full_offset(int i) |
| 2584 | { |
| 2585 | return offsetof(CPUPPCState, vsr[i].u64[0]); |
| 2586 | } |
| 2587 | |
| 2588 | static inline int fpr_offset(int i) |
| 2589 | { |
| 2590 | return vsr64_offset(i, true); |
| 2591 | } |
| 2592 | |
| 2593 | static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) |
| 2594 | { |
| 2595 | return (uint64_t *)((uintptr_t)env + fpr_offset(i)); |
| 2596 | } |
| 2597 | |
| 2598 | static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) |
| 2599 | { |
| 2600 | return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false)); |
| 2601 | } |
| 2602 | |
| 2603 | static inline long avr64_offset(int i, bool high) |
| 2604 | { |
| 2605 | return vsr64_offset(i + 32, high); |
| 2606 | } |
| 2607 | |
| 2608 | static inline int avr_full_offset(int i) |
| 2609 | { |
| 2610 | return vsr_full_offset(i + 32); |
| 2611 | } |
| 2612 | |
| 2613 | static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) |
| 2614 | { |
| 2615 | return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i)); |
| 2616 | } |
| 2617 | |
| 2618 | void dump_mmu(CPUPPCState *env); |
| 2619 | |
| 2620 | void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); |
| 2621 | #endif /* PPC_CPU_H */ |
| 2622 |
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