1/* RISC-V ISA constants */
2
3#ifndef TARGET_RISCV_CPU_BITS_H
4#define TARGET_RISCV_CPU_BITS_H
5
6#define get_field(reg, mask) (((reg) & \
7 (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
8#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
9 (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
10 (target_ulong)(mask)))
11
12/* Floating point round mode */
13#define FSR_RD_SHIFT 5
14#define FSR_RD (0x7 << FSR_RD_SHIFT)
15
16/* Floating point accrued exception flags */
17#define FPEXC_NX 0x01
18#define FPEXC_UF 0x02
19#define FPEXC_OF 0x04
20#define FPEXC_DZ 0x08
21#define FPEXC_NV 0x10
22
23/* Floating point status register bits */
24#define FSR_AEXC_SHIFT 0
25#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
26#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
27#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
28#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
29#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
30#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
31
32/* Control and Status Registers */
33
34/* User Trap Setup */
35#define CSR_USTATUS 0x000
36#define CSR_UIE 0x004
37#define CSR_UTVEC 0x005
38
39/* User Trap Handling */
40#define CSR_USCRATCH 0x040
41#define CSR_UEPC 0x041
42#define CSR_UCAUSE 0x042
43#define CSR_UTVAL 0x043
44#define CSR_UIP 0x044
45
46/* User Floating-Point CSRs */
47#define CSR_FFLAGS 0x001
48#define CSR_FRM 0x002
49#define CSR_FCSR 0x003
50
51/* User Timers and Counters */
52#define CSR_CYCLE 0xc00
53#define CSR_TIME 0xc01
54#define CSR_INSTRET 0xc02
55#define CSR_HPMCOUNTER3 0xc03
56#define CSR_HPMCOUNTER4 0xc04
57#define CSR_HPMCOUNTER5 0xc05
58#define CSR_HPMCOUNTER6 0xc06
59#define CSR_HPMCOUNTER7 0xc07
60#define CSR_HPMCOUNTER8 0xc08
61#define CSR_HPMCOUNTER9 0xc09
62#define CSR_HPMCOUNTER10 0xc0a
63#define CSR_HPMCOUNTER11 0xc0b
64#define CSR_HPMCOUNTER12 0xc0c
65#define CSR_HPMCOUNTER13 0xc0d
66#define CSR_HPMCOUNTER14 0xc0e
67#define CSR_HPMCOUNTER15 0xc0f
68#define CSR_HPMCOUNTER16 0xc10
69#define CSR_HPMCOUNTER17 0xc11
70#define CSR_HPMCOUNTER18 0xc12
71#define CSR_HPMCOUNTER19 0xc13
72#define CSR_HPMCOUNTER20 0xc14
73#define CSR_HPMCOUNTER21 0xc15
74#define CSR_HPMCOUNTER22 0xc16
75#define CSR_HPMCOUNTER23 0xc17
76#define CSR_HPMCOUNTER24 0xc18
77#define CSR_HPMCOUNTER25 0xc19
78#define CSR_HPMCOUNTER26 0xc1a
79#define CSR_HPMCOUNTER27 0xc1b
80#define CSR_HPMCOUNTER28 0xc1c
81#define CSR_HPMCOUNTER29 0xc1d
82#define CSR_HPMCOUNTER30 0xc1e
83#define CSR_HPMCOUNTER31 0xc1f
84#define CSR_CYCLEH 0xc80
85#define CSR_TIMEH 0xc81
86#define CSR_INSTRETH 0xc82
87#define CSR_HPMCOUNTER3H 0xc83
88#define CSR_HPMCOUNTER4H 0xc84
89#define CSR_HPMCOUNTER5H 0xc85
90#define CSR_HPMCOUNTER6H 0xc86
91#define CSR_HPMCOUNTER7H 0xc87
92#define CSR_HPMCOUNTER8H 0xc88
93#define CSR_HPMCOUNTER9H 0xc89
94#define CSR_HPMCOUNTER10H 0xc8a
95#define CSR_HPMCOUNTER11H 0xc8b
96#define CSR_HPMCOUNTER12H 0xc8c
97#define CSR_HPMCOUNTER13H 0xc8d
98#define CSR_HPMCOUNTER14H 0xc8e
99#define CSR_HPMCOUNTER15H 0xc8f
100#define CSR_HPMCOUNTER16H 0xc90
101#define CSR_HPMCOUNTER17H 0xc91
102#define CSR_HPMCOUNTER18H 0xc92
103#define CSR_HPMCOUNTER19H 0xc93
104#define CSR_HPMCOUNTER20H 0xc94
105#define CSR_HPMCOUNTER21H 0xc95
106#define CSR_HPMCOUNTER22H 0xc96
107#define CSR_HPMCOUNTER23H 0xc97
108#define CSR_HPMCOUNTER24H 0xc98
109#define CSR_HPMCOUNTER25H 0xc99
110#define CSR_HPMCOUNTER26H 0xc9a
111#define CSR_HPMCOUNTER27H 0xc9b
112#define CSR_HPMCOUNTER28H 0xc9c
113#define CSR_HPMCOUNTER29H 0xc9d
114#define CSR_HPMCOUNTER30H 0xc9e
115#define CSR_HPMCOUNTER31H 0xc9f
116
117/* Machine Timers and Counters */
118#define CSR_MCYCLE 0xb00
119#define CSR_MINSTRET 0xb02
120#define CSR_MCYCLEH 0xb80
121#define CSR_MINSTRETH 0xb82
122
123/* Machine Information Registers */
124#define CSR_MVENDORID 0xf11
125#define CSR_MARCHID 0xf12
126#define CSR_MIMPID 0xf13
127#define CSR_MHARTID 0xf14
128
129/* Machine Trap Setup */
130#define CSR_MSTATUS 0x300
131#define CSR_MISA 0x301
132#define CSR_MEDELEG 0x302
133#define CSR_MIDELEG 0x303
134#define CSR_MIE 0x304
135#define CSR_MTVEC 0x305
136#define CSR_MCOUNTEREN 0x306
137
138/* Legacy Counter Setup (priv v1.9.1) */
139/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
140#define CSR_MUCOUNTEREN 0x320
141#define CSR_MSCOUNTEREN 0x321
142#define CSR_MHCOUNTEREN 0x322
143
144/* Machine Trap Handling */
145#define CSR_MSCRATCH 0x340
146#define CSR_MEPC 0x341
147#define CSR_MCAUSE 0x342
148#define CSR_MTVAL 0x343
149#define CSR_MIP 0x344
150
151/* Legacy Machine Trap Handling (priv v1.9.1) */
152#define CSR_MBADADDR 0x343
153
154/* Supervisor Trap Setup */
155#define CSR_SSTATUS 0x100
156#define CSR_SEDELEG 0x102
157#define CSR_SIDELEG 0x103
158#define CSR_SIE 0x104
159#define CSR_STVEC 0x105
160#define CSR_SCOUNTEREN 0x106
161
162/* Supervisor Trap Handling */
163#define CSR_SSCRATCH 0x140
164#define CSR_SEPC 0x141
165#define CSR_SCAUSE 0x142
166#define CSR_STVAL 0x143
167#define CSR_SIP 0x144
168
169/* Legacy Supervisor Trap Handling (priv v1.9.1) */
170#define CSR_SBADADDR 0x143
171
172/* Supervisor Protection and Translation */
173#define CSR_SPTBR 0x180
174#define CSR_SATP 0x180
175
176/* Physical Memory Protection */
177#define CSR_PMPCFG0 0x3a0
178#define CSR_PMPCFG1 0x3a1
179#define CSR_PMPCFG2 0x3a2
180#define CSR_PMPCFG3 0x3a3
181#define CSR_PMPADDR0 0x3b0
182#define CSR_PMPADDR1 0x3b1
183#define CSR_PMPADDR2 0x3b2
184#define CSR_PMPADDR3 0x3b3
185#define CSR_PMPADDR4 0x3b4
186#define CSR_PMPADDR5 0x3b5
187#define CSR_PMPADDR6 0x3b6
188#define CSR_PMPADDR7 0x3b7
189#define CSR_PMPADDR8 0x3b8
190#define CSR_PMPADDR9 0x3b9
191#define CSR_PMPADDR10 0x3ba
192#define CSR_PMPADDR11 0x3bb
193#define CSR_PMPADDR12 0x3bc
194#define CSR_PMPADDR13 0x3bd
195#define CSR_PMPADDR14 0x3be
196#define CSR_PMPADDR15 0x3bf
197
198/* Debug/Trace Registers (shared with Debug Mode) */
199#define CSR_TSELECT 0x7a0
200#define CSR_TDATA1 0x7a1
201#define CSR_TDATA2 0x7a2
202#define CSR_TDATA3 0x7a3
203
204/* Debug Mode Registers */
205#define CSR_DCSR 0x7b0
206#define CSR_DPC 0x7b1
207#define CSR_DSCRATCH 0x7b2
208
209/* Hpervisor CSRs */
210#define CSR_HSTATUS 0xa00
211#define CSR_HEDELEG 0xa02
212#define CSR_HIDELEG 0xa03
213#define CSR_HGATP 0xa80
214
215#if defined(TARGET_RISCV32)
216#define HGATP_MODE SATP32_MODE
217#define HGATP_ASID SATP32_ASID
218#define HGATP_PPN SATP32_PPN
219#endif
220#if defined(TARGET_RISCV64)
221#define HGATP_MODE SATP64_MODE
222#define HGATP_ASID SATP64_ASID
223#define HGATP_PPN SATP64_PPN
224#endif
225
226/* Performance Counters */
227#define CSR_MHPMCOUNTER3 0xb03
228#define CSR_MHPMCOUNTER4 0xb04
229#define CSR_MHPMCOUNTER5 0xb05
230#define CSR_MHPMCOUNTER6 0xb06
231#define CSR_MHPMCOUNTER7 0xb07
232#define CSR_MHPMCOUNTER8 0xb08
233#define CSR_MHPMCOUNTER9 0xb09
234#define CSR_MHPMCOUNTER10 0xb0a
235#define CSR_MHPMCOUNTER11 0xb0b
236#define CSR_MHPMCOUNTER12 0xb0c
237#define CSR_MHPMCOUNTER13 0xb0d
238#define CSR_MHPMCOUNTER14 0xb0e
239#define CSR_MHPMCOUNTER15 0xb0f
240#define CSR_MHPMCOUNTER16 0xb10
241#define CSR_MHPMCOUNTER17 0xb11
242#define CSR_MHPMCOUNTER18 0xb12
243#define CSR_MHPMCOUNTER19 0xb13
244#define CSR_MHPMCOUNTER20 0xb14
245#define CSR_MHPMCOUNTER21 0xb15
246#define CSR_MHPMCOUNTER22 0xb16
247#define CSR_MHPMCOUNTER23 0xb17
248#define CSR_MHPMCOUNTER24 0xb18
249#define CSR_MHPMCOUNTER25 0xb19
250#define CSR_MHPMCOUNTER26 0xb1a
251#define CSR_MHPMCOUNTER27 0xb1b
252#define CSR_MHPMCOUNTER28 0xb1c
253#define CSR_MHPMCOUNTER29 0xb1d
254#define CSR_MHPMCOUNTER30 0xb1e
255#define CSR_MHPMCOUNTER31 0xb1f
256#define CSR_MHPMEVENT3 0x323
257#define CSR_MHPMEVENT4 0x324
258#define CSR_MHPMEVENT5 0x325
259#define CSR_MHPMEVENT6 0x326
260#define CSR_MHPMEVENT7 0x327
261#define CSR_MHPMEVENT8 0x328
262#define CSR_MHPMEVENT9 0x329
263#define CSR_MHPMEVENT10 0x32a
264#define CSR_MHPMEVENT11 0x32b
265#define CSR_MHPMEVENT12 0x32c
266#define CSR_MHPMEVENT13 0x32d
267#define CSR_MHPMEVENT14 0x32e
268#define CSR_MHPMEVENT15 0x32f
269#define CSR_MHPMEVENT16 0x330
270#define CSR_MHPMEVENT17 0x331
271#define CSR_MHPMEVENT18 0x332
272#define CSR_MHPMEVENT19 0x333
273#define CSR_MHPMEVENT20 0x334
274#define CSR_MHPMEVENT21 0x335
275#define CSR_MHPMEVENT22 0x336
276#define CSR_MHPMEVENT23 0x337
277#define CSR_MHPMEVENT24 0x338
278#define CSR_MHPMEVENT25 0x339
279#define CSR_MHPMEVENT26 0x33a
280#define CSR_MHPMEVENT27 0x33b
281#define CSR_MHPMEVENT28 0x33c
282#define CSR_MHPMEVENT29 0x33d
283#define CSR_MHPMEVENT30 0x33e
284#define CSR_MHPMEVENT31 0x33f
285#define CSR_MHPMCOUNTER3H 0xb83
286#define CSR_MHPMCOUNTER4H 0xb84
287#define CSR_MHPMCOUNTER5H 0xb85
288#define CSR_MHPMCOUNTER6H 0xb86
289#define CSR_MHPMCOUNTER7H 0xb87
290#define CSR_MHPMCOUNTER8H 0xb88
291#define CSR_MHPMCOUNTER9H 0xb89
292#define CSR_MHPMCOUNTER10H 0xb8a
293#define CSR_MHPMCOUNTER11H 0xb8b
294#define CSR_MHPMCOUNTER12H 0xb8c
295#define CSR_MHPMCOUNTER13H 0xb8d
296#define CSR_MHPMCOUNTER14H 0xb8e
297#define CSR_MHPMCOUNTER15H 0xb8f
298#define CSR_MHPMCOUNTER16H 0xb90
299#define CSR_MHPMCOUNTER17H 0xb91
300#define CSR_MHPMCOUNTER18H 0xb92
301#define CSR_MHPMCOUNTER19H 0xb93
302#define CSR_MHPMCOUNTER20H 0xb94
303#define CSR_MHPMCOUNTER21H 0xb95
304#define CSR_MHPMCOUNTER22H 0xb96
305#define CSR_MHPMCOUNTER23H 0xb97
306#define CSR_MHPMCOUNTER24H 0xb98
307#define CSR_MHPMCOUNTER25H 0xb99
308#define CSR_MHPMCOUNTER26H 0xb9a
309#define CSR_MHPMCOUNTER27H 0xb9b
310#define CSR_MHPMCOUNTER28H 0xb9c
311#define CSR_MHPMCOUNTER29H 0xb9d
312#define CSR_MHPMCOUNTER30H 0xb9e
313#define CSR_MHPMCOUNTER31H 0xb9f
314
315/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
316#define CSR_HIE 0x204
317#define CSR_HTVEC 0x205
318
319/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
320#define CSR_HSCRATCH 0x240
321#define CSR_HEPC 0x241
322#define CSR_HCAUSE 0x242
323#define CSR_HBADADDR 0x243
324#define CSR_HIP 0x244
325
326/* Legacy Machine Protection and Translation (priv v1.9.1) */
327#define CSR_MBASE 0x380
328#define CSR_MBOUND 0x381
329#define CSR_MIBASE 0x382
330#define CSR_MIBOUND 0x383
331#define CSR_MDBASE 0x384
332#define CSR_MDBOUND 0x385
333
334/* mstatus CSR bits */
335#define MSTATUS_UIE 0x00000001
336#define MSTATUS_SIE 0x00000002
337#define MSTATUS_MIE 0x00000008
338#define MSTATUS_UPIE 0x00000010
339#define MSTATUS_SPIE 0x00000020
340#define MSTATUS_MPIE 0x00000080
341#define MSTATUS_SPP 0x00000100
342#define MSTATUS_MPP 0x00001800
343#define MSTATUS_FS 0x00006000
344#define MSTATUS_XS 0x00018000
345#define MSTATUS_MPRV 0x00020000
346#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
347#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
348#define MSTATUS_MXR 0x00080000
349#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
350#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
351#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
352#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
353#define MSTATUS_MTL 0x4000000000ULL
354#define MSTATUS_MPV 0x8000000000ULL
355
356#define MSTATUS64_UXL 0x0000000300000000ULL
357#define MSTATUS64_SXL 0x0000000C00000000ULL
358
359#define MSTATUS32_SD 0x80000000
360#define MSTATUS64_SD 0x8000000000000000ULL
361
362#define MISA32_MXL 0xC0000000
363#define MISA64_MXL 0xC000000000000000ULL
364
365#define MXL_RV32 1
366#define MXL_RV64 2
367#define MXL_RV128 3
368
369#if defined(TARGET_RISCV32)
370#define MSTATUS_SD MSTATUS32_SD
371#define MISA_MXL MISA32_MXL
372#define MXL_VAL MXL_RV32
373#elif defined(TARGET_RISCV64)
374#define MSTATUS_SD MSTATUS64_SD
375#define MISA_MXL MISA64_MXL
376#define MXL_VAL MXL_RV64
377#endif
378
379/* sstatus CSR bits */
380#define SSTATUS_UIE 0x00000001
381#define SSTATUS_SIE 0x00000002
382#define SSTATUS_UPIE 0x00000010
383#define SSTATUS_SPIE 0x00000020
384#define SSTATUS_SPP 0x00000100
385#define SSTATUS_FS 0x00006000
386#define SSTATUS_XS 0x00018000
387#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
388#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
389#define SSTATUS_MXR 0x00080000
390
391#define SSTATUS32_SD 0x80000000
392#define SSTATUS64_SD 0x8000000000000000ULL
393
394#if defined(TARGET_RISCV32)
395#define SSTATUS_SD SSTATUS32_SD
396#elif defined(TARGET_RISCV64)
397#define SSTATUS_SD SSTATUS64_SD
398#endif
399
400/* hstatus CSR bits */
401#define HSTATUS_SPRV 0x00000001
402#define HSTATUS_STL 0x00000040
403#define HSTATUS_SPV 0x00000080
404#define HSTATUS_SP2P 0x00000100
405#define HSTATUS_SP2V 0x00000200
406#define HSTATUS_VTVM 0x00100000
407#define HSTATUS_VTSR 0x00400000
408
409#define HSTATUS32_WPRI 0xFF8FF87E
410#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
411
412#if defined(TARGET_RISCV32)
413#define HSTATUS_WPRI HSTATUS32_WPRI
414#elif defined(TARGET_RISCV64)
415#define HSTATUS_WPRI HSTATUS64_WPRI
416#endif
417
418/* Privilege modes */
419#define PRV_U 0
420#define PRV_S 1
421#define PRV_H 2 /* Reserved */
422#define PRV_M 3
423
424/* RV32 satp CSR field masks */
425#define SATP32_MODE 0x80000000
426#define SATP32_ASID 0x7fc00000
427#define SATP32_PPN 0x003fffff
428
429/* RV64 satp CSR field masks */
430#define SATP64_MODE 0xF000000000000000ULL
431#define SATP64_ASID 0x0FFFF00000000000ULL
432#define SATP64_PPN 0x00000FFFFFFFFFFFULL
433
434#if defined(TARGET_RISCV32)
435#define SATP_MODE SATP32_MODE
436#define SATP_ASID SATP32_ASID
437#define SATP_PPN SATP32_PPN
438#endif
439#if defined(TARGET_RISCV64)
440#define SATP_MODE SATP64_MODE
441#define SATP_ASID SATP64_ASID
442#define SATP_PPN SATP64_PPN
443#endif
444
445/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
446#define VM_1_09_MBARE 0
447#define VM_1_09_MBB 1
448#define VM_1_09_MBBID 2
449#define VM_1_09_SV32 8
450#define VM_1_09_SV39 9
451#define VM_1_09_SV48 10
452
453/* VM modes (satp.mode) privileged ISA 1.10 */
454#define VM_1_10_MBARE 0
455#define VM_1_10_SV32 1
456#define VM_1_10_SV39 8
457#define VM_1_10_SV48 9
458#define VM_1_10_SV57 10
459#define VM_1_10_SV64 11
460
461/* Page table entry (PTE) fields */
462#define PTE_V 0x001 /* Valid */
463#define PTE_R 0x002 /* Read */
464#define PTE_W 0x004 /* Write */
465#define PTE_X 0x008 /* Execute */
466#define PTE_U 0x010 /* User */
467#define PTE_G 0x020 /* Global */
468#define PTE_A 0x040 /* Accessed */
469#define PTE_D 0x080 /* Dirty */
470#define PTE_SOFT 0x300 /* Reserved for Software */
471
472/* Page table PPN shift amount */
473#define PTE_PPN_SHIFT 10
474
475/* Leaf page shift amount */
476#define PGSHIFT 12
477
478/* Default Reset Vector adress */
479#define DEFAULT_RSTVEC 0x1000
480
481/* Exception causes */
482#define EXCP_NONE -1 /* sentinel value */
483#define RISCV_EXCP_INST_ADDR_MIS 0x0
484#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
485#define RISCV_EXCP_ILLEGAL_INST 0x2
486#define RISCV_EXCP_BREAKPOINT 0x3
487#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
488#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
489#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
490#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
491#define RISCV_EXCP_U_ECALL 0x8
492#define RISCV_EXCP_S_ECALL 0x9
493#define RISCV_EXCP_H_ECALL 0xa
494#define RISCV_EXCP_M_ECALL 0xb
495#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
496#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
497#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
498
499#define RISCV_EXCP_INT_FLAG 0x80000000
500#define RISCV_EXCP_INT_MASK 0x7fffffff
501
502/* Interrupt causes */
503#define IRQ_U_SOFT 0
504#define IRQ_S_SOFT 1
505#define IRQ_H_SOFT 2 /* reserved */
506#define IRQ_M_SOFT 3
507#define IRQ_U_TIMER 4
508#define IRQ_S_TIMER 5
509#define IRQ_H_TIMER 6 /* reserved */
510#define IRQ_M_TIMER 7
511#define IRQ_U_EXT 8
512#define IRQ_S_EXT 9
513#define IRQ_H_EXT 10 /* reserved */
514#define IRQ_M_EXT 11
515
516/* mip masks */
517#define MIP_USIP (1 << IRQ_U_SOFT)
518#define MIP_SSIP (1 << IRQ_S_SOFT)
519#define MIP_HSIP (1 << IRQ_H_SOFT)
520#define MIP_MSIP (1 << IRQ_M_SOFT)
521#define MIP_UTIP (1 << IRQ_U_TIMER)
522#define MIP_STIP (1 << IRQ_S_TIMER)
523#define MIP_HTIP (1 << IRQ_H_TIMER)
524#define MIP_MTIP (1 << IRQ_M_TIMER)
525#define MIP_UEIP (1 << IRQ_U_EXT)
526#define MIP_SEIP (1 << IRQ_S_EXT)
527#define MIP_HEIP (1 << IRQ_H_EXT)
528#define MIP_MEIP (1 << IRQ_M_EXT)
529
530/* sip masks */
531#define SIP_SSIP MIP_SSIP
532#define SIP_STIP MIP_STIP
533#define SIP_SEIP MIP_SEIP
534
535#endif
536