1 | /* |
2 | * S/390 virtual CPU header |
3 | * |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright IBM Corp. 2012, 2018 |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
15 | * General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
19 | */ |
20 | |
21 | #ifndef S390X_CPU_H |
22 | #define S390X_CPU_H |
23 | |
24 | #include "cpu-qom.h" |
25 | #include "cpu_models.h" |
26 | #include "exec/cpu-defs.h" |
27 | |
28 | #define ELF_MACHINE_UNAME "S390X" |
29 | |
30 | /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ |
31 | #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) |
32 | |
33 | #define 1 |
34 | |
35 | #define MMU_MODE0_SUFFIX _primary |
36 | #define MMU_MODE1_SUFFIX _secondary |
37 | #define MMU_MODE2_SUFFIX _home |
38 | #define MMU_MODE3_SUFFIX _real |
39 | |
40 | #define MMU_USER_IDX 0 |
41 | |
42 | #define S390_MAX_CPUS 248 |
43 | |
44 | typedef struct PSW { |
45 | uint64_t mask; |
46 | uint64_t addr; |
47 | } PSW; |
48 | |
49 | struct CPUS390XState { |
50 | uint64_t regs[16]; /* GP registers */ |
51 | /* |
52 | * The floating point registers are part of the vector registers. |
53 | * vregs[0][0] -> vregs[15][0] are 16 floating point registers |
54 | */ |
55 | uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ |
56 | uint32_t aregs[16]; /* access registers */ |
57 | uint8_t riccb[64]; /* runtime instrumentation control */ |
58 | uint64_t gscb[4]; /* guarded storage control */ |
59 | uint64_t etoken; /* etoken */ |
60 | uint64_t etoken_extension; /* etoken extension */ |
61 | |
62 | /* Fields up to this point are not cleared by initial CPU reset */ |
63 | struct {} start_initial_reset_fields; |
64 | |
65 | uint32_t fpc; /* floating-point control register */ |
66 | uint32_t cc_op; |
67 | bool bpbc; /* branch prediction blocking */ |
68 | |
69 | float_status fpu_status; /* passed to softfloat lib */ |
70 | |
71 | /* The low part of a 128-bit return, or remainder of a divide. */ |
72 | uint64_t retxl; |
73 | |
74 | PSW psw; |
75 | |
76 | S390CrashReason crash_reason; |
77 | |
78 | uint64_t cc_src; |
79 | uint64_t cc_dst; |
80 | uint64_t cc_vr; |
81 | |
82 | uint64_t ex_value; |
83 | |
84 | uint64_t __excp_addr; |
85 | uint64_t psa; |
86 | |
87 | uint32_t int_pgm_code; |
88 | uint32_t int_pgm_ilen; |
89 | |
90 | uint32_t int_svc_code; |
91 | uint32_t int_svc_ilen; |
92 | |
93 | uint64_t per_address; |
94 | uint16_t per_perc_atmid; |
95 | |
96 | uint64_t cregs[16]; /* control registers */ |
97 | |
98 | int pending_int; |
99 | uint16_t external_call_addr; |
100 | DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); |
101 | |
102 | uint64_t ckc; |
103 | uint64_t cputm; |
104 | uint32_t todpr; |
105 | |
106 | uint64_t pfault_token; |
107 | uint64_t pfault_compare; |
108 | uint64_t pfault_select; |
109 | |
110 | uint64_t gbea; |
111 | uint64_t pp; |
112 | |
113 | /* Fields up to this point are cleared by a CPU reset */ |
114 | struct {} end_reset_fields; |
115 | |
116 | #if !defined(CONFIG_USER_ONLY) |
117 | uint32_t core_id; /* PoP "CPU address", same as cpu_index */ |
118 | uint64_t cpuid; |
119 | #endif |
120 | |
121 | QEMUTimer *tod_timer; |
122 | |
123 | QEMUTimer *cpu_timer; |
124 | |
125 | /* |
126 | * The cpu state represents the logical state of a cpu. In contrast to other |
127 | * architectures, there is a difference between a halt and a stop on s390. |
128 | * If all cpus are either stopped (including check stop) or in the disabled |
129 | * wait state, the vm can be shut down. |
130 | * The acceptable cpu_state values are defined in the CpuInfoS390State |
131 | * enum. |
132 | */ |
133 | uint8_t cpu_state; |
134 | |
135 | /* currently processed sigp order */ |
136 | uint8_t sigp_order; |
137 | |
138 | }; |
139 | |
140 | static inline uint64_t *get_freg(CPUS390XState *cs, int nr) |
141 | { |
142 | return &cs->vregs[nr][0]; |
143 | } |
144 | |
145 | /** |
146 | * S390CPU: |
147 | * @env: #CPUS390XState. |
148 | * |
149 | * An S/390 CPU. |
150 | */ |
151 | struct S390CPU { |
152 | /*< private >*/ |
153 | CPUState parent_obj; |
154 | /*< public >*/ |
155 | |
156 | CPUNegativeOffsetState neg; |
157 | CPUS390XState env; |
158 | S390CPUModel *model; |
159 | /* needed for live migration */ |
160 | void *irqstate; |
161 | uint32_t irqstate_saved_size; |
162 | }; |
163 | |
164 | |
165 | #ifndef CONFIG_USER_ONLY |
166 | extern const VMStateDescription vmstate_s390_cpu; |
167 | #endif |
168 | |
169 | /* distinguish between 24 bit and 31 bit addressing */ |
170 | #define HIGH_ORDER_BIT 0x80000000 |
171 | |
172 | /* Interrupt Codes */ |
173 | /* Program Interrupts */ |
174 | #define PGM_OPERATION 0x0001 |
175 | #define PGM_PRIVILEGED 0x0002 |
176 | #define PGM_EXECUTE 0x0003 |
177 | #define PGM_PROTECTION 0x0004 |
178 | #define PGM_ADDRESSING 0x0005 |
179 | #define PGM_SPECIFICATION 0x0006 |
180 | #define PGM_DATA 0x0007 |
181 | #define PGM_FIXPT_OVERFLOW 0x0008 |
182 | #define PGM_FIXPT_DIVIDE 0x0009 |
183 | #define PGM_DEC_OVERFLOW 0x000a |
184 | #define PGM_DEC_DIVIDE 0x000b |
185 | #define PGM_HFP_EXP_OVERFLOW 0x000c |
186 | #define PGM_HFP_EXP_UNDERFLOW 0x000d |
187 | #define PGM_HFP_SIGNIFICANCE 0x000e |
188 | #define PGM_HFP_DIVIDE 0x000f |
189 | #define PGM_SEGMENT_TRANS 0x0010 |
190 | #define PGM_PAGE_TRANS 0x0011 |
191 | #define PGM_TRANS_SPEC 0x0012 |
192 | #define PGM_SPECIAL_OP 0x0013 |
193 | #define PGM_OPERAND 0x0015 |
194 | #define PGM_TRACE_TABLE 0x0016 |
195 | #define PGM_VECTOR_PROCESSING 0x001b |
196 | #define PGM_SPACE_SWITCH 0x001c |
197 | #define PGM_HFP_SQRT 0x001d |
198 | #define PGM_PC_TRANS_SPEC 0x001f |
199 | #define PGM_AFX_TRANS 0x0020 |
200 | #define PGM_ASX_TRANS 0x0021 |
201 | #define PGM_LX_TRANS 0x0022 |
202 | #define PGM_EX_TRANS 0x0023 |
203 | #define PGM_PRIM_AUTH 0x0024 |
204 | #define PGM_SEC_AUTH 0x0025 |
205 | #define PGM_ALET_SPEC 0x0028 |
206 | #define PGM_ALEN_SPEC 0x0029 |
207 | #define PGM_ALE_SEQ 0x002a |
208 | #define PGM_ASTE_VALID 0x002b |
209 | #define PGM_ASTE_SEQ 0x002c |
210 | #define PGM_EXT_AUTH 0x002d |
211 | #define PGM_STACK_FULL 0x0030 |
212 | #define PGM_STACK_EMPTY 0x0031 |
213 | #define PGM_STACK_SPEC 0x0032 |
214 | #define PGM_STACK_TYPE 0x0033 |
215 | #define PGM_STACK_OP 0x0034 |
216 | #define PGM_ASCE_TYPE 0x0038 |
217 | #define PGM_REG_FIRST_TRANS 0x0039 |
218 | #define PGM_REG_SEC_TRANS 0x003a |
219 | #define PGM_REG_THIRD_TRANS 0x003b |
220 | #define PGM_MONITOR 0x0040 |
221 | #define PGM_PER 0x0080 |
222 | #define PGM_CRYPTO 0x0119 |
223 | |
224 | /* External Interrupts */ |
225 | #define EXT_INTERRUPT_KEY 0x0040 |
226 | #define EXT_CLOCK_COMP 0x1004 |
227 | #define EXT_CPU_TIMER 0x1005 |
228 | #define EXT_MALFUNCTION 0x1200 |
229 | #define EXT_EMERGENCY 0x1201 |
230 | #define EXT_EXTERNAL_CALL 0x1202 |
231 | #define EXT_ETR 0x1406 |
232 | #define EXT_SERVICE 0x2401 |
233 | #define EXT_VIRTIO 0x2603 |
234 | |
235 | /* PSW defines */ |
236 | #undef PSW_MASK_PER |
237 | #undef PSW_MASK_UNUSED_2 |
238 | #undef PSW_MASK_UNUSED_3 |
239 | #undef PSW_MASK_DAT |
240 | #undef PSW_MASK_IO |
241 | #undef PSW_MASK_EXT |
242 | #undef PSW_MASK_KEY |
243 | #undef PSW_SHIFT_KEY |
244 | #undef PSW_MASK_MCHECK |
245 | #undef PSW_MASK_WAIT |
246 | #undef PSW_MASK_PSTATE |
247 | #undef PSW_MASK_ASC |
248 | #undef PSW_SHIFT_ASC |
249 | #undef PSW_MASK_CC |
250 | #undef PSW_MASK_PM |
251 | #undef PSW_SHIFT_MASK_PM |
252 | #undef PSW_MASK_64 |
253 | #undef PSW_MASK_32 |
254 | #undef PSW_MASK_ESA_ADDR |
255 | |
256 | #define PSW_MASK_PER 0x4000000000000000ULL |
257 | #define PSW_MASK_UNUSED_2 0x2000000000000000ULL |
258 | #define PSW_MASK_UNUSED_3 0x1000000000000000ULL |
259 | #define PSW_MASK_DAT 0x0400000000000000ULL |
260 | #define PSW_MASK_IO 0x0200000000000000ULL |
261 | #define PSW_MASK_EXT 0x0100000000000000ULL |
262 | #define PSW_MASK_KEY 0x00F0000000000000ULL |
263 | #define PSW_SHIFT_KEY 52 |
264 | #define PSW_MASK_MCHECK 0x0004000000000000ULL |
265 | #define PSW_MASK_WAIT 0x0002000000000000ULL |
266 | #define PSW_MASK_PSTATE 0x0001000000000000ULL |
267 | #define PSW_MASK_ASC 0x0000C00000000000ULL |
268 | #define PSW_SHIFT_ASC 46 |
269 | #define PSW_MASK_CC 0x0000300000000000ULL |
270 | #define PSW_MASK_PM 0x00000F0000000000ULL |
271 | #define PSW_SHIFT_MASK_PM 40 |
272 | #define PSW_MASK_64 0x0000000100000000ULL |
273 | #define PSW_MASK_32 0x0000000080000000ULL |
274 | #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL |
275 | |
276 | #undef PSW_ASC_PRIMARY |
277 | #undef PSW_ASC_ACCREG |
278 | #undef PSW_ASC_SECONDARY |
279 | #undef PSW_ASC_HOME |
280 | |
281 | #define PSW_ASC_PRIMARY 0x0000000000000000ULL |
282 | #define PSW_ASC_ACCREG 0x0000400000000000ULL |
283 | #define PSW_ASC_SECONDARY 0x0000800000000000ULL |
284 | #define PSW_ASC_HOME 0x0000C00000000000ULL |
285 | |
286 | /* the address space values shifted */ |
287 | #define AS_PRIMARY 0 |
288 | #define AS_ACCREG 1 |
289 | #define AS_SECONDARY 2 |
290 | #define AS_HOME 3 |
291 | |
292 | /* tb flags */ |
293 | |
294 | #define FLAG_MASK_PSW_SHIFT 31 |
295 | #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) |
296 | #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) |
297 | #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) |
298 | #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) |
299 | #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) |
300 | #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) |
301 | #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ |
302 | | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) |
303 | |
304 | /* we'll use some unused PSW positions to store CR flags in tb flags */ |
305 | #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) |
306 | #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) |
307 | |
308 | /* Control register 0 bits */ |
309 | #define CR0_LOWPROT 0x0000000010000000ULL |
310 | #define CR0_SECONDARY 0x0000000004000000ULL |
311 | #define CR0_EDAT 0x0000000000800000ULL |
312 | #define CR0_AFP 0x0000000000040000ULL |
313 | #define CR0_VECTOR 0x0000000000020000ULL |
314 | #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL |
315 | #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL |
316 | #define CR0_CKC_SC 0x0000000000000800ULL |
317 | #define CR0_CPU_TIMER_SC 0x0000000000000400ULL |
318 | #define CR0_SERVICE_SC 0x0000000000000200ULL |
319 | |
320 | /* Control register 14 bits */ |
321 | #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL |
322 | |
323 | /* MMU */ |
324 | #define MMU_PRIMARY_IDX 0 |
325 | #define MMU_SECONDARY_IDX 1 |
326 | #define MMU_HOME_IDX 2 |
327 | #define MMU_REAL_IDX 3 |
328 | |
329 | static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) |
330 | { |
331 | if (!(env->psw.mask & PSW_MASK_DAT)) { |
332 | return MMU_REAL_IDX; |
333 | } |
334 | |
335 | if (ifetch) { |
336 | if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { |
337 | return MMU_HOME_IDX; |
338 | } |
339 | return MMU_PRIMARY_IDX; |
340 | } |
341 | |
342 | switch (env->psw.mask & PSW_MASK_ASC) { |
343 | case PSW_ASC_PRIMARY: |
344 | return MMU_PRIMARY_IDX; |
345 | case PSW_ASC_SECONDARY: |
346 | return MMU_SECONDARY_IDX; |
347 | case PSW_ASC_HOME: |
348 | return MMU_HOME_IDX; |
349 | case PSW_ASC_ACCREG: |
350 | /* Fallthrough: access register mode is not yet supported */ |
351 | default: |
352 | abort(); |
353 | } |
354 | } |
355 | |
356 | static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, |
357 | target_ulong *cs_base, uint32_t *flags) |
358 | { |
359 | *pc = env->psw.addr; |
360 | *cs_base = env->ex_value; |
361 | *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; |
362 | if (env->cregs[0] & CR0_AFP) { |
363 | *flags |= FLAG_MASK_AFP; |
364 | } |
365 | if (env->cregs[0] & CR0_VECTOR) { |
366 | *flags |= FLAG_MASK_VECTOR; |
367 | } |
368 | } |
369 | |
370 | /* PER bits from control register 9 */ |
371 | #define PER_CR9_EVENT_BRANCH 0x80000000 |
372 | #define PER_CR9_EVENT_IFETCH 0x40000000 |
373 | #define PER_CR9_EVENT_STORE 0x20000000 |
374 | #define PER_CR9_EVENT_STORE_REAL 0x08000000 |
375 | #define PER_CR9_EVENT_NULLIFICATION 0x01000000 |
376 | #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 |
377 | #define PER_CR9_CONTROL_ALTERATION 0x00200000 |
378 | |
379 | /* PER bits from the PER CODE/ATMID/AI in lowcore */ |
380 | #define PER_CODE_EVENT_BRANCH 0x8000 |
381 | #define PER_CODE_EVENT_IFETCH 0x4000 |
382 | #define PER_CODE_EVENT_STORE 0x2000 |
383 | #define PER_CODE_EVENT_STORE_REAL 0x0800 |
384 | #define PER_CODE_EVENT_NULLIFICATION 0x0100 |
385 | |
386 | #define EXCP_EXT 1 /* external interrupt */ |
387 | #define EXCP_SVC 2 /* supervisor call (syscall) */ |
388 | #define EXCP_PGM 3 /* program interruption */ |
389 | #define EXCP_RESTART 4 /* restart interrupt */ |
390 | #define EXCP_STOP 5 /* stop interrupt */ |
391 | #define EXCP_IO 7 /* I/O interrupt */ |
392 | #define EXCP_MCHK 8 /* machine check */ |
393 | |
394 | #define INTERRUPT_EXT_CPU_TIMER (1 << 3) |
395 | #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) |
396 | #define INTERRUPT_EXTERNAL_CALL (1 << 5) |
397 | #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) |
398 | #define INTERRUPT_RESTART (1 << 7) |
399 | #define INTERRUPT_STOP (1 << 8) |
400 | |
401 | /* Program Status Word. */ |
402 | #define S390_PSWM_REGNUM 0 |
403 | #define S390_PSWA_REGNUM 1 |
404 | /* General Purpose Registers. */ |
405 | #define S390_R0_REGNUM 2 |
406 | #define S390_R1_REGNUM 3 |
407 | #define S390_R2_REGNUM 4 |
408 | #define S390_R3_REGNUM 5 |
409 | #define S390_R4_REGNUM 6 |
410 | #define S390_R5_REGNUM 7 |
411 | #define S390_R6_REGNUM 8 |
412 | #define S390_R7_REGNUM 9 |
413 | #define S390_R8_REGNUM 10 |
414 | #define S390_R9_REGNUM 11 |
415 | #define S390_R10_REGNUM 12 |
416 | #define S390_R11_REGNUM 13 |
417 | #define S390_R12_REGNUM 14 |
418 | #define S390_R13_REGNUM 15 |
419 | #define S390_R14_REGNUM 16 |
420 | #define S390_R15_REGNUM 17 |
421 | /* Total Core Registers. */ |
422 | #define S390_NUM_CORE_REGS 18 |
423 | |
424 | static inline void setcc(S390CPU *cpu, uint64_t cc) |
425 | { |
426 | CPUS390XState *env = &cpu->env; |
427 | |
428 | env->psw.mask &= ~(3ull << 44); |
429 | env->psw.mask |= (cc & 3) << 44; |
430 | env->cc_op = cc; |
431 | } |
432 | |
433 | /* STSI */ |
434 | #define STSI_R0_FC_MASK 0x00000000f0000000ULL |
435 | #define STSI_R0_FC_CURRENT 0x0000000000000000ULL |
436 | #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL |
437 | #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL |
438 | #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL |
439 | #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL |
440 | #define STSI_R0_SEL1_MASK 0x00000000000000ffULL |
441 | #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL |
442 | #define STSI_R1_SEL2_MASK 0x000000000000ffffULL |
443 | |
444 | /* Basic Machine Configuration */ |
445 | typedef struct SysIB_111 { |
446 | uint8_t res1[32]; |
447 | uint8_t manuf[16]; |
448 | uint8_t type[4]; |
449 | uint8_t res2[12]; |
450 | uint8_t model[16]; |
451 | uint8_t sequence[16]; |
452 | uint8_t plant[4]; |
453 | uint8_t res3[3996]; |
454 | } SysIB_111; |
455 | QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); |
456 | |
457 | /* Basic Machine CPU */ |
458 | typedef struct SysIB_121 { |
459 | uint8_t res1[80]; |
460 | uint8_t sequence[16]; |
461 | uint8_t plant[4]; |
462 | uint8_t res2[2]; |
463 | uint16_t cpu_addr; |
464 | uint8_t res3[3992]; |
465 | } SysIB_121; |
466 | QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); |
467 | |
468 | /* Basic Machine CPUs */ |
469 | typedef struct SysIB_122 { |
470 | uint8_t res1[32]; |
471 | uint32_t capability; |
472 | uint16_t total_cpus; |
473 | uint16_t conf_cpus; |
474 | uint16_t standby_cpus; |
475 | uint16_t reserved_cpus; |
476 | uint16_t adjustments[2026]; |
477 | } SysIB_122; |
478 | QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); |
479 | |
480 | /* LPAR CPU */ |
481 | typedef struct SysIB_221 { |
482 | uint8_t res1[80]; |
483 | uint8_t sequence[16]; |
484 | uint8_t plant[4]; |
485 | uint16_t cpu_id; |
486 | uint16_t cpu_addr; |
487 | uint8_t res3[3992]; |
488 | } SysIB_221; |
489 | QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); |
490 | |
491 | /* LPAR CPUs */ |
492 | typedef struct SysIB_222 { |
493 | uint8_t res1[32]; |
494 | uint16_t lpar_num; |
495 | uint8_t res2; |
496 | uint8_t lcpuc; |
497 | uint16_t total_cpus; |
498 | uint16_t conf_cpus; |
499 | uint16_t standby_cpus; |
500 | uint16_t reserved_cpus; |
501 | uint8_t name[8]; |
502 | uint32_t caf; |
503 | uint8_t res3[16]; |
504 | uint16_t dedicated_cpus; |
505 | uint16_t shared_cpus; |
506 | uint8_t res4[4020]; |
507 | } SysIB_222; |
508 | QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); |
509 | |
510 | /* VM CPUs */ |
511 | typedef struct SysIB_322 { |
512 | uint8_t res1[31]; |
513 | uint8_t count; |
514 | struct { |
515 | uint8_t res2[4]; |
516 | uint16_t total_cpus; |
517 | uint16_t conf_cpus; |
518 | uint16_t standby_cpus; |
519 | uint16_t reserved_cpus; |
520 | uint8_t name[8]; |
521 | uint32_t caf; |
522 | uint8_t cpi[16]; |
523 | uint8_t res5[3]; |
524 | uint8_t ext_name_encoding; |
525 | uint32_t res3; |
526 | uint8_t uuid[16]; |
527 | } vm[8]; |
528 | uint8_t res4[1504]; |
529 | uint8_t ext_names[8][256]; |
530 | } SysIB_322; |
531 | QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); |
532 | |
533 | typedef union SysIB { |
534 | SysIB_111 sysib_111; |
535 | SysIB_121 sysib_121; |
536 | SysIB_122 sysib_122; |
537 | SysIB_221 sysib_221; |
538 | SysIB_222 sysib_222; |
539 | SysIB_322 sysib_322; |
540 | } SysIB; |
541 | QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); |
542 | |
543 | /* MMU defines */ |
544 | #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ |
545 | #define ASCE_SUBSPACE 0x200 /* subspace group control */ |
546 | #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ |
547 | #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ |
548 | #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ |
549 | #define ASCE_REAL_SPACE 0x20 /* real space control */ |
550 | #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ |
551 | #define ASCE_TYPE_REGION1 0x0c /* region first table type */ |
552 | #define ASCE_TYPE_REGION2 0x08 /* region second table type */ |
553 | #define ASCE_TYPE_REGION3 0x04 /* region third table type */ |
554 | #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ |
555 | #define ASCE_TABLE_LENGTH 0x03 /* region table length */ |
556 | |
557 | #define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */ |
558 | #define REGION_ENTRY_RO 0x200 /* region/segment protection bit */ |
559 | #define REGION_ENTRY_TF 0xc0 /* region/segment table offset */ |
560 | #define REGION_ENTRY_INV 0x20 /* invalid region table entry */ |
561 | #define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
562 | #define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ |
563 | #define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ |
564 | #define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ |
565 | #define REGION_ENTRY_LENGTH 0x03 /* region third length */ |
566 | |
567 | #define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */ |
568 | #define SEGMENT_ENTRY_FC 0x400 /* format control */ |
569 | #define SEGMENT_ENTRY_RO 0x200 /* page protection bit */ |
570 | #define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ |
571 | |
572 | #define VADDR_PX 0xff000 /* page index bits */ |
573 | |
574 | #define PAGE_RO 0x200 /* HW read-only bit */ |
575 | #define PAGE_INVALID 0x400 /* HW invalid bit */ |
576 | #define PAGE_RES0 0x800 /* bit must be zero */ |
577 | |
578 | #define SK_C (0x1 << 1) |
579 | #define SK_R (0x1 << 2) |
580 | #define SK_F (0x1 << 3) |
581 | #define SK_ACC_MASK (0xf << 4) |
582 | |
583 | /* SIGP order codes */ |
584 | #define SIGP_SENSE 0x01 |
585 | #define SIGP_EXTERNAL_CALL 0x02 |
586 | #define SIGP_EMERGENCY 0x03 |
587 | #define SIGP_START 0x04 |
588 | #define SIGP_STOP 0x05 |
589 | #define SIGP_RESTART 0x06 |
590 | #define SIGP_STOP_STORE_STATUS 0x09 |
591 | #define SIGP_INITIAL_CPU_RESET 0x0b |
592 | #define SIGP_CPU_RESET 0x0c |
593 | #define SIGP_SET_PREFIX 0x0d |
594 | #define SIGP_STORE_STATUS_ADDR 0x0e |
595 | #define SIGP_SET_ARCH 0x12 |
596 | #define SIGP_COND_EMERGENCY 0x13 |
597 | #define SIGP_SENSE_RUNNING 0x15 |
598 | #define SIGP_STORE_ADTL_STATUS 0x17 |
599 | |
600 | /* SIGP condition codes */ |
601 | #define SIGP_CC_ORDER_CODE_ACCEPTED 0 |
602 | #define SIGP_CC_STATUS_STORED 1 |
603 | #define SIGP_CC_BUSY 2 |
604 | #define SIGP_CC_NOT_OPERATIONAL 3 |
605 | |
606 | /* SIGP status bits */ |
607 | #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL |
608 | #define SIGP_STAT_NOT_RUNNING 0x00000400UL |
609 | #define SIGP_STAT_INCORRECT_STATE 0x00000200UL |
610 | #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL |
611 | #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL |
612 | #define SIGP_STAT_STOPPED 0x00000040UL |
613 | #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL |
614 | #define SIGP_STAT_CHECK_STOP 0x00000010UL |
615 | #define SIGP_STAT_INOPERATIVE 0x00000004UL |
616 | #define SIGP_STAT_INVALID_ORDER 0x00000002UL |
617 | #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL |
618 | |
619 | /* SIGP SET ARCHITECTURE modes */ |
620 | #define SIGP_MODE_ESA_S390 0 |
621 | #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 |
622 | #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 |
623 | |
624 | /* SIGP order code mask corresponding to bit positions 56-63 */ |
625 | #define SIGP_ORDER_MASK 0x000000ff |
626 | |
627 | /* machine check interruption code */ |
628 | |
629 | /* subclasses */ |
630 | #define MCIC_SC_SD 0x8000000000000000ULL |
631 | #define MCIC_SC_PD 0x4000000000000000ULL |
632 | #define MCIC_SC_SR 0x2000000000000000ULL |
633 | #define MCIC_SC_CD 0x0800000000000000ULL |
634 | #define MCIC_SC_ED 0x0400000000000000ULL |
635 | #define MCIC_SC_DG 0x0100000000000000ULL |
636 | #define MCIC_SC_W 0x0080000000000000ULL |
637 | #define MCIC_SC_CP 0x0040000000000000ULL |
638 | #define MCIC_SC_SP 0x0020000000000000ULL |
639 | #define MCIC_SC_CK 0x0010000000000000ULL |
640 | |
641 | /* subclass modifiers */ |
642 | #define MCIC_SCM_B 0x0002000000000000ULL |
643 | #define MCIC_SCM_DA 0x0000000020000000ULL |
644 | #define MCIC_SCM_AP 0x0000000000080000ULL |
645 | |
646 | /* storage errors */ |
647 | #define MCIC_SE_SE 0x0000800000000000ULL |
648 | #define MCIC_SE_SC 0x0000400000000000ULL |
649 | #define MCIC_SE_KE 0x0000200000000000ULL |
650 | #define MCIC_SE_DS 0x0000100000000000ULL |
651 | #define MCIC_SE_IE 0x0000000080000000ULL |
652 | |
653 | /* validity bits */ |
654 | #define MCIC_VB_WP 0x0000080000000000ULL |
655 | #define MCIC_VB_MS 0x0000040000000000ULL |
656 | #define MCIC_VB_PM 0x0000020000000000ULL |
657 | #define MCIC_VB_IA 0x0000010000000000ULL |
658 | #define MCIC_VB_FA 0x0000008000000000ULL |
659 | #define MCIC_VB_VR 0x0000004000000000ULL |
660 | #define MCIC_VB_EC 0x0000002000000000ULL |
661 | #define MCIC_VB_FP 0x0000001000000000ULL |
662 | #define MCIC_VB_GR 0x0000000800000000ULL |
663 | #define MCIC_VB_CR 0x0000000400000000ULL |
664 | #define MCIC_VB_ST 0x0000000100000000ULL |
665 | #define MCIC_VB_AR 0x0000000040000000ULL |
666 | #define MCIC_VB_GS 0x0000000008000000ULL |
667 | #define MCIC_VB_PR 0x0000000000200000ULL |
668 | #define MCIC_VB_FC 0x0000000000100000ULL |
669 | #define MCIC_VB_CT 0x0000000000020000ULL |
670 | #define MCIC_VB_CC 0x0000000000010000ULL |
671 | |
672 | static inline uint64_t s390_build_validity_mcic(void) |
673 | { |
674 | uint64_t mcic; |
675 | |
676 | /* |
677 | * Indicate all validity bits (no damage) only. Other bits have to be |
678 | * added by the caller. (storage errors, subclasses and subclass modifiers) |
679 | */ |
680 | mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | |
681 | MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | |
682 | MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; |
683 | if (s390_has_feat(S390_FEAT_VECTOR)) { |
684 | mcic |= MCIC_VB_VR; |
685 | } |
686 | if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { |
687 | mcic |= MCIC_VB_GS; |
688 | } |
689 | return mcic; |
690 | } |
691 | |
692 | static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) |
693 | { |
694 | cpu_reset(cs); |
695 | } |
696 | |
697 | static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) |
698 | { |
699 | S390CPUClass *scc = S390_CPU_GET_CLASS(cs); |
700 | |
701 | scc->cpu_reset(cs); |
702 | } |
703 | |
704 | static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) |
705 | { |
706 | S390CPUClass *scc = S390_CPU_GET_CLASS(cs); |
707 | |
708 | scc->initial_cpu_reset(cs); |
709 | } |
710 | |
711 | static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) |
712 | { |
713 | S390CPUClass *scc = S390_CPU_GET_CLASS(cs); |
714 | |
715 | scc->load_normal(cs); |
716 | } |
717 | |
718 | |
719 | /* cpu.c */ |
720 | void s390_crypto_reset(void); |
721 | int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); |
722 | void s390_set_max_pagesize(uint64_t pagesize, Error **errp); |
723 | void s390_cmma_reset(void); |
724 | void s390_enable_css_support(S390CPU *cpu); |
725 | int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, |
726 | int vq, bool assign); |
727 | #ifndef CONFIG_USER_ONLY |
728 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); |
729 | #else |
730 | static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) |
731 | { |
732 | return 0; |
733 | } |
734 | #endif /* CONFIG_USER_ONLY */ |
735 | static inline uint8_t s390_cpu_get_state(S390CPU *cpu) |
736 | { |
737 | return cpu->env.cpu_state; |
738 | } |
739 | |
740 | |
741 | /* cpu_models.c */ |
742 | void s390_cpu_list(void); |
743 | #define cpu_list s390_cpu_list |
744 | void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, |
745 | const S390FeatInit feat_init); |
746 | |
747 | |
748 | /* helper.c */ |
749 | #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU |
750 | #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) |
751 | #define CPU_RESOLVING_TYPE TYPE_S390_CPU |
752 | |
753 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
754 | signal handlers to inform the virtual CPU of exceptions. non zero |
755 | is returned if the signal was handled by the virtual CPU. */ |
756 | int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); |
757 | #define cpu_signal_handler cpu_s390x_signal_handler |
758 | |
759 | |
760 | /* interrupt.c */ |
761 | void s390_crw_mchk(void); |
762 | void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, |
763 | uint32_t io_int_parm, uint32_t io_int_word); |
764 | /* automatically detect the instruction length */ |
765 | #define ILEN_AUTO 0xff |
766 | #define RA_IGNORED 0 |
767 | void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, |
768 | uintptr_t ra); |
769 | /* service interrupts are floating therefore we must not pass an cpustate */ |
770 | void s390_sclp_extint(uint32_t parm); |
771 | |
772 | /* mmu_helper.c */ |
773 | int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, |
774 | int len, bool is_write); |
775 | #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ |
776 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) |
777 | #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ |
778 | s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) |
779 | #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ |
780 | s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) |
781 | #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ |
782 | s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) |
783 | void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); |
784 | |
785 | |
786 | /* sigp.c */ |
787 | int s390_cpu_restart(S390CPU *cpu); |
788 | void s390_init_sigp(void); |
789 | |
790 | |
791 | /* outside of target/s390x/ */ |
792 | S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); |
793 | |
794 | typedef CPUS390XState CPUArchState; |
795 | typedef S390CPU ArchCPU; |
796 | |
797 | #include "exec/cpu-all.h" |
798 | |
799 | #endif |
800 | |