1 | /* |
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License |
6 | * as published by the Free Software Foundation, version 2. |
7 | * |
8 | * This program is distributed in the hope that it will be useful, but |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
11 | * NON INFRINGEMENT. See the GNU General Public License for |
12 | * more details. |
13 | */ |
14 | |
15 | #ifndef ARCH_SPR_DEF_64_H |
16 | #define ARCH_SPR_DEF_64_H |
17 | |
18 | #define SPR_AUX_PERF_COUNT_0 0x2105 |
19 | #define SPR_AUX_PERF_COUNT_1 0x2106 |
20 | #define SPR_AUX_PERF_COUNT_CTL 0x2107 |
21 | #define SPR_AUX_PERF_COUNT_STS 0x2108 |
22 | #define SPR_CMPEXCH_VALUE 0x2780 |
23 | #define SPR_CYCLE 0x2781 |
24 | #define SPR_DONE 0x2705 |
25 | #define SPR_DSTREAM_PF 0x2706 |
26 | #define SPR_EVENT_BEGIN 0x2782 |
27 | #define SPR_EVENT_END 0x2783 |
28 | #define SPR_EX_CONTEXT_0_0 0x2580 |
29 | #define SPR_EX_CONTEXT_0_1 0x2581 |
30 | #define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 |
31 | #define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 |
32 | #define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 |
33 | #define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 |
34 | #define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 |
35 | #define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 |
36 | #define SPR_EX_CONTEXT_1_0 0x2480 |
37 | #define SPR_EX_CONTEXT_1_1 0x2481 |
38 | #define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 |
39 | #define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 |
40 | #define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 |
41 | #define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 |
42 | #define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 |
43 | #define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 |
44 | #define SPR_EX_CONTEXT_2_0 0x2380 |
45 | #define SPR_EX_CONTEXT_2_1 0x2381 |
46 | #define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 |
47 | #define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 |
48 | #define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 |
49 | #define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 |
50 | #define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 |
51 | #define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 |
52 | #define SPR_FAIL 0x2707 |
53 | #define SPR_IDN_AVAIL_EN 0x1a05 |
54 | #define SPR_IDN_DATA_AVAIL 0x0a80 |
55 | #define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 |
56 | #define SPR_IDN_DEMUX_COUNT_0 0x0a05 |
57 | #define SPR_IDN_DEMUX_COUNT_1 0x0a06 |
58 | #define SPR_IDN_DIRECTION_PROTECT 0x1405 |
59 | #define SPR_IDN_PENDING 0x0a08 |
60 | #define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 |
61 | #define SPR_INTCTRL_0_STATUS 0x2505 |
62 | #define SPR_INTCTRL_1_STATUS 0x2405 |
63 | #define SPR_INTCTRL_2_STATUS 0x2305 |
64 | #define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 |
65 | #define SPR_INTERRUPT_MASK_0 0x2506 |
66 | #define SPR_INTERRUPT_MASK_1 0x2406 |
67 | #define SPR_INTERRUPT_MASK_2 0x2306 |
68 | #define SPR_INTERRUPT_MASK_RESET_0 0x2507 |
69 | #define SPR_INTERRUPT_MASK_RESET_1 0x2407 |
70 | #define SPR_INTERRUPT_MASK_RESET_2 0x2307 |
71 | #define SPR_INTERRUPT_MASK_SET_0 0x2508 |
72 | #define SPR_INTERRUPT_MASK_SET_1 0x2408 |
73 | #define SPR_INTERRUPT_MASK_SET_2 0x2308 |
74 | #define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 |
75 | #define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 |
76 | #define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 |
77 | #define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 |
78 | #define SPR_IPI_EVENT_0 0x1f05 |
79 | #define SPR_IPI_EVENT_1 0x1e05 |
80 | #define SPR_IPI_EVENT_2 0x1d05 |
81 | #define SPR_IPI_EVENT_RESET_0 0x1f06 |
82 | #define SPR_IPI_EVENT_RESET_1 0x1e06 |
83 | #define SPR_IPI_EVENT_RESET_2 0x1d06 |
84 | #define SPR_IPI_EVENT_SET_0 0x1f07 |
85 | #define SPR_IPI_EVENT_SET_1 0x1e07 |
86 | #define SPR_IPI_EVENT_SET_2 0x1d07 |
87 | #define SPR_IPI_MASK_0 0x1f08 |
88 | #define SPR_IPI_MASK_1 0x1e08 |
89 | #define SPR_IPI_MASK_2 0x1d08 |
90 | #define SPR_IPI_MASK_RESET_0 0x1f09 |
91 | #define SPR_IPI_MASK_RESET_1 0x1e09 |
92 | #define SPR_IPI_MASK_RESET_2 0x1d09 |
93 | #define SPR_IPI_MASK_SET_0 0x1f0a |
94 | #define SPR_IPI_MASK_SET_1 0x1e0a |
95 | #define SPR_IPI_MASK_SET_2 0x1d0a |
96 | #define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 |
97 | #define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 |
98 | #define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 |
99 | #define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 |
100 | #define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 |
101 | #define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 |
102 | #define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 |
103 | #define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 |
104 | #define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 |
105 | #define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 |
106 | #define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 |
107 | #define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 |
108 | #define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 |
109 | #define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 |
110 | #define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 |
111 | #define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 |
112 | #define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 |
113 | #define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 |
114 | #define SPR_MPL_IDN_TIMER_SET_0 0x1800 |
115 | #define SPR_MPL_IDN_TIMER_SET_1 0x1801 |
116 | #define SPR_MPL_IDN_TIMER_SET_2 0x1802 |
117 | #define SPR_MPL_INTCTRL_0_SET_0 0x2500 |
118 | #define SPR_MPL_INTCTRL_0_SET_1 0x2501 |
119 | #define SPR_MPL_INTCTRL_0_SET_2 0x2502 |
120 | #define SPR_MPL_INTCTRL_1_SET_0 0x2400 |
121 | #define SPR_MPL_INTCTRL_1_SET_1 0x2401 |
122 | #define SPR_MPL_INTCTRL_1_SET_2 0x2402 |
123 | #define SPR_MPL_INTCTRL_2_SET_0 0x2300 |
124 | #define SPR_MPL_INTCTRL_2_SET_1 0x2301 |
125 | #define SPR_MPL_INTCTRL_2_SET_2 0x2302 |
126 | #define SPR_MPL_IPI_0 0x1f04 |
127 | #define SPR_MPL_IPI_0_SET_0 0x1f00 |
128 | #define SPR_MPL_IPI_0_SET_1 0x1f01 |
129 | #define SPR_MPL_IPI_0_SET_2 0x1f02 |
130 | #define SPR_MPL_IPI_1 0x1e04 |
131 | #define SPR_MPL_IPI_1_SET_0 0x1e00 |
132 | #define SPR_MPL_IPI_1_SET_1 0x1e01 |
133 | #define SPR_MPL_IPI_1_SET_2 0x1e02 |
134 | #define SPR_MPL_IPI_2 0x1d04 |
135 | #define SPR_MPL_IPI_2_SET_0 0x1d00 |
136 | #define SPR_MPL_IPI_2_SET_1 0x1d01 |
137 | #define SPR_MPL_IPI_2_SET_2 0x1d02 |
138 | #define SPR_MPL_PERF_COUNT_SET_0 0x2000 |
139 | #define SPR_MPL_PERF_COUNT_SET_1 0x2001 |
140 | #define SPR_MPL_PERF_COUNT_SET_2 0x2002 |
141 | #define SPR_MPL_UDN_ACCESS_SET_0 0x0b00 |
142 | #define SPR_MPL_UDN_ACCESS_SET_1 0x0b01 |
143 | #define SPR_MPL_UDN_ACCESS_SET_2 0x0b02 |
144 | #define SPR_MPL_UDN_AVAIL_SET_0 0x1b00 |
145 | #define SPR_MPL_UDN_AVAIL_SET_1 0x1b01 |
146 | #define SPR_MPL_UDN_AVAIL_SET_2 0x1b02 |
147 | #define SPR_MPL_UDN_COMPLETE_SET_0 0x0600 |
148 | #define SPR_MPL_UDN_COMPLETE_SET_1 0x0601 |
149 | #define SPR_MPL_UDN_COMPLETE_SET_2 0x0602 |
150 | #define SPR_MPL_UDN_FIREWALL_SET_0 0x1500 |
151 | #define SPR_MPL_UDN_FIREWALL_SET_1 0x1501 |
152 | #define SPR_MPL_UDN_FIREWALL_SET_2 0x1502 |
153 | #define SPR_MPL_UDN_TIMER_SET_0 0x1900 |
154 | #define SPR_MPL_UDN_TIMER_SET_1 0x1901 |
155 | #define SPR_MPL_UDN_TIMER_SET_2 0x1902 |
156 | #define SPR_MPL_WORLD_ACCESS_SET_0 0x2700 |
157 | #define SPR_MPL_WORLD_ACCESS_SET_1 0x2701 |
158 | #define SPR_MPL_WORLD_ACCESS_SET_2 0x2702 |
159 | #define SPR_PASS 0x2709 |
160 | #define SPR_PERF_COUNT_0 0x2005 |
161 | #define SPR_PERF_COUNT_1 0x2006 |
162 | #define SPR_PERF_COUNT_CTL 0x2007 |
163 | #define SPR_PERF_COUNT_DN_CTL 0x2008 |
164 | #define SPR_PERF_COUNT_STS 0x2009 |
165 | #define SPR_PROC_STATUS 0x2784 |
166 | #define SPR_SIM_CONTROL 0x2785 |
167 | #define SPR_SINGLE_STEP_CONTROL_0 0x0405 |
168 | #define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1 |
169 | #define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2 |
170 | #define SPR_SINGLE_STEP_CONTROL_1 0x0305 |
171 | #define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1 |
172 | #define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2 |
173 | #define SPR_SINGLE_STEP_CONTROL_2 0x0205 |
174 | #define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1 |
175 | #define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2 |
176 | #define SPR_SINGLE_STEP_EN_0_0 0x250a |
177 | #define SPR_SINGLE_STEP_EN_0_1 0x240a |
178 | #define SPR_SINGLE_STEP_EN_0_2 0x230a |
179 | #define SPR_SINGLE_STEP_EN_1_0 0x250b |
180 | #define SPR_SINGLE_STEP_EN_1_1 0x240b |
181 | #define SPR_SINGLE_STEP_EN_1_2 0x230b |
182 | #define SPR_SINGLE_STEP_EN_2_0 0x250c |
183 | #define SPR_SINGLE_STEP_EN_2_1 0x240c |
184 | #define SPR_SINGLE_STEP_EN_2_2 0x230c |
185 | #define SPR_SYSTEM_SAVE_0_0 0x2582 |
186 | #define SPR_SYSTEM_SAVE_0_1 0x2583 |
187 | #define SPR_SYSTEM_SAVE_0_2 0x2584 |
188 | #define SPR_SYSTEM_SAVE_0_3 0x2585 |
189 | #define SPR_SYSTEM_SAVE_1_0 0x2482 |
190 | #define SPR_SYSTEM_SAVE_1_1 0x2483 |
191 | #define SPR_SYSTEM_SAVE_1_2 0x2484 |
192 | #define SPR_SYSTEM_SAVE_1_3 0x2485 |
193 | #define SPR_SYSTEM_SAVE_2_0 0x2382 |
194 | #define SPR_SYSTEM_SAVE_2_1 0x2383 |
195 | #define SPR_SYSTEM_SAVE_2_2 0x2384 |
196 | #define SPR_SYSTEM_SAVE_2_3 0x2385 |
197 | #define SPR_TILE_COORD 0x270b |
198 | #define SPR_TILE_RTF_HWM 0x270c |
199 | #define SPR_TILE_TIMER_CONTROL 0x1605 |
200 | #define SPR_UDN_AVAIL_EN 0x1b05 |
201 | #define SPR_UDN_DATA_AVAIL 0x0b80 |
202 | #define SPR_UDN_DEADLOCK_TIMEOUT 0x1906 |
203 | #define SPR_UDN_DEMUX_COUNT_0 0x0b05 |
204 | #define SPR_UDN_DEMUX_COUNT_1 0x0b06 |
205 | #define SPR_UDN_DEMUX_COUNT_2 0x0b07 |
206 | #define SPR_UDN_DEMUX_COUNT_3 0x0b08 |
207 | #define SPR_UDN_DIRECTION_PROTECT 0x1505 |
208 | #define SPR_UDN_PENDING 0x0b0a |
209 | #define SPR_WATCH_MASK 0x200a |
210 | #define SPR_WATCH_VAL 0x200b |
211 | |
212 | #endif |
213 | |