1 | /* |
2 | * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn |
3 | * |
4 | * This library is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU Lesser General Public |
6 | * License as published by the Free Software Foundation; either |
7 | * version 2.1 of the License, or (at your option) any later version. |
8 | * |
9 | * This library is distributed in the hope that it will be useful, |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
12 | * Lesser General Public License for more details. |
13 | * |
14 | * You should have received a copy of the GNU Lesser General Public |
15 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
16 | */ |
17 | |
18 | #include "qemu/osdep.h" |
19 | |
20 | #include "cpu.h" |
21 | #include "exec/exec-all.h" |
22 | #include "fpu/softfloat-helpers.h" |
23 | #include "qemu/qemu-print.h" |
24 | |
25 | enum { |
26 | TLBRET_DIRTY = -4, |
27 | TLBRET_INVALID = -3, |
28 | TLBRET_NOMATCH = -2, |
29 | TLBRET_BADADDR = -1, |
30 | TLBRET_MATCH = 0 |
31 | }; |
32 | |
33 | #if defined(CONFIG_SOFTMMU) |
34 | static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, |
35 | int *prot, target_ulong address, |
36 | int rw, int access_type) |
37 | { |
38 | int ret = TLBRET_MATCH; |
39 | |
40 | *physical = address & 0xFFFFFFFF; |
41 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
42 | |
43 | return ret; |
44 | } |
45 | #endif |
46 | |
47 | /* TODO: Add exeption support*/ |
48 | static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, |
49 | int rw, int tlb_error) |
50 | { |
51 | } |
52 | |
53 | bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
54 | MMUAccessType rw, int mmu_idx, |
55 | bool probe, uintptr_t retaddr) |
56 | { |
57 | TriCoreCPU *cpu = TRICORE_CPU(cs); |
58 | CPUTriCoreState *env = &cpu->env; |
59 | hwaddr physical; |
60 | int prot; |
61 | int access_type; |
62 | int ret = 0; |
63 | |
64 | rw &= 1; |
65 | access_type = ACCESS_INT; |
66 | ret = get_physical_address(env, &physical, &prot, |
67 | address, rw, access_type); |
68 | |
69 | qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " |
70 | TARGET_FMT_plx " prot %d\n" , |
71 | __func__, (target_ulong)address, ret, physical, prot); |
72 | |
73 | if (ret == TLBRET_MATCH) { |
74 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
75 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, |
76 | mmu_idx, TARGET_PAGE_SIZE); |
77 | return true; |
78 | } else { |
79 | assert(ret < 0); |
80 | if (probe) { |
81 | return false; |
82 | } |
83 | raise_mmu_exception(env, address, rw, ret); |
84 | cpu_loop_exit_restore(cs, retaddr); |
85 | } |
86 | } |
87 | |
88 | static void tricore_cpu_list_entry(gpointer data, gpointer user_data) |
89 | { |
90 | ObjectClass *oc = data; |
91 | const char *typename; |
92 | char *name; |
93 | |
94 | typename = object_class_get_name(oc); |
95 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU)); |
96 | qemu_printf(" %s\n" , name); |
97 | g_free(name); |
98 | } |
99 | |
100 | void tricore_cpu_list(void) |
101 | { |
102 | GSList *list; |
103 | |
104 | list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false); |
105 | qemu_printf("Available CPUs:\n" ); |
106 | g_slist_foreach(list, tricore_cpu_list_entry, NULL); |
107 | g_slist_free(list); |
108 | } |
109 | |
110 | void fpu_set_state(CPUTriCoreState *env) |
111 | { |
112 | set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status); |
113 | set_flush_inputs_to_zero(1, &env->fp_status); |
114 | set_flush_to_zero(1, &env->fp_status); |
115 | set_default_nan_mode(1, &env->fp_status); |
116 | } |
117 | |
118 | uint32_t psw_read(CPUTriCoreState *env) |
119 | { |
120 | /* clear all USB bits */ |
121 | env->PSW &= 0x6ffffff; |
122 | /* now set them from the cache */ |
123 | env->PSW |= ((env->PSW_USB_C != 0) << 31); |
124 | env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); |
125 | env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2); |
126 | env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3); |
127 | env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4); |
128 | |
129 | return env->PSW; |
130 | } |
131 | |
132 | void psw_write(CPUTriCoreState *env, uint32_t val) |
133 | { |
134 | env->PSW_USB_C = (val & MASK_USB_C); |
135 | env->PSW_USB_V = (val & MASK_USB_V) << 1; |
136 | env->PSW_USB_SV = (val & MASK_USB_SV) << 2; |
137 | env->PSW_USB_AV = (val & MASK_USB_AV) << 3; |
138 | env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4; |
139 | env->PSW = val; |
140 | |
141 | fpu_set_state(env); |
142 | } |
143 | |