1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1999-2006 Tensilica Inc.
9 */
10
11#ifndef XTENSA_FSF_CORE_ISA_H
12#define XTENSA_FSF_CORE_ISA_H
13
14/****************************************************************************
15 Parameters Useful for Any Code, USER or PRIVILEGED
16 ****************************************************************************/
17
18/*
19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
20 * configured, and a value of 0 otherwise. These macros are always defined.
21 */
22
23
24/*----------------------------------------------------------------------
25 ISA
26 ----------------------------------------------------------------------*/
27
28#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
29#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
30#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
31#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
32#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
33#define XCHAL_HAVE_DEBUG 1 /* debug option */
34#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
36#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
37#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
38#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
39#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
40#define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */
41#define XCHAL_HAVE_MUL32 0 /* MULL instruction */
42#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
43#define XCHAL_HAVE_L32R 1 /* L32R instruction */
44#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
45#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
46#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
47#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
48#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
49#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
50#define XCHAL_HAVE_ABS 1 /* ABS instruction */
51/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
52/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
53#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
54#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
55#define XCHAL_HAVE_SPECULATION 0 /* speculation */
56#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
57#define XCHAL_NUM_CONTEXTS 1 /* */
58#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
59#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
60#define XCHAL_HAVE_PRID 1 /* processor ID register */
61#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
62#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
63#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
64#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
65#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
66#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
67#define XCHAL_HAVE_FP 0 /* floating point pkg */
68#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
69#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
70#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
71
72
73/*----------------------------------------------------------------------
74 MISC
75 ----------------------------------------------------------------------*/
76
77#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
78#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
79#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
80/* In T1050, applies to selected core load and store instructions (see ISA): */
81#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
82#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
83
84#define XCHAL_SW_VERSION 800002 /* sw version of this header */
85
86#define XCHAL_CORE_ID "fsf" /* alphanum core name
87 (CoreID) set in the Xtensa
88 Processor Generator */
89
90#define XCHAL_CORE_DESCRIPTION "fsf standard core"
91#define XCHAL_BUILD_UNIQUE_ID 0x00006700 /* 22-bit sw build ID */
92
93/*
94 * These definitions describe the hardware targeted by this software.
95 */
96#define XCHAL_HW_CONFIGID0 0xC103C3FF /* ConfigID hi 32 bits*/
97#define XCHAL_HW_CONFIGID1 0x0C006700 /* ConfigID lo 32 bits*/
98#define XCHAL_HW_VERSION_NAME "LX2.0.0" /* full version name */
99#define XCHAL_HW_VERSION_MAJOR 2200 /* major ver# of targeted hw */
100#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
101#define XTHAL_HW_REL_LX2 1
102#define XTHAL_HW_REL_LX2_0 1
103#define XTHAL_HW_REL_LX2_0_0 1
104#define XCHAL_HW_CONFIGID_RELIABLE 1
105/* If software targets a *range* of hardware versions, these are the bounds: */
106#define XCHAL_HW_MIN_VERSION_MAJOR 2200 /* major v of earliest tgt hw */
107#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
108#define XCHAL_HW_MAX_VERSION_MAJOR 2200 /* major v of latest tgt hw */
109#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
110
111
112/*----------------------------------------------------------------------
113 CACHE
114 ----------------------------------------------------------------------*/
115
116#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
117#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
118#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
119#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
120
121#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
122#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
123
124#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
125
126
127
128
129/****************************************************************************
130 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
131 ****************************************************************************/
132
133
134#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
135
136/*----------------------------------------------------------------------
137 CACHE
138 ----------------------------------------------------------------------*/
139
140#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
141
142/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
143
144/* Number of cache sets in log2(lines per way): */
145#define XCHAL_ICACHE_SETWIDTH 8
146#define XCHAL_DCACHE_SETWIDTH 8
147
148/* Cache set associativity (number of ways): */
149#define XCHAL_ICACHE_WAYS 2
150#define XCHAL_DCACHE_WAYS 2
151
152/* Cache features: */
153#define XCHAL_ICACHE_LINE_LOCKABLE 0
154#define XCHAL_DCACHE_LINE_LOCKABLE 0
155#define XCHAL_ICACHE_ECC_PARITY 0
156#define XCHAL_DCACHE_ECC_PARITY 0
157
158/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
159#define XCHAL_CA_BITS 4
160
161
162/*----------------------------------------------------------------------
163 INTERNAL I/D RAM/ROMs and XLMI
164 ----------------------------------------------------------------------*/
165
166#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
167#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
168#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
169#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
170#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
171#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
172
173
174/*----------------------------------------------------------------------
175 INTERRUPTS and TIMERS
176 ----------------------------------------------------------------------*/
177
178#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
179#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
180#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
181#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
182#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
183#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
184#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
185#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
186#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
187 (not including level zero) */
188#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
189 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
190
191/* Masks of interrupts at each interrupt level: */
192#define XCHAL_INTLEVEL1_MASK 0x000064F9
193#define XCHAL_INTLEVEL2_MASK 0x00008902
194#define XCHAL_INTLEVEL3_MASK 0x00011204
195#define XCHAL_INTLEVEL4_MASK 0x00000000
196#define XCHAL_INTLEVEL5_MASK 0x00000000
197#define XCHAL_INTLEVEL6_MASK 0x00000000
198#define XCHAL_INTLEVEL7_MASK 0x00000000
199
200/* Masks of interrupts at each range 1..n of interrupt levels: */
201#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
202#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
203#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
204#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
205#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
206#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
207#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
208
209/* Level of each interrupt: */
210#define XCHAL_INT0_LEVEL 1
211#define XCHAL_INT1_LEVEL 2
212#define XCHAL_INT2_LEVEL 3
213#define XCHAL_INT3_LEVEL 1
214#define XCHAL_INT4_LEVEL 1
215#define XCHAL_INT5_LEVEL 1
216#define XCHAL_INT6_LEVEL 1
217#define XCHAL_INT7_LEVEL 1
218#define XCHAL_INT8_LEVEL 2
219#define XCHAL_INT9_LEVEL 3
220#define XCHAL_INT10_LEVEL 1
221#define XCHAL_INT11_LEVEL 2
222#define XCHAL_INT12_LEVEL 3
223#define XCHAL_INT13_LEVEL 1
224#define XCHAL_INT14_LEVEL 1
225#define XCHAL_INT15_LEVEL 2
226#define XCHAL_INT16_LEVEL 3
227#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
228#define XCHAL_HAVE_DEBUG_EXTERN_INT 0 /* OCD external db interrupt */
229
230/* Type of each interrupt: */
231#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
232#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
233#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
234#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
235#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
236#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
237#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
238#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
239#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
240#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
241#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
242#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
243#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
244#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
245#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
246#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
247#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
248
249/* Masks of interrupts for each type of interrupt: */
250#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
251#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
252#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
253#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
254#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
255#define XCHAL_INTTYPE_MASK_NMI 0x00000000
256#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
257
258/* Interrupt numbers assigned to specific interrupt sources: */
259#define XCHAL_TIMER0_INTERRUPT 10 /* CCOMPARE0 */
260#define XCHAL_TIMER1_INTERRUPT 11 /* CCOMPARE1 */
261#define XCHAL_TIMER2_INTERRUPT 12 /* CCOMPARE2 */
262#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
263
264/* Interrupt numbers for levels at which only one interrupt is configured: */
265/* (There are many interrupts each at level(s) 1, 2, 3.) */
266
267
268/*
269 * External interrupt vectors/levels.
270 * These macros describe how Xtensa processor interrupt numbers
271 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
272 * map to external BInterrupt<n> pins, for those interrupts
273 * configured as external (level-triggered, edge-triggered, or NMI).
274 * See the Xtensa processor databook for more details.
275 */
276
277/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
278#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
279#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
280#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
281#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
282#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
283#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
284#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
285#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
286#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
287#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
288
289
290/*----------------------------------------------------------------------
291 EXCEPTIONS and VECTORS
292 ----------------------------------------------------------------------*/
293
294#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
295 number: 1 == XEA1 (old)
296 2 == XEA2 (new)
297 0 == XEAX (extern) */
298#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
299#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
300#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
301#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
302#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
303
304#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
305#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
306#define XCHAL_USER_VECTOR_VADDR 0xD0000220
307#define XCHAL_USER_VECTOR_PADDR 0x00000220
308#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
309#define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
310#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
311#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
312#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
313#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
314#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
315#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
316#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
317#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
318#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
319#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
320#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
321#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
322
323
324/*----------------------------------------------------------------------
325 DEBUG
326 ----------------------------------------------------------------------*/
327
328#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
329#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
330#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
331#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
332
333
334/*----------------------------------------------------------------------
335 MMU
336 ----------------------------------------------------------------------*/
337
338/* See <xtensa/config/core-matmap.h> header file for more details. */
339
340#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
341#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
342#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
343#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
344#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
345#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
346#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
347 [autorefill] and protection)
348 usable for an MMU-based OS */
349/* If none of the above last 4 are set, it's a custom TLB configuration. */
350#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
351#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
352
353#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
354#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
355#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
356
357#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
358
359
360#endif /* XTENSA_FSF_CORE_ISA_H */
361