1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) { \
30 .targno = (no), \
31 .flags = (fl), \
32 .type = (typ), \
33 .group = (grp), \
34 .size = (sz), \
35},
36#define XTREG_END { .targno = -1 },
37
38#ifndef XCHAL_HAVE_DEPBITS
39#define XCHAL_HAVE_DEPBITS 0
40#endif
41
42#ifndef XCHAL_HAVE_DIV32
43#define XCHAL_HAVE_DIV32 0
44#endif
45
46#ifndef XCHAL_UNALIGNED_LOAD_HW
47#define XCHAL_UNALIGNED_LOAD_HW 0
48#endif
49
50#ifndef XCHAL_HAVE_VECBASE
51#define XCHAL_HAVE_VECBASE 0
52#define XCHAL_VECBASE_RESET_VADDR 0
53#endif
54
55#ifndef XCHAL_RESET_VECTOR0_VADDR
56#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
57#endif
58
59#ifndef XCHAL_RESET_VECTOR1_VADDR
60#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
61#endif
62
63#ifndef XCHAL_HW_MIN_VERSION
64#define XCHAL_HW_MIN_VERSION 0
65#endif
66
67#ifndef XCHAL_LOOP_BUFFER_SIZE
68#define XCHAL_LOOP_BUFFER_SIZE 0
69#endif
70
71#ifndef XCHAL_HAVE_EXTERN_REGS
72#define XCHAL_HAVE_EXTERN_REGS 0
73#endif
74
75#ifndef XCHAL_HAVE_MPU
76#define XCHAL_HAVE_MPU 0
77#endif
78
79#ifndef XCHAL_HAVE_EXCLUSIVE
80#define XCHAL_HAVE_EXCLUSIVE 0
81#endif
82
83#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
84
85#define XTENSA_OPTIONS ( \
86 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
87 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
88 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
89 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
90 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
91 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
92 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
93 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
94 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
95 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
96 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
97 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
98 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
99 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
100 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
101 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
102 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
103 XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
104 XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
105 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
106 /* Interrupts and exceptions */ \
107 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
108 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
109 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
110 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
111 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
112 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
113 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
114 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
115 /* Local memory, TODO */ \
116 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
117 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
118 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
119 XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
120 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
121 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
122 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
123 XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
124 XTENSA_OPTION_MEMORY_ECC_PARITY) | \
125 /* Memory protection and translation */ \
126 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
127 XTENSA_OPTION_REGION_PROTECTION) | \
128 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
129 XTENSA_OPTION_REGION_TRANSLATION) | \
130 XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \
131 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
132 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
133 /* Other, TODO */ \
134 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
135 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
136 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
137 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
138 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
139 XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
140
141#ifndef XCHAL_WINDOW_OF4_VECOFS
142#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
143#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
144#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
145#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
146#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
147#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
148#endif
149
150#if XCHAL_HAVE_WINDOWED
151#define WINDOW_VECTORS \
152 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
153 XCHAL_WINDOW_VECTORS_VADDR, \
154 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
155 XCHAL_WINDOW_VECTORS_VADDR, \
156 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
157 XCHAL_WINDOW_VECTORS_VADDR, \
158 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
159 XCHAL_WINDOW_VECTORS_VADDR, \
160 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
161 XCHAL_WINDOW_VECTORS_VADDR, \
162 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
163 XCHAL_WINDOW_VECTORS_VADDR,
164#else
165#define WINDOW_VECTORS
166#endif
167
168#define EXCEPTION_VECTORS { \
169 [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
170 [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
171 WINDOW_VECTORS \
172 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
173 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
174 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
175 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
176 }
177
178#define INTERRUPT_VECTORS { \
179 0, \
180 0, \
181 XCHAL_INTLEVEL2_VECTOR_VADDR, \
182 XCHAL_INTLEVEL3_VECTOR_VADDR, \
183 XCHAL_INTLEVEL4_VECTOR_VADDR, \
184 XCHAL_INTLEVEL5_VECTOR_VADDR, \
185 XCHAL_INTLEVEL6_VECTOR_VADDR, \
186 XCHAL_INTLEVEL7_VECTOR_VADDR, \
187 }
188
189#define LEVEL_MASKS { \
190 [1] = XCHAL_INTLEVEL1_MASK, \
191 [2] = XCHAL_INTLEVEL2_MASK, \
192 [3] = XCHAL_INTLEVEL3_MASK, \
193 [4] = XCHAL_INTLEVEL4_MASK, \
194 [5] = XCHAL_INTLEVEL5_MASK, \
195 [6] = XCHAL_INTLEVEL6_MASK, \
196 [7] = XCHAL_INTLEVEL7_MASK, \
197 }
198
199#define INTTYPE_MASKS { \
200 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
201 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
202 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
203 }
204
205#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
206#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
207#define XTHAL_INTTYPE_NMI INTTYPE_NMI
208#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
209#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
210#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
211#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
212#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
213#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
214#define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE
215#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
216#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
217
218
219#define INTERRUPT(i) { \
220 .level = XCHAL_INT ## i ## _LEVEL, \
221 .inttype = XCHAL_INT ## i ## _TYPE, \
222 }
223
224#define INTERRUPTS { \
225 [0] = INTERRUPT(0), \
226 [1] = INTERRUPT(1), \
227 [2] = INTERRUPT(2), \
228 [3] = INTERRUPT(3), \
229 [4] = INTERRUPT(4), \
230 [5] = INTERRUPT(5), \
231 [6] = INTERRUPT(6), \
232 [7] = INTERRUPT(7), \
233 [8] = INTERRUPT(8), \
234 [9] = INTERRUPT(9), \
235 [10] = INTERRUPT(10), \
236 [11] = INTERRUPT(11), \
237 [12] = INTERRUPT(12), \
238 [13] = INTERRUPT(13), \
239 [14] = INTERRUPT(14), \
240 [15] = INTERRUPT(15), \
241 [16] = INTERRUPT(16), \
242 [17] = INTERRUPT(17), \
243 [18] = INTERRUPT(18), \
244 [19] = INTERRUPT(19), \
245 [20] = INTERRUPT(20), \
246 [21] = INTERRUPT(21), \
247 [22] = INTERRUPT(22), \
248 [23] = INTERRUPT(23), \
249 [24] = INTERRUPT(24), \
250 [25] = INTERRUPT(25), \
251 [26] = INTERRUPT(26), \
252 [27] = INTERRUPT(27), \
253 [28] = INTERRUPT(28), \
254 [29] = INTERRUPT(29), \
255 [30] = INTERRUPT(30), \
256 [31] = INTERRUPT(31), \
257 }
258
259#define TIMERINTS { \
260 [0] = XCHAL_TIMER0_INTERRUPT, \
261 [1] = XCHAL_TIMER1_INTERRUPT, \
262 [2] = XCHAL_TIMER2_INTERRUPT, \
263 }
264
265#define EXTINTS { \
266 [0] = XCHAL_EXTINT0_NUM, \
267 [1] = XCHAL_EXTINT1_NUM, \
268 [2] = XCHAL_EXTINT2_NUM, \
269 [3] = XCHAL_EXTINT3_NUM, \
270 [4] = XCHAL_EXTINT4_NUM, \
271 [5] = XCHAL_EXTINT5_NUM, \
272 [6] = XCHAL_EXTINT6_NUM, \
273 [7] = XCHAL_EXTINT7_NUM, \
274 [8] = XCHAL_EXTINT8_NUM, \
275 [9] = XCHAL_EXTINT9_NUM, \
276 [10] = XCHAL_EXTINT10_NUM, \
277 [11] = XCHAL_EXTINT11_NUM, \
278 [12] = XCHAL_EXTINT12_NUM, \
279 [13] = XCHAL_EXTINT13_NUM, \
280 [14] = XCHAL_EXTINT14_NUM, \
281 [15] = XCHAL_EXTINT15_NUM, \
282 [16] = XCHAL_EXTINT16_NUM, \
283 [17] = XCHAL_EXTINT17_NUM, \
284 [18] = XCHAL_EXTINT18_NUM, \
285 [19] = XCHAL_EXTINT19_NUM, \
286 [20] = XCHAL_EXTINT20_NUM, \
287 [21] = XCHAL_EXTINT21_NUM, \
288 [22] = XCHAL_EXTINT22_NUM, \
289 [23] = XCHAL_EXTINT23_NUM, \
290 [24] = XCHAL_EXTINT24_NUM, \
291 [25] = XCHAL_EXTINT25_NUM, \
292 [26] = XCHAL_EXTINT26_NUM, \
293 [27] = XCHAL_EXTINT27_NUM, \
294 [28] = XCHAL_EXTINT28_NUM, \
295 [29] = XCHAL_EXTINT29_NUM, \
296 [30] = XCHAL_EXTINT30_NUM, \
297 [31] = XCHAL_EXTINT31_NUM, \
298 }
299
300#define EXCEPTIONS_SECTION \
301 .excm_level = XCHAL_EXCM_LEVEL, \
302 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
303 .exception_vector = EXCEPTION_VECTORS
304
305#define INTERRUPTS_SECTION \
306 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
307 .nlevel = XCHAL_NUM_INTLEVELS, \
308 .interrupt_vector = INTERRUPT_VECTORS, \
309 .level_mask = LEVEL_MASKS, \
310 .inttype_mask = INTTYPE_MASKS, \
311 .interrupt = INTERRUPTS, \
312 .nccompare = XCHAL_NUM_TIMERS, \
313 .timerint = TIMERINTS, \
314 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
315 .extint = EXTINTS
316
317#if XCHAL_HAVE_PTP_MMU
318
319#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
320 .nways = ways, \
321 .way_size = { \
322 (refill_way_size), (refill_way_size), \
323 (refill_way_size), (refill_way_size), \
324 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
325 }, \
326 .varway56 = (way56), \
327 .nrefillentries = (refill_way_size) * 4, \
328 }
329
330#define ITLB(varway56) \
331 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
332
333#define DTLB(varway56) \
334 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
335
336#define TLB_SECTION \
337 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
338 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
339
340#ifndef XCHAL_SYSROM0_PADDR
341#define XCHAL_SYSROM0_PADDR 0xfe000000
342#define XCHAL_SYSROM0_SIZE 0x02000000
343#endif
344
345#ifndef XCHAL_SYSRAM0_PADDR
346#define XCHAL_SYSRAM0_PADDR 0x00000000
347#define XCHAL_SYSRAM0_SIZE 0x08000000
348#endif
349
350#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
351
352#define TLB_TEMPLATE { \
353 .nways = 1, \
354 .way_size = { \
355 8, \
356 } \
357 }
358
359#define TLB_SECTION \
360 .itlb = TLB_TEMPLATE, \
361 .dtlb = TLB_TEMPLATE
362
363#ifndef XCHAL_SYSROM0_PADDR
364#define XCHAL_SYSROM0_PADDR 0x50000000
365#define XCHAL_SYSROM0_SIZE 0x04000000
366#endif
367
368#ifndef XCHAL_SYSRAM0_PADDR
369#define XCHAL_SYSRAM0_PADDR 0x60000000
370#define XCHAL_SYSRAM0_SIZE 0x04000000
371#endif
372
373#elif XCHAL_HAVE_MPU
374
375#ifndef XTENSA_MPU_BG_MAP
376#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
377 { .vaddr = 0, .attr = 0x00006700, }, \
378}
379#endif
380
381#define TLB_SECTION \
382 .mpu_align = XCHAL_MPU_ALIGN, \
383 .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \
384 .n_mpu_bg_segments = 1, \
385 .mpu_bg = XTENSA_MPU_BG_MAP
386
387#ifndef XCHAL_SYSROM0_PADDR
388#define XCHAL_SYSROM0_PADDR 0x50000000
389#define XCHAL_SYSROM0_SIZE 0x04000000
390#endif
391
392#ifndef XCHAL_SYSRAM0_PADDR
393#define XCHAL_SYSRAM0_PADDR 0x60000000
394#define XCHAL_SYSRAM0_SIZE 0x04000000
395#endif
396
397#else
398
399#ifndef XCHAL_SYSROM0_PADDR
400#define XCHAL_SYSROM0_PADDR 0x50000000
401#define XCHAL_SYSROM0_SIZE 0x04000000
402#endif
403
404#ifndef XCHAL_SYSRAM0_PADDR
405#define XCHAL_SYSRAM0_PADDR 0x60000000
406#define XCHAL_SYSRAM0_SIZE 0x04000000
407#endif
408
409#endif
410
411#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
412#define REGISTER_CORE(core) \
413 static void __attribute__((constructor)) register_core(void) \
414 { \
415 static XtensaConfigList node = { \
416 .config = &core, \
417 }; \
418 xtensa_register_core(&node); \
419 }
420#else
421#define REGISTER_CORE(core)
422#endif
423
424#define DEBUG_SECTION \
425 .debug_level = XCHAL_DEBUGLEVEL, \
426 .nibreak = XCHAL_NUM_IBREAK, \
427 .ndbreak = XCHAL_NUM_DBREAK
428
429#define CACHE_SECTION \
430 .icache_ways = XCHAL_ICACHE_WAYS, \
431 .dcache_ways = XCHAL_DCACHE_WAYS, \
432 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
433 .memctl_mask = \
434 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
435 (XCHAL_DCACHE_SIZE ? \
436 MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
437 MEMCTL_ISNP | MEMCTL_DSNP | \
438 (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
439
440#define MEM_LOCATION(name, n) \
441 { \
442 .addr = XCHAL_ ## name ## n ## _PADDR, \
443 .size = XCHAL_ ## name ## n ## _SIZE, \
444 }
445
446#define MEM_SECTIONS(name) \
447 MEM_LOCATION(name, 0), \
448 MEM_LOCATION(name, 1), \
449 MEM_LOCATION(name, 2), \
450 MEM_LOCATION(name, 3)
451
452#define MEM_SECTION(name) \
453 .num = XCHAL_NUM_ ## name, \
454 .location = { \
455 MEM_SECTIONS(name) \
456 }
457
458#define SYSMEM_SECTION(name) \
459 .num = 1, \
460 .location = { \
461 { \
462 .addr = XCHAL_ ## name ## 0_PADDR, \
463 .size = XCHAL_ ## name ## 0_SIZE, \
464 } \
465 }
466
467#define LOCAL_MEMORIES_SECTION \
468 .instrom = { \
469 MEM_SECTION(INSTROM) \
470 }, \
471 .instram = { \
472 MEM_SECTION(INSTRAM) \
473 }, \
474 .datarom = { \
475 MEM_SECTION(DATAROM) \
476 }, \
477 .dataram = { \
478 MEM_SECTION(DATARAM) \
479 }, \
480 .sysrom = { \
481 SYSMEM_SECTION(SYSROM) \
482 }, \
483 .sysram = { \
484 SYSMEM_SECTION(SYSRAM) \
485 }
486
487#define CONFIG_SECTION \
488 .configid = { \
489 XCHAL_HW_CONFIGID0, \
490 XCHAL_HW_CONFIGID1, \
491 }
492
493#define DEFAULT_SECTIONS \
494 .options = XTENSA_OPTIONS, \
495 .nareg = XCHAL_NUM_AREGS, \
496 .ndepc = (XCHAL_XEA_VERSION >= 2), \
497 .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
498 .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
499 EXCEPTIONS_SECTION, \
500 INTERRUPTS_SECTION, \
501 TLB_SECTION, \
502 DEBUG_SECTION, \
503 CACHE_SECTION, \
504 LOCAL_MEMORIES_SECTION, \
505 CONFIG_SECTION
506
507
508#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
509#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
510#endif
511#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
512#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
513#endif
514#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
515#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
516#endif
517#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
518#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
519#endif
520#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
521#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
522#endif
523#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
524#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
525#endif
526
527
528#if XCHAL_NUM_INTERRUPTS <= 0
529#define XCHAL_INT0_LEVEL 0
530#define XCHAL_INT0_TYPE 0
531#endif
532#if XCHAL_NUM_INTERRUPTS <= 1
533#define XCHAL_INT1_LEVEL 0
534#define XCHAL_INT1_TYPE 0
535#endif
536#if XCHAL_NUM_INTERRUPTS <= 2
537#define XCHAL_INT2_LEVEL 0
538#define XCHAL_INT2_TYPE 0
539#endif
540#if XCHAL_NUM_INTERRUPTS <= 3
541#define XCHAL_INT3_LEVEL 0
542#define XCHAL_INT3_TYPE 0
543#endif
544#if XCHAL_NUM_INTERRUPTS <= 4
545#define XCHAL_INT4_LEVEL 0
546#define XCHAL_INT4_TYPE 0
547#endif
548#if XCHAL_NUM_INTERRUPTS <= 5
549#define XCHAL_INT5_LEVEL 0
550#define XCHAL_INT5_TYPE 0
551#endif
552#if XCHAL_NUM_INTERRUPTS <= 6
553#define XCHAL_INT6_LEVEL 0
554#define XCHAL_INT6_TYPE 0
555#endif
556#if XCHAL_NUM_INTERRUPTS <= 7
557#define XCHAL_INT7_LEVEL 0
558#define XCHAL_INT7_TYPE 0
559#endif
560#if XCHAL_NUM_INTERRUPTS <= 8
561#define XCHAL_INT8_LEVEL 0
562#define XCHAL_INT8_TYPE 0
563#endif
564#if XCHAL_NUM_INTERRUPTS <= 9
565#define XCHAL_INT9_LEVEL 0
566#define XCHAL_INT9_TYPE 0
567#endif
568#if XCHAL_NUM_INTERRUPTS <= 10
569#define XCHAL_INT10_LEVEL 0
570#define XCHAL_INT10_TYPE 0
571#endif
572#if XCHAL_NUM_INTERRUPTS <= 11
573#define XCHAL_INT11_LEVEL 0
574#define XCHAL_INT11_TYPE 0
575#endif
576#if XCHAL_NUM_INTERRUPTS <= 12
577#define XCHAL_INT12_LEVEL 0
578#define XCHAL_INT12_TYPE 0
579#endif
580#if XCHAL_NUM_INTERRUPTS <= 13
581#define XCHAL_INT13_LEVEL 0
582#define XCHAL_INT13_TYPE 0
583#endif
584#if XCHAL_NUM_INTERRUPTS <= 14
585#define XCHAL_INT14_LEVEL 0
586#define XCHAL_INT14_TYPE 0
587#endif
588#if XCHAL_NUM_INTERRUPTS <= 15
589#define XCHAL_INT15_LEVEL 0
590#define XCHAL_INT15_TYPE 0
591#endif
592#if XCHAL_NUM_INTERRUPTS <= 16
593#define XCHAL_INT16_LEVEL 0
594#define XCHAL_INT16_TYPE 0
595#endif
596#if XCHAL_NUM_INTERRUPTS <= 17
597#define XCHAL_INT17_LEVEL 0
598#define XCHAL_INT17_TYPE 0
599#endif
600#if XCHAL_NUM_INTERRUPTS <= 18
601#define XCHAL_INT18_LEVEL 0
602#define XCHAL_INT18_TYPE 0
603#endif
604#if XCHAL_NUM_INTERRUPTS <= 19
605#define XCHAL_INT19_LEVEL 0
606#define XCHAL_INT19_TYPE 0
607#endif
608#if XCHAL_NUM_INTERRUPTS <= 20
609#define XCHAL_INT20_LEVEL 0
610#define XCHAL_INT20_TYPE 0
611#endif
612#if XCHAL_NUM_INTERRUPTS <= 21
613#define XCHAL_INT21_LEVEL 0
614#define XCHAL_INT21_TYPE 0
615#endif
616#if XCHAL_NUM_INTERRUPTS <= 22
617#define XCHAL_INT22_LEVEL 0
618#define XCHAL_INT22_TYPE 0
619#endif
620#if XCHAL_NUM_INTERRUPTS <= 23
621#define XCHAL_INT23_LEVEL 0
622#define XCHAL_INT23_TYPE 0
623#endif
624#if XCHAL_NUM_INTERRUPTS <= 24
625#define XCHAL_INT24_LEVEL 0
626#define XCHAL_INT24_TYPE 0
627#endif
628#if XCHAL_NUM_INTERRUPTS <= 25
629#define XCHAL_INT25_LEVEL 0
630#define XCHAL_INT25_TYPE 0
631#endif
632#if XCHAL_NUM_INTERRUPTS <= 26
633#define XCHAL_INT26_LEVEL 0
634#define XCHAL_INT26_TYPE 0
635#endif
636#if XCHAL_NUM_INTERRUPTS <= 27
637#define XCHAL_INT27_LEVEL 0
638#define XCHAL_INT27_TYPE 0
639#endif
640#if XCHAL_NUM_INTERRUPTS <= 28
641#define XCHAL_INT28_LEVEL 0
642#define XCHAL_INT28_TYPE 0
643#endif
644#if XCHAL_NUM_INTERRUPTS <= 29
645#define XCHAL_INT29_LEVEL 0
646#define XCHAL_INT29_TYPE 0
647#endif
648#if XCHAL_NUM_INTERRUPTS <= 30
649#define XCHAL_INT30_LEVEL 0
650#define XCHAL_INT30_TYPE 0
651#endif
652#if XCHAL_NUM_INTERRUPTS <= 31
653#define XCHAL_INT31_LEVEL 0
654#define XCHAL_INT31_TYPE 0
655#endif
656
657
658#if XCHAL_NUM_EXTINTERRUPTS <= 0
659#define XCHAL_EXTINT0_NUM 0
660#endif
661#if XCHAL_NUM_EXTINTERRUPTS <= 1
662#define XCHAL_EXTINT1_NUM 0
663#endif
664#if XCHAL_NUM_EXTINTERRUPTS <= 2
665#define XCHAL_EXTINT2_NUM 0
666#endif
667#if XCHAL_NUM_EXTINTERRUPTS <= 3
668#define XCHAL_EXTINT3_NUM 0
669#endif
670#if XCHAL_NUM_EXTINTERRUPTS <= 4
671#define XCHAL_EXTINT4_NUM 0
672#endif
673#if XCHAL_NUM_EXTINTERRUPTS <= 5
674#define XCHAL_EXTINT5_NUM 0
675#endif
676#if XCHAL_NUM_EXTINTERRUPTS <= 6
677#define XCHAL_EXTINT6_NUM 0
678#endif
679#if XCHAL_NUM_EXTINTERRUPTS <= 7
680#define XCHAL_EXTINT7_NUM 0
681#endif
682#if XCHAL_NUM_EXTINTERRUPTS <= 8
683#define XCHAL_EXTINT8_NUM 0
684#endif
685#if XCHAL_NUM_EXTINTERRUPTS <= 9
686#define XCHAL_EXTINT9_NUM 0
687#endif
688#if XCHAL_NUM_EXTINTERRUPTS <= 10
689#define XCHAL_EXTINT10_NUM 0
690#endif
691#if XCHAL_NUM_EXTINTERRUPTS <= 11
692#define XCHAL_EXTINT11_NUM 0
693#endif
694#if XCHAL_NUM_EXTINTERRUPTS <= 12
695#define XCHAL_EXTINT12_NUM 0
696#endif
697#if XCHAL_NUM_EXTINTERRUPTS <= 13
698#define XCHAL_EXTINT13_NUM 0
699#endif
700#if XCHAL_NUM_EXTINTERRUPTS <= 14
701#define XCHAL_EXTINT14_NUM 0
702#endif
703#if XCHAL_NUM_EXTINTERRUPTS <= 15
704#define XCHAL_EXTINT15_NUM 0
705#endif
706#if XCHAL_NUM_EXTINTERRUPTS <= 16
707#define XCHAL_EXTINT16_NUM 0
708#endif
709#if XCHAL_NUM_EXTINTERRUPTS <= 17
710#define XCHAL_EXTINT17_NUM 0
711#endif
712#if XCHAL_NUM_EXTINTERRUPTS <= 18
713#define XCHAL_EXTINT18_NUM 0
714#endif
715#if XCHAL_NUM_EXTINTERRUPTS <= 19
716#define XCHAL_EXTINT19_NUM 0
717#endif
718#if XCHAL_NUM_EXTINTERRUPTS <= 20
719#define XCHAL_EXTINT20_NUM 0
720#endif
721#if XCHAL_NUM_EXTINTERRUPTS <= 21
722#define XCHAL_EXTINT21_NUM 0
723#endif
724#if XCHAL_NUM_EXTINTERRUPTS <= 22
725#define XCHAL_EXTINT22_NUM 0
726#endif
727#if XCHAL_NUM_EXTINTERRUPTS <= 23
728#define XCHAL_EXTINT23_NUM 0
729#endif
730#if XCHAL_NUM_EXTINTERRUPTS <= 24
731#define XCHAL_EXTINT24_NUM 0
732#endif
733#if XCHAL_NUM_EXTINTERRUPTS <= 25
734#define XCHAL_EXTINT25_NUM 0
735#endif
736#if XCHAL_NUM_EXTINTERRUPTS <= 26
737#define XCHAL_EXTINT26_NUM 0
738#endif
739#if XCHAL_NUM_EXTINTERRUPTS <= 27
740#define XCHAL_EXTINT27_NUM 0
741#endif
742#if XCHAL_NUM_EXTINTERRUPTS <= 28
743#define XCHAL_EXTINT28_NUM 0
744#endif
745#if XCHAL_NUM_EXTINTERRUPTS <= 29
746#define XCHAL_EXTINT29_NUM 0
747#endif
748#if XCHAL_NUM_EXTINTERRUPTS <= 30
749#define XCHAL_EXTINT30_NUM 0
750#endif
751#if XCHAL_NUM_EXTINTERRUPTS <= 31
752#define XCHAL_EXTINT31_NUM 0
753#endif
754
755
756#define XTHAL_TIMER_UNCONFIGURED 0
757
758#if XCHAL_NUM_INSTROM < 1
759#define XCHAL_INSTROM0_PADDR 0
760#define XCHAL_INSTROM0_SIZE 0
761#endif
762#if XCHAL_NUM_INSTROM < 2
763#define XCHAL_INSTROM1_PADDR 0
764#define XCHAL_INSTROM1_SIZE 0
765#endif
766#if XCHAL_NUM_INSTROM < 3
767#define XCHAL_INSTROM2_PADDR 0
768#define XCHAL_INSTROM2_SIZE 0
769#endif
770#if XCHAL_NUM_INSTROM < 4
771#define XCHAL_INSTROM3_PADDR 0
772#define XCHAL_INSTROM3_SIZE 0
773#endif
774#if XCHAL_NUM_INSTROM > MAX_NMEMORY
775#error XCHAL_NUM_INSTROM > MAX_NMEMORY
776#endif
777
778#if XCHAL_NUM_INSTRAM < 1
779#define XCHAL_INSTRAM0_PADDR 0
780#define XCHAL_INSTRAM0_SIZE 0
781#endif
782#if XCHAL_NUM_INSTRAM < 2
783#define XCHAL_INSTRAM1_PADDR 0
784#define XCHAL_INSTRAM1_SIZE 0
785#endif
786#if XCHAL_NUM_INSTRAM < 3
787#define XCHAL_INSTRAM2_PADDR 0
788#define XCHAL_INSTRAM2_SIZE 0
789#endif
790#if XCHAL_NUM_INSTRAM < 4
791#define XCHAL_INSTRAM3_PADDR 0
792#define XCHAL_INSTRAM3_SIZE 0
793#endif
794#if XCHAL_NUM_INSTRAM > MAX_NMEMORY
795#error XCHAL_NUM_INSTRAM > MAX_NMEMORY
796#endif
797
798#if XCHAL_NUM_DATAROM < 1
799#define XCHAL_DATAROM0_PADDR 0
800#define XCHAL_DATAROM0_SIZE 0
801#endif
802#if XCHAL_NUM_DATAROM < 2
803#define XCHAL_DATAROM1_PADDR 0
804#define XCHAL_DATAROM1_SIZE 0
805#endif
806#if XCHAL_NUM_DATAROM < 3
807#define XCHAL_DATAROM2_PADDR 0
808#define XCHAL_DATAROM2_SIZE 0
809#endif
810#if XCHAL_NUM_DATAROM < 4
811#define XCHAL_DATAROM3_PADDR 0
812#define XCHAL_DATAROM3_SIZE 0
813#endif
814#if XCHAL_NUM_DATAROM > MAX_NMEMORY
815#error XCHAL_NUM_DATAROM > MAX_NMEMORY
816#endif
817
818#if XCHAL_NUM_DATARAM < 1
819#define XCHAL_DATARAM0_PADDR 0
820#define XCHAL_DATARAM0_SIZE 0
821#endif
822#if XCHAL_NUM_DATARAM < 2
823#define XCHAL_DATARAM1_PADDR 0
824#define XCHAL_DATARAM1_SIZE 0
825#endif
826#if XCHAL_NUM_DATARAM < 3
827#define XCHAL_DATARAM2_PADDR 0
828#define XCHAL_DATARAM2_SIZE 0
829#endif
830#if XCHAL_NUM_DATARAM < 4
831#define XCHAL_DATARAM3_PADDR 0
832#define XCHAL_DATARAM3_SIZE 0
833#endif
834#if XCHAL_NUM_DATARAM > MAX_NMEMORY
835#error XCHAL_NUM_DATARAM > MAX_NMEMORY
836#endif
837