1 | /* |
2 | * Tiny Code Generator for QEMU |
3 | * |
4 | * Copyright (c) 2008 Fabrice Bellard |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | /* |
26 | * DEF(name, oargs, iargs, cargs, flags) |
27 | */ |
28 | |
29 | /* predefined ops */ |
30 | DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) |
31 | DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) |
32 | |
33 | /* variable number of parameters */ |
34 | DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) |
35 | |
36 | DEF(br, 0, 0, 1, TCG_OPF_BB_END) |
37 | |
38 | #define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0) |
39 | #if TCG_TARGET_REG_BITS == 32 |
40 | # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT |
41 | #else |
42 | # define IMPL64 TCG_OPF_64BIT |
43 | #endif |
44 | |
45 | DEF(mb, 0, 0, 1, 0) |
46 | |
47 | DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) |
48 | DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) |
49 | DEF(setcond_i32, 1, 2, 1, 0) |
50 | DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) |
51 | /* load/store */ |
52 | DEF(ld8u_i32, 1, 1, 1, 0) |
53 | DEF(ld8s_i32, 1, 1, 1, 0) |
54 | DEF(ld16u_i32, 1, 1, 1, 0) |
55 | DEF(ld16s_i32, 1, 1, 1, 0) |
56 | DEF(ld_i32, 1, 1, 1, 0) |
57 | DEF(st8_i32, 0, 2, 1, 0) |
58 | DEF(st16_i32, 0, 2, 1, 0) |
59 | DEF(st_i32, 0, 2, 1, 0) |
60 | /* arith */ |
61 | DEF(add_i32, 1, 2, 0, 0) |
62 | DEF(sub_i32, 1, 2, 0, 0) |
63 | DEF(mul_i32, 1, 2, 0, 0) |
64 | DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
65 | DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
66 | DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) |
67 | DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) |
68 | DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) |
69 | DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) |
70 | DEF(and_i32, 1, 2, 0, 0) |
71 | DEF(or_i32, 1, 2, 0, 0) |
72 | DEF(xor_i32, 1, 2, 0, 0) |
73 | /* shifts/rotates */ |
74 | DEF(shl_i32, 1, 2, 0, 0) |
75 | DEF(shr_i32, 1, 2, 0, 0) |
76 | DEF(sar_i32, 1, 2, 0, 0) |
77 | DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) |
78 | DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) |
79 | DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) |
80 | DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32)) |
81 | DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32)) |
82 | DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32)) |
83 | |
84 | DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END) |
85 | |
86 | DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) |
87 | DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) |
88 | DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32)) |
89 | DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32)) |
90 | DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32)) |
91 | DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32)) |
92 | DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32)) |
93 | DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) |
94 | |
95 | DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) |
96 | DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32)) |
97 | DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32)) |
98 | DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) |
99 | DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32)) |
100 | DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32)) |
101 | DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) |
102 | DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) |
103 | DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) |
104 | DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) |
105 | DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) |
106 | DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) |
107 | DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) |
108 | DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32)) |
109 | DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) |
110 | DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) |
111 | |
112 | DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) |
113 | DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) |
114 | DEF(setcond_i64, 1, 2, 1, IMPL64) |
115 | DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) |
116 | /* load/store */ |
117 | DEF(ld8u_i64, 1, 1, 1, IMPL64) |
118 | DEF(ld8s_i64, 1, 1, 1, IMPL64) |
119 | DEF(ld16u_i64, 1, 1, 1, IMPL64) |
120 | DEF(ld16s_i64, 1, 1, 1, IMPL64) |
121 | DEF(ld32u_i64, 1, 1, 1, IMPL64) |
122 | DEF(ld32s_i64, 1, 1, 1, IMPL64) |
123 | DEF(ld_i64, 1, 1, 1, IMPL64) |
124 | DEF(st8_i64, 0, 2, 1, IMPL64) |
125 | DEF(st16_i64, 0, 2, 1, IMPL64) |
126 | DEF(st32_i64, 0, 2, 1, IMPL64) |
127 | DEF(st_i64, 0, 2, 1, IMPL64) |
128 | /* arith */ |
129 | DEF(add_i64, 1, 2, 0, IMPL64) |
130 | DEF(sub_i64, 1, 2, 0, IMPL64) |
131 | DEF(mul_i64, 1, 2, 0, IMPL64) |
132 | DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
133 | DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
134 | DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) |
135 | DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) |
136 | DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) |
137 | DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) |
138 | DEF(and_i64, 1, 2, 0, IMPL64) |
139 | DEF(or_i64, 1, 2, 0, IMPL64) |
140 | DEF(xor_i64, 1, 2, 0, IMPL64) |
141 | /* shifts/rotates */ |
142 | DEF(shl_i64, 1, 2, 0, IMPL64) |
143 | DEF(shr_i64, 1, 2, 0, IMPL64) |
144 | DEF(sar_i64, 1, 2, 0, IMPL64) |
145 | DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) |
146 | DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) |
147 | DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) |
148 | DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64)) |
149 | DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) |
150 | DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64)) |
151 | |
152 | /* size changing ops */ |
153 | DEF(ext_i32_i64, 1, 1, 0, IMPL64) |
154 | DEF(extu_i32_i64, 1, 1, 0, IMPL64) |
155 | DEF(extrl_i64_i32, 1, 1, 0, |
156 | IMPL(TCG_TARGET_HAS_extrl_i64_i32) |
157 | | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) |
158 | DEF(extrh_i64_i32, 1, 1, 0, |
159 | IMPL(TCG_TARGET_HAS_extrh_i64_i32) |
160 | | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) |
161 | |
162 | DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64) |
163 | DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) |
164 | DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) |
165 | DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64)) |
166 | DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64)) |
167 | DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64)) |
168 | DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64)) |
169 | DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) |
170 | DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) |
171 | DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) |
172 | DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) |
173 | DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64)) |
174 | DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) |
175 | DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) |
176 | DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) |
177 | DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) |
178 | DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) |
179 | DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64)) |
180 | DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64)) |
181 | DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64)) |
182 | |
183 | DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) |
184 | DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) |
185 | DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64)) |
186 | DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) |
187 | DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) |
188 | DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) |
189 | |
190 | #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) |
191 | #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) |
192 | |
193 | /* QEMU specific */ |
194 | DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, |
195 | TCG_OPF_NOT_PRESENT) |
196 | DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) |
197 | DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) |
198 | DEF(goto_ptr, 0, 1, 0, |
199 | TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr)) |
200 | |
201 | DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, |
202 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
203 | DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, |
204 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
205 | DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, |
206 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) |
207 | DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, |
208 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) |
209 | |
210 | /* Host vector support. */ |
211 | |
212 | #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) |
213 | |
214 | DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) |
215 | DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) |
216 | |
217 | DEF(dup_vec, 1, 1, 0, IMPLVEC) |
218 | DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) |
219 | |
220 | DEF(ld_vec, 1, 1, 1, IMPLVEC) |
221 | DEF(st_vec, 0, 2, 1, IMPLVEC) |
222 | DEF(dupm_vec, 1, 1, 1, IMPLVEC) |
223 | |
224 | DEF(add_vec, 1, 2, 0, IMPLVEC) |
225 | DEF(sub_vec, 1, 2, 0, IMPLVEC) |
226 | DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) |
227 | DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) |
228 | DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) |
229 | DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) |
230 | DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) |
231 | DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) |
232 | DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) |
233 | DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) |
234 | DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) |
235 | DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) |
236 | DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) |
237 | |
238 | DEF(and_vec, 1, 2, 0, IMPLVEC) |
239 | DEF(or_vec, 1, 2, 0, IMPLVEC) |
240 | DEF(xor_vec, 1, 2, 0, IMPLVEC) |
241 | DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec)) |
242 | DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec)) |
243 | DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec)) |
244 | |
245 | DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) |
246 | DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) |
247 | DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) |
248 | |
249 | DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) |
250 | DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) |
251 | DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) |
252 | |
253 | DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) |
254 | DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) |
255 | DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) |
256 | |
257 | DEF(cmp_vec, 1, 2, 1, IMPLVEC) |
258 | |
259 | DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) |
260 | DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) |
261 | |
262 | DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) |
263 | |
264 | #if TCG_TARGET_MAYBE_vec |
265 | #include "tcg-target.opc.h" |
266 | #endif |
267 | |
268 | #undef TLADDR_ARGS |
269 | #undef DATA64_ARGS |
270 | #undef IMPL |
271 | #undef IMPL64 |
272 | #undef IMPLVEC |
273 | #undef DEF |
274 | |