1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25/*
26 * DEF(name, oargs, iargs, cargs, flags)
27 */
28
29/* predefined ops */
30DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
31DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
32
33/* variable number of parameters */
34DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
35
36DEF(br, 0, 0, 1, TCG_OPF_BB_END)
37
38#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
39#if TCG_TARGET_REG_BITS == 32
40# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
41#else
42# define IMPL64 TCG_OPF_64BIT
43#endif
44
45DEF(mb, 0, 0, 1, 0)
46
47DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
48DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
49DEF(setcond_i32, 1, 2, 1, 0)
50DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
51/* load/store */
52DEF(ld8u_i32, 1, 1, 1, 0)
53DEF(ld8s_i32, 1, 1, 1, 0)
54DEF(ld16u_i32, 1, 1, 1, 0)
55DEF(ld16s_i32, 1, 1, 1, 0)
56DEF(ld_i32, 1, 1, 1, 0)
57DEF(st8_i32, 0, 2, 1, 0)
58DEF(st16_i32, 0, 2, 1, 0)
59DEF(st_i32, 0, 2, 1, 0)
60/* arith */
61DEF(add_i32, 1, 2, 0, 0)
62DEF(sub_i32, 1, 2, 0, 0)
63DEF(mul_i32, 1, 2, 0, 0)
64DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
65DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
66DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
67DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
68DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
69DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
70DEF(and_i32, 1, 2, 0, 0)
71DEF(or_i32, 1, 2, 0, 0)
72DEF(xor_i32, 1, 2, 0, 0)
73/* shifts/rotates */
74DEF(shl_i32, 1, 2, 0, 0)
75DEF(shr_i32, 1, 2, 0, 0)
76DEF(sar_i32, 1, 2, 0, 0)
77DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
78DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
79DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
80DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
81DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
82DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
83
84DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
85
86DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
87DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
88DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
89DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
90DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
91DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
92DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
93DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
94
95DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
96DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
97DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
98DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
99DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
100DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
101DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
102DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
103DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
104DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
105DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
106DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
107DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
108DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
109DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
110DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
111
112DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
113DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
114DEF(setcond_i64, 1, 2, 1, IMPL64)
115DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
116/* load/store */
117DEF(ld8u_i64, 1, 1, 1, IMPL64)
118DEF(ld8s_i64, 1, 1, 1, IMPL64)
119DEF(ld16u_i64, 1, 1, 1, IMPL64)
120DEF(ld16s_i64, 1, 1, 1, IMPL64)
121DEF(ld32u_i64, 1, 1, 1, IMPL64)
122DEF(ld32s_i64, 1, 1, 1, IMPL64)
123DEF(ld_i64, 1, 1, 1, IMPL64)
124DEF(st8_i64, 0, 2, 1, IMPL64)
125DEF(st16_i64, 0, 2, 1, IMPL64)
126DEF(st32_i64, 0, 2, 1, IMPL64)
127DEF(st_i64, 0, 2, 1, IMPL64)
128/* arith */
129DEF(add_i64, 1, 2, 0, IMPL64)
130DEF(sub_i64, 1, 2, 0, IMPL64)
131DEF(mul_i64, 1, 2, 0, IMPL64)
132DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
133DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
134DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
135DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
136DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
137DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
138DEF(and_i64, 1, 2, 0, IMPL64)
139DEF(or_i64, 1, 2, 0, IMPL64)
140DEF(xor_i64, 1, 2, 0, IMPL64)
141/* shifts/rotates */
142DEF(shl_i64, 1, 2, 0, IMPL64)
143DEF(shr_i64, 1, 2, 0, IMPL64)
144DEF(sar_i64, 1, 2, 0, IMPL64)
145DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
146DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
147DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
148DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
149DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
150DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
151
152/* size changing ops */
153DEF(ext_i32_i64, 1, 1, 0, IMPL64)
154DEF(extu_i32_i64, 1, 1, 0, IMPL64)
155DEF(extrl_i64_i32, 1, 1, 0,
156 IMPL(TCG_TARGET_HAS_extrl_i64_i32)
157 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
158DEF(extrh_i64_i32, 1, 1, 0,
159 IMPL(TCG_TARGET_HAS_extrh_i64_i32)
160 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
161
162DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
163DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
164DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
165DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
166DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
167DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
168DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
169DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
170DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
171DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
172DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
173DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
174DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
175DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
176DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
177DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
178DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
179DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
180DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
181DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
182
183DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
184DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
185DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
186DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
187DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
188DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
189
190#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
191#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
192
193/* QEMU specific */
194DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
195 TCG_OPF_NOT_PRESENT)
196DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
197DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
198DEF(goto_ptr, 0, 1, 0,
199 TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr))
200
201DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
202 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
203DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
204 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
205DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
206 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
207DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
208 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
209
210/* Host vector support. */
211
212#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
213
214DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
215DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
216
217DEF(dup_vec, 1, 1, 0, IMPLVEC)
218DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
219
220DEF(ld_vec, 1, 1, 1, IMPLVEC)
221DEF(st_vec, 0, 2, 1, IMPLVEC)
222DEF(dupm_vec, 1, 1, 1, IMPLVEC)
223
224DEF(add_vec, 1, 2, 0, IMPLVEC)
225DEF(sub_vec, 1, 2, 0, IMPLVEC)
226DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
227DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
228DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
229DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
230DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
231DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
232DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
233DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
234DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
235DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
236DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
237
238DEF(and_vec, 1, 2, 0, IMPLVEC)
239DEF(or_vec, 1, 2, 0, IMPLVEC)
240DEF(xor_vec, 1, 2, 0, IMPLVEC)
241DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
242DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
243DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
244
245DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
246DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
247DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
248
249DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
250DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
251DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
252
253DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
254DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
255DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
256
257DEF(cmp_vec, 1, 2, 1, IMPLVEC)
258
259DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
260DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
261
262DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
263
264#if TCG_TARGET_MAYBE_vec
265#include "tcg-target.opc.h"
266#endif
267
268#undef TLADDR_ARGS
269#undef DATA64_ARGS
270#undef IMPL
271#undef IMPL64
272#undef IMPLVEC
273#undef DEF
274