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40
41#ifndef QGLOBAL_H
42# include <QtCore/qglobal.h>
43#endif
44
45#ifndef QPROCESSORDETECTION_H
46#define QPROCESSORDETECTION_H
47
48/*
49 This file uses preprocessor #defines to set various Q_PROCESSOR_* #defines
50 based on the following patterns:
51
52 Q_PROCESSOR_{FAMILY}
53 Q_PROCESSOR_{FAMILY}_{VARIANT}
54 Q_PROCESSOR_{FAMILY}_{REVISION}
55
56 The first is always defined. Defines for the various revisions/variants are
57 optional and usually dependent on how the compiler was invoked. Variants
58 that are a superset of another should have a define for the superset.
59
60 In addition to the processor family, variants, and revisions, we also set
61 Q_BYTE_ORDER appropriately for the target processor. For bi-endian
62 processors, we try to auto-detect the byte order using the __BIG_ENDIAN__,
63 __LITTLE_ENDIAN__, or __BYTE_ORDER__ preprocessor macros.
64
65 Note: when adding support for new processors, be sure to update
66 config.tests/arch/arch.cpp to ensure that configure can detect the target
67 and host architectures.
68*/
69
70/* Machine byte-order, reuse preprocessor provided macros when available */
71#if defined(__ORDER_BIG_ENDIAN__)
72# define Q_BIG_ENDIAN __ORDER_BIG_ENDIAN__
73#else
74# define Q_BIG_ENDIAN 4321
75#endif
76#if defined(__ORDER_LITTLE_ENDIAN__)
77# define Q_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
78#else
79# define Q_LITTLE_ENDIAN 1234
80#endif
81
82/*
83 Alpha family, no revisions or variants
84
85 Alpha is bi-endian, use endianness auto-detection implemented below.
86*/
87// #elif defined(__alpha__) || defined(_M_ALPHA)
88// # define Q_PROCESSOR_ALPHA
89// Q_BYTE_ORDER not defined, use endianness auto-detection
90
91/*
92 ARM family, known revisions: V5, V6, V7, V8
93
94 ARM is bi-endian, detect using __ARMEL__ or __ARMEB__, falling back to
95 auto-detection implemented below.
96*/
97#if defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(_M_ARM64) || defined(__aarch64__) || defined(__ARM64__)
98# if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
99# define Q_PROCESSOR_ARM_64
100# define Q_PROCESSOR_WORDSIZE 8
101# else
102# define Q_PROCESSOR_ARM_32
103# endif
104# if defined(__ARM_ARCH) && __ARM_ARCH > 1
105# define Q_PROCESSOR_ARM __ARM_ARCH
106# elif defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM > 1
107# define Q_PROCESSOR_ARM __TARGET_ARCH_ARM
108# elif defined(_M_ARM) && _M_ARM > 1
109# define Q_PROCESSOR_ARM _M_ARM
110# elif defined(__ARM64_ARCH_8__) \
111 || defined(__aarch64__) \
112 || defined(__ARMv8__) \
113 || defined(__ARMv8_A__) \
114 || defined(_M_ARM64)
115# define Q_PROCESSOR_ARM 8
116# elif defined(__ARM_ARCH_7__) \
117 || defined(__ARM_ARCH_7A__) \
118 || defined(__ARM_ARCH_7R__) \
119 || defined(__ARM_ARCH_7M__) \
120 || defined(__ARM_ARCH_7S__) \
121 || defined(_ARM_ARCH_7) \
122 || defined(__CORE_CORTEXA__)
123# define Q_PROCESSOR_ARM 7
124# elif defined(__ARM_ARCH_6__) \
125 || defined(__ARM_ARCH_6J__) \
126 || defined(__ARM_ARCH_6T2__) \
127 || defined(__ARM_ARCH_6Z__) \
128 || defined(__ARM_ARCH_6K__) \
129 || defined(__ARM_ARCH_6ZK__) \
130 || defined(__ARM_ARCH_6M__)
131# define Q_PROCESSOR_ARM 6
132# elif defined(__ARM_ARCH_5TEJ__) \
133 || defined(__ARM_ARCH_5TE__)
134# define Q_PROCESSOR_ARM 5
135# elif defined(__ARM_ARCH_4T__)
136# define Q_PROCESSOR_ARM 4
137# else
138# define Q_PROCESSOR_ARM 0
139# endif
140# if Q_PROCESSOR_ARM >= 8
141# define Q_PROCESSOR_ARM_V8
142# endif
143# if Q_PROCESSOR_ARM >= 7
144# define Q_PROCESSOR_ARM_V7
145# endif
146# if Q_PROCESSOR_ARM >= 6
147# define Q_PROCESSOR_ARM_V6
148# endif
149# if Q_PROCESSOR_ARM >= 5
150# define Q_PROCESSOR_ARM_V5
151# endif
152# if Q_PROCESSOR_ARM >= 4
153# define Q_PROCESSOR_ARM_V4
154# else
155# error "ARM architecture too old"
156# endif
157# if defined(__ARMEL__) || defined(_M_ARM64)
158# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
159# elif defined(__ARMEB__)
160# define Q_BYTE_ORDER Q_BIG_ENDIAN
161# else
162// Q_BYTE_ORDER not defined, use endianness auto-detection
163#endif
164
165/*
166 AVR32 family, no revisions or variants
167
168 AVR32 is big-endian.
169*/
170// #elif defined(__avr32__)
171// # define Q_PROCESSOR_AVR32
172// # define Q_BYTE_ORDER Q_BIG_ENDIAN
173
174/*
175 Blackfin family, no revisions or variants
176
177 Blackfin is little-endian.
178*/
179// #elif defined(__bfin__)
180// # define Q_PROCESSOR_BLACKFIN
181// # define Q_BYTE_ORDER Q_LITTLE_ENDIAN
182
183/*
184 X86 family, known variants: 32- and 64-bit
185
186 X86 is little-endian.
187*/
188#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
189# define Q_PROCESSOR_X86_32
190# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
191# define Q_PROCESSOR_WORDSIZE 4
192
193/*
194 * We define Q_PROCESSOR_X86 == 6 for anything above a equivalent or better
195 * than a Pentium Pro (the processor whose architecture was called P6) or an
196 * Athlon.
197 *
198 * All processors since the Pentium III and the Athlon 4 have SSE support, so
199 * we use that to detect. That leaves the original Athlon, Pentium Pro and
200 * Pentium II.
201 */
202
203# if defined(_M_IX86)
204# define Q_PROCESSOR_X86 (_M_IX86/100)
205# elif defined(__i686__) || defined(__athlon__) || defined(__SSE__) || defined(__pentiumpro__)
206# define Q_PROCESSOR_X86 6
207# elif defined(__i586__) || defined(__k6__) || defined(__pentium__)
208# define Q_PROCESSOR_X86 5
209# elif defined(__i486__) || defined(__80486__)
210# define Q_PROCESSOR_X86 4
211# else
212# define Q_PROCESSOR_X86 3
213# endif
214
215#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
216# define Q_PROCESSOR_X86 6
217# define Q_PROCESSOR_X86_64
218# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
219# define Q_PROCESSOR_WORDSIZE 8
220
221/*
222 Itanium (IA-64) family, no revisions or variants
223
224 Itanium is bi-endian, use endianness auto-detection implemented below.
225*/
226#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
227# define Q_PROCESSOR_IA64
228# define Q_PROCESSOR_WORDSIZE 8
229// Q_BYTE_ORDER not defined, use endianness auto-detection
230
231/*
232 MIPS family, known revisions: I, II, III, IV, 32, 64
233
234 MIPS is bi-endian, use endianness auto-detection implemented below.
235*/
236#elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
237# define Q_PROCESSOR_MIPS
238# if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
239# define Q_PROCESSOR_MIPS_I
240# endif
241# if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
242# define Q_PROCESSOR_MIPS_II
243# endif
244# if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
245# define Q_PROCESSOR_MIPS_III
246# endif
247# if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
248# define Q_PROCESSOR_MIPS_IV
249# endif
250# if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
251# define Q_PROCESSOR_MIPS_V
252# endif
253# if defined(_MIPS_ARCH_MIPS32) || defined(__mips32) || (defined(__mips) && __mips - 0 >= 32)
254# define Q_PROCESSOR_MIPS_32
255# endif
256# if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
257# define Q_PROCESSOR_MIPS_64
258# define Q_PROCESSOR_WORDSIZE 8
259# endif
260# if defined(__MIPSEL__)
261# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
262# elif defined(__MIPSEB__)
263# define Q_BYTE_ORDER Q_BIG_ENDIAN
264# else
265// Q_BYTE_ORDER not defined, use endianness auto-detection
266# endif
267
268/*
269 Power family, known variants: 32- and 64-bit
270
271 There are many more known variants/revisions that we do not handle/detect.
272 See http://en.wikipedia.org/wiki/Power_Architecture
273 and http://en.wikipedia.org/wiki/File:PowerISA-evolution.svg
274
275 Power is bi-endian, use endianness auto-detection implemented below.
276*/
277#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
278 || defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC) \
279 || defined(_M_MPPC) || defined(_M_PPC)
280# define Q_PROCESSOR_POWER
281# if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
282# define Q_PROCESSOR_POWER_64
283# define Q_PROCESSOR_WORDSIZE 8
284# else
285# define Q_PROCESSOR_POWER_32
286# endif
287// Q_BYTE_ORDER not defined, use endianness auto-detection
288
289/*
290 RISC-V family, known variants: 32- and 64-bit
291
292 RISC-V is little-endian.
293*/
294#elif defined(__riscv)
295# define Q_PROCESSOR_RISCV
296# if __riscv_xlen == 64
297# define Q_PROCESSOR_RISCV_64
298# else
299# define Q_PROCESSOR_RISCV_32
300# endif
301# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
302
303/*
304 S390 family, known variant: S390X (64-bit)
305
306 S390 is big-endian.
307*/
308#elif defined(__s390__)
309# define Q_PROCESSOR_S390
310# if defined(__s390x__)
311# define Q_PROCESSOR_S390_X
312# endif
313# define Q_BYTE_ORDER Q_BIG_ENDIAN
314
315/*
316 SuperH family, optional revision: SH-4A
317
318 SuperH is bi-endian, use endianness auto-detection implemented below.
319*/
320// #elif defined(__sh__)
321// # define Q_PROCESSOR_SH
322// # if defined(__sh4a__)
323// # define Q_PROCESSOR_SH_4A
324// # endif
325// Q_BYTE_ORDER not defined, use endianness auto-detection
326
327/*
328 SPARC family, optional revision: V9
329
330 SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
331 as the default byte order. Assume all SPARC systems are big-endian.
332*/
333#elif defined(__sparc__)
334# define Q_PROCESSOR_SPARC
335# if defined(__sparc_v9__)
336# define Q_PROCESSOR_SPARC_V9
337# endif
338# if defined(__sparc64__)
339# define Q_PROCESSOR_SPARC_64
340# endif
341# define Q_BYTE_ORDER Q_BIG_ENDIAN
342
343// -- Web Assembly --
344#elif defined(__EMSCRIPTEN__)
345# define Q_PROCESSOR_WASM
346# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
347# define Q_PROCESSOR_WORDSIZE 8
348#endif
349
350/*
351 NOTE:
352 GCC 4.6 added __BYTE_ORDER__, __ORDER_BIG_ENDIAN__, __ORDER_LITTLE_ENDIAN__
353 and __ORDER_PDP_ENDIAN__ in SVN r165881. If you are using GCC 4.6 or newer,
354 this code will properly detect your target byte order; if you are not, and
355 the __LITTLE_ENDIAN__ or __BIG_ENDIAN__ macros are not defined, then this
356 code will fail to detect the target byte order.
357*/
358// Some processors support either endian format, try to detect which we are using.
359#if !defined(Q_BYTE_ORDER)
360# if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
361// Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
362# define Q_BYTE_ORDER __BYTE_ORDER__
363# elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
364# define Q_BYTE_ORDER Q_BIG_ENDIAN
365# elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN) \
366 || defined(WINAPI_FAMILY) // WinRT is always little-endian according to MSDN.
367# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
368# else
369# error "Unable to determine byte order!"
370# endif
371#endif
372
373/*
374 Size of a pointer and the machine register size. We detect a 64-bit system by:
375 * GCC and compatible compilers (Clang, ICC on OS X and Windows) always define
376 __SIZEOF_POINTER__. This catches all known cases of ILP32 builds on 64-bit
377 processors.
378 * Most other Unix compilers define __LP64__ or _LP64 on 64-bit mode
379 (Long and Pointer 64-bit)
380 * If Q_PROCESSOR_WORDSIZE was defined above, it's assumed to match the pointer
381 size.
382 Otherwise, we assume to be 32-bit and then check in qglobal.cpp that it is right.
383*/
384
385#if defined __SIZEOF_POINTER__
386# define QT_POINTER_SIZE __SIZEOF_POINTER__
387#elif defined(__LP64__) || defined(_LP64)
388# define QT_POINTER_SIZE 8
389#elif defined(Q_PROCESSOR_WORDSIZE)
390# define QT_POINTER_SIZE Q_PROCESSOR_WORDSIZE
391#else
392# define QT_POINTER_SIZE 4
393#endif
394
395/*
396 Define Q_PROCESSOR_WORDSIZE to be the size of the machine's word (usually,
397 the size of the register). On some architectures where a pointer could be
398 smaller than the register, the macro is defined above.
399
400 Falls back to QT_POINTER_SIZE if not set explicitly for the platform.
401*/
402#ifndef Q_PROCESSOR_WORDSIZE
403# define Q_PROCESSOR_WORDSIZE QT_POINTER_SIZE
404#endif
405
406
407#endif // QPROCESSORDETECTION_H
408