1 | /*****************************************************************************\ |
2 | Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. |
3 | This file is licensed under the Snes9x License. |
4 | For further information, consult the LICENSE file in the root directory. |
5 | \*****************************************************************************/ |
6 | |
7 | #ifndef _GETSET_H_ |
8 | #define _GETSET_H_ |
9 | |
10 | #include "cpuexec.h" |
11 | #include "dsp.h" |
12 | #include "sa1.h" |
13 | #include "spc7110.h" |
14 | #include "c4.h" |
15 | #include "obc1.h" |
16 | #include "seta.h" |
17 | #include "bsx.h" |
18 | #include "msu1.h" |
19 | |
20 | #define addCyclesInMemoryAccess \ |
21 | if (!CPU.InDMAorHDMA) \ |
22 | { \ |
23 | CPU.Cycles += speed; \ |
24 | while (CPU.Cycles >= CPU.NextEvent) \ |
25 | S9xDoHEventProcessing(); \ |
26 | } |
27 | |
28 | #define addCyclesInMemoryAccess_x2 \ |
29 | if (!CPU.InDMAorHDMA) \ |
30 | { \ |
31 | CPU.Cycles += speed << 1; \ |
32 | while (CPU.Cycles >= CPU.NextEvent) \ |
33 | S9xDoHEventProcessing(); \ |
34 | } |
35 | |
36 | extern uint8 OpenBus; |
37 | |
38 | static inline int32 memory_speed (uint32 address) |
39 | { |
40 | if (address & 0x408000) |
41 | { |
42 | if (address & 0x800000) |
43 | return (CPU.FastROMSpeed); |
44 | |
45 | return (SLOW_ONE_CYCLE); |
46 | } |
47 | |
48 | if ((address + 0x6000) & 0x4000) |
49 | return (SLOW_ONE_CYCLE); |
50 | |
51 | if ((address - 0x4000) & 0x7e00) |
52 | return (ONE_CYCLE); |
53 | |
54 | return (TWO_CYCLES); |
55 | } |
56 | |
57 | inline uint8 S9xGetByte (uint32 Address) |
58 | { |
59 | int block = (Address & 0xffffff) >> MEMMAP_SHIFT; |
60 | uint8 *GetAddress = Memory.Map[block]; |
61 | int32 speed = memory_speed(Address); |
62 | uint8 byte; |
63 | |
64 | if (GetAddress >= (uint8 *) CMemory::MAP_LAST) |
65 | { |
66 | byte = *(GetAddress + (Address & 0xffff)); |
67 | addCyclesInMemoryAccess; |
68 | return (byte); |
69 | } |
70 | |
71 | switch ((pint) GetAddress) |
72 | { |
73 | case CMemory::MAP_CPU: |
74 | byte = S9xGetCPU(Address & 0xffff); |
75 | addCyclesInMemoryAccess; |
76 | return (byte); |
77 | |
78 | case CMemory::MAP_PPU: |
79 | if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100) |
80 | return (OpenBus); |
81 | |
82 | byte = S9xGetPPU(Address & 0xffff); |
83 | addCyclesInMemoryAccess; |
84 | return (byte); |
85 | |
86 | case CMemory::MAP_LOROM_SRAM: |
87 | case CMemory::MAP_SA1RAM: |
88 | // Address & 0x7fff : offset into bank |
89 | // Address & 0xff0000 : bank |
90 | // bank >> 1 | offset : SRAM address, unbound |
91 | // unbound & SRAMMask : SRAM offset |
92 | byte = *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)); |
93 | addCyclesInMemoryAccess; |
94 | return (byte); |
95 | |
96 | case CMemory::MAP_LOROM_SRAM_B: |
97 | byte = *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)); |
98 | addCyclesInMemoryAccess; |
99 | return (byte); |
100 | |
101 | case CMemory::MAP_HIROM_SRAM: |
102 | case CMemory::MAP_RONLY_SRAM: |
103 | byte = *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)); |
104 | addCyclesInMemoryAccess; |
105 | return (byte); |
106 | |
107 | case CMemory::MAP_BWRAM: |
108 | byte = *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)); |
109 | addCyclesInMemoryAccess; |
110 | return (byte); |
111 | |
112 | case CMemory::MAP_DSP: |
113 | byte = S9xGetDSP(Address & 0xffff); |
114 | addCyclesInMemoryAccess; |
115 | return (byte); |
116 | |
117 | case CMemory::MAP_SPC7110_ROM: |
118 | byte = S9xGetSPC7110Byte(Address); |
119 | addCyclesInMemoryAccess; |
120 | return (byte); |
121 | |
122 | case CMemory::MAP_SPC7110_DRAM: |
123 | byte = S9xGetSPC7110(0x4800); |
124 | addCyclesInMemoryAccess; |
125 | return (byte); |
126 | |
127 | case CMemory::MAP_C4: |
128 | byte = S9xGetC4(Address & 0xffff); |
129 | addCyclesInMemoryAccess; |
130 | return (byte); |
131 | |
132 | case CMemory::MAP_OBC_RAM: |
133 | byte = S9xGetOBC1(Address & 0xffff); |
134 | addCyclesInMemoryAccess; |
135 | return (byte); |
136 | |
137 | case CMemory::MAP_SETA_DSP: |
138 | byte = S9xGetSetaDSP(Address); |
139 | addCyclesInMemoryAccess; |
140 | return (byte); |
141 | |
142 | case CMemory::MAP_SETA_RISC: |
143 | byte = S9xGetST018(Address); |
144 | addCyclesInMemoryAccess; |
145 | return (byte); |
146 | |
147 | case CMemory::MAP_BSX: |
148 | byte = S9xGetBSX(Address); |
149 | addCyclesInMemoryAccess; |
150 | return (byte); |
151 | |
152 | case CMemory::MAP_NONE: |
153 | default: |
154 | byte = OpenBus; |
155 | addCyclesInMemoryAccess; |
156 | return (byte); |
157 | } |
158 | } |
159 | |
160 | inline uint16 S9xGetWord (uint32 Address, enum s9xwrap_t w = WRAP_NONE) |
161 | { |
162 | uint16 word; |
163 | |
164 | uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff)); |
165 | if ((Address & mask) == mask) |
166 | { |
167 | PC_t a; |
168 | |
169 | word = OpenBus = S9xGetByte(Address); |
170 | |
171 | switch (w) |
172 | { |
173 | case WRAP_PAGE: |
174 | a.xPBPC = Address; |
175 | a.B.xPCl++; |
176 | return (word | (S9xGetByte(a.xPBPC) << 8)); |
177 | |
178 | case WRAP_BANK: |
179 | a.xPBPC = Address; |
180 | a.W.xPC++; |
181 | return (word | (S9xGetByte(a.xPBPC) << 8)); |
182 | |
183 | case WRAP_NONE: |
184 | default: |
185 | return (word | (S9xGetByte(Address + 1) << 8)); |
186 | } |
187 | } |
188 | |
189 | int block = (Address & 0xffffff) >> MEMMAP_SHIFT; |
190 | uint8 *GetAddress = Memory.Map[block]; |
191 | int32 speed = memory_speed(Address); |
192 | |
193 | if (GetAddress >= (uint8 *) CMemory::MAP_LAST) |
194 | { |
195 | word = READ_WORD(GetAddress + (Address & 0xffff)); |
196 | addCyclesInMemoryAccess_x2; |
197 | return (word); |
198 | } |
199 | |
200 | switch ((pint) GetAddress) |
201 | { |
202 | case CMemory::MAP_CPU: |
203 | word = S9xGetCPU(Address & 0xffff); |
204 | addCyclesInMemoryAccess; |
205 | word |= S9xGetCPU((Address + 1) & 0xffff) << 8; |
206 | addCyclesInMemoryAccess; |
207 | return (word); |
208 | |
209 | case CMemory::MAP_PPU: |
210 | if (CPU.InDMAorHDMA) |
211 | { |
212 | word = OpenBus = S9xGetByte(Address); |
213 | return (word | (S9xGetByte(Address + 1) << 8)); |
214 | } |
215 | |
216 | word = S9xGetPPU(Address & 0xffff); |
217 | addCyclesInMemoryAccess; |
218 | word |= S9xGetPPU((Address + 1) & 0xffff) << 8; |
219 | addCyclesInMemoryAccess; |
220 | return (word); |
221 | |
222 | case CMemory::MAP_LOROM_SRAM: |
223 | case CMemory::MAP_SA1RAM: |
224 | if (Memory.SRAMMask >= MEMMAP_MASK) |
225 | word = READ_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)); |
226 | else |
227 | word = (*(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask))) | |
228 | ((*(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask))) << 8); |
229 | addCyclesInMemoryAccess_x2; |
230 | return (word); |
231 | |
232 | case CMemory::MAP_LOROM_SRAM_B: |
233 | if (Multi.sramMaskB >= MEMMAP_MASK) |
234 | word = READ_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)); |
235 | else |
236 | word = (*(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB))) | |
237 | ((*(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB))) << 8); |
238 | addCyclesInMemoryAccess_x2; |
239 | return (word); |
240 | |
241 | case CMemory::MAP_HIROM_SRAM: |
242 | case CMemory::MAP_RONLY_SRAM: |
243 | if (Memory.SRAMMask >= MEMMAP_MASK) |
244 | word = READ_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)); |
245 | else |
246 | word = (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) | |
247 | (*(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) << 8)); |
248 | addCyclesInMemoryAccess_x2; |
249 | return (word); |
250 | |
251 | case CMemory::MAP_BWRAM: |
252 | word = READ_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)); |
253 | addCyclesInMemoryAccess_x2; |
254 | return (word); |
255 | |
256 | case CMemory::MAP_DSP: |
257 | word = S9xGetDSP(Address & 0xffff); |
258 | addCyclesInMemoryAccess; |
259 | word |= S9xGetDSP((Address + 1) & 0xffff) << 8; |
260 | addCyclesInMemoryAccess; |
261 | return (word); |
262 | |
263 | case CMemory::MAP_SPC7110_ROM: |
264 | word = S9xGetSPC7110Byte(Address); |
265 | addCyclesInMemoryAccess; |
266 | word |= S9xGetSPC7110Byte(Address + 1) << 8; |
267 | addCyclesInMemoryAccess; |
268 | return (word); |
269 | |
270 | case CMemory::MAP_SPC7110_DRAM: |
271 | word = S9xGetSPC7110(0x4800); |
272 | addCyclesInMemoryAccess; |
273 | word |= S9xGetSPC7110(0x4800) << 8; |
274 | addCyclesInMemoryAccess; |
275 | return (word); |
276 | |
277 | case CMemory::MAP_C4: |
278 | word = S9xGetC4(Address & 0xffff); |
279 | addCyclesInMemoryAccess; |
280 | word |= S9xGetC4((Address + 1) & 0xffff) << 8; |
281 | addCyclesInMemoryAccess; |
282 | return (word); |
283 | |
284 | case CMemory::MAP_OBC_RAM: |
285 | word = S9xGetOBC1(Address & 0xffff); |
286 | addCyclesInMemoryAccess; |
287 | word |= S9xGetOBC1((Address + 1) & 0xffff) << 8; |
288 | addCyclesInMemoryAccess; |
289 | return (word); |
290 | |
291 | case CMemory::MAP_SETA_DSP: |
292 | word = S9xGetSetaDSP(Address); |
293 | addCyclesInMemoryAccess; |
294 | word |= S9xGetSetaDSP(Address + 1) << 8; |
295 | addCyclesInMemoryAccess; |
296 | return (word); |
297 | |
298 | case CMemory::MAP_SETA_RISC: |
299 | word = S9xGetST018(Address); |
300 | addCyclesInMemoryAccess; |
301 | word |= S9xGetST018(Address + 1) << 8; |
302 | addCyclesInMemoryAccess; |
303 | return (word); |
304 | |
305 | case CMemory::MAP_BSX: |
306 | word = S9xGetBSX(Address); |
307 | addCyclesInMemoryAccess; |
308 | word |= S9xGetBSX(Address + 1) << 8; |
309 | addCyclesInMemoryAccess; |
310 | return (word); |
311 | |
312 | case CMemory::MAP_NONE: |
313 | default: |
314 | word = OpenBus | (OpenBus << 8); |
315 | addCyclesInMemoryAccess_x2; |
316 | return (word); |
317 | } |
318 | } |
319 | |
320 | inline void S9xSetByte (uint8 Byte, uint32 Address) |
321 | { |
322 | int block = (Address & 0xffffff) >> MEMMAP_SHIFT; |
323 | uint8 *SetAddress = Memory.WriteMap[block]; |
324 | int32 speed = memory_speed(Address); |
325 | |
326 | if (SetAddress >= (uint8 *) CMemory::MAP_LAST) |
327 | { |
328 | *(SetAddress + (Address & 0xffff)) = Byte; |
329 | addCyclesInMemoryAccess; |
330 | return; |
331 | } |
332 | |
333 | switch ((pint) SetAddress) |
334 | { |
335 | case CMemory::MAP_CPU: |
336 | S9xSetCPU(Byte, Address & 0xffff); |
337 | addCyclesInMemoryAccess; |
338 | return; |
339 | |
340 | case CMemory::MAP_PPU: |
341 | if (CPU.InDMAorHDMA && (Address & 0xff00) == 0x2100) |
342 | return; |
343 | |
344 | S9xSetPPU(Byte, Address & 0xffff); |
345 | addCyclesInMemoryAccess; |
346 | return; |
347 | |
348 | case CMemory::MAP_LOROM_SRAM: |
349 | if (Memory.SRAMMask) |
350 | { |
351 | *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = Byte; |
352 | CPU.SRAMModified = TRUE; |
353 | } |
354 | |
355 | addCyclesInMemoryAccess; |
356 | return; |
357 | |
358 | case CMemory::MAP_LOROM_SRAM_B: |
359 | if (Multi.sramMaskB) |
360 | { |
361 | *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = Byte; |
362 | CPU.SRAMModified = TRUE; |
363 | } |
364 | |
365 | addCyclesInMemoryAccess; |
366 | return; |
367 | |
368 | case CMemory::MAP_HIROM_SRAM: |
369 | if (Memory.SRAMMask) |
370 | { |
371 | *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = Byte; |
372 | CPU.SRAMModified = TRUE; |
373 | } |
374 | |
375 | addCyclesInMemoryAccess; |
376 | return; |
377 | |
378 | case CMemory::MAP_BWRAM: |
379 | *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte; |
380 | CPU.SRAMModified = TRUE; |
381 | addCyclesInMemoryAccess; |
382 | return; |
383 | |
384 | case CMemory::MAP_SA1RAM: |
385 | *(Memory.SRAM + (Address & 0xffff)) = Byte; |
386 | addCyclesInMemoryAccess; |
387 | return; |
388 | |
389 | case CMemory::MAP_DSP: |
390 | S9xSetDSP(Byte, Address & 0xffff); |
391 | addCyclesInMemoryAccess; |
392 | return; |
393 | |
394 | case CMemory::MAP_C4: |
395 | S9xSetC4(Byte, Address & 0xffff); |
396 | addCyclesInMemoryAccess; |
397 | return; |
398 | |
399 | case CMemory::MAP_OBC_RAM: |
400 | S9xSetOBC1(Byte, Address & 0xffff); |
401 | addCyclesInMemoryAccess; |
402 | return; |
403 | |
404 | case CMemory::MAP_SETA_DSP: |
405 | S9xSetSetaDSP(Byte, Address); |
406 | addCyclesInMemoryAccess; |
407 | return; |
408 | |
409 | case CMemory::MAP_SETA_RISC: |
410 | S9xSetST018(Byte, Address); |
411 | addCyclesInMemoryAccess; |
412 | return; |
413 | |
414 | case CMemory::MAP_BSX: |
415 | S9xSetBSX(Byte, Address); |
416 | addCyclesInMemoryAccess; |
417 | return; |
418 | |
419 | case CMemory::MAP_NONE: |
420 | default: |
421 | addCyclesInMemoryAccess; |
422 | return; |
423 | } |
424 | } |
425 | |
426 | inline void S9xSetWord (uint16 Word, uint32 Address, enum s9xwrap_t w = WRAP_NONE, enum s9xwriteorder_t o = WRITE_01) |
427 | { |
428 | uint32 mask = MEMMAP_MASK & (w == WRAP_PAGE ? 0xff : (w == WRAP_BANK ? 0xffff : 0xffffff)); |
429 | if ((Address & mask) == mask) |
430 | { |
431 | PC_t a; |
432 | |
433 | if (!o) |
434 | S9xSetByte((uint8) Word, Address); |
435 | |
436 | switch (w) |
437 | { |
438 | case WRAP_PAGE: |
439 | a.xPBPC = Address; |
440 | a.B.xPCl++; |
441 | S9xSetByte(Word >> 8, a.xPBPC); |
442 | break; |
443 | |
444 | case WRAP_BANK: |
445 | a.xPBPC = Address; |
446 | a.W.xPC++; |
447 | S9xSetByte(Word >> 8, a.xPBPC); |
448 | break; |
449 | |
450 | case WRAP_NONE: |
451 | default: |
452 | S9xSetByte(Word >> 8, Address + 1); |
453 | break; |
454 | } |
455 | |
456 | if (o) |
457 | S9xSetByte((uint8) Word, Address); |
458 | |
459 | return; |
460 | } |
461 | |
462 | int block = (Address & 0xffffff) >> MEMMAP_SHIFT; |
463 | uint8 *SetAddress = Memory.WriteMap[block]; |
464 | int32 speed = memory_speed(Address); |
465 | |
466 | if (SetAddress >= (uint8 *) CMemory::MAP_LAST) |
467 | { |
468 | WRITE_WORD(SetAddress + (Address & 0xffff), Word); |
469 | addCyclesInMemoryAccess_x2; |
470 | return; |
471 | } |
472 | |
473 | switch ((pint) SetAddress) |
474 | { |
475 | case CMemory::MAP_CPU: |
476 | if (o) |
477 | { |
478 | S9xSetCPU(Word >> 8, (Address + 1) & 0xffff); |
479 | addCyclesInMemoryAccess; |
480 | S9xSetCPU((uint8) Word, Address & 0xffff); |
481 | addCyclesInMemoryAccess; |
482 | return; |
483 | } |
484 | else |
485 | { |
486 | S9xSetCPU((uint8) Word, Address & 0xffff); |
487 | addCyclesInMemoryAccess; |
488 | S9xSetCPU(Word >> 8, (Address + 1) & 0xffff); |
489 | addCyclesInMemoryAccess; |
490 | return; |
491 | } |
492 | |
493 | case CMemory::MAP_PPU: |
494 | if (CPU.InDMAorHDMA) |
495 | { |
496 | if ((Address & 0xff00) != 0x2100) |
497 | S9xSetPPU((uint8) Word, Address & 0xffff); |
498 | if (((Address + 1) & 0xff00) != 0x2100) |
499 | S9xSetPPU(Word >> 8, (Address + 1) & 0xffff); |
500 | return; |
501 | } |
502 | |
503 | if (o) |
504 | { |
505 | S9xSetPPU(Word >> 8, (Address + 1) & 0xffff); |
506 | addCyclesInMemoryAccess; |
507 | S9xSetPPU((uint8) Word, Address & 0xffff); |
508 | addCyclesInMemoryAccess; |
509 | return; |
510 | } |
511 | else |
512 | { |
513 | S9xSetPPU((uint8) Word, Address & 0xffff); |
514 | addCyclesInMemoryAccess; |
515 | S9xSetPPU(Word >> 8, (Address + 1) & 0xffff); |
516 | addCyclesInMemoryAccess; |
517 | return; |
518 | } |
519 | |
520 | case CMemory::MAP_LOROM_SRAM: |
521 | if (Memory.SRAMMask) |
522 | { |
523 | if (Memory.SRAMMask >= MEMMAP_MASK) |
524 | WRITE_WORD(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask), Word); |
525 | else |
526 | { |
527 | *(Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)) = (uint8) Word; |
528 | *(Memory.SRAM + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Memory.SRAMMask)) = Word >> 8; |
529 | } |
530 | |
531 | CPU.SRAMModified = TRUE; |
532 | } |
533 | |
534 | addCyclesInMemoryAccess_x2; |
535 | return; |
536 | |
537 | case CMemory::MAP_LOROM_SRAM_B: |
538 | if (Multi.sramMaskB) |
539 | { |
540 | if (Multi.sramMaskB >= MEMMAP_MASK) |
541 | WRITE_WORD(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB), Word); |
542 | else |
543 | { |
544 | *(Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)) = (uint8) Word; |
545 | *(Multi.sramB + (((((Address + 1) & 0xff0000) >> 1) | ((Address + 1) & 0x7fff)) & Multi.sramMaskB)) = Word >> 8; |
546 | } |
547 | |
548 | CPU.SRAMModified = TRUE; |
549 | } |
550 | |
551 | addCyclesInMemoryAccess_x2; |
552 | return; |
553 | |
554 | case CMemory::MAP_HIROM_SRAM: |
555 | if (Memory.SRAMMask) |
556 | { |
557 | if (Memory.SRAMMask >= MEMMAP_MASK) |
558 | WRITE_WORD(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask), Word); |
559 | else |
560 | { |
561 | *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)) = (uint8) Word; |
562 | *(Memory.SRAM + ((((Address + 1) & 0x7fff) - 0x6000 + (((Address + 1) & 0xf0000) >> 3)) & Memory.SRAMMask)) = Word >> 8; |
563 | } |
564 | |
565 | CPU.SRAMModified = TRUE; |
566 | } |
567 | |
568 | addCyclesInMemoryAccess_x2; |
569 | return; |
570 | |
571 | case CMemory::MAP_BWRAM: |
572 | WRITE_WORD(Memory.BWRAM + ((Address & 0x7fff) - 0x6000), Word); |
573 | CPU.SRAMModified = TRUE; |
574 | addCyclesInMemoryAccess_x2; |
575 | return; |
576 | |
577 | case CMemory::MAP_SA1RAM: |
578 | WRITE_WORD(Memory.SRAM + (Address & 0xffff), Word); |
579 | addCyclesInMemoryAccess_x2; |
580 | return; |
581 | |
582 | case CMemory::MAP_DSP: |
583 | if (o) |
584 | { |
585 | S9xSetDSP(Word >> 8, (Address + 1) & 0xffff); |
586 | addCyclesInMemoryAccess; |
587 | S9xSetDSP((uint8) Word, Address & 0xffff); |
588 | addCyclesInMemoryAccess; |
589 | return; |
590 | } |
591 | else |
592 | { |
593 | S9xSetDSP((uint8) Word, Address & 0xffff); |
594 | addCyclesInMemoryAccess; |
595 | S9xSetDSP(Word >> 8, (Address + 1) & 0xffff); |
596 | addCyclesInMemoryAccess; |
597 | return; |
598 | } |
599 | |
600 | case CMemory::MAP_C4: |
601 | if (o) |
602 | { |
603 | S9xSetC4(Word >> 8, (Address + 1) & 0xffff); |
604 | addCyclesInMemoryAccess; |
605 | S9xSetC4((uint8) Word, Address & 0xffff); |
606 | addCyclesInMemoryAccess; |
607 | return; |
608 | } |
609 | else |
610 | { |
611 | S9xSetC4((uint8) Word, Address & 0xffff); |
612 | addCyclesInMemoryAccess; |
613 | S9xSetC4(Word >> 8, (Address + 1) & 0xffff); |
614 | addCyclesInMemoryAccess; |
615 | return; |
616 | } |
617 | |
618 | case CMemory::MAP_OBC_RAM: |
619 | if (o) |
620 | { |
621 | S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff); |
622 | addCyclesInMemoryAccess; |
623 | S9xSetOBC1((uint8) Word, Address & 0xffff); |
624 | addCyclesInMemoryAccess; |
625 | return; |
626 | } |
627 | else |
628 | { |
629 | S9xSetOBC1((uint8) Word, Address & 0xffff); |
630 | addCyclesInMemoryAccess; |
631 | S9xSetOBC1(Word >> 8, (Address + 1) & 0xffff); |
632 | addCyclesInMemoryAccess; |
633 | return; |
634 | } |
635 | |
636 | case CMemory::MAP_SETA_DSP: |
637 | if (o) |
638 | { |
639 | S9xSetSetaDSP(Word >> 8, Address + 1); |
640 | addCyclesInMemoryAccess; |
641 | S9xSetSetaDSP((uint8) Word, Address); |
642 | addCyclesInMemoryAccess; |
643 | return; |
644 | } |
645 | else |
646 | { |
647 | S9xSetSetaDSP((uint8) Word, Address); |
648 | addCyclesInMemoryAccess; |
649 | S9xSetSetaDSP(Word >> 8, Address + 1); |
650 | addCyclesInMemoryAccess; |
651 | return; |
652 | } |
653 | |
654 | case CMemory::MAP_SETA_RISC: |
655 | if (o) |
656 | { |
657 | S9xSetST018(Word >> 8, Address + 1); |
658 | addCyclesInMemoryAccess; |
659 | S9xSetST018((uint8) Word, Address); |
660 | addCyclesInMemoryAccess; |
661 | return; |
662 | } |
663 | else |
664 | { |
665 | S9xSetST018((uint8) Word, Address); |
666 | addCyclesInMemoryAccess; |
667 | S9xSetST018(Word >> 8, Address + 1); |
668 | addCyclesInMemoryAccess; |
669 | return; |
670 | } |
671 | |
672 | case CMemory::MAP_BSX: |
673 | if (o) |
674 | { |
675 | S9xSetBSX(Word >> 8, Address + 1); |
676 | addCyclesInMemoryAccess; |
677 | S9xSetBSX((uint8) Word, Address); |
678 | addCyclesInMemoryAccess; |
679 | return; |
680 | } |
681 | else |
682 | { |
683 | S9xSetBSX((uint8) Word, Address); |
684 | addCyclesInMemoryAccess; |
685 | S9xSetBSX(Word >> 8, Address + 1); |
686 | addCyclesInMemoryAccess; |
687 | return; |
688 | } |
689 | |
690 | case CMemory::MAP_NONE: |
691 | default: |
692 | addCyclesInMemoryAccess_x2; |
693 | return; |
694 | } |
695 | } |
696 | |
697 | inline void S9xSetPCBase (uint32 Address) |
698 | { |
699 | Registers.PBPC = Address & 0xffffff; |
700 | ICPU.ShiftedPB = Address & 0xff0000; |
701 | |
702 | uint8 *GetAddress = Memory.Map[(int)((Address & 0xffffff) >> MEMMAP_SHIFT)]; |
703 | |
704 | CPU.MemSpeed = memory_speed(Address); |
705 | CPU.MemSpeedx2 = CPU.MemSpeed << 1; |
706 | |
707 | if (GetAddress >= (uint8 *) CMemory::MAP_LAST) |
708 | { |
709 | CPU.PCBase = GetAddress; |
710 | return; |
711 | } |
712 | |
713 | switch ((pint) GetAddress) |
714 | { |
715 | case CMemory::MAP_LOROM_SRAM: |
716 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
717 | CPU.PCBase = NULL; |
718 | else |
719 | CPU.PCBase = Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff); |
720 | return; |
721 | |
722 | case CMemory::MAP_LOROM_SRAM_B: |
723 | if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK) |
724 | CPU.PCBase = NULL; |
725 | else |
726 | CPU.PCBase = Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff); |
727 | return; |
728 | |
729 | case CMemory::MAP_HIROM_SRAM: |
730 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
731 | CPU.PCBase = NULL; |
732 | else |
733 | CPU.PCBase = Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff); |
734 | return; |
735 | |
736 | case CMemory::MAP_BWRAM: |
737 | CPU.PCBase = Memory.BWRAM - 0x6000 - (Address & 0x8000); |
738 | return; |
739 | |
740 | case CMemory::MAP_SA1RAM: |
741 | CPU.PCBase = Memory.SRAM; |
742 | return; |
743 | |
744 | case CMemory::MAP_SPC7110_ROM: |
745 | CPU.PCBase = S9xGetBasePointerSPC7110(Address); |
746 | return; |
747 | |
748 | case CMemory::MAP_C4: |
749 | CPU.PCBase = S9xGetBasePointerC4(Address & 0xffff); |
750 | return; |
751 | |
752 | case CMemory::MAP_OBC_RAM: |
753 | CPU.PCBase = S9xGetBasePointerOBC1(Address & 0xffff); |
754 | return; |
755 | |
756 | case CMemory::MAP_BSX: |
757 | CPU.PCBase = S9xGetBasePointerBSX(Address); |
758 | return; |
759 | |
760 | case CMemory::MAP_NONE: |
761 | default: |
762 | CPU.PCBase = NULL; |
763 | return; |
764 | } |
765 | } |
766 | |
767 | inline uint8 * S9xGetBasePointer (uint32 Address) |
768 | { |
769 | uint8 *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT]; |
770 | |
771 | if (GetAddress >= (uint8 *) CMemory::MAP_LAST) |
772 | return (GetAddress); |
773 | |
774 | switch ((pint) GetAddress) |
775 | { |
776 | case CMemory::MAP_LOROM_SRAM: |
777 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
778 | return (NULL); |
779 | return (Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask) - (Address & 0xffff)); |
780 | |
781 | case CMemory::MAP_LOROM_SRAM_B: |
782 | if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK) |
783 | return (NULL); |
784 | return (Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB) - (Address & 0xffff)); |
785 | |
786 | case CMemory::MAP_HIROM_SRAM: |
787 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
788 | return (NULL); |
789 | return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask) - (Address & 0xffff)); |
790 | |
791 | case CMemory::MAP_BWRAM: |
792 | return (Memory.BWRAM - 0x6000 - (Address & 0x8000)); |
793 | |
794 | case CMemory::MAP_SA1RAM: |
795 | return (Memory.SRAM); |
796 | |
797 | case CMemory::MAP_SPC7110_ROM: |
798 | return (S9xGetBasePointerSPC7110(Address)); |
799 | |
800 | case CMemory::MAP_C4: |
801 | return (S9xGetBasePointerC4(Address & 0xffff)); |
802 | |
803 | case CMemory::MAP_OBC_RAM: |
804 | return (S9xGetBasePointerOBC1(Address & 0xffff)); |
805 | |
806 | case CMemory::MAP_NONE: |
807 | default: |
808 | return (NULL); |
809 | } |
810 | } |
811 | |
812 | inline uint8 * S9xGetMemPointer (uint32 Address) |
813 | { |
814 | uint8 *GetAddress = Memory.Map[(Address & 0xffffff) >> MEMMAP_SHIFT]; |
815 | |
816 | if (GetAddress >= (uint8 *) CMemory::MAP_LAST) |
817 | return (GetAddress + (Address & 0xffff)); |
818 | |
819 | switch ((pint) GetAddress) |
820 | { |
821 | case CMemory::MAP_LOROM_SRAM: |
822 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
823 | return (NULL); |
824 | return (Memory.SRAM + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Memory.SRAMMask)); |
825 | |
826 | case CMemory::MAP_LOROM_SRAM_B: |
827 | if ((Multi.sramMaskB & MEMMAP_MASK) != MEMMAP_MASK) |
828 | return (NULL); |
829 | return (Multi.sramB + ((((Address & 0xff0000) >> 1) | (Address & 0x7fff)) & Multi.sramMaskB)); |
830 | |
831 | case CMemory::MAP_HIROM_SRAM: |
832 | if ((Memory.SRAMMask & MEMMAP_MASK) != MEMMAP_MASK) |
833 | return (NULL); |
834 | return (Memory.SRAM + (((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) & Memory.SRAMMask)); |
835 | |
836 | case CMemory::MAP_BWRAM: |
837 | return (Memory.BWRAM - 0x6000 + (Address & 0x7fff)); |
838 | |
839 | case CMemory::MAP_SA1RAM: |
840 | return (Memory.SRAM + (Address & 0xffff)); |
841 | |
842 | case CMemory::MAP_SPC7110_ROM: |
843 | return (S9xGetBasePointerSPC7110(Address) + (Address & 0xffff)); |
844 | |
845 | case CMemory::MAP_C4: |
846 | return (S9xGetMemPointerC4(Address & 0xffff)); |
847 | |
848 | case CMemory::MAP_OBC_RAM: |
849 | return (S9xGetMemPointerOBC1(Address & 0xffff)); |
850 | |
851 | case CMemory::MAP_NONE: |
852 | default: |
853 | return (NULL); |
854 | } |
855 | } |
856 | |
857 | #endif |
858 | |