1/*
2 Copyright (c) 2005-2019 Intel Corporation
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#ifndef __TBBexample_graph_logicsim_tba_H
18#define __TBBexample_graph_logicsim_tba_H 1
19
20#include "one_bit_adder.h"
21
22class two_bit_adder : public composite_node< tuple< signal_t, signal_t, signal_t, signal_t, signal_t >,
23 tuple< signal_t, signal_t, signal_t > > {
24 graph& my_graph;
25 std::vector<one_bit_adder> two_adders;
26 typedef composite_node< tuple< signal_t, signal_t, signal_t, signal_t, signal_t >,
27 tuple< signal_t, signal_t, signal_t > > base_type;
28 public:
29 two_bit_adder(graph& g) : base_type(g), my_graph(g), two_adders(2, one_bit_adder(g)) {
30 make_connections();
31 set_up_composite();
32 }
33 two_bit_adder(const two_bit_adder& src) :
34 base_type(src.my_graph), my_graph(src.my_graph), two_adders(2, one_bit_adder(src.my_graph))
35 {
36 make_connections();
37 set_up_composite();
38 }
39 ~two_bit_adder() {}
40
41private:
42 void make_connections() {
43 make_edge(output_port<1>(two_adders[0]), input_port<0>(two_adders[1]));
44 }
45 void set_up_composite() {
46
47 base_type::input_ports_type input_tuple(input_port<0>(two_adders[0]/*CI*/), input_port<1>(two_adders[0]), input_port<2>(two_adders[0]), input_port<1>(two_adders[1]), input_port<2>(two_adders[1]));
48
49 base_type::output_ports_type output_tuple(output_port<0>(two_adders[0]), output_port<0>(two_adders[1]),output_port<1>(two_adders[1]/*CO*/));
50 base_type::set_external_ports(input_tuple, output_tuple);
51 }
52};
53
54#endif /* __TBBexample_graph_logicsim_tba_H */
55
56