1 | #ifndef CAPSTONE_SPARC_H |
2 | #define CAPSTONE_SPARC_H |
3 | |
4 | /* Capstone Disassembly Engine */ |
5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ |
6 | |
7 | #ifdef __cplusplus |
8 | extern "C" { |
9 | #endif |
10 | |
11 | #include "platform.h" |
12 | |
13 | // GCC SPARC toolchain has a default macro called "sparc" which breaks |
14 | // compilation |
15 | #undef sparc |
16 | |
17 | #ifdef _MSC_VER |
18 | #pragma warning(disable:4201) |
19 | #endif |
20 | |
21 | /// Enums corresponding to Sparc condition codes, both icc's and fcc's. |
22 | typedef enum sparc_cc { |
23 | SPARC_CC_INVALID = 0, ///< invalid CC (default) |
24 | // Integer condition codes |
25 | SPARC_CC_ICC_A = 8+256, ///< Always |
26 | SPARC_CC_ICC_N = 0+256, ///< Never |
27 | SPARC_CC_ICC_NE = 9+256, ///< Not Equal |
28 | SPARC_CC_ICC_E = 1+256, ///< Equal |
29 | SPARC_CC_ICC_G = 10+256, ///< Greater |
30 | SPARC_CC_ICC_LE = 2+256, ///< Less or Equal |
31 | SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal |
32 | SPARC_CC_ICC_L = 3+256, ///< Less |
33 | SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned |
34 | SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned |
35 | SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned |
36 | SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned |
37 | SPARC_CC_ICC_POS = 14+256, ///< Positive |
38 | SPARC_CC_ICC_NEG = 6+256, ///< Negative |
39 | SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear |
40 | SPARC_CC_ICC_VS = 7+256, ///< Overflow Set |
41 | |
42 | // Floating condition codes |
43 | SPARC_CC_FCC_A = 8+16+256, ///< Always |
44 | SPARC_CC_FCC_N = 0+16+256, ///< Never |
45 | SPARC_CC_FCC_U = 7+16+256, ///< Unordered |
46 | SPARC_CC_FCC_G = 6+16+256, ///< Greater |
47 | SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater |
48 | SPARC_CC_FCC_L = 4+16+256, ///< Less |
49 | SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less |
50 | SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater |
51 | SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal |
52 | SPARC_CC_FCC_E = 9+16+256, ///< Equal |
53 | SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal |
54 | SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal |
55 | SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal |
56 | SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal |
57 | SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal |
58 | SPARC_CC_FCC_O = 15+16+256, ///< Ordered |
59 | } sparc_cc; |
60 | |
61 | /// Branch hint |
62 | typedef enum sparc_hint { |
63 | SPARC_HINT_INVALID = 0, ///< no hint |
64 | SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction |
65 | SPARC_HINT_PT = 1 << 1, ///< branch taken |
66 | SPARC_HINT_PN = 1 << 2, ///< branch NOT taken |
67 | } sparc_hint; |
68 | |
69 | /// Operand type for instruction's operands |
70 | typedef enum sparc_op_type { |
71 | SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). |
72 | SPARC_OP_REG, ///< = CS_OP_REG (Register operand). |
73 | SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand). |
74 | SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand). |
75 | } sparc_op_type; |
76 | |
77 | /// SPARC registers |
78 | typedef enum sparc_reg { |
79 | SPARC_REG_INVALID = 0, |
80 | |
81 | SPARC_REG_F0, |
82 | SPARC_REG_F1, |
83 | SPARC_REG_F2, |
84 | SPARC_REG_F3, |
85 | SPARC_REG_F4, |
86 | SPARC_REG_F5, |
87 | SPARC_REG_F6, |
88 | SPARC_REG_F7, |
89 | SPARC_REG_F8, |
90 | SPARC_REG_F9, |
91 | SPARC_REG_F10, |
92 | SPARC_REG_F11, |
93 | SPARC_REG_F12, |
94 | SPARC_REG_F13, |
95 | SPARC_REG_F14, |
96 | SPARC_REG_F15, |
97 | SPARC_REG_F16, |
98 | SPARC_REG_F17, |
99 | SPARC_REG_F18, |
100 | SPARC_REG_F19, |
101 | SPARC_REG_F20, |
102 | SPARC_REG_F21, |
103 | SPARC_REG_F22, |
104 | SPARC_REG_F23, |
105 | SPARC_REG_F24, |
106 | SPARC_REG_F25, |
107 | SPARC_REG_F26, |
108 | SPARC_REG_F27, |
109 | SPARC_REG_F28, |
110 | SPARC_REG_F29, |
111 | SPARC_REG_F30, |
112 | SPARC_REG_F31, |
113 | SPARC_REG_F32, |
114 | SPARC_REG_F34, |
115 | SPARC_REG_F36, |
116 | SPARC_REG_F38, |
117 | SPARC_REG_F40, |
118 | SPARC_REG_F42, |
119 | SPARC_REG_F44, |
120 | SPARC_REG_F46, |
121 | SPARC_REG_F48, |
122 | SPARC_REG_F50, |
123 | SPARC_REG_F52, |
124 | SPARC_REG_F54, |
125 | SPARC_REG_F56, |
126 | SPARC_REG_F58, |
127 | SPARC_REG_F60, |
128 | SPARC_REG_F62, |
129 | SPARC_REG_FCC0, // Floating condition codes |
130 | SPARC_REG_FCC1, |
131 | SPARC_REG_FCC2, |
132 | SPARC_REG_FCC3, |
133 | SPARC_REG_FP, |
134 | SPARC_REG_G0, |
135 | SPARC_REG_G1, |
136 | SPARC_REG_G2, |
137 | SPARC_REG_G3, |
138 | SPARC_REG_G4, |
139 | SPARC_REG_G5, |
140 | SPARC_REG_G6, |
141 | SPARC_REG_G7, |
142 | SPARC_REG_I0, |
143 | SPARC_REG_I1, |
144 | SPARC_REG_I2, |
145 | SPARC_REG_I3, |
146 | SPARC_REG_I4, |
147 | SPARC_REG_I5, |
148 | SPARC_REG_I7, |
149 | SPARC_REG_ICC, // Integer condition codes |
150 | SPARC_REG_L0, |
151 | SPARC_REG_L1, |
152 | SPARC_REG_L2, |
153 | SPARC_REG_L3, |
154 | SPARC_REG_L4, |
155 | SPARC_REG_L5, |
156 | SPARC_REG_L6, |
157 | SPARC_REG_L7, |
158 | SPARC_REG_O0, |
159 | SPARC_REG_O1, |
160 | SPARC_REG_O2, |
161 | SPARC_REG_O3, |
162 | SPARC_REG_O4, |
163 | SPARC_REG_O5, |
164 | SPARC_REG_O7, |
165 | SPARC_REG_SP, |
166 | SPARC_REG_Y, |
167 | |
168 | // special register |
169 | SPARC_REG_XCC, |
170 | |
171 | SPARC_REG_ENDING, // <-- mark the end of the list of registers |
172 | |
173 | // extras |
174 | SPARC_REG_O6 = SPARC_REG_SP, |
175 | SPARC_REG_I6 = SPARC_REG_FP, |
176 | } sparc_reg; |
177 | |
178 | /// Instruction's operand referring to memory |
179 | /// This is associated with SPARC_OP_MEM operand type above |
180 | typedef struct sparc_op_mem { |
181 | uint8_t base; ///< base register, can be safely interpreted as |
182 | ///< a value of type `sparc_reg`, but it is only |
183 | ///< one byte wide |
184 | uint8_t index; ///< index register, same conditions apply here |
185 | int32_t disp; ///< displacement/offset value |
186 | } sparc_op_mem; |
187 | |
188 | /// Instruction operand |
189 | typedef struct cs_sparc_op { |
190 | sparc_op_type type; ///< operand type |
191 | union { |
192 | sparc_reg reg; ///< register value for REG operand |
193 | int64_t imm; ///< immediate value for IMM operand |
194 | sparc_op_mem mem; ///< base/disp value for MEM operand |
195 | }; |
196 | } cs_sparc_op; |
197 | |
198 | /// Instruction structure |
199 | typedef struct cs_sparc { |
200 | sparc_cc cc; ///< code condition for this insn |
201 | sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint. |
202 | /// Number of operands of this instruction, |
203 | /// or 0 when instruction has no operand. |
204 | uint8_t op_count; |
205 | cs_sparc_op operands[4]; ///< operands for this instruction. |
206 | } cs_sparc; |
207 | |
208 | /// SPARC instruction |
209 | typedef enum sparc_insn { |
210 | SPARC_INS_INVALID = 0, |
211 | |
212 | SPARC_INS_ADDCC, |
213 | SPARC_INS_ADDX, |
214 | SPARC_INS_ADDXCC, |
215 | SPARC_INS_ADDXC, |
216 | SPARC_INS_ADDXCCC, |
217 | SPARC_INS_ADD, |
218 | SPARC_INS_ALIGNADDR, |
219 | SPARC_INS_ALIGNADDRL, |
220 | SPARC_INS_ANDCC, |
221 | SPARC_INS_ANDNCC, |
222 | SPARC_INS_ANDN, |
223 | SPARC_INS_AND, |
224 | SPARC_INS_ARRAY16, |
225 | SPARC_INS_ARRAY32, |
226 | SPARC_INS_ARRAY8, |
227 | SPARC_INS_B, |
228 | SPARC_INS_JMP, |
229 | SPARC_INS_BMASK, |
230 | SPARC_INS_FB, |
231 | SPARC_INS_BRGEZ, |
232 | SPARC_INS_BRGZ, |
233 | SPARC_INS_BRLEZ, |
234 | SPARC_INS_BRLZ, |
235 | SPARC_INS_BRNZ, |
236 | SPARC_INS_BRZ, |
237 | SPARC_INS_BSHUFFLE, |
238 | SPARC_INS_CALL, |
239 | SPARC_INS_CASX, |
240 | SPARC_INS_CAS, |
241 | SPARC_INS_CMASK16, |
242 | SPARC_INS_CMASK32, |
243 | SPARC_INS_CMASK8, |
244 | SPARC_INS_CMP, |
245 | SPARC_INS_EDGE16, |
246 | SPARC_INS_EDGE16L, |
247 | SPARC_INS_EDGE16LN, |
248 | SPARC_INS_EDGE16N, |
249 | SPARC_INS_EDGE32, |
250 | SPARC_INS_EDGE32L, |
251 | SPARC_INS_EDGE32LN, |
252 | SPARC_INS_EDGE32N, |
253 | SPARC_INS_EDGE8, |
254 | SPARC_INS_EDGE8L, |
255 | SPARC_INS_EDGE8LN, |
256 | SPARC_INS_EDGE8N, |
257 | SPARC_INS_FABSD, |
258 | SPARC_INS_FABSQ, |
259 | SPARC_INS_FABSS, |
260 | SPARC_INS_FADDD, |
261 | SPARC_INS_FADDQ, |
262 | SPARC_INS_FADDS, |
263 | SPARC_INS_FALIGNDATA, |
264 | SPARC_INS_FAND, |
265 | SPARC_INS_FANDNOT1, |
266 | SPARC_INS_FANDNOT1S, |
267 | SPARC_INS_FANDNOT2, |
268 | SPARC_INS_FANDNOT2S, |
269 | SPARC_INS_FANDS, |
270 | SPARC_INS_FCHKSM16, |
271 | SPARC_INS_FCMPD, |
272 | SPARC_INS_FCMPEQ16, |
273 | SPARC_INS_FCMPEQ32, |
274 | SPARC_INS_FCMPGT16, |
275 | SPARC_INS_FCMPGT32, |
276 | SPARC_INS_FCMPLE16, |
277 | SPARC_INS_FCMPLE32, |
278 | SPARC_INS_FCMPNE16, |
279 | SPARC_INS_FCMPNE32, |
280 | SPARC_INS_FCMPQ, |
281 | SPARC_INS_FCMPS, |
282 | SPARC_INS_FDIVD, |
283 | SPARC_INS_FDIVQ, |
284 | SPARC_INS_FDIVS, |
285 | SPARC_INS_FDMULQ, |
286 | SPARC_INS_FDTOI, |
287 | SPARC_INS_FDTOQ, |
288 | SPARC_INS_FDTOS, |
289 | SPARC_INS_FDTOX, |
290 | SPARC_INS_FEXPAND, |
291 | SPARC_INS_FHADDD, |
292 | SPARC_INS_FHADDS, |
293 | SPARC_INS_FHSUBD, |
294 | SPARC_INS_FHSUBS, |
295 | SPARC_INS_FITOD, |
296 | SPARC_INS_FITOQ, |
297 | SPARC_INS_FITOS, |
298 | SPARC_INS_FLCMPD, |
299 | SPARC_INS_FLCMPS, |
300 | SPARC_INS_FLUSHW, |
301 | SPARC_INS_FMEAN16, |
302 | SPARC_INS_FMOVD, |
303 | SPARC_INS_FMOVQ, |
304 | SPARC_INS_FMOVRDGEZ, |
305 | SPARC_INS_FMOVRQGEZ, |
306 | SPARC_INS_FMOVRSGEZ, |
307 | SPARC_INS_FMOVRDGZ, |
308 | SPARC_INS_FMOVRQGZ, |
309 | SPARC_INS_FMOVRSGZ, |
310 | SPARC_INS_FMOVRDLEZ, |
311 | SPARC_INS_FMOVRQLEZ, |
312 | SPARC_INS_FMOVRSLEZ, |
313 | SPARC_INS_FMOVRDLZ, |
314 | SPARC_INS_FMOVRQLZ, |
315 | SPARC_INS_FMOVRSLZ, |
316 | SPARC_INS_FMOVRDNZ, |
317 | SPARC_INS_FMOVRQNZ, |
318 | SPARC_INS_FMOVRSNZ, |
319 | SPARC_INS_FMOVRDZ, |
320 | SPARC_INS_FMOVRQZ, |
321 | SPARC_INS_FMOVRSZ, |
322 | SPARC_INS_FMOVS, |
323 | SPARC_INS_FMUL8SUX16, |
324 | SPARC_INS_FMUL8ULX16, |
325 | SPARC_INS_FMUL8X16, |
326 | SPARC_INS_FMUL8X16AL, |
327 | SPARC_INS_FMUL8X16AU, |
328 | SPARC_INS_FMULD, |
329 | SPARC_INS_FMULD8SUX16, |
330 | SPARC_INS_FMULD8ULX16, |
331 | SPARC_INS_FMULQ, |
332 | SPARC_INS_FMULS, |
333 | SPARC_INS_FNADDD, |
334 | SPARC_INS_FNADDS, |
335 | SPARC_INS_FNAND, |
336 | SPARC_INS_FNANDS, |
337 | SPARC_INS_FNEGD, |
338 | SPARC_INS_FNEGQ, |
339 | SPARC_INS_FNEGS, |
340 | SPARC_INS_FNHADDD, |
341 | SPARC_INS_FNHADDS, |
342 | SPARC_INS_FNOR, |
343 | SPARC_INS_FNORS, |
344 | SPARC_INS_FNOT1, |
345 | SPARC_INS_FNOT1S, |
346 | SPARC_INS_FNOT2, |
347 | SPARC_INS_FNOT2S, |
348 | SPARC_INS_FONE, |
349 | SPARC_INS_FONES, |
350 | SPARC_INS_FOR, |
351 | SPARC_INS_FORNOT1, |
352 | SPARC_INS_FORNOT1S, |
353 | SPARC_INS_FORNOT2, |
354 | SPARC_INS_FORNOT2S, |
355 | SPARC_INS_FORS, |
356 | SPARC_INS_FPACK16, |
357 | SPARC_INS_FPACK32, |
358 | SPARC_INS_FPACKFIX, |
359 | SPARC_INS_FPADD16, |
360 | SPARC_INS_FPADD16S, |
361 | SPARC_INS_FPADD32, |
362 | SPARC_INS_FPADD32S, |
363 | SPARC_INS_FPADD64, |
364 | SPARC_INS_FPMERGE, |
365 | SPARC_INS_FPSUB16, |
366 | SPARC_INS_FPSUB16S, |
367 | SPARC_INS_FPSUB32, |
368 | SPARC_INS_FPSUB32S, |
369 | SPARC_INS_FQTOD, |
370 | SPARC_INS_FQTOI, |
371 | SPARC_INS_FQTOS, |
372 | SPARC_INS_FQTOX, |
373 | SPARC_INS_FSLAS16, |
374 | SPARC_INS_FSLAS32, |
375 | SPARC_INS_FSLL16, |
376 | SPARC_INS_FSLL32, |
377 | SPARC_INS_FSMULD, |
378 | SPARC_INS_FSQRTD, |
379 | SPARC_INS_FSQRTQ, |
380 | SPARC_INS_FSQRTS, |
381 | SPARC_INS_FSRA16, |
382 | SPARC_INS_FSRA32, |
383 | SPARC_INS_FSRC1, |
384 | SPARC_INS_FSRC1S, |
385 | SPARC_INS_FSRC2, |
386 | SPARC_INS_FSRC2S, |
387 | SPARC_INS_FSRL16, |
388 | SPARC_INS_FSRL32, |
389 | SPARC_INS_FSTOD, |
390 | SPARC_INS_FSTOI, |
391 | SPARC_INS_FSTOQ, |
392 | SPARC_INS_FSTOX, |
393 | SPARC_INS_FSUBD, |
394 | SPARC_INS_FSUBQ, |
395 | SPARC_INS_FSUBS, |
396 | SPARC_INS_FXNOR, |
397 | SPARC_INS_FXNORS, |
398 | SPARC_INS_FXOR, |
399 | SPARC_INS_FXORS, |
400 | SPARC_INS_FXTOD, |
401 | SPARC_INS_FXTOQ, |
402 | SPARC_INS_FXTOS, |
403 | SPARC_INS_FZERO, |
404 | SPARC_INS_FZEROS, |
405 | SPARC_INS_JMPL, |
406 | SPARC_INS_LDD, |
407 | SPARC_INS_LD, |
408 | SPARC_INS_LDQ, |
409 | SPARC_INS_LDSB, |
410 | SPARC_INS_LDSH, |
411 | SPARC_INS_LDSW, |
412 | SPARC_INS_LDUB, |
413 | SPARC_INS_LDUH, |
414 | SPARC_INS_LDX, |
415 | SPARC_INS_LZCNT, |
416 | SPARC_INS_MEMBAR, |
417 | SPARC_INS_MOVDTOX, |
418 | SPARC_INS_MOV, |
419 | SPARC_INS_MOVRGEZ, |
420 | SPARC_INS_MOVRGZ, |
421 | SPARC_INS_MOVRLEZ, |
422 | SPARC_INS_MOVRLZ, |
423 | SPARC_INS_MOVRNZ, |
424 | SPARC_INS_MOVRZ, |
425 | SPARC_INS_MOVSTOSW, |
426 | SPARC_INS_MOVSTOUW, |
427 | SPARC_INS_MULX, |
428 | SPARC_INS_NOP, |
429 | SPARC_INS_ORCC, |
430 | SPARC_INS_ORNCC, |
431 | SPARC_INS_ORN, |
432 | SPARC_INS_OR, |
433 | SPARC_INS_PDIST, |
434 | SPARC_INS_PDISTN, |
435 | SPARC_INS_POPC, |
436 | SPARC_INS_RD, |
437 | SPARC_INS_RESTORE, |
438 | SPARC_INS_RETT, |
439 | SPARC_INS_SAVE, |
440 | SPARC_INS_SDIVCC, |
441 | SPARC_INS_SDIVX, |
442 | SPARC_INS_SDIV, |
443 | SPARC_INS_SETHI, |
444 | SPARC_INS_SHUTDOWN, |
445 | SPARC_INS_SIAM, |
446 | SPARC_INS_SLLX, |
447 | SPARC_INS_SLL, |
448 | SPARC_INS_SMULCC, |
449 | SPARC_INS_SMUL, |
450 | SPARC_INS_SRAX, |
451 | SPARC_INS_SRA, |
452 | SPARC_INS_SRLX, |
453 | SPARC_INS_SRL, |
454 | SPARC_INS_STBAR, |
455 | SPARC_INS_STB, |
456 | SPARC_INS_STD, |
457 | SPARC_INS_ST, |
458 | SPARC_INS_STH, |
459 | SPARC_INS_STQ, |
460 | SPARC_INS_STX, |
461 | SPARC_INS_SUBCC, |
462 | SPARC_INS_SUBX, |
463 | SPARC_INS_SUBXCC, |
464 | SPARC_INS_SUB, |
465 | SPARC_INS_SWAP, |
466 | SPARC_INS_TADDCCTV, |
467 | SPARC_INS_TADDCC, |
468 | SPARC_INS_T, |
469 | SPARC_INS_TSUBCCTV, |
470 | SPARC_INS_TSUBCC, |
471 | SPARC_INS_UDIVCC, |
472 | SPARC_INS_UDIVX, |
473 | SPARC_INS_UDIV, |
474 | SPARC_INS_UMULCC, |
475 | SPARC_INS_UMULXHI, |
476 | SPARC_INS_UMUL, |
477 | SPARC_INS_UNIMP, |
478 | SPARC_INS_FCMPED, |
479 | SPARC_INS_FCMPEQ, |
480 | SPARC_INS_FCMPES, |
481 | SPARC_INS_WR, |
482 | SPARC_INS_XMULX, |
483 | SPARC_INS_XMULXHI, |
484 | SPARC_INS_XNORCC, |
485 | SPARC_INS_XNOR, |
486 | SPARC_INS_XORCC, |
487 | SPARC_INS_XOR, |
488 | |
489 | // alias instructions |
490 | SPARC_INS_RET, |
491 | SPARC_INS_RETL, |
492 | |
493 | SPARC_INS_ENDING, // <-- mark the end of the list of instructions |
494 | } sparc_insn; |
495 | |
496 | /// Group of SPARC instructions |
497 | typedef enum sparc_insn_group { |
498 | SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID |
499 | |
500 | // Generic groups |
501 | // all jump instructions (conditional+direct+indirect jumps) |
502 | SPARC_GRP_JUMP, ///< = CS_GRP_JUMP |
503 | |
504 | // Architecture-specific groups |
505 | SPARC_GRP_HARDQUAD = 128, |
506 | SPARC_GRP_V9, |
507 | SPARC_GRP_VIS, |
508 | SPARC_GRP_VIS2, |
509 | SPARC_GRP_VIS3, |
510 | SPARC_GRP_32BIT, |
511 | SPARC_GRP_64BIT, |
512 | |
513 | SPARC_GRP_ENDING, // <-- mark the end of the list of groups |
514 | } sparc_insn_group; |
515 | |
516 | #ifdef __cplusplus |
517 | } |
518 | #endif |
519 | |
520 | #endif |
521 | |