1/* Copyright (C) 2015 Povilas Kanapickas <povilas@radix.lt>
2
3 Distributed under the Boost Software License, Version 1.0.
4 (See accompanying file LICENSE_1_0.txt or copy at
5 http://www.boost.org/LICENSE_1_0.txt)
6*/
7
8/* This file contains macros that set up information for single architecture
9 definition. It's here to reduce duplication. Other files supply appropriate
10 definitions of certain input macros and collect the output from the macros
11 defined in this file.
12
13 Note that in C++ it's not possible to substitute the nested macros in
14 replacement list of a #define at the point of definition of said #define.
15 All nested macros will be substituted to the current values at each site of
16 use. The consequence is that the resulting macros of this file may only be
17 evaluated by #if elsewhere, otherwise the last inclusion of the file will
18 effectively overwrite the values.
19
20 The input data may be supplied via two ways:
21 1) If SIMDPP_ARCH_PP_LIST is not defined, then the instruction sets should
22 be supplied via SIMDPP_ARCH_* macros. If particular macro expands to
23 non-zero value then the given instruction set and any subsets are
24 enabled. After processing the information supplied via SIMDPP_ARCH_*
25 this file undefines all these macros.
26
27 2) If SIMDPP_ARCH_PP_LIST is defined, then it supplies a list of enabled
28 instruction sets. The macro should be defined to a comma-separated list
29 of identifiers, each equivalent to one of SIMDPP_ARCH_* macro names.
30
31 Note that if SIMDPP_ARCH_PP_LIST is defined, then all SIMDPP_ARCH_* macros
32 themselves must not be defined, as they cause unintended expansions within
33 tihs file.
34
35 The output data:
36
37 SIMDPP_ARCH_PP_USE_* - defined depending on whether the particular
38 instructions are enabled.
39
40 SIMDPP_ARCH_PP_NS_USE_* - defined depending on whether the particular
41 instructions set id should be included into SIMDPP_ARCH_NAMESPACE
42 definition. The difference from SIMDPP_ARCH_PP_USE_* is that some
43 instruction sets are subsets of other instruction sets, so it makes
44 no sense to make the namespace longer. E.g. we use arch_ssse3 instead of
45 arch_sse2_sse3_ssse3.
46*/
47
48#include <simdpp/detail/preprocessor.h>
49#include <simdpp/detail/preprocessor/cat.hpp>
50#include <simdpp/detail/preprocessor/facilities/expand.hpp>
51#include <simdpp/detail/insn_id.h>
52
53// Undef output macros
54#ifdef SIMDPP_ARCH_PP_ARCH_ID
55#undef SIMDPP_ARCH_PP_ARCH_ID
56#endif
57
58#ifdef SIMDPP_ARCH_PP_USE_NULL
59#undef SIMDPP_ARCH_PP_USE_NULL
60#endif
61#ifdef SIMDPP_ARCH_PP_USE_SSE2
62#undef SIMDPP_ARCH_PP_USE_SSE2
63#endif
64#ifdef SIMDPP_ARCH_PP_USE_SSE3
65#undef SIMDPP_ARCH_PP_USE_SSE3
66#endif
67#ifdef SIMDPP_ARCH_PP_USE_SSSE3
68#undef SIMDPP_ARCH_PP_USE_SSSE3
69#endif
70#ifdef SIMDPP_ARCH_PP_USE_SSE4_1
71#undef SIMDPP_ARCH_PP_USE_SSE4_1
72#endif
73#ifdef SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN
74#undef SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN
75#endif
76#ifdef SIMDPP_ARCH_PP_USE_AVX
77#undef SIMDPP_ARCH_PP_USE_AVX
78#endif
79#ifdef SIMDPP_ARCH_PP_USE_AVX2
80#undef SIMDPP_ARCH_PP_USE_AVX2
81#endif
82#ifdef SIMDPP_ARCH_PP_USE_AVX512F
83#undef SIMDPP_ARCH_PP_USE_AVX512F
84#endif
85#ifdef SIMDPP_ARCH_PP_USE_AVX512BW
86#undef SIMDPP_ARCH_PP_USE_AVX512BW
87#endif
88#ifdef SIMDPP_ARCH_PP_USE_AVX512DQ
89#undef SIMDPP_ARCH_PP_USE_AVX512DQ
90#endif
91#ifdef SIMDPP_ARCH_PP_USE_AVX512VL
92#undef SIMDPP_ARCH_PP_USE_AVX512VL
93#endif
94#ifdef SIMDPP_ARCH_PP_USE_FMA3
95#undef SIMDPP_ARCH_PP_USE_FMA3
96#endif
97#ifdef SIMDPP_ARCH_PP_USE_FMA4
98#undef SIMDPP_ARCH_PP_USE_FMA4
99#endif
100#ifdef SIMDPP_ARCH_PP_USE_XOP
101#undef SIMDPP_ARCH_PP_USE_XOP
102#endif
103#ifdef SIMDPP_ARCH_PP_USE_NEON
104#undef SIMDPP_ARCH_PP_USE_NEON
105#endif
106#ifdef SIMDPP_ARCH_PP_USE_NEON_FLT_SP
107#undef SIMDPP_ARCH_PP_USE_NEON_FLT_SP
108#endif
109#ifdef SIMDPP_ARCH_PP_USE_ALTIVEC
110#undef SIMDPP_ARCH_PP_USE_ALTIVEC
111#endif
112#ifdef SIMDPP_ARCH_PP_USE_VSX_206
113#undef SIMDPP_ARCH_PP_USE_VSX_206
114#endif
115#ifdef SIMDPP_ARCH_PP_USE_VSX_207
116#undef SIMDPP_ARCH_PP_USE_VSX_207
117#endif
118#ifdef SIMDPP_ARCH_PP_USE_MSA
119#undef SIMDPP_ARCH_PP_USE_MSA
120#endif
121
122#ifdef SIMDPP_ARCH_PP_NS_USE_NULL
123#undef SIMDPP_ARCH_PP_NS_USE_NULL
124#endif
125#ifdef SIMDPP_ARCH_PP_NS_USE_SSE2
126#undef SIMDPP_ARCH_PP_NS_USE_SSE2
127#endif
128#ifdef SIMDPP_ARCH_PP_NS_USE_SSE3
129#undef SIMDPP_ARCH_PP_NS_USE_SSE3
130#endif
131#ifdef SIMDPP_ARCH_PP_NS_USE_SSSE3
132#undef SIMDPP_ARCH_PP_NS_USE_SSSE3
133#endif
134#ifdef SIMDPP_ARCH_PP_NS_USE_SSE4_1
135#undef SIMDPP_ARCH_PP_NS_USE_SSE4_1
136#endif
137#ifdef SIMDPP_ARCH_PP_NS_USE_POPCNT_INSN
138#undef SIMDPP_ARCH_PP_NS_USE_POPCNT_INSN
139#endif
140#ifdef SIMDPP_ARCH_PP_NS_USE_AVX
141#undef SIMDPP_ARCH_PP_NS_USE_AVX
142#endif
143#ifdef SIMDPP_ARCH_PP_NS_USE_AVX2
144#undef SIMDPP_ARCH_PP_NS_USE_AVX2
145#endif
146#ifdef SIMDPP_ARCH_PP_NS_USE_AVX512F
147#undef SIMDPP_ARCH_PP_NS_USE_AVX512F
148#endif
149#ifdef SIMDPP_ARCH_PP_NS_USE_AVX512BW
150#undef SIMDPP_ARCH_PP_NS_USE_AVX512BW
151#endif
152#ifdef SIMDPP_ARCH_PP_NS_USE_AVX512DQ
153#undef SIMDPP_ARCH_PP_NS_USE_AVX512DQ
154#endif
155#ifdef SIMDPP_ARCH_PP_NS_USE_AVX512VL
156#undef SIMDPP_ARCH_PP_NS_USE_AVX512VL
157#endif
158#ifdef SIMDPP_ARCH_PP_NS_USE_FMA3
159#undef SIMDPP_ARCH_PP_NS_USE_FMA3
160#endif
161#ifdef SIMDPP_ARCH_PP_NS_USE_FMA4
162#undef SIMDPP_ARCH_PP_NS_USE_FMA4
163#endif
164#ifdef SIMDPP_ARCH_PP_NS_USE_XOP
165#undef SIMDPP_ARCH_PP_NS_USE_XOP
166#endif
167#ifdef SIMDPP_ARCH_PP_NS_USE_NEON
168#undef SIMDPP_ARCH_PP_NS_USE_NEON
169#endif
170#ifdef SIMDPP_ARCH_PP_NS_USE_NEON_FLT_SP
171#undef SIMDPP_ARCH_PP_NS_USE_NEON_FLT_SP
172#endif
173#ifdef SIMDPP_ARCH_PP_NS_USE_ALTIVEC
174#undef SIMDPP_ARCH_PP_NS_USE_ALTIVEC
175#endif
176#ifdef SIMDPP_ARCH_PP_NS_USE_VSX_206
177#undef SIMDPP_ARCH_PP_NS_USE_VSX_206
178#endif
179#ifdef SIMDPP_ARCH_PP_NS_USE_VSX_207
180#undef SIMDPP_ARCH_PP_NS_USE_VSX_207
181#endif
182#ifdef SIMDPP_ARCH_PP_NS_USE_MSA
183#undef SIMDPP_ARCH_PP_NS_USE_MSA
184#endif
185
186#ifdef SIMDPP_ARCH_PP_LIST
187
188 #define SIMDPP_ARCH_CREATE_MASK2(x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,...) \
189 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x0) | \
190 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x1) | \
191 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x2) | \
192 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x3) | \
193 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x4) | \
194 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x5) | \
195 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x6) | \
196 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x7) | \
197 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x8) | \
198 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x9) | \
199 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x10) | \
200 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x11) | \
201 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x12) | \
202 SIMDPP_PP_CAT(SIMDPP_PREFIX_, x13)
203
204 #define SIMDPP_ARCH_PP_CREATE_MASK(...) SIMDPP_PP_EXPAND( SIMDPP_ARCH_CREATE_MASK2(__VA_ARGS__,0,0,0,0,0,0,0,0,0,0,0,0,0,0) )
205 #define SIMDPP_ARCH_PP_MASK SIMDPP_ARCH_PP_CREATE_MASK(SIMDPP_ARCH_PP_LIST)
206
207 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_SSE2) == SIMDPP_INSN_MASK_SSE2
208 #define SIMDPP_ARCH_PP_USE_SSE2 1
209 #endif
210 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_SSE3) == SIMDPP_INSN_MASK_SSE3
211 #define SIMDPP_ARCH_PP_USE_SSE3 1
212 #endif
213 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_SSSE3) == SIMDPP_INSN_MASK_SSSE3
214 #define SIMDPP_ARCH_PP_USE_SSSE3 1
215 #endif
216 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_SSE4_1) == SIMDPP_INSN_MASK_SSE4_1
217 #define SIMDPP_ARCH_PP_USE_SSE4_1 1
218 #endif
219 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_POPCNT_INSN) == SIMDPP_INSN_MASK_POPCNT_INSN
220 #define SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN 1
221 #endif
222 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX) == SIMDPP_INSN_MASK_AVX
223 #define SIMDPP_ARCH_PP_USE_AVX 1
224 #endif
225 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX2) == SIMDPP_INSN_MASK_AVX2
226 #define SIMDPP_ARCH_PP_USE_AVX2 1
227 #endif
228 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_FMA3) == SIMDPP_INSN_MASK_FMA3
229 #define SIMDPP_ARCH_PP_USE_FMA3 1
230 #endif
231 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_FMA4) == SIMDPP_INSN_MASK_FMA4
232 #define SIMDPP_ARCH_PP_USE_FMA4 1
233 #endif
234 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_XOP) == SIMDPP_INSN_MASK_XOP
235 #define SIMDPP_ARCH_PP_USE_XOP 1
236 #endif
237 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX512F) == SIMDPP_INSN_MASK_AVX512F
238 #define SIMDPP_ARCH_PP_USE_AVX512F 1
239 #endif
240 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX512BW) == SIMDPP_INSN_MASK_AVX512BW
241 #define SIMDPP_ARCH_PP_USE_AVX512BW 1
242 #endif
243 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX512DQ) == SIMDPP_INSN_MASK_AVX512DQ
244 #define SIMDPP_ARCH_PP_USE_AVX512DQ 1
245 #endif
246 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_AVX512VL) == SIMDPP_INSN_MASK_AVX512VL
247 #define SIMDPP_ARCH_PP_USE_AVX512VL 1
248 #endif
249 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_NEON) == SIMDPP_INSN_MASK_NEON
250 #define SIMDPP_ARCH_PP_USE_NEON 1
251 #endif
252 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_NEON_FLT_SP) == SIMDPP_INSN_MASK_NEON_FLT_SP
253 #define SIMDPP_ARCH_PP_USE_NEON_FLT_SP 1
254 #endif
255 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_ALTIVEC) == SIMDPP_INSN_MASK_ALTIVEC
256 #define SIMDPP_ARCH_PP_USE_ALTIVEC 1
257 #endif
258 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_VSX_206) == SIMDPP_INSN_MASK_VSX_206
259 #define SIMDPP_ARCH_PP_USE_VSX_206 1
260 #endif
261 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_VSX_207) == SIMDPP_INSN_MASK_VSX_207
262 #define SIMDPP_ARCH_PP_USE_VSX_207 1
263 #endif
264 #if ((SIMDPP_ARCH_PP_MASK) & SIMDPP_INSN_MASK_MSA) == SIMDPP_INSN_MASK_MSA
265 #define SIMDPP_ARCH_PP_USE_MSA 1
266 #endif
267 #undef SIMDPP_ARCH_PP_MASK
268 #undef SIMDPP_ARCH_CREATE_MASK2
269 #undef SIMDPP_ARCH_CREATE_MASK
270#else
271
272 #ifdef SIMDPP_ARCH_X86_SSE2
273 #define SIMDPP_ARCH_PP_USE_SSE2 1
274 #undef SIMDPP_ARCH_X86_SSE2
275 #endif
276 #ifdef SIMDPP_ARCH_X86_SSE3
277 #define SIMDPP_ARCH_PP_USE_SSE3 1
278 #undef SIMDPP_ARCH_X86_SSE3
279 #endif
280 #ifdef SIMDPP_ARCH_X86_SSSE3
281 #define SIMDPP_ARCH_PP_USE_SSSE3 1
282 #undef SIMDPP_ARCH_X86_SSSE3
283 #endif
284 #ifdef SIMDPP_ARCH_X86_SSE4_1
285 #define SIMDPP_ARCH_PP_USE_SSE4_1 1
286 #undef SIMDPP_ARCH_X86_SSE4_1
287 #endif
288 #ifdef SIMDPP_ARCH_X86_POPCNT_INSN
289 #define SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN 1
290 #undef SIMDPP_ARCH_X86_POPCNT_INSN
291 #endif
292 #ifdef SIMDPP_ARCH_X86_AVX
293 #define SIMDPP_ARCH_PP_USE_AVX 1
294 #undef SIMDPP_ARCH_X86_AVX
295 #endif
296 #ifdef SIMDPP_ARCH_X86_AVX2
297 #define SIMDPP_ARCH_PP_USE_AVX2 1
298 #undef SIMDPP_ARCH_X86_AVX2
299 #endif
300 #ifdef SIMDPP_ARCH_X86_FMA3
301 #define SIMDPP_ARCH_PP_USE_FMA3 1
302 #undef SIMDPP_ARCH_X86_FMA3
303 #endif
304 #ifdef SIMDPP_ARCH_X86_FMA4
305 #define SIMDPP_ARCH_PP_USE_FMA4 1
306 #undef SIMDPP_ARCH_X86_FMA4
307 #endif
308 #ifdef SIMDPP_ARCH_X86_XOP
309 #define SIMDPP_ARCH_PP_USE_XOP 1
310 #undef SIMDPP_ARCH_X86_XOP
311 #endif
312 #ifdef SIMDPP_ARCH_X86_AVX512F
313 #define SIMDPP_ARCH_PP_USE_AVX512F 1
314 #undef SIMDPP_ARCH_X86_AVX512F
315 #endif
316 #ifdef SIMDPP_ARCH_X86_AVX512BW
317 #define SIMDPP_ARCH_PP_USE_AVX512BW 1
318 #undef SIMDPP_ARCH_X86_AVX512BW
319 #endif
320 #ifdef SIMDPP_ARCH_X86_AVX512DQ
321 #define SIMDPP_ARCH_PP_USE_AVX512DQ 1
322 #undef SIMDPP_ARCH_X86_AVX512DQ
323 #endif
324 #ifdef SIMDPP_ARCH_X86_AVX512VL
325 #define SIMDPP_ARCH_PP_USE_AVX512VL 1
326 #undef SIMDPP_ARCH_X86_AVX512VL
327 #endif
328 #ifdef SIMDPP_ARCH_ARM_NEON
329 #define SIMDPP_ARCH_PP_USE_NEON 1
330 #undef SIMDPP_ARCH_ARM_NEON
331 #endif
332 #ifdef SIMDPP_ARCH_ARM_NEON_FLT_SP
333 #define SIMDPP_ARCH_PP_USE_NEON_FLT_SP 1
334 #undef SIMDPP_ARCH_ARM_NEON_FLT_SP
335 #endif
336 #ifdef SIMDPP_ARCH_POWER_ALTIVEC
337 #define SIMDPP_ARCH_PP_USE_ALTIVEC 1
338 #undef SIMDPP_ARCH_POWER_ALTIVEC
339 #endif
340 #ifdef SIMDPP_ARCH_POWER_VSX_206
341 #define SIMDPP_ARCH_PP_USE_VSX_206 1
342 #undef SIMDPP_ARCH_POWER_VSX_206
343 #endif
344 #ifdef SIMDPP_ARCH_POWER_VSX_207
345 #define SIMDPP_ARCH_PP_USE_VSX_207 1
346 #undef SIMDPP_ARCH_POWER_VSX_207
347 #endif
348 #ifdef SIMDPP_ARCH_MIPS_MSA
349 #define SIMDPP_ARCH_PP_USE_MSA 1
350 #undef SIMDPP_ARCH_MIPS_MSA
351 #endif
352#endif
353
354// Define support of instruction sets that are implicitly available when another
355// instruction set is available
356#if SIMDPP_ARCH_PP_USE_AVX512VL
357 #ifndef SIMDPP_ARCH_PP_USE_AVX512F
358 #define SIMDPP_ARCH_PP_USE_AVX512F 1
359 #endif
360#endif
361
362#if SIMDPP_ARCH_PP_USE_AVX512DQ
363 #ifndef SIMDPP_ARCH_PP_USE_AVX512F
364 #define SIMDPP_ARCH_PP_USE_AVX512F 1
365 #endif
366#endif
367
368#if SIMDPP_ARCH_PP_USE_AVX512BW
369 #ifndef SIMDPP_ARCH_PP_USE_AVX512F
370 #define SIMDPP_ARCH_PP_USE_AVX512F 1
371 #endif
372#endif
373
374#if SIMDPP_ARCH_PP_USE_AVX512F
375 #ifndef SIMDPP_ARCH_PP_USE_AVX2
376 #define SIMDPP_ARCH_PP_USE_AVX2 1
377 #endif
378#endif
379
380#if SIMDPP_ARCH_PP_USE_AVX2
381 #ifndef SIMDPP_ARCH_PP_USE_AVX
382 #define SIMDPP_ARCH_PP_USE_AVX 1
383 #endif
384#endif
385
386#if SIMDPP_ARCH_PP_USE_AVX
387 #ifndef SIMDPP_ARCH_PP_USE_SSE4_1
388 #define SIMDPP_ARCH_PP_USE_SSE4_1 1
389 #endif
390#endif
391
392#if SIMDPP_ARCH_PP_USE_FMA3
393 #ifndef SIMDPP_ARCH_PP_USE_SSE3
394 #define SIMDPP_ARCH_PP_USE_SSE3 1
395 #endif
396#endif
397
398#if SIMDPP_ARCH_PP_USE_FMA4
399 #ifndef SIMDPP_ARCH_PP_USE_SSE3
400 #define SIMDPP_ARCH_PP_USE_SSE3 1
401 #endif
402#endif
403
404#if SIMDPP_ARCH_PP_USE_XOP
405 #ifndef SIMDPP_ARCH_PP_USE_SSE3
406 #define SIMDPP_ARCH_PP_USE_SSE3 1
407 #endif
408#endif
409
410#if SIMDPP_ARCH_PP_USE_SSE4_1
411 #ifndef SIMDPP_ARCH_PP_USE_SSSE3
412 #define SIMDPP_ARCH_PP_USE_SSSE3 1
413 #endif
414#endif
415
416#if SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN
417 #ifndef SIMDPP_ARCH_PP_USE_SSSE3
418 #define SIMDPP_ARCH_PP_USE_SSSE3 1
419 #endif
420#endif
421
422#if SIMDPP_ARCH_PP_USE_SSSE3
423 #ifndef SIMDPP_ARCH_PP_USE_SSE3
424 #define SIMDPP_ARCH_PP_USE_SSE3 1
425 #endif
426#endif
427
428#if SIMDPP_ARCH_PP_USE_SSE3
429 #ifndef SIMDPP_ARCH_PP_USE_SSE2
430 #define SIMDPP_ARCH_PP_USE_SSE2 1
431 #endif
432#endif
433
434#if SIMDPP_ARCH_PP_USE_NEON_FLT_SP
435 #ifndef SIMDPP_ARCH_PP_USE_NEON
436 #define SIMDPP_ARCH_PP_USE_NEON 1
437 #endif
438#endif
439
440#if SIMDPP_ARCH_PP_USE_VSX_207
441 #ifndef SIMDPP_ARCH_PP_USE_VSX_206
442 #define SIMDPP_ARCH_PP_USE_VSX_206 1
443 #endif
444#endif
445
446#if SIMDPP_ARCH_PP_USE_VSX_206
447 #ifndef SIMDPP_ARCH_PP_USE_ALTIVEC
448 #define SIMDPP_ARCH_PP_USE_ALTIVEC 1
449 #endif
450#endif
451
452#if !(SIMDPP_ARCH_PP_USE_SSE2 || SIMDPP_ARCH_PP_USE_NEON || \
453 SIMDPP_ARCH_PP_USE_NEON_FLT_SP || SIMDPP_ARCH_PP_USE_ALTIVEC || SIMDPP_ARCH_PP_USE_MSA)
454#define SIMDPP_ARCH_PP_USE_NULL 1
455#endif
456
457#if SIMDPP_ARCH_PP_USE_FMA3 && SIMDPP_ARCH_PP_USE_FMA4
458 #error "FMA3 and FMA4 can't be used together"
459#endif
460
461// To limit the length of the SIMDPP_ARCH_NAMESPACE and friends, we omit
462// instruction sets that are subsets of other enabled instruction sets. For
463// example, for SSE3 we generate arch_sse3 instead of arch_sse2_sse3.
464
465#if SIMDPP_ARCH_PP_USE_NULL
466#define SIMDPP_ARCH_PP_NS_USE_NULL 1
467#endif
468#if SIMDPP_ARCH_PP_USE_SSE2 && !SIMDPP_ARCH_PP_USE_SSE3
469#define SIMDPP_ARCH_PP_NS_USE_SSE2 1
470#endif
471#if SIMDPP_ARCH_PP_USE_SSE3 && !SIMDPP_ARCH_PP_USE_SSSE3 && !SIMDPP_ARCH_PP_USE_XOP && !SIMDPP_ARCH_PP_USE_FMA3 && !SIMDPP_ARCH_PP_USE_FMA4
472#define SIMDPP_ARCH_PP_NS_USE_SSE3 1
473#endif
474#if SIMDPP_ARCH_PP_USE_SSSE3 && !SIMDPP_ARCH_PP_USE_SSE4_1
475#define SIMDPP_ARCH_PP_NS_USE_SSSE3 1
476#endif
477#if SIMDPP_ARCH_PP_USE_SSE4_1 && !SIMDPP_ARCH_PP_USE_AVX
478#define SIMDPP_ARCH_PP_NS_USE_SSE4_1 1
479#endif
480#if SIMDPP_ARCH_PP_USE_X86_POPCNT_INSN
481#define SIMDPP_ARCH_PP_NS_USE_POPCNT_INSN 1
482#endif
483#if SIMDPP_ARCH_PP_USE_AVX && !SIMDPP_ARCH_PP_USE_AVX2
484#define SIMDPP_ARCH_PP_NS_USE_AVX 1
485#endif
486#if SIMDPP_ARCH_PP_USE_AVX2 && !SIMDPP_ARCH_PP_USE_AVX512F
487#define SIMDPP_ARCH_PP_NS_USE_AVX2 1
488#endif
489#if SIMDPP_ARCH_PP_USE_AVX512F && !SIMDPP_ARCH_PP_USE_AVX512BW && !SIMDPP_ARCH_PP_USE_AVX512DQ && !SIMDPP_ARCH_PP_USE_AVX512VL
490#define SIMDPP_ARCH_PP_NS_USE_AVX512F 1
491#endif
492#if SIMDPP_ARCH_PP_USE_AVX512BW
493#define SIMDPP_ARCH_PP_NS_USE_AVX512BW 1
494#endif
495#if SIMDPP_ARCH_PP_USE_AVX512DQ
496#define SIMDPP_ARCH_PP_NS_USE_AVX512DQ 1
497#endif
498#if SIMDPP_ARCH_PP_USE_AVX512VL
499#define SIMDPP_ARCH_PP_NS_USE_AVX512VL 1
500#endif
501#if SIMDPP_ARCH_PP_USE_FMA3
502#define SIMDPP_ARCH_PP_NS_USE_FMA3 1
503#endif
504#if SIMDPP_ARCH_PP_USE_FMA4
505#define SIMDPP_ARCH_PP_NS_USE_FMA4 1
506#endif
507#if SIMDPP_ARCH_PP_USE_XOP
508#define SIMDPP_ARCH_PP_NS_USE_XOP 1
509#endif
510#if SIMDPP_ARCH_PP_USE_NEON && !SIMDPP_ARCH_PP_USE_NEON_FLT_SP
511#define SIMDPP_ARCH_PP_NS_USE_NEON 1
512#endif
513#if SIMDPP_ARCH_PP_USE_NEON_FLT_SP
514#define SIMDPP_ARCH_PP_NS_USE_NEON_FLT_SP 1
515#endif
516#if SIMDPP_ARCH_PP_USE_ALTIVEC && !SIMDPP_ARCH_PP_USE_VSX_206
517#define SIMDPP_ARCH_PP_NS_USE_ALTIVEC 1
518#endif
519#if SIMDPP_ARCH_PP_USE_VSX_206 && !SIMDPP_ARCH_PP_USE_VSX_207
520#define SIMDPP_ARCH_PP_NS_USE_VSX_206 1
521#endif
522#if SIMDPP_ARCH_PP_USE_VSX_207
523#define SIMDPP_ARCH_PP_NS_USE_VSX_207 1
524#endif
525#if SIMDPP_ARCH_PP_USE_MSA
526#define SIMDPP_ARCH_PP_NS_USE_MSA 1
527#endif
528