1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_I_SHIFT_L_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_I_SHIFT_L_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/capabilities.h>
18#include <simdpp/detail/insn/i_shift_l.h>
19#include <simdpp/detail/insn/i_shift_l_v.h>
20#include <simdpp/detail/not_implemented.h>
21
22namespace simdpp {
23namespace SIMDPP_ARCH_NAMESPACE {
24
25// -----------------------------------------------------------------------------
26// shift by scalar
27
28/** Shifts 8-bit values left by @a count bits while shifting in zeros.
29
30 @code
31 r0 = a0 << count
32 ...
33 rN = aN << count
34 @endcode
35*/
36template<unsigned N, class E> SIMDPP_INL
37int8<N,expr_empty> operator<<(const int8<N,E>& a, unsigned count)
38{
39 uint8<N> qa = a.eval();
40 return detail::insn::i_shift_l(qa, count);
41}
42
43template<unsigned N, class E> SIMDPP_INL
44uint8<N,expr_empty> operator<<(const uint8<N,E>& a, unsigned count)
45{
46 return detail::insn::i_shift_l(a.eval(), count);
47}
48
49/** Shifts 16-bit values left by @a count bits while shifting in zeros.
50
51 @code
52 r0 = a0 << count
53 ...
54 rN = aN << count
55 @endcode
56*/
57template<unsigned N, class E> SIMDPP_INL
58int16<N,expr_empty> operator<<(const int16<N,E>& a, unsigned count)
59{
60 uint16<N> qa = a.eval();
61 return detail::insn::i_shift_l(qa, count);
62}
63
64template<unsigned N, class E> SIMDPP_INL
65uint16<N,expr_empty> operator<<(const uint16<N,E>& a, unsigned count)
66{
67 return detail::insn::i_shift_l(a.eval(), count);
68}
69
70/** Shifts 32-bit values left by @a count bits while shifting in zeros.
71
72 @code
73 r0 = a0 << count
74 ...
75 rN = aN << count
76 @endcode
77*/
78template<unsigned N, class E> SIMDPP_INL
79int32<N,expr_empty> operator<<(const int32<N,E>& a, unsigned count)
80{
81 uint32<N> qa = a.eval();
82 return detail::insn::i_shift_l(qa, count);
83}
84
85template<unsigned N, class E> SIMDPP_INL
86uint32<N,expr_empty> operator<<(const uint32<N,E>& a, unsigned count)
87{
88 return detail::insn::i_shift_l(a.eval(), count);
89}
90
91/** Shifts 64-bit values left by @a count bits while shifting in zeros.
92
93 @code
94 r0 = a0 << count
95 ...
96 rN = aN << count
97 @endcode
98*/
99template<unsigned N, class E> SIMDPP_INL
100int64<N,expr_empty> operator<<(const int64<N,E>& a, unsigned count)
101{
102 uint64<N> qa = a.eval();
103 return detail::insn::i_shift_l(qa, count);
104}
105
106template<unsigned N, class E> SIMDPP_INL
107uint64<N,expr_empty> operator<<(const uint64<N,E>& a, unsigned count)
108{
109 return detail::insn::i_shift_l(a.eval(), count);
110}
111
112// -----------------------------------------------------------------------------
113// shift by vector
114
115/** Shifts 8-bit values left by the number of bits in corresponding element
116 in the given count vector. Zero bits are shifted in.
117
118 @code
119 r0 = a0 << count0
120 ...
121 rN = aN << countN
122 @endcode
123*/
124template<unsigned N, class E> SIMDPP_INL
125int8<N,expr_empty> operator<<(const int8<N,E>& a, const uint8<N,E>& count)
126{
127#if SIMDPP_HAS_INT8_SHIFT_R_BY_VECTOR
128 uint8<N> qa = a.eval();
129 return detail::insn::i_shift_l_v(qa, count.eval());
130#else
131 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
132#endif
133}
134
135template<unsigned N, class E> SIMDPP_INL
136uint8<N,expr_empty> operator<<(const uint8<N,E>& a, const uint8<N,E>& count)
137{
138#if SIMDPP_HAS_UINT8_SHIFT_R_BY_VECTOR
139 return detail::insn::i_shift_l_v(a.eval(), count.eval());
140#else
141 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
142#endif
143}
144
145/** Shifts 16-bit values left by the number of bits in corresponding element
146 in the given count vector. Zero bits are shifted in.
147
148 @code
149 r0 = a0 << count0
150 ...
151 rN = aN << countN
152 @endcode
153*/
154template<unsigned N, class E> SIMDPP_INL
155int16<N,expr_empty> operator<<(const int16<N,E>& a, const uint16<N,E>& count)
156{
157#if SIMDPP_HAS_INT16_SHIFT_R_BY_VECTOR
158 uint16<N> qa = a.eval();
159 return detail::insn::i_shift_l_v(qa, count.eval());
160#else
161 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
162#endif
163}
164
165template<unsigned N, class E> SIMDPP_INL
166uint16<N,expr_empty> operator<<(const uint16<N,E>& a, const uint16<N,E>& count)
167{
168#if SIMDPP_HAS_UINT16_SHIFT_R_BY_VECTOR
169 return detail::insn::i_shift_l_v(a.eval(), count.eval());
170#else
171 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
172#endif
173}
174
175/** Shifts 32-bit values left by the number of bits in corresponding element
176 in the given count vector. Zero bits are shifted in.
177
178 @code
179 r0 = a0 << count0
180 ...
181 rN = aN << countN
182 @endcode
183*/
184template<unsigned N, class E> SIMDPP_INL
185int32<N,expr_empty> operator<<(const int32<N,E>& a, const uint32<N,E>& count)
186{
187#if SIMDPP_HAS_INT32_SHIFT_R_BY_VECTOR
188 uint32<N> qa = a.eval();
189 return detail::insn::i_shift_l_v(qa, count.eval());
190#else
191 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
192#endif
193}
194
195template<unsigned N, class E> SIMDPP_INL
196uint32<N,expr_empty> operator<<(const uint32<N,E>& a, const uint32<N,E>& count)
197{
198#if SIMDPP_HAS_UINT32_SHIFT_R_BY_VECTOR
199 return detail::insn::i_shift_l_v(a.eval(), count.eval());
200#else
201 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
202#endif
203}
204
205// -----------------------------------------------------------------------------
206// shift by compile-time constant
207
208} // namespace SIMDPP_ARCH_NAMESPACE
209} // namespace simdpp
210
211#endif
212
213