1// Licensed to the .NET Foundation under one or more agreements.
2// The .NET Foundation licenses this file to you under the MIT license.
3// See the LICENSE file in the project root for more information.
4
5#if defined(_TARGET_ARM64_)
6
7// The ARM64 instructions are all 32 bits in size.
8// we use an unsigned int to hold the encoded instructions.
9// This typedef defines the type that we use to hold encoded instructions.
10//
11typedef unsigned int code_t;
12
13static bool strictArmAsm;
14
15/************************************************************************/
16/* Routines that compute the size of / encode instructions */
17/************************************************************************/
18
19#ifdef DEBUG
20
21/************************************************************************/
22/* Debug-only routines to display instructions */
23/************************************************************************/
24
25const char* emitFPregName(unsigned reg, bool varName = true);
26const char* emitVectorRegName(regNumber reg);
27
28void emitDispInst(instruction ins);
29void emitDispImm(ssize_t imm, bool addComma, bool alwaysHex = false);
30void emitDispFloatZero();
31void emitDispFloatImm(ssize_t imm8);
32void emitDispImmOptsLSL12(ssize_t imm, insOpts opt);
33void emitDispCond(insCond cond);
34void emitDispFlags(insCflags flags);
35void emitDispBarrier(insBarrier barrier);
36void emitDispShiftOpts(insOpts opt);
37void emitDispExtendOpts(insOpts opt);
38void emitDispLSExtendOpts(insOpts opt);
39void emitDispReg(regNumber reg, emitAttr attr, bool addComma);
40void emitDispVectorReg(regNumber reg, insOpts opt, bool addComma);
41void emitDispVectorRegIndex(regNumber reg, emitAttr elemsize, ssize_t index, bool addComma);
42void emitDispArrangement(insOpts opt);
43void emitDispShiftedReg(regNumber reg, insOpts opt, ssize_t imm, emitAttr attr);
44void emitDispExtendReg(regNumber reg, insOpts opt, ssize_t imm);
45void emitDispAddrRI(regNumber reg, insOpts opt, ssize_t imm);
46void emitDispAddrRRExt(regNumber reg1, regNumber reg2, insOpts opt, bool isScaled, emitAttr size);
47
48void emitDispIns(instrDesc* id,
49 bool isNew,
50 bool doffs,
51 bool asmfm,
52 unsigned offs = 0,
53 BYTE* pCode = 0,
54 size_t sz = 0,
55 insGroup* ig = NULL);
56#endif // DEBUG
57
58/************************************************************************/
59/* Private members that deal with target-dependent instr. descriptors */
60/************************************************************************/
61
62private:
63instrDesc* emitNewInstrCallDir(int argCnt,
64 VARSET_VALARG_TP GCvars,
65 regMaskTP gcrefRegs,
66 regMaskTP byrefRegs,
67 emitAttr retSize,
68 emitAttr secondRetSize);
69
70instrDesc* emitNewInstrCallInd(int argCnt,
71 ssize_t disp,
72 VARSET_VALARG_TP GCvars,
73 regMaskTP gcrefRegs,
74 regMaskTP byrefRegs,
75 emitAttr retSize,
76 emitAttr secondRetSize);
77
78/************************************************************************/
79/* Private helpers for instruction output */
80/************************************************************************/
81
82private:
83bool emitInsIsCompare(instruction ins);
84bool emitInsIsLoad(instruction ins);
85bool emitInsIsStore(instruction ins);
86bool emitInsIsLoadOrStore(instruction ins);
87emitAttr emitInsAdjustLoadStoreAttr(instruction ins, emitAttr attr);
88emitAttr emitInsTargetRegSize(instrDesc* id);
89emitAttr emitInsLoadStoreSize(instrDesc* id);
90
91emitter::insFormat emitInsFormat(instruction ins);
92emitter::code_t emitInsCode(instruction ins, insFormat fmt);
93
94// Generate code for a load or store operation and handle the case of contained GT_LEA op1 with [base + index<<scale +
95// offset]
96void emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataReg, GenTreeIndir* indir);
97
98// Emit the 32-bit Arm64 instruction 'code' into the 'dst' buffer
99static unsigned emitOutput_Instr(BYTE* dst, code_t code);
100
101// A helper method to return the natural scale for an EA 'size'
102static unsigned NaturalScale_helper(emitAttr size);
103
104// A helper method to perform a Rotate-Right shift operation
105static UINT64 ROR_helper(UINT64 value, unsigned sh, unsigned width);
106
107// A helper method to perform a 'NOT' bitwise complement operation
108static UINT64 NOT_helper(UINT64 value, unsigned width);
109
110// A helper method to perform a bit Replicate operation
111static UINT64 Replicate_helper(UINT64 value, unsigned width, emitAttr size);
112
113/************************************************************************
114*
115* This union is used to to encode/decode the special ARM64 immediate values
116* that is listed as imm(N,r,s) and referred to as 'bitmask immediate'
117*/
118
119union bitMaskImm {
120 struct
121 {
122 unsigned immS : 6; // bits 0..5
123 unsigned immR : 6; // bits 6..11
124 unsigned immN : 1; // bits 12
125 };
126 unsigned immNRS; // concat N:R:S forming a 13-bit unsigned immediate
127};
128
129/************************************************************************
130*
131* Convert between a 64-bit immediate and its 'bitmask immediate'
132* representation imm(i16,hw)
133*/
134
135static emitter::bitMaskImm emitEncodeBitMaskImm(INT64 imm, emitAttr size);
136
137static INT64 emitDecodeBitMaskImm(const emitter::bitMaskImm bmImm, emitAttr size);
138
139/************************************************************************
140*
141* This union is used to to encode/decode the special ARM64 immediate values
142* that is listed as imm(i16,hw) and referred to as 'halfword immediate'
143*/
144
145union halfwordImm {
146 struct
147 {
148 unsigned immVal : 16; // bits 0..15
149 unsigned immHW : 2; // bits 16..17
150 };
151 unsigned immHWVal; // concat HW:Val forming a 18-bit unsigned immediate
152};
153
154/************************************************************************
155*
156* Convert between a 64-bit immediate and its 'halfword immediate'
157* representation imm(i16,hw)
158*/
159
160static emitter::halfwordImm emitEncodeHalfwordImm(INT64 imm, emitAttr size);
161
162static INT64 emitDecodeHalfwordImm(const emitter::halfwordImm hwImm, emitAttr size);
163
164/************************************************************************
165*
166* This union is used to encode/decode the special ARM64 immediate values
167* that is listed as imm(i16,by) and referred to as 'byteShifted immediate'
168*/
169
170union byteShiftedImm {
171 struct
172 {
173 unsigned immVal : 8; // bits 0..7
174 unsigned immBY : 2; // bits 8..9
175 unsigned immOnes : 1; // bit 10
176 };
177 unsigned immBSVal; // concat Ones:BY:Val forming a 10-bit unsigned immediate
178};
179
180/************************************************************************
181*
182* Convert between a 16/32-bit immediate and its 'byteShifted immediate'
183* representation imm(i8,by)
184*/
185
186static emitter::byteShiftedImm emitEncodeByteShiftedImm(INT64 imm, emitAttr size, bool allow_MSL);
187
188static INT32 emitDecodeByteShiftedImm(const emitter::byteShiftedImm bsImm, emitAttr size);
189
190/************************************************************************
191*
192* This union is used to to encode/decode the special ARM64 immediate values
193* that are use for FMOV immediate and referred to as 'float 8-bit immediate'
194*/
195
196union floatImm8 {
197 struct
198 {
199 unsigned immMant : 4; // bits 0..3
200 unsigned immExp : 3; // bits 4..6
201 unsigned immSign : 1; // bits 7
202 };
203 unsigned immFPIVal; // concat Sign:Exp:Mant forming an 8-bit unsigned immediate
204};
205
206/************************************************************************
207*
208* Convert between a double and its 'float 8-bit immediate' representation
209*/
210
211static emitter::floatImm8 emitEncodeFloatImm8(double immDbl);
212
213static double emitDecodeFloatImm8(const emitter::floatImm8 fpImm);
214
215/************************************************************************
216*
217* This union is used to to encode/decode the cond, nzcv and imm5 values for
218* instructions that use them in the small constant immediate field
219*/
220
221union condFlagsImm {
222 struct
223 {
224 insCond cond : 4; // bits 0..3
225 insCflags flags : 4; // bits 4..7
226 unsigned imm5 : 5; // bits 8..12
227 };
228 unsigned immCFVal; // concat imm5:flags:cond forming an 13-bit unsigned immediate
229};
230
231// Returns an encoding for the specified register used in the 'Rd' position
232static code_t insEncodeReg_Rd(regNumber reg);
233
234// Returns an encoding for the specified register used in the 'Rt' position
235static code_t insEncodeReg_Rt(regNumber reg);
236
237// Returns an encoding for the specified register used in the 'Rn' position
238static code_t insEncodeReg_Rn(regNumber reg);
239
240// Returns an encoding for the specified register used in the 'Rm' position
241static code_t insEncodeReg_Rm(regNumber reg);
242
243// Returns an encoding for the specified register used in the 'Ra' position
244static code_t insEncodeReg_Ra(regNumber reg);
245
246// Returns an encoding for the specified register used in the 'Vd' position
247static code_t insEncodeReg_Vd(regNumber reg);
248
249// Returns an encoding for the specified register used in the 'Vt' position
250static code_t insEncodeReg_Vt(regNumber reg);
251
252// Returns an encoding for the specified register used in the 'Vn' position
253static code_t insEncodeReg_Vn(regNumber reg);
254
255// Returns an encoding for the specified register used in the 'Vm' position
256static code_t insEncodeReg_Vm(regNumber reg);
257
258// Returns an encoding for the specified register used in the 'Va' position
259static code_t insEncodeReg_Va(regNumber reg);
260
261// Returns an encoding for the imm which represents the condition code.
262static code_t insEncodeCond(insCond cond);
263
264// Returns an encoding for the imm whioch represents the 'condition code'
265// with the lowest bit inverted (marked by invert(<cond>) in the architecture manual.
266static code_t insEncodeInvertedCond(insCond cond);
267
268// Returns an encoding for the imm which represents the flags.
269static code_t insEncodeFlags(insCflags flags);
270
271// Returns the encoding for the Shift Count bits to be used for Arm64 encodings
272static code_t insEncodeShiftCount(ssize_t imm, emitAttr size);
273
274// Returns the encoding to select the datasize for most Arm64 instructions
275static code_t insEncodeDatasize(emitAttr size);
276
277// Returns the encoding to select the datasize for the general load/store Arm64 instructions
278static code_t insEncodeDatasizeLS(code_t code, emitAttr size);
279
280// Returns the encoding to select the datasize for the vector load/store Arm64 instructions
281static code_t insEncodeDatasizeVLS(code_t code, emitAttr size);
282
283// Returns the encoding to select the datasize for the vector load/store pair Arm64 instructions
284static code_t insEncodeDatasizeVPLS(code_t code, emitAttr size);
285
286// Returns the encoding to select the datasize for bitfield Arm64 instructions
287static code_t insEncodeDatasizeBF(code_t code, emitAttr size);
288
289// Returns the encoding to select the vectorsize for SIMD Arm64 instructions
290static code_t insEncodeVectorsize(emitAttr size);
291
292// Returns the encoding to select 'index' for an Arm64 vector elem instruction
293static code_t insEncodeVectorIndex(emitAttr elemsize, ssize_t index);
294
295// Returns the encoding to select 'index2' for an Arm64 'ins' elem instruction
296static code_t insEncodeVectorIndex2(emitAttr elemsize, ssize_t index2);
297
298// Returns the encoding to select 'index' for an Arm64 'mul' elem instruction
299static code_t insEncodeVectorIndexLMH(emitAttr elemsize, ssize_t index);
300
301// Returns the encoding to shift by 'shift' bits for an Arm64 vector or scalar instruction
302static code_t insEncodeVectorShift(emitAttr size, ssize_t shift);
303
304// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 vector instruction
305static code_t insEncodeElemsize(emitAttr size);
306
307// Returns the encoding to select the 4/8 byte elemsize for an Arm64 float vector instruction
308static code_t insEncodeFloatElemsize(emitAttr size);
309
310// Returns the encoding to select the index for an Arm64 float vector by elem instruction
311static code_t insEncodeFloatIndex(emitAttr elemsize, ssize_t index);
312
313// Returns the encoding to select the 'conversion' operation for a type 'fmt' Arm64 instruction
314static code_t insEncodeConvertOpt(insFormat fmt, insOpts conversion);
315
316// Returns the encoding to have the Rn register of a ld/st reg be Pre/Post/Not indexed updated
317static code_t insEncodeIndexedOpt(insOpts opt);
318
319// Returns the encoding to have the Rn register of a ld/st pair be Pre/Post/Not indexed updated
320static code_t insEncodePairIndexedOpt(instruction ins, insOpts opt);
321
322// Returns the encoding to apply a Shift Type on the Rm register
323static code_t insEncodeShiftType(insOpts opt);
324
325// Returns the encoding to apply a 12 bit left shift to the immediate
326static code_t insEncodeShiftImm12(insOpts opt);
327
328// Returns the encoding to have the Rm register use an extend operation
329static code_t insEncodeExtend(insOpts opt);
330
331// Returns the encoding to scale the Rm register by {0,1,2,3,4} in an extend operation
332static code_t insEncodeExtendScale(ssize_t imm);
333
334// Returns the encoding to have the Rm register be auto scaled by the ld/st size
335static code_t insEncodeReg3Scale(bool isScaled);
336
337// Returns true if 'reg' represents an integer register.
338static bool isIntegerRegister(regNumber reg)
339{
340 return (reg >= REG_INT_FIRST) && (reg <= REG_INT_LAST);
341}
342
343// Returns true if 'value' is a legal unsigned immediate 8 bit encoding (such as for fMOV).
344static bool isValidUimm8(ssize_t value)
345{
346 return (0 <= value) && (value <= 0xFFLL);
347};
348
349// Returns true if 'value' is a legal unsigned immediate 12 bit encoding (such as for CMP, CMN).
350static bool isValidUimm12(ssize_t value)
351{
352 return (0 <= value) && (value <= 0xFFFLL);
353};
354
355// Returns true if 'value' is a legal unsigned immediate 16 bit encoding (such as for MOVZ, MOVN, MOVK).
356static bool isValidUimm16(ssize_t value)
357{
358 return (0 <= value) && (value <= 0xFFFFLL);
359};
360
361// Returns true if 'value' is a legal signed immediate 26 bit encoding (such as for B or BL).
362static bool isValidSimm26(ssize_t value)
363{
364 return (-0x2000000LL <= value) && (value <= 0x1FFFFFFLL);
365};
366
367// Returns true if 'value' is a legal signed immediate 19 bit encoding (such as for B.cond, CBNZ, CBZ).
368static bool isValidSimm19(ssize_t value)
369{
370 return (-0x40000LL <= value) && (value <= 0x3FFFFLL);
371};
372
373// Returns true if 'value' is a legal signed immediate 14 bit encoding (such as for TBNZ, TBZ).
374static bool isValidSimm14(ssize_t value)
375{
376 return (-0x2000LL <= value) && (value <= 0x1FFFLL);
377};
378
379// Returns true if 'value' represents a valid 'bitmask immediate' encoding.
380static bool isValidImmNRS(size_t value, emitAttr size)
381{
382 return (value >= 0) && (value < 0x2000);
383} // any unsigned 13-bit immediate
384
385// Returns true if 'value' represents a valid 'halfword immediate' encoding.
386static bool isValidImmHWVal(size_t value, emitAttr size)
387{
388 return (value >= 0) && (value < 0x40000);
389} // any unsigned 18-bit immediate
390
391// Returns true if 'value' represents a valid 'byteShifted immediate' encoding.
392static bool isValidImmBSVal(size_t value, emitAttr size)
393{
394 return (value >= 0) && (value < 0x800);
395} // any unsigned 11-bit immediate
396
397// The return value replaces REG_ZR with REG_SP
398static regNumber encodingZRtoSP(regNumber reg)
399{
400 return (reg == REG_ZR) ? REG_SP : reg;
401} // ZR (R31) encodes the SP register
402
403// The return value replaces REG_SP with REG_ZR
404static regNumber encodingSPtoZR(regNumber reg)
405{
406 return (reg == REG_SP) ? REG_ZR : reg;
407} // SP is encoded using ZR (R31)
408
409// For the given 'ins' returns the reverse instruction, if one exists, otherwise returns INS_INVALID
410static instruction insReverse(instruction ins);
411
412// For the given 'datasize' and 'elemsize' returns the insOpts that specifies the vector register arrangement
413static insOpts optMakeArrangement(emitAttr datasize, emitAttr elemsize);
414
415// For the given 'datasize' and 'opt' returns true if it specifies a valid vector register arrangement
416static bool isValidArrangement(emitAttr datasize, insOpts opt);
417
418// For the given 'arrangement' returns the 'datasize' specified by the vector register arrangement
419static emitAttr optGetDatasize(insOpts arrangement);
420
421// For the given 'arrangement' returns the 'elemsize' specified by the vector register arrangement
422static emitAttr optGetElemsize(insOpts arrangement);
423
424// For the given 'arrangement' returns the 'widen-arrangement' specified by the vector register arrangement
425static insOpts optWidenElemsize(insOpts arrangement);
426
427// For the given 'conversion' returns the 'dstsize' specified by the conversion option
428static emitAttr optGetDstsize(insOpts conversion);
429
430// For the given 'conversion' returns the 'srcsize' specified by the conversion option
431static emitAttr optGetSrcsize(insOpts conversion);
432
433// For the given 'datasize', 'elemsize' and 'index' returns true, if it specifies a valid 'index'
434// for an element of size 'elemsize' in a vector register of size 'datasize'
435static bool isValidVectorIndex(emitAttr datasize, emitAttr elemsize, ssize_t index);
436
437/************************************************************************/
438/* Public inline informational methods */
439/************************************************************************/
440
441public:
442// true if this 'imm' can be encoded as a input operand to a mov instruction
443static bool emitIns_valid_imm_for_mov(INT64 imm, emitAttr size);
444
445// true if this 'imm' can be encoded as a input operand to a vector movi instruction
446static bool emitIns_valid_imm_for_movi(INT64 imm, emitAttr size);
447
448// true if this 'immDbl' can be encoded as a input operand to a fmov instruction
449static bool emitIns_valid_imm_for_fmov(double immDbl);
450
451// true if this 'imm' can be encoded as a input operand to an add instruction
452static bool emitIns_valid_imm_for_add(INT64 imm, emitAttr size = EA_8BYTE);
453
454// true if this 'imm' can be encoded as a input operand to a cmp instruction
455static bool emitIns_valid_imm_for_cmp(INT64 imm, emitAttr size);
456
457// true if this 'imm' can be encoded as a input operand to an alu instruction
458static bool emitIns_valid_imm_for_alu(INT64 imm, emitAttr size);
459
460// true if this 'imm' can be encoded as the offset in a ldr/str instruction
461static bool emitIns_valid_imm_for_ldst_offset(INT64 imm, emitAttr size);
462
463// true if 'imm' can use the left shifted by 12 bits encoding
464static bool canEncodeWithShiftImmBy12(INT64 imm);
465
466// Normalize the 'imm' so that the upper bits, as defined by 'size' are zero
467static INT64 normalizeImm64(INT64 imm, emitAttr size);
468
469// Normalize the 'imm' so that the upper bits, as defined by 'size' are zero
470static INT32 normalizeImm32(INT32 imm, emitAttr size);
471
472// true if 'imm' can be encoded using a 'bitmask immediate', also returns the encoding if wbBMI is non-null
473static bool canEncodeBitMaskImm(INT64 imm, emitAttr size, emitter::bitMaskImm* wbBMI = nullptr);
474
475// true if 'imm' can be encoded using a 'halfword immediate', also returns the encoding if wbHWI is non-null
476static bool canEncodeHalfwordImm(INT64 imm, emitAttr size, emitter::halfwordImm* wbHWI = nullptr);
477
478// true if 'imm' can be encoded using a 'byteShifted immediate', also returns the encoding if wbBSI is non-null
479static bool canEncodeByteShiftedImm(INT64 imm, emitAttr size, bool allow_MSL, emitter::byteShiftedImm* wbBSI = nullptr);
480
481// true if 'immDbl' can be encoded using a 'float immediate', also returns the encoding if wbFPI is non-null
482static bool canEncodeFloatImm8(double immDbl, emitter::floatImm8* wbFPI = nullptr);
483
484// Returns the number of bits used by the given 'size'.
485inline static unsigned getBitWidth(emitAttr size)
486{
487 assert(size <= EA_8BYTE);
488 return (unsigned)size * BITS_PER_BYTE;
489}
490
491// Returns true if the imm represents a valid bit shift or bit position for the given 'size' [0..31] or [0..63]
492inline static unsigned isValidImmShift(ssize_t imm, emitAttr size)
493{
494 return (imm >= 0) && (imm < getBitWidth(size));
495}
496
497inline static bool isValidGeneralDatasize(emitAttr size)
498{
499 return (size == EA_8BYTE) || (size == EA_4BYTE);
500}
501
502inline static bool isValidScalarDatasize(emitAttr size)
503{
504 return (size == EA_8BYTE) || (size == EA_4BYTE);
505}
506
507inline static bool isValidVectorDatasize(emitAttr size)
508{
509 return (size == EA_16BYTE) || (size == EA_8BYTE);
510}
511
512inline static bool isValidGeneralLSDatasize(emitAttr size)
513{
514 return (size == EA_8BYTE) || (size == EA_4BYTE) || (size == EA_2BYTE) || (size == EA_1BYTE);
515}
516
517inline static bool isValidVectorLSDatasize(emitAttr size)
518{
519 return (size == EA_16BYTE) || (size == EA_8BYTE) || (size == EA_4BYTE) || (size == EA_2BYTE) || (size == EA_1BYTE);
520}
521
522inline static bool isValidVectorLSPDatasize(emitAttr size)
523{
524 return (size == EA_16BYTE) || (size == EA_8BYTE) || (size == EA_4BYTE);
525}
526
527inline static bool isValidVectorElemsize(emitAttr size)
528{
529 return (size == EA_8BYTE) || (size == EA_4BYTE) || (size == EA_2BYTE) || (size == EA_1BYTE);
530}
531
532inline static bool isValidVectorFcvtsize(emitAttr size)
533{
534 return (size == EA_8BYTE) || (size == EA_4BYTE) || (size == EA_2BYTE);
535}
536
537inline static bool isValidVectorElemsizeFloat(emitAttr size)
538{
539 return (size == EA_8BYTE) || (size == EA_4BYTE);
540}
541
542inline static bool isGeneralRegister(regNumber reg)
543{
544 return (reg >= REG_INT_FIRST) && (reg <= REG_LR);
545} // Excludes REG_ZR
546
547inline static bool isGeneralRegisterOrZR(regNumber reg)
548{
549 return (reg >= REG_INT_FIRST) && (reg <= REG_ZR);
550} // Includes REG_ZR
551
552inline static bool isGeneralRegisterOrSP(regNumber reg)
553{
554 return isGeneralRegister(reg) || (reg == REG_SP);
555} // Includes REG_SP, Excludes REG_ZR
556
557inline static bool isVectorRegister(regNumber reg)
558{
559 return (reg >= REG_FP_FIRST && reg <= REG_FP_LAST);
560}
561
562inline static bool isFloatReg(regNumber reg)
563{
564 return isVectorRegister(reg);
565}
566
567inline static bool insOptsNone(insOpts opt)
568{
569 return (opt == INS_OPTS_NONE);
570}
571
572inline static bool insOptsIndexed(insOpts opt)
573{
574 return (opt == INS_OPTS_PRE_INDEX) || (opt == INS_OPTS_POST_INDEX);
575}
576
577inline static bool insOptsPreIndex(insOpts opt)
578{
579 return (opt == INS_OPTS_PRE_INDEX);
580}
581
582inline static bool insOptsPostIndex(insOpts opt)
583{
584 return (opt == INS_OPTS_POST_INDEX);
585}
586
587inline static bool insOptsLSL12(insOpts opt) // special 12-bit shift only used for imm12
588{
589 return (opt == INS_OPTS_LSL12);
590}
591
592inline static bool insOptsAnyShift(insOpts opt)
593{
594 return ((opt >= INS_OPTS_LSL) && (opt <= INS_OPTS_ROR));
595}
596
597inline static bool insOptsAluShift(insOpts opt) // excludes ROR
598{
599 return ((opt >= INS_OPTS_LSL) && (opt <= INS_OPTS_ASR));
600}
601
602inline static bool insOptsVectorImmShift(insOpts opt)
603{
604 return ((opt == INS_OPTS_LSL) || (opt == INS_OPTS_MSL));
605}
606
607inline static bool insOptsLSL(insOpts opt)
608{
609 return (opt == INS_OPTS_LSL);
610}
611
612inline static bool insOptsLSR(insOpts opt)
613{
614 return (opt == INS_OPTS_LSR);
615}
616
617inline static bool insOptsASR(insOpts opt)
618{
619 return (opt == INS_OPTS_ASR);
620}
621
622inline static bool insOptsROR(insOpts opt)
623{
624 return (opt == INS_OPTS_ROR);
625}
626
627inline static bool insOptsAnyExtend(insOpts opt)
628{
629 return ((opt >= INS_OPTS_UXTB) && (opt <= INS_OPTS_SXTX));
630}
631
632inline static bool insOptsLSExtend(insOpts opt)
633{
634 return ((opt == INS_OPTS_NONE) || (opt == INS_OPTS_LSL) || (opt == INS_OPTS_UXTW) || (opt == INS_OPTS_SXTW) ||
635 (opt == INS_OPTS_UXTX) || (opt == INS_OPTS_SXTX));
636}
637
638inline static bool insOpts32BitExtend(insOpts opt)
639{
640 return ((opt == INS_OPTS_UXTW) || (opt == INS_OPTS_SXTW));
641}
642
643inline static bool insOpts64BitExtend(insOpts opt)
644{
645 return ((opt == INS_OPTS_UXTX) || (opt == INS_OPTS_SXTX));
646}
647
648inline static bool insOptsAnyArrangement(insOpts opt)
649{
650 return ((opt >= INS_OPTS_8B) && (opt <= INS_OPTS_2D));
651}
652
653inline static bool insOptsConvertFloatToFloat(insOpts opt)
654{
655 return ((opt >= INS_OPTS_S_TO_D) && (opt <= INS_OPTS_D_TO_H));
656}
657
658inline static bool insOptsConvertFloatToInt(insOpts opt)
659{
660 return ((opt >= INS_OPTS_S_TO_4BYTE) && (opt <= INS_OPTS_D_TO_8BYTE));
661}
662
663inline static bool insOptsConvertIntToFloat(insOpts opt)
664{
665 return ((opt >= INS_OPTS_4BYTE_TO_S) && (opt <= INS_OPTS_8BYTE_TO_D));
666}
667
668static bool isValidImmCond(ssize_t imm);
669static bool isValidImmCondFlags(ssize_t imm);
670static bool isValidImmCondFlagsImm5(ssize_t imm);
671
672/************************************************************************/
673/* The public entry points to output instructions */
674/************************************************************************/
675
676public:
677void emitIns(instruction ins);
678
679void emitIns_I(instruction ins, emitAttr attr, ssize_t imm);
680
681void emitIns_R(instruction ins, emitAttr attr, regNumber reg);
682
683void emitIns_R_I(instruction ins, emitAttr attr, regNumber reg, ssize_t imm, insOpts opt = INS_OPTS_NONE);
684
685void emitIns_R_F(instruction ins, emitAttr attr, regNumber reg, double immDbl, insOpts opt = INS_OPTS_NONE);
686
687void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insOpts opt = INS_OPTS_NONE);
688
689void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insFlags flags)
690{
691 emitIns_R_R(ins, attr, reg1, reg2);
692}
693
694void emitIns_R_I_I(
695 instruction ins, emitAttr attr, regNumber reg1, ssize_t imm1, ssize_t imm2, insOpts opt = INS_OPTS_NONE);
696
697void emitIns_R_R_I(
698 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, ssize_t imm, insOpts opt = INS_OPTS_NONE);
699
700// Checks for a large immediate that needs a second instruction
701void emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, ssize_t imm);
702
703void emitIns_R_R_R(
704 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insOpts opt = INS_OPTS_NONE);
705
706void emitIns_R_R_R_I(instruction ins,
707 emitAttr attr,
708 regNumber reg1,
709 regNumber reg2,
710 regNumber reg3,
711 ssize_t imm,
712 insOpts opt = INS_OPTS_NONE,
713 emitAttr attrReg2 = EA_UNKNOWN);
714
715void emitIns_R_R_R_Ext(instruction ins,
716 emitAttr attr,
717 regNumber reg1,
718 regNumber reg2,
719 regNumber reg3,
720 insOpts opt = INS_OPTS_NONE,
721 int shiftAmount = -1);
722
723void emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2);
724
725void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4);
726
727void emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond);
728
729void emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCond cond);
730
731void emitIns_R_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insCond cond);
732
733void emitIns_R_R_FLAGS_COND(
734 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCflags flags, insCond cond);
735
736void emitIns_R_I_FLAGS_COND(instruction ins, emitAttr attr, regNumber reg1, int imm, insCflags flags, insCond cond);
737
738void emitIns_BARR(instruction ins, insBarrier barrier);
739
740void emitIns_C(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fdlHnd, int offs);
741
742void emitIns_S(instruction ins, emitAttr attr, int varx, int offs);
743
744void emitIns_S_R(instruction ins, emitAttr attr, regNumber ireg, int varx, int offs);
745
746void emitIns_S_S_R_R(
747 instruction ins, emitAttr attr, emitAttr attr2, regNumber ireg, regNumber ireg2, int varx, int offs);
748
749void emitIns_R_S(instruction ins, emitAttr attr, regNumber ireg, int varx, int offs);
750
751void emitIns_R_R_S_S(
752 instruction ins, emitAttr attr, emitAttr attr2, regNumber ireg, regNumber ireg2, int varx, int offs);
753
754void emitIns_S_I(instruction ins, emitAttr attr, int varx, int offs, int val);
755
756void emitIns_R_C(
757 instruction ins, emitAttr attr, regNumber reg, regNumber tmpReg, CORINFO_FIELD_HANDLE fldHnd, int offs);
758
759void emitIns_C_R(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, regNumber reg, int offs);
760
761void emitIns_C_I(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fdlHnd, ssize_t offs, ssize_t val);
762
763void emitIns_R_L(instruction ins, emitAttr attr, BasicBlock* dst, regNumber reg);
764
765void emitIns_R_D(instruction ins, emitAttr attr, unsigned offs, regNumber reg);
766
767void emitIns_J_R(instruction ins, emitAttr attr, BasicBlock* dst, regNumber reg);
768
769void emitIns_J_R_I(instruction ins, emitAttr attr, BasicBlock* dst, regNumber reg, int imm);
770
771void emitIns_I_AR(instruction ins, emitAttr attr, int val, regNumber reg, int offs);
772
773void emitIns_R_AR(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, int offs);
774
775void emitIns_R_AI(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp);
776
777void emitIns_AR_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, int offs);
778
779void emitIns_R_ARR(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, regNumber rg2, int disp);
780
781void emitIns_ARR_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, regNumber rg2, int disp);
782
783void emitIns_R_ARX(
784 instruction ins, emitAttr attr, regNumber ireg, regNumber reg, regNumber rg2, unsigned mul, int disp);
785
786enum EmitCallType
787{
788
789 // I have included here, but commented out, all the values used by the x86 emitter.
790 // However, ARM has a much reduced instruction set, and so the ARM emitter only
791 // supports a subset of the x86 variants. By leaving them commented out, it becomes
792 // a compile time error if code tries to use them (and hopefully see this comment
793 // and know why they are unavailible on ARM), while making it easier to stay
794 // in-sync with x86 and possibly add them back in if needed.
795
796 EC_FUNC_TOKEN, // Direct call to a helper/static/nonvirtual/global method
797 // EC_FUNC_TOKEN_INDIR, // Indirect call to a helper/static/nonvirtual/global method
798 EC_FUNC_ADDR, // Direct call to an absolute address
799
800 // EC_FUNC_VIRTUAL, // Call to a virtual method (using the vtable)
801 EC_INDIR_R, // Indirect call via register
802 // EC_INDIR_SR, // Indirect call via stack-reference (local var)
803 // EC_INDIR_C, // Indirect call via static class var
804 // EC_INDIR_ARD, // Indirect call via an addressing mode
805
806 EC_COUNT
807};
808
809void emitIns_Call(EmitCallType callType,
810 CORINFO_METHOD_HANDLE methHnd,
811 INDEBUG_LDISASM_COMMA(CORINFO_SIG_INFO* sigInfo) // used to report call sites to the EE
812 void* addr,
813 ssize_t argSize,
814 emitAttr retSize,
815 emitAttr secondRetSize,
816 VARSET_VALARG_TP ptrVars,
817 regMaskTP gcrefRegs,
818 regMaskTP byrefRegs,
819 IL_OFFSETX ilOffset = BAD_IL_OFFSET,
820 regNumber ireg = REG_NA,
821 regNumber xreg = REG_NA,
822 unsigned xmul = 0,
823 ssize_t disp = 0,
824 bool isJump = false);
825
826BYTE* emitOutputLJ(insGroup* ig, BYTE* dst, instrDesc* i);
827unsigned emitOutputCall(insGroup* ig, BYTE* dst, instrDesc* i, code_t code);
828BYTE* emitOutputLoadLabel(BYTE* dst, BYTE* srcAddr, BYTE* dstAddr, instrDescJmp* id);
829BYTE* emitOutputShortBranch(BYTE* dst, instruction ins, insFormat fmt, ssize_t distVal, instrDescJmp* id);
830BYTE* emitOutputShortAddress(BYTE* dst, instruction ins, insFormat fmt, ssize_t distVal, regNumber reg);
831BYTE* emitOutputShortConstant(
832 BYTE* dst, instruction ins, insFormat fmt, ssize_t distVal, regNumber reg, emitAttr opSize);
833
834/*****************************************************************************
835 *
836 * Given an instrDesc, return true if it's a conditional jump.
837 */
838
839inline bool emitIsCondJump(instrDesc* jmp)
840{
841 return ((jmp->idInsFmt() == IF_BI_0B) || (jmp->idInsFmt() == IF_BI_1A) || (jmp->idInsFmt() == IF_BI_1B) ||
842 (jmp->idInsFmt() == IF_LARGEJMP));
843}
844
845/*****************************************************************************
846 *
847 * Given a instrDesc, return true if it's an unconditional jump.
848 */
849
850inline bool emitIsUncondJump(instrDesc* jmp)
851{
852 return (jmp->idInsFmt() == IF_BI_0A);
853}
854
855/*****************************************************************************
856 *
857 * Given a instrDesc, return true if it's a direct call.
858 */
859
860inline bool emitIsDirectCall(instrDesc* call)
861{
862 return (call->idInsFmt() == IF_BI_0C);
863}
864
865/*****************************************************************************
866 *
867 * Given a instrDesc, return true if it's a load label instruction.
868 */
869
870inline bool emitIsLoadLabel(instrDesc* jmp)
871{
872 return ((jmp->idInsFmt() == IF_DI_1E) || // adr or arp
873 (jmp->idInsFmt() == IF_LARGEADR));
874}
875
876/*****************************************************************************
877*
878* Given a instrDesc, return true if it's a load constant instruction.
879*/
880
881inline bool emitIsLoadConstant(instrDesc* jmp)
882{
883 return ((jmp->idInsFmt() == IF_LS_1A) || // ldr
884 (jmp->idInsFmt() == IF_LARGELDC));
885}
886
887#endif // _TARGET_ARM64_
888