| 1 | // Licensed to the .NET Foundation under one or more agreements. |
|---|---|
| 2 | // The .NET Foundation licenses this file to you under the MIT license. |
| 3 | // See the LICENSE file in the project root for more information. |
| 4 | |
| 5 | /***************************************************************************** |
| 6 | * Arm64 instructions for JIT compiler |
| 7 | * |
| 8 | * id -- the enum name for the instruction |
| 9 | * nm -- textual name (for assembly dipslay) |
| 10 | * fp -- floating point instruction |
| 11 | * ld/st/cmp -- load/store/compare instruction |
| 12 | * fmt -- encoding format used by this instruction |
| 13 | * e1 -- encoding 1 |
| 14 | * e2 -- encoding 2 |
| 15 | * e3 -- encoding 3 |
| 16 | * e4 -- encoding 4 |
| 17 | * e5 -- encoding 5 |
| 18 | * |
| 19 | ******************************************************************************/ |
| 20 | |
| 21 | #if !defined(_TARGET_ARM64_) |
| 22 | #error Unexpected target type |
| 23 | #endif |
| 24 | |
| 25 | #ifndef INST1 |
| 26 | #error INST1 must be defined before including this file. |
| 27 | #endif |
| 28 | #ifndef INST2 |
| 29 | #error INST2 must be defined before including this file. |
| 30 | #endif |
| 31 | #ifndef INST3 |
| 32 | #error INST3 must be defined before including this file. |
| 33 | #endif |
| 34 | #ifndef INST4 |
| 35 | #error INST4 must be defined before including this file. |
| 36 | #endif |
| 37 | #ifndef INST5 |
| 38 | #error INST5 must be defined before including this file. |
| 39 | #endif |
| 40 | #ifndef INST6 |
| 41 | #error INST6 must be defined before including this file. |
| 42 | #endif |
| 43 | #ifndef INST9 |
| 44 | #error INST9 must be defined before including this file. |
| 45 | #endif |
| 46 | |
| 47 | /*****************************************************************************/ |
| 48 | /* The following is ARM64-specific */ |
| 49 | /*****************************************************************************/ |
| 50 | |
| 51 | // If you're adding a new instruction: |
| 52 | // You need not only to fill in one of these macros describing the instruction, but also: |
| 53 | // * If the instruction writes to more than one destination register, update the function |
| 54 | // emitInsMayWriteMultipleRegs in emitArm64.cpp. |
| 55 | |
| 56 | // clang-format off |
| 57 | INST9(invalid, "INVALID", 0, 0, IF_NONE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE, BAD_CODE) |
| 58 | |
| 59 | // enum name FP LD/ST DR_2E DR_2G DI_1B DI_1D DV_3C DV_2B DV_2C DV_2E DV_2F |
| 60 | INST9(mov, "mov", 0, 0, IF_EN9, 0x2A0003E0, 0x11000000, 0x52800000, 0x320003E0, 0x0EA01C00, 0x0E003C00, 0x4E001C00, 0x5E000400, 0x6E000400) |
| 61 | // mov Rd,Rm DR_2E X0101010000mmmmm 00000011111ddddd 2A00 03E0 |
| 62 | // mov Rd,Rn DR_2G X001000100000000 000000nnnnnddddd 1100 0000 mov to/from SP only |
| 63 | // mov Rd,imm(i16,hw) DI_1B X10100101hwiiiii iiiiiiiiiiiddddd 5280 0000 imm(i16,hw) |
| 64 | // mov Rd,imm(N,r,s) DI_1D X01100100Nrrrrrr ssssss11111ddddd 3200 03E0 imm(N,r,s) |
| 65 | // mov Vd,Vn DV_3C 0Q001110101nnnnn 000111nnnnnddddd 0EA0 1C00 Vd,Vn |
| 66 | // mov Rd,Vn[0] DV_2B 0Q001110000iiiii 001111nnnnnddddd 0E00 3C00 Rd,Vn[] (to general) |
| 67 | // mov Vd[],Rn DV_2C 01001110000iiiii 000111nnnnnddddd 4E00 1C00 Vd[],Rn (from general) |
| 68 | // mov Vd,Vn[] DV_2E 01011110000iiiii 000001nnnnnddddd 5E00 0400 Vd,Vn[] (scalar by elem) |
| 69 | // mov Vd[],Vn[] DV_2F 01101110000iiiii 0jjjj1nnnnnddddd 6E00 0400 Vd[],Vn[] (from/to elem) |
| 70 | |
| 71 | // enum name FP LD/ST DR_3A DR_3B DR_3C DI_2A DV_3A DV_3E |
| 72 | INST6(add, "add", 0, 0, IF_EN6A, 0x0B000000, 0x0B000000, 0x0B200000, 0x11000000, 0x0E208400, 0x5EE08400) |
| 73 | // add Rd,Rn,Rm DR_3A X0001011000mmmmm 000000nnnnnddddd 0B00 0000 Rd,Rn,Rm |
| 74 | // add Rd,Rn,(Rm,shk,imm) DR_3B X0001011sh0mmmmm ssssssnnnnnddddd 0B00 0000 Rm {LSL,LSR,ASR} imm(0-63) |
| 75 | // add Rd,Rn,(Rm,ext,shl) DR_3C X0001011001mmmmm ooosssnnnnnddddd 0B20 0000 ext(Rm) LSL imm(0-4) |
| 76 | // add Rd,Rn,i12 DI_2A X0010001shiiiiii iiiiiinnnnnddddd 1100 0000 imm(i12,sh) |
| 77 | // add Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 100001nnnnnddddd 0E20 8400 Vd,Vn,Vm (vector) |
| 78 | // add Vd,Vn,Vm DV_3E 01011110111mmmmm 100001nnnnnddddd 5EE0 8400 Vd,Vn,Vm (scalar) |
| 79 | |
| 80 | INST6(sub, "sub", 0, 0, IF_EN6A, 0x4B000000, 0x4B000000, 0x4B200000, 0x51000000, 0x2E208400, 0x7EE08400) |
| 81 | // sub Rd,Rn,Rm DR_3A X1001011000mmmmm 000000nnnnnddddd 4B00 0000 Rd,Rn,Rm |
| 82 | // sub Rd,Rn,(Rm,shk,imm) DR_3B X1001011sh0mmmmm ssssssnnnnnddddd 4B00 0000 Rm {LSL,LSR,ASR} imm(0-63) |
| 83 | // sub Rd,Rn,(Rm,ext,shl) DR_3C X1001011001mmmmm ooosssnnnnnddddd 4B20 0000 ext(Rm) LSL imm(0-4) |
| 84 | // sub Rd,Rn,i12 DI_2A X1010001shiiiiii iiiiiinnnnnddddd 5100 0000 imm(i12,sh) |
| 85 | // sub Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 100001nnnnnddddd 2E20 8400 Vd,Vn,Vm (vector) |
| 86 | // sub Vd,Vn,Vm DV_3E 01111110111mmmmm 100001nnnnnddddd 7EE0 8400 Vd,Vn,Vm (scalar) |
| 87 | |
| 88 | // enum name FP LD/ST LS_2A LS_2B LS_2C LS_3A LS_1A |
| 89 | INST5(ldr, "ldr", 0,LD, IF_EN5A, 0xB9400000, 0xB9400000, 0xB8400000, 0xB8600800, 0x18000000) |
| 90 | // ldr Rt,[Xn] LS_2A 1X11100101000000 000000nnnnnttttt B940 0000 |
| 91 | // ldr Rt,[Xn+pimm12] LS_2B 1X11100101iiiiii iiiiiinnnnnttttt B940 0000 imm(0-4095<<{2,3}) |
| 92 | // ldr Rt,[Xn+simm9] LS_2C 1X111000010iiiii iiiiPPnnnnnttttt B840 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 93 | // ldr Rt,[Xn,(Rm,ext,shl)] LS_3A 1X111000011mmmmm oooS10nnnnnttttt B860 0800 [Xn, ext(Rm) LSL {0,2,3}] |
| 94 | // ldr Vt/Rt,[PC+simm19<<2] LS_1A XX011V00iiiiiiii iiiiiiiiiiittttt 1800 0000 [PC +- imm(1MB)] |
| 95 | |
| 96 | INST5(ldrsw, "ldrsw", 0,LD, IF_EN5A, 0xB9800000, 0xB9800000, 0xB8800000, 0xB8A00800, 0x98000000) |
| 97 | // ldrsw Rt,[Xn] LS_2A 1011100110000000 000000nnnnnttttt B980 0000 |
| 98 | // ldrsw Rt,[Xn+pimm12] LS_2B 1011100110iiiiii iiiiiinnnnnttttt B980 0000 imm(0-4095<<2) |
| 99 | // ldrsw Rt,[Xn+simm9] LS_2C 10111000100iiiii iiiiPPnnnnnttttt B880 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 100 | // ldrsw Rt,[Xn,(Rm,ext,shl)] LS_3A 10111000101mmmmm oooS10nnnnnttttt B8A0 0800 [Xn, ext(Rm) LSL {0,2}] |
| 101 | // ldrsw Rt,[PC+simm19<<2] LS_1A 10011000iiiiiiii iiiiiiiiiiittttt 9800 0000 [PC +- imm(1MB)] |
| 102 | |
| 103 | // enum name FP LD/ST DV_2G DV_2H DV_2I DV_1A DV_1B |
| 104 | INST5(fmov, "fmov", 0, 0, IF_EN5B, 0x1E204000, 0x1E260000, 0x1E270000, 0x1E201000, 0x0F00F400) |
| 105 | // fmov Vd,Vn DV_2G 000111100X100000 010000nnnnnddddd 1E20 4000 Vd,Vn (scalar) |
| 106 | // fmov Rd,Vn DV_2H X00111100X100110 000000nnnnnddddd 1E26 0000 Rd,Vn (scalar, to general) |
| 107 | // fmov Vd,Rn DV_2I X00111100X100111 000000nnnnnddddd 1E27 0000 Vd,Rn (scalar, from general) |
| 108 | // fmov Vd,immfp DV_1A 000111100X1iiiii iii10000000ddddd 1E20 1000 Vd,immfp (scalar) |
| 109 | // fmov Vd,immfp DV_1B 0QX0111100000iii 111101iiiiiddddd 0F00 F400 Vd,immfp (immediate vector) |
| 110 | |
| 111 | // enum name FP LD/ST DR_3A DR_3B DI_2C DV_3C DV_1B |
| 112 | INST5(orr, "orr", 0, 0, IF_EN5C, 0x2A000000, 0x2A000000, 0x32000000, 0x0EA01C00, 0x0F001400) |
| 113 | // orr Rd,Rn,Rm DR_3A X0101010000mmmmm 000000nnnnnddddd 2A00 0000 |
| 114 | // orr Rd,Rn,(Rm,shk,imm) DR_3B X0101010sh0mmmmm iiiiiinnnnnddddd 2A00 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 115 | // orr Rd,Rn,imm(N,r,s) DI_2C X01100100Nrrrrrr ssssssnnnnnddddd 3200 0000 imm(N,r,s) |
| 116 | // orr Vd,Vn,Vm DV_3C 0Q001110101mmmmm 000111nnnnnddddd 0EA0 1C00 Vd,Vn,Vm |
| 117 | // orr Vd,imm8 DV_1B 0Q00111100000iii ---101iiiiiddddd 0F00 1400 Vd imm8 (immediate vector) |
| 118 | |
| 119 | // enum name FP LD/ST LS_2A LS_2B LS_2C LS_3A |
| 120 | INST4(ldrb, "ldrb", 0,LD, IF_EN4A, 0x39400000, 0x39400000, 0x38400000, 0x38600800) |
| 121 | // ldrb Rt,[Xn] LS_2A 0011100101000000 000000nnnnnttttt 3940 0000 |
| 122 | // ldrb Rt,[Xn+pimm12] LS_2B 0011100101iiiiii iiiiiinnnnnttttt 3940 0000 imm(0-4095) |
| 123 | // ldrb Rt,[Xn+simm9] LS_2C 00111000010iiiii iiiiPPnnnnnttttt 3840 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 124 | // ldrb Rt,[Xn,(Rm,ext,shl)] LS_3A 00111000011mmmmm oooS10nnnnnttttt 3860 0800 [Xn, ext(Rm)] |
| 125 | |
| 126 | INST4(ldrh, "ldrh", 0,LD, IF_EN4A, 0x79400000, 0x79400000, 0x78400000, 0x78600800) |
| 127 | // ldrh Rt,[Xn] LS_2A 0111100101000000 000000nnnnnttttt 7940 0000 |
| 128 | // ldrh Rt,[Xn+pimm12] LS_2B 0111100101iiiiii iiiiiinnnnnttttt 7940 0000 imm(0-4095<<1) |
| 129 | // ldrh Rt,[Xn+simm9] LS_2C 01111000010iiiii iiiiPPnnnnnttttt 7840 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 130 | // ldrh Rt,[Xn,(Rm,ext,shl)] LS_3A 01111000011mmmmm oooS10nnnnnttttt 7860 0800 [Xn, ext(Rm) LSL {0,1}] |
| 131 | |
| 132 | INST4(ldrsb, "ldrsb", 0,LD, IF_EN4A, 0x39800000, 0x39800000, 0x38800000, 0x38A00800) |
| 133 | // ldrsb Rt,[Xn] LS_2A 001110011X000000 000000nnnnnttttt 3980 0000 |
| 134 | // ldrsb Rt,[Xn+pimm12] LS_2B 001110011Xiiiiii iiiiiinnnnnttttt 3980 0000 imm(0-4095) |
| 135 | // ldrsb Rt,[Xn+simm9] LS_2C 001110001X0iiiii iiii01nnnnnttttt 3880 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 136 | // ldrsb Rt,[Xn,(Rm,ext,shl)] LS_3A 001110001X1mmmmm oooS10nnnnnttttt 38A0 0800 [Xn, ext(Rm)] |
| 137 | |
| 138 | INST4(ldrsh, "ldrsh", 0,LD, IF_EN4A, 0x79800000, 0x79800000, 0x78800000, 0x78A00800) |
| 139 | // ldrsh Rt,[Xn] LS_2A 011110011X000000 000000nnnnnttttt 7980 0000 |
| 140 | // ldrsh Rt,[Xn+pimm12] LS_2B 011110011Xiiiiii iiiiiinnnnnttttt 7980 0000 imm(0-4095<<1) |
| 141 | // ldrsh Rt,[Xn+simm9] LS_2C 011110001X0iiiii iiiiPPnnnnnttttt 7880 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 142 | // ldrsh Rt,[Xn,(Rm,ext,shl)] LS_3A 011110001X1mmmmm oooS10nnnnnttttt 78A0 0800 [Xn, ext(Rm) LSL {0,1}] |
| 143 | |
| 144 | INST4(str, "str", 0,ST, IF_EN4A, 0xB9000000, 0xB9000000, 0xB8000000, 0xB8200800) |
| 145 | // str Rt,[Xn] LS_2A 1X11100100000000 000000nnnnnttttt B900 0000 |
| 146 | // str Rt,[Xn+pimm12] LS_2B 1X11100100iiiiii iiiiiinnnnnttttt B900 0000 imm(0-4095<<{2,3}) |
| 147 | // str Rt,[Xn+simm9] LS_2C 1X111000000iiiii iiiiPPnnnnnttttt B800 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 148 | // str Rt,[Xn,(Rm,ext,shl)] LS_3A 1X111000001mmmmm oooS10nnnnnttttt B820 0800 [Xn, ext(Rm)] |
| 149 | |
| 150 | INST4(strb, "strb", 0,ST, IF_EN4A, 0x39000000, 0x39000000, 0x38000000, 0x38200800) |
| 151 | // strb Rt,[Xn] LS_2A 0011100100000000 000000nnnnnttttt 3900 0000 |
| 152 | // strb Rt,[Xn+pimm12] LS_2B 0011100100iiiiii iiiiiinnnnnttttt 3900 0000 imm(0-4095) |
| 153 | // strb Rt,[Xn+simm9] LS_2C 00111000000iiiii iiiiPPnnnnnttttt 3800 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 154 | // strb Rt,[Xn,(Rm,ext,shl)] LS_3A 00111000001mmmmm oooS10nnnnnttttt 3820 0800 [Xn, ext(Rm)] |
| 155 | |
| 156 | INST4(strh, "strh", 0,ST, IF_EN4A, 0x79000000, 0x79000000, 0x78000000, 0x78200800) |
| 157 | // strh Rt,[Xn] LS_2A 0111100100000000 000000nnnnnttttt 7900 0000 |
| 158 | // strh Rt,[Xn+pimm12] LS_2B 0111100100iiiiii iiiiiinnnnnttttt 7900 0000 imm(0-4095<<1) |
| 159 | // strh Rt,[Xn+simm9] LS_2C 01111000000iiiii iiiiPPnnnnnttttt 7800 0000 [Xn imm(-256..+255) pre/post/no inc] |
| 160 | // strh Rt,[Xn,(Rm,ext,shl)] LS_3A 01111000001mmmmm oooS10nnnnnttttt 7820 0800 [Xn, ext(Rm)] |
| 161 | |
| 162 | // enum name FP LD/ST DR_3A DR_3B DR_3C DI_2A |
| 163 | INST4(adds, "adds", 0, 0, IF_EN4B, 0x2B000000, 0x2B000000, 0x2B200000, 0x31000000) |
| 164 | // adds Rd,Rn,Rm DR_3A X0101011000mmmmm 000000nnnnnddddd 2B00 0000 |
| 165 | // adds Rd,Rn,(Rm,shk,imm) DR_3B X0101011sh0mmmmm ssssssnnnnnddddd 2B00 0000 Rm {LSL,LSR,ASR} imm(0-63) |
| 166 | // adds Rd,Rn,(Rm,ext,shl) DR_3C X0101011001mmmmm ooosssnnnnnddddd 2B20 0000 ext(Rm) LSL imm(0-4) |
| 167 | // adds Rd,Rn,i12 DI_2A X0110001shiiiiii iiiiiinnnnnddddd 3100 0000 imm(i12,sh) |
| 168 | |
| 169 | INST4(subs, "subs", 0, 0, IF_EN4B, 0x6B000000, 0x6B000000, 0x6B200000, 0x71000000) |
| 170 | // subs Rd,Rn,Rm DR_3A X1101011000mmmmm 000000nnnnnddddd 6B00 0000 |
| 171 | // subs Rd,Rn,(Rm,shk,imm) DR_3B X1101011sh0mmmmm ssssssnnnnnddddd 6B00 0000 Rm {LSL,LSR,ASR} imm(0-63) |
| 172 | // subs Rd,Rn,(Rm,ext,shl) DR_3C X1101011001mmmmm ooosssnnnnnddddd 6B20 0000 ext(Rm) LSL imm(0-4) |
| 173 | // subs Rd,Rn,i12 DI_2A X1110001shiiiiii iiiiiinnnnnddddd 7100 0000 imm(i12,sh) |
| 174 | |
| 175 | // enum name FP LD/ST DR_2A DR_2B DR_2C DI_1A |
| 176 | INST4(cmp, "cmp", 0,CMP,IF_EN4C, 0x6B00001F, 0x6B00001F, 0x6B20001F, 0x7100001F) |
| 177 | // cmp Rn,Rm DR_2A X1101011000mmmmm 000000nnnnn11111 6B00 001F |
| 178 | // cmp Rn,(Rm,shk,imm) DR_2B X1101011sh0mmmmm ssssssnnnnn11111 6B00 001F Rm {LSL,LSR,ASR} imm(0-63) |
| 179 | // cmp Rn,(Rm,ext,shl) DR_2C X1101011001mmmmm ooosssnnnnn11111 6B20 001F ext(Rm) LSL imm(0-4) |
| 180 | // cmp Rn,i12 DI_1A X111000100iiiiii iiiiiinnnnn11111 7100 001F imm(i12,sh) |
| 181 | |
| 182 | INST4(cmn, "cmn", 0,CMP,IF_EN4C, 0x2B00001F, 0x2B00001F, 0x2B20001F, 0x3100001F) |
| 183 | // cmn Rn,Rm DR_2A X0101011000mmmmm 000000nnnnn11111 2B00 001F |
| 184 | // cmn Rn,(Rm,shk,imm) DR_2B X0101011sh0mmmmm ssssssnnnnn11111 2B00 001F Rm {LSL,LSR,ASR} imm(0-63) |
| 185 | // cmn Rn,(Rm,ext,shl) DR_2C X0101011001mmmmm ooosssnnnnn11111 2B20 001F ext(Rm) LSL imm(0-4) |
| 186 | // cmn Rn,i12 DI_1A X0110001shiiiiii iiiiiinnnnn11111 3100 001F imm(0-4095) |
| 187 | |
| 188 | // enum name FP LD/ST DV_3B DV_3D DV_3BI DV_3DI |
| 189 | INST4(fmul, "fmul", 0, 0, IF_EN4D, 0x2E20DC00, 0x1E200800, 0x0F809000, 0x5F809000) |
| 190 | // fmul Vd,Vn,Vm DV_3B 0Q1011100X1mmmmm 110111nnnnnddddd 2E20 DC00 Vd,Vn,Vm (vector) |
| 191 | // fmul Vd,Vn,Vm DV_3D 000111100X1mmmmm 000010nnnnnddddd 1E20 0800 Vd,Vn,Vm (scalar) |
| 192 | // fmul Vd,Vn,Vm[] DV_3BI 0Q0011111XLmmmmm 1001H0nnnnnddddd 0F80 9000 Vd,Vn,Vm[] (vector by elem) |
| 193 | // fmul Vd,Vn,Vm[] DV_3DI 010111111XLmmmmm 1001H0nnnnnddddd 5F80 9000 Vd,Vn,Vm[] (scalar by elem) |
| 194 | |
| 195 | INST4(fmulx, "fmulx", 0, 0, IF_EN4D, 0x0E20DC00, 0x5E20DC00, 0x2F809000, 0x7F809000) |
| 196 | // fmulx Vd,Vn,Vm DV_3B 0Q0011100X1mmmmm 110111nnnnnddddd 0E20 DC00 Vd,Vn,Vm (vector) |
| 197 | // fmulx Vd,Vn,Vm DV_3D 010111100X1mmmmm 110111nnnnnddddd 5E20 DC00 Vd,Vn,Vm (scalar) |
| 198 | // fmulx Vd,Vn,Vm[] DV_3BI 0Q1011111XLmmmmm 1001H0nnnnnddddd 2F80 9000 Vd,Vn,Vm[] (vector by elem) |
| 199 | // fmulx Vd,Vn,Vm[] DV_3DI 011111111XLmmmmm 1001H0nnnnnddddd 7F80 9000 Vd,Vn,Vm[] (scalar by elem) |
| 200 | |
| 201 | // enum name FP LD/ST DR_3A DR_3B DI_2C DV_3C |
| 202 | INST4(and, "and", 0, 0, IF_EN4E, 0x0A000000, 0x0A000000, 0x12000000, 0x0E201C00) |
| 203 | // and Rd,Rn,Rm DR_3A X0001010000mmmmm 000000nnnnnddddd 0A00 0000 |
| 204 | // and Rd,Rn,(Rm,shk,imm) DR_3B X0001010sh0mmmmm iiiiiinnnnnddddd 0A00 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 205 | // and Rd,Rn,imm(N,r,s) DI_2C X00100100Nrrrrrr ssssssnnnnnddddd 1200 0000 imm(N,r,s) |
| 206 | // and Vd,Vn,Vm DV_3C 0Q001110001mmmmm 000111nnnnnddddd 0E20 1C00 Vd,Vn,Vm |
| 207 | |
| 208 | INST4(eor, "eor", 0, 0, IF_EN4E, 0x4A000000, 0x4A000000, 0x52000000, 0x2E201C00) |
| 209 | // eor Rd,Rn,Rm DR_3A X1001010000mmmmm 000000nnnnnddddd 4A00 0000 |
| 210 | // eor Rd,Rn,(Rm,shk,imm) DR_3B X1001010sh0mmmmm iiiiiinnnnnddddd 4A00 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 211 | // eor Rd,Rn,imm(N,r,s) DI_2C X10100100Nrrrrrr ssssssnnnnnddddd 5200 0000 imm(N,r,s) |
| 212 | // eor Vd,Vn,Vm DV_3C 0Q101110001mmmmm 000111nnnnnddddd 2E20 1C00 Vd,Vn,Vm |
| 213 | |
| 214 | // enum name FP LD/ST DR_3A DR_3B DV_3C DV_1B |
| 215 | INST4(bic, "bic", 0, 0, IF_EN4F, 0x0A200000, 0x0A200000, 0x0E601C00, 0x2F001400) |
| 216 | // bic Rd,Rn,Rm DR_3A X0001010001mmmmm 000000nnnnnddddd 0A20 0000 |
| 217 | // bic Rd,Rn,(Rm,shk,imm) DR_3B X0001010sh1mmmmm iiiiiinnnnnddddd 0A20 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 218 | // bic Vd,Vn,Vm DV_3C 0Q001110011mmmmm 000111nnnnnddddd 0E60 1C00 Vd,Vn,Vm |
| 219 | // bic Vd,imm8 DV_1B 0Q10111100000iii ---101iiiiiddddd 2F00 1400 Vd imm8 (immediate vector) |
| 220 | |
| 221 | // enum name FP LD/ST DR_2E DR_2F DV_2M DV_2L |
| 222 | INST4(neg, "neg", 0, 0, IF_EN4G, 0x4B0003E0, 0x4B0003E0, 0x2E20B800, 0x7E20B800) |
| 223 | // neg Rd,Rm DR_2E X1001011000mmmmm 00000011111ddddd 4B00 03E0 |
| 224 | // neg Rd,(Rm,shk,imm) DR_2F X1001011sh0mmmmm ssssss11111ddddd 4B00 03E0 Rm {LSL,LSR,ASR} imm(0-63) |
| 225 | // neg Vd,Vn DV_2M 0Q101110XX100000 101110nnnnnddddd 2E20 B800 Vd,Vn (vector) |
| 226 | // neg Vd,Vn DV_2L 01111110XX100000 101110nnnnnddddd 7E20 B800 Vd,Vn (scalar) |
| 227 | |
| 228 | // enum name FP LD/ST DV_3E DV_3A DV_2L DV_2M |
| 229 | INST4(cmeq, "cmeq", 0, 0, IF_EN4H, 0x7EE08C00, 0x2E208C00, 0x5E209800, 0x0E209800) |
| 230 | // cmeq Vd,Vn,Vm DV_3E 01111110111mmmmm 100011nnnnnddddd 7EE0 8C00 Vd,Vn,Vm (scalar) |
| 231 | // cmeq Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 100011nnnnnddddd 2E20 8C00 Vd,Vn,Vm (vector) |
| 232 | // cmeq Vd,Vn DV_2L 01011110XX100000 100110nnnnnddddd 5E20 9800 Vd,Vn (scalar) |
| 233 | // cmeq Vd,Vn DV_2M 0Q001110XX100000 100110nnnnnddddd 0E20 9800 Vd,Vn (vector) |
| 234 | |
| 235 | INST4(cmge, "cmge", 0, 0, IF_EN4H, 0x5EE03C00, 0x0E203C00, 0x7E208800, 0x2E208800) |
| 236 | // cmge Vd,Vn,Vm DV_3E 01011110111mmmmm 001111nnnnnddddd 5EE0 3C00 Vd,Vn,Vm (scalar) |
| 237 | // cmge Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 001111nnnnnddddd 0E20 3C00 Vd,Vn,Vm (vector) |
| 238 | // cmge Vd,Vn DV_2L 01111110XX100000 100010nnnnnddddd 5E20 8800 Vd,Vn (scalar) |
| 239 | // cmge Vd,Vn DV_2M 0Q101110XX100000 100010nnnnnddddd 2E20 8800 Vd,Vn (vector) |
| 240 | |
| 241 | INST4(cmgt, "cmgt", 0, 0, IF_EN4H, 0x5EE03400, 0x0E203400, 0x5E208800, 0x0E208800) |
| 242 | // cmgt Vd,Vn,Vm DV_3E 01011110111mmmmm 001101nnnnnddddd 5EE0 3400 Vd,Vn,Vm (scalar) |
| 243 | // cmgt Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 001101nnnnnddddd 0E20 3400 Vd,Vn,Vm (vector) |
| 244 | // cmgt Vd,Vn DV_2L 01011110XX100000 100010nnnnnddddd 5E20 8800 Vd,Vn (scalar) |
| 245 | // cmgt Vd,Vn DV_2M 0Q001110XX100000 101110nnnnnddddd 0E20 8800 Vd,Vn (vector) |
| 246 | |
| 247 | // enum name FP LD/ST DV_3D DV_3B DV_2G DV_2A |
| 248 | INST4(fcmeq, "fcmeq", 0, 0, IF_EN4I, 0x5E20E400, 0x0E20E400, 0x5EA0D800, 0x0EA0D800) |
| 249 | // fcmeq Vd,Vn,Vm DV_3D 010111100X1mmmmm 111001nnnnnddddd 5E20 E400 Vd Vn Vm (scalar) |
| 250 | // fcmeq Vd,Vn,Vm DV_3B 0Q0011100X1mmmmm 111001nnnnnddddd 0E20 E400 Vd,Vn,Vm (vector) |
| 251 | // fcmeq Vd,Vn DV_2G 010111101X100000 110110nnnnnddddd 5EA0 D800 Vd Vn (scalar) |
| 252 | // fcmeq Vd,Vn DV_2A 0Q0011101X100000 110110nnnnnddddd 0EA0 D800 Vd Vn (vector) |
| 253 | |
| 254 | INST4(fcmge, "fcmge", 0, 0, IF_EN4I, 0x7E20E400, 0x2E20E400, 0x7EA0C800, 0x2EA0C800) |
| 255 | // fcmge Vd,Vn,Vm DV_3D 011111100X1mmmmm 111001nnnnnddddd 7E20 E400 Vd Vn Vm (scalar) |
| 256 | // fcmge Vd,Vn,Vm DV_3B 0Q1011100X1mmmmm 111001nnnnnddddd 2E20 E400 Vd,Vn,Vm (vector) |
| 257 | // fcmge Vd,Vn DV_2G 011111101X100000 110010nnnnnddddd 7EA0 E800 Vd Vn (scalar) |
| 258 | // fcmge Vd,Vn DV_2A 0Q1011101X100000 110010nnnnnddddd 2EA0 C800 Vd Vn (vector) |
| 259 | |
| 260 | INST4(fcmgt, "fcmgt", 0, 0, IF_EN4I, 0x7EA0E400, 0x2EA0E400, 0x5EA0C800, 0x0EA0C800) |
| 261 | // fcmgt Vd,Vn,Vm DV_3D 011111101X1mmmmm 111001nnnnnddddd 7EA0 E400 Vd Vn Vm (scalar) |
| 262 | // fcmgt Vd,Vn,Vm DV_3B 0Q1011101X1mmmmm 111001nnnnnddddd 2EA0 E400 Vd,Vn,Vm (vector) |
| 263 | // fcmgt Vd,Vn DV_2G 010111101X100000 110010nnnnnddddd 5EA0 E800 Vd Vn (scalar) |
| 264 | // fcmgt Vd,Vn DV_2A 0Q0011101X100000 110010nnnnnddddd 0EA0 C800 Vd Vn (vector) |
| 265 | |
| 266 | // enum name FP LD/ST DR_3A DR_3B DI_2C |
| 267 | INST3(ands, "ands", 0, 0, IF_EN3A, 0x6A000000, 0x6A000000, 0x72000000) |
| 268 | // ands Rd,Rn,Rm DR_3A X1101010000mmmmm 000000nnnnnddddd 6A00 0000 |
| 269 | // ands Rd,Rn,(Rm,shk,imm) DR_3B X1101010sh0mmmmm iiiiiinnnnnddddd 6A00 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 270 | // ands Rd,Rn,imm(N,r,s) DI_2C X11100100Nrrrrrr ssssssnnnnnddddd 7200 0000 imm(N,r,s) |
| 271 | |
| 272 | // enum name FP LD/ST DR_2A DR_2B DI_1C |
| 273 | INST3(tst, "tst", 0, 0, IF_EN3B, 0x6A00001F, 0x6A00001F, 0x7200001F) |
| 274 | // tst Rn,Rm DR_2A X1101010000mmmmm 000000nnnnn11111 6A00 001F |
| 275 | // tst Rn,(Rm,shk,imm) DR_2B X1101010sh0mmmmm iiiiiinnnnn11111 6A00 001F Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 276 | // tst Rn,imm(N,r,s) DI_1C X11100100Nrrrrrr ssssssnnnnn11111 7200 001F imm(N,r,s) |
| 277 | |
| 278 | // enum name FP LD/ST DR_3A DR_3B DV_3C |
| 279 | INST3(orn, "orn", 0, 0, IF_EN3C, 0x2A200000, 0x2A200000, 0x0EE01C00) |
| 280 | // orn Rd,Rn,Rm DR_3A X0101010001mmmmm 000000nnnnnddddd 2A20 0000 |
| 281 | // orn Rd,Rn,(Rm,shk,imm) DR_3B X0101010sh1mmmmm iiiiiinnnnnddddd 2A20 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 282 | // orn Vd,Vn,Vm DV_3C 0Q001110111mmmmm 000111nnnnnddddd 0EE0 1C00 Vd,Vn,Vm |
| 283 | |
| 284 | // enum name FP LD/ST DV_2C DV_2D DV_2E |
| 285 | INST3(dup, "dup", 0, 0, IF_EN3D, 0x0E000C00, 0x0E000400, 0x5E000400) |
| 286 | // dup Vd,Rn DV_2C 0Q001110000iiiii 000011nnnnnddddd 0E00 0C00 Vd,Rn (vector from general) |
| 287 | // dup Vd,Vn[] DV_2D 0Q001110000iiiii 000001nnnnnddddd 0E00 0400 Vd,Vn[] (vector by elem) |
| 288 | // dup Vd,Vn[] DV_2E 01011110000iiiii 000001nnnnnddddd 5E00 0400 Vd,Vn[] (scalar by elem) |
| 289 | |
| 290 | // enum name FP LD/ST DV_3B DV_3BI DV_3DI |
| 291 | INST3(fmla, "fmla", 0, 0, IF_EN3E, 0x0E20CC00, 0x0F801000, 0x5F801000) |
| 292 | // fmla Vd,Vn,Vm DV_3B 0Q0011100X1mmmmm 110011nnnnnddddd 0E20 CC00 Vd,Vn,Vm (vector) |
| 293 | // fmla Vd,Vn,Vm[] DV_3BI 0Q0011111XLmmmmm 0001H0nnnnnddddd 0F80 1000 Vd,Vn,Vm[] (vector by elem) |
| 294 | // fmla Vd,Vn,Vm[] DV_3DI 010111111XLmmmmm 0001H0nnnnnddddd 5F80 1000 Vd,Vn,Vm[] (scalar by elem) |
| 295 | |
| 296 | INST3(fmls, "fmls", 0, 0, IF_EN3E, 0x0EA0CC00, 0x0F805000, 0x5F805000) |
| 297 | // fmls Vd,Vn,Vm DV_3B 0Q0011101X1mmmmm 110011nnnnnddddd 0EA0 CC00 Vd,Vn,Vm (vector) |
| 298 | // fmls Vd,Vn,Vm[] DV_3BI 0Q0011111XLmmmmm 0101H0nnnnnddddd 0F80 5000 Vd,Vn,Vm[] (vector by elem) |
| 299 | // fmls Vd,Vn,Vm[] DV_3DI 010111111XLmmmmm 0101H0nnnnnddddd 5F80 5000 Vd,Vn,Vm[] (scalar by elem) |
| 300 | |
| 301 | // enum name FP LD/ST DV_2A DV_2G DV_2H |
| 302 | INST3(fcvtas, "fcvtas", 0, 0, IF_EN3F, 0x0E21C800, 0x5E21C800, 0x1E240000) |
| 303 | // fcvtas Vd,Vn DV_2A 0Q0011100X100001 110010nnnnnddddd 0E21 C800 Vd,Vn (vector) |
| 304 | // fcvtas Vd,Vn DV_2G 010111100X100001 110010nnnnnddddd 5E21 C800 Vd,Vn (scalar) |
| 305 | // fcvtas Rd,Vn DV_2H X00111100X100100 000000nnnnnddddd 1E24 0000 Rd,Vn (scalar, to general) |
| 306 | |
| 307 | INST3(fcvtau, "fcvtau", 0, 0, IF_EN3F, 0x2E21C800, 0x7E21C800, 0x1E250000) |
| 308 | // fcvtau Vd,Vn DV_2A 0Q1011100X100001 111010nnnnnddddd 2E21 C800 Vd,Vn (vector) |
| 309 | // fcvtau Vd,Vn DV_2G 011111100X100001 111010nnnnnddddd 7E21 C800 Vd,Vn (scalar) |
| 310 | // fcvtau Rd,Vn DV_2H X00111100X100101 000000nnnnnddddd 1E25 0000 Rd,Vn (scalar, to general) |
| 311 | |
| 312 | INST3(fcvtms, "fcvtms", 0, 0, IF_EN3F, 0x0E21B800, 0x5E21B800, 0x1E300000) |
| 313 | // fcvtms Vd,Vn DV_2A 0Q0011100X100001 101110nnnnnddddd 0E21 B800 Vd,Vn (vector) |
| 314 | // fcvtms Vd,Vn DV_2G 010111100X100001 101110nnnnnddddd 5E21 B800 Vd,Vn (scalar) |
| 315 | // fcvtms Rd,Vn DV_2H X00111100X110000 000000nnnnnddddd 1E30 0000 Rd,Vn (scalar, to general) |
| 316 | |
| 317 | INST3(fcvtmu, "fcvtmu", 0, 0, IF_EN3F, 0x2E21B800, 0x7E21B800, 0x1E310000) |
| 318 | // fcvtmu Vd,Vn DV_2A 0Q1011100X100001 101110nnnnnddddd 2E21 B800 Vd,Vn (vector) |
| 319 | // fcvtmu Vd,Vn DV_2G 011111100X100001 101110nnnnnddddd 7E21 B800 Vd,Vn (scalar) |
| 320 | // fcvtmu Rd,Vn DV_2H X00111100X110001 000000nnnnnddddd 1E31 0000 Rd,Vn (scalar, to general) |
| 321 | |
| 322 | INST3(fcvtns, "fcvtns", 0, 0, IF_EN3F, 0x0E21A800, 0x5E21A800, 0x1E200000) |
| 323 | // fcvtns Vd,Vn DV_2A 0Q0011100X100001 101010nnnnnddddd 0E21 A800 Vd,Vn (vector) |
| 324 | // fcvtns Vd,Vn DV_2G 010111100X100001 101010nnnnnddddd 5E21 A800 Vd,Vn (scalar) |
| 325 | // fcvtns Rd,Vn DV_2H X00111100X100000 000000nnnnnddddd 1E20 0000 Rd,Vn (scalar, to general) |
| 326 | |
| 327 | INST3(fcvtnu, "fcvtnu", 0, 0, IF_EN3F, 0x2E21A800, 0x7E21A800, 0x1E210000) |
| 328 | // fcvtnu Vd,Vn DV_2A 0Q1011100X100001 101010nnnnnddddd 2E21 A800 Vd,Vn (vector) |
| 329 | // fcvtnu Vd,Vn DV_2G 011111100X100001 101010nnnnnddddd 7E21 A800 Vd,Vn (scalar) |
| 330 | // fcvtnu Rd,Vn DV_2H X00111100X100001 000000nnnnnddddd 1E21 0000 Rd,Vn (scalar, to general) |
| 331 | |
| 332 | INST3(fcvtps, "fcvtps", 0, 0, IF_EN3F, 0x0EA1A800, 0x5EA1A800, 0x1E280000) |
| 333 | // fcvtps Vd,Vn DV_2A 0Q0011101X100001 101010nnnnnddddd 0EA1 A800 Vd,Vn (vector) |
| 334 | // fcvtps Vd,Vn DV_2G 010111101X100001 101010nnnnnddddd 5EA1 A800 Vd,Vn (scalar) |
| 335 | // fcvtps Rd,Vn DV_2H X00111100X101000 000000nnnnnddddd 1E28 0000 Rd,Vn (scalar, to general) |
| 336 | |
| 337 | INST3(fcvtpu, "fcvtpu", 0, 0, IF_EN3F, 0x2EA1A800, 0x7EA1A800, 0x1E290000) |
| 338 | // fcvtpu Vd,Vn DV_2A 0Q1011101X100001 101010nnnnnddddd 2EA1 A800 Vd,Vn (vector) |
| 339 | // fcvtpu Vd,Vn DV_2G 011111101X100001 101010nnnnnddddd 7EA1 A800 Vd,Vn (scalar) |
| 340 | // fcvtpu Rd,Vn DV_2H X00111100X101001 000000nnnnnddddd 1E29 0000 Rd,Vn (scalar, to general) |
| 341 | |
| 342 | INST3(fcvtzs, "fcvtzs", 0, 0, IF_EN3F, 0x0EA1B800, 0x5EA1B800, 0x1E380000) |
| 343 | // fcvtzs Vd,Vn DV_2A 0Q0011101X100001 101110nnnnnddddd 0EA1 B800 Vd,Vn (vector) |
| 344 | // fcvtzs Vd,Vn DV_2G 010111101X100001 101110nnnnnddddd 5EA1 B800 Vd,Vn (scalar) |
| 345 | // fcvtzs Rd,Vn DV_2H X00111100X111000 000000nnnnnddddd 1E38 0000 Rd,Vn (scalar, to general) |
| 346 | |
| 347 | INST3(fcvtzu, "fcvtzu", 0, 0, IF_EN3F, 0x2EA1B800, 0x7EA1B800, 0x1E390000) |
| 348 | // fcvtzu Vd,Vn DV_2A 0Q1011101X100001 101110nnnnnddddd 2EA1 B800 Vd,Vn (vector) |
| 349 | // fcvtzu Vd,Vn DV_2G 011111101X100001 101110nnnnnddddd 7EA1 B800 Vd,Vn (scalar) |
| 350 | // fcvtzu Rd,Vn DV_2H X00111100X111001 000000nnnnnddddd 1E39 0000 Rd,Vn (scalar, to general) |
| 351 | |
| 352 | // enum name FP LD/ST DV_2A DV_2G DV_2I |
| 353 | INST3(scvtf, "scvtf", 0, 0, IF_EN3G, 0x0E21D800, 0x5E21D800, 0x1E220000) |
| 354 | // scvtf Vd,Vn DV_2A 0Q0011100X100001 110110nnnnnddddd 0E21 D800 Vd,Vn (vector) |
| 355 | // scvtf Vd,Vn DV_2G 010111100X100001 110110nnnnnddddd 7E21 D800 Vd,Vn (scalar) |
| 356 | // scvtf Rd,Vn DV_2I X00111100X100010 000000nnnnnddddd 1E22 0000 Vd,Rn (scalar, from general) |
| 357 | |
| 358 | INST3(ucvtf, "ucvtf", 0, 0, IF_EN3G, 0x2E21D800, 0x7E21D800, 0x1E230000) |
| 359 | // ucvtf Vd,Vn DV_2A 0Q1011100X100001 110110nnnnnddddd 2E21 D800 Vd,Vn (vector) |
| 360 | // ucvtf Vd,Vn DV_2G 011111100X100001 110110nnnnnddddd 7E21 D800 Vd,Vn (scalar) |
| 361 | // ucvtf Rd,Vn DV_2I X00111100X100011 000000nnnnnddddd 1E23 0000 Vd,Rn (scalar, from general) |
| 362 | |
| 363 | INST3(mul, "mul", 0, 0, IF_EN3H, 0x1B007C00, 0x0E209C00, 0x0F008000) |
| 364 | // mul Rd,Rn,Rm DR_3A X0011011000mmmmm 011111nnnnnddddd 1B00 7C00 |
| 365 | // mul Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 100111nnnnnddddd 0E20 9C00 Vd,Vn,Vm (vector) |
| 366 | // mul Vd,Vn,Vm[] DV_3AI 0Q001111XXLMmmmm 1000H0nnnnnddddd 0F00 8000 Vd,Vn,Vm[] (vector by elem) |
| 367 | |
| 368 | // enum name FP LD/ST DR_2E DR_2F DV_2M |
| 369 | INST3(mvn, "mvn", 0, 0, IF_EN3I, 0x2A2003E0, 0x2A2003E0, 0x2E205800) |
| 370 | // mvn Rd,Rm DR_2E X0101010001mmmmm 00000011111ddddd 2A20 03E0 |
| 371 | // mvn Rd,(Rm,shk,imm) DR_2F X0101010sh1mmmmm iiiiii11111ddddd 2A20 03E0 Rm {LSL,LSR,ASR} imm(0-63) |
| 372 | // mvn Vd,Vn DV_2M 0Q10111000100000 010110nnnnnddddd 2E20 5800 Vd,Vn (vector) |
| 373 | |
| 374 | |
| 375 | // enum name FP LD/ST DR_2E DR_2F |
| 376 | INST2(negs, "negs", 0, 0, IF_EN2A, 0x6B0003E0, 0x6B0003E0) |
| 377 | // negs Rd,Rm DR_2E X1101011000mmmmm 00000011111ddddd 6B00 03E0 |
| 378 | // negs Rd,(Rm,shk,imm) DR_2F X1101011sh0mmmmm ssssss11111ddddd 6B00 03E0 Rm {LSL,LSR,ASR} imm(0-63) |
| 379 | |
| 380 | // enum name FP LD/ST DR_3A DR_3B |
| 381 | INST2(bics, "bics", 0, 0, IF_EN2B, 0x6A200000, 0x6A200000) |
| 382 | // bics Rd,Rn,Rm DR_3A X1101010001mmmmm 000000nnnnnddddd 6A20 0000 |
| 383 | // bics Rd,Rn,(Rm,shk,imm) DR_3B X1101010sh1mmmmm iiiiiinnnnnddddd 6A20 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 384 | |
| 385 | INST2(eon, "eon", 0, 0, IF_EN2B, 0x4A200000, 0x4A200000) |
| 386 | // eon Rd,Rn,Rm DR_3A X1001010001mmmmm 000000nnnnnddddd 4A20 0000 |
| 387 | // eon Rd,Rn,(Rm,shk,imm) DR_3B X1001010sh1mmmmm iiiiiinnnnnddddd 4A20 0000 Rm {LSL,LSR,ASR,ROR} imm(0-63) |
| 388 | |
| 389 | // enum name FP LD/ST DR_3A DI_2C |
| 390 | INST2(lsl, "lsl", 0, 0, IF_EN2C, 0x1AC02000, 0x53000000) |
| 391 | // lsl Rd,Rn,Rm DR_3A X0011010110mmmmm 001000nnnnnddddd 1AC0 2000 |
| 392 | // lsl Rd,Rn,imm6 DI_2D X10100110Xrrrrrr ssssssnnnnnddddd 5300 0000 imm(N,r,s) |
| 393 | |
| 394 | INST2(lsr, "lsr", 0, 0, IF_EN2C, 0x1AC02400, 0x53000000) |
| 395 | // lsr Rd,Rn,Rm DR_3A X0011010110mmmmm 001001nnnnnddddd 1AC0 2400 |
| 396 | // lsr Rd,Rn,imm6 DI_2D X10100110Xrrrrrr ssssssnnnnnddddd 5300 0000 imm(N,r,s) |
| 397 | |
| 398 | INST2(asr, "asr", 0, 0, IF_EN2C, 0x1AC02800, 0x13000000) |
| 399 | // asr Rd,Rn,Rm DR_3A X0011010110mmmmm 001010nnnnnddddd 1AC0 2800 |
| 400 | // asr Rd,Rn,imm6 DI_2D X00100110Xrrrrrr ssssssnnnnnddddd 1300 0000 imm(N,r,s) |
| 401 | |
| 402 | // enum name FP LD/ST DR_3A DI_2B |
| 403 | INST2(ror, "ror", 0, 0, IF_EN2D, 0x1AC02C00, 0x13800000) |
| 404 | // ror Rd,Rn,Rm DR_3A X0011010110mmmmm 001011nnnnnddddd 1AC0 2C00 |
| 405 | // ror Rd,Rn,imm6 DI_2B X00100111X0nnnnn ssssssnnnnnddddd 1380 0000 imm(0-63) |
| 406 | |
| 407 | // enum name FP LD/ST LS_3B LS_3C |
| 408 | INST2(ldp, "ldp", 0,LD, IF_EN2E, 0x29400000, 0x28400000) |
| 409 | // ldp Rt,Ra,[Xn] LS_3B X010100101000000 0aaaaannnnnttttt 2940 0000 [Xn imm7] |
| 410 | // ldp Rt,Ra,[Xn+simm7] LS_3C X010100PP1iiiiii iaaaaannnnnttttt 2840 0000 [Xn imm7 LSL {} pre/post/no inc] |
| 411 | |
| 412 | INST2(ldpsw, "ldpsw", 0,LD, IF_EN2E, 0x69400000, 0x68400000) |
| 413 | // ldpsw Rt,Ra,[Xn] LS_3B 0110100101000000 0aaaaannnnnttttt 6940 0000 [Xn imm7] |
| 414 | // ldpsw Rt,Ra,[Xn+simm7] LS_3C 0110100PP1iiiiii iaaaaannnnnttttt 6840 0000 [Xn imm7 LSL {} pre/post/no inc] |
| 415 | |
| 416 | INST2(stp, "stp", 0,ST, IF_EN2E, 0x29000000, 0x28000000) |
| 417 | // stp Rt,Ra,[Xn] LS_3B X010100100000000 0aaaaannnnnttttt 2900 0000 [Xn imm7] |
| 418 | // stp Rt,Ra,[Xn+simm7] LS_3C X010100PP0iiiiii iaaaaannnnnttttt 2800 0000 [Xn imm7 LSL {} pre/post/no inc] |
| 419 | |
| 420 | INST2(ldnp, "ldnp", 0,LD, IF_EN2E, 0x28400000, 0x28400000) |
| 421 | // ldnp Rt,Ra,[Xn] LS_3B X010100001000000 0aaaaannnnnttttt 2840 0000 [Xn imm7] |
| 422 | // ldnp Rt,Ra,[Xn+simm7] LS_3C X010100001iiiiii iaaaaannnnnttttt 2840 0000 [Xn imm7 LSL {}] |
| 423 | |
| 424 | INST2(stnp, "stnp", 0,ST, IF_EN2E, 0x28000000, 0x28000000) |
| 425 | // stnp Rt,Ra,[Xn] LS_3B X010100000000000 0aaaaannnnnttttt 2800 0000 [Xn imm7] |
| 426 | // stnp Rt,Ra,[Xn+simm7] LS_3C X010100000iiiiii iaaaaannnnnttttt 2800 0000 [Xn imm7 LSL {}] |
| 427 | |
| 428 | INST2(ccmp, "ccmp", 0,CMP,IF_EN2F, 0x7A400000, 0x7A400800) |
| 429 | // ccmp Rn,Rm, nzcv,cond DR_2I X1111010010mmmmm cccc00nnnnn0nzcv 7A40 0000 nzcv, cond |
| 430 | // ccmp Rn,imm5,nzcv,cond DI_1F X1111010010iiiii cccc10nnnnn0nzcv 7A40 0800 imm5, nzcv, cond |
| 431 | |
| 432 | INST2(ccmn, "ccmn", 0,CMP,IF_EN2F, 0x3A400000, 0x3A400800) |
| 433 | // ccmn Rn,Rm, nzcv,cond DR_2I X0111010010mmmmm cccc00nnnnn0nzcv 3A40 0000 nzcv, cond |
| 434 | // ccmn Rn,imm5,nzcv,cond DI_1F X0111010910iiiii cccc10nnnnn0nzcv 3A40 0800 imm5, nzcv, cond |
| 435 | |
| 436 | // enum name FP LD/ST DV_2C DV_2F |
| 437 | INST2(ins, "ins", 0, 0, IF_EN2H, 0x4E001C00, 0x6E000400) |
| 438 | // ins Vd[],Rn DV_2C 01001110000iiiii 000111nnnnnddddd 4E00 1C00 Vd[],Rn (from general) |
| 439 | // ins Vd[],Vn[] DV_2F 01101110000iiiii 0jjjj1nnnnnddddd 6E00 0400 Vd[],Vn[] (from/to elem) |
| 440 | |
| 441 | // enum name FP LD/ST DV_3B DV_3D |
| 442 | INST2(fadd, "fadd", 0, 0, IF_EN2G, 0x0E20D400, 0x1E202800) |
| 443 | // fadd Vd,Vn,Vm DV_3B 0Q0011100X1mmmmm 110101nnnnnddddd 0E20 D400 Vd,Vn,Vm (vector) |
| 444 | // fadd Vd,Vn,Vm DV_3D 000111100X1mmmmm 001010nnnnnddddd 1E20 2800 Vd,Vn,Vm (scalar) |
| 445 | |
| 446 | INST2(fsub, "fsub", 0, 0, IF_EN2G, 0x0EA0D400, 0x1E203800) |
| 447 | // fsub Vd,Vn,Vm DV_3B 0Q0011101X1mmmmm 110101nnnnnddddd 0EA0 D400 Vd,Vn,Vm (vector) |
| 448 | // fsub Vd,Vn,Vm DV_3D 000111100X1mmmmm 001110nnnnnddddd 1E20 3800 Vd,Vn,Vm (scalar) |
| 449 | |
| 450 | INST2(fdiv, "fdiv", 0, 0, IF_EN2G, 0x2E20FC00, 0x1E201800) |
| 451 | // fdiv Vd,Vn,Vm DV_3B 0Q1011100X1mmmmm 111111nnnnnddddd 2E20 FC00 Vd,Vn,Vm (vector) |
| 452 | // fdiv Vd,Vn,Vm DV_3D 000111100X1mmmmm 000110nnnnnddddd 1E20 1800 Vd,Vn,Vm (scalar) |
| 453 | |
| 454 | INST2(fmax, "fmax", 0, 0, IF_EN2G, 0x0E20F400, 0x1E204800) |
| 455 | // fmax Vd,Vn,Vm DV_3B 0Q0011100X1mmmmm 111101nnnnnddddd 0E20 F400 Vd,Vn,Vm (vector) |
| 456 | // fmax Vd,Vn,Vm DV_3D 000111100X1mmmmm 010010nnnnnddddd 1E20 4800 Vd,Vn,Vm (scalar) |
| 457 | |
| 458 | INST2(fmin, "fmin", 0, 0, IF_EN2G, 0x0EA0F400, 0x1E205800) |
| 459 | // fmin Vd,Vn,Vm DV_3B 0Q0011101X1mmmmm 111101nnnnnddddd 0EA0 F400 Vd,Vn,Vm (vector) |
| 460 | // fmin Vd,Vn,Vm DV_3D 000111100X1mmmmm 010110nnnnnddddd 1E20 5800 Vd,Vn,Vm (scalar) |
| 461 | |
| 462 | INST2(fabd, "fabd", 0, 0, IF_EN2G, 0x0EA0F400, 0x1E205800) |
| 463 | // fabd Vd,Vn,Vm DV_3B 0Q1011101X1mmmmm 110101nnnnnddddd 2EA0 D400 Vd,Vn,Vm (vector) |
| 464 | // fabd Vd,Vn,Vm DV_3D 011111101X1mmmmm 110101nnnnnddddd 7EA0 D400 Vd,Vn,Vm (scalar) |
| 465 | |
| 466 | // enum name FP LD/ST DV_2K DV_1C |
| 467 | INST2(fcmp, "fcmp", 0, 0, IF_EN2I, 0x1E202000, 0x1E202008) |
| 468 | // fcmp Vn,Vm DV_2K 000111100X1mmmmm 001000nnnnn00000 1E20 2000 Vn Vm |
| 469 | // fcmp Vn,#0.0 DV_1C 000111100X100000 001000nnnnn01000 1E20 2008 Vn #0.0 |
| 470 | |
| 471 | INST2(fcmpe, "fcmpe", 0, 0, IF_EN2I, 0x1E202010, 0x1E202018) |
| 472 | // fcmpe Vn,Vm DV_2K 000111100X1mmmmm 001000nnnnn10000 1E20 2010 Vn Vm |
| 473 | // fcmpe Vn,#0.0 DV_1C 000111100X100000 001000nnnnn11000 1E20 2018 Vn #0.0 |
| 474 | |
| 475 | // enum name FP LD/ST DV_2A DV_2G |
| 476 | INST2(fabs, "fabs", 0, 0, IF_EN2J, 0x0EA0F800, 0x1E20C000) |
| 477 | // fabs Vd,Vn DV_2A 0Q0011101X100000 111110nnnnnddddd 0EA0 F800 Vd,Vn (vector) |
| 478 | // fabs Vd,Vn DV_2G 000111100X100000 110000nnnnnddddd 1E20 C000 Vd,Vn (scalar) |
| 479 | |
| 480 | INST2(fcmle, "fcmle", 0, 0, IF_EN2J, 0x2EA0D800, 0x7EA0D800) |
| 481 | // fcmle Vd,Vn DV_2A 0Q1011101X100000 111110nnnnnddddd 2EA0 D800 Vd,Vn (vector) |
| 482 | // fcmle Vd,Vn DV_2G 011111101X100000 110110nnnnnddddd 7EA0 D800 Vd,Vn (scalar) |
| 483 | |
| 484 | INST2(fcmlt, "fcmlt", 0, 0, IF_EN2J, 0x0EA0E800, 0x5EA0E800) |
| 485 | // fcmlt Vd,Vn DV_2A 0Q0011101X100000 111110nnnnnddddd 0EA0 E800 Vd,Vn (vector) |
| 486 | // fcmlt Vd,Vn DV_2G 010111101X100000 111010nnnnnddddd 5EA0 E800 Vd,Vn (scalar) |
| 487 | |
| 488 | INST2(fneg, "fneg", 0, 0, IF_EN2J, 0x2EA0F800, 0x1E214000) |
| 489 | // fneg Vd,Vn DV_2A 0Q1011101X100000 111110nnnnnddddd 2EA0 F800 Vd,Vn (vector) |
| 490 | // fneg Vd,Vn DV_2G 000111100X100001 010000nnnnnddddd 1E21 4000 Vd,Vn (scalar) |
| 491 | |
| 492 | INST2(fsqrt, "fsqrt", 0, 0, IF_EN2J, 0x2EA1F800, 0x1E21C000) |
| 493 | // fsqrt Vd,Vn DV_2A 0Q1011101X100001 111110nnnnnddddd 2EA1 F800 Vd,Vn (vector) |
| 494 | // fsqrt Vd,Vn DV_2G 000111100X100001 110000nnnnnddddd 1E21 C000 Vd,Vn (scalar) |
| 495 | |
| 496 | INST2(frintn, "frintn", 0, 0, IF_EN2J, 0x0E218800, 0x1E244000) |
| 497 | // frintn Vd,Vn DV_2A 0Q0011100X100001 100010nnnnnddddd 0E21 8800 Vd,Vn (vector) |
| 498 | // frintn Vd,Vn DV_2G 000111100X100100 010000nnnnnddddd 1E24 4000 Vd,Vn (scalar) |
| 499 | |
| 500 | INST2(frintp, "frintp", 0, 0, IF_EN2J, 0x0EA18800, 0x1E24C000) |
| 501 | // frintp Vd,Vn DV_2A 0Q0011101X100001 100010nnnnnddddd 0EA1 8800 Vd,Vn (vector) |
| 502 | // frintp Vd,Vn DV_2G 000111100X100100 110000nnnnnddddd 1E24 C000 Vd,Vn (scalar) |
| 503 | |
| 504 | INST2(frintm, "frintm", 0, 0, IF_EN2J, 0x0E219800, 0x1E254000) |
| 505 | // frintm Vd,Vn DV_2A 0Q0011100X100001 100110nnnnnddddd 0E21 9800 Vd,Vn (vector) |
| 506 | // frintm Vd,Vn DV_2G 000111100X100101 010000nnnnnddddd 1E25 4000 Vd,Vn (scalar) |
| 507 | |
| 508 | INST2(frintz, "frintz", 0, 0, IF_EN2J, 0x0EA19800, 0x1E25C000) |
| 509 | // frintz Vd,Vn DV_2A 0Q0011101X100001 100110nnnnnddddd 0EA1 9800 Vd,Vn (vector) |
| 510 | // frintz Vd,Vn DV_2G 000111100X100101 110000nnnnnddddd 1E25 C000 Vd,Vn (scalar) |
| 511 | |
| 512 | INST2(frinta, "frinta", 0, 0, IF_EN2J, 0x2E218800, 0x1E264000) |
| 513 | // frinta Vd,Vn DV_2A 0Q1011100X100001 100010nnnnnddddd 2E21 8800 Vd,Vn (vector) |
| 514 | // frinta Vd,Vn DV_2G 000111100X100110 010000nnnnnddddd 1E26 4000 Vd,Vn (scalar) |
| 515 | |
| 516 | INST2(frintx, "frintx", 0, 0, IF_EN2J, 0x2E219800, 0x1E274000) |
| 517 | // frintx Vd,Vn DV_2A 0Q1011100X100001 100110nnnnnddddd 2E21 9800 Vd,Vn (vector) |
| 518 | // frintx Vd,Vn DV_2G 000111100X100111 010000nnnnnddddd 1E27 4000 Vd,Vn (scalar) |
| 519 | |
| 520 | INST2(frinti, "frinti", 0, 0, IF_EN2J, 0x2EA19800, 0x1E27C000) |
| 521 | // frinti Vd,Vn DV_2A 0Q1011101X100001 100110nnnnnddddd 2EA1 9800 Vd,Vn (vector) |
| 522 | // frinti Vd,Vn DV_2G 000111100X100111 110000nnnnnddddd 1E27 C000 Vd,Vn (scalar) |
| 523 | |
| 524 | // enum name FP LD/ST DV_2M DV_2L |
| 525 | INST2(abs, "abs", 0, 0, IF_EN2K, 0x0E20B800, 0x5E20B800) |
| 526 | // abs Vd,Vn DV_2M 0Q001110XX100000 101110nnnnnddddd 0E20 B800 Vd,Vn (vector) |
| 527 | // abs Vd,Vn DV_2L 01011110XX100000 101110nnnnnddddd 5E20 B800 Vd,Vn (scalar) |
| 528 | |
| 529 | INST2(cmle, "cmle", 0, 0, IF_EN2K, 0x2E209800, 0x7E209800) |
| 530 | // cmle Vd,Vn DV_2M 0Q101110XX100000 100110nnnnnddddd 2E20 9800 Vd,Vn (vector) |
| 531 | // cmle Vd,Vn DV_2L 01111110XX100000 100110nnnnnddddd 7E20 9800 Vd,Vn (scalar) |
| 532 | |
| 533 | INST2(cmlt, "cmlt", 0, 0, IF_EN2K, 0x0E20A800, 0x5E20A800) |
| 534 | // cmlt Vd,Vn DV_2M 0Q101110XX100000 101010nnnnnddddd 0E20 A800 Vd,Vn (vector) |
| 535 | // cmlt Vd,Vn DV_2L 01011110XX100000 101010nnnnnddddd 5E20 A800 Vd,Vn (scalar) |
| 536 | |
| 537 | // enum name FP LD/ST DR_2G DV_2M |
| 538 | INST2(cls, "cls", 0, 0, IF_EN2L, 0x5AC01400, 0x0E204800) |
| 539 | // cls Rd,Rm DR_2G X101101011000000 000101nnnnnddddd 5AC0 1400 Rd Rn (general) |
| 540 | // cls Vd,Vn DV_2M 0Q00111000100000 010010nnnnnddddd 0E20 4800 Vd,Vn (vector) |
| 541 | |
| 542 | INST2(clz, "clz", 0, 0, IF_EN2L, 0x5AC01000, 0x2E204800) |
| 543 | // clz Rd,Rm DR_2G X101101011000000 000100nnnnnddddd 5AC0 1000 Rd Rn (general) |
| 544 | // clz Vd,Vn DV_2M 0Q10111000100000 010010nnnnnddddd 2E20 4800 Vd,Vn (vector) |
| 545 | |
| 546 | INST2(rbit, "rbit", 0, 0, IF_EN2L, 0x5AC00000, 0x2E605800) |
| 547 | // rbit Rd,Rm DR_2G X101101011000000 000000nnnnnddddd 5AC0 0000 Rd Rn (general) |
| 548 | // rbit Vd,Vn DV_2M 0Q10111001100000 010110nnnnnddddd 2E60 5800 Vd,Vn (vector) |
| 549 | |
| 550 | INST2(rev16, "rev16", 0, 0, IF_EN2L, 0x5AC00400, 0x0E201800) |
| 551 | // rev16 Rd,Rm DR_2G X101101011000000 000001nnnnnddddd 5AC0 0400 Rd Rn (general) |
| 552 | // rev16 Vd,Vn DV_2M 0Q001110XX100000 000110nnnnnddddd 0E20 1800 Vd,Vn (vector) |
| 553 | |
| 554 | INST2(rev32, "rev32", 0, 0, IF_EN2L, 0xDAC00800, 0x2E200800) |
| 555 | // rev32 Rd,Rm DR_2G 1101101011000000 000010nnnnnddddd DAC0 0800 Rd Rn (general) |
| 556 | // rev32 Vd,Vn DV_2M 0Q101110XX100000 000010nnnnnddddd 2E20 0800 Vd,Vn (vector) |
| 557 | |
| 558 | // enum name FP LD/ST DV_3A DV_3AI |
| 559 | INST2(mla, "mla", 0, 0, IF_EN2M, 0x0E209400, 0x2F000000) |
| 560 | // mla Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 100101nnnnnddddd 0E20 9400 Vd,Vn,Vm (vector) |
| 561 | // mla Vd,Vn,Vm[] DV_3AI 0Q101111XXLMmmmm 0000H0nnnnnddddd 2F00 0000 Vd,Vn,Vm[] (vector by elem) |
| 562 | |
| 563 | INST2(mls, "mls", 0, 0, IF_EN2M, 0x2E209400, 0x2F004000) |
| 564 | // mls Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 100101nnnnnddddd 2E20 9400 Vd,Vn,Vm (vector) |
| 565 | // mls Vd,Vn,Vm[] DV_3AI 0Q101111XXLMmmmm 0100H0nnnnnddddd 2F00 4000 Vd,Vn,Vm[] (vector by elem) |
| 566 | |
| 567 | // enum name FP LD/ST DV_2N DV_2O |
| 568 | INST2(sshr, "sshr", 0, 0, IF_EN2N, 0x5F000400, 0x0F000400) |
| 569 | // sshr Vd,Vn,imm DV_2N 010111110iiiiiii 000001nnnnnddddd 5F00 0400 Vd Vn imm (shift - scalar) |
| 570 | // sshr Vd,Vn,imm DV_2O 0Q0011110iiiiiii 000001nnnnnddddd 0F00 0400 Vd,Vn imm (shift - vector) |
| 571 | |
| 572 | INST2(ssra, "ssra", 0, 0, IF_EN2N, 0x5F001400, 0x0F001400) |
| 573 | // ssra Vd,Vn,imm DV_2N 010111110iiiiiii 000101nnnnnddddd 5F00 1400 Vd Vn imm (shift - scalar) |
| 574 | // ssra Vd,Vn,imm DV_2O 0Q0011110iiiiiii 000101nnnnnddddd 0F00 1400 Vd,Vn imm (shift - vector) |
| 575 | |
| 576 | INST2(srshr, "srshr", 0, 0, IF_EN2N, 0x5F002400, 0x0F002400) |
| 577 | // srshr Vd,Vn,imm DV_2N 010111110iiiiiii 001001nnnnnddddd 5F00 0400 Vd Vn imm (shift - scalar) |
| 578 | // srshr Vd,Vn,imm DV_2O 0Q0011110iiiiiii 001001nnnnnddddd 0F00 0400 Vd,Vn imm (shift - vector) |
| 579 | |
| 580 | INST2(srsra, "srsra", 0, 0, IF_EN2N, 0x5F003400, 0x0F003400) |
| 581 | // srsra Vd,Vn,imm DV_2N 010111110iiiiiii 001101nnnnnddddd 5F00 1400 Vd Vn imm (shift - scalar) |
| 582 | // srsra Vd,Vn,imm DV_2O 0Q0011110iiiiiii 001101nnnnnddddd 0F00 1400 Vd,Vn imm (shift - vector) |
| 583 | |
| 584 | INST2(shl, "shl", 0, 0, IF_EN2N, 0x5F005400, 0x0F005400) |
| 585 | // shl Vd,Vn,imm DV_2N 010111110iiiiiii 010101nnnnnddddd 5F00 5400 Vd Vn imm (shift - scalar) |
| 586 | // shl Vd,Vn,imm DV_2O 0Q0011110iiiiiii 010101nnnnnddddd 0F00 5400 Vd,Vn imm (shift - vector) |
| 587 | |
| 588 | INST2(ushr, "ushr", 0, 0, IF_EN2N, 0x7F000400, 0x2F000400) |
| 589 | // ushr Vd,Vn,imm DV_2N 011111110iiiiiii 000001nnnnnddddd 7F00 0400 Vd Vn imm (shift - scalar) |
| 590 | // ushr Vd,Vn,imm DV_2O 0Q1011110iiiiiii 000001nnnnnddddd 2F00 0400 Vd,Vn imm (shift - vector) |
| 591 | |
| 592 | INST2(usra, "usra", 0, 0, IF_EN2N, 0x7F001400, 0x2F001400) |
| 593 | // usra Vd,Vn,imm DV_2N 011111110iiiiiii 000101nnnnnddddd 7F00 1400 Vd Vn imm (shift - scalar) |
| 594 | // usra Vd,Vn,imm DV_2O 0Q1011110iiiiiii 000101nnnnnddddd 2F00 1400 Vd,Vn imm (shift - vector) |
| 595 | |
| 596 | INST2(urshr, "urshr", 0, 0, IF_EN2N, 0x7F002400, 0x2F002400) |
| 597 | // urshr Vd,Vn,imm DV_2N 011111110iiiiiii 001001nnnnnddddd 7F00 2400 Vd Vn imm (shift - scalar) |
| 598 | // urshr Vd,Vn,imm DV_2O 0Q1011110iiiiiii 001001nnnnnddddd 2F00 2400 Vd,Vn imm (shift - vector) |
| 599 | |
| 600 | INST2(ursra, "ursra", 0, 0, IF_EN2N, 0x7F003400, 0x2F003400) |
| 601 | // ursra Vd,Vn,imm DV_2N 011111110iiiiiii 001101nnnnnddddd 7F00 3400 Vd Vn imm (shift - scalar) |
| 602 | // ursra Vd,Vn,imm DV_2O 0Q1011110iiiiiii 001101nnnnnddddd 2F00 3400 Vd,Vn imm (shift - vector) |
| 603 | |
| 604 | INST2(sri, "sri", 0, 0, IF_EN2N, 0x7F004400, 0x2F004400) |
| 605 | // sri Vd,Vn,imm DV_2N 011111110iiiiiii 010001nnnnnddddd 7F00 4400 Vd Vn imm (shift - scalar) |
| 606 | // sri Vd,Vn,imm DV_2O 0Q1011110iiiiiii 010001nnnnnddddd 2F00 4400 Vd,Vn imm (shift - vector) |
| 607 | |
| 608 | INST2(sli, "sli", 0, 0, IF_EN2N, 0x7F005400, 0x2F005400) |
| 609 | // sli Vd,Vn,imm DV_2N 011111110iiiiiii 010101nnnnnddddd 7F00 5400 Vd Vn imm (shift - scalar) |
| 610 | // sli Vd,Vn,imm DV_2O 0Q1011110iiiiiii 010101nnnnnddddd 2F00 5400 Vd,Vn imm (shift - vector) |
| 611 | |
| 612 | // enum name FP LD/ST DV_3E DV_3A |
| 613 | INST2(cmhi, "cmhi", 0, 0, IF_EN2O, 0x7EE03400, 0x2E203400) |
| 614 | // cmhi Vd,Vn,Vm DV_3E 01111110111mmmmm 001101nnnnnddddd 7EE0 3400 Vd,Vn,Vm (scalar) |
| 615 | // cmhi Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 001101nnnnnddddd 2E20 3400 Vd,Vn,Vm (vector) |
| 616 | |
| 617 | INST2(cmhs, "cmhs", 0, 0, IF_EN2O, 0x7EE03C00, 0x2E203C00) |
| 618 | // cmhs Vd,Vn,Vm DV_3E 01111110111mmmmm 001111nnnnnddddd 7EE0 3C00 Vd,Vn,Vm (scalar) |
| 619 | // cmhs Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 001111nnnnnddddd 2E20 3C00 Vd,Vn,Vm (vector) |
| 620 | |
| 621 | INST2(ctst, "ctst", 0, 0, IF_EN2O, 0x5EE08C00, 0x0E208C00) |
| 622 | // ctst Vd,Vn,Vm DV_3E 01011110111mmmmm 100011nnnnnddddd 5EE0 8C00 Vd,Vn,Vm (scalar) |
| 623 | // ctst Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 100011nnnnnddddd 0E20 8C00 Vd,Vn,Vm (vector) |
| 624 | |
| 625 | // enum name FP LD/ST DV_2G DV_3B |
| 626 | INST2(faddp, "faddp", 0, 0, IF_EN2P, 0x7E30D800, 0x2E20D400) |
| 627 | // faddp Vd,Vn DV_2G 011111100X110000 110110nnnnnddddd 7E30 D800 Vd,Vn (scalar) |
| 628 | // faddp Vd,Vn,Vm DV_3B 0Q1011100X1mmmmm 110101nnnnnddddd 2E20 D400 Vd,Vn,Vm (vector) |
| 629 | |
| 630 | INST1(ldar, "ldar", 0,LD, IF_LS_2A, 0x88DFFC00) |
| 631 | // ldar Rt,[Xn] LS_2A 1X00100011011111 111111nnnnnttttt 88DF FC00 |
| 632 | |
| 633 | INST1(ldarb, "ldarb", 0,LD, IF_LS_2A, 0x08DFFC00) |
| 634 | // ldarb Rt,[Xn] LS_2A 0000100011011111 111111nnnnnttttt 08DF FC00 |
| 635 | |
| 636 | INST1(ldarh, "ldarh", 0,LD, IF_LS_2A, 0x48DFFC00) |
| 637 | // ldarh Rt,[Xn] LS_2A 0100100011011111 111111nnnnnttttt 48DF FC00 |
| 638 | |
| 639 | INST1(ldxr, "ldxr", 0,LD, IF_LS_2A, 0x885F7C00) |
| 640 | // ldxr Rt,[Xn] LS_2A 1X00100001011111 011111nnnnnttttt 885F 7C00 |
| 641 | |
| 642 | INST1(ldxrb, "ldxrb", 0,LD, IF_LS_2A, 0x085F7C00) |
| 643 | // ldxrb Rt,[Xn] LS_2A 0000100001011111 011111nnnnnttttt 085F 7C00 |
| 644 | |
| 645 | INST1(ldxrh, "ldxrh", 0,LD, IF_LS_2A, 0x485F7C00) |
| 646 | // ldxrh Rt,[Xn] LS_2A 0100100001011111 011111nnnnnttttt 485F 7C00 |
| 647 | |
| 648 | INST1(ldaxr, "ldaxr", 0,LD, IF_LS_2A, 0x885FFC00) |
| 649 | // ldaxr Rt,[Xn] LS_2A 1X00100001011111 111111nnnnnttttt 885F FC00 |
| 650 | |
| 651 | INST1(ldaxrb, "ldaxrb", 0,LD, IF_LS_2A, 0x085FFC00) |
| 652 | // ldaxrb Rt,[Xn] LS_2A 0000100001011111 111111nnnnnttttt 085F FC00 |
| 653 | |
| 654 | INST1(ldaxrh, "ldaxrh", 0,LD, IF_LS_2A, 0x485FFC00) |
| 655 | // ldaxrh Rt,[Xn] LS_2A 0100100001011111 111111nnnnnttttt 485F FC00 |
| 656 | |
| 657 | INST1(ldur, "ldur", 0,LD, IF_LS_2C, 0xB8400000) |
| 658 | // ldur Rt,[Xn+simm9] LS_2C 1X111000010iiiii iiii00nnnnnttttt B840 0000 [Xn imm(-256..+255)] |
| 659 | |
| 660 | INST1(ldurb, "ldurb", 0,LD, IF_LS_2C, 0x38400000) |
| 661 | // ldurb Rt,[Xn+simm9] LS_2C 00111000010iiiii iiii00nnnnnttttt 3840 0000 [Xn imm(-256..+255)] |
| 662 | |
| 663 | INST1(ldurh, "ldurh", 0,LD, IF_LS_2C, 0x78400000) |
| 664 | // ldurh Rt,[Xn+simm9] LS_2C 01111000010iiiii iiii00nnnnnttttt 7840 0000 [Xn imm(-256..+255)] |
| 665 | |
| 666 | INST1(ldursb, "ldursb", 0,LD, IF_LS_2C, 0x38800000) |
| 667 | // ldursb Rt,[Xn+simm9] LS_2C 001110001X0iiiii iiii00nnnnnttttt 3880 0000 [Xn imm(-256..+255)] |
| 668 | |
| 669 | INST1(ldursh, "ldursh", 0,LD, IF_LS_2C, 0x78800000) |
| 670 | // ldursh Rt,[Xn+simm9] LS_2C 011110001X0iiiii iiii00nnnnnttttt 7880 0000 [Xn imm(-256..+255)] |
| 671 | |
| 672 | INST1(ldursw, "ldursw", 0,LD, IF_LS_2C, 0xB8800000) |
| 673 | // ldursw Rt,[Xn+simm9] LS_2C 10111000100iiiii iiii00nnnnnttttt B880 0000 [Xn imm(-256..+255)] |
| 674 | |
| 675 | INST1(stlr, "stlr", 0,ST, IF_LS_2A, 0x889FFC00) |
| 676 | // stlr Rt,[Xn] LS_2A 1X00100010011111 111111nnnnnttttt 889F FC00 |
| 677 | |
| 678 | INST1(stlrb, "stlrb", 0,ST, IF_LS_2A, 0x089FFC00) |
| 679 | // stlrb Rt,[Xn] LS_2A 0000100010011111 111111nnnnnttttt 089F FC00 |
| 680 | |
| 681 | INST1(stlrh, "stlrh", 0,ST, IF_LS_2A, 0x489FFC00) |
| 682 | // stlrh Rt,[Xn] LS_2A 0100100010011111 111111nnnnnttttt 489F FC00 |
| 683 | |
| 684 | INST1(stxr, "stxr", 0,ST, IF_LS_3D, 0x88007C00) |
| 685 | // stxr Ws, Rt,[Xn] LS_3D 1X001000000sssss 011111nnnnnttttt 8800 7C00 |
| 686 | |
| 687 | INST1(stxrb, "stxrb", 0,ST, IF_LS_3D, 0x08007C00) |
| 688 | // stxrb Ws, Rt,[Xn] LS_3D 00001000000sssss 011111nnnnnttttt 0800 7C00 |
| 689 | |
| 690 | INST1(stxrh, "stxrh", 0,ST, IF_LS_3D, 0x48007C00) |
| 691 | // stxrh Ws, Rt,[Xn] LS_3D 01001000000sssss 011111nnnnnttttt 4800 7C00 |
| 692 | |
| 693 | INST1(stlxr, "stlxr", 0,ST, IF_LS_3D, 0x8800FC00) |
| 694 | // stlxr Ws, Rt,[Xn] LS_3D 1X001000000sssss 111111nnnnnttttt 8800 FC00 |
| 695 | |
| 696 | INST1(stlxrb, "stlxrb", 0,ST, IF_LS_3D, 0x0800FC00) |
| 697 | // stlxrb Ws, Rt,[Xn] LS_3D 00001000000sssss 111111nnnnnttttt 0800 FC00 |
| 698 | |
| 699 | INST1(stlxrh, "stlxrh", 0,ST, IF_LS_3D, 0x4800FC00) |
| 700 | // stlxrh Ws, Rt,[Xn] LS_3D 01001000000sssss 111111nnnnnttttt 4800 FC00 |
| 701 | |
| 702 | INST1(stur, "stur", 0,ST, IF_LS_2C, 0xB8000000) |
| 703 | // stur Rt,[Xn+simm9] LS_2C 1X111000000iiiii iiii00nnnnnttttt B800 0000 [Xn imm(-256..+255)] |
| 704 | |
| 705 | INST1(sturb, "sturb", 0,ST, IF_LS_2C, 0x38000000) |
| 706 | // sturb Rt,[Xn+simm9] LS_2C 00111000000iiiii iiii00nnnnnttttt 3800 0000 [Xn imm(-256..+255)] |
| 707 | |
| 708 | INST1(sturh, "sturh", 0,ST, IF_LS_2C, 0x78000000) |
| 709 | // sturh Rt,[Xn+simm9] LS_2C 01111000000iiiii iiii00nnnnnttttt 7800 0000 [Xn imm(-256..+255)] |
| 710 | |
| 711 | INST1(casb, "casb", 0, LD|ST, IF_LS_3E, 0x08A07C00) |
| 712 | // casb Wm, Wt, [Xn] LS_3E 00001000101mmmmm 011111nnnnnttttt 08A0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 713 | |
| 714 | INST1(casab, "casab", 0, LD|ST, IF_LS_3E, 0x08E07C00) |
| 715 | // casab Wm, Wt, [Xn] LS_3E 00001000111mmmmm 011111nnnnnttttt 08E0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 716 | |
| 717 | INST1(casalb, "casalb", 0, LD|ST, IF_LS_3E, 0x08E0FC00) |
| 718 | // casalb Wm, Wt, [Xn] LS_3E 00001000111mmmmm 111111nnnnnttttt 08E0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 719 | |
| 720 | INST1(caslb, "caslb", 0, LD|ST, IF_LS_3E, 0x08A0FC00) |
| 721 | // caslb Wm, Wt, [Xn] LS_3E 00001000101mmmmm 111111nnnnnttttt 08A0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 722 | |
| 723 | INST1(cash, "cash", 0, LD|ST, IF_LS_3E, 0x48A07C00) |
| 724 | // cash Wm, Wt, [Xn] LS_3E 01001000101mmmmm 011111nnnnnttttt 48A0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 725 | |
| 726 | INST1(casah, "casah", 0, LD|ST, IF_LS_3E, 0x48E07C00) |
| 727 | // casah Wm, Wt, [Xn] LS_3E 01001000111mmmmm 011111nnnnnttttt 48E0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 728 | |
| 729 | INST1(casalh, "casalh", 0, LD|ST, IF_LS_3E, 0x48E0FC00) |
| 730 | // casalh Wm, Wt, [Xn] LS_3E 01001000111mmmmm 111111nnnnnttttt 48E0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 731 | |
| 732 | INST1(caslh, "caslh", 0, LD|ST, IF_LS_3E, 0x48A0FC00) |
| 733 | // caslh Wm, Wt, [Xn] LS_3E 01001000101mmmmm 111111nnnnnttttt 48A0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 734 | |
| 735 | INST1(cas, "cas", 0, LD|ST, IF_LS_3E, 0x88A07C00) |
| 736 | // cas Rm, Rt, [Xn] LS_3E 1X001000101mmmmm 011111nnnnnttttt 88A0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 737 | |
| 738 | INST1(casa, "casa", 0, LD|ST, IF_LS_3E, 0x88E07C00) |
| 739 | // casa Rm, Rt, [Xn] LS_3E 1X001000111mmmmm 011111nnnnnttttt 88E0 7C00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 740 | |
| 741 | INST1(casal, "casal", 0, LD|ST, IF_LS_3E, 0x88E0FC00) |
| 742 | // casal Rm, Rt, [Xn] LS_3E 1X001000111mmmmm 111111nnnnnttttt 88E0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 743 | |
| 744 | INST1(casl, "casl", 0, LD|ST, IF_LS_3E, 0x88A0FC00) |
| 745 | // casl Rm, Rt, [Xn] LS_3E 1X001000101mmmmm 111111nnnnnttttt 88A0 FC00 Rm Rt Rn ARMv8.1 LSE Atomics |
| 746 | |
| 747 | INST1(ldaddb, "ldaddb", 0, LD|ST, IF_LS_3E, 0x38200000) |
| 748 | // ldaddb Wm, Wt, [Xn] LS_3E 00111000001mmmmm 000000nnnnnttttt 3820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 749 | |
| 750 | INST1(ldaddab, "ldaddab", 0, LD|ST, IF_LS_3E, 0x38A00000) |
| 751 | // ldaddab Wm, Wt, [Xn] LS_3E 00111000101mmmmm 000000nnnnnttttt 38A0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 752 | |
| 753 | INST1(ldaddalb,"ldaddalb",0, LD|ST, IF_LS_3E, 0x38E00000) |
| 754 | // ldaddalb Wm, Wt, [Xn] LS_3E 00111000111mmmmm 000000nnnnnttttt 38E0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 755 | |
| 756 | INST1(ldaddlb, "ldaddlb", 0, LD|ST, IF_LS_3E, 0x38600000) |
| 757 | // ldaddlb Wm, Wt, [Xn] LS_3E 00111000011mmmmm 000000nnnnnttttt 3860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 758 | |
| 759 | INST1(ldaddh, "ldaddh", 0, LD|ST, IF_LS_3E, 0x78200000) |
| 760 | // ldaddh Wm, Wt, [Xn] LS_3E 01111000001mmmmm 000000nnnnnttttt 7820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 761 | |
| 762 | INST1(ldaddah, "ldaddah", 0, LD|ST, IF_LS_3E, 0x78A00000) |
| 763 | // ldaddah Wm, Wt, [Xn] LS_3E 01111000101mmmmm 000000nnnnnttttt 78A0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 764 | |
| 765 | INST1(ldaddalh,"ldaddalh",0, LD|ST, IF_LS_3E, 0x78E00000) |
| 766 | // ldaddalh Wm, Wt, [Xn] LS_3E 01111000111mmmmm 000000nnnnnttttt 78E0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 767 | |
| 768 | INST1(ldaddlh, "ldaddlh", 0, LD|ST, IF_LS_3E, 0x78600000) |
| 769 | // ldaddlh Wm, Wt, [Xn] LS_3E 01111000011mmmmm 000000nnnnnttttt 7860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 770 | |
| 771 | INST1(ldadd, "ldadd", 0, LD|ST, IF_LS_3E, 0xB8200000) |
| 772 | // ldadd Rm, Rt, [Xn] LS_3E 1X111000001mmmmm 000000nnnnnttttt B820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 773 | |
| 774 | INST1(ldadda, "ldadda", 0, LD|ST, IF_LS_3E, 0xB8A00000) |
| 775 | // ldadda Rm, Rt, [Xn] LS_3E 1X111000101mmmmm 000000nnnnnttttt B8A0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 776 | |
| 777 | INST1(ldaddal, "ldaddal", 0, LD|ST, IF_LS_3E, 0xB8E00000) |
| 778 | // ldaddal Rm, Rt, [Xn] LS_3E 1X111000111mmmmm 000000nnnnnttttt B8E0 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 779 | |
| 780 | INST1(ldaddl, "ldaddl", 0, LD|ST, IF_LS_3E, 0xB8600000) |
| 781 | // ldaddl Rm, Rt, [Xn] LS_3E 1X111000011mmmmm 000000nnnnnttttt B860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 782 | |
| 783 | INST1(staddb, "staddb", 0, ST, IF_LS_3E, 0x38200000) |
| 784 | // staddb Wm, [Xn] LS_3E 00111000001mmmmm 000000nnnnnttttt 3820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 785 | |
| 786 | INST1(staddlb, "staddlb", 0, ST, IF_LS_3E, 0x38600000) |
| 787 | // staddlb Wm, [Xn] LS_3E 00111000011mmmmm 000000nnnnnttttt 3860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 788 | |
| 789 | INST1(staddh, "staddh", 0, ST, IF_LS_3E, 0x78200000) |
| 790 | // staddh Wm, [Xn] LS_3E 01111000001mmmmm 000000nnnnnttttt 7820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 791 | |
| 792 | INST1(staddlh, "staddlh", 0, ST, IF_LS_3E, 0x78600000) |
| 793 | // staddlh Wm, [Xn] LS_3E 01111000011mmmmm 000000nnnnnttttt 7860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 794 | |
| 795 | INST1(stadd, "stadd", 0, ST, IF_LS_3E, 0xB8200000) |
| 796 | // stadd Rm, [Xn] LS_3E 1X111000001mmmmm 000000nnnnnttttt B820 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 797 | |
| 798 | INST1(staddl, "staddl", 0, ST, IF_LS_3E, 0xB8600000) |
| 799 | // staddl Rm, [Xn] LS_3E 1X111000011mmmmm 000000nnnnnttttt B860 0000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 800 | |
| 801 | INST1(swpb, "swpb", 0, LD|ST, IF_LS_3E, 0x38208000) |
| 802 | // swpb Wm, Wt, [Xn] LS_3E 00111000001mmmmm 100000nnnnnttttt 3820 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 803 | |
| 804 | INST1(swpab, "swpab", 0, LD|ST, IF_LS_3E, 0x38A08000) |
| 805 | // swpab Wm, Wt, [Xn] LS_3E 00111000101mmmmm 100000nnnnnttttt 38A0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 806 | |
| 807 | INST1(swpalb, "swpalb", 0, LD|ST, IF_LS_3E, 0x38E08000) |
| 808 | // swpalb Wm, Wt, [Xn] LS_3E 00111000111mmmmm 100000nnnnnttttt 38E0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 809 | |
| 810 | INST1(swplb, "swplb", 0, LD|ST, IF_LS_3E, 0x38608000) |
| 811 | // swplb Wm, Wt, [Xn] LS_3E 00111000011mmmmm 100000nnnnnttttt 3860 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 812 | |
| 813 | INST1(swph, "swph", 0, LD|ST, IF_LS_3E, 0x78208000) |
| 814 | // swph Wm, Wt, [Xn] LS_3E 01111000001mmmmm 100000nnnnnttttt 7820 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 815 | |
| 816 | INST1(swpah, "swpah", 0, LD|ST, IF_LS_3E, 0x78A08000) |
| 817 | // swpah Wm, Wt, [Xn] LS_3E 01111000101mmmmm 100000nnnnnttttt 78A0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 818 | |
| 819 | INST1(swpalh, "swpalh", 0, LD|ST, IF_LS_3E, 0x78E08000) |
| 820 | // swpalh Wm, Wt, [Xn] LS_3E 01111000111mmmmm 100000nnnnnttttt 78E0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 821 | |
| 822 | INST1(swplh, "swplh", 0, LD|ST, IF_LS_3E, 0x78608000) |
| 823 | // swplh Wm, Wt, [Xn] LS_3E 01111000011mmmmm 100000nnnnnttttt 7860 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 824 | |
| 825 | INST1(swp, "swp", 0, LD|ST, IF_LS_3E, 0xB8208000) |
| 826 | // swp Rm, Rt, [Xn] LS_3E 1X111000001mmmmm 100000nnnnnttttt B820 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 827 | |
| 828 | INST1(swpa, "swpa", 0, LD|ST, IF_LS_3E, 0xB8A08000) |
| 829 | // swpa Rm, Rt, [Xn] LS_3E 1X111000101mmmmm 100000nnnnnttttt B8A0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 830 | |
| 831 | INST1(swpal, "swpal", 0, LD|ST, IF_LS_3E, 0xB8E08000) |
| 832 | // swpal Rm, Rt, [Xn] LS_3E 1X111000111mmmmm 100000nnnnnttttt B8E0 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 833 | |
| 834 | INST1(swpl, "swpl", 0, LD|ST, IF_LS_3E, 0xB8608000) |
| 835 | // swpl Rm, Rt, [Xn] LS_3E 1X111000011mmmmm 100000nnnnnttttt B860 8000 Rm Rt Rn ARMv8.1 LSE Atomics |
| 836 | |
| 837 | INST1(adr, "adr", 0, 0, IF_DI_1E, 0x10000000) |
| 838 | // adr Rd, simm21 DI_1E 0ii10000iiiiiiii iiiiiiiiiiiddddd 1000 0000 Rd simm21 |
| 839 | |
| 840 | INST1(adrp, "adrp", 0, 0, IF_DI_1E, 0x90000000) |
| 841 | // adrp Rd, simm21 DI_1E 1ii10000iiiiiiii iiiiiiiiiiiddddd 9000 0000 Rd simm21 |
| 842 | |
| 843 | INST1(b, "b", 0, 0, IF_BI_0A, 0x14000000) |
| 844 | // b simm26 BI_0A 000101iiiiiiiiii iiiiiiiiiiiiiiii 1400 0000 simm26:00 |
| 845 | |
| 846 | INST1(b_tail, "b", 0, 0, IF_BI_0C, 0x14000000) |
| 847 | // b simm26 BI_0A 000101iiiiiiiiii iiiiiiiiiiiiiiii 1400 0000 simm26:00, same as b representing a tail call of bl. |
| 848 | |
| 849 | INST1(bl_local,"bl", 0, 0, IF_BI_0A, 0x94000000) |
| 850 | // bl simm26 BI_0A 100101iiiiiiiiii iiiiiiiiiiiiiiii 9400 0000 simm26:00, same as bl, but with a BasicBlock target. |
| 851 | |
| 852 | INST1(bl, "bl", 0, 0, IF_BI_0C, 0x94000000) |
| 853 | // bl simm26 BI_0C 100101iiiiiiiiii iiiiiiiiiiiiiiii 9400 0000 simm26:00 |
| 854 | |
| 855 | INST1(br, "br", 0, 0, IF_BR_1A, 0xD61F0000) |
| 856 | // br Rn BR_1A 1101011000011111 000000nnnnn00000 D61F 0000, an indirect branch like switch expansion |
| 857 | |
| 858 | INST1(br_tail, "br", 0, 0, IF_BR_1B, 0xD61F0000) |
| 859 | // br Rn BR_1B 1101011000011111 000000nnnnn00000 D61F 0000, same as br representing a tail call of blr. Encode target with Reg3. |
| 860 | |
| 861 | INST1(blr, "blr", 0, 0, IF_BR_1B, 0xD63F0000) |
| 862 | // blr Rn BR_1B 1101011000111111 000000nnnnn00000 D63F 0000, Encode target with Reg3. |
| 863 | |
| 864 | INST1(ret, "ret", 0, 0, IF_BR_1A, 0xD65F0000) |
| 865 | // ret Rn BR_1A 1101011001011111 000000nnnnn00000 D65F 0000 |
| 866 | |
| 867 | INST1(beq, "beq", 0, 0, IF_BI_0B, 0x54000000) |
| 868 | // beq simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00000 5400 0000 simm19:00 |
| 869 | |
| 870 | INST1(bne, "bne", 0, 0, IF_BI_0B, 0x54000001) |
| 871 | // bne simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00001 5400 0001 simm19:00 |
| 872 | |
| 873 | INST1(bhs, "bhs", 0, 0, IF_BI_0B, 0x54000002) |
| 874 | // bhs simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00010 5400 0002 simm19:00 |
| 875 | |
| 876 | INST1(blo, "blo", 0, 0, IF_BI_0B, 0x54000003) |
| 877 | // blo simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00011 5400 0003 simm19:00 |
| 878 | |
| 879 | INST1(bmi, "bmi", 0, 0, IF_BI_0B, 0x54000004) |
| 880 | // bmi simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00100 5400 0004 simm19:00 |
| 881 | |
| 882 | INST1(bpl, "bpl", 0, 0, IF_BI_0B, 0x54000005) |
| 883 | // bpl simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00101 5400 0005 simm19:00 |
| 884 | |
| 885 | INST1(bvs, "bvs", 0, 0, IF_BI_0B, 0x54000006) |
| 886 | // bvs simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00110 5400 0006 simm19:00 |
| 887 | |
| 888 | INST1(bvc, "bvc", 0, 0, IF_BI_0B, 0x54000007) |
| 889 | // bvc simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii00111 5400 0007 simm19:00 |
| 890 | |
| 891 | INST1(bhi, "bhi", 0, 0, IF_BI_0B, 0x54000008) |
| 892 | // bhi simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01000 5400 0008 simm19:00 |
| 893 | |
| 894 | INST1(bls, "bls", 0, 0, IF_BI_0B, 0x54000009) |
| 895 | // bls simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01001 5400 0009 simm19:00 |
| 896 | |
| 897 | INST1(bge, "bge", 0, 0, IF_BI_0B, 0x5400000A) |
| 898 | // bge simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01010 5400 000A simm19:00 |
| 899 | |
| 900 | INST1(blt, "blt", 0, 0, IF_BI_0B, 0x5400000B) |
| 901 | // blt simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01011 5400 000B simm19:00 |
| 902 | |
| 903 | INST1(bgt, "bgt", 0, 0, IF_BI_0B, 0x5400000C) |
| 904 | // bgt simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01100 5400 000C simm19:00 |
| 905 | |
| 906 | INST1(ble, "ble", 0, 0, IF_BI_0B, 0x5400000D) |
| 907 | // ble simm19 BI_0B 01010100iiiiiiii iiiiiiiiiii01101 5400 000D simm19:00 |
| 908 | |
| 909 | INST1(cbz, "cbz", 0, 0, IF_BI_1A, 0x34000000) |
| 910 | // cbz Rt, simm19 BI_1A X0110100iiiiiiii iiiiiiiiiiittttt 3400 0000 Rt simm19:00 |
| 911 | |
| 912 | INST1(cbnz, "cbnz", 0, 0, IF_BI_1A, 0x35000000) |
| 913 | // cbnz Rt, simm19 BI_1A X0110101iiiiiiii iiiiiiiiiiittttt 3500 0000 Rt simm19:00 |
| 914 | |
| 915 | INST1(tbz, "tbz", 0, 0, IF_BI_1B, 0x36000000) |
| 916 | // tbz Rt, imm6, simm14 BI_1B B0110110bbbbbiii iiiiiiiiiiittttt 3600 0000 Rt imm6, simm14:00 |
| 917 | |
| 918 | INST1(tbnz, "tbnz", 0, 0, IF_BI_1B, 0x37000000) |
| 919 | // tbnz Rt, imm6, simm14 BI_1B B0110111bbbbbiii iiiiiiiiiiittttt 3700 0000 Rt imm6, simm14:00 |
| 920 | |
| 921 | INST1(movk, "movk", 0, 0, IF_DI_1B, 0x72800000) |
| 922 | // movk Rd,imm(i16,hw) DI_1B X11100101hwiiiii iiiiiiiiiiiddddd 7280 0000 imm(i16,hw) |
| 923 | |
| 924 | INST1(movn, "movn", 0, 0, IF_DI_1B, 0x12800000) |
| 925 | // movn Rd,imm(i16,hw) DI_1B X00100101hwiiiii iiiiiiiiiiiddddd 1280 0000 imm(i16,hw) |
| 926 | |
| 927 | INST1(movz, "movz", 0, 0, IF_DI_1B, 0x52800000) |
| 928 | // movz Rd,imm(i16,hw) DI_1B X10100101hwiiiii iiiiiiiiiiiddddd 5280 0000 imm(i16,hw) |
| 929 | |
| 930 | INST1(csel, "csel", 0, 0, IF_DR_3D, 0x1A800000) |
| 931 | // csel Rd,Rn,Rm,cond DR_3D X0011010100mmmmm cccc00nnnnnddddd 1A80 0000 cond |
| 932 | |
| 933 | INST1(csinc, "csinc", 0, 0, IF_DR_3D, 0x1A800400) |
| 934 | // csinc Rd,Rn,Rm,cond DR_3D X0011010100mmmmm cccc01nnnnnddddd 1A80 0400 cond |
| 935 | |
| 936 | INST1(csinv, "csinv", 0, 0, IF_DR_3D, 0x5A800000) |
| 937 | // csinv Rd,Rn,Rm,cond DR_3D X1011010100mmmmm cccc00nnnnnddddd 5A80 0000 cond |
| 938 | |
| 939 | INST1(csneg, "csneg", 0, 0, IF_DR_3D, 0x5A800400) |
| 940 | // csneg Rd,Rn,Rm,cond DR_3D X1011010100mmmmm cccc01nnnnnddddd 5A80 0400 cond |
| 941 | |
| 942 | INST1(cinc, "cinc", 0, 0, IF_DR_2D, 0x1A800400) |
| 943 | // cinc Rd,Rn,cond DR_2D X0011010100nnnnn cccc01nnnnnddddd 1A80 0400 cond |
| 944 | |
| 945 | INST1(cinv, "cinv", 0, 0, IF_DR_2D, 0x5A800000) |
| 946 | // cinv Rd,Rn,cond DR_2D X1011010100nnnnn cccc00nnnnnddddd 5A80 0000 cond |
| 947 | |
| 948 | INST1(cneg, "cneg", 0, 0, IF_DR_2D, 0x5A800400) |
| 949 | // cneg Rd,Rn,cond DR_2D X1011010100nnnnn cccc01nnnnnddddd 5A80 0400 cond |
| 950 | |
| 951 | INST1(cset, "cset", 0, 0, IF_DR_1D, 0x1A9F07E0) |
| 952 | // cset Rd,cond DR_1D X001101010011111 cccc0111111ddddd 1A9F 07E0 Rd cond |
| 953 | |
| 954 | INST1(csetm, "csetm", 0, 0, IF_DR_1D, 0x5A9F03E0) |
| 955 | // csetm Rd,cond DR_1D X101101010011111 cccc0011111ddddd 5A9F 03E0 Rd cond |
| 956 | |
| 957 | INST1(aese, "aese", 0, 0, IF_DV_2P, 0x4E284800) |
| 958 | // aese Vd.16B,Vn.16B DV_2P 0100111000101000 010010nnnnnddddd 4E28 4800 Vd.16B Vn.16B (vector) |
| 959 | |
| 960 | INST1(aesd, "aesd", 0, 0, IF_DV_2P, 0x4E285800) |
| 961 | // aesd Vd.16B,Vn.16B DV_2P 0100111000101000 010110nnnnnddddd 4E28 5800 Vd.16B Vn.16B (vector) |
| 962 | |
| 963 | INST1(aesmc, "aesmc", 0, 0, IF_DV_2P, 0x4E286800) |
| 964 | // aesmc Vd.16B,Vn.16B DV_2P 0100111000101000 011010nnnnnddddd 4E28 6800 Vd.16B Vn.16B (vector) |
| 965 | |
| 966 | INST1(aesimc, "aesimc", 0, 0, IF_DV_2P, 0x4E287800) |
| 967 | // aesimc Vd.16B,Vn.16B DV_2P 0100111000101000 011110nnnnnddddd 4E28 7800 Vd.16B Vn.16B (vector) |
| 968 | |
| 969 | INST1(rev, "rev", 0, 0, IF_DR_2G, 0x5AC00800) |
| 970 | // rev Rd,Rm DR_2G X101101011000000 00001Xnnnnnddddd 5AC0 0800 Rd Rn |
| 971 | |
| 972 | INST1(rev64, "rev64", 0, 0, IF_DV_2M, 0x0E200800) |
| 973 | // rev64 Vd,Vn DV_2M 0Q001110XX100000 000010nnnnnddddd 0E20 0800 Vd,Vn (vector) |
| 974 | |
| 975 | INST1(adc, "adc", 0, 0, IF_DR_3A, 0x1A000000) |
| 976 | // adc Rd,Rn,Rm DR_3A X0011010000mmmmm 000000nnnnnddddd 1A00 0000 |
| 977 | |
| 978 | INST1(adcs, "adcs", 0, 0, IF_DR_3A, 0x3A000000) |
| 979 | // adcs Rd,Rn,Rm DR_3A X0111010000mmmmm 000000nnnnnddddd 3A00 0000 |
| 980 | |
| 981 | INST1(sbc, "sbc", 0, 0, IF_DR_3A, 0x5A000000) |
| 982 | // sdc Rd,Rn,Rm DR_3A X1011010000mmmmm 000000nnnnnddddd 5A00 0000 |
| 983 | |
| 984 | INST1(sbcs, "sbcs", 0, 0, IF_DR_3A, 0x7A000000) |
| 985 | // sdcs Rd,Rn,Rm DR_3A X1111010000mmmmm 000000nnnnnddddd 7A00 0000 |
| 986 | |
| 987 | INST1(udiv, "udiv", 0, 0, IF_DR_3A, 0x1AC00800) |
| 988 | // udiv Rd,Rn,Rm DR_3A X0011010110mmmmm 000010nnnnnddddd 1AC0 0800 |
| 989 | |
| 990 | INST1(sdiv, "sdiv", 0, 0, IF_DR_3A, 0x1AC00C00) |
| 991 | // sdiv Rd,Rn,Rm DR_3A X0011010110mmmmm 000011nnnnnddddd 1AC0 0C00 |
| 992 | |
| 993 | INST1(mneg, "mneg", 0, 0, IF_DR_3A, 0x1B00FC00) |
| 994 | // mneg Rd,Rn,Rm DR_3A X0011011000mmmmm 111111nnnnnddddd 1B00 FC00 |
| 995 | |
| 996 | INST1(madd, "madd", 0, 0, IF_DR_4A, 0x1B000000) |
| 997 | // madd Rd,Rn,Rm,Ra DR_4A X0011011000mmmmm 0aaaaannnnnddddd 1B00 0000 |
| 998 | |
| 999 | INST1(msub, "msub", 0, 0, IF_DR_4A, 0x1B008000) |
| 1000 | // msub Rd,Rn,Rm,Ra DR_4A X0011011000mmmmm 1aaaaannnnnddddd 1B00 8000 |
| 1001 | |
| 1002 | INST1(smull, "smull", 0, 0, IF_DR_3A, 0x9B207C00) |
| 1003 | // smull Rd,Rn,Rm DR_3A 10011011001mmmmm 011111nnnnnddddd 9B20 7C00 |
| 1004 | |
| 1005 | INST1(smaddl, "smaddl", 0, 0, IF_DR_4A, 0x9B200000) |
| 1006 | // smaddl Rd,Rn,Rm,Ra DR_4A 10011011001mmmmm 0aaaaannnnnddddd 9B20 0000 |
| 1007 | |
| 1008 | INST1(smnegl, "smnegl", 0, 0, IF_DR_3A, 0x9B20FC00) |
| 1009 | // smnegl Rd,Rn,Rm DR_3A 10011011001mmmmm 111111nnnnnddddd 9B20 FC00 |
| 1010 | |
| 1011 | INST1(smsubl, "smsubl", 0, 0, IF_DR_4A, 0x9B208000) |
| 1012 | // smsubl Rd,Rn,Rm,Ra DR_4A 10011011001mmmmm 1aaaaannnnnddddd 9B20 8000 |
| 1013 | |
| 1014 | INST1(smulh, "smulh", 0, 0, IF_DR_3A, 0x9B407C00) |
| 1015 | // smulh Rd,Rn,Rm DR_3A 10011011010mmmmm 011111nnnnnddddd 9B40 7C00 |
| 1016 | |
| 1017 | INST1(umull, "umull", 0, 0, IF_DR_3A, 0x9BA07C00) |
| 1018 | // umull Rd,Rn,Rm DR_3A 10011011101mmmmm 011111nnnnnddddd 9BA0 7C00 |
| 1019 | |
| 1020 | INST1(umaddl, "umaddl", 0, 0, IF_DR_4A, 0x9BA00000) |
| 1021 | // umaddl Rd,Rn,Rm,Ra DR_4A 10011011101mmmmm 0aaaaannnnnddddd 9BA0 0000 |
| 1022 | |
| 1023 | INST1(umnegl, "umnegl", 0, 0, IF_DR_3A, 0x9BA0FC00) |
| 1024 | // umnegl Rd,Rn,Rm DR_3A 10011011101mmmmm 111111nnnnnddddd 9BA0 FC00 |
| 1025 | |
| 1026 | INST1(umsubl, "umsubl", 0, 0, IF_DR_4A, 0x9BA08000) |
| 1027 | // umsubl Rd,Rn,Rm,Ra DR_4A 10011011101mmmmm 1aaaaannnnnddddd 9BA0 8000 |
| 1028 | |
| 1029 | INST1(umulh, "umulh", 0, 0, IF_DR_3A, 0x9BC07C00) |
| 1030 | // umulh Rd,Rn,Rm DR_3A 10011011110mmmmm 011111nnnnnddddd 9BC0 7C00 |
| 1031 | |
| 1032 | INST1(extr, "extr", 0, 0, IF_DR_3E, 0x13800000) |
| 1033 | // extr Rd,Rn,Rm,imm6 DR_3E X00100111X0mmmmm ssssssnnnnnddddd 1380 0000 imm(0-63) |
| 1034 | |
| 1035 | INST1(lslv, "lslv", 0, 0, IF_DR_3A, 0x1AC02000) |
| 1036 | // lslv Rd,Rn,Rm DR_3A X0011010110mmmmm 001000nnnnnddddd 1AC0 2000 |
| 1037 | |
| 1038 | INST1(lsrv, "lsrv", 0, 0, IF_DR_3A, 0x1AC02400) |
| 1039 | // lsrv Rd,Rn,Rm DR_3A X0011010110mmmmm 001001nnnnnddddd 1AC0 2400 |
| 1040 | |
| 1041 | INST1(asrv, "asrv", 0, 0, IF_DR_3A, 0x1AC02800) |
| 1042 | // asrv Rd,Rn,Rm DR_3A X0011010110mmmmm 001010nnnnnddddd 1AC0 2800 |
| 1043 | |
| 1044 | INST1(rorv, "rorv", 0, 0, IF_DR_3A, 0x1AC02C00) |
| 1045 | // rorv Rd,Rn,Rm DR_3A X0011010110mmmmm 001011nnnnnddddd 1AC0 2C00 |
| 1046 | |
| 1047 | INST1(sha1c, "sha1c", 0, 0, IF_DV_3F, 0x5E000000) |
| 1048 | // sha1c Qd, Sn Vm.4S DV_3F 01011110000mmmmm 000000nnnnnddddd 5E00 0000 Qd Sn Vm.4S (vector) |
| 1049 | |
| 1050 | INST1(sha1m, "sha1m", 0, 0, IF_DV_3F, 0x5E002000) |
| 1051 | // sha1m Qd, Sn Vm.4S DV_3F 01011110000mmmmm 001000nnnnnddddd 5E00 0000 Qd Sn Vm.4S (vector) |
| 1052 | |
| 1053 | INST1(sha1p, "sha1p", 0, 0, IF_DV_3F, 0x5E001000) |
| 1054 | // sha1m Qd, Sn Vm.4S DV_3F 01011110000mmmmm 000100nnnnnddddd 5E00 0000 Qd Sn Vm.4S (vector) |
| 1055 | |
| 1056 | INST1(sha1h, "sha1h", 0, 0, IF_DR_2J, 0x5E280800) |
| 1057 | // sha1h Sd, Sn DR_2H 0101111000101000 000010nnnnnddddd 5E28 0800 Sn Sn |
| 1058 | |
| 1059 | INST1(sha1su0, "sha1su0", 0, 0, IF_DV_3F, 0x5E003000) |
| 1060 | // sha1su0 Vd.4S,Vn.4S,Vm.4S DV_3F 01011110000mmmmm 001100nnnnnddddd 5E00 3000 Vd.4S Vn.4S Vm.4S (vector) |
| 1061 | |
| 1062 | INST1(sha1su1, "sha1su1", 0, 0, IF_DV_2P, 0x5E281800) |
| 1063 | // sha1su1 Vd.4S, Vn.4S DV_2P 0101111000101000 000110nnnnnddddd 5E28 1800 Vd.4S Vn.4S (vector) |
| 1064 | |
| 1065 | INST1(sha256h, "sha256h", 0, 0, IF_DV_3F, 0x5E004000) |
| 1066 | // sha256h Qd,Qn,Vm.4S DV_3F 01011110000mmmmm 010000nnnnnddddd 5E00 4000 Qd Qn Vm.4S (vector) |
| 1067 | |
| 1068 | INST1(sha256h2, "sha256h2", 0, 0, IF_DV_3F, 0x5E005000) |
| 1069 | // sha256h Qd,Qn,Vm.4S DV_3F 01011110000mmmmm 010100nnnnnddddd 5E00 5000 Qd Qn Vm.4S (vector) |
| 1070 | |
| 1071 | INST1(sha256su0, "sha256su0", 0, 0, IF_DV_2P, 0x5E282800) |
| 1072 | // sha256su0 Vd.4S,Vn.4S DV_2P 0101111000101000 001010nnnnnddddd 5E28 2800 Vd.4S Vn.4S (vector) |
| 1073 | |
| 1074 | INST1(sha256su1, "sha256su1", 0, 0, IF_DV_3F, 0x5E006000) |
| 1075 | // sha256su1 Vd.4S,Vn.4S,Vm.4S DV_3F 01011110000mmmmm 011000nnnnnddddd 5E00 6000 Vd.4S Vn.4S Vm.4S (vector) |
| 1076 | |
| 1077 | INST1(sbfm, "sbfm", 0, 0, IF_DI_2D, 0x13000000) |
| 1078 | // sbfm Rd,Rn,imr,ims DI_2D X00100110Nrrrrrr ssssssnnnnnddddd 1300 0000 imr, ims |
| 1079 | |
| 1080 | INST1(bfm, "bfm", 0, 0, IF_DI_2D, 0x33000000) |
| 1081 | // bfm Rd,Rn,imr,ims DI_2D X01100110Nrrrrrr ssssssnnnnnddddd 3300 0000 imr, ims |
| 1082 | |
| 1083 | INST1(ubfm, "ubfm", 0, 0, IF_DI_2D, 0x53000000) |
| 1084 | // ubfm Rd,Rn,imr,ims DI_2D X10100110Nrrrrrr ssssssnnnnnddddd 5300 0000 imr, ims |
| 1085 | |
| 1086 | INST1(sbfiz, "sbfiz", 0, 0, IF_DI_2D, 0x13000000) |
| 1087 | // sbfiz Rd,Rn,lsb,width DI_2D X00100110Nrrrrrr ssssssnnnnnddddd 1300 0000 imr, ims |
| 1088 | |
| 1089 | INST1(bfi, "bfi", 0, 0, IF_DI_2D, 0x33000000) |
| 1090 | // bfi Rd,Rn,lsb,width DI_2D X01100110Nrrrrrr ssssssnnnnnddddd 3300 0000 imr, ims |
| 1091 | |
| 1092 | INST1(ubfiz, "ubfiz", 0, 0, IF_DI_2D, 0x53000000) |
| 1093 | // ubfiz Rd,Rn,lsb,width DI_2D X10100110Nrrrrrr ssssssnnnnnddddd 5300 0000 imr, ims |
| 1094 | |
| 1095 | INST1(sbfx, "sbfx", 0, 0, IF_DI_2D, 0x13000000) |
| 1096 | // sbfx Rd,Rn,lsb,width DI_2D X00100110Nrrrrrr ssssssnnnnnddddd 1300 0000 imr, ims |
| 1097 | |
| 1098 | INST1(bfxil, "bfxil", 0, 0, IF_DI_2D, 0x33000000) |
| 1099 | // bfxil Rd,Rn,lsb,width DI_2D X01100110Nrrrrrr ssssssnnnnnddddd 3300 0000 imr, ims |
| 1100 | |
| 1101 | INST1(ubfx, "ubfx", 0, 0, IF_DI_2D, 0x53000000) |
| 1102 | // ubfx Rd,Rn,lsb,width DI_2D X10100110Nrrrrrr ssssssnnnnnddddd 5300 0000 imr, ims |
| 1103 | |
| 1104 | INST1(sxtb, "sxtb", 0, 0, IF_DR_2H, 0x13001C00) |
| 1105 | // sxtb Rd,Rn DR_2H X00100110X000000 000111nnnnnddddd 1300 1C00 |
| 1106 | |
| 1107 | INST1(sxth, "sxth", 0, 0, IF_DR_2H, 0x13003C00) |
| 1108 | // sxth Rd,Rn DR_2H X00100110X000000 001111nnnnnddddd 1300 3C00 |
| 1109 | |
| 1110 | INST1(sxtw, "sxtw", 0, 0, IF_DR_2H, 0x13007C00) |
| 1111 | // sxtw Rd,Rn DR_2H X00100110X000000 011111nnnnnddddd 1300 7C00 |
| 1112 | |
| 1113 | INST1(uxtb, "uxtb", 0, 0, IF_DR_2H, 0x53001C00) |
| 1114 | // uxtb Rd,Rn DR_2H 0101001100000000 000111nnnnnddddd 5300 1C00 |
| 1115 | |
| 1116 | INST1(uxth, "uxth", 0, 0, IF_DR_2H, 0x53003C00) |
| 1117 | // uxth Rd,Rn DR_2H 0101001100000000 001111nnnnnddddd 5300 3C00 |
| 1118 | |
| 1119 | INST1(nop, "nop", 0, 0, IF_SN_0A, 0xD503201F) |
| 1120 | // nop SN_0A 1101010100000011 0010000000011111 D503 201F |
| 1121 | |
| 1122 | INST1(bkpt, "bkpt", 0, 0, IF_SN_0A, 0xD43E0000) |
| 1123 | // brpt SN_0A 1101010000111110 0000000000000000 D43E 0000 0xF000 |
| 1124 | |
| 1125 | INST1(brk, "brk", 0, 0, IF_SI_0A, 0xD4200000) |
| 1126 | // brk imm16 SI_0A 11010100001iiiii iiiiiiiiiii00000 D420 0000 imm16 |
| 1127 | |
| 1128 | INST1(dsb, "dsb", 0, 0, IF_SI_0B, 0xD503309F) |
| 1129 | // dsb barrierKind SI_0B 1101010100000011 0011bbbb10011111 D503 309F imm4 - barrier kind |
| 1130 | |
| 1131 | INST1(dmb, "dmb", 0, 0, IF_SI_0B, 0xD50330BF) |
| 1132 | // dmb barrierKind SI_0B 1101010100000011 0011bbbb10111111 D503 30BF imm4 - barrier kind |
| 1133 | |
| 1134 | INST1(isb, "isb", 0, 0, IF_SI_0B, 0xD50330DF) |
| 1135 | // isb barrierKind SI_0B 1101010100000011 0011bbbb11011111 D503 30DF imm4 - barrier kind |
| 1136 | |
| 1137 | INST1(umov, "umov", 0, 0, IF_DV_2B, 0x0E003C00) |
| 1138 | // umov Rd,Vn[] DV_2B 0Q001110000iiiii 001111nnnnnddddd 0E00 3C00 Rd,Vn[] |
| 1139 | |
| 1140 | INST1(smov, "smov", 0, 0, IF_DV_2B, 0x0E002C00) |
| 1141 | // smov Rd,Vn[] DV_2B 0Q001110000iiiii 001011nnnnnddddd 0E00 3C00 Rd,Vn[] |
| 1142 | |
| 1143 | INST1(movi, "movi", 0, 0, IF_DV_1B, 0x0F000400) |
| 1144 | // movi Vd,imm8 DV_1B 0QX0111100000iii cmod01iiiiiddddd 0F00 0400 Vd imm8 (immediate vector) |
| 1145 | |
| 1146 | INST1(mvni, "mvni", 0, 0, IF_DV_1B, 0x2F000400) |
| 1147 | // mvni Vd,imm8 DV_1B 0Q10111100000iii cmod01iiiiiddddd 2F00 0400 Vd imm8 (immediate vector) |
| 1148 | |
| 1149 | INST1(bsl, "bsl", 0, 0, IF_DV_3C, 0x2E601C00) |
| 1150 | // bsl Vd,Vn,Vm DV_3C 0Q101110011mmmmm 000111nnnnnddddd 2E60 1C00 Vd,Vn,Vm |
| 1151 | |
| 1152 | INST1(bit, "bit", 0, 0, IF_DV_3C, 0x2EA01C00) |
| 1153 | // bit Vd,Vn,Vm DV_3C 0Q101110101mmmmm 000111nnnnnddddd 2EA0 1C00 Vd,Vn,Vm |
| 1154 | |
| 1155 | INST1(bif, "bif", 0, 0, IF_DV_3C, 0x2EE01C00) |
| 1156 | // bif Vd,Vn,Vm DV_3C 0Q101110111mmmmm 000111nnnnnddddd 2EE0 1C00 Vd,Vn,Vm |
| 1157 | |
| 1158 | INST1(addv, "addv", 0, 0, IF_DV_2M, 0x0E31B800) |
| 1159 | // addv Vd,Vn DV_2M 0Q001110XX110001 101110nnnnnddddd 0E31 B800 Vd,Vn (vector) |
| 1160 | |
| 1161 | INST1(cnt, "cnt", 0, 0, IF_DV_2M, 0x0E205800) |
| 1162 | // cnt Vd,Vn DV_2M 0Q00111000100000 010110nnnnnddddd 0E20 5800 Vd,Vn (vector) |
| 1163 | |
| 1164 | INST1(not, "not", 0, 0, IF_DV_2M, 0x2E205800) |
| 1165 | // not Vd,Vn DV_2M 0Q10111000100000 010110nnnnnddddd 2E20 5800 Vd,Vn (vector) |
| 1166 | |
| 1167 | INST1(saddlv, "saddlv", 0, 0, IF_DV_2M, 0x0E303800) |
| 1168 | // saddlv Vd,Vn DV_2M 0Q001110XX110000 001110nnnnnddddd 0E30 3800 Vd,Vn (vector) |
| 1169 | |
| 1170 | INST1(smaxv, "smaxv", 0, 0, IF_DV_2M, 0x0E30A800) |
| 1171 | // smaxv Vd,Vn DV_2M 0Q001110XX110000 101010nnnnnddddd 0E30 A800 Vd,Vn (vector) |
| 1172 | |
| 1173 | INST1(sminv, "sminv", 0, 0, IF_DV_2M, 0x0E31A800) |
| 1174 | // sminv Vd,Vn DV_2M 0Q001110XX110001 101010nnnnnddddd 0E31 A800 Vd,Vn (vector) |
| 1175 | |
| 1176 | INST1(uaddlv, "uaddlv", 0, 0, IF_DV_2M, 0x2E303800) |
| 1177 | // uaddlv Vd,Vn DV_2M 0Q101110XX110000 001110nnnnnddddd 2E30 3800 Vd,Vn (vector) |
| 1178 | |
| 1179 | INST1(umaxv, "umaxv", 0, 0, IF_DV_2M, 0x2E30A800) |
| 1180 | // umaxv Vd,Vn DV_2M 0Q101110XX110000 101010nnnnnddddd 2E30 A800 Vd,Vn (vector) |
| 1181 | |
| 1182 | INST1(uminv, "uminv", 0, 0, IF_DV_2M, 0x2E31A800) |
| 1183 | // uminv Vd,Vn DV_2M 0Q101110XX110001 101010nnnnnddddd 2E31 A800 Vd,Vn (vector) |
| 1184 | |
| 1185 | INST1(xtn, "xtn", 0, 0, IF_DV_2M, 0x0E212800) |
| 1186 | // xtn Vd,Vn DV_2M 00101110XX110000 001110nnnnnddddd 0E21 2800 Vd,Vn (vector) |
| 1187 | |
| 1188 | INST1(xtn2, "xtn2", 0, 0, IF_DV_2M, 0x4E212800) |
| 1189 | // xtn2 Vd,Vn DV_2M 01101110XX110000 001110nnnnnddddd 4E21 2800 Vd,Vn (vector) |
| 1190 | |
| 1191 | INST1(fnmul, "fnmul", 0, 0, IF_DV_3D, 0x1E208800) |
| 1192 | // fnmul Vd,Vn,Vm DV_3D 000111100X1mmmmm 100010nnnnnddddd 1E20 8800 Vd,Vn,Vm (scalar) |
| 1193 | |
| 1194 | INST1(fmadd, "fmadd", 0, 0, IF_DV_4A, 0x1F000000) |
| 1195 | // fmadd Vd,Va,Vn,Vm DV_4A 000111110X0mmmmm 0aaaaannnnnddddd 1F00 0000 Vd Vn Vm Va (scalar) |
| 1196 | |
| 1197 | INST1(fmsub, "fmsub", 0, 0, IF_DV_4A, 0x1F008000) |
| 1198 | // fmsub Vd,Va,Vn,Vm DV_4A 000111110X0mmmmm 1aaaaannnnnddddd 1F00 8000 Vd Vn Vm Va (scalar) |
| 1199 | |
| 1200 | INST1(fnmadd, "fnmadd", 0, 0, IF_DV_4A, 0x1F200000) |
| 1201 | // fnmadd Vd,Va,Vn,Vm DV_4A 000111110X1mmmmm 0aaaaannnnnddddd 1F20 0000 Vd Vn Vm Va (scalar) |
| 1202 | |
| 1203 | INST1(fnmsub, "fnmsub", 0, 0, IF_DV_4A, 0x1F208000) |
| 1204 | // fnmsub Vd,Va,Vn,Vm DV_4A 000111110X1mmmmm 1aaaaannnnnddddd 1F20 8000 Vd Vn Vm Va (scalar) |
| 1205 | |
| 1206 | INST1(fcvt, "fcvt", 0, 0, IF_DV_2J, 0x1E224000) |
| 1207 | // fcvt Vd,Vn DV_2J 00011110SS10001D D10000nnnnnddddd 1E22 4000 Vd,Vn |
| 1208 | |
| 1209 | INST1(pmul, "pmul", 0, 0, IF_DV_3A, 0x2E209C00) |
| 1210 | // pmul Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 100111nnnnnddddd 2E20 9C00 Vd,Vn,Vm (vector) |
| 1211 | |
| 1212 | INST1(saba, "saba", 0, 0, IF_DV_3A, 0x0E207C00) |
| 1213 | // saba Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 011111nnnnnddddd 0E20 7C00 Vd,Vn,Vm (vector) |
| 1214 | |
| 1215 | INST1(sabd, "sabd", 0, 0, IF_DV_3A, 0x0E207400) |
| 1216 | // sabd Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 011101nnnnnddddd 0E20 7400 Vd,Vn,Vm (vector) |
| 1217 | |
| 1218 | INST1(smax, "smax", 0, 0, IF_DV_3A, 0x0E206400) |
| 1219 | // smax Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 011001nnnnnddddd 0E20 6400 Vd,Vn,Vm (vector) |
| 1220 | |
| 1221 | INST1(smin, "smin", 0, 0, IF_DV_3A, 0x0E206C00) |
| 1222 | // smax Vd,Vn,Vm DV_3A 0Q001110XX1mmmmm 011011nnnnnddddd 0E20 6C00 Vd,Vn,Vm (vector) |
| 1223 | |
| 1224 | INST1(uaba, "uaba", 0, 0, IF_DV_3A, 0x2E207C00) |
| 1225 | // uaba Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 011111nnnnnddddd 2E20 7C00 Vd,Vn,Vm (vector) |
| 1226 | |
| 1227 | INST1(uabd, "uabd", 0, 0, IF_DV_3A, 0x2E207400) |
| 1228 | // uabd Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 011101nnnnnddddd 2E20 7400 Vd,Vn,Vm (vector) |
| 1229 | |
| 1230 | INST1(umax, "umax", 0, 0, IF_DV_3A, 0x2E206400) |
| 1231 | // umax Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 011001nnnnnddddd 2E20 6400 Vd,Vn,Vm (vector) |
| 1232 | |
| 1233 | INST1(umin, "umin", 0, 0, IF_DV_3A, 0x2E206C00) |
| 1234 | // umin Vd,Vn,Vm DV_3A 0Q101110XX1mmmmm 011011nnnnnddddd 2E20 6C00 Vd,Vn,Vm (vector) |
| 1235 | |
| 1236 | INST1(fcvtl, "fcvtl", 0, 0, IF_DV_2G, 0x0E217800) |
| 1237 | // fcvtl Vd,Vn DV_2G 000011100X100001 011110nnnnnddddd 0E21 7800 Vd,Vn (scalar) |
| 1238 | |
| 1239 | INST1(fcvtl2, "fcvtl2", 0, 0, IF_DV_2G, 0x4E217800) |
| 1240 | // fcvtl2 Vd,Vn DV_2G 040011100X100001 011110nnnnnddddd 4E21 7800 Vd,Vn (scalar) |
| 1241 | |
| 1242 | INST1(fcvtn, "fcvtn", 0, 0, IF_DV_2G, 0x0E216800) |
| 1243 | // fcvtn Vd,Vn DV_2G 000011100X100001 011010nnnnnddddd 0E21 6800 Vd,Vn (scalar) |
| 1244 | |
| 1245 | INST1(fcvtn2, "fcvtn2", 0, 0, IF_DV_2G, 0x4E216800) |
| 1246 | // fcvtn2 Vd,Vn DV_2G 040011100X100001 011010nnnnnddddd 4E21 6800 Vd,Vn (scalar) |
| 1247 | |
| 1248 | INST1(shll, "shll", 0, 0, IF_DV_2M, 0x2F00A400) |
| 1249 | // shll Vd,Vn,imm DV_2M 0Q101110XX100001 001110nnnnnddddd 2E21 3800 Vd,Vn, {8/16/32} |
| 1250 | |
| 1251 | INST1(shll2, "shll2", 0, 0, IF_DV_2M, 0x6F00A400) |
| 1252 | // shll Vd,Vn,imm DV_2M 0Q101110XX100001 001110nnnnnddddd 2E21 3800 Vd,Vn, {8/16/32} |
| 1253 | |
| 1254 | INST1(sshll, "sshll", 0, 0, IF_DV_2O, 0x0F00A400) |
| 1255 | // sshll Vd,Vn,imm DV_2O 000011110iiiiiii 101001nnnnnddddd 0F00 A400 Vd,Vn imm (shift - vector) |
| 1256 | |
| 1257 | INST1(sshll2, "sshll2", 0, 0, IF_DV_2O, 0x4F00A400) |
| 1258 | // sshll2 Vd,Vn,imm DV_2O 010011110iiiiiii 101001nnnnnddddd 4F00 A400 Vd,Vn imm (shift - vector) |
| 1259 | |
| 1260 | INST1(ushll, "ushll", 0, 0, IF_DV_2O, 0x2F00A400) |
| 1261 | // ushll Vd,Vn,imm DV_2O 001011110iiiiiii 101001nnnnnddddd 2F00 A400 Vd,Vn imm (shift - vector) |
| 1262 | |
| 1263 | INST1(ushll2, "ushll2", 0, 0, IF_DV_2O, 0x6F00A400) |
| 1264 | // ushll2 Vd,Vn,imm DV_2O 011011110iiiiiii 101001nnnnnddddd 6F00 A400 Vd,Vn imm (shift - vector) |
| 1265 | |
| 1266 | INST1(shrn, "shrn", 0, 0, IF_DV_2O, 0x0F008400) |
| 1267 | // shrn Vd,Vn,imm DV_2O 000011110iiiiiii 100001nnnnnddddd 0F00 8400 Vd,Vn imm (shift - vector) |
| 1268 | |
| 1269 | INST1(shrn2, "shrn2", 0, 0, IF_DV_2O, 0x4F008400) |
| 1270 | // shrn2 Vd,Vn,imm DV_2O 010011110iiiiiii 100001nnnnnddddd 4F00 8400 Vd,Vn imm (shift - vector) |
| 1271 | |
| 1272 | INST1(rshrn, "rshrn", 0, 0, IF_DV_2O, 0x0F008C00) |
| 1273 | // rshrn Vd,Vn,imm DV_2O 000011110iiiiiii 100011nnnnnddddd 0F00 8C00 Vd,Vn imm (shift - vector) |
| 1274 | |
| 1275 | INST1(rshrn2, "rshrn2", 0, 0, IF_DV_2O, 0x4F008C00) |
| 1276 | // rshrn2 Vd,Vn,imm DV_2O 010011110iiiiiii 100011nnnnnddddd 4F00 8C00 Vd,Vn imm (shift - vector) |
| 1277 | |
| 1278 | INST1(sxtl, "sxtl", 0, 0, IF_DV_2O, 0x0F00A400) |
| 1279 | // sxtl Vd,Vn DV_2O 000011110iiiiiii 101001nnnnnddddd 0F00 A400 Vd,Vn (shift - vector) |
| 1280 | |
| 1281 | INST1(sxtl2, "sxtl2", 0, 0, IF_DV_2O, 0x4F00A400) |
| 1282 | // sxtl2 Vd,Vn DV_2O 010011110iiiiiii 101001nnnnnddddd 4F00 A400 Vd,Vn (shift - vector) |
| 1283 | |
| 1284 | INST1(uxtl, "uxtl", 0, 0, IF_DV_2O, 0x2F00A400) |
| 1285 | // uxtl Vd,Vn DV_2O 001011110iiiiiii 101001nnnnnddddd 2F00 A400 Vd,Vn (shift - vector) |
| 1286 | |
| 1287 | INST1(uxtl2, "uxtl2", 0, 0, IF_DV_2O, 0x6F00A400) |
| 1288 | // uxtl2 Vd,Vn DV_2O 011011110iiiiiii 101001nnnnnddddd 6F00 A400 Vd,Vn (shift - vector) |
| 1289 | // clang-format on |
| 1290 | |
| 1291 | /*****************************************************************************/ |
| 1292 | #undef INST1 |
| 1293 | #undef INST2 |
| 1294 | #undef INST3 |
| 1295 | #undef INST4 |
| 1296 | #undef INST5 |
| 1297 | #undef INST6 |
| 1298 | #undef INST9 |
| 1299 | /*****************************************************************************/ |
| 1300 |
Generated while processing CoreCLR/jit/codegenarm64.cpp
Generated on 2019-Jan-08 from project CoreCLR revision 2.1
Powered by 
Code Browser 2.1
Generator usage only permitted with license.