1/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
2 * All rights reserved.
3 *
4 * This package is an SSL implementation written
5 * by Eric Young (eay@cryptsoft.com).
6 * The implementation was written so as to conform with Netscapes SSL.
7 *
8 * This library is free for commercial and non-commercial use as long as
9 * the following conditions are aheared to. The following conditions
10 * apply to all code found in this distribution, be it the RC4, RSA,
11 * lhash, DES, etc., code; not just the SSL code. The SSL documentation
12 * included with this distribution is covered by the same copyright terms
13 * except that the holder is Tim Hudson (tjh@cryptsoft.com).
14 *
15 * Copyright remains Eric Young's, and as such any Copyright notices in
16 * the code are not to be removed.
17 * If this package is used in a product, Eric Young should be given attribution
18 * as the author of the parts of the library used.
19 * This can be in the form of a textual message at program startup or
20 * in documentation (online or textual) provided with the package.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 * 1. Redistributions of source code must retain the copyright
26 * notice, this list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright
28 * notice, this list of conditions and the following disclaimer in the
29 * documentation and/or other materials provided with the distribution.
30 * 3. All advertising materials mentioning features or use of this software
31 * must display the following acknowledgement:
32 * "This product includes cryptographic software written by
33 * Eric Young (eay@cryptsoft.com)"
34 * The word 'cryptographic' can be left out if the rouines from the library
35 * being used are not cryptographic related :-).
36 * 4. If you include any Windows specific code (or a derivative thereof) from
37 * the apps directory (application code) you must include an acknowledgement:
38 * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
39 *
40 * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
52 * The licence and distribution terms for any publically available version or
53 * derivative of this code cannot be changed. i.e. this code cannot simply be
54 * copied and put under another distribution licence
55 * [including the GNU Public Licence.] */
56
57#include <openssl/cpu.h>
58
59
60#if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
61
62#include <inttypes.h>
63#include <stdio.h>
64#include <stdlib.h>
65#include <string.h>
66
67#if defined(_MSC_VER)
68OPENSSL_MSVC_PRAGMA(warning(push, 3))
69#include <immintrin.h>
70#include <intrin.h>
71OPENSSL_MSVC_PRAGMA(warning(pop))
72#endif
73
74#include "internal.h"
75
76
77// OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
78// is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
79// |*out_edx|.
80static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
81 uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
82#if defined(_MSC_VER)
83 int tmp[4];
84 __cpuid(tmp, (int)leaf);
85 *out_eax = (uint32_t)tmp[0];
86 *out_ebx = (uint32_t)tmp[1];
87 *out_ecx = (uint32_t)tmp[2];
88 *out_edx = (uint32_t)tmp[3];
89#elif defined(__pic__) && defined(OPENSSL_32_BIT)
90 // Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
91 // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
92 __asm__ volatile (
93 "xor %%ecx, %%ecx\n"
94 "mov %%ebx, %%edi\n"
95 "cpuid\n"
96 "xchg %%edi, %%ebx\n"
97 : "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
98 : "a"(leaf)
99 );
100#else
101 __asm__ volatile (
102 "xor %%ecx, %%ecx\n"
103 "cpuid\n"
104 : "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
105 : "a"(leaf)
106 );
107#endif
108}
109
110// OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
111// Currently only XCR0 is defined by Intel so |xcr| should always be zero.
112static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
113#if defined(_MSC_VER)
114 return (uint64_t)_xgetbv(xcr);
115#else
116 uint32_t eax, edx;
117 __asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
118 return (((uint64_t)edx) << 32) | eax;
119#endif
120}
121
122// handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
123// and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this.
124static void handle_cpu_env(uint32_t *out, const char *in) {
125 const int invert = in[0] == '~';
126 uint64_t v;
127
128 if (!sscanf(in + invert, "%" PRIu64, &v)) {
129 return;
130 }
131
132 if (invert) {
133 out[0] &= ~v;
134 out[1] &= ~(v >> 32);
135 } else {
136 out[0] = v;
137 out[1] = v >> 32;
138 }
139}
140
141void OPENSSL_cpuid_setup(void) {
142 // Determine the vendor and maximum input value.
143 uint32_t eax, ebx, ecx, edx;
144 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
145
146 uint32_t num_ids = eax;
147
148 int is_intel = ebx == 0x756e6547 /* Genu */ &&
149 edx == 0x49656e69 /* ineI */ &&
150 ecx == 0x6c65746e /* ntel */;
151 int is_amd = ebx == 0x68747541 /* Auth */ &&
152 edx == 0x69746e65 /* enti */ &&
153 ecx == 0x444d4163 /* cAMD */;
154
155 uint32_t extended_features[2] = {0};
156 if (num_ids >= 7) {
157 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
158 extended_features[0] = ebx;
159 extended_features[1] = ecx;
160 }
161
162 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
163
164 if (is_amd) {
165 // See https://www.amd.com/system/files/TechDocs/25481.pdf, page 10.
166 const uint32_t base_family = (eax >> 8) & 15;
167
168 uint32_t family = base_family;
169 if (base_family == 0xf) {
170 const uint32_t ext_family = (eax >> 20) & 255;
171 family += ext_family;
172 }
173
174 if (family < 0x17) {
175 // Disable RDRAND on AMD families before 0x17 (Zen) due to reported
176 // failures after suspend.
177 // https://bugzilla.redhat.com/show_bug.cgi?id=1150286
178 ecx &= ~(1u << 30);
179 }
180 }
181
182 // Force the hyper-threading bit so that the more conservative path is always
183 // chosen.
184 edx |= 1u << 28;
185
186 // Reserved bit #20 was historically repurposed to control the in-memory
187 // representation of RC4 state. Always set it to zero.
188 edx &= ~(1u << 20);
189
190 // Reserved bit #30 is repurposed to signal an Intel CPU.
191 if (is_intel) {
192 edx |= (1u << 30);
193
194 // Clear the XSAVE bit on Knights Landing to mimic Silvermont. This enables
195 // some Silvermont-specific codepaths which perform better. See OpenSSL
196 // commit 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
197 if ((eax & 0x0fff0ff0) == 0x00050670 /* Knights Landing */ ||
198 (eax & 0x0fff0ff0) == 0x00080650 /* Knights Mill (per SDE) */) {
199 ecx &= ~(1u << 26);
200 }
201 } else {
202 edx &= ~(1u << 30);
203 }
204
205 // The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD
206 // XOP code paths.
207 ecx &= ~(1u << 11);
208
209 uint64_t xcr0 = 0;
210 if (ecx & (1u << 27)) {
211 // XCR0 may only be queried if the OSXSAVE bit is set.
212 xcr0 = OPENSSL_xgetbv(0);
213 }
214 // See Intel manual, volume 1, section 14.3.
215 if ((xcr0 & 6) != 6) {
216 // YMM registers cannot be used.
217 ecx &= ~(1u << 28); // AVX
218 ecx &= ~(1u << 12); // FMA
219 ecx &= ~(1u << 11); // AMD XOP
220 // Clear AVX2 and AVX512* bits.
221 //
222 // TODO(davidben): Should bits 17 and 26-28 also be cleared? Upstream
223 // doesn't clear those.
224 extended_features[0] &=
225 ~((1u << 5) | (1u << 16) | (1u << 21) | (1u << 30) | (1u << 31));
226 }
227 // See Intel manual, volume 1, section 15.2.
228 if ((xcr0 & 0xe6) != 0xe6) {
229 // Clear AVX512F. Note we don't touch other AVX512 extensions because they
230 // can be used with YMM.
231 extended_features[0] &= ~(1u << 16);
232 }
233
234 // Disable ADX instructions on Knights Landing. See OpenSSL commit
235 // 64d92d74985ebb3d0be58a9718f9e080a14a8e7f.
236 if ((ecx & (1u << 26)) == 0) {
237 extended_features[0] &= ~(1u << 19);
238 }
239
240 OPENSSL_ia32cap_P[0] = edx;
241 OPENSSL_ia32cap_P[1] = ecx;
242 OPENSSL_ia32cap_P[2] = extended_features[0];
243 OPENSSL_ia32cap_P[3] = extended_features[1];
244
245 const char *env1, *env2;
246 env1 = getenv("OPENSSL_ia32cap");
247 if (env1 == NULL) {
248 return;
249 }
250
251 // OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
252 // Each value is a 64-bit, unsigned value which may start with "0x" to
253 // indicate a hex value. Prior to the 64-bit value, a '~' may be given.
254 //
255 // If '~' isn't present, then the value is taken as the result of the CPUID.
256 // Otherwise the value is inverted and ANDed with the probed CPUID result.
257 //
258 // The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
259 // and [3].
260
261 handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
262 env2 = strchr(env1, ':');
263 if (env2 != NULL) {
264 handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
265 }
266}
267
268#endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)
269