1/*
2** x86/x64 IR assembler (SSA IR -> machine code).
3** Copyright (C) 2005-2021 Mike Pall. See Copyright Notice in luajit.h
4*/
5
6/* -- Guard handling ------------------------------------------------------ */
7
8/* Generate an exit stub group at the bottom of the reserved MCode memory. */
9static MCode *asm_exitstub_gen(ASMState *as, ExitNo group)
10{
11 ExitNo i, groupofs = (group*EXITSTUBS_PER_GROUP) & 0xff;
12 MCode *mxp = as->mcbot;
13 MCode *mxpstart = mxp;
14 if (mxp + (2+2)*EXITSTUBS_PER_GROUP+8+5 >= as->mctop)
15 asm_mclimit(as);
16 /* Push low byte of exitno for each exit stub. */
17 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)groupofs;
18 for (i = 1; i < EXITSTUBS_PER_GROUP; i++) {
19 *mxp++ = XI_JMPs; *mxp++ = (MCode)((2+2)*(EXITSTUBS_PER_GROUP - i) - 2);
20 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)(groupofs + i);
21 }
22 /* Push the high byte of the exitno for each exit stub group. */
23 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)((group*EXITSTUBS_PER_GROUP)>>8);
24#if !LJ_GC64
25 /* Store DISPATCH at original stack slot 0. Account for the two push ops. */
26 *mxp++ = XI_MOVmi;
27 *mxp++ = MODRM(XM_OFS8, 0, RID_ESP);
28 *mxp++ = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
29 *mxp++ = 2*sizeof(void *);
30 *(int32_t *)mxp = ptr2addr(J2GG(as->J)->dispatch); mxp += 4;
31#endif
32 /* Jump to exit handler which fills in the ExitState. */
33 *mxp++ = XI_JMP; mxp += 4;
34 *((int32_t *)(mxp-4)) = jmprel(as->J, mxp, (MCode *)(void *)lj_vm_exit_handler);
35 /* Commit the code for this group (even if assembly fails later on). */
36 lj_mcode_commitbot(as->J, mxp);
37 as->mcbot = mxp;
38 as->mclim = as->mcbot + MCLIM_REDZONE;
39 return mxpstart;
40}
41
42/* Setup all needed exit stubs. */
43static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
44{
45 ExitNo i;
46 if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
47 lj_trace_err(as->J, LJ_TRERR_SNAPOV);
48 for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
49 if (as->J->exitstubgroup[i] == NULL)
50 as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
51}
52
53/* Emit conditional branch to exit for guard.
54** It's important to emit this *after* all registers have been allocated,
55** because rematerializations may invalidate the flags.
56*/
57static void asm_guardcc(ASMState *as, int cc)
58{
59 MCode *target = exitstub_addr(as->J, as->snapno);
60 MCode *p = as->mcp;
61 if (LJ_UNLIKELY(p == as->invmcp)) {
62 as->loopinv = 1;
63 *(int32_t *)(p+1) = jmprel(as->J, p+5, target);
64 target = p;
65 cc ^= 1;
66 if (as->realign) {
67 if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
68 as->mrm.ofs += 2; /* Fixup RIP offset for pending fused load. */
69 emit_sjcc(as, cc, target);
70 return;
71 }
72 }
73 if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
74 as->mrm.ofs += 6; /* Fixup RIP offset for pending fused load. */
75 emit_jcc(as, cc, target);
76}
77
78/* -- Memory operand fusion ----------------------------------------------- */
79
80/* Limit linear search to this distance. Avoids O(n^2) behavior. */
81#define CONFLICT_SEARCH_LIM 31
82
83/* Check if a reference is a signed 32 bit constant. */
84static int asm_isk32(ASMState *as, IRRef ref, int32_t *k)
85{
86 if (irref_isk(ref)) {
87 IRIns *ir = IR(ref);
88#if LJ_GC64
89 if (ir->o == IR_KNULL || !irt_is64(ir->t)) {
90 *k = ir->i;
91 return 1;
92 } else if (checki32((int64_t)ir_k64(ir)->u64)) {
93 *k = (int32_t)ir_k64(ir)->u64;
94 return 1;
95 }
96#else
97 if (ir->o != IR_KINT64) {
98 *k = ir->i;
99 return 1;
100 } else if (checki32((int64_t)ir_kint64(ir)->u64)) {
101 *k = (int32_t)ir_kint64(ir)->u64;
102 return 1;
103 }
104#endif
105 }
106 return 0;
107}
108
109/* Check if there's no conflicting instruction between curins and ref.
110** Also avoid fusing loads if there are multiple references.
111*/
112static int noconflict(ASMState *as, IRRef ref, IROp conflict, int noload)
113{
114 IRIns *ir = as->ir;
115 IRRef i = as->curins;
116 if (i > ref + CONFLICT_SEARCH_LIM)
117 return 0; /* Give up, ref is too far away. */
118 while (--i > ref) {
119 if (ir[i].o == conflict)
120 return 0; /* Conflict found. */
121 else if (!noload && (ir[i].op1 == ref || ir[i].op2 == ref))
122 return 0;
123 }
124 return 1; /* Ok, no conflict. */
125}
126
127/* Fuse array base into memory operand. */
128static IRRef asm_fuseabase(ASMState *as, IRRef ref)
129{
130 IRIns *irb = IR(ref);
131 as->mrm.ofs = 0;
132 if (irb->o == IR_FLOAD) {
133 IRIns *ira = IR(irb->op1);
134 lj_assertA(irb->op2 == IRFL_TAB_ARRAY, "expected FLOAD TAB_ARRAY");
135 /* We can avoid the FLOAD of t->array for colocated arrays. */
136 if (ira->o == IR_TNEW && ira->op1 <= LJ_MAX_COLOSIZE &&
137 !neverfuse(as) && noconflict(as, irb->op1, IR_NEWREF, 1)) {
138 as->mrm.ofs = (int32_t)sizeof(GCtab); /* Ofs to colocated array. */
139 return irb->op1; /* Table obj. */
140 }
141 } else if (irb->o == IR_ADD && irref_isk(irb->op2)) {
142 /* Fuse base offset (vararg load). */
143 as->mrm.ofs = IR(irb->op2)->i;
144 return irb->op1;
145 }
146 return ref; /* Otherwise use the given array base. */
147}
148
149/* Fuse array reference into memory operand. */
150static void asm_fusearef(ASMState *as, IRIns *ir, RegSet allow)
151{
152 IRIns *irx;
153 lj_assertA(ir->o == IR_AREF, "expected AREF");
154 as->mrm.base = (uint8_t)ra_alloc1(as, asm_fuseabase(as, ir->op1), allow);
155 irx = IR(ir->op2);
156 if (irref_isk(ir->op2)) {
157 as->mrm.ofs += 8*irx->i;
158 as->mrm.idx = RID_NONE;
159 } else {
160 rset_clear(allow, as->mrm.base);
161 as->mrm.scale = XM_SCALE8;
162 /* Fuse a constant ADD (e.g. t[i+1]) into the offset.
163 ** Doesn't help much without ABCelim, but reduces register pressure.
164 */
165 if (!LJ_64 && /* Has bad effects with negative index on x64. */
166 mayfuse(as, ir->op2) && ra_noreg(irx->r) &&
167 irx->o == IR_ADD && irref_isk(irx->op2)) {
168 as->mrm.ofs += 8*IR(irx->op2)->i;
169 as->mrm.idx = (uint8_t)ra_alloc1(as, irx->op1, allow);
170 } else {
171 as->mrm.idx = (uint8_t)ra_alloc1(as, ir->op2, allow);
172 }
173 }
174}
175
176/* Fuse array/hash/upvalue reference into memory operand.
177** Caveat: this may allocate GPRs for the base/idx registers. Be sure to
178** pass the final allow mask, excluding any GPRs used for other inputs.
179** In particular: 2-operand GPR instructions need to call ra_dest() first!
180*/
181static void asm_fuseahuref(ASMState *as, IRRef ref, RegSet allow)
182{
183 IRIns *ir = IR(ref);
184 if (ra_noreg(ir->r)) {
185 switch ((IROp)ir->o) {
186 case IR_AREF:
187 if (mayfuse(as, ref)) {
188 asm_fusearef(as, ir, allow);
189 return;
190 }
191 break;
192 case IR_HREFK:
193 if (mayfuse(as, ref)) {
194 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
195 as->mrm.ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
196 as->mrm.idx = RID_NONE;
197 return;
198 }
199 break;
200 case IR_UREFC:
201 if (irref_isk(ir->op1)) {
202 GCfunc *fn = ir_kfunc(IR(ir->op1));
203 GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
204#if LJ_GC64
205 int64_t ofs = dispofs(as, &uv->tv);
206 if (checki32(ofs) && checki32(ofs+4)) {
207 as->mrm.ofs = (int32_t)ofs;
208 as->mrm.base = RID_DISPATCH;
209 as->mrm.idx = RID_NONE;
210 return;
211 }
212#else
213 as->mrm.ofs = ptr2addr(&uv->tv);
214 as->mrm.base = as->mrm.idx = RID_NONE;
215 return;
216#endif
217 }
218 break;
219 default:
220 lj_assertA(ir->o == IR_HREF || ir->o == IR_NEWREF || ir->o == IR_UREFO ||
221 ir->o == IR_KKPTR,
222 "bad IR op %d", ir->o);
223 break;
224 }
225 }
226 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
227 as->mrm.ofs = 0;
228 as->mrm.idx = RID_NONE;
229}
230
231/* Fuse FLOAD/FREF reference into memory operand. */
232static void asm_fusefref(ASMState *as, IRIns *ir, RegSet allow)
233{
234 lj_assertA(ir->o == IR_FLOAD || ir->o == IR_FREF,
235 "bad IR op %d", ir->o);
236 as->mrm.idx = RID_NONE;
237 if (ir->op1 == REF_NIL) { /* FLOAD from GG_State with offset. */
238#if LJ_GC64
239 as->mrm.ofs = (int32_t)(ir->op2 << 2) - GG_OFS(dispatch);
240 as->mrm.base = RID_DISPATCH;
241#else
242 as->mrm.ofs = (int32_t)(ir->op2 << 2) + ptr2addr(J2GG(as->J));
243 as->mrm.base = RID_NONE;
244#endif
245 return;
246 }
247 as->mrm.ofs = field_ofs[ir->op2];
248 if (irref_isk(ir->op1)) {
249 IRIns *op1 = IR(ir->op1);
250#if LJ_GC64
251 if (ir->op1 == REF_NIL) {
252 as->mrm.ofs -= GG_OFS(dispatch);
253 as->mrm.base = RID_DISPATCH;
254 return;
255 } else if (op1->o == IR_KPTR || op1->o == IR_KKPTR) {
256 intptr_t ofs = dispofs(as, ir_kptr(op1));
257 if (checki32(as->mrm.ofs + ofs)) {
258 as->mrm.ofs += (int32_t)ofs;
259 as->mrm.base = RID_DISPATCH;
260 return;
261 }
262 }
263#else
264 as->mrm.ofs += op1->i;
265 as->mrm.base = RID_NONE;
266 return;
267#endif
268 }
269 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
270}
271
272/* Fuse string reference into memory operand. */
273static void asm_fusestrref(ASMState *as, IRIns *ir, RegSet allow)
274{
275 IRIns *irr;
276 lj_assertA(ir->o == IR_STRREF, "bad IR op %d", ir->o);
277 as->mrm.base = as->mrm.idx = RID_NONE;
278 as->mrm.scale = XM_SCALE1;
279 as->mrm.ofs = sizeof(GCstr);
280 if (!LJ_GC64 && irref_isk(ir->op1)) {
281 as->mrm.ofs += IR(ir->op1)->i;
282 } else {
283 Reg r = ra_alloc1(as, ir->op1, allow);
284 rset_clear(allow, r);
285 as->mrm.base = (uint8_t)r;
286 }
287 irr = IR(ir->op2);
288 if (irref_isk(ir->op2)) {
289 as->mrm.ofs += irr->i;
290 } else {
291 Reg r;
292 /* Fuse a constant add into the offset, e.g. string.sub(s, i+10). */
293 if (!LJ_64 && /* Has bad effects with negative index on x64. */
294 mayfuse(as, ir->op2) && irr->o == IR_ADD && irref_isk(irr->op2)) {
295 as->mrm.ofs += IR(irr->op2)->i;
296 r = ra_alloc1(as, irr->op1, allow);
297 } else {
298 r = ra_alloc1(as, ir->op2, allow);
299 }
300 if (as->mrm.base == RID_NONE)
301 as->mrm.base = (uint8_t)r;
302 else
303 as->mrm.idx = (uint8_t)r;
304 }
305}
306
307static void asm_fusexref(ASMState *as, IRRef ref, RegSet allow)
308{
309 IRIns *ir = IR(ref);
310 as->mrm.idx = RID_NONE;
311 if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
312#if LJ_GC64
313 intptr_t ofs = dispofs(as, ir_kptr(ir));
314 if (checki32(ofs)) {
315 as->mrm.ofs = (int32_t)ofs;
316 as->mrm.base = RID_DISPATCH;
317 return;
318 }
319 } if (0) {
320#else
321 as->mrm.ofs = ir->i;
322 as->mrm.base = RID_NONE;
323 } else if (ir->o == IR_STRREF) {
324 asm_fusestrref(as, ir, allow);
325#endif
326 } else {
327 as->mrm.ofs = 0;
328 if (canfuse(as, ir) && ir->o == IR_ADD && ra_noreg(ir->r)) {
329 /* Gather (base+idx*sz)+ofs as emitted by cdata ptr/array indexing. */
330 IRIns *irx;
331 IRRef idx;
332 Reg r;
333 if (asm_isk32(as, ir->op2, &as->mrm.ofs)) { /* Recognize x+ofs. */
334 ref = ir->op1;
335 ir = IR(ref);
336 if (!(ir->o == IR_ADD && canfuse(as, ir) && ra_noreg(ir->r)))
337 goto noadd;
338 }
339 as->mrm.scale = XM_SCALE1;
340 idx = ir->op1;
341 ref = ir->op2;
342 irx = IR(idx);
343 if (!(irx->o == IR_BSHL || irx->o == IR_ADD)) { /* Try other operand. */
344 idx = ir->op2;
345 ref = ir->op1;
346 irx = IR(idx);
347 }
348 if (canfuse(as, irx) && ra_noreg(irx->r)) {
349 if (irx->o == IR_BSHL && irref_isk(irx->op2) && IR(irx->op2)->i <= 3) {
350 /* Recognize idx<<b with b = 0-3, corresponding to sz = (1),2,4,8. */
351 idx = irx->op1;
352 as->mrm.scale = (uint8_t)(IR(irx->op2)->i << 6);
353 } else if (irx->o == IR_ADD && irx->op1 == irx->op2) {
354 /* FOLD does idx*2 ==> idx<<1 ==> idx+idx. */
355 idx = irx->op1;
356 as->mrm.scale = XM_SCALE2;
357 }
358 }
359 r = ra_alloc1(as, idx, allow);
360 rset_clear(allow, r);
361 as->mrm.idx = (uint8_t)r;
362 }
363 noadd:
364 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
365 }
366}
367
368/* Fuse load of 64 bit IR constant into memory operand. */
369static Reg asm_fuseloadk64(ASMState *as, IRIns *ir)
370{
371 const uint64_t *k = &ir_k64(ir)->u64;
372 if (!LJ_GC64 || checki32((intptr_t)k)) {
373 as->mrm.ofs = ptr2addr(k);
374 as->mrm.base = RID_NONE;
375#if LJ_GC64
376 } else if (checki32(dispofs(as, k))) {
377 as->mrm.ofs = (int32_t)dispofs(as, k);
378 as->mrm.base = RID_DISPATCH;
379 } else if (checki32(mcpofs(as, k)) && checki32(mcpofs(as, k+1)) &&
380 checki32(mctopofs(as, k)) && checki32(mctopofs(as, k+1))) {
381 as->mrm.ofs = (int32_t)mcpofs(as, k);
382 as->mrm.base = RID_RIP;
383 } else { /* Intern 64 bit constant at bottom of mcode. */
384 if (ir->i) {
385 lj_assertA(*k == *(uint64_t*)(as->mctop - ir->i),
386 "bad interned 64 bit constant");
387 } else {
388 while ((uintptr_t)as->mcbot & 7) *as->mcbot++ = XI_INT3;
389 *(uint64_t*)as->mcbot = *k;
390 ir->i = (int32_t)(as->mctop - as->mcbot);
391 as->mcbot += 8;
392 as->mclim = as->mcbot + MCLIM_REDZONE;
393 lj_mcode_commitbot(as->J, as->mcbot);
394 }
395 as->mrm.ofs = (int32_t)mcpofs(as, as->mctop - ir->i);
396 as->mrm.base = RID_RIP;
397#endif
398 }
399 as->mrm.idx = RID_NONE;
400 return RID_MRM;
401}
402
403/* Fuse load into memory operand.
404**
405** Important caveat: this may emit RIP-relative loads! So don't place any
406** code emitters between this function and the use of its result.
407** The only permitted exception is asm_guardcc().
408*/
409static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
410{
411 IRIns *ir = IR(ref);
412 if (ra_hasreg(ir->r)) {
413 if (allow != RSET_EMPTY) { /* Fast path. */
414 ra_noweak(as, ir->r);
415 return ir->r;
416 }
417 fusespill:
418 /* Force a spill if only memory operands are allowed (asm_x87load). */
419 as->mrm.base = RID_ESP;
420 as->mrm.ofs = ra_spill(as, ir);
421 as->mrm.idx = RID_NONE;
422 return RID_MRM;
423 }
424 if (ir->o == IR_KNUM) {
425 RegSet avail = as->freeset & ~as->modset & RSET_FPR;
426 lj_assertA(allow != RSET_EMPTY, "no register allowed");
427 if (!(avail & (avail-1))) /* Fuse if less than two regs available. */
428 return asm_fuseloadk64(as, ir);
429 } else if (ref == REF_BASE || ir->o == IR_KINT64) {
430 RegSet avail = as->freeset & ~as->modset & RSET_GPR;
431 lj_assertA(allow != RSET_EMPTY, "no register allowed");
432 if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
433 if (ref == REF_BASE) {
434#if LJ_GC64
435 as->mrm.ofs = (int32_t)dispofs(as, &J2G(as->J)->jit_base);
436 as->mrm.base = RID_DISPATCH;
437#else
438 as->mrm.ofs = ptr2addr(&J2G(as->J)->jit_base);
439 as->mrm.base = RID_NONE;
440#endif
441 as->mrm.idx = RID_NONE;
442 return RID_MRM;
443 } else {
444 return asm_fuseloadk64(as, ir);
445 }
446 }
447 } else if (mayfuse(as, ref)) {
448 RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
449 if (ir->o == IR_SLOAD) {
450 if (!(ir->op2 & (IRSLOAD_PARENT|IRSLOAD_CONVERT)) &&
451 noconflict(as, ref, IR_RETF, 0) &&
452 !(LJ_GC64 && irt_isaddr(ir->t))) {
453 as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
454 as->mrm.ofs = 8*((int32_t)ir->op1-1-LJ_FR2) +
455 (!LJ_FR2 && (ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
456 as->mrm.idx = RID_NONE;
457 return RID_MRM;
458 }
459 } else if (ir->o == IR_FLOAD) {
460 /* Generic fusion is only ok for 32 bit operand (but see asm_comp). */
461 if ((irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t)) &&
462 noconflict(as, ref, IR_FSTORE, 0)) {
463 asm_fusefref(as, ir, xallow);
464 return RID_MRM;
465 }
466 } else if (ir->o == IR_ALOAD || ir->o == IR_HLOAD || ir->o == IR_ULOAD) {
467 if (noconflict(as, ref, ir->o + IRDELTA_L2S, 0) &&
468 !(LJ_GC64 && irt_isaddr(ir->t))) {
469 asm_fuseahuref(as, ir->op1, xallow);
470 return RID_MRM;
471 }
472 } else if (ir->o == IR_XLOAD) {
473 /* Generic fusion is not ok for 8/16 bit operands (but see asm_comp).
474 ** Fusing unaligned memory operands is ok on x86 (except for SIMD types).
475 */
476 if ((!irt_typerange(ir->t, IRT_I8, IRT_U16)) &&
477 noconflict(as, ref, IR_XSTORE, 0)) {
478 asm_fusexref(as, ir->op1, xallow);
479 return RID_MRM;
480 }
481 } else if (ir->o == IR_VLOAD && !(LJ_GC64 && irt_isaddr(ir->t))) {
482 asm_fuseahuref(as, ir->op1, xallow);
483 return RID_MRM;
484 }
485 }
486 if (ir->o == IR_FLOAD && ir->op1 == REF_NIL) {
487 asm_fusefref(as, ir, RSET_EMPTY);
488 return RID_MRM;
489 }
490 if (!(as->freeset & allow) && !emit_canremat(ref) &&
491 (allow == RSET_EMPTY || ra_hasspill(ir->s) || iscrossref(as, ref)))
492 goto fusespill;
493 return ra_allocref(as, ref, allow);
494}
495
496#if LJ_64
497/* Don't fuse a 32 bit load into a 64 bit operation. */
498static Reg asm_fuseloadm(ASMState *as, IRRef ref, RegSet allow, int is64)
499{
500 if (is64 && !irt_is64(IR(ref)->t))
501 return ra_alloc1(as, ref, allow);
502 return asm_fuseload(as, ref, allow);
503}
504#else
505#define asm_fuseloadm(as, ref, allow, is64) asm_fuseload(as, (ref), (allow))
506#endif
507
508/* -- Calls --------------------------------------------------------------- */
509
510/* Count the required number of stack slots for a call. */
511static int asm_count_call_slots(ASMState *as, const CCallInfo *ci, IRRef *args)
512{
513 uint32_t i, nargs = CCI_XNARGS(ci);
514 int nslots = 0;
515#if LJ_64
516 if (LJ_ABI_WIN) {
517 nslots = (int)(nargs*2); /* Only matters for more than four args. */
518 } else {
519 int ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
520 for (i = 0; i < nargs; i++)
521 if (args[i] && irt_isfp(IR(args[i])->t)) {
522 if (nfpr > 0) nfpr--; else nslots += 2;
523 } else {
524 if (ngpr > 0) ngpr--; else nslots += 2;
525 }
526 }
527#else
528 int ngpr = 0;
529 if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
530 ngpr = 2;
531 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
532 ngpr = 1;
533 for (i = 0; i < nargs; i++)
534 if (args[i] && irt_isfp(IR(args[i])->t)) {
535 nslots += irt_isnum(IR(args[i])->t) ? 2 : 1;
536 } else {
537 if (ngpr > 0) ngpr--; else nslots++;
538 }
539#endif
540 return nslots;
541}
542
543/* Generate a call to a C function. */
544static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
545{
546 uint32_t n, nargs = CCI_XNARGS(ci);
547 int32_t ofs = STACKARG_OFS;
548#if LJ_64
549 uint32_t gprs = REGARG_GPRS;
550 Reg fpr = REGARG_FIRSTFPR;
551#if !LJ_ABI_WIN
552 MCode *patchnfpr = NULL;
553#endif
554#else
555 uint32_t gprs = 0;
556 if ((ci->flags & CCI_CC_MASK) != CCI_CC_CDECL) {
557 if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
558 gprs = (REGARG_GPRS & 31);
559 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
560 gprs = REGARG_GPRS;
561 }
562#endif
563 if ((void *)ci->func)
564 emit_call(as, ci->func);
565#if LJ_64
566 if ((ci->flags & CCI_VARARG)) { /* Special handling for vararg calls. */
567#if LJ_ABI_WIN
568 for (n = 0; n < 4 && n < nargs; n++) {
569 IRIns *ir = IR(args[n]);
570 if (irt_isfp(ir->t)) /* Duplicate FPRs in GPRs. */
571 emit_rr(as, XO_MOVDto, (irt_isnum(ir->t) ? REX_64 : 0) | (fpr+n),
572 ((gprs >> (n*5)) & 31)); /* Either MOVD or MOVQ. */
573 }
574#else
575 patchnfpr = --as->mcp; /* Indicate number of used FPRs in register al. */
576 *--as->mcp = XI_MOVrib | RID_EAX;
577#endif
578 }
579#endif
580 for (n = 0; n < nargs; n++) { /* Setup args. */
581 IRRef ref = args[n];
582 IRIns *ir = IR(ref);
583 Reg r;
584#if LJ_64 && LJ_ABI_WIN
585 /* Windows/x64 argument registers are strictly positional. */
586 r = irt_isfp(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
587 fpr++; gprs >>= 5;
588#elif LJ_64
589 /* POSIX/x64 argument registers are used in order of appearance. */
590 if (irt_isfp(ir->t)) {
591 r = fpr <= REGARG_LASTFPR ? fpr++ : 0;
592 } else {
593 r = gprs & 31; gprs >>= 5;
594 }
595#else
596 if (ref && irt_isfp(ir->t)) {
597 r = 0;
598 } else {
599 r = gprs & 31; gprs >>= 5;
600 if (!ref) continue;
601 }
602#endif
603 if (r) { /* Argument is in a register. */
604 if (r < RID_MAX_GPR && ref < ASMREF_TMP1) {
605#if LJ_64
606 if (LJ_GC64 ? !(ir->o == IR_KINT || ir->o == IR_KNULL) : ir->o == IR_KINT64)
607 emit_loadu64(as, r, ir_k64(ir)->u64);
608 else
609#endif
610 emit_loadi(as, r, ir->i);
611 } else {
612 /* Must have been evicted. */
613 lj_assertA(rset_test(as->freeset, r), "reg %d not free", r);
614 if (ra_hasreg(ir->r)) {
615 ra_noweak(as, ir->r);
616 emit_movrr(as, ir, r, ir->r);
617 } else {
618 ra_allocref(as, ref, RID2RSET(r));
619 }
620 }
621 } else if (irt_isfp(ir->t)) { /* FP argument is on stack. */
622 lj_assertA(!(irt_isfloat(ir->t) && irref_isk(ref)),
623 "unexpected float constant");
624 if (LJ_32 && (ofs & 4) && irref_isk(ref)) {
625 /* Split stores for unaligned FP consts. */
626 emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
627 emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
628 } else {
629 r = ra_alloc1(as, ref, RSET_FPR);
630 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto,
631 r, RID_ESP, ofs);
632 }
633 ofs += (LJ_32 && irt_isfloat(ir->t)) ? 4 : 8;
634 } else { /* Non-FP argument is on stack. */
635 if (LJ_32 && ref < ASMREF_TMP1) {
636 emit_movmroi(as, RID_ESP, ofs, ir->i);
637 } else {
638 r = ra_alloc1(as, ref, RSET_GPR);
639 emit_movtomro(as, REX_64 + r, RID_ESP, ofs);
640 }
641 ofs += sizeof(intptr_t);
642 }
643 checkmclim(as);
644 }
645#if LJ_64 && !LJ_ABI_WIN
646 if (patchnfpr) *patchnfpr = fpr - REGARG_FIRSTFPR;
647#endif
648}
649
650/* Setup result reg/sp for call. Evict scratch regs. */
651static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
652{
653 RegSet drop = RSET_SCRATCH;
654 int hiop = (LJ_32 && (ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
655 if ((ci->flags & CCI_NOFPRCLOBBER))
656 drop &= ~RSET_FPR;
657 if (ra_hasreg(ir->r))
658 rset_clear(drop, ir->r); /* Dest reg handled below. */
659 if (hiop && ra_hasreg((ir+1)->r))
660 rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
661 ra_evictset(as, drop); /* Evictions must be performed first. */
662 if (ra_used(ir)) {
663 if (irt_isfp(ir->t)) {
664 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
665#if LJ_64
666 if ((ci->flags & CCI_CASTU64)) {
667 Reg dest = ir->r;
668 if (ra_hasreg(dest)) {
669 ra_free(as, dest);
670 ra_modified(as, dest);
671 emit_rr(as, XO_MOVD, dest|REX_64, RID_RET); /* Really MOVQ. */
672 }
673 if (ofs) emit_movtomro(as, RID_RET|REX_64, RID_ESP, ofs);
674 } else {
675 ra_destreg(as, ir, RID_FPRET);
676 }
677#else
678 /* Number result is in x87 st0 for x86 calling convention. */
679 Reg dest = ir->r;
680 if (ra_hasreg(dest)) {
681 ra_free(as, dest);
682 ra_modified(as, dest);
683 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS,
684 dest, RID_ESP, ofs);
685 }
686 if ((ci->flags & CCI_CASTU64)) {
687 emit_movtomro(as, RID_RETLO, RID_ESP, ofs);
688 emit_movtomro(as, RID_RETHI, RID_ESP, ofs+4);
689 } else {
690 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
691 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
692 }
693#endif
694#if LJ_32
695 } else if (hiop) {
696 ra_destpair(as, ir);
697#endif
698 } else {
699 lj_assertA(!irt_ispri(ir->t), "PRI dest");
700 ra_destreg(as, ir, RID_RET);
701 }
702 } else if (LJ_32 && irt_isfp(ir->t) && !(ci->flags & CCI_CASTU64)) {
703 emit_x87op(as, XI_FPOP); /* Pop unused result from x87 st0. */
704 }
705}
706
707/* Return a constant function pointer or NULL for indirect calls. */
708static void *asm_callx_func(ASMState *as, IRIns *irf, IRRef func)
709{
710#if LJ_32
711 UNUSED(as);
712 if (irref_isk(func))
713 return (void *)irf->i;
714#else
715 if (irref_isk(func)) {
716 MCode *p;
717 if (irf->o == IR_KINT64)
718 p = (MCode *)(void *)ir_k64(irf)->u64;
719 else
720 p = (MCode *)(void *)(uintptr_t)(uint32_t)irf->i;
721 if (p - as->mcp == (int32_t)(p - as->mcp))
722 return p; /* Call target is still in +-2GB range. */
723 /* Avoid the indirect case of emit_call(). Try to hoist func addr. */
724 }
725#endif
726 return NULL;
727}
728
729static void asm_callx(ASMState *as, IRIns *ir)
730{
731 IRRef args[CCI_NARGS_MAX*2];
732 CCallInfo ci;
733 IRRef func;
734 IRIns *irf;
735 int32_t spadj = 0;
736 ci.flags = asm_callx_flags(as, ir);
737 asm_collectargs(as, ir, &ci, args);
738 asm_setupresult(as, ir, &ci);
739#if LJ_32
740 /* Have to readjust stack after non-cdecl calls due to callee cleanup. */
741 if ((ci.flags & CCI_CC_MASK) != CCI_CC_CDECL)
742 spadj = 4 * asm_count_call_slots(as, &ci, args);
743#endif
744 func = ir->op2; irf = IR(func);
745 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
746 ci.func = (ASMFunction)asm_callx_func(as, irf, func);
747 if (!(void *)ci.func) {
748 /* Use a (hoistable) non-scratch register for indirect calls. */
749 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
750 Reg r = ra_alloc1(as, func, allow);
751 if (LJ_32) emit_spsub(as, spadj); /* Above code may cause restores! */
752 emit_rr(as, XO_GROUP5, XOg_CALL, r);
753 } else if (LJ_32) {
754 emit_spsub(as, spadj);
755 }
756 asm_gencall(as, &ci, args);
757}
758
759/* -- Returns ------------------------------------------------------------- */
760
761/* Return to lower frame. Guard that it goes to the right spot. */
762static void asm_retf(ASMState *as, IRIns *ir)
763{
764 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
765#if LJ_FR2
766 Reg rpc = ra_scratch(as, rset_exclude(RSET_GPR, base));
767#endif
768 void *pc = ir_kptr(IR(ir->op2));
769 int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
770 as->topslot -= (BCReg)delta;
771 if ((int32_t)as->topslot < 0) as->topslot = 0;
772 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
773 emit_setgl(as, base, jit_base);
774 emit_addptr(as, base, -8*delta);
775 asm_guardcc(as, CC_NE);
776#if LJ_FR2
777 emit_rmro(as, XO_CMP, rpc|REX_GC64, base, -8);
778 emit_loadu64(as, rpc, u64ptr(pc));
779#else
780 emit_gmroi(as, XG_ARITHi(XOg_CMP), base, -4, ptr2addr(pc));
781#endif
782}
783
784/* -- Type conversions ---------------------------------------------------- */
785
786static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
787{
788 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
789 Reg dest = ra_dest(as, ir, RSET_GPR);
790 asm_guardcc(as, CC_P);
791 asm_guardcc(as, CC_NE);
792 emit_rr(as, XO_UCOMISD, left, tmp);
793 emit_rr(as, XO_CVTSI2SD, tmp, dest);
794 emit_rr(as, XO_XORPS, tmp, tmp); /* Avoid partial register stall. */
795 emit_rr(as, XO_CVTTSD2SI, dest, left);
796 /* Can't fuse since left is needed twice. */
797}
798
799static void asm_tobit(ASMState *as, IRIns *ir)
800{
801 Reg dest = ra_dest(as, ir, RSET_GPR);
802 Reg tmp = ra_noreg(IR(ir->op1)->r) ?
803 ra_alloc1(as, ir->op1, RSET_FPR) :
804 ra_scratch(as, RSET_FPR);
805 Reg right;
806 emit_rr(as, XO_MOVDto, tmp, dest);
807 right = asm_fuseload(as, ir->op2, rset_exclude(RSET_FPR, tmp));
808 emit_mrm(as, XO_ADDSD, tmp, right);
809 ra_left(as, tmp, ir->op1);
810}
811
812static void asm_conv(ASMState *as, IRIns *ir)
813{
814 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
815 int st64 = (st == IRT_I64 || st == IRT_U64 || (LJ_64 && st == IRT_P64));
816 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
817 IRRef lref = ir->op1;
818 lj_assertA(irt_type(ir->t) != st, "inconsistent types for CONV");
819 lj_assertA(!(LJ_32 && (irt_isint64(ir->t) || st64)),
820 "IR %04d has unsplit 64 bit type",
821 (int)(ir - as->ir) - REF_BIAS);
822 if (irt_isfp(ir->t)) {
823 Reg dest = ra_dest(as, ir, RSET_FPR);
824 if (stfp) { /* FP to FP conversion. */
825 Reg left = asm_fuseload(as, lref, RSET_FPR);
826 emit_mrm(as, st == IRT_NUM ? XO_CVTSD2SS : XO_CVTSS2SD, dest, left);
827 if (left == dest) return; /* Avoid the XO_XORPS. */
828 } else if (LJ_32 && st == IRT_U32) { /* U32 to FP conversion on x86. */
829 /* number = (2^52+2^51 .. u32) - (2^52+2^51) */
830 cTValue *k = &as->J->k64[LJ_K64_TOBIT];
831 Reg bias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
832 if (irt_isfloat(ir->t))
833 emit_rr(as, XO_CVTSD2SS, dest, dest);
834 emit_rr(as, XO_SUBSD, dest, bias); /* Subtract 2^52+2^51 bias. */
835 emit_rr(as, XO_XORPS, dest, bias); /* Merge bias and integer. */
836 emit_rma(as, XO_MOVSD, bias, k);
837 emit_mrm(as, XO_MOVD, dest, asm_fuseload(as, lref, RSET_GPR));
838 return;
839 } else { /* Integer to FP conversion. */
840 Reg left = (LJ_64 && (st == IRT_U32 || st == IRT_U64)) ?
841 ra_alloc1(as, lref, RSET_GPR) :
842 asm_fuseloadm(as, lref, RSET_GPR, st64);
843 if (LJ_64 && st == IRT_U64) {
844 MCLabel l_end = emit_label(as);
845 cTValue *k = &as->J->k64[LJ_K64_2P64];
846 emit_rma(as, XO_ADDSD, dest, k); /* Add 2^64 to compensate. */
847 emit_sjcc(as, CC_NS, l_end);
848 emit_rr(as, XO_TEST, left|REX_64, left); /* Check if u64 >= 2^63. */
849 }
850 emit_mrm(as, irt_isnum(ir->t) ? XO_CVTSI2SD : XO_CVTSI2SS,
851 dest|((LJ_64 && (st64 || st == IRT_U32)) ? REX_64 : 0), left);
852 }
853 emit_rr(as, XO_XORPS, dest, dest); /* Avoid partial register stall. */
854 } else if (stfp) { /* FP to integer conversion. */
855 if (irt_isguard(ir->t)) {
856 /* Checked conversions are only supported from number to int. */
857 lj_assertA(irt_isint(ir->t) && st == IRT_NUM,
858 "bad type for checked CONV");
859 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
860 } else {
861 Reg dest = ra_dest(as, ir, RSET_GPR);
862 x86Op op = st == IRT_NUM ? XO_CVTTSD2SI : XO_CVTTSS2SI;
863 if (LJ_64 ? irt_isu64(ir->t) : irt_isu32(ir->t)) {
864 /* LJ_64: For inputs >= 2^63 add -2^64, convert again. */
865 /* LJ_32: For inputs >= 2^31 add -2^31, convert again and add 2^31. */
866 Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
867 ra_scratch(as, RSET_FPR);
868 MCLabel l_end = emit_label(as);
869 if (LJ_32)
870 emit_gri(as, XG_ARITHi(XOg_ADD), dest, (int32_t)0x80000000);
871 emit_rr(as, op, dest|REX_64, tmp);
872 if (st == IRT_NUM)
873 emit_rma(as, XO_ADDSD, tmp, &as->J->k64[LJ_K64_M2P64_31]);
874 else
875 emit_rma(as, XO_ADDSS, tmp, &as->J->k32[LJ_K32_M2P64_31]);
876 emit_sjcc(as, CC_NS, l_end);
877 emit_rr(as, XO_TEST, dest|REX_64, dest); /* Check if dest negative. */
878 emit_rr(as, op, dest|REX_64, tmp);
879 ra_left(as, tmp, lref);
880 } else {
881 if (LJ_64 && irt_isu32(ir->t))
882 emit_rr(as, XO_MOV, dest, dest); /* Zero hiword. */
883 emit_mrm(as, op,
884 dest|((LJ_64 &&
885 (irt_is64(ir->t) || irt_isu32(ir->t))) ? REX_64 : 0),
886 asm_fuseload(as, lref, RSET_FPR));
887 }
888 }
889 } else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
890 Reg left, dest = ra_dest(as, ir, RSET_GPR);
891 RegSet allow = RSET_GPR;
892 x86Op op;
893 lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t), "bad type for CONV EXT");
894 if (st == IRT_I8) {
895 op = XO_MOVSXb; allow = RSET_GPR8; dest |= FORCE_REX;
896 } else if (st == IRT_U8) {
897 op = XO_MOVZXb; allow = RSET_GPR8; dest |= FORCE_REX;
898 } else if (st == IRT_I16) {
899 op = XO_MOVSXw;
900 } else {
901 op = XO_MOVZXw;
902 }
903 left = asm_fuseload(as, lref, allow);
904 /* Add extra MOV if source is already in wrong register. */
905 if (!LJ_64 && left != RID_MRM && !rset_test(allow, left)) {
906 Reg tmp = ra_scratch(as, allow);
907 emit_rr(as, op, dest, tmp);
908 emit_rr(as, XO_MOV, tmp, left);
909 } else {
910 emit_mrm(as, op, dest, left);
911 }
912 } else { /* 32/64 bit integer conversions. */
913 if (LJ_32) { /* Only need to handle 32/32 bit no-op (cast) on x86. */
914 Reg dest = ra_dest(as, ir, RSET_GPR);
915 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
916 } else if (irt_is64(ir->t)) {
917 Reg dest = ra_dest(as, ir, RSET_GPR);
918 if (st64 || !(ir->op2 & IRCONV_SEXT)) {
919 /* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
920 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
921 } else { /* 32 to 64 bit sign extension. */
922 Reg left = asm_fuseload(as, lref, RSET_GPR);
923 emit_mrm(as, XO_MOVSXd, dest|REX_64, left);
924 }
925 } else {
926 Reg dest = ra_dest(as, ir, RSET_GPR);
927 if (st64) {
928 Reg left = asm_fuseload(as, lref, RSET_GPR);
929 /* This is either a 32 bit reg/reg mov which zeroes the hiword
930 ** or a load of the loword from a 64 bit address.
931 */
932 emit_mrm(as, XO_MOV, dest, left);
933 } else { /* 32/32 bit no-op (cast). */
934 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
935 }
936 }
937 }
938}
939
940#if LJ_32 && LJ_HASFFI
941/* No SSE conversions to/from 64 bit on x86, so resort to ugly x87 code. */
942
943/* 64 bit integer to FP conversion in 32 bit mode. */
944static void asm_conv_fp_int64(ASMState *as, IRIns *ir)
945{
946 Reg hi = ra_alloc1(as, ir->op1, RSET_GPR);
947 Reg lo = ra_alloc1(as, (ir-1)->op1, rset_exclude(RSET_GPR, hi));
948 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
949 Reg dest = ir->r;
950 if (ra_hasreg(dest)) {
951 ra_free(as, dest);
952 ra_modified(as, dest);
953 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, dest, RID_ESP, ofs);
954 }
955 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
956 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
957 if (((ir-1)->op2 & IRCONV_SRCMASK) == IRT_U64) {
958 /* For inputs in [2^63,2^64-1] add 2^64 to compensate. */
959 MCLabel l_end = emit_label(as);
960 emit_rma(as, XO_FADDq, XOg_FADDq, &as->J->k64[LJ_K64_2P64]);
961 emit_sjcc(as, CC_NS, l_end);
962 emit_rr(as, XO_TEST, hi, hi); /* Check if u64 >= 2^63. */
963 } else {
964 lj_assertA(((ir-1)->op2 & IRCONV_SRCMASK) == IRT_I64, "bad type for CONV");
965 }
966 emit_rmro(as, XO_FILDq, XOg_FILDq, RID_ESP, 0);
967 /* NYI: Avoid narrow-to-wide store-to-load forwarding stall. */
968 emit_rmro(as, XO_MOVto, hi, RID_ESP, 4);
969 emit_rmro(as, XO_MOVto, lo, RID_ESP, 0);
970}
971
972/* FP to 64 bit integer conversion in 32 bit mode. */
973static void asm_conv_int64_fp(ASMState *as, IRIns *ir)
974{
975 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
976 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
977 Reg lo, hi;
978 lj_assertA(st == IRT_NUM || st == IRT_FLOAT, "bad type for CONV");
979 lj_assertA(dt == IRT_I64 || dt == IRT_U64, "bad type for CONV");
980 hi = ra_dest(as, ir, RSET_GPR);
981 lo = ra_dest(as, ir-1, rset_exclude(RSET_GPR, hi));
982 if (ra_used(ir-1)) emit_rmro(as, XO_MOV, lo, RID_ESP, 0);
983 /* NYI: Avoid wide-to-narrow store-to-load forwarding stall. */
984 if (!(as->flags & JIT_F_SSE3)) { /* Set FPU rounding mode to default. */
985 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 4);
986 emit_rmro(as, XO_MOVto, lo, RID_ESP, 4);
987 emit_gri(as, XG_ARITHi(XOg_AND), lo, 0xf3ff);
988 }
989 if (dt == IRT_U64) {
990 /* For inputs in [2^63,2^64-1] add -2^64 and convert again. */
991 MCLabel l_pop, l_end = emit_label(as);
992 emit_x87op(as, XI_FPOP);
993 l_pop = emit_label(as);
994 emit_sjmp(as, l_end);
995 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
996 if ((as->flags & JIT_F_SSE3))
997 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
998 else
999 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
1000 emit_rma(as, XO_FADDq, XOg_FADDq, &as->J->k64[LJ_K64_M2P64]);
1001 emit_sjcc(as, CC_NS, l_pop);
1002 emit_rr(as, XO_TEST, hi, hi); /* Check if out-of-range (2^63). */
1003 }
1004 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
1005 if ((as->flags & JIT_F_SSE3)) { /* Truncation is easy with SSE3. */
1006 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
1007 } else { /* Otherwise set FPU rounding mode to truncate before the store. */
1008 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
1009 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 0);
1010 emit_rmro(as, XO_MOVtow, lo, RID_ESP, 0);
1011 emit_rmro(as, XO_ARITHw(XOg_OR), lo, RID_ESP, 0);
1012 emit_loadi(as, lo, 0xc00);
1013 emit_rmro(as, XO_FNSTCW, XOg_FNSTCW, RID_ESP, 0);
1014 }
1015 if (dt == IRT_U64)
1016 emit_x87op(as, XI_FDUP);
1017 emit_mrm(as, st == IRT_NUM ? XO_FLDq : XO_FLDd,
1018 st == IRT_NUM ? XOg_FLDq: XOg_FLDd,
1019 asm_fuseload(as, ir->op1, RSET_EMPTY));
1020}
1021
1022static void asm_conv64(ASMState *as, IRIns *ir)
1023{
1024 if (irt_isfp(ir->t))
1025 asm_conv_fp_int64(as, ir);
1026 else
1027 asm_conv_int64_fp(as, ir);
1028}
1029#endif
1030
1031static void asm_strto(ASMState *as, IRIns *ir)
1032{
1033 /* Force a spill slot for the destination register (if any). */
1034 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
1035 IRRef args[2];
1036 RegSet drop = RSET_SCRATCH;
1037 if ((drop & RSET_FPR) != RSET_FPR && ra_hasreg(ir->r))
1038 rset_set(drop, ir->r); /* WIN64 doesn't spill all FPRs. */
1039 ra_evictset(as, drop);
1040 asm_guardcc(as, CC_E);
1041 emit_rr(as, XO_TEST, RID_RET, RID_RET); /* Test return status. */
1042 args[0] = ir->op1; /* GCstr *str */
1043 args[1] = ASMREF_TMP1; /* TValue *n */
1044 asm_gencall(as, ci, args);
1045 /* Store the result to the spill slot or temp slots. */
1046 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)|REX_64,
1047 RID_ESP, sps_scale(ir->s));
1048}
1049
1050/* -- Memory references --------------------------------------------------- */
1051
1052/* Get pointer to TValue. */
1053static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
1054{
1055 IRIns *ir = IR(ref);
1056 if (irt_isnum(ir->t)) {
1057 /* For numbers use the constant itself or a spill slot as a TValue. */
1058 if (irref_isk(ref))
1059 emit_loada(as, dest, ir_knum(ir));
1060 else
1061 emit_rmro(as, XO_LEA, dest|REX_64, RID_ESP, ra_spill(as, ir));
1062 } else {
1063 /* Otherwise use g->tmptv to hold the TValue. */
1064#if LJ_GC64
1065 if (irref_isk(ref)) {
1066 TValue k;
1067 lj_ir_kvalue(as->J->L, &k, ir);
1068 emit_movmroi(as, dest, 4, k.u32.hi);
1069 emit_movmroi(as, dest, 0, k.u32.lo);
1070 } else {
1071 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
1072 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, dest));
1073 if (irt_is64(ir->t)) {
1074 emit_u32(as, irt_toitype(ir->t) << 15);
1075 emit_rmro(as, XO_ARITHi, XOg_OR, dest, 4);
1076 } else {
1077 /* Currently, no caller passes integers that might end up here. */
1078 emit_movmroi(as, dest, 4, (irt_toitype(ir->t) << 15));
1079 }
1080 emit_movtomro(as, REX_64IR(ir, src), dest, 0);
1081 }
1082#else
1083 if (!irref_isk(ref)) {
1084 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, dest));
1085 emit_movtomro(as, REX_64IR(ir, src), dest, 0);
1086 } else if (!irt_ispri(ir->t)) {
1087 emit_movmroi(as, dest, 0, ir->i);
1088 }
1089 if (!(LJ_64 && irt_islightud(ir->t)))
1090 emit_movmroi(as, dest, 4, irt_toitype(ir->t));
1091#endif
1092 emit_loada(as, dest, &J2G(as->J)->tmptv);
1093 }
1094}
1095
1096static void asm_aref(ASMState *as, IRIns *ir)
1097{
1098 Reg dest = ra_dest(as, ir, RSET_GPR);
1099 asm_fusearef(as, ir, RSET_GPR);
1100 if (!(as->mrm.idx == RID_NONE && as->mrm.ofs == 0))
1101 emit_mrm(as, XO_LEA, dest|REX_GC64, RID_MRM);
1102 else if (as->mrm.base != dest)
1103 emit_rr(as, XO_MOV, dest|REX_GC64, as->mrm.base);
1104}
1105
1106/* Inlined hash lookup. Specialized for key type and for const keys.
1107** The equivalent C code is:
1108** Node *n = hashkey(t, key);
1109** do {
1110** if (lj_obj_equal(&n->key, key)) return &n->val;
1111** } while ((n = nextnode(n)));
1112** return niltv(L);
1113*/
1114static void asm_href(ASMState *as, IRIns *ir, IROp merge)
1115{
1116 RegSet allow = RSET_GPR;
1117 int destused = ra_used(ir);
1118 Reg dest = ra_dest(as, ir, allow);
1119 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
1120 Reg key = RID_NONE, tmp = RID_NONE;
1121 IRIns *irkey = IR(ir->op2);
1122 int isk = irref_isk(ir->op2);
1123 IRType1 kt = irkey->t;
1124 uint32_t khash;
1125 MCLabel l_end, l_loop, l_next;
1126
1127 if (!isk) {
1128 rset_clear(allow, tab);
1129 key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
1130 if (LJ_GC64 || !irt_isstr(kt))
1131 tmp = ra_scratch(as, rset_exclude(allow, key));
1132 }
1133
1134 /* Key not found in chain: jump to exit (if merged) or load niltv. */
1135 l_end = emit_label(as);
1136 if (merge == IR_NE)
1137 asm_guardcc(as, CC_E); /* XI_JMP is not found by lj_asm_patchexit. */
1138 else if (destused)
1139 emit_loada(as, dest, niltvg(J2G(as->J)));
1140
1141 /* Follow hash chain until the end. */
1142 l_loop = emit_sjcc_label(as, CC_NZ);
1143 emit_rr(as, XO_TEST, dest|REX_GC64, dest);
1144 emit_rmro(as, XO_MOV, dest|REX_GC64, dest, offsetof(Node, next));
1145 l_next = emit_label(as);
1146
1147 /* Type and value comparison. */
1148 if (merge == IR_EQ)
1149 asm_guardcc(as, CC_E);
1150 else
1151 emit_sjcc(as, CC_E, l_end);
1152 if (irt_isnum(kt)) {
1153 if (isk) {
1154 /* Assumes -0.0 is already canonicalized to +0.0. */
1155 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
1156 (int32_t)ir_knum(irkey)->u32.lo);
1157 emit_sjcc(as, CC_NE, l_next);
1158 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
1159 (int32_t)ir_knum(irkey)->u32.hi);
1160 } else {
1161 emit_sjcc(as, CC_P, l_next);
1162 emit_rmro(as, XO_UCOMISD, key, dest, offsetof(Node, key.n));
1163 emit_sjcc(as, CC_AE, l_next);
1164 /* The type check avoids NaN penalties and complaints from Valgrind. */
1165#if LJ_64 && !LJ_GC64
1166 emit_u32(as, LJ_TISNUM);
1167 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
1168#else
1169 emit_i8(as, LJ_TISNUM);
1170 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
1171#endif
1172 }
1173#if LJ_64 && !LJ_GC64
1174 } else if (irt_islightud(kt)) {
1175 emit_rmro(as, XO_CMP, key|REX_64, dest, offsetof(Node, key.u64));
1176#endif
1177#if LJ_GC64
1178 } else if (irt_isaddr(kt)) {
1179 if (isk) {
1180 TValue k;
1181 k.u64 = ((uint64_t)irt_toitype(irkey->t) << 47) | irkey[1].tv.u64;
1182 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
1183 k.u32.lo);
1184 emit_sjcc(as, CC_NE, l_next);
1185 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
1186 k.u32.hi);
1187 } else {
1188 emit_rmro(as, XO_CMP, tmp|REX_64, dest, offsetof(Node, key.u64));
1189 }
1190 } else {
1191 lj_assertA(irt_ispri(kt) && !irt_isnil(kt), "bad HREF key type");
1192 emit_u32(as, (irt_toitype(kt)<<15)|0x7fff);
1193 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
1194#else
1195 } else {
1196 if (!irt_ispri(kt)) {
1197 lj_assertA(irt_isaddr(kt), "bad HREF key type");
1198 if (isk)
1199 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.gcr),
1200 ptr2addr(ir_kgc(irkey)));
1201 else
1202 emit_rmro(as, XO_CMP, key, dest, offsetof(Node, key.gcr));
1203 emit_sjcc(as, CC_NE, l_next);
1204 }
1205 lj_assertA(!irt_isnil(kt), "bad HREF key type");
1206 emit_i8(as, irt_toitype(kt));
1207 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
1208#endif
1209 }
1210 emit_sfixup(as, l_loop);
1211 checkmclim(as);
1212#if LJ_GC64
1213 if (!isk && irt_isaddr(kt)) {
1214 emit_rr(as, XO_OR, tmp|REX_64, key);
1215 emit_loadu64(as, tmp, (uint64_t)irt_toitype(kt) << 47);
1216 }
1217#endif
1218
1219 /* Load main position relative to tab->node into dest. */
1220 khash = isk ? ir_khash(as, irkey) : 1;
1221 if (khash == 0) {
1222 emit_rmro(as, XO_MOV, dest|REX_GC64, tab, offsetof(GCtab, node));
1223 } else {
1224 emit_rmro(as, XO_ARITH(XOg_ADD), dest|REX_GC64, tab, offsetof(GCtab,node));
1225 emit_shifti(as, XOg_SHL, dest, 3);
1226 emit_rmrxo(as, XO_LEA, dest, dest, dest, XM_SCALE2, 0);
1227 if (isk) {
1228 emit_gri(as, XG_ARITHi(XOg_AND), dest, (int32_t)khash);
1229 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
1230 } else if (irt_isstr(kt)) {
1231 emit_rmro(as, XO_ARITH(XOg_AND), dest, key, offsetof(GCstr, sid));
1232 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
1233 } else { /* Must match with hashrot() in lj_tab.c. */
1234 emit_rmro(as, XO_ARITH(XOg_AND), dest, tab, offsetof(GCtab, hmask));
1235 emit_rr(as, XO_ARITH(XOg_SUB), dest, tmp);
1236 emit_shifti(as, XOg_ROL, tmp, HASH_ROT3);
1237 emit_rr(as, XO_ARITH(XOg_XOR), dest, tmp);
1238 emit_shifti(as, XOg_ROL, dest, HASH_ROT2);
1239 emit_rr(as, XO_ARITH(XOg_SUB), tmp, dest);
1240 emit_shifti(as, XOg_ROL, dest, HASH_ROT1);
1241 emit_rr(as, XO_ARITH(XOg_XOR), tmp, dest);
1242 if (irt_isnum(kt)) {
1243 emit_rr(as, XO_ARITH(XOg_ADD), dest, dest);
1244#if LJ_64
1245 emit_shifti(as, XOg_SHR|REX_64, dest, 32);
1246 emit_rr(as, XO_MOV, tmp, dest);
1247 emit_rr(as, XO_MOVDto, key|REX_64, dest);
1248#else
1249 emit_rmro(as, XO_MOV, dest, RID_ESP, ra_spill(as, irkey)+4);
1250 emit_rr(as, XO_MOVDto, key, tmp);
1251#endif
1252 } else {
1253 emit_rr(as, XO_MOV, tmp, key);
1254#if LJ_GC64
1255 checkmclim(as);
1256 emit_gri(as, XG_ARITHi(XOg_XOR), dest, irt_toitype(kt) << 15);
1257 if ((as->flags & JIT_F_BMI2)) {
1258 emit_i8(as, 32);
1259 emit_mrm(as, XV_RORX|VEX_64, dest, key);
1260 } else {
1261 emit_shifti(as, XOg_SHR|REX_64, dest, 32);
1262 emit_rr(as, XO_MOV, dest|REX_64, key|REX_64);
1263 }
1264#else
1265 emit_rmro(as, XO_LEA, dest, key, HASH_BIAS);
1266#endif
1267 }
1268 }
1269 }
1270}
1271
1272static void asm_hrefk(ASMState *as, IRIns *ir)
1273{
1274 IRIns *kslot = IR(ir->op2);
1275 IRIns *irkey = IR(kslot->op1);
1276 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
1277 Reg dest = ra_used(ir) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
1278 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
1279#if !LJ_64
1280 MCLabel l_exit;
1281#endif
1282 lj_assertA(ofs % sizeof(Node) == 0, "unaligned HREFK slot");
1283 if (ra_hasreg(dest)) {
1284 if (ofs != 0) {
1285 if (dest == node)
1286 emit_gri(as, XG_ARITHi(XOg_ADD), dest|REX_GC64, ofs);
1287 else
1288 emit_rmro(as, XO_LEA, dest|REX_GC64, node, ofs);
1289 } else if (dest != node) {
1290 emit_rr(as, XO_MOV, dest|REX_GC64, node);
1291 }
1292 }
1293 asm_guardcc(as, CC_NE);
1294#if LJ_64
1295 if (!irt_ispri(irkey->t)) {
1296 Reg key = ra_scratch(as, rset_exclude(RSET_GPR, node));
1297 emit_rmro(as, XO_CMP, key|REX_64, node,
1298 ofs + (int32_t)offsetof(Node, key.u64));
1299 lj_assertA(irt_isnum(irkey->t) || irt_isgcv(irkey->t),
1300 "bad HREFK key type");
1301 /* Assumes -0.0 is already canonicalized to +0.0. */
1302 emit_loadu64(as, key, irt_isnum(irkey->t) ? ir_knum(irkey)->u64 :
1303#if LJ_GC64
1304 ((uint64_t)irt_toitype(irkey->t) << 47) |
1305 (uint64_t)ir_kgc(irkey));
1306#else
1307 ((uint64_t)irt_toitype(irkey->t) << 32) |
1308 (uint64_t)(uint32_t)ptr2addr(ir_kgc(irkey)));
1309#endif
1310 } else {
1311 lj_assertA(!irt_isnil(irkey->t), "bad HREFK key type");
1312#if LJ_GC64
1313 emit_i32(as, (irt_toitype(irkey->t)<<15)|0x7fff);
1314 emit_rmro(as, XO_ARITHi, XOg_CMP, node,
1315 ofs + (int32_t)offsetof(Node, key.it));
1316#else
1317 emit_i8(as, irt_toitype(irkey->t));
1318 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1319 ofs + (int32_t)offsetof(Node, key.it));
1320#endif
1321 }
1322#else
1323 l_exit = emit_label(as);
1324 if (irt_isnum(irkey->t)) {
1325 /* Assumes -0.0 is already canonicalized to +0.0. */
1326 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1327 ofs + (int32_t)offsetof(Node, key.u32.lo),
1328 (int32_t)ir_knum(irkey)->u32.lo);
1329 emit_sjcc(as, CC_NE, l_exit);
1330 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1331 ofs + (int32_t)offsetof(Node, key.u32.hi),
1332 (int32_t)ir_knum(irkey)->u32.hi);
1333 } else {
1334 if (!irt_ispri(irkey->t)) {
1335 lj_assertA(irt_isgcv(irkey->t), "bad HREFK key type");
1336 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1337 ofs + (int32_t)offsetof(Node, key.gcr),
1338 ptr2addr(ir_kgc(irkey)));
1339 emit_sjcc(as, CC_NE, l_exit);
1340 }
1341 lj_assertA(!irt_isnil(irkey->t), "bad HREFK key type");
1342 emit_i8(as, irt_toitype(irkey->t));
1343 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1344 ofs + (int32_t)offsetof(Node, key.it));
1345 }
1346#endif
1347}
1348
1349static void asm_uref(ASMState *as, IRIns *ir)
1350{
1351 Reg dest = ra_dest(as, ir, RSET_GPR);
1352 if (irref_isk(ir->op1)) {
1353 GCfunc *fn = ir_kfunc(IR(ir->op1));
1354 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
1355 emit_rma(as, XO_MOV, dest|REX_GC64, v);
1356 } else {
1357 Reg uv = ra_scratch(as, RSET_GPR);
1358 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
1359 if (ir->o == IR_UREFC) {
1360 emit_rmro(as, XO_LEA, dest|REX_GC64, uv, offsetof(GCupval, tv));
1361 asm_guardcc(as, CC_NE);
1362 emit_i8(as, 1);
1363 emit_rmro(as, XO_ARITHib, XOg_CMP, uv, offsetof(GCupval, closed));
1364 } else {
1365 emit_rmro(as, XO_MOV, dest|REX_GC64, uv, offsetof(GCupval, v));
1366 }
1367 emit_rmro(as, XO_MOV, uv|REX_GC64, func,
1368 (int32_t)offsetof(GCfuncL, uvptr) +
1369 (int32_t)sizeof(MRef) * (int32_t)(ir->op2 >> 8));
1370 }
1371}
1372
1373static void asm_fref(ASMState *as, IRIns *ir)
1374{
1375 Reg dest = ra_dest(as, ir, RSET_GPR);
1376 asm_fusefref(as, ir, RSET_GPR);
1377 emit_mrm(as, XO_LEA, dest, RID_MRM);
1378}
1379
1380static void asm_strref(ASMState *as, IRIns *ir)
1381{
1382 Reg dest = ra_dest(as, ir, RSET_GPR);
1383 asm_fusestrref(as, ir, RSET_GPR);
1384 if (as->mrm.base == RID_NONE)
1385 emit_loadi(as, dest, as->mrm.ofs);
1386 else if (as->mrm.base == dest && as->mrm.idx == RID_NONE)
1387 emit_gri(as, XG_ARITHi(XOg_ADD), dest|REX_GC64, as->mrm.ofs);
1388 else
1389 emit_mrm(as, XO_LEA, dest|REX_GC64, RID_MRM);
1390}
1391
1392/* -- Loads and stores ---------------------------------------------------- */
1393
1394static void asm_fxload(ASMState *as, IRIns *ir)
1395{
1396 Reg dest = ra_dest(as, ir, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
1397 x86Op xo;
1398 if (ir->o == IR_FLOAD)
1399 asm_fusefref(as, ir, RSET_GPR);
1400 else
1401 asm_fusexref(as, ir->op1, RSET_GPR);
1402 /* ir->op2 is ignored -- unaligned loads are ok on x86. */
1403 switch (irt_type(ir->t)) {
1404 case IRT_I8: xo = XO_MOVSXb; break;
1405 case IRT_U8: xo = XO_MOVZXb; break;
1406 case IRT_I16: xo = XO_MOVSXw; break;
1407 case IRT_U16: xo = XO_MOVZXw; break;
1408 case IRT_NUM: xo = XO_MOVSD; break;
1409 case IRT_FLOAT: xo = XO_MOVSS; break;
1410 default:
1411 if (LJ_64 && irt_is64(ir->t))
1412 dest |= REX_64;
1413 else
1414 lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t),
1415 "unsplit 64 bit load");
1416 xo = XO_MOV;
1417 break;
1418 }
1419 emit_mrm(as, xo, dest, RID_MRM);
1420}
1421
1422#define asm_fload(as, ir) asm_fxload(as, ir)
1423#define asm_xload(as, ir) asm_fxload(as, ir)
1424
1425static void asm_fxstore(ASMState *as, IRIns *ir)
1426{
1427 RegSet allow = RSET_GPR;
1428 Reg src = RID_NONE, osrc = RID_NONE;
1429 int32_t k = 0;
1430 if (ir->r == RID_SINK)
1431 return;
1432 /* The IRT_I16/IRT_U16 stores should never be simplified for constant
1433 ** values since mov word [mem], imm16 has a length-changing prefix.
1434 */
1435 if (irt_isi16(ir->t) || irt_isu16(ir->t) || irt_isfp(ir->t) ||
1436 !asm_isk32(as, ir->op2, &k)) {
1437 RegSet allow8 = irt_isfp(ir->t) ? RSET_FPR :
1438 (irt_isi8(ir->t) || irt_isu8(ir->t)) ? RSET_GPR8 : RSET_GPR;
1439 src = osrc = ra_alloc1(as, ir->op2, allow8);
1440 if (!LJ_64 && !rset_test(allow8, src)) { /* Already in wrong register. */
1441 rset_clear(allow, osrc);
1442 src = ra_scratch(as, allow8);
1443 }
1444 rset_clear(allow, src);
1445 }
1446 if (ir->o == IR_FSTORE) {
1447 asm_fusefref(as, IR(ir->op1), allow);
1448 } else {
1449 asm_fusexref(as, ir->op1, allow);
1450 if (LJ_32 && ir->o == IR_HIOP) as->mrm.ofs += 4;
1451 }
1452 if (ra_hasreg(src)) {
1453 x86Op xo;
1454 switch (irt_type(ir->t)) {
1455 case IRT_I8: case IRT_U8: xo = XO_MOVtob; src |= FORCE_REX; break;
1456 case IRT_I16: case IRT_U16: xo = XO_MOVtow; break;
1457 case IRT_NUM: xo = XO_MOVSDto; break;
1458 case IRT_FLOAT: xo = XO_MOVSSto; break;
1459#if LJ_64 && !LJ_GC64
1460 case IRT_LIGHTUD:
1461 /* NYI: mask 64 bit lightuserdata. */
1462 lj_assertA(0, "store of lightuserdata");
1463#endif
1464 default:
1465 if (LJ_64 && irt_is64(ir->t))
1466 src |= REX_64;
1467 else
1468 lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t),
1469 "unsplit 64 bit store");
1470 xo = XO_MOVto;
1471 break;
1472 }
1473 emit_mrm(as, xo, src, RID_MRM);
1474 if (!LJ_64 && src != osrc) {
1475 ra_noweak(as, osrc);
1476 emit_rr(as, XO_MOV, src, osrc);
1477 }
1478 } else {
1479 if (irt_isi8(ir->t) || irt_isu8(ir->t)) {
1480 emit_i8(as, k);
1481 emit_mrm(as, XO_MOVmib, 0, RID_MRM);
1482 } else {
1483 lj_assertA(irt_is64(ir->t) || irt_isint(ir->t) || irt_isu32(ir->t) ||
1484 irt_isaddr(ir->t), "bad store type");
1485 emit_i32(as, k);
1486 emit_mrm(as, XO_MOVmi, REX_64IR(ir, 0), RID_MRM);
1487 }
1488 }
1489}
1490
1491#define asm_fstore(as, ir) asm_fxstore(as, ir)
1492#define asm_xstore(as, ir) asm_fxstore(as, ir)
1493
1494#if LJ_64 && !LJ_GC64
1495static Reg asm_load_lightud64(ASMState *as, IRIns *ir, int typecheck)
1496{
1497 if (ra_used(ir) || typecheck) {
1498 Reg dest = ra_dest(as, ir, RSET_GPR);
1499 if (typecheck) {
1500 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, dest));
1501 asm_guardcc(as, CC_NE);
1502 emit_i8(as, -2);
1503 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
1504 emit_shifti(as, XOg_SAR|REX_64, tmp, 47);
1505 emit_rr(as, XO_MOV, tmp|REX_64, dest);
1506 }
1507 return dest;
1508 } else {
1509 return RID_NONE;
1510 }
1511}
1512#endif
1513
1514static void asm_ahuvload(ASMState *as, IRIns *ir)
1515{
1516#if LJ_GC64
1517 Reg tmp = RID_NONE;
1518#endif
1519 lj_assertA(irt_isnum(ir->t) || irt_ispri(ir->t) || irt_isaddr(ir->t) ||
1520 (LJ_DUALNUM && irt_isint(ir->t)),
1521 "bad load type %d", irt_type(ir->t));
1522#if LJ_64 && !LJ_GC64
1523 if (irt_islightud(ir->t)) {
1524 Reg dest = asm_load_lightud64(as, ir, 1);
1525 if (ra_hasreg(dest)) {
1526 asm_fuseahuref(as, ir->op1, RSET_GPR);
1527 emit_mrm(as, XO_MOV, dest|REX_64, RID_MRM);
1528 }
1529 return;
1530 } else
1531#endif
1532 if (ra_used(ir)) {
1533 RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
1534 Reg dest = ra_dest(as, ir, allow);
1535 asm_fuseahuref(as, ir->op1, RSET_GPR);
1536#if LJ_GC64
1537 if (irt_isaddr(ir->t)) {
1538 emit_shifti(as, XOg_SHR|REX_64, dest, 17);
1539 asm_guardcc(as, CC_NE);
1540 emit_i8(as, irt_toitype(ir->t));
1541 emit_rr(as, XO_ARITHi8, XOg_CMP, dest);
1542 emit_i8(as, XI_O16);
1543 if ((as->flags & JIT_F_BMI2)) {
1544 emit_i8(as, 47);
1545 emit_mrm(as, XV_RORX|VEX_64, dest, RID_MRM);
1546 } else {
1547 emit_shifti(as, XOg_ROR|REX_64, dest, 47);
1548 emit_mrm(as, XO_MOV, dest|REX_64, RID_MRM);
1549 }
1550 return;
1551 } else
1552#endif
1553 emit_mrm(as, dest < RID_MAX_GPR ? XO_MOV : XO_MOVSD, dest, RID_MRM);
1554 } else {
1555 RegSet gpr = RSET_GPR;
1556#if LJ_GC64
1557 if (irt_isaddr(ir->t)) {
1558 tmp = ra_scratch(as, RSET_GPR);
1559 gpr = rset_exclude(gpr, tmp);
1560 }
1561#endif
1562 asm_fuseahuref(as, ir->op1, gpr);
1563 }
1564 /* Always do the type check, even if the load result is unused. */
1565 as->mrm.ofs += 4;
1566 asm_guardcc(as, irt_isnum(ir->t) ? CC_AE : CC_NE);
1567 if (LJ_64 && irt_type(ir->t) >= IRT_NUM) {
1568 lj_assertA(irt_isinteger(ir->t) || irt_isnum(ir->t),
1569 "bad load type %d", irt_type(ir->t));
1570#if LJ_GC64
1571 emit_u32(as, LJ_TISNUM << 15);
1572#else
1573 emit_u32(as, LJ_TISNUM);
1574#endif
1575 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
1576#if LJ_GC64
1577 } else if (irt_isaddr(ir->t)) {
1578 as->mrm.ofs -= 4;
1579 emit_i8(as, irt_toitype(ir->t));
1580 emit_mrm(as, XO_ARITHi8, XOg_CMP, tmp);
1581 emit_shifti(as, XOg_SAR|REX_64, tmp, 47);
1582 emit_mrm(as, XO_MOV, tmp|REX_64, RID_MRM);
1583 } else if (irt_isnil(ir->t)) {
1584 as->mrm.ofs -= 4;
1585 emit_i8(as, -1);
1586 emit_mrm(as, XO_ARITHi8, XOg_CMP|REX_64, RID_MRM);
1587 } else {
1588 emit_u32(as, (irt_toitype(ir->t) << 15) | 0x7fff);
1589 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
1590#else
1591 } else {
1592 emit_i8(as, irt_toitype(ir->t));
1593 emit_mrm(as, XO_ARITHi8, XOg_CMP, RID_MRM);
1594#endif
1595 }
1596}
1597
1598static void asm_ahustore(ASMState *as, IRIns *ir)
1599{
1600 if (ir->r == RID_SINK)
1601 return;
1602 if (irt_isnum(ir->t)) {
1603 Reg src = ra_alloc1(as, ir->op2, RSET_FPR);
1604 asm_fuseahuref(as, ir->op1, RSET_GPR);
1605 emit_mrm(as, XO_MOVSDto, src, RID_MRM);
1606#if LJ_64 && !LJ_GC64
1607 } else if (irt_islightud(ir->t)) {
1608 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
1609 asm_fuseahuref(as, ir->op1, rset_exclude(RSET_GPR, src));
1610 emit_mrm(as, XO_MOVto, src|REX_64, RID_MRM);
1611#endif
1612#if LJ_GC64
1613 } else if (irref_isk(ir->op2)) {
1614 TValue k;
1615 lj_ir_kvalue(as->J->L, &k, IR(ir->op2));
1616 asm_fuseahuref(as, ir->op1, RSET_GPR);
1617 if (tvisnil(&k)) {
1618 emit_i32(as, -1);
1619 emit_mrm(as, XO_MOVmi, REX_64, RID_MRM);
1620 } else {
1621 emit_u32(as, k.u32.lo);
1622 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1623 as->mrm.ofs += 4;
1624 emit_u32(as, k.u32.hi);
1625 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1626 }
1627#endif
1628 } else {
1629 IRIns *irr = IR(ir->op2);
1630 RegSet allow = RSET_GPR;
1631 Reg src = RID_NONE;
1632 if (!irref_isk(ir->op2)) {
1633 src = ra_alloc1(as, ir->op2, allow);
1634 rset_clear(allow, src);
1635 }
1636 asm_fuseahuref(as, ir->op1, allow);
1637 if (ra_hasreg(src)) {
1638#if LJ_GC64
1639 if (!(LJ_DUALNUM && irt_isinteger(ir->t))) {
1640 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
1641 as->mrm.ofs += 4;
1642 emit_u32(as, irt_toitype(ir->t) << 15);
1643 emit_mrm(as, XO_ARITHi, XOg_OR, RID_MRM);
1644 as->mrm.ofs -= 4;
1645 emit_mrm(as, XO_MOVto, src|REX_64, RID_MRM);
1646 return;
1647 }
1648#endif
1649 emit_mrm(as, XO_MOVto, src, RID_MRM);
1650 } else if (!irt_ispri(irr->t)) {
1651 lj_assertA(irt_isaddr(ir->t) || (LJ_DUALNUM && irt_isinteger(ir->t)),
1652 "bad store type");
1653 emit_i32(as, irr->i);
1654 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1655 }
1656 as->mrm.ofs += 4;
1657#if LJ_GC64
1658 lj_assertA(LJ_DUALNUM && irt_isinteger(ir->t), "bad store type");
1659 emit_i32(as, LJ_TNUMX << 15);
1660#else
1661 emit_i32(as, (int32_t)irt_toitype(ir->t));
1662#endif
1663 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1664 }
1665}
1666
1667static void asm_sload(ASMState *as, IRIns *ir)
1668{
1669 int32_t ofs = 8*((int32_t)ir->op1-1-LJ_FR2) +
1670 (!LJ_FR2 && (ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
1671 IRType1 t = ir->t;
1672 Reg base;
1673 lj_assertA(!(ir->op2 & IRSLOAD_PARENT),
1674 "bad parent SLOAD"); /* Handled by asm_head_side(). */
1675 lj_assertA(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK),
1676 "inconsistent SLOAD variant");
1677 lj_assertA(LJ_DUALNUM ||
1678 !irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)),
1679 "bad SLOAD type");
1680 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1681 Reg left = ra_scratch(as, RSET_FPR);
1682 asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
1683 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1684 emit_rmro(as, XO_MOVSD, left, base, ofs);
1685 t.irt = IRT_NUM; /* Continue with a regular number type check. */
1686#if LJ_64 && !LJ_GC64
1687 } else if (irt_islightud(t)) {
1688 Reg dest = asm_load_lightud64(as, ir, (ir->op2 & IRSLOAD_TYPECHECK));
1689 if (ra_hasreg(dest)) {
1690 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1691 emit_rmro(as, XO_MOV, dest|REX_64, base, ofs);
1692 }
1693 return;
1694#endif
1695 } else if (ra_used(ir)) {
1696 RegSet allow = irt_isnum(t) ? RSET_FPR : RSET_GPR;
1697 Reg dest = ra_dest(as, ir, allow);
1698 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1699 lj_assertA(irt_isnum(t) || irt_isint(t) || irt_isaddr(t),
1700 "bad SLOAD type %d", irt_type(t));
1701 if ((ir->op2 & IRSLOAD_CONVERT)) {
1702 t.irt = irt_isint(t) ? IRT_NUM : IRT_INT; /* Check for original type. */
1703 emit_rmro(as, irt_isint(t) ? XO_CVTSI2SD : XO_CVTTSD2SI, dest, base, ofs);
1704 } else {
1705#if LJ_GC64
1706 if (irt_isaddr(t)) {
1707 /* LJ_GC64 type check + tag removal without BMI2 and with BMI2:
1708 **
1709 ** mov r64, [addr] rorx r64, [addr], 47
1710 ** ror r64, 47
1711 ** cmp r16, itype cmp r16, itype
1712 ** jne ->exit jne ->exit
1713 ** shr r64, 16 shr r64, 16
1714 */
1715 emit_shifti(as, XOg_SHR|REX_64, dest, 17);
1716 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1717 asm_guardcc(as, CC_NE);
1718 emit_i8(as, irt_toitype(t));
1719 emit_rr(as, XO_ARITHi8, XOg_CMP, dest);
1720 emit_i8(as, XI_O16);
1721 }
1722 if ((as->flags & JIT_F_BMI2)) {
1723 emit_i8(as, 47);
1724 emit_rmro(as, XV_RORX|VEX_64, dest, base, ofs);
1725 } else {
1726 if ((ir->op2 & IRSLOAD_TYPECHECK))
1727 emit_shifti(as, XOg_ROR|REX_64, dest, 47);
1728 else
1729 emit_shifti(as, XOg_SHL|REX_64, dest, 17);
1730 emit_rmro(as, XO_MOV, dest|REX_64, base, ofs);
1731 }
1732 return;
1733 } else
1734#endif
1735 emit_rmro(as, irt_isnum(t) ? XO_MOVSD : XO_MOV, dest, base, ofs);
1736 }
1737 } else {
1738 if (!(ir->op2 & IRSLOAD_TYPECHECK))
1739 return; /* No type check: avoid base alloc. */
1740 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1741 }
1742 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1743 /* Need type check, even if the load result is unused. */
1744 asm_guardcc(as, irt_isnum(t) ? CC_AE : CC_NE);
1745 if (LJ_64 && irt_type(t) >= IRT_NUM) {
1746 lj_assertA(irt_isinteger(t) || irt_isnum(t),
1747 "bad SLOAD type %d", irt_type(t));
1748#if LJ_GC64
1749 emit_u32(as, LJ_TISNUM << 15);
1750#else
1751 emit_u32(as, LJ_TISNUM);
1752#endif
1753 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
1754#if LJ_GC64
1755 } else if (irt_isnil(t)) {
1756 /* LJ_GC64 type check for nil:
1757 **
1758 ** cmp qword [addr], -1
1759 ** jne ->exit
1760 */
1761 emit_i8(as, -1);
1762 emit_rmro(as, XO_ARITHi8, XOg_CMP|REX_64, base, ofs);
1763 } else if (irt_ispri(t)) {
1764 emit_u32(as, (irt_toitype(t) << 15) | 0x7fff);
1765 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
1766 } else {
1767 /* LJ_GC64 type check only:
1768 **
1769 ** mov r64, [addr]
1770 ** sar r64, 47
1771 ** cmp r32, itype
1772 ** jne ->exit
1773 */
1774 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, base));
1775 emit_i8(as, irt_toitype(t));
1776 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
1777 emit_shifti(as, XOg_SAR|REX_64, tmp, 47);
1778 emit_rmro(as, XO_MOV, tmp|REX_64, base, ofs);
1779#else
1780 } else {
1781 emit_i8(as, irt_toitype(t));
1782 emit_rmro(as, XO_ARITHi8, XOg_CMP, base, ofs+4);
1783#endif
1784 }
1785 }
1786}
1787
1788/* -- Allocations --------------------------------------------------------- */
1789
1790#if LJ_HASFFI
1791static void asm_cnew(ASMState *as, IRIns *ir)
1792{
1793 CTState *cts = ctype_ctsG(J2G(as->J));
1794 CTypeID id = (CTypeID)IR(ir->op1)->i;
1795 CTSize sz;
1796 CTInfo info = lj_ctype_info(cts, id, &sz);
1797 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1798 IRRef args[4];
1799 lj_assertA(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL),
1800 "bad CNEW/CNEWI operands");
1801
1802 as->gcsteps++;
1803 asm_setupresult(as, ir, ci); /* GCcdata * */
1804
1805 /* Initialize immutable cdata object. */
1806 if (ir->o == IR_CNEWI) {
1807 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1808#if LJ_64
1809 Reg r64 = sz == 8 ? REX_64 : 0;
1810 if (irref_isk(ir->op2)) {
1811 IRIns *irk = IR(ir->op2);
1812 uint64_t k = (irk->o == IR_KINT64 ||
1813 (LJ_GC64 && (irk->o == IR_KPTR || irk->o == IR_KKPTR))) ?
1814 ir_k64(irk)->u64 : (uint64_t)(uint32_t)irk->i;
1815 if (sz == 4 || checki32((int64_t)k)) {
1816 emit_i32(as, (int32_t)k);
1817 emit_rmro(as, XO_MOVmi, r64, RID_RET, sizeof(GCcdata));
1818 } else {
1819 emit_movtomro(as, RID_ECX + r64, RID_RET, sizeof(GCcdata));
1820 emit_loadu64(as, RID_ECX, k);
1821 }
1822 } else {
1823 Reg r = ra_alloc1(as, ir->op2, allow);
1824 emit_movtomro(as, r + r64, RID_RET, sizeof(GCcdata));
1825 }
1826#else
1827 int32_t ofs = sizeof(GCcdata);
1828 if (sz == 8) {
1829 ofs += 4; ir++;
1830 lj_assertA(ir->o == IR_HIOP, "missing CNEWI HIOP");
1831 }
1832 do {
1833 if (irref_isk(ir->op2)) {
1834 emit_movmroi(as, RID_RET, ofs, IR(ir->op2)->i);
1835 } else {
1836 Reg r = ra_alloc1(as, ir->op2, allow);
1837 emit_movtomro(as, r, RID_RET, ofs);
1838 rset_clear(allow, r);
1839 }
1840 if (ofs == sizeof(GCcdata)) break;
1841 ofs -= 4; ir--;
1842 } while (1);
1843#endif
1844 lj_assertA(sz == 4 || sz == 8, "bad CNEWI size %d", sz);
1845 } else if (ir->op2 != REF_NIL) { /* Create VLA/VLS/aligned cdata. */
1846 ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1847 args[0] = ASMREF_L; /* lua_State *L */
1848 args[1] = ir->op1; /* CTypeID id */
1849 args[2] = ir->op2; /* CTSize sz */
1850 args[3] = ASMREF_TMP1; /* CTSize align */
1851 asm_gencall(as, ci, args);
1852 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1853 return;
1854 }
1855
1856 /* Combine initialization of marked, gct and ctypeid. */
1857 emit_movtomro(as, RID_ECX, RID_RET, offsetof(GCcdata, marked));
1858 emit_gri(as, XG_ARITHi(XOg_OR), RID_ECX,
1859 (int32_t)((~LJ_TCDATA<<8)+(id<<16)));
1860 emit_gri(as, XG_ARITHi(XOg_AND), RID_ECX, LJ_GC_WHITES);
1861 emit_opgl(as, XO_MOVZXb, RID_ECX, gc.currentwhite);
1862
1863 args[0] = ASMREF_L; /* lua_State *L */
1864 args[1] = ASMREF_TMP1; /* MSize size */
1865 asm_gencall(as, ci, args);
1866 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)(sz+sizeof(GCcdata)));
1867}
1868#endif
1869
1870/* -- Write barriers ------------------------------------------------------ */
1871
1872static void asm_tbar(ASMState *as, IRIns *ir)
1873{
1874 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1875 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1876 MCLabel l_end = emit_label(as);
1877 emit_movtomro(as, tmp|REX_GC64, tab, offsetof(GCtab, gclist));
1878 emit_setgl(as, tab, gc.grayagain);
1879 emit_getgl(as, tmp, gc.grayagain);
1880 emit_i8(as, ~LJ_GC_BLACK);
1881 emit_rmro(as, XO_ARITHib, XOg_AND, tab, offsetof(GCtab, marked));
1882 emit_sjcc(as, CC_Z, l_end);
1883 emit_i8(as, LJ_GC_BLACK);
1884 emit_rmro(as, XO_GROUP3b, XOg_TEST, tab, offsetof(GCtab, marked));
1885}
1886
1887static void asm_obar(ASMState *as, IRIns *ir)
1888{
1889 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1890 IRRef args[2];
1891 MCLabel l_end;
1892 Reg obj;
1893 /* No need for other object barriers (yet). */
1894 lj_assertA(IR(ir->op1)->o == IR_UREFC, "bad OBAR type");
1895 ra_evictset(as, RSET_SCRATCH);
1896 l_end = emit_label(as);
1897 args[0] = ASMREF_TMP1; /* global_State *g */
1898 args[1] = ir->op1; /* TValue *tv */
1899 asm_gencall(as, ci, args);
1900 emit_loada(as, ra_releasetmp(as, ASMREF_TMP1), J2G(as->J));
1901 obj = IR(ir->op1)->r;
1902 emit_sjcc(as, CC_Z, l_end);
1903 emit_i8(as, LJ_GC_WHITES);
1904 if (irref_isk(ir->op2)) {
1905 GCobj *vp = ir_kgc(IR(ir->op2));
1906 emit_rma(as, XO_GROUP3b, XOg_TEST, &vp->gch.marked);
1907 } else {
1908 Reg val = ra_alloc1(as, ir->op2, rset_exclude(RSET_SCRATCH&RSET_GPR, obj));
1909 emit_rmro(as, XO_GROUP3b, XOg_TEST, val, (int32_t)offsetof(GChead, marked));
1910 }
1911 emit_sjcc(as, CC_Z, l_end);
1912 emit_i8(as, LJ_GC_BLACK);
1913 emit_rmro(as, XO_GROUP3b, XOg_TEST, obj,
1914 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1915}
1916
1917/* -- FP/int arithmetic and logic operations ------------------------------ */
1918
1919/* Load reference onto x87 stack. Force a spill to memory if needed. */
1920static void asm_x87load(ASMState *as, IRRef ref)
1921{
1922 IRIns *ir = IR(ref);
1923 if (ir->o == IR_KNUM) {
1924 cTValue *tv = ir_knum(ir);
1925 if (tvispzero(tv)) /* Use fldz only for +0. */
1926 emit_x87op(as, XI_FLDZ);
1927 else if (tvispone(tv))
1928 emit_x87op(as, XI_FLD1);
1929 else
1930 emit_rma(as, XO_FLDq, XOg_FLDq, tv);
1931 } else if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT && !ra_used(ir) &&
1932 !irref_isk(ir->op1) && mayfuse(as, ir->op1)) {
1933 IRIns *iri = IR(ir->op1);
1934 emit_rmro(as, XO_FILDd, XOg_FILDd, RID_ESP, ra_spill(as, iri));
1935 } else {
1936 emit_mrm(as, XO_FLDq, XOg_FLDq, asm_fuseload(as, ref, RSET_EMPTY));
1937 }
1938}
1939
1940static void asm_fpmath(ASMState *as, IRIns *ir)
1941{
1942 IRFPMathOp fpm = (IRFPMathOp)ir->op2;
1943 if (fpm == IRFPM_SQRT) {
1944 Reg dest = ra_dest(as, ir, RSET_FPR);
1945 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1946 emit_mrm(as, XO_SQRTSD, dest, left);
1947 } else if (fpm <= IRFPM_TRUNC) {
1948 if (as->flags & JIT_F_SSE4_1) { /* SSE4.1 has a rounding instruction. */
1949 Reg dest = ra_dest(as, ir, RSET_FPR);
1950 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1951 /* ROUNDSD has a 4-byte opcode which doesn't fit in x86Op.
1952 ** Let's pretend it's a 3-byte opcode, and compensate afterwards.
1953 ** This is atrocious, but the alternatives are much worse.
1954 */
1955 /* Round down/up/trunc == 1001/1010/1011. */
1956 emit_i8(as, 0x09 + fpm);
1957 emit_mrm(as, XO_ROUNDSD, dest, left);
1958 if (LJ_64 && as->mcp[1] != (MCode)(XO_ROUNDSD >> 16)) {
1959 as->mcp[0] = as->mcp[1]; as->mcp[1] = 0x0f; /* Swap 0F and REX. */
1960 }
1961 *--as->mcp = 0x66; /* 1st byte of ROUNDSD opcode. */
1962 } else { /* Call helper functions for SSE2 variant. */
1963 /* The modified regs must match with the *.dasc implementation. */
1964 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM3+1)|RID2RSET(RID_EAX);
1965 if (ra_hasreg(ir->r))
1966 rset_clear(drop, ir->r); /* Dest reg handled below. */
1967 ra_evictset(as, drop);
1968 ra_destreg(as, ir, RID_XMM0);
1969 emit_call(as, fpm == IRFPM_FLOOR ? lj_vm_floor_sse :
1970 fpm == IRFPM_CEIL ? lj_vm_ceil_sse : lj_vm_trunc_sse);
1971 ra_left(as, RID_XMM0, ir->op1);
1972 }
1973 } else {
1974 asm_callid(as, ir, IRCALL_lj_vm_floor + fpm);
1975 }
1976}
1977
1978static void asm_ldexp(ASMState *as, IRIns *ir)
1979{
1980 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
1981 Reg dest = ir->r;
1982 if (ra_hasreg(dest)) {
1983 ra_free(as, dest);
1984 ra_modified(as, dest);
1985 emit_rmro(as, XO_MOVSD, dest, RID_ESP, ofs);
1986 }
1987 emit_rmro(as, XO_FSTPq, XOg_FSTPq, RID_ESP, ofs);
1988 emit_x87op(as, XI_FPOP1);
1989 emit_x87op(as, XI_FSCALE);
1990 asm_x87load(as, ir->op1);
1991 asm_x87load(as, ir->op2);
1992}
1993
1994static void asm_fppowi(ASMState *as, IRIns *ir)
1995{
1996 /* The modified regs must match with the *.dasc implementation. */
1997 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM1+1)|RID2RSET(RID_EAX);
1998 if (ra_hasreg(ir->r))
1999 rset_clear(drop, ir->r); /* Dest reg handled below. */
2000 ra_evictset(as, drop);
2001 ra_destreg(as, ir, RID_XMM0);
2002 emit_call(as, lj_vm_powi_sse);
2003 ra_left(as, RID_XMM0, ir->op1);
2004 ra_left(as, RID_EAX, ir->op2);
2005}
2006
2007static int asm_swapops(ASMState *as, IRIns *ir)
2008{
2009 IRIns *irl = IR(ir->op1);
2010 IRIns *irr = IR(ir->op2);
2011 lj_assertA(ra_noreg(irr->r), "bad usage");
2012 if (!irm_iscomm(lj_ir_mode[ir->o]))
2013 return 0; /* Can't swap non-commutative operations. */
2014 if (irref_isk(ir->op2))
2015 return 0; /* Don't swap constants to the left. */
2016 if (ra_hasreg(irl->r))
2017 return 1; /* Swap if left already has a register. */
2018 if (ra_samehint(ir->r, irr->r))
2019 return 1; /* Swap if dest and right have matching hints. */
2020 if (as->curins > as->loopref) { /* In variant part? */
2021 if (ir->op2 < as->loopref && !irt_isphi(irr->t))
2022 return 0; /* Keep invariants on the right. */
2023 if (ir->op1 < as->loopref && !irt_isphi(irl->t))
2024 return 1; /* Swap invariants to the right. */
2025 }
2026 if (opisfusableload(irl->o))
2027 return 1; /* Swap fusable loads to the right. */
2028 return 0; /* Otherwise don't swap. */
2029}
2030
2031static void asm_fparith(ASMState *as, IRIns *ir, x86Op xo)
2032{
2033 IRRef lref = ir->op1;
2034 IRRef rref = ir->op2;
2035 RegSet allow = RSET_FPR;
2036 Reg dest;
2037 Reg right = IR(rref)->r;
2038 if (ra_hasreg(right)) {
2039 rset_clear(allow, right);
2040 ra_noweak(as, right);
2041 }
2042 dest = ra_dest(as, ir, allow);
2043 if (lref == rref) {
2044 right = dest;
2045 } else if (ra_noreg(right)) {
2046 if (asm_swapops(as, ir)) {
2047 IRRef tmp = lref; lref = rref; rref = tmp;
2048 }
2049 right = asm_fuseload(as, rref, rset_clear(allow, dest));
2050 }
2051 emit_mrm(as, xo, dest, right);
2052 ra_left(as, dest, lref);
2053}
2054
2055static void asm_intarith(ASMState *as, IRIns *ir, x86Arith xa)
2056{
2057 IRRef lref = ir->op1;
2058 IRRef rref = ir->op2;
2059 RegSet allow = RSET_GPR;
2060 Reg dest, right;
2061 int32_t k = 0;
2062 if (as->flagmcp == as->mcp) { /* Drop test r,r instruction. */
2063 MCode *p = as->mcp + ((LJ_64 && *as->mcp < XI_TESTb) ? 3 : 2);
2064 MCode *q = p[0] == 0x0f ? p+1 : p;
2065 if ((*q & 15) < 14) {
2066 if ((*q & 15) >= 12) *q -= 4; /* L <->S, NL <-> NS */
2067 as->flagmcp = NULL;
2068 as->mcp = p;
2069 } /* else: cannot transform LE/NLE to cc without use of OF. */
2070 }
2071 right = IR(rref)->r;
2072 if (ra_hasreg(right)) {
2073 rset_clear(allow, right);
2074 ra_noweak(as, right);
2075 }
2076 dest = ra_dest(as, ir, allow);
2077 if (lref == rref) {
2078 right = dest;
2079 } else if (ra_noreg(right) && !asm_isk32(as, rref, &k)) {
2080 if (asm_swapops(as, ir)) {
2081 IRRef tmp = lref; lref = rref; rref = tmp;
2082 }
2083 right = asm_fuseloadm(as, rref, rset_clear(allow, dest), irt_is64(ir->t));
2084 }
2085 if (irt_isguard(ir->t)) /* For IR_ADDOV etc. */
2086 asm_guardcc(as, CC_O);
2087 if (xa != XOg_X_IMUL) {
2088 if (ra_hasreg(right))
2089 emit_mrm(as, XO_ARITH(xa), REX_64IR(ir, dest), right);
2090 else
2091 emit_gri(as, XG_ARITHi(xa), REX_64IR(ir, dest), k);
2092 } else if (ra_hasreg(right)) { /* IMUL r, mrm. */
2093 emit_mrm(as, XO_IMUL, REX_64IR(ir, dest), right);
2094 } else { /* IMUL r, r, k. */
2095 /* NYI: use lea/shl/add/sub (FOLD only does 2^k) depending on CPU. */
2096 Reg left = asm_fuseloadm(as, lref, RSET_GPR, irt_is64(ir->t));
2097 x86Op xo;
2098 if (checki8(k)) { emit_i8(as, k); xo = XO_IMULi8;
2099 } else { emit_i32(as, k); xo = XO_IMULi; }
2100 emit_mrm(as, xo, REX_64IR(ir, dest), left);
2101 return;
2102 }
2103 ra_left(as, dest, lref);
2104}
2105
2106/* LEA is really a 4-operand ADD with an independent destination register,
2107** up to two source registers and an immediate. One register can be scaled
2108** by 1, 2, 4 or 8. This can be used to avoid moves or to fuse several
2109** instructions.
2110**
2111** Currently only a few common cases are supported:
2112** - 3-operand ADD: y = a+b; y = a+k with a and b already allocated
2113** - Left ADD fusion: y = (a+b)+k; y = (a+k)+b
2114** - Right ADD fusion: y = a+(b+k)
2115** The ommited variants have already been reduced by FOLD.
2116**
2117** There are more fusion opportunities, like gathering shifts or joining
2118** common references. But these are probably not worth the trouble, since
2119** array indexing is not decomposed and already makes use of all fields
2120** of the ModRM operand.
2121*/
2122static int asm_lea(ASMState *as, IRIns *ir)
2123{
2124 IRIns *irl = IR(ir->op1);
2125 IRIns *irr = IR(ir->op2);
2126 RegSet allow = RSET_GPR;
2127 Reg dest;
2128 as->mrm.base = as->mrm.idx = RID_NONE;
2129 as->mrm.scale = XM_SCALE1;
2130 as->mrm.ofs = 0;
2131 if (ra_hasreg(irl->r)) {
2132 rset_clear(allow, irl->r);
2133 ra_noweak(as, irl->r);
2134 as->mrm.base = irl->r;
2135 if (irref_isk(ir->op2) || ra_hasreg(irr->r)) {
2136 /* The PHI renaming logic does a better job in some cases. */
2137 if (ra_hasreg(ir->r) &&
2138 ((irt_isphi(irl->t) && as->phireg[ir->r] == ir->op1) ||
2139 (irt_isphi(irr->t) && as->phireg[ir->r] == ir->op2)))
2140 return 0;
2141 if (irref_isk(ir->op2)) {
2142 as->mrm.ofs = irr->i;
2143 } else {
2144 rset_clear(allow, irr->r);
2145 ra_noweak(as, irr->r);
2146 as->mrm.idx = irr->r;
2147 }
2148 } else if (irr->o == IR_ADD && mayfuse(as, ir->op2) &&
2149 irref_isk(irr->op2)) {
2150 Reg idx = ra_alloc1(as, irr->op1, allow);
2151 rset_clear(allow, idx);
2152 as->mrm.idx = (uint8_t)idx;
2153 as->mrm.ofs = IR(irr->op2)->i;
2154 } else {
2155 return 0;
2156 }
2157 } else if (ir->op1 != ir->op2 && irl->o == IR_ADD && mayfuse(as, ir->op1) &&
2158 (irref_isk(ir->op2) || irref_isk(irl->op2))) {
2159 Reg idx, base = ra_alloc1(as, irl->op1, allow);
2160 rset_clear(allow, base);
2161 as->mrm.base = (uint8_t)base;
2162 if (irref_isk(ir->op2)) {
2163 as->mrm.ofs = irr->i;
2164 idx = ra_alloc1(as, irl->op2, allow);
2165 } else {
2166 as->mrm.ofs = IR(irl->op2)->i;
2167 idx = ra_alloc1(as, ir->op2, allow);
2168 }
2169 rset_clear(allow, idx);
2170 as->mrm.idx = (uint8_t)idx;
2171 } else {
2172 return 0;
2173 }
2174 dest = ra_dest(as, ir, allow);
2175 emit_mrm(as, XO_LEA, dest, RID_MRM);
2176 return 1; /* Success. */
2177}
2178
2179static void asm_add(ASMState *as, IRIns *ir)
2180{
2181 if (irt_isnum(ir->t))
2182 asm_fparith(as, ir, XO_ADDSD);
2183 else if (as->flagmcp == as->mcp || irt_is64(ir->t) || !asm_lea(as, ir))
2184 asm_intarith(as, ir, XOg_ADD);
2185}
2186
2187static void asm_sub(ASMState *as, IRIns *ir)
2188{
2189 if (irt_isnum(ir->t))
2190 asm_fparith(as, ir, XO_SUBSD);
2191 else /* Note: no need for LEA trick here. i-k is encoded as i+(-k). */
2192 asm_intarith(as, ir, XOg_SUB);
2193}
2194
2195static void asm_mul(ASMState *as, IRIns *ir)
2196{
2197 if (irt_isnum(ir->t))
2198 asm_fparith(as, ir, XO_MULSD);
2199 else
2200 asm_intarith(as, ir, XOg_X_IMUL);
2201}
2202
2203#define asm_fpdiv(as, ir) asm_fparith(as, ir, XO_DIVSD)
2204
2205static void asm_neg_not(ASMState *as, IRIns *ir, x86Group3 xg)
2206{
2207 Reg dest = ra_dest(as, ir, RSET_GPR);
2208 emit_rr(as, XO_GROUP3, REX_64IR(ir, xg), dest);
2209 ra_left(as, dest, ir->op1);
2210}
2211
2212static void asm_neg(ASMState *as, IRIns *ir)
2213{
2214 if (irt_isnum(ir->t))
2215 asm_fparith(as, ir, XO_XORPS);
2216 else
2217 asm_neg_not(as, ir, XOg_NEG);
2218}
2219
2220#define asm_abs(as, ir) asm_fparith(as, ir, XO_ANDPS)
2221
2222static void asm_intmin_max(ASMState *as, IRIns *ir, int cc)
2223{
2224 Reg right, dest = ra_dest(as, ir, RSET_GPR);
2225 IRRef lref = ir->op1, rref = ir->op2;
2226 if (irref_isk(rref)) { lref = rref; rref = ir->op1; }
2227 right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, dest));
2228 emit_rr(as, XO_CMOV + (cc<<24), REX_64IR(ir, dest), right);
2229 emit_rr(as, XO_CMP, REX_64IR(ir, dest), right);
2230 ra_left(as, dest, lref);
2231}
2232
2233static void asm_min(ASMState *as, IRIns *ir)
2234{
2235 if (irt_isnum(ir->t))
2236 asm_fparith(as, ir, XO_MINSD);
2237 else
2238 asm_intmin_max(as, ir, CC_G);
2239}
2240
2241static void asm_max(ASMState *as, IRIns *ir)
2242{
2243 if (irt_isnum(ir->t))
2244 asm_fparith(as, ir, XO_MAXSD);
2245 else
2246 asm_intmin_max(as, ir, CC_L);
2247}
2248
2249/* Note: don't use LEA for overflow-checking arithmetic! */
2250#define asm_addov(as, ir) asm_intarith(as, ir, XOg_ADD)
2251#define asm_subov(as, ir) asm_intarith(as, ir, XOg_SUB)
2252#define asm_mulov(as, ir) asm_intarith(as, ir, XOg_X_IMUL)
2253
2254#define asm_bnot(as, ir) asm_neg_not(as, ir, XOg_NOT)
2255
2256static void asm_bswap(ASMState *as, IRIns *ir)
2257{
2258 Reg dest = ra_dest(as, ir, RSET_GPR);
2259 as->mcp = emit_op(XO_BSWAP + ((dest&7) << 24),
2260 REX_64IR(ir, 0), dest, 0, as->mcp, 1);
2261 ra_left(as, dest, ir->op1);
2262}
2263
2264#define asm_band(as, ir) asm_intarith(as, ir, XOg_AND)
2265#define asm_bor(as, ir) asm_intarith(as, ir, XOg_OR)
2266#define asm_bxor(as, ir) asm_intarith(as, ir, XOg_XOR)
2267
2268static void asm_bitshift(ASMState *as, IRIns *ir, x86Shift xs, x86Op xv)
2269{
2270 IRRef rref = ir->op2;
2271 IRIns *irr = IR(rref);
2272 Reg dest;
2273 if (irref_isk(rref)) { /* Constant shifts. */
2274 int shift;
2275 dest = ra_dest(as, ir, RSET_GPR);
2276 shift = irr->i & (irt_is64(ir->t) ? 63 : 31);
2277 if (!xv && shift && (as->flags & JIT_F_BMI2)) {
2278 Reg left = asm_fuseloadm(as, ir->op1, RSET_GPR, irt_is64(ir->t));
2279 if (left != dest) { /* BMI2 rotate right by constant. */
2280 emit_i8(as, xs == XOg_ROL ? -shift : shift);
2281 emit_mrm(as, VEX_64IR(ir, XV_RORX), dest, left);
2282 return;
2283 }
2284 }
2285 switch (shift) {
2286 case 0: break;
2287 case 1: emit_rr(as, XO_SHIFT1, REX_64IR(ir, xs), dest); break;
2288 default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break;
2289 }
2290 } else if ((as->flags & JIT_F_BMI2) && xv) { /* BMI2 variable shifts. */
2291 Reg left, right;
2292 dest = ra_dest(as, ir, RSET_GPR);
2293 right = ra_alloc1(as, rref, RSET_GPR);
2294 left = asm_fuseloadm(as, ir->op1, rset_exclude(RSET_GPR, right),
2295 irt_is64(ir->t));
2296 emit_mrm(as, VEX_64IR(ir, xv) ^ (right << 19), dest, left);
2297 return;
2298 } else { /* Variable shifts implicitly use register cl (i.e. ecx). */
2299 Reg right;
2300 dest = ra_dest(as, ir, rset_exclude(RSET_GPR, RID_ECX));
2301 if (dest == RID_ECX) {
2302 dest = ra_scratch(as, rset_exclude(RSET_GPR, RID_ECX));
2303 emit_rr(as, XO_MOV, REX_64IR(ir, RID_ECX), dest);
2304 }
2305 right = irr->r;
2306 if (ra_noreg(right))
2307 right = ra_allocref(as, rref, RID2RSET(RID_ECX));
2308 else if (right != RID_ECX)
2309 ra_scratch(as, RID2RSET(RID_ECX));
2310 emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest);
2311 ra_noweak(as, right);
2312 if (right != RID_ECX)
2313 emit_rr(as, XO_MOV, RID_ECX, right);
2314 }
2315 ra_left(as, dest, ir->op1);
2316 /*
2317 ** Note: avoid using the flags resulting from a shift or rotate!
2318 ** All of them cause a partial flag stall, except for r,1 shifts
2319 ** (but not rotates). And a shift count of 0 leaves the flags unmodified.
2320 */
2321}
2322
2323#define asm_bshl(as, ir) asm_bitshift(as, ir, XOg_SHL, XV_SHLX)
2324#define asm_bshr(as, ir) asm_bitshift(as, ir, XOg_SHR, XV_SHRX)
2325#define asm_bsar(as, ir) asm_bitshift(as, ir, XOg_SAR, XV_SARX)
2326#define asm_brol(as, ir) asm_bitshift(as, ir, XOg_ROL, 0)
2327#define asm_bror(as, ir) asm_bitshift(as, ir, XOg_ROR, 0)
2328
2329/* -- Comparisons --------------------------------------------------------- */
2330
2331/* Virtual flags for unordered FP comparisons. */
2332#define VCC_U 0x1000 /* Unordered. */
2333#define VCC_P 0x2000 /* Needs extra CC_P branch. */
2334#define VCC_S 0x4000 /* Swap avoids CC_P branch. */
2335#define VCC_PS (VCC_P|VCC_S)
2336
2337/* Map of comparisons to flags. ORDER IR. */
2338#define COMPFLAGS(ci, cin, cu, cf) ((ci)+((cu)<<4)+((cin)<<8)+(cf))
2339static const uint16_t asm_compmap[IR_ABC+1] = {
2340 /* signed non-eq unsigned flags */
2341 /* LT */ COMPFLAGS(CC_GE, CC_G, CC_AE, VCC_PS),
2342 /* GE */ COMPFLAGS(CC_L, CC_L, CC_B, 0),
2343 /* LE */ COMPFLAGS(CC_G, CC_G, CC_A, VCC_PS),
2344 /* GT */ COMPFLAGS(CC_LE, CC_L, CC_BE, 0),
2345 /* ULT */ COMPFLAGS(CC_AE, CC_A, CC_AE, VCC_U),
2346 /* UGE */ COMPFLAGS(CC_B, CC_B, CC_B, VCC_U|VCC_PS),
2347 /* ULE */ COMPFLAGS(CC_A, CC_A, CC_A, VCC_U),
2348 /* UGT */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS),
2349 /* EQ */ COMPFLAGS(CC_NE, CC_NE, CC_NE, VCC_P),
2350 /* NE */ COMPFLAGS(CC_E, CC_E, CC_E, VCC_U|VCC_P),
2351 /* ABC */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS) /* Same as UGT. */
2352};
2353
2354/* FP and integer comparisons. */
2355static void asm_comp(ASMState *as, IRIns *ir)
2356{
2357 uint32_t cc = asm_compmap[ir->o];
2358 if (irt_isnum(ir->t)) {
2359 IRRef lref = ir->op1;
2360 IRRef rref = ir->op2;
2361 Reg left, right;
2362 MCLabel l_around;
2363 /*
2364 ** An extra CC_P branch is required to preserve ordered/unordered
2365 ** semantics for FP comparisons. This can be avoided by swapping
2366 ** the operands and inverting the condition (except for EQ and UNE).
2367 ** So always try to swap if possible.
2368 **
2369 ** Another option would be to swap operands to achieve better memory
2370 ** operand fusion. But it's unlikely that this outweighs the cost
2371 ** of the extra branches.
2372 */
2373 if (cc & VCC_S) { /* Swap? */
2374 IRRef tmp = lref; lref = rref; rref = tmp;
2375 cc ^= (VCC_PS|(5<<4)); /* A <-> B, AE <-> BE, PS <-> none */
2376 }
2377 left = ra_alloc1(as, lref, RSET_FPR);
2378 l_around = emit_label(as);
2379 asm_guardcc(as, cc >> 4);
2380 if (cc & VCC_P) { /* Extra CC_P branch required? */
2381 if (!(cc & VCC_U)) {
2382 asm_guardcc(as, CC_P); /* Branch to exit for ordered comparisons. */
2383 } else if (l_around != as->invmcp) {
2384 emit_sjcc(as, CC_P, l_around); /* Branch around for unordered. */
2385 } else {
2386 /* Patched to mcloop by asm_loop_fixup. */
2387 as->loopinv = 2;
2388 if (as->realign)
2389 emit_sjcc(as, CC_P, as->mcp);
2390 else
2391 emit_jcc(as, CC_P, as->mcp);
2392 }
2393 }
2394 right = asm_fuseload(as, rref, rset_exclude(RSET_FPR, left));
2395 emit_mrm(as, XO_UCOMISD, left, right);
2396 } else {
2397 IRRef lref = ir->op1, rref = ir->op2;
2398 IROp leftop = (IROp)(IR(lref)->o);
2399 Reg r64 = REX_64IR(ir, 0);
2400 int32_t imm = 0;
2401 lj_assertA(irt_is64(ir->t) || irt_isint(ir->t) ||
2402 irt_isu32(ir->t) || irt_isaddr(ir->t) || irt_isu8(ir->t),
2403 "bad comparison data type %d", irt_type(ir->t));
2404 /* Swap constants (only for ABC) and fusable loads to the right. */
2405 if (irref_isk(lref) || (!irref_isk(rref) && opisfusableload(leftop))) {
2406 if ((cc & 0xc) == 0xc) cc ^= 0x53; /* L <-> G, LE <-> GE */
2407 else if ((cc & 0xa) == 0x2) cc ^= 0x55; /* A <-> B, AE <-> BE */
2408 lref = ir->op2; rref = ir->op1;
2409 }
2410 if (asm_isk32(as, rref, &imm)) {
2411 IRIns *irl = IR(lref);
2412 /* Check wether we can use test ins. Not for unsigned, since CF=0. */
2413 int usetest = (imm == 0 && (cc & 0xa) != 0x2);
2414 if (usetest && irl->o == IR_BAND && irl+1 == ir && !ra_used(irl)) {
2415 /* Combine comp(BAND(ref, r/imm), 0) into test mrm, r/imm. */
2416 Reg right, left = RID_NONE;
2417 RegSet allow = RSET_GPR;
2418 if (!asm_isk32(as, irl->op2, &imm)) {
2419 left = ra_alloc1(as, irl->op2, allow);
2420 rset_clear(allow, left);
2421 } else { /* Try to Fuse IRT_I8/IRT_U8 loads, too. See below. */
2422 IRIns *irll = IR(irl->op1);
2423 if (opisfusableload((IROp)irll->o) &&
2424 (irt_isi8(irll->t) || irt_isu8(irll->t))) {
2425 IRType1 origt = irll->t; /* Temporarily flip types. */
2426 irll->t.irt = (irll->t.irt & ~IRT_TYPE) | IRT_INT;
2427 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
2428 right = asm_fuseload(as, irl->op1, RSET_GPR);
2429 as->curins++;
2430 irll->t = origt;
2431 if (right != RID_MRM) goto test_nofuse;
2432 /* Fusion succeeded, emit test byte mrm, imm8. */
2433 asm_guardcc(as, cc);
2434 emit_i8(as, (imm & 0xff));
2435 emit_mrm(as, XO_GROUP3b, XOg_TEST, RID_MRM);
2436 return;
2437 }
2438 }
2439 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
2440 right = asm_fuseloadm(as, irl->op1, allow, r64);
2441 as->curins++; /* Undo the above. */
2442 test_nofuse:
2443 asm_guardcc(as, cc);
2444 if (ra_noreg(left)) {
2445 emit_i32(as, imm);
2446 emit_mrm(as, XO_GROUP3, r64 + XOg_TEST, right);
2447 } else {
2448 emit_mrm(as, XO_TEST, r64 + left, right);
2449 }
2450 } else {
2451 Reg left;
2452 if (opisfusableload((IROp)irl->o) &&
2453 ((irt_isu8(irl->t) && checku8(imm)) ||
2454 ((irt_isi8(irl->t) || irt_isi16(irl->t)) && checki8(imm)) ||
2455 (irt_isu16(irl->t) && checku16(imm) && checki8((int16_t)imm)))) {
2456 /* Only the IRT_INT case is fused by asm_fuseload.
2457 ** The IRT_I8/IRT_U8 loads and some IRT_I16/IRT_U16 loads
2458 ** are handled here.
2459 ** Note that cmp word [mem], imm16 should not be generated,
2460 ** since it has a length-changing prefix. Compares of a word
2461 ** against a sign-extended imm8 are ok, however.
2462 */
2463 IRType1 origt = irl->t; /* Temporarily flip types. */
2464 irl->t.irt = (irl->t.irt & ~IRT_TYPE) | IRT_INT;
2465 left = asm_fuseload(as, lref, RSET_GPR);
2466 irl->t = origt;
2467 if (left == RID_MRM) { /* Fusion succeeded? */
2468 if (irt_isu8(irl->t) || irt_isu16(irl->t))
2469 cc >>= 4; /* Need unsigned compare. */
2470 asm_guardcc(as, cc);
2471 emit_i8(as, imm);
2472 emit_mrm(as, (irt_isi8(origt) || irt_isu8(origt)) ?
2473 XO_ARITHib : XO_ARITHiw8, r64 + XOg_CMP, RID_MRM);
2474 return;
2475 } /* Otherwise handle register case as usual. */
2476 } else {
2477 left = asm_fuseloadm(as, lref,
2478 irt_isu8(ir->t) ? RSET_GPR8 : RSET_GPR, r64);
2479 }
2480 asm_guardcc(as, cc);
2481 if (usetest && left != RID_MRM) {
2482 /* Use test r,r instead of cmp r,0. */
2483 x86Op xo = XO_TEST;
2484 if (irt_isu8(ir->t)) {
2485 lj_assertA(ir->o == IR_EQ || ir->o == IR_NE, "bad usage");
2486 xo = XO_TESTb;
2487 if (!rset_test(RSET_RANGE(RID_EAX, RID_EBX+1), left)) {
2488 if (LJ_64) {
2489 left |= FORCE_REX;
2490 } else {
2491 emit_i32(as, 0xff);
2492 emit_mrm(as, XO_GROUP3, XOg_TEST, left);
2493 return;
2494 }
2495 }
2496 }
2497 emit_rr(as, xo, r64 + left, left);
2498 if (irl+1 == ir) /* Referencing previous ins? */
2499 as->flagmcp = as->mcp; /* Set flag to drop test r,r if possible. */
2500 } else {
2501 emit_gmrmi(as, XG_ARITHi(XOg_CMP), r64 + left, imm);
2502 }
2503 }
2504 } else {
2505 Reg left = ra_alloc1(as, lref, RSET_GPR);
2506 Reg right = asm_fuseloadm(as, rref, rset_exclude(RSET_GPR, left), r64);
2507 asm_guardcc(as, cc);
2508 emit_mrm(as, XO_CMP, r64 + left, right);
2509 }
2510 }
2511}
2512
2513#define asm_equal(as, ir) asm_comp(as, ir)
2514
2515#if LJ_32 && LJ_HASFFI
2516/* 64 bit integer comparisons in 32 bit mode. */
2517static void asm_comp_int64(ASMState *as, IRIns *ir)
2518{
2519 uint32_t cc = asm_compmap[(ir-1)->o];
2520 RegSet allow = RSET_GPR;
2521 Reg lefthi = RID_NONE, leftlo = RID_NONE;
2522 Reg righthi = RID_NONE, rightlo = RID_NONE;
2523 MCLabel l_around;
2524 x86ModRM mrm;
2525
2526 as->curins--; /* Skip loword ins. Avoids failing in noconflict(), too. */
2527
2528 /* Allocate/fuse hiword operands. */
2529 if (irref_isk(ir->op2)) {
2530 lefthi = asm_fuseload(as, ir->op1, allow);
2531 } else {
2532 lefthi = ra_alloc1(as, ir->op1, allow);
2533 rset_clear(allow, lefthi);
2534 righthi = asm_fuseload(as, ir->op2, allow);
2535 if (righthi == RID_MRM) {
2536 if (as->mrm.base != RID_NONE) rset_clear(allow, as->mrm.base);
2537 if (as->mrm.idx != RID_NONE) rset_clear(allow, as->mrm.idx);
2538 } else {
2539 rset_clear(allow, righthi);
2540 }
2541 }
2542 mrm = as->mrm; /* Save state for hiword instruction. */
2543
2544 /* Allocate/fuse loword operands. */
2545 if (irref_isk((ir-1)->op2)) {
2546 leftlo = asm_fuseload(as, (ir-1)->op1, allow);
2547 } else {
2548 leftlo = ra_alloc1(as, (ir-1)->op1, allow);
2549 rset_clear(allow, leftlo);
2550 rightlo = asm_fuseload(as, (ir-1)->op2, allow);
2551 }
2552
2553 /* All register allocations must be performed _before_ this point. */
2554 l_around = emit_label(as);
2555 as->invmcp = as->flagmcp = NULL; /* Cannot use these optimizations. */
2556
2557 /* Loword comparison and branch. */
2558 asm_guardcc(as, cc >> 4); /* Always use unsigned compare for loword. */
2559 if (ra_noreg(rightlo)) {
2560 int32_t imm = IR((ir-1)->op2)->i;
2561 if (imm == 0 && ((cc >> 4) & 0xa) != 0x2 && leftlo != RID_MRM)
2562 emit_rr(as, XO_TEST, leftlo, leftlo);
2563 else
2564 emit_gmrmi(as, XG_ARITHi(XOg_CMP), leftlo, imm);
2565 } else {
2566 emit_mrm(as, XO_CMP, leftlo, rightlo);
2567 }
2568
2569 /* Hiword comparison and branches. */
2570 if ((cc & 15) != CC_NE)
2571 emit_sjcc(as, CC_NE, l_around); /* Hiword unequal: skip loword compare. */
2572 if ((cc & 15) != CC_E)
2573 asm_guardcc(as, cc >> 8); /* Hiword compare without equality check. */
2574 as->mrm = mrm; /* Restore state. */
2575 if (ra_noreg(righthi)) {
2576 int32_t imm = IR(ir->op2)->i;
2577 if (imm == 0 && (cc & 0xa) != 0x2 && lefthi != RID_MRM)
2578 emit_rr(as, XO_TEST, lefthi, lefthi);
2579 else
2580 emit_gmrmi(as, XG_ARITHi(XOg_CMP), lefthi, imm);
2581 } else {
2582 emit_mrm(as, XO_CMP, lefthi, righthi);
2583 }
2584}
2585#endif
2586
2587/* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
2588
2589/* Hiword op of a split 64 bit op. Previous op must be the loword op. */
2590static void asm_hiop(ASMState *as, IRIns *ir)
2591{
2592#if LJ_32 && LJ_HASFFI
2593 /* HIOP is marked as a store because it needs its own DCE logic. */
2594 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
2595 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
2596 if ((ir-1)->o == IR_CONV) { /* Conversions to/from 64 bit. */
2597 as->curins--; /* Always skip the CONV. */
2598 if (usehi || uselo)
2599 asm_conv64(as, ir);
2600 return;
2601 } else if ((ir-1)->o <= IR_NE) { /* 64 bit integer comparisons. ORDER IR. */
2602 asm_comp_int64(as, ir);
2603 return;
2604 } else if ((ir-1)->o == IR_XSTORE) {
2605 if ((ir-1)->r != RID_SINK)
2606 asm_fxstore(as, ir);
2607 return;
2608 }
2609 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
2610 switch ((ir-1)->o) {
2611 case IR_ADD:
2612 as->flagmcp = NULL;
2613 as->curins--;
2614 asm_intarith(as, ir, XOg_ADC);
2615 asm_intarith(as, ir-1, XOg_ADD);
2616 break;
2617 case IR_SUB:
2618 as->flagmcp = NULL;
2619 as->curins--;
2620 asm_intarith(as, ir, XOg_SBB);
2621 asm_intarith(as, ir-1, XOg_SUB);
2622 break;
2623 case IR_NEG: {
2624 Reg dest = ra_dest(as, ir, RSET_GPR);
2625 emit_rr(as, XO_GROUP3, XOg_NEG, dest);
2626 emit_i8(as, 0);
2627 emit_rr(as, XO_ARITHi8, XOg_ADC, dest);
2628 ra_left(as, dest, ir->op1);
2629 as->curins--;
2630 asm_neg_not(as, ir-1, XOg_NEG);
2631 break;
2632 }
2633 case IR_CALLN:
2634 case IR_CALLXS:
2635 if (!uselo)
2636 ra_allocref(as, ir->op1, RID2RSET(RID_RETLO)); /* Mark lo op as used. */
2637 break;
2638 case IR_CNEWI:
2639 /* Nothing to do here. Handled by CNEWI itself. */
2640 break;
2641 default: lj_assertA(0, "bad HIOP for op %d", (ir-1)->o); break;
2642 }
2643#else
2644 /* Unused on x64 or without FFI. */
2645 UNUSED(as); UNUSED(ir); lj_assertA(0, "unexpected HIOP");
2646#endif
2647}
2648
2649/* -- Profiling ----------------------------------------------------------- */
2650
2651static void asm_prof(ASMState *as, IRIns *ir)
2652{
2653 UNUSED(ir);
2654 asm_guardcc(as, CC_NE);
2655 emit_i8(as, HOOK_PROFILE);
2656 emit_rma(as, XO_GROUP3b, XOg_TEST, &J2G(as->J)->hookmask);
2657}
2658
2659/* -- Stack handling ------------------------------------------------------ */
2660
2661/* Check Lua stack size for overflow. Use exit handler as fallback. */
2662static void asm_stack_check(ASMState *as, BCReg topslot,
2663 IRIns *irp, RegSet allow, ExitNo exitno)
2664{
2665 /* Try to get an unused temp. register, otherwise spill/restore eax. */
2666 Reg pbase = irp ? irp->r : RID_BASE;
2667 Reg r = allow ? rset_pickbot(allow) : RID_EAX;
2668 emit_jcc(as, CC_B, exitstub_addr(as->J, exitno));
2669 if (allow == RSET_EMPTY) /* Restore temp. register. */
2670 emit_rmro(as, XO_MOV, r|REX_64, RID_ESP, 0);
2671 else
2672 ra_modified(as, r);
2673 emit_gri(as, XG_ARITHi(XOg_CMP), r|REX_GC64, (int32_t)(8*topslot));
2674 if (ra_hasreg(pbase) && pbase != r)
2675 emit_rr(as, XO_ARITH(XOg_SUB), r|REX_GC64, pbase);
2676 else
2677#if LJ_GC64
2678 emit_rmro(as, XO_ARITH(XOg_SUB), r|REX_64, RID_DISPATCH,
2679 (int32_t)dispofs(as, &J2G(as->J)->jit_base));
2680#else
2681 emit_rmro(as, XO_ARITH(XOg_SUB), r, RID_NONE,
2682 ptr2addr(&J2G(as->J)->jit_base));
2683#endif
2684 emit_rmro(as, XO_MOV, r|REX_GC64, r, offsetof(lua_State, maxstack));
2685 emit_getgl(as, r, cur_L);
2686 if (allow == RSET_EMPTY) /* Spill temp. register. */
2687 emit_rmro(as, XO_MOVto, r|REX_64, RID_ESP, 0);
2688}
2689
2690/* Restore Lua stack from on-trace state. */
2691static void asm_stack_restore(ASMState *as, SnapShot *snap)
2692{
2693 SnapEntry *map = &as->T->snapmap[snap->mapofs];
2694#if !LJ_FR2 || defined(LUA_USE_ASSERT)
2695 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1-LJ_FR2];
2696#endif
2697 MSize n, nent = snap->nent;
2698 /* Store the value of all modified slots to the Lua stack. */
2699 for (n = 0; n < nent; n++) {
2700 SnapEntry sn = map[n];
2701 BCReg s = snap_slot(sn);
2702 int32_t ofs = 8*((int32_t)s-1-LJ_FR2);
2703 IRRef ref = snap_ref(sn);
2704 IRIns *ir = IR(ref);
2705 if ((sn & SNAP_NORESTORE))
2706 continue;
2707 if (irt_isnum(ir->t)) {
2708 Reg src = ra_alloc1(as, ref, RSET_FPR);
2709 emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs);
2710 } else {
2711 lj_assertA(irt_ispri(ir->t) || irt_isaddr(ir->t) ||
2712 (LJ_DUALNUM && irt_isinteger(ir->t)),
2713 "restore of IR type %d", irt_type(ir->t));
2714 if (!irref_isk(ref)) {
2715 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
2716#if LJ_GC64
2717 if (irt_is64(ir->t)) {
2718 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
2719 emit_u32(as, irt_toitype(ir->t) << 15);
2720 emit_rmro(as, XO_ARITHi, XOg_OR, RID_BASE, ofs+4);
2721 } else if (LJ_DUALNUM && irt_isinteger(ir->t)) {
2722 emit_movmroi(as, RID_BASE, ofs+4, LJ_TISNUM << 15);
2723 } else {
2724 emit_movmroi(as, RID_BASE, ofs+4, (irt_toitype(ir->t)<<15)|0x7fff);
2725 }
2726#endif
2727 emit_movtomro(as, REX_64IR(ir, src), RID_BASE, ofs);
2728#if LJ_GC64
2729 } else {
2730 TValue k;
2731 lj_ir_kvalue(as->J->L, &k, ir);
2732 if (tvisnil(&k)) {
2733 emit_i32(as, -1);
2734 emit_rmro(as, XO_MOVmi, REX_64, RID_BASE, ofs);
2735 } else {
2736 emit_movmroi(as, RID_BASE, ofs+4, k.u32.hi);
2737 emit_movmroi(as, RID_BASE, ofs, k.u32.lo);
2738 }
2739#else
2740 } else if (!irt_ispri(ir->t)) {
2741 emit_movmroi(as, RID_BASE, ofs, ir->i);
2742#endif
2743 }
2744 if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2745#if !LJ_FR2
2746 if (s != 0) /* Do not overwrite link to previous frame. */
2747 emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*flinks--));
2748#endif
2749#if !LJ_GC64
2750 } else {
2751 if (!(LJ_64 && irt_islightud(ir->t)))
2752 emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t));
2753#endif
2754 }
2755 }
2756 checkmclim(as);
2757 }
2758 lj_assertA(map + nent == flinks, "inconsistent frames in snapshot");
2759}
2760
2761/* -- GC handling --------------------------------------------------------- */
2762
2763/* Check GC threshold and do one or more GC steps. */
2764static void asm_gc_check(ASMState *as)
2765{
2766 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2767 IRRef args[2];
2768 MCLabel l_end;
2769 Reg tmp;
2770 ra_evictset(as, RSET_SCRATCH);
2771 l_end = emit_label(as);
2772 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2773 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
2774 emit_rr(as, XO_TEST, RID_RET, RID_RET);
2775 args[0] = ASMREF_TMP1; /* global_State *g */
2776 args[1] = ASMREF_TMP2; /* MSize steps */
2777 asm_gencall(as, ci, args);
2778 tmp = ra_releasetmp(as, ASMREF_TMP1);
2779#if LJ_GC64
2780 emit_rmro(as, XO_LEA, tmp|REX_64, RID_DISPATCH, GG_DISP2G);
2781#else
2782 emit_loada(as, tmp, J2G(as->J));
2783#endif
2784 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP2), as->gcsteps);
2785 /* Jump around GC step if GC total < GC threshold. */
2786 emit_sjcc(as, CC_B, l_end);
2787 emit_opgl(as, XO_ARITH(XOg_CMP), tmp|REX_GC64, gc.threshold);
2788 emit_getgl(as, tmp, gc.total);
2789 as->gcsteps = 0;
2790 checkmclim(as);
2791}
2792
2793/* -- Loop handling ------------------------------------------------------- */
2794
2795/* Fixup the loop branch. */
2796static void asm_loop_fixup(ASMState *as)
2797{
2798 MCode *p = as->mctop;
2799 MCode *target = as->mcp;
2800 if (as->realign) { /* Realigned loops use short jumps. */
2801 as->realign = NULL; /* Stop another retry. */
2802 lj_assertA(((intptr_t)target & 15) == 0, "loop realign failed");
2803 if (as->loopinv) { /* Inverted loop branch? */
2804 p -= 5;
2805 p[0] = XI_JMP;
2806 lj_assertA(target - p >= -128, "loop realign failed");
2807 p[-1] = (MCode)(target - p); /* Patch sjcc. */
2808 if (as->loopinv == 2)
2809 p[-3] = (MCode)(target - p + 2); /* Patch opt. short jp. */
2810 } else {
2811 lj_assertA(target - p >= -128, "loop realign failed");
2812 p[-1] = (MCode)(int8_t)(target - p); /* Patch short jmp. */
2813 p[-2] = XI_JMPs;
2814 }
2815 } else {
2816 MCode *newloop;
2817 p[-5] = XI_JMP;
2818 if (as->loopinv) { /* Inverted loop branch? */
2819 /* asm_guardcc already inverted the jcc and patched the jmp. */
2820 p -= 5;
2821 newloop = target+4;
2822 *(int32_t *)(p-4) = (int32_t)(target - p); /* Patch jcc. */
2823 if (as->loopinv == 2) {
2824 *(int32_t *)(p-10) = (int32_t)(target - p + 6); /* Patch opt. jp. */
2825 newloop = target+8;
2826 }
2827 } else { /* Otherwise just patch jmp. */
2828 *(int32_t *)(p-4) = (int32_t)(target - p);
2829 newloop = target+3;
2830 }
2831 /* Realign small loops and shorten the loop branch. */
2832 if (newloop >= p - 128) {
2833 as->realign = newloop; /* Force a retry and remember alignment. */
2834 as->curins = as->stopins; /* Abort asm_trace now. */
2835 as->T->nins = as->orignins; /* Remove any added renames. */
2836 }
2837 }
2838}
2839
2840/* -- Head of trace ------------------------------------------------------- */
2841
2842/* Coalesce BASE register for a root trace. */
2843static void asm_head_root_base(ASMState *as)
2844{
2845 IRIns *ir = IR(REF_BASE);
2846 Reg r = ir->r;
2847 if (ra_hasreg(r)) {
2848 ra_free(as, r);
2849 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2850 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2851 if (r != RID_BASE)
2852 emit_rr(as, XO_MOV, r|REX_GC64, RID_BASE);
2853 }
2854}
2855
2856/* Coalesce or reload BASE register for a side trace. */
2857static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
2858{
2859 IRIns *ir = IR(REF_BASE);
2860 Reg r = ir->r;
2861 if (ra_hasreg(r)) {
2862 ra_free(as, r);
2863 if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2864 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2865 if (irp->r == r) {
2866 rset_clear(allow, r); /* Mark same BASE register as coalesced. */
2867 } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
2868 /* Move from coalesced parent reg. */
2869 rset_clear(allow, irp->r);
2870 emit_rr(as, XO_MOV, r|REX_GC64, irp->r);
2871 } else {
2872 emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
2873 }
2874 }
2875 return allow;
2876}
2877
2878/* -- Tail of trace ------------------------------------------------------- */
2879
2880/* Fixup the tail code. */
2881static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2882{
2883 /* Note: don't use as->mcp swap + emit_*: emit_op overwrites more bytes. */
2884 MCode *p = as->mctop;
2885 MCode *target, *q;
2886 int32_t spadj = as->T->spadjust;
2887 if (spadj == 0) {
2888 p -= LJ_64 ? 7 : 6;
2889 } else {
2890 MCode *p1;
2891 /* Patch stack adjustment. */
2892 if (checki8(spadj)) {
2893 p -= 3;
2894 p1 = p-6;
2895 *p1 = (MCode)spadj;
2896 } else {
2897 p1 = p-9;
2898 *(int32_t *)p1 = spadj;
2899 }
2900#if LJ_64
2901 p1[-3] = 0x48;
2902#endif
2903 p1[-2] = (MCode)(checki8(spadj) ? XI_ARITHi8 : XI_ARITHi);
2904 p1[-1] = MODRM(XM_REG, XOg_ADD, RID_ESP);
2905 }
2906 /* Patch exit branch. */
2907 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
2908 *(int32_t *)(p-4) = jmprel(as->J, p, target);
2909 p[-5] = XI_JMP;
2910 /* Drop unused mcode tail. Fill with NOPs to make the prefetcher happy. */
2911 for (q = as->mctop-1; q >= p; q--)
2912 *q = XI_NOP;
2913 as->mctop = p;
2914}
2915
2916/* Prepare tail of code. */
2917static void asm_tail_prep(ASMState *as)
2918{
2919 MCode *p = as->mctop;
2920 /* Realign and leave room for backwards loop branch or exit branch. */
2921 if (as->realign) {
2922 int i = ((int)(intptr_t)as->realign) & 15;
2923 /* Fill unused mcode tail with NOPs to make the prefetcher happy. */
2924 while (i-- > 0)
2925 *--p = XI_NOP;
2926 as->mctop = p;
2927 p -= (as->loopinv ? 5 : 2); /* Space for short/near jmp. */
2928 } else {
2929 p -= 5; /* Space for exit branch (near jmp). */
2930 }
2931 if (as->loopref) {
2932 as->invmcp = as->mcp = p;
2933 } else {
2934 /* Leave room for ESP adjustment: add esp, imm or lea esp, [esp+imm] */
2935 as->mcp = p - (LJ_64 ? 7 : 6);
2936 as->invmcp = NULL;
2937 }
2938}
2939
2940/* -- Trace setup --------------------------------------------------------- */
2941
2942/* Ensure there are enough stack slots for call arguments. */
2943static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2944{
2945 IRRef args[CCI_NARGS_MAX*2];
2946 int nslots;
2947 asm_collectargs(as, ir, ci, args);
2948 nslots = asm_count_call_slots(as, ci, args);
2949 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
2950 as->evenspill = nslots;
2951#if LJ_64
2952 return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
2953#else
2954 return irt_isfp(ir->t) ? REGSP_INIT : REGSP_HINT(RID_RET);
2955#endif
2956}
2957
2958/* Target-specific setup. */
2959static void asm_setup_target(ASMState *as)
2960{
2961 asm_exitstub_setup(as, as->T->nsnap);
2962 as->mrm.base = 0;
2963}
2964
2965/* -- Trace patching ------------------------------------------------------ */
2966
2967static const uint8_t map_op1[256] = {
29680x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x20,
29690x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,
29700x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
29710x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
2972#if LJ_64
29730x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,
2974#else
29750x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
2976#endif
29770x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
29780x51,0x51,0x92,0x92,0x10,0x10,0x12,0x11,0x45,0x86,0x52,0x93,0x51,0x51,0x51,0x51,
29790x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
29800x93,0x86,0x93,0x93,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
29810x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x47,0x51,0x51,0x51,0x51,0x51,
2982#if LJ_64
29830x59,0x59,0x59,0x59,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
2984#else
29850x55,0x55,0x55,0x55,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
2986#endif
29870x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,
29880x93,0x93,0x53,0x51,0x70,0x71,0x93,0x86,0x54,0x51,0x53,0x51,0x51,0x52,0x51,0x51,
29890x92,0x92,0x92,0x92,0x52,0x52,0x51,0x51,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
29900x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x45,0x45,0x47,0x52,0x51,0x51,0x51,0x51,
29910x10,0x51,0x10,0x10,0x51,0x51,0x63,0x66,0x51,0x51,0x51,0x51,0x51,0x51,0x92,0x92
2992};
2993
2994static const uint8_t map_op2[256] = {
29950x93,0x93,0x93,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x51,0x52,0x51,0x93,0x52,0x94,
29960x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
29970x53,0x53,0x53,0x53,0x53,0x53,0x53,0x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
29980x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x34,0x51,0x35,0x51,0x51,0x51,0x51,0x51,
29990x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30000x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30010x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30020x94,0x54,0x54,0x54,0x93,0x93,0x93,0x52,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30030x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,
30040x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30050x52,0x52,0x52,0x93,0x94,0x93,0x51,0x51,0x52,0x52,0x52,0x93,0x94,0x93,0x93,0x93,
30060x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x94,0x93,0x93,0x93,0x93,0x93,
30070x93,0x93,0x94,0x93,0x94,0x94,0x94,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
30080x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30090x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
30100x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x52
3011};
3012
3013static uint32_t asm_x86_inslen(const uint8_t* p)
3014{
3015 uint32_t result = 0;
3016 uint32_t prefixes = 0;
3017 uint32_t x = map_op1[*p];
3018 for (;;) {
3019 switch (x >> 4) {
3020 case 0: return result + x + (prefixes & 4);
3021 case 1: prefixes |= x; x = map_op1[*++p]; result++; break;
3022 case 2: x = map_op2[*++p]; break;
3023 case 3: p++; goto mrm;
3024 case 4: result -= (prefixes & 2); /* fallthrough */
3025 case 5: return result + (x & 15);
3026 case 6: /* Group 3. */
3027 if (p[1] & 0x38) x = 2;
3028 else if ((prefixes & 2) && (x == 0x66)) x = 4;
3029 goto mrm;
3030 case 7: /* VEX c4/c5. */
3031 if (LJ_32 && p[1] < 0xc0) {
3032 x = 2;
3033 goto mrm;
3034 }
3035 if (x == 0x70) {
3036 x = *++p & 0x1f;
3037 result++;
3038 if (x >= 2) {
3039 p += 2;
3040 result += 2;
3041 goto mrm;
3042 }
3043 }
3044 p++;
3045 result++;
3046 x = map_op2[*++p];
3047 break;
3048 case 8: result -= (prefixes & 2); /* fallthrough */
3049 case 9: mrm: /* ModR/M and possibly SIB. */
3050 result += (x & 15);
3051 x = *++p;
3052 switch (x >> 6) {
3053 case 0: if ((x & 7) == 5) return result + 4; break;
3054 case 1: result++; break;
3055 case 2: result += 4; break;
3056 case 3: return result;
3057 }
3058 if ((x & 7) == 4) {
3059 result++;
3060 if (x < 0x40 && (p[1] & 7) == 5) result += 4;
3061 }
3062 return result;
3063 }
3064 }
3065}
3066
3067/* Patch exit jumps of existing machine code to a new target. */
3068void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
3069{
3070 MCode *p = T->mcode;
3071 MCode *mcarea = lj_mcode_patch(J, p, 0);
3072 MSize len = T->szmcode;
3073 MCode *px = exitstub_addr(J, exitno) - 6;
3074 MCode *pe = p+len-6;
3075 MCode *pgc = NULL;
3076#if LJ_GC64
3077 uint32_t statei = (uint32_t)(GG_OFS(g.vmstate) - GG_OFS(dispatch));
3078#else
3079 uint32_t statei = u32ptr(&J2G(J)->vmstate);
3080#endif
3081 if (len > 5 && p[len-5] == XI_JMP && p+len-6 + *(int32_t *)(p+len-4) == px)
3082 *(int32_t *)(p+len-4) = jmprel(J, p+len, target);
3083 /* Do not patch parent exit for a stack check. Skip beyond vmstate update. */
3084 for (; p < pe; p += asm_x86_inslen(p)) {
3085 intptr_t ofs = LJ_GC64 ? (p[0] & 0xf0) == 0x40 : LJ_64;
3086 if (*(uint32_t *)(p+2+ofs) == statei && p[ofs+LJ_GC64-LJ_64] == XI_MOVmi)
3087 break;
3088 }
3089 lj_assertJ(p < pe, "instruction length decoder failed");
3090 for (; p < pe; p += asm_x86_inslen(p)) {
3091 if ((*(uint16_t *)p & 0xf0ff) == 0x800f && p + *(int32_t *)(p+2) == px &&
3092 p != pgc) {
3093 *(int32_t *)(p+2) = jmprel(J, p+6, target);
3094 } else if (*p == XI_CALL &&
3095 (void *)(p+5+*(int32_t *)(p+1)) == (void *)lj_gc_step_jit) {
3096 pgc = p+7; /* Do not patch GC check exit. */
3097 }
3098 }
3099 lj_mcode_sync(T->mcode, T->mcode + T->szmcode);
3100 lj_mcode_patch(J, mcarea, 1);
3101}
3102
3103