1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - rsp_core.h *
3 * Mupen64Plus homepage: https://mupen64plus.org/ *
4 * Copyright (C) 2014 Bobby Smiles *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21
22#ifndef M64P_DEVICE_RCP_RSP_RSP_CORE_H
23#define M64P_DEVICE_RCP_RSP_RSP_CORE_H
24
25#include <stdint.h>
26
27#include "osal/preproc.h"
28
29struct mi_controller;
30struct rdp_core;
31struct ri_controller;
32
33enum { SP_MEM_SIZE = 0x2000 };
34
35enum
36{
37 /* SP_STATUS - read */
38 SP_STATUS_HALT = 0x0001,
39 SP_STATUS_BROKE = 0x0002,
40 SP_STATUS_DMA_BUSY = 0x0004,
41 SP_STATUS_DMA_FULL = 0x0008,
42 SP_STATUS_IO_FULL = 0x0010,
43 SP_STATUS_SSTEP = 0x0020,
44 SP_STATUS_INTR_BREAK = 0x0040,
45 SP_STATUS_SIG0 = 0x0080,
46 SP_STATUS_YIELD = 0x0080,
47 SP_STATUS_SIG1 = 0x0100,
48 SP_STATUS_YIELDED = 0x0100,
49 SP_STATUS_SIG2 = 0x0200,
50 SP_STATUS_TASKDONE = 0x0200,
51 SP_STATUS_SIG3 = 0x0400,
52 SP_STATUS_SIG4 = 0x0800,
53 SP_STATUS_SIG5 = 0x1000,
54 SP_STATUS_SIG6 = 0x2000,
55 SP_STATUS_SIG7 = 0x4000,
56};
57
58enum sp_registers
59{
60 SP_MEM_ADDR_REG,
61 SP_DRAM_ADDR_REG,
62 SP_RD_LEN_REG,
63 SP_WR_LEN_REG,
64 SP_STATUS_REG,
65 SP_DMA_FULL_REG,
66 SP_DMA_BUSY_REG,
67 SP_SEMAPHORE_REG,
68 SP_REGS_COUNT
69};
70
71enum sp_registers2
72{
73 SP_PC_REG,
74 SP_IBIST_REG,
75 SP_REGS2_COUNT
76};
77
78
79struct rsp_core
80{
81 uint32_t* mem;
82 uint32_t regs[SP_REGS_COUNT];
83 uint32_t regs2[SP_REGS2_COUNT];
84 uint32_t rsp_task_locked;
85
86 struct mi_controller* mi;
87 struct rdp_core* dp;
88 struct ri_controller* ri;
89};
90
91static osal_inline uint32_t rsp_mem_address(uint32_t address)
92{
93 return (address & 0x1fff) >> 2;
94}
95
96static osal_inline uint32_t rsp_reg(uint32_t address)
97{
98 return (address & 0xffff) >> 2;
99}
100
101static osal_inline uint32_t rsp_reg2(uint32_t address)
102{
103 return (address & 0xffff) >> 2;
104}
105
106void init_rsp(struct rsp_core* sp,
107 uint32_t* sp_mem,
108 struct mi_controller* mi,
109 struct rdp_core* dp,
110 struct ri_controller* ri);
111
112void poweron_rsp(struct rsp_core* sp);
113
114void read_rsp_mem(void* opaque, uint32_t address, uint32_t* value);
115void write_rsp_mem(void* opaque, uint32_t address, uint32_t value, uint32_t mask);
116
117void read_rsp_regs(void* opaque, uint32_t address, uint32_t* value);
118void write_rsp_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask);
119
120void read_rsp_regs2(void* opaque, uint32_t address, uint32_t* value);
121void write_rsp_regs2(void* opaque, uint32_t address, uint32_t value, uint32_t mask);
122
123void do_SP_Task(struct rsp_core* sp);
124
125void rsp_interrupt_event(void* opaque);
126
127#endif
128