1#line 1 "ad_x86_format.cpp"
2//
3// Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5//
6// This code is free software; you can redistribute it and/or modify it
7// under the terms of the GNU General Public License version 2 only, as
8// published by the Free Software Foundation.
9//
10// This code is distributed in the hope that it will be useful, but WITHOUT
11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13// version 2 for more details (a copy is included in the LICENSE file that
14// accompanied this code).
15//
16// You should have received a copy of the GNU General Public License version
17// 2 along with this work; if not, write to the Free Software Foundation,
18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19//
20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21// or visit www.oracle.com if you need additional information or have any
22// questions.
23//
24//
25
26// Machine Generated File. Do Not Edit!
27
28#include "precompiled.hpp"
29#include "adfiles/ad_x86.hpp"
30
31#ifndef PRODUCT
32void UniverseOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
33 st->print("$$univ");
34}
35void UniverseOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
36 st->print("$$univ");
37}
38#endif
39
40#ifndef PRODUCT
41void sRegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
42}
43void sRegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
44}
45#endif
46
47#ifndef PRODUCT
48void sRegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
49}
50void sRegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
51}
52#endif
53
54#ifndef PRODUCT
55void sRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
56}
57void sRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
58}
59#endif
60
61#ifndef PRODUCT
62void sRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
63}
64void sRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
65}
66#endif
67
68#ifndef PRODUCT
69void sRegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
70}
71void sRegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
72}
73#endif
74
75#ifndef PRODUCT
76void immIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
77 st->print("#%d", _c0);
78}
79void immIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
80 st->print("#%d", _c0);
81}
82#endif
83
84#ifndef PRODUCT
85void immI0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
86 st->print("#%d", _c0);
87}
88void immI0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
89 st->print("#%d", _c0);
90}
91#endif
92
93#ifndef PRODUCT
94void immI1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
95 st->print("#%d", _c0);
96}
97void immI1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
98 st->print("#%d", _c0);
99}
100#endif
101
102#ifndef PRODUCT
103void immI_M1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
104 st->print("#%d", _c0);
105}
106void immI_M1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
107 st->print("#%d", _c0);
108}
109#endif
110
111#ifndef PRODUCT
112void immI2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
113 st->print("#%d", _c0);
114}
115void immI2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
116 st->print("#%d", _c0);
117}
118#endif
119
120#ifndef PRODUCT
121void immI8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
122 st->print("#%d", _c0);
123}
124void immI8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
125 st->print("#%d", _c0);
126}
127#endif
128
129#ifndef PRODUCT
130void immU8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
131 st->print("#%d", _c0);
132}
133void immU8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
134 st->print("#%d", _c0);
135}
136#endif
137
138#ifndef PRODUCT
139void immI16Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
140 st->print("#%d", _c0);
141}
142void immI16Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
143 st->print("#%d", _c0);
144}
145#endif
146
147#ifndef PRODUCT
148void immU31Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
149 st->print("#%d", _c0);
150}
151void immU31Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
152 st->print("#%d", _c0);
153}
154#endif
155
156#ifndef PRODUCT
157void immI_32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
158 st->print("#%d", _c0);
159}
160void immI_32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
161 st->print("#%d", _c0);
162}
163#endif
164
165#ifndef PRODUCT
166void immI_64Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
167 st->print("#%d", _c0);
168}
169void immI_64Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
170 st->print("#%d", _c0);
171}
172#endif
173
174#ifndef PRODUCT
175void immPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
176 if (_c0) _c0->dump_on(st);
177}
178void immPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
179 if (_c0) _c0->dump_on(st);
180}
181#endif
182
183#ifndef PRODUCT
184void immP0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
185 if (_c0) _c0->dump_on(st);
186}
187void immP0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
188 if (_c0) _c0->dump_on(st);
189}
190#endif
191
192#ifndef PRODUCT
193void immNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
194 if (_c0) _c0->dump_on(st);
195}
196void immNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
197 if (_c0) _c0->dump_on(st);
198}
199#endif
200
201#ifndef PRODUCT
202void immNKlassOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
203 if (_c0) _c0->dump_on(st);
204}
205void immNKlassOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
206 if (_c0) _c0->dump_on(st);
207}
208#endif
209
210#ifndef PRODUCT
211void immN0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
212 if (_c0) _c0->dump_on(st);
213}
214void immN0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
215 if (_c0) _c0->dump_on(st);
216}
217#endif
218
219#ifndef PRODUCT
220void immP31Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
221 if (_c0) _c0->dump_on(st);
222}
223void immP31Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
224 if (_c0) _c0->dump_on(st);
225}
226#endif
227
228#ifndef PRODUCT
229void immLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
230 st->print("#" INT64_FORMAT, (int64_t)_c0);
231}
232void immLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
233 st->print("#" INT64_FORMAT, (int64_t)_c0);
234}
235#endif
236
237#ifndef PRODUCT
238void immL8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
239 st->print("#" INT64_FORMAT, (int64_t)_c0);
240}
241void immL8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
242 st->print("#" INT64_FORMAT, (int64_t)_c0);
243}
244#endif
245
246#ifndef PRODUCT
247void immUL32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
248 st->print("#" INT64_FORMAT, (int64_t)_c0);
249}
250void immUL32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
251 st->print("#" INT64_FORMAT, (int64_t)_c0);
252}
253#endif
254
255#ifndef PRODUCT
256void immL32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
257 st->print("#" INT64_FORMAT, (int64_t)_c0);
258}
259void immL32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
260 st->print("#" INT64_FORMAT, (int64_t)_c0);
261}
262#endif
263
264#ifndef PRODUCT
265void immL0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
266 st->print("#" INT64_FORMAT, (int64_t)_c0);
267}
268void immL0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
269 st->print("#" INT64_FORMAT, (int64_t)_c0);
270}
271#endif
272
273#ifndef PRODUCT
274void immL1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
275 st->print("#" INT64_FORMAT, (int64_t)_c0);
276}
277void immL1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
278 st->print("#" INT64_FORMAT, (int64_t)_c0);
279}
280#endif
281
282#ifndef PRODUCT
283void immL_M1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
284 st->print("#" INT64_FORMAT, (int64_t)_c0);
285}
286void immL_M1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
287 st->print("#" INT64_FORMAT, (int64_t)_c0);
288}
289#endif
290
291#ifndef PRODUCT
292void immL10Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
293 st->print("#" INT64_FORMAT, (int64_t)_c0);
294}
295void immL10Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
296 st->print("#" INT64_FORMAT, (int64_t)_c0);
297}
298#endif
299
300#ifndef PRODUCT
301void immL_127Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
302 st->print("#" INT64_FORMAT, (int64_t)_c0);
303}
304void immL_127Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
305 st->print("#" INT64_FORMAT, (int64_t)_c0);
306}
307#endif
308
309#ifndef PRODUCT
310void immL_32bitsOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
311 st->print("#" INT64_FORMAT, (int64_t)_c0);
312}
313void immL_32bitsOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
314 st->print("#" INT64_FORMAT, (int64_t)_c0);
315}
316#endif
317
318#ifndef PRODUCT
319void immF0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
320 st->print("#%f", _c0);
321}
322void immF0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
323 st->print("#%f", _c0);
324}
325#endif
326
327#ifndef PRODUCT
328void immFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
329 st->print("#%f", _c0);
330}
331void immFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
332 st->print("#%f", _c0);
333}
334#endif
335
336#ifndef PRODUCT
337void immD0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
338 st->print("#%f", _c0);
339}
340void immD0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
341 st->print("#%f", _c0);
342}
343#endif
344
345#ifndef PRODUCT
346void immDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
347 st->print("#%f", _c0);
348}
349void immDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
350 st->print("#%f", _c0);
351}
352#endif
353
354#ifndef PRODUCT
355void immI_16Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
356 st->print("#%d", _c0);
357}
358void immI_16Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
359 st->print("#%d", _c0);
360}
361#endif
362
363#ifndef PRODUCT
364void immI_24Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
365 st->print("#%d", _c0);
366}
367void immI_24Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
368 st->print("#%d", _c0);
369}
370#endif
371
372#ifndef PRODUCT
373void immI_255Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
374 st->print("#%d", _c0);
375}
376void immI_255Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
377 st->print("#%d", _c0);
378}
379#endif
380
381#ifndef PRODUCT
382void immI_65535Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
383 st->print("#%d", _c0);
384}
385void immI_65535Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
386 st->print("#%d", _c0);
387}
388#endif
389
390#ifndef PRODUCT
391void immL_255Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
392 st->print("#" INT64_FORMAT, (int64_t)_c0);
393}
394void immL_255Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
395 st->print("#" INT64_FORMAT, (int64_t)_c0);
396}
397#endif
398
399#ifndef PRODUCT
400void immL_65535Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
401 st->print("#" INT64_FORMAT, (int64_t)_c0);
402}
403void immL_65535Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
404 st->print("#" INT64_FORMAT, (int64_t)_c0);
405}
406#endif
407
408#ifndef PRODUCT
409void rRegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
410 { char reg_str[128];
411 ra->dump_register(node,reg_str);
412 st->print("%s",reg_str);
413 }
414}
415void rRegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
416 { char reg_str[128];
417 ra->dump_register(node->in(idx),reg_str);
418 st->print("%s",reg_str);
419 }
420}
421#endif
422
423#ifndef PRODUCT
424void rax_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
425 st->print_raw("RAX");
426}
427void rax_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
428 st->print_raw("RAX");
429}
430#endif
431
432#ifndef PRODUCT
433void rbx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
434 st->print_raw("RBX");
435}
436void rbx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
437 st->print_raw("RBX");
438}
439#endif
440
441#ifndef PRODUCT
442void rcx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
443 st->print_raw("RCX");
444}
445void rcx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
446 st->print_raw("RCX");
447}
448#endif
449
450#ifndef PRODUCT
451void rdx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
452 st->print_raw("RDX");
453}
454void rdx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
455 st->print_raw("RDX");
456}
457#endif
458
459#ifndef PRODUCT
460void rdi_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
461 st->print_raw("RDI");
462}
463void rdi_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
464 st->print_raw("RDI");
465}
466#endif
467
468#ifndef PRODUCT
469void no_rcx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
470 { char reg_str[128];
471 ra->dump_register(node,reg_str);
472 st->print("%s",reg_str);
473 }
474}
475void no_rcx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
476 { char reg_str[128];
477 ra->dump_register(node->in(idx),reg_str);
478 st->print("%s",reg_str);
479 }
480}
481#endif
482
483#ifndef PRODUCT
484void no_rax_rdx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
485 { char reg_str[128];
486 ra->dump_register(node,reg_str);
487 st->print("%s",reg_str);
488 }
489}
490void no_rax_rdx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
491 { char reg_str[128];
492 ra->dump_register(node->in(idx),reg_str);
493 st->print("%s",reg_str);
494 }
495}
496#endif
497
498#ifndef PRODUCT
499void any_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
500 { char reg_str[128];
501 ra->dump_register(node,reg_str);
502 st->print("%s",reg_str);
503 }
504}
505void any_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
506 { char reg_str[128];
507 ra->dump_register(node->in(idx),reg_str);
508 st->print("%s",reg_str);
509 }
510}
511#endif
512
513#ifndef PRODUCT
514void rRegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
515 { char reg_str[128];
516 ra->dump_register(node,reg_str);
517 st->print("%s",reg_str);
518 }
519}
520void rRegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
521 { char reg_str[128];
522 ra->dump_register(node->in(idx),reg_str);
523 st->print("%s",reg_str);
524 }
525}
526#endif
527
528#ifndef PRODUCT
529void rRegNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
530 { char reg_str[128];
531 ra->dump_register(node,reg_str);
532 st->print("%s",reg_str);
533 }
534}
535void rRegNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
536 { char reg_str[128];
537 ra->dump_register(node->in(idx),reg_str);
538 st->print("%s",reg_str);
539 }
540}
541#endif
542
543#ifndef PRODUCT
544void no_rax_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
545 { char reg_str[128];
546 ra->dump_register(node,reg_str);
547 st->print("%s",reg_str);
548 }
549}
550void no_rax_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
551 { char reg_str[128];
552 ra->dump_register(node->in(idx),reg_str);
553 st->print("%s",reg_str);
554 }
555}
556#endif
557
558#ifndef PRODUCT
559void no_rbp_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
560 { char reg_str[128];
561 ra->dump_register(node,reg_str);
562 st->print("%s",reg_str);
563 }
564}
565void no_rbp_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
566 { char reg_str[128];
567 ra->dump_register(node->in(idx),reg_str);
568 st->print("%s",reg_str);
569 }
570}
571#endif
572
573#ifndef PRODUCT
574void no_rax_rbx_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
575 { char reg_str[128];
576 ra->dump_register(node,reg_str);
577 st->print("%s",reg_str);
578 }
579}
580void no_rax_rbx_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
581 { char reg_str[128];
582 ra->dump_register(node->in(idx),reg_str);
583 st->print("%s",reg_str);
584 }
585}
586#endif
587
588#ifndef PRODUCT
589void rax_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
590 { char reg_str[128];
591 ra->dump_register(node,reg_str);
592 st->print("%s",reg_str);
593 }
594}
595void rax_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
596 { char reg_str[128];
597 ra->dump_register(node->in(idx),reg_str);
598 st->print("%s",reg_str);
599 }
600}
601#endif
602
603#ifndef PRODUCT
604void rax_RegNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
605 { char reg_str[128];
606 ra->dump_register(node,reg_str);
607 st->print("%s",reg_str);
608 }
609}
610void rax_RegNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
611 { char reg_str[128];
612 ra->dump_register(node->in(idx),reg_str);
613 st->print("%s",reg_str);
614 }
615}
616#endif
617
618#ifndef PRODUCT
619void rbx_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
620 { char reg_str[128];
621 ra->dump_register(node,reg_str);
622 st->print("%s",reg_str);
623 }
624}
625void rbx_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
626 { char reg_str[128];
627 ra->dump_register(node->in(idx),reg_str);
628 st->print("%s",reg_str);
629 }
630}
631#endif
632
633#ifndef PRODUCT
634void rsi_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
635 { char reg_str[128];
636 ra->dump_register(node,reg_str);
637 st->print("%s",reg_str);
638 }
639}
640void rsi_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
641 { char reg_str[128];
642 ra->dump_register(node->in(idx),reg_str);
643 st->print("%s",reg_str);
644 }
645}
646#endif
647
648#ifndef PRODUCT
649void rdi_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
650 { char reg_str[128];
651 ra->dump_register(node,reg_str);
652 st->print("%s",reg_str);
653 }
654}
655void rdi_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
656 { char reg_str[128];
657 ra->dump_register(node->in(idx),reg_str);
658 st->print("%s",reg_str);
659 }
660}
661#endif
662
663#ifndef PRODUCT
664void r15_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
665 { char reg_str[128];
666 ra->dump_register(node,reg_str);
667 st->print("%s",reg_str);
668 }
669}
670void r15_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
671 { char reg_str[128];
672 ra->dump_register(node->in(idx),reg_str);
673 st->print("%s",reg_str);
674 }
675}
676#endif
677
678#ifndef PRODUCT
679void rRegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
680 { char reg_str[128];
681 ra->dump_register(node,reg_str);
682 st->print("%s",reg_str);
683 }
684}
685void rRegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
686 { char reg_str[128];
687 ra->dump_register(node->in(idx),reg_str);
688 st->print("%s",reg_str);
689 }
690}
691#endif
692
693#ifndef PRODUCT
694void no_rax_rdx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
695 { char reg_str[128];
696 ra->dump_register(node,reg_str);
697 st->print("%s",reg_str);
698 }
699}
700void no_rax_rdx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
701 { char reg_str[128];
702 ra->dump_register(node->in(idx),reg_str);
703 st->print("%s",reg_str);
704 }
705}
706#endif
707
708#ifndef PRODUCT
709void no_rax_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
710 { char reg_str[128];
711 ra->dump_register(node,reg_str);
712 st->print("%s",reg_str);
713 }
714}
715void no_rax_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
716 { char reg_str[128];
717 ra->dump_register(node->in(idx),reg_str);
718 st->print("%s",reg_str);
719 }
720}
721#endif
722
723#ifndef PRODUCT
724void no_rcx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
725 { char reg_str[128];
726 ra->dump_register(node,reg_str);
727 st->print("%s",reg_str);
728 }
729}
730void no_rcx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
731 { char reg_str[128];
732 ra->dump_register(node->in(idx),reg_str);
733 st->print("%s",reg_str);
734 }
735}
736#endif
737
738#ifndef PRODUCT
739void rax_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
740 st->print_raw("RAX");
741}
742void rax_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
743 st->print_raw("RAX");
744}
745#endif
746
747#ifndef PRODUCT
748void rcx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
749 { char reg_str[128];
750 ra->dump_register(node,reg_str);
751 st->print("%s",reg_str);
752 }
753}
754void rcx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
755 { char reg_str[128];
756 ra->dump_register(node->in(idx),reg_str);
757 st->print("%s",reg_str);
758 }
759}
760#endif
761
762#ifndef PRODUCT
763void rdx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
764 { char reg_str[128];
765 ra->dump_register(node,reg_str);
766 st->print("%s",reg_str);
767 }
768}
769void rdx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
770 { char reg_str[128];
771 ra->dump_register(node->in(idx),reg_str);
772 st->print("%s",reg_str);
773 }
774}
775#endif
776
777#ifndef PRODUCT
778void rFlagsRegOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
779 st->print_raw("RFLAGS");
780}
781void rFlagsRegOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
782 st->print_raw("RFLAGS");
783}
784#endif
785
786#ifndef PRODUCT
787void rFlagsRegUOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
788 st->print_raw("RFLAGS_U");
789}
790void rFlagsRegUOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
791 st->print_raw("RFLAGS_U");
792}
793#endif
794
795#ifndef PRODUCT
796void rFlagsRegUCFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
797 st->print_raw("RFLAGS_U_CF");
798}
799void rFlagsRegUCFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
800 st->print_raw("RFLAGS_U_CF");
801}
802#endif
803
804#ifndef PRODUCT
805void regFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
806 { char reg_str[128];
807 ra->dump_register(node,reg_str);
808 st->print("%s",reg_str);
809 }
810}
811void regFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
812 { char reg_str[128];
813 ra->dump_register(node->in(idx),reg_str);
814 st->print("%s",reg_str);
815 }
816}
817#endif
818
819#ifndef PRODUCT
820void legRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
821 { char reg_str[128];
822 ra->dump_register(node,reg_str);
823 st->print("%s",reg_str);
824 }
825}
826void legRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
827 { char reg_str[128];
828 ra->dump_register(node->in(idx),reg_str);
829 st->print("%s",reg_str);
830 }
831}
832#endif
833
834#ifndef PRODUCT
835void vlRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
836 { char reg_str[128];
837 ra->dump_register(node,reg_str);
838 st->print("%s",reg_str);
839 }
840}
841void vlRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
842 { char reg_str[128];
843 ra->dump_register(node->in(idx),reg_str);
844 st->print("%s",reg_str);
845 }
846}
847#endif
848
849#ifndef PRODUCT
850void regDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
851 { char reg_str[128];
852 ra->dump_register(node,reg_str);
853 st->print("%s",reg_str);
854 }
855}
856void regDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
857 { char reg_str[128];
858 ra->dump_register(node->in(idx),reg_str);
859 st->print("%s",reg_str);
860 }
861}
862#endif
863
864#ifndef PRODUCT
865void legRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
866 { char reg_str[128];
867 ra->dump_register(node,reg_str);
868 st->print("%s",reg_str);
869 }
870}
871void legRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
872 { char reg_str[128];
873 ra->dump_register(node->in(idx),reg_str);
874 st->print("%s",reg_str);
875 }
876}
877#endif
878
879#ifndef PRODUCT
880void vlRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
881 { char reg_str[128];
882 ra->dump_register(node,reg_str);
883 st->print("%s",reg_str);
884 }
885}
886void vlRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
887 { char reg_str[128];
888 ra->dump_register(node->in(idx),reg_str);
889 st->print("%s",reg_str);
890 }
891}
892#endif
893
894#ifndef PRODUCT
895void vecSOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
896 { char reg_str[128];
897 ra->dump_register(node,reg_str);
898 st->print("%s",reg_str);
899 }
900}
901void vecSOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
902 { char reg_str[128];
903 ra->dump_register(node->in(idx),reg_str);
904 st->print("%s",reg_str);
905 }
906}
907#endif
908
909#ifndef PRODUCT
910void legVecSOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
911 { char reg_str[128];
912 ra->dump_register(node,reg_str);
913 st->print("%s",reg_str);
914 }
915}
916void legVecSOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
917 { char reg_str[128];
918 ra->dump_register(node->in(idx),reg_str);
919 st->print("%s",reg_str);
920 }
921}
922#endif
923
924#ifndef PRODUCT
925void vecDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
926 { char reg_str[128];
927 ra->dump_register(node,reg_str);
928 st->print("%s",reg_str);
929 }
930}
931void vecDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
932 { char reg_str[128];
933 ra->dump_register(node->in(idx),reg_str);
934 st->print("%s",reg_str);
935 }
936}
937#endif
938
939#ifndef PRODUCT
940void legVecDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
941 { char reg_str[128];
942 ra->dump_register(node,reg_str);
943 st->print("%s",reg_str);
944 }
945}
946void legVecDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
947 { char reg_str[128];
948 ra->dump_register(node->in(idx),reg_str);
949 st->print("%s",reg_str);
950 }
951}
952#endif
953
954#ifndef PRODUCT
955void vecXOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
956 { char reg_str[128];
957 ra->dump_register(node,reg_str);
958 st->print("%s",reg_str);
959 }
960}
961void vecXOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
962 { char reg_str[128];
963 ra->dump_register(node->in(idx),reg_str);
964 st->print("%s",reg_str);
965 }
966}
967#endif
968
969#ifndef PRODUCT
970void legVecXOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
971 { char reg_str[128];
972 ra->dump_register(node,reg_str);
973 st->print("%s",reg_str);
974 }
975}
976void legVecXOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
977 { char reg_str[128];
978 ra->dump_register(node->in(idx),reg_str);
979 st->print("%s",reg_str);
980 }
981}
982#endif
983
984#ifndef PRODUCT
985void vecYOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
986 { char reg_str[128];
987 ra->dump_register(node,reg_str);
988 st->print("%s",reg_str);
989 }
990}
991void vecYOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
992 { char reg_str[128];
993 ra->dump_register(node->in(idx),reg_str);
994 st->print("%s",reg_str);
995 }
996}
997#endif
998
999#ifndef PRODUCT
1000void legVecYOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1001 { char reg_str[128];
1002 ra->dump_register(node,reg_str);
1003 st->print("%s",reg_str);
1004 }
1005}
1006void legVecYOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1007 { char reg_str[128];
1008 ra->dump_register(node->in(idx),reg_str);
1009 st->print("%s",reg_str);
1010 }
1011}
1012#endif
1013
1014#ifndef PRODUCT
1015void indirectOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1016 st->print_raw("[");
1017 { char reg_str[128];
1018 ra->dump_register(node,reg_str);
1019 st->print("%s",reg_str);
1020 }
1021 st->print_raw("]");
1022}
1023void indirectOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1024 st->print_raw("[");
1025 { char reg_str[128];
1026 ra->dump_register(node->in(idx),reg_str);
1027 st->print("%s",reg_str);
1028 }
1029 st->print_raw("]");
1030}
1031#endif
1032
1033#ifndef PRODUCT
1034void indOffset8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1035 st->print_raw("[");
1036 { char reg_str[128];
1037 ra->dump_register(node,reg_str);
1038 st->print("%s",reg_str);
1039 }
1040 st->print_raw(" + ");
1041 st->print("#" INT64_FORMAT, (int64_t)_c0);
1042 st->print_raw(" (8-bit)]");
1043}
1044void indOffset8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1045 st->print_raw("[");
1046 { char reg_str[128];
1047 ra->dump_register(node->in(idx),reg_str);
1048 st->print("%s",reg_str);
1049 }
1050 st->print_raw(" + ");
1051 st->print("#" INT64_FORMAT, (int64_t)_c0);
1052 st->print_raw(" (8-bit)]");
1053}
1054#endif
1055
1056#ifndef PRODUCT
1057void indOffset32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1058 st->print_raw("[");
1059 { char reg_str[128];
1060 ra->dump_register(node,reg_str);
1061 st->print("%s",reg_str);
1062 }
1063 st->print_raw(" + ");
1064 st->print("#" INT64_FORMAT, (int64_t)_c0);
1065 st->print_raw(" (32-bit)]");
1066}
1067void indOffset32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1068 st->print_raw("[");
1069 { char reg_str[128];
1070 ra->dump_register(node->in(idx),reg_str);
1071 st->print("%s",reg_str);
1072 }
1073 st->print_raw(" + ");
1074 st->print("#" INT64_FORMAT, (int64_t)_c0);
1075 st->print_raw(" (32-bit)]");
1076}
1077#endif
1078
1079#ifndef PRODUCT
1080void indIndexOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1081 st->print_raw("[");
1082 { char reg_str[128];
1083 ra->dump_register(node,reg_str);
1084 st->print("%s",reg_str);
1085 }
1086 st->print_raw(" + ");
1087 st->print("#" INT64_FORMAT, (int64_t)_c0);
1088 st->print_raw(" + ");
1089 { char reg_str[128];
1090 ra->dump_register(node,reg_str);
1091 st->print("%s",reg_str);
1092 }
1093 st->print_raw("]");
1094}
1095void indIndexOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1096 st->print_raw("[");
1097 { char reg_str[128];
1098 ra->dump_register(node->in(idx),reg_str);
1099 st->print("%s",reg_str);
1100 }
1101 st->print_raw(" + ");
1102 st->print("#" INT64_FORMAT, (int64_t)_c0);
1103 st->print_raw(" + ");
1104 { char reg_str[128];
1105 ra->dump_register(node->in(idx+1),reg_str);
1106 st->print("%s",reg_str);
1107 }
1108 st->print_raw("]");
1109}
1110#endif
1111
1112#ifndef PRODUCT
1113void indIndexOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1114 st->print_raw("[");
1115 { char reg_str[128];
1116 ra->dump_register(node,reg_str);
1117 st->print("%s",reg_str);
1118 }
1119 st->print_raw(" + ");
1120 { char reg_str[128];
1121 ra->dump_register(node,reg_str);
1122 st->print("%s",reg_str);
1123 }
1124 st->print_raw("]");
1125}
1126void indIndexOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1127 st->print_raw("[");
1128 { char reg_str[128];
1129 ra->dump_register(node->in(idx),reg_str);
1130 st->print("%s",reg_str);
1131 }
1132 st->print_raw(" + ");
1133 { char reg_str[128];
1134 ra->dump_register(node->in(idx+1),reg_str);
1135 st->print("%s",reg_str);
1136 }
1137 st->print_raw("]");
1138}
1139#endif
1140
1141#ifndef PRODUCT
1142void indIndexScaleOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1143 st->print_raw("[");
1144 { char reg_str[128];
1145 ra->dump_register(node,reg_str);
1146 st->print("%s",reg_str);
1147 }
1148 st->print_raw(" + ");
1149 { char reg_str[128];
1150 ra->dump_register(node,reg_str);
1151 st->print("%s",reg_str);
1152 }
1153 st->print_raw(" << ");
1154 st->print("#%d", _c0);
1155 st->print_raw("]");
1156}
1157void indIndexScaleOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1158 st->print_raw("[");
1159 { char reg_str[128];
1160 ra->dump_register(node->in(idx),reg_str);
1161 st->print("%s",reg_str);
1162 }
1163 st->print_raw(" + ");
1164 { char reg_str[128];
1165 ra->dump_register(node->in(idx+1),reg_str);
1166 st->print("%s",reg_str);
1167 }
1168 st->print_raw(" << ");
1169 st->print("#%d", _c0);
1170 st->print_raw("]");
1171}
1172#endif
1173
1174#ifndef PRODUCT
1175void indPosIndexScaleOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1176 st->print_raw("[");
1177 { char reg_str[128];
1178 ra->dump_register(node,reg_str);
1179 st->print("%s",reg_str);
1180 }
1181 st->print_raw(" + pos ");
1182 { char reg_str[128];
1183 ra->dump_register(node,reg_str);
1184 st->print("%s",reg_str);
1185 }
1186 st->print_raw(" << ");
1187 st->print("#%d", _c0);
1188 st->print_raw("]");
1189}
1190void indPosIndexScaleOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1191 st->print_raw("[");
1192 { char reg_str[128];
1193 ra->dump_register(node->in(idx),reg_str);
1194 st->print("%s",reg_str);
1195 }
1196 st->print_raw(" + pos ");
1197 { char reg_str[128];
1198 ra->dump_register(node->in(idx+1),reg_str);
1199 st->print("%s",reg_str);
1200 }
1201 st->print_raw(" << ");
1202 st->print("#%d", _c0);
1203 st->print_raw("]");
1204}
1205#endif
1206
1207#ifndef PRODUCT
1208void indIndexScaleOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1209 st->print_raw("[");
1210 { char reg_str[128];
1211 ra->dump_register(node,reg_str);
1212 st->print("%s",reg_str);
1213 }
1214 st->print_raw(" + ");
1215 st->print("#" INT64_FORMAT, (int64_t)_c1);
1216 st->print_raw(" + ");
1217 { char reg_str[128];
1218 ra->dump_register(node,reg_str);
1219 st->print("%s",reg_str);
1220 }
1221 st->print_raw(" << ");
1222 st->print("#%d", _c0);
1223 st->print_raw("]");
1224}
1225void indIndexScaleOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1226 st->print_raw("[");
1227 { char reg_str[128];
1228 ra->dump_register(node->in(idx),reg_str);
1229 st->print("%s",reg_str);
1230 }
1231 st->print_raw(" + ");
1232 st->print("#" INT64_FORMAT, (int64_t)_c1);
1233 st->print_raw(" + ");
1234 { char reg_str[128];
1235 ra->dump_register(node->in(idx+1),reg_str);
1236 st->print("%s",reg_str);
1237 }
1238 st->print_raw(" << ");
1239 st->print("#%d", _c0);
1240 st->print_raw("]");
1241}
1242#endif
1243
1244#ifndef PRODUCT
1245void indPosIndexOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1246 st->print_raw("[");
1247 { char reg_str[128];
1248 ra->dump_register(node,reg_str);
1249 st->print("%s",reg_str);
1250 }
1251 st->print_raw(" + ");
1252 st->print("#" INT64_FORMAT, (int64_t)_c0);
1253 st->print_raw(" + ");
1254 { char reg_str[128];
1255 ra->dump_register(node,reg_str);
1256 st->print("%s",reg_str);
1257 }
1258 st->print_raw("]");
1259}
1260void indPosIndexOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1261 st->print_raw("[");
1262 { char reg_str[128];
1263 ra->dump_register(node->in(idx),reg_str);
1264 st->print("%s",reg_str);
1265 }
1266 st->print_raw(" + ");
1267 st->print("#" INT64_FORMAT, (int64_t)_c0);
1268 st->print_raw(" + ");
1269 { char reg_str[128];
1270 ra->dump_register(node->in(idx+1),reg_str);
1271 st->print("%s",reg_str);
1272 }
1273 st->print_raw("]");
1274}
1275#endif
1276
1277#ifndef PRODUCT
1278void indPosIndexScaleOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1279 st->print_raw("[");
1280 { char reg_str[128];
1281 ra->dump_register(node,reg_str);
1282 st->print("%s",reg_str);
1283 }
1284 st->print_raw(" + ");
1285 st->print("#" INT64_FORMAT, (int64_t)_c1);
1286 st->print_raw(" + ");
1287 { char reg_str[128];
1288 ra->dump_register(node,reg_str);
1289 st->print("%s",reg_str);
1290 }
1291 st->print_raw(" << ");
1292 st->print("#%d", _c0);
1293 st->print_raw("]");
1294}
1295void indPosIndexScaleOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1296 st->print_raw("[");
1297 { char reg_str[128];
1298 ra->dump_register(node->in(idx),reg_str);
1299 st->print("%s",reg_str);
1300 }
1301 st->print_raw(" + ");
1302 st->print("#" INT64_FORMAT, (int64_t)_c1);
1303 st->print_raw(" + ");
1304 { char reg_str[128];
1305 ra->dump_register(node->in(idx+1),reg_str);
1306 st->print("%s",reg_str);
1307 }
1308 st->print_raw(" << ");
1309 st->print("#%d", _c0);
1310 st->print_raw("]");
1311}
1312#endif
1313
1314#ifndef PRODUCT
1315void indCompressedOopOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1316 st->print_raw("[R12 + ");
1317 { char reg_str[128];
1318 ra->dump_register(node,reg_str);
1319 st->print("%s",reg_str);
1320 }
1321 st->print_raw(" << 3 + ");
1322 st->print("#" INT64_FORMAT, (int64_t)_c0);
1323 st->print_raw("] (compressed oop addressing)");
1324}
1325void indCompressedOopOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1326 st->print_raw("[R12 + ");
1327 { char reg_str[128];
1328 ra->dump_register(node->in(idx),reg_str);
1329 st->print("%s",reg_str);
1330 }
1331 st->print_raw(" << 3 + ");
1332 st->print("#" INT64_FORMAT, (int64_t)_c0);
1333 st->print_raw("] (compressed oop addressing)");
1334}
1335#endif
1336
1337#ifndef PRODUCT
1338void indirectNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1339 st->print_raw("[");
1340 { char reg_str[128];
1341 ra->dump_register(node,reg_str);
1342 st->print("%s",reg_str);
1343 }
1344 st->print_raw("]");
1345}
1346void indirectNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1347 st->print_raw("[");
1348 { char reg_str[128];
1349 ra->dump_register(node->in(idx),reg_str);
1350 st->print("%s",reg_str);
1351 }
1352 st->print_raw("]");
1353}
1354#endif
1355
1356#ifndef PRODUCT
1357void indOffset8NarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1358 st->print_raw("[");
1359 { char reg_str[128];
1360 ra->dump_register(node,reg_str);
1361 st->print("%s",reg_str);
1362 }
1363 st->print_raw(" + ");
1364 st->print("#" INT64_FORMAT, (int64_t)_c0);
1365 st->print_raw(" (8-bit)]");
1366}
1367void indOffset8NarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1368 st->print_raw("[");
1369 { char reg_str[128];
1370 ra->dump_register(node->in(idx),reg_str);
1371 st->print("%s",reg_str);
1372 }
1373 st->print_raw(" + ");
1374 st->print("#" INT64_FORMAT, (int64_t)_c0);
1375 st->print_raw(" (8-bit)]");
1376}
1377#endif
1378
1379#ifndef PRODUCT
1380void indOffset32NarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1381 st->print_raw("[");
1382 { char reg_str[128];
1383 ra->dump_register(node,reg_str);
1384 st->print("%s",reg_str);
1385 }
1386 st->print_raw(" + ");
1387 st->print("#" INT64_FORMAT, (int64_t)_c0);
1388 st->print_raw(" (32-bit)]");
1389}
1390void indOffset32NarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1391 st->print_raw("[");
1392 { char reg_str[128];
1393 ra->dump_register(node->in(idx),reg_str);
1394 st->print("%s",reg_str);
1395 }
1396 st->print_raw(" + ");
1397 st->print("#" INT64_FORMAT, (int64_t)_c0);
1398 st->print_raw(" (32-bit)]");
1399}
1400#endif
1401
1402#ifndef PRODUCT
1403void indIndexOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1404 st->print_raw("[");
1405 { char reg_str[128];
1406 ra->dump_register(node,reg_str);
1407 st->print("%s",reg_str);
1408 }
1409 st->print_raw(" + ");
1410 st->print("#" INT64_FORMAT, (int64_t)_c0);
1411 st->print_raw(" + ");
1412 { char reg_str[128];
1413 ra->dump_register(node,reg_str);
1414 st->print("%s",reg_str);
1415 }
1416 st->print_raw("]");
1417}
1418void indIndexOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1419 st->print_raw("[");
1420 { char reg_str[128];
1421 ra->dump_register(node->in(idx),reg_str);
1422 st->print("%s",reg_str);
1423 }
1424 st->print_raw(" + ");
1425 st->print("#" INT64_FORMAT, (int64_t)_c0);
1426 st->print_raw(" + ");
1427 { char reg_str[128];
1428 ra->dump_register(node->in(idx+1),reg_str);
1429 st->print("%s",reg_str);
1430 }
1431 st->print_raw("]");
1432}
1433#endif
1434
1435#ifndef PRODUCT
1436void indIndexNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1437 st->print_raw("[");
1438 { char reg_str[128];
1439 ra->dump_register(node,reg_str);
1440 st->print("%s",reg_str);
1441 }
1442 st->print_raw(" + ");
1443 { char reg_str[128];
1444 ra->dump_register(node,reg_str);
1445 st->print("%s",reg_str);
1446 }
1447 st->print_raw("]");
1448}
1449void indIndexNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1450 st->print_raw("[");
1451 { char reg_str[128];
1452 ra->dump_register(node->in(idx),reg_str);
1453 st->print("%s",reg_str);
1454 }
1455 st->print_raw(" + ");
1456 { char reg_str[128];
1457 ra->dump_register(node->in(idx+1),reg_str);
1458 st->print("%s",reg_str);
1459 }
1460 st->print_raw("]");
1461}
1462#endif
1463
1464#ifndef PRODUCT
1465void indIndexScaleNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1466 st->print_raw("[");
1467 { char reg_str[128];
1468 ra->dump_register(node,reg_str);
1469 st->print("%s",reg_str);
1470 }
1471 st->print_raw(" + ");
1472 { char reg_str[128];
1473 ra->dump_register(node,reg_str);
1474 st->print("%s",reg_str);
1475 }
1476 st->print_raw(" << ");
1477 st->print("#%d", _c0);
1478 st->print_raw("]");
1479}
1480void indIndexScaleNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1481 st->print_raw("[");
1482 { char reg_str[128];
1483 ra->dump_register(node->in(idx),reg_str);
1484 st->print("%s",reg_str);
1485 }
1486 st->print_raw(" + ");
1487 { char reg_str[128];
1488 ra->dump_register(node->in(idx+1),reg_str);
1489 st->print("%s",reg_str);
1490 }
1491 st->print_raw(" << ");
1492 st->print("#%d", _c0);
1493 st->print_raw("]");
1494}
1495#endif
1496
1497#ifndef PRODUCT
1498void indIndexScaleOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1499 st->print_raw("[");
1500 { char reg_str[128];
1501 ra->dump_register(node,reg_str);
1502 st->print("%s",reg_str);
1503 }
1504 st->print_raw(" + ");
1505 st->print("#" INT64_FORMAT, (int64_t)_c1);
1506 st->print_raw(" + ");
1507 { char reg_str[128];
1508 ra->dump_register(node,reg_str);
1509 st->print("%s",reg_str);
1510 }
1511 st->print_raw(" << ");
1512 st->print("#%d", _c0);
1513 st->print_raw("]");
1514}
1515void indIndexScaleOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1516 st->print_raw("[");
1517 { char reg_str[128];
1518 ra->dump_register(node->in(idx),reg_str);
1519 st->print("%s",reg_str);
1520 }
1521 st->print_raw(" + ");
1522 st->print("#" INT64_FORMAT, (int64_t)_c1);
1523 st->print_raw(" + ");
1524 { char reg_str[128];
1525 ra->dump_register(node->in(idx+1),reg_str);
1526 st->print("%s",reg_str);
1527 }
1528 st->print_raw(" << ");
1529 st->print("#%d", _c0);
1530 st->print_raw("]");
1531}
1532#endif
1533
1534#ifndef PRODUCT
1535void indPosIndexOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1536 st->print_raw("[");
1537 { char reg_str[128];
1538 ra->dump_register(node,reg_str);
1539 st->print("%s",reg_str);
1540 }
1541 st->print_raw(" + ");
1542 st->print("#" INT64_FORMAT, (int64_t)_c0);
1543 st->print_raw(" + ");
1544 { char reg_str[128];
1545 ra->dump_register(node,reg_str);
1546 st->print("%s",reg_str);
1547 }
1548 st->print_raw("]");
1549}
1550void indPosIndexOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1551 st->print_raw("[");
1552 { char reg_str[128];
1553 ra->dump_register(node->in(idx),reg_str);
1554 st->print("%s",reg_str);
1555 }
1556 st->print_raw(" + ");
1557 st->print("#" INT64_FORMAT, (int64_t)_c0);
1558 st->print_raw(" + ");
1559 { char reg_str[128];
1560 ra->dump_register(node->in(idx+1),reg_str);
1561 st->print("%s",reg_str);
1562 }
1563 st->print_raw("]");
1564}
1565#endif
1566
1567#ifndef PRODUCT
1568void indPosIndexScaleOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1569 st->print_raw("[");
1570 { char reg_str[128];
1571 ra->dump_register(node,reg_str);
1572 st->print("%s",reg_str);
1573 }
1574 st->print_raw(" + ");
1575 st->print("#" INT64_FORMAT, (int64_t)_c1);
1576 st->print_raw(" + ");
1577 { char reg_str[128];
1578 ra->dump_register(node,reg_str);
1579 st->print("%s",reg_str);
1580 }
1581 st->print_raw(" << ");
1582 st->print("#%d", _c0);
1583 st->print_raw("]");
1584}
1585void indPosIndexScaleOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1586 st->print_raw("[");
1587 { char reg_str[128];
1588 ra->dump_register(node->in(idx),reg_str);
1589 st->print("%s",reg_str);
1590 }
1591 st->print_raw(" + ");
1592 st->print("#" INT64_FORMAT, (int64_t)_c1);
1593 st->print_raw(" + ");
1594 { char reg_str[128];
1595 ra->dump_register(node->in(idx+1),reg_str);
1596 st->print("%s",reg_str);
1597 }
1598 st->print_raw(" << ");
1599 st->print("#%d", _c0);
1600 st->print_raw("]");
1601}
1602#endif
1603
1604#ifndef PRODUCT
1605void stackSlotPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1606 st->print_raw("[");
1607 { char reg_str[128];
1608 ra->dump_register(node,reg_str);
1609 st->print("%s",reg_str);
1610 }
1611 st->print_raw("]");
1612}
1613void stackSlotPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1614 st->print_raw("[");
1615 { char reg_str[128];
1616 ra->dump_register(node->in(idx),reg_str);
1617 st->print("%s",reg_str);
1618 }
1619 st->print_raw("]");
1620}
1621#endif
1622
1623#ifndef PRODUCT
1624void stackSlotIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1625 st->print_raw("[");
1626 { char reg_str[128];
1627 ra->dump_register(node,reg_str);
1628 st->print("%s",reg_str);
1629 }
1630 st->print_raw("]");
1631}
1632void stackSlotIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1633 st->print_raw("[");
1634 { char reg_str[128];
1635 ra->dump_register(node->in(idx),reg_str);
1636 st->print("%s",reg_str);
1637 }
1638 st->print_raw("]");
1639}
1640#endif
1641
1642#ifndef PRODUCT
1643void stackSlotFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1644 st->print_raw("[");
1645 { char reg_str[128];
1646 ra->dump_register(node,reg_str);
1647 st->print("%s",reg_str);
1648 }
1649 st->print_raw("]");
1650}
1651void stackSlotFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1652 st->print_raw("[");
1653 { char reg_str[128];
1654 ra->dump_register(node->in(idx),reg_str);
1655 st->print("%s",reg_str);
1656 }
1657 st->print_raw("]");
1658}
1659#endif
1660
1661#ifndef PRODUCT
1662void stackSlotDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1663 st->print_raw("[");
1664 { char reg_str[128];
1665 ra->dump_register(node,reg_str);
1666 st->print("%s",reg_str);
1667 }
1668 st->print_raw("]");
1669}
1670void stackSlotDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1671 st->print_raw("[");
1672 { char reg_str[128];
1673 ra->dump_register(node->in(idx),reg_str);
1674 st->print("%s",reg_str);
1675 }
1676 st->print_raw("]");
1677}
1678#endif
1679
1680#ifndef PRODUCT
1681void stackSlotLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1682 st->print_raw("[");
1683 { char reg_str[128];
1684 ra->dump_register(node,reg_str);
1685 st->print("%s",reg_str);
1686 }
1687 st->print_raw("]");
1688}
1689void stackSlotLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1690 st->print_raw("[");
1691 { char reg_str[128];
1692 ra->dump_register(node->in(idx),reg_str);
1693 st->print("%s",reg_str);
1694 }
1695 st->print_raw("]");
1696}
1697#endif
1698
1699#ifndef PRODUCT
1700void cmpOpOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1701 st->print_raw("");
1702 if( _c0 == BoolTest::eq ) st->print_raw("e");
1703 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1704 else if( _c0 == BoolTest::le ) st->print_raw("le");
1705 else if( _c0 == BoolTest::ge ) st->print_raw("ge");
1706 else if( _c0 == BoolTest::lt ) st->print_raw("l");
1707 else if( _c0 == BoolTest::gt ) st->print_raw("g");
1708 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1709 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1710}
1711void cmpOpOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1712 st->print_raw("");
1713 if( _c0 == BoolTest::eq ) st->print_raw("e");
1714 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1715 else if( _c0 == BoolTest::le ) st->print_raw("le");
1716 else if( _c0 == BoolTest::ge ) st->print_raw("ge");
1717 else if( _c0 == BoolTest::lt ) st->print_raw("l");
1718 else if( _c0 == BoolTest::gt ) st->print_raw("g");
1719 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1720 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1721}
1722#endif
1723
1724#ifndef PRODUCT
1725void cmpOpUOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1726 st->print_raw("");
1727 if( _c0 == BoolTest::eq ) st->print_raw("e");
1728 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1729 else if( _c0 == BoolTest::le ) st->print_raw("be");
1730 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1731 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1732 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1733 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1734 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1735}
1736void cmpOpUOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1737 st->print_raw("");
1738 if( _c0 == BoolTest::eq ) st->print_raw("e");
1739 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1740 else if( _c0 == BoolTest::le ) st->print_raw("be");
1741 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1742 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1743 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1744 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1745 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1746}
1747#endif
1748
1749#ifndef PRODUCT
1750void cmpOpUCFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1751 st->print_raw("");
1752 if( _c0 == BoolTest::eq ) st->print_raw("e");
1753 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1754 else if( _c0 == BoolTest::le ) st->print_raw("be");
1755 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1756 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1757 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1758 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1759 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1760}
1761void cmpOpUCFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1762 st->print_raw("");
1763 if( _c0 == BoolTest::eq ) st->print_raw("e");
1764 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1765 else if( _c0 == BoolTest::le ) st->print_raw("be");
1766 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1767 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1768 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1769 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1770 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1771}
1772#endif
1773
1774#ifndef PRODUCT
1775void cmpOpUCF2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1776 st->print_raw("");
1777 if( _c0 == BoolTest::eq ) st->print_raw("e");
1778 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1779 else if( _c0 == BoolTest::le ) st->print_raw("be");
1780 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1781 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1782 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1783 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1784 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1785}
1786void cmpOpUCF2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1787 st->print_raw("");
1788 if( _c0 == BoolTest::eq ) st->print_raw("e");
1789 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
1790 else if( _c0 == BoolTest::le ) st->print_raw("be");
1791 else if( _c0 == BoolTest::ge ) st->print_raw("nb");
1792 else if( _c0 == BoolTest::lt ) st->print_raw("b");
1793 else if( _c0 == BoolTest::gt ) st->print_raw("nbe");
1794 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
1795 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
1796}
1797#endif
1798
1799#ifndef PRODUCT
1800void rxmm0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1801 { char reg_str[128];
1802 ra->dump_register(node,reg_str);
1803 st->print("%s",reg_str);
1804 }
1805}
1806void rxmm0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1807 { char reg_str[128];
1808 ra->dump_register(node->in(idx),reg_str);
1809 st->print("%s",reg_str);
1810 }
1811}
1812#endif
1813
1814#ifndef PRODUCT
1815void rxmm1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1816 { char reg_str[128];
1817 ra->dump_register(node,reg_str);
1818 st->print("%s",reg_str);
1819 }
1820}
1821void rxmm1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1822 { char reg_str[128];
1823 ra->dump_register(node->in(idx),reg_str);
1824 st->print("%s",reg_str);
1825 }
1826}
1827#endif
1828
1829#ifndef PRODUCT
1830void rxmm2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1831 { char reg_str[128];
1832 ra->dump_register(node,reg_str);
1833 st->print("%s",reg_str);
1834 }
1835}
1836void rxmm2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1837 { char reg_str[128];
1838 ra->dump_register(node->in(idx),reg_str);
1839 st->print("%s",reg_str);
1840 }
1841}
1842#endif
1843
1844#ifndef PRODUCT
1845void rxmm3Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1846 { char reg_str[128];
1847 ra->dump_register(node,reg_str);
1848 st->print("%s",reg_str);
1849 }
1850}
1851void rxmm3Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1852 { char reg_str[128];
1853 ra->dump_register(node->in(idx),reg_str);
1854 st->print("%s",reg_str);
1855 }
1856}
1857#endif
1858
1859#ifndef PRODUCT
1860void rxmm4Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1861 { char reg_str[128];
1862 ra->dump_register(node,reg_str);
1863 st->print("%s",reg_str);
1864 }
1865}
1866void rxmm4Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1867 { char reg_str[128];
1868 ra->dump_register(node->in(idx),reg_str);
1869 st->print("%s",reg_str);
1870 }
1871}
1872#endif
1873
1874#ifndef PRODUCT
1875void rxmm5Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1876 { char reg_str[128];
1877 ra->dump_register(node,reg_str);
1878 st->print("%s",reg_str);
1879 }
1880}
1881void rxmm5Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1882 { char reg_str[128];
1883 ra->dump_register(node->in(idx),reg_str);
1884 st->print("%s",reg_str);
1885 }
1886}
1887#endif
1888
1889#ifndef PRODUCT
1890void rxmm6Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1891 { char reg_str[128];
1892 ra->dump_register(node,reg_str);
1893 st->print("%s",reg_str);
1894 }
1895}
1896void rxmm6Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1897 { char reg_str[128];
1898 ra->dump_register(node->in(idx),reg_str);
1899 st->print("%s",reg_str);
1900 }
1901}
1902#endif
1903
1904#ifndef PRODUCT
1905void rxmm7Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1906 { char reg_str[128];
1907 ra->dump_register(node,reg_str);
1908 st->print("%s",reg_str);
1909 }
1910}
1911void rxmm7Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1912 { char reg_str[128];
1913 ra->dump_register(node->in(idx),reg_str);
1914 st->print("%s",reg_str);
1915 }
1916}
1917#endif
1918
1919#ifndef PRODUCT
1920void rxmm8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1921 { char reg_str[128];
1922 ra->dump_register(node,reg_str);
1923 st->print("%s",reg_str);
1924 }
1925}
1926void rxmm8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1927 { char reg_str[128];
1928 ra->dump_register(node->in(idx),reg_str);
1929 st->print("%s",reg_str);
1930 }
1931}
1932#endif
1933
1934#ifndef PRODUCT
1935void rxmm9Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1936 { char reg_str[128];
1937 ra->dump_register(node,reg_str);
1938 st->print("%s",reg_str);
1939 }
1940}
1941void rxmm9Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1942 { char reg_str[128];
1943 ra->dump_register(node->in(idx),reg_str);
1944 st->print("%s",reg_str);
1945 }
1946}
1947#endif
1948
1949#ifndef PRODUCT
1950void rxmm10Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1951 { char reg_str[128];
1952 ra->dump_register(node,reg_str);
1953 st->print("%s",reg_str);
1954 }
1955}
1956void rxmm10Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1957 { char reg_str[128];
1958 ra->dump_register(node->in(idx),reg_str);
1959 st->print("%s",reg_str);
1960 }
1961}
1962#endif
1963
1964#ifndef PRODUCT
1965void rxmm11Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1966 { char reg_str[128];
1967 ra->dump_register(node,reg_str);
1968 st->print("%s",reg_str);
1969 }
1970}
1971void rxmm11Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1972 { char reg_str[128];
1973 ra->dump_register(node->in(idx),reg_str);
1974 st->print("%s",reg_str);
1975 }
1976}
1977#endif
1978
1979#ifndef PRODUCT
1980void rxmm12Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1981 { char reg_str[128];
1982 ra->dump_register(node,reg_str);
1983 st->print("%s",reg_str);
1984 }
1985}
1986void rxmm12Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
1987 { char reg_str[128];
1988 ra->dump_register(node->in(idx),reg_str);
1989 st->print("%s",reg_str);
1990 }
1991}
1992#endif
1993
1994#ifndef PRODUCT
1995void rxmm13Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
1996 { char reg_str[128];
1997 ra->dump_register(node,reg_str);
1998 st->print("%s",reg_str);
1999 }
2000}
2001void rxmm13Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2002 { char reg_str[128];
2003 ra->dump_register(node->in(idx),reg_str);
2004 st->print("%s",reg_str);
2005 }
2006}
2007#endif
2008
2009#ifndef PRODUCT
2010void rxmm14Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2011 { char reg_str[128];
2012 ra->dump_register(node,reg_str);
2013 st->print("%s",reg_str);
2014 }
2015}
2016void rxmm14Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2017 { char reg_str[128];
2018 ra->dump_register(node->in(idx),reg_str);
2019 st->print("%s",reg_str);
2020 }
2021}
2022#endif
2023
2024#ifndef PRODUCT
2025void rxmm15Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2026 { char reg_str[128];
2027 ra->dump_register(node,reg_str);
2028 st->print("%s",reg_str);
2029 }
2030}
2031void rxmm15Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2032 { char reg_str[128];
2033 ra->dump_register(node->in(idx),reg_str);
2034 st->print("%s",reg_str);
2035 }
2036}
2037#endif
2038
2039#ifndef PRODUCT
2040void rxmm16Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2041 { char reg_str[128];
2042 ra->dump_register(node,reg_str);
2043 st->print("%s",reg_str);
2044 }
2045}
2046void rxmm16Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2047 { char reg_str[128];
2048 ra->dump_register(node->in(idx),reg_str);
2049 st->print("%s",reg_str);
2050 }
2051}
2052#endif
2053
2054#ifndef PRODUCT
2055void rxmm17Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2056 { char reg_str[128];
2057 ra->dump_register(node,reg_str);
2058 st->print("%s",reg_str);
2059 }
2060}
2061void rxmm17Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2062 { char reg_str[128];
2063 ra->dump_register(node->in(idx),reg_str);
2064 st->print("%s",reg_str);
2065 }
2066}
2067#endif
2068
2069#ifndef PRODUCT
2070void rxmm18Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2071 { char reg_str[128];
2072 ra->dump_register(node,reg_str);
2073 st->print("%s",reg_str);
2074 }
2075}
2076void rxmm18Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2077 { char reg_str[128];
2078 ra->dump_register(node->in(idx),reg_str);
2079 st->print("%s",reg_str);
2080 }
2081}
2082#endif
2083
2084#ifndef PRODUCT
2085void rxmm19Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2086 { char reg_str[128];
2087 ra->dump_register(node,reg_str);
2088 st->print("%s",reg_str);
2089 }
2090}
2091void rxmm19Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2092 { char reg_str[128];
2093 ra->dump_register(node->in(idx),reg_str);
2094 st->print("%s",reg_str);
2095 }
2096}
2097#endif
2098
2099#ifndef PRODUCT
2100void rxmm20Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2101 { char reg_str[128];
2102 ra->dump_register(node,reg_str);
2103 st->print("%s",reg_str);
2104 }
2105}
2106void rxmm20Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2107 { char reg_str[128];
2108 ra->dump_register(node->in(idx),reg_str);
2109 st->print("%s",reg_str);
2110 }
2111}
2112#endif
2113
2114#ifndef PRODUCT
2115void rxmm21Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2116 { char reg_str[128];
2117 ra->dump_register(node,reg_str);
2118 st->print("%s",reg_str);
2119 }
2120}
2121void rxmm21Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2122 { char reg_str[128];
2123 ra->dump_register(node->in(idx),reg_str);
2124 st->print("%s",reg_str);
2125 }
2126}
2127#endif
2128
2129#ifndef PRODUCT
2130void rxmm22Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2131 { char reg_str[128];
2132 ra->dump_register(node,reg_str);
2133 st->print("%s",reg_str);
2134 }
2135}
2136void rxmm22Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2137 { char reg_str[128];
2138 ra->dump_register(node->in(idx),reg_str);
2139 st->print("%s",reg_str);
2140 }
2141}
2142#endif
2143
2144#ifndef PRODUCT
2145void rxmm23Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2146 { char reg_str[128];
2147 ra->dump_register(node,reg_str);
2148 st->print("%s",reg_str);
2149 }
2150}
2151void rxmm23Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2152 { char reg_str[128];
2153 ra->dump_register(node->in(idx),reg_str);
2154 st->print("%s",reg_str);
2155 }
2156}
2157#endif
2158
2159#ifndef PRODUCT
2160void rxmm24Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2161 { char reg_str[128];
2162 ra->dump_register(node,reg_str);
2163 st->print("%s",reg_str);
2164 }
2165}
2166void rxmm24Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2167 { char reg_str[128];
2168 ra->dump_register(node->in(idx),reg_str);
2169 st->print("%s",reg_str);
2170 }
2171}
2172#endif
2173
2174#ifndef PRODUCT
2175void rxmm25Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2176 { char reg_str[128];
2177 ra->dump_register(node,reg_str);
2178 st->print("%s",reg_str);
2179 }
2180}
2181void rxmm25Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2182 { char reg_str[128];
2183 ra->dump_register(node->in(idx),reg_str);
2184 st->print("%s",reg_str);
2185 }
2186}
2187#endif
2188
2189#ifndef PRODUCT
2190void rxmm26Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2191 { char reg_str[128];
2192 ra->dump_register(node,reg_str);
2193 st->print("%s",reg_str);
2194 }
2195}
2196void rxmm26Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2197 { char reg_str[128];
2198 ra->dump_register(node->in(idx),reg_str);
2199 st->print("%s",reg_str);
2200 }
2201}
2202#endif
2203
2204#ifndef PRODUCT
2205void rxmm27Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2206 { char reg_str[128];
2207 ra->dump_register(node,reg_str);
2208 st->print("%s",reg_str);
2209 }
2210}
2211void rxmm27Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2212 { char reg_str[128];
2213 ra->dump_register(node->in(idx),reg_str);
2214 st->print("%s",reg_str);
2215 }
2216}
2217#endif
2218
2219#ifndef PRODUCT
2220void rxmm28Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2221 { char reg_str[128];
2222 ra->dump_register(node,reg_str);
2223 st->print("%s",reg_str);
2224 }
2225}
2226void rxmm28Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2227 { char reg_str[128];
2228 ra->dump_register(node->in(idx),reg_str);
2229 st->print("%s",reg_str);
2230 }
2231}
2232#endif
2233
2234#ifndef PRODUCT
2235void rxmm29Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2236 { char reg_str[128];
2237 ra->dump_register(node,reg_str);
2238 st->print("%s",reg_str);
2239 }
2240}
2241void rxmm29Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2242 { char reg_str[128];
2243 ra->dump_register(node->in(idx),reg_str);
2244 st->print("%s",reg_str);
2245 }
2246}
2247#endif
2248
2249#ifndef PRODUCT
2250void rxmm30Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2251 { char reg_str[128];
2252 ra->dump_register(node,reg_str);
2253 st->print("%s",reg_str);
2254 }
2255}
2256void rxmm30Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2257 { char reg_str[128];
2258 ra->dump_register(node->in(idx),reg_str);
2259 st->print("%s",reg_str);
2260 }
2261}
2262#endif
2263
2264#ifndef PRODUCT
2265void rxmm31Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2266 { char reg_str[128];
2267 ra->dump_register(node,reg_str);
2268 st->print("%s",reg_str);
2269 }
2270}
2271void rxmm31Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2272 { char reg_str[128];
2273 ra->dump_register(node->in(idx),reg_str);
2274 st->print("%s",reg_str);
2275 }
2276}
2277#endif
2278
2279#ifndef PRODUCT
2280void vecZOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2281 { char reg_str[128];
2282 ra->dump_register(node,reg_str);
2283 st->print("%s",reg_str);
2284 }
2285}
2286void vecZOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2287 { char reg_str[128];
2288 ra->dump_register(node->in(idx),reg_str);
2289 st->print("%s",reg_str);
2290 }
2291}
2292#endif
2293
2294#ifndef PRODUCT
2295void legVecZOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2296 { char reg_str[128];
2297 ra->dump_register(node,reg_str);
2298 st->print("%s",reg_str);
2299 }
2300}
2301void legVecZOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2302 { char reg_str[128];
2303 ra->dump_register(node->in(idx),reg_str);
2304 st->print("%s",reg_str);
2305 }
2306}
2307#endif
2308
2309#ifndef PRODUCT
2310void cmpOp_vcmppdOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
2311 st->print_raw("");
2312 if( _c0 == BoolTest::eq ) st->print_raw("eq");
2313 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
2314 else if( _c0 == BoolTest::le ) st->print_raw("le");
2315 else if( _c0 == BoolTest::ge ) st->print_raw("ge");
2316 else if( _c0 == BoolTest::lt ) st->print_raw("lt");
2317 else if( _c0 == BoolTest::gt ) st->print_raw("gt");
2318 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
2319 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
2320}
2321void cmpOp_vcmppdOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const {
2322 st->print_raw("");
2323 if( _c0 == BoolTest::eq ) st->print_raw("eq");
2324 else if( _c0 == BoolTest::ne ) st->print_raw("ne");
2325 else if( _c0 == BoolTest::le ) st->print_raw("le");
2326 else if( _c0 == BoolTest::ge ) st->print_raw("ge");
2327 else if( _c0 == BoolTest::lt ) st->print_raw("lt");
2328 else if( _c0 == BoolTest::gt ) st->print_raw("gt");
2329 else if( _c0 == BoolTest::overflow ) st->print_raw("o");
2330 else if( _c0 == BoolTest::no_overflow ) st->print_raw("no");
2331}
2332#endif
2333#ifndef PRODUCT
2334void loadBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2335 // Start at oper_input_base() and count operands
2336 unsigned idx0 = 2;
2337 unsigned idx1 = 2; // mem
2338 st->print_raw("movsbl ");
2339 opnd_array(0)->int_format(ra, this, st); // dst
2340 st->print_raw(", ");
2341 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2342 st->print_raw("\t# byte");
2343 if (ra->C->alias_type(adr_type())->field() != NULL) {
2344 ciField* f = ra->C->alias_type(adr_type())->field();
2345 st->print(" ! Field: ");
2346 if (f->is_volatile())
2347 st->print("volatile ");
2348 f->holder()->name()->print_symbol_on(st);
2349 st->print(".");
2350 f->name()->print_symbol_on(st);
2351 if (f->is_constant())
2352 st->print(" (constant)");
2353 } else {
2354 if (ra->C->alias_type(adr_type())->is_volatile())
2355 st->print(" volatile!");
2356 }
2357}
2358#endif
2359#ifndef PRODUCT
2360void loadB2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2361 // Start at oper_input_base() and count operands
2362 unsigned idx0 = 2;
2363 unsigned idx1 = 2; // mem
2364 st->print_raw("movsbq ");
2365 opnd_array(0)->int_format(ra, this, st); // dst
2366 st->print_raw(", ");
2367 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2368 st->print_raw("\t# byte -> long");
2369}
2370#endif
2371#ifndef PRODUCT
2372void loadUBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2373 // Start at oper_input_base() and count operands
2374 unsigned idx0 = 2;
2375 unsigned idx1 = 2; // mem
2376 st->print_raw("movzbl ");
2377 opnd_array(0)->int_format(ra, this, st); // dst
2378 st->print_raw(", ");
2379 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2380 st->print_raw("\t# ubyte");
2381 if (ra->C->alias_type(adr_type())->field() != NULL) {
2382 ciField* f = ra->C->alias_type(adr_type())->field();
2383 st->print(" ! Field: ");
2384 if (f->is_volatile())
2385 st->print("volatile ");
2386 f->holder()->name()->print_symbol_on(st);
2387 st->print(".");
2388 f->name()->print_symbol_on(st);
2389 if (f->is_constant())
2390 st->print(" (constant)");
2391 } else {
2392 if (ra->C->alias_type(adr_type())->is_volatile())
2393 st->print(" volatile!");
2394 }
2395}
2396#endif
2397#ifndef PRODUCT
2398void loadUB2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2399 // Start at oper_input_base() and count operands
2400 unsigned idx0 = 2;
2401 unsigned idx1 = 2; // mem
2402 st->print_raw("movzbq ");
2403 opnd_array(0)->int_format(ra, this, st); // dst
2404 st->print_raw(", ");
2405 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2406 st->print_raw("\t# ubyte -> long");
2407}
2408#endif
2409#ifndef PRODUCT
2410void loadUB2L_immINode::format(PhaseRegAlloc *ra, outputStream *st) const {
2411 // Start at oper_input_base() and count operands
2412 unsigned idx0 = 2;
2413 unsigned idx1 = 2; // mem
2414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2415 st->print_raw("movzbq ");
2416 opnd_array(0)->int_format(ra, this, st); // dst
2417 st->print_raw(", ");
2418 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2419 st->print_raw("\t# ubyte & 32-bit mask -> long\n\t");
2420 st->print_raw("andl ");
2421 opnd_array(0)->int_format(ra, this, st); // dst
2422 st->print_raw(", right_n_bits(");
2423 opnd_array(2)->ext_format(ra, this,idx2, st); // mask
2424 st->print_raw(", 8)");
2425}
2426#endif
2427#ifndef PRODUCT
2428void loadSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2429 // Start at oper_input_base() and count operands
2430 unsigned idx0 = 2;
2431 unsigned idx1 = 2; // mem
2432 st->print_raw("movswl ");
2433 opnd_array(0)->int_format(ra, this, st); // dst
2434 st->print_raw(", ");
2435 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2436 st->print_raw("\t# short");
2437 if (ra->C->alias_type(adr_type())->field() != NULL) {
2438 ciField* f = ra->C->alias_type(adr_type())->field();
2439 st->print(" ! Field: ");
2440 if (f->is_volatile())
2441 st->print("volatile ");
2442 f->holder()->name()->print_symbol_on(st);
2443 st->print(".");
2444 f->name()->print_symbol_on(st);
2445 if (f->is_constant())
2446 st->print(" (constant)");
2447 } else {
2448 if (ra->C->alias_type(adr_type())->is_volatile())
2449 st->print(" volatile!");
2450 }
2451}
2452#endif
2453#ifndef PRODUCT
2454void loadS2BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2455 // Start at oper_input_base() and count operands
2456 unsigned idx0 = 2;
2457 unsigned idx1 = 2; // mem
2458 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
2459 st->print_raw("movsbl ");
2460 opnd_array(0)->int_format(ra, this, st); // dst
2461 st->print_raw(", ");
2462 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2463 st->print_raw("\t# short -> byte");
2464}
2465#endif
2466#ifndef PRODUCT
2467void loadS2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2468 // Start at oper_input_base() and count operands
2469 unsigned idx0 = 2;
2470 unsigned idx1 = 2; // mem
2471 st->print_raw("movswq ");
2472 opnd_array(0)->int_format(ra, this, st); // dst
2473 st->print_raw(", ");
2474 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2475 st->print_raw("\t# short -> long");
2476}
2477#endif
2478#ifndef PRODUCT
2479void loadUSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2480 // Start at oper_input_base() and count operands
2481 unsigned idx0 = 2;
2482 unsigned idx1 = 2; // mem
2483 st->print_raw("movzwl ");
2484 opnd_array(0)->int_format(ra, this, st); // dst
2485 st->print_raw(", ");
2486 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2487 st->print_raw("\t# ushort/char");
2488 if (ra->C->alias_type(adr_type())->field() != NULL) {
2489 ciField* f = ra->C->alias_type(adr_type())->field();
2490 st->print(" ! Field: ");
2491 if (f->is_volatile())
2492 st->print("volatile ");
2493 f->holder()->name()->print_symbol_on(st);
2494 st->print(".");
2495 f->name()->print_symbol_on(st);
2496 if (f->is_constant())
2497 st->print(" (constant)");
2498 } else {
2499 if (ra->C->alias_type(adr_type())->is_volatile())
2500 st->print(" volatile!");
2501 }
2502}
2503#endif
2504#ifndef PRODUCT
2505void loadUS2BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2506 // Start at oper_input_base() and count operands
2507 unsigned idx0 = 2;
2508 unsigned idx1 = 2; // mem
2509 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
2510 st->print_raw("movsbl ");
2511 opnd_array(0)->int_format(ra, this, st); // dst
2512 st->print_raw(", ");
2513 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2514 st->print_raw("\t# ushort -> byte");
2515}
2516#endif
2517#ifndef PRODUCT
2518void loadUS2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2519 // Start at oper_input_base() and count operands
2520 unsigned idx0 = 2;
2521 unsigned idx1 = 2; // mem
2522 st->print_raw("movzwq ");
2523 opnd_array(0)->int_format(ra, this, st); // dst
2524 st->print_raw(", ");
2525 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2526 st->print_raw("\t# ushort/char -> long");
2527}
2528#endif
2529#ifndef PRODUCT
2530void loadUS2L_immI_255Node::format(PhaseRegAlloc *ra, outputStream *st) const {
2531 // Start at oper_input_base() and count operands
2532 unsigned idx0 = 2;
2533 unsigned idx1 = 2; // mem
2534 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2535 st->print_raw("movzbq ");
2536 opnd_array(0)->int_format(ra, this, st); // dst
2537 st->print_raw(", ");
2538 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2539 st->print_raw("\t# ushort/char & 0xFF -> long");
2540}
2541#endif
2542#ifndef PRODUCT
2543void loadUS2L_immINode::format(PhaseRegAlloc *ra, outputStream *st) const {
2544 // Start at oper_input_base() and count operands
2545 unsigned idx0 = 2;
2546 unsigned idx1 = 2; // mem
2547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2548 st->print_raw("movzwq ");
2549 opnd_array(0)->int_format(ra, this, st); // dst
2550 st->print_raw(", ");
2551 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2552 st->print_raw("\t# ushort/char & 32-bit mask -> long\n\t");
2553 st->print_raw("andl ");
2554 opnd_array(0)->int_format(ra, this, st); // dst
2555 st->print_raw(", right_n_bits(");
2556 opnd_array(2)->ext_format(ra, this,idx2, st); // mask
2557 st->print_raw(", 16)");
2558}
2559#endif
2560#ifndef PRODUCT
2561void loadINode::format(PhaseRegAlloc *ra, outputStream *st) const {
2562 // Start at oper_input_base() and count operands
2563 unsigned idx0 = 2;
2564 unsigned idx1 = 2; // mem
2565 st->print_raw("movl ");
2566 opnd_array(0)->int_format(ra, this, st); // dst
2567 st->print_raw(", ");
2568 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2569 st->print_raw("\t# int");
2570 if (ra->C->alias_type(adr_type())->field() != NULL) {
2571 ciField* f = ra->C->alias_type(adr_type())->field();
2572 st->print(" ! Field: ");
2573 if (f->is_volatile())
2574 st->print("volatile ");
2575 f->holder()->name()->print_symbol_on(st);
2576 st->print(".");
2577 f->name()->print_symbol_on(st);
2578 if (f->is_constant())
2579 st->print(" (constant)");
2580 } else {
2581 if (ra->C->alias_type(adr_type())->is_volatile())
2582 st->print(" volatile!");
2583 }
2584}
2585#endif
2586#ifndef PRODUCT
2587void loadI2BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2588 // Start at oper_input_base() and count operands
2589 unsigned idx0 = 2;
2590 unsigned idx1 = 2; // mem
2591 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
2592 st->print_raw("movsbl ");
2593 opnd_array(0)->int_format(ra, this, st); // dst
2594 st->print_raw(", ");
2595 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2596 st->print_raw("\t# int -> byte");
2597}
2598#endif
2599#ifndef PRODUCT
2600void loadI2UBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2601 // Start at oper_input_base() and count operands
2602 unsigned idx0 = 2;
2603 unsigned idx1 = 2; // mem
2604 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2605 st->print_raw("movzbl ");
2606 opnd_array(0)->int_format(ra, this, st); // dst
2607 st->print_raw(", ");
2608 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2609 st->print_raw("\t# int -> ubyte");
2610}
2611#endif
2612#ifndef PRODUCT
2613void loadI2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2614 // Start at oper_input_base() and count operands
2615 unsigned idx0 = 2;
2616 unsigned idx1 = 2; // mem
2617 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
2618 st->print_raw("movswl ");
2619 opnd_array(0)->int_format(ra, this, st); // dst
2620 st->print_raw(", ");
2621 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2622 st->print_raw("\t# int -> short");
2623}
2624#endif
2625#ifndef PRODUCT
2626void loadI2USNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2627 // Start at oper_input_base() and count operands
2628 unsigned idx0 = 2;
2629 unsigned idx1 = 2; // mem
2630 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2631 st->print_raw("movzwl ");
2632 opnd_array(0)->int_format(ra, this, st); // dst
2633 st->print_raw(", ");
2634 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2635 st->print_raw("\t# int -> ushort/char");
2636}
2637#endif
2638#ifndef PRODUCT
2639void loadI2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2640 // Start at oper_input_base() and count operands
2641 unsigned idx0 = 2;
2642 unsigned idx1 = 2; // mem
2643 st->print_raw("movslq ");
2644 opnd_array(0)->int_format(ra, this, st); // dst
2645 st->print_raw(", ");
2646 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2647 st->print_raw("\t# int -> long");
2648}
2649#endif
2650#ifndef PRODUCT
2651void loadI2L_immI_255Node::format(PhaseRegAlloc *ra, outputStream *st) const {
2652 // Start at oper_input_base() and count operands
2653 unsigned idx0 = 2;
2654 unsigned idx1 = 2; // mem
2655 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2656 st->print_raw("movzbq ");
2657 opnd_array(0)->int_format(ra, this, st); // dst
2658 st->print_raw(", ");
2659 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2660 st->print_raw("\t# int & 0xFF -> long");
2661}
2662#endif
2663#ifndef PRODUCT
2664void loadI2L_immI_65535Node::format(PhaseRegAlloc *ra, outputStream *st) const {
2665 // Start at oper_input_base() and count operands
2666 unsigned idx0 = 2;
2667 unsigned idx1 = 2; // mem
2668 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2669 st->print_raw("movzwq ");
2670 opnd_array(0)->int_format(ra, this, st); // dst
2671 st->print_raw(", ");
2672 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2673 st->print_raw("\t# int & 0xFFFF -> long");
2674}
2675#endif
2676#ifndef PRODUCT
2677void loadI2L_immU31Node::format(PhaseRegAlloc *ra, outputStream *st) const {
2678 // Start at oper_input_base() and count operands
2679 unsigned idx0 = 2;
2680 unsigned idx1 = 2; // mem
2681 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2682 st->print_raw("movl ");
2683 opnd_array(0)->int_format(ra, this, st); // dst
2684 st->print_raw(", ");
2685 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2686 st->print_raw("\t# int & 31-bit mask -> long\n\t");
2687 st->print_raw("andl ");
2688 opnd_array(0)->int_format(ra, this, st); // dst
2689 st->print_raw(", ");
2690 opnd_array(2)->ext_format(ra, this,idx2, st); // mask
2691}
2692#endif
2693#ifndef PRODUCT
2694void loadUI2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2695 // Start at oper_input_base() and count operands
2696 unsigned idx0 = 2;
2697 unsigned idx1 = 2; // mem
2698 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
2699 st->print_raw("movl ");
2700 opnd_array(0)->int_format(ra, this, st); // dst
2701 st->print_raw(", ");
2702 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2703 st->print_raw("\t# uint -> long");
2704}
2705#endif
2706#ifndef PRODUCT
2707void loadLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2708 // Start at oper_input_base() and count operands
2709 unsigned idx0 = 2;
2710 unsigned idx1 = 2; // mem
2711 st->print_raw("movq ");
2712 opnd_array(0)->int_format(ra, this, st); // dst
2713 st->print_raw(", ");
2714 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2715 st->print_raw("\t# long");
2716 if (ra->C->alias_type(adr_type())->field() != NULL) {
2717 ciField* f = ra->C->alias_type(adr_type())->field();
2718 st->print(" ! Field: ");
2719 if (f->is_volatile())
2720 st->print("volatile ");
2721 f->holder()->name()->print_symbol_on(st);
2722 st->print(".");
2723 f->name()->print_symbol_on(st);
2724 if (f->is_constant())
2725 st->print(" (constant)");
2726 } else {
2727 if (ra->C->alias_type(adr_type())->is_volatile())
2728 st->print(" volatile!");
2729 }
2730}
2731#endif
2732#ifndef PRODUCT
2733void loadRangeNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2734 // Start at oper_input_base() and count operands
2735 unsigned idx0 = 2;
2736 unsigned idx1 = 2; // mem
2737 st->print_raw("movl ");
2738 opnd_array(0)->int_format(ra, this, st); // dst
2739 st->print_raw(", ");
2740 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2741 st->print_raw("\t# range");
2742 if (ra->C->alias_type(adr_type())->field() != NULL) {
2743 ciField* f = ra->C->alias_type(adr_type())->field();
2744 st->print(" ! Field: ");
2745 if (f->is_volatile())
2746 st->print("volatile ");
2747 f->holder()->name()->print_symbol_on(st);
2748 st->print(".");
2749 f->name()->print_symbol_on(st);
2750 if (f->is_constant())
2751 st->print(" (constant)");
2752 } else {
2753 if (ra->C->alias_type(adr_type())->is_volatile())
2754 st->print(" volatile!");
2755 }
2756}
2757#endif
2758#ifndef PRODUCT
2759void loadPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2760 // Start at oper_input_base() and count operands
2761 unsigned idx0 = 2;
2762 unsigned idx1 = 2; // mem
2763 st->print_raw("movq ");
2764 opnd_array(0)->int_format(ra, this, st); // dst
2765 st->print_raw(", ");
2766 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2767 st->print_raw("\t# ptr");
2768 if (ra->C->alias_type(adr_type())->field() != NULL) {
2769 ciField* f = ra->C->alias_type(adr_type())->field();
2770 st->print(" ! Field: ");
2771 if (f->is_volatile())
2772 st->print("volatile ");
2773 f->holder()->name()->print_symbol_on(st);
2774 st->print(".");
2775 f->name()->print_symbol_on(st);
2776 if (f->is_constant())
2777 st->print(" (constant)");
2778 } else {
2779 if (ra->C->alias_type(adr_type())->is_volatile())
2780 st->print(" volatile!");
2781 }
2782}
2783#endif
2784#ifndef PRODUCT
2785void loadNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2786 // Start at oper_input_base() and count operands
2787 unsigned idx0 = 2;
2788 unsigned idx1 = 2; // mem
2789 st->print_raw("movl ");
2790 opnd_array(0)->int_format(ra, this, st); // dst
2791 st->print_raw(", ");
2792 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2793 st->print_raw("\t# compressed ptr");
2794 if (ra->C->alias_type(adr_type())->field() != NULL) {
2795 ciField* f = ra->C->alias_type(adr_type())->field();
2796 st->print(" ! Field: ");
2797 if (f->is_volatile())
2798 st->print("volatile ");
2799 f->holder()->name()->print_symbol_on(st);
2800 st->print(".");
2801 f->name()->print_symbol_on(st);
2802 if (f->is_constant())
2803 st->print(" (constant)");
2804 } else {
2805 if (ra->C->alias_type(adr_type())->is_volatile())
2806 st->print(" volatile!");
2807 }
2808}
2809#endif
2810#ifndef PRODUCT
2811void loadKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2812 // Start at oper_input_base() and count operands
2813 unsigned idx0 = 2;
2814 unsigned idx1 = 2; // mem
2815 st->print_raw("movq ");
2816 opnd_array(0)->int_format(ra, this, st); // dst
2817 st->print_raw(", ");
2818 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2819 st->print_raw("\t# class");
2820 if (ra->C->alias_type(adr_type())->field() != NULL) {
2821 ciField* f = ra->C->alias_type(adr_type())->field();
2822 st->print(" ! Field: ");
2823 if (f->is_volatile())
2824 st->print("volatile ");
2825 f->holder()->name()->print_symbol_on(st);
2826 st->print(".");
2827 f->name()->print_symbol_on(st);
2828 if (f->is_constant())
2829 st->print(" (constant)");
2830 } else {
2831 if (ra->C->alias_type(adr_type())->is_volatile())
2832 st->print(" volatile!");
2833 }
2834}
2835#endif
2836#ifndef PRODUCT
2837void loadNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2838 // Start at oper_input_base() and count operands
2839 unsigned idx0 = 2;
2840 unsigned idx1 = 2; // mem
2841 st->print_raw("movl ");
2842 opnd_array(0)->int_format(ra, this, st); // dst
2843 st->print_raw(", ");
2844 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2845 st->print_raw("\t# compressed klass ptr");
2846 if (ra->C->alias_type(adr_type())->field() != NULL) {
2847 ciField* f = ra->C->alias_type(adr_type())->field();
2848 st->print(" ! Field: ");
2849 if (f->is_volatile())
2850 st->print("volatile ");
2851 f->holder()->name()->print_symbol_on(st);
2852 st->print(".");
2853 f->name()->print_symbol_on(st);
2854 if (f->is_constant())
2855 st->print(" (constant)");
2856 } else {
2857 if (ra->C->alias_type(adr_type())->is_volatile())
2858 st->print(" volatile!");
2859 }
2860}
2861#endif
2862#ifndef PRODUCT
2863void loadFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2864 // Start at oper_input_base() and count operands
2865 unsigned idx0 = 2;
2866 unsigned idx1 = 2; // mem
2867 st->print_raw("movss ");
2868 opnd_array(0)->int_format(ra, this, st); // dst
2869 st->print_raw(", ");
2870 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2871 st->print_raw("\t# float");
2872 if (ra->C->alias_type(adr_type())->field() != NULL) {
2873 ciField* f = ra->C->alias_type(adr_type())->field();
2874 st->print(" ! Field: ");
2875 if (f->is_volatile())
2876 st->print("volatile ");
2877 f->holder()->name()->print_symbol_on(st);
2878 st->print(".");
2879 f->name()->print_symbol_on(st);
2880 if (f->is_constant())
2881 st->print(" (constant)");
2882 } else {
2883 if (ra->C->alias_type(adr_type())->is_volatile())
2884 st->print(" volatile!");
2885 }
2886}
2887#endif
2888#ifndef PRODUCT
2889void MoveF2VLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2890 // Start at oper_input_base() and count operands
2891 unsigned idx0 = 1;
2892 unsigned idx1 = 1; // src
2893 st->print_raw("movss ");
2894 opnd_array(0)->int_format(ra, this, st); // dst
2895 st->print_raw(",");
2896 opnd_array(1)->ext_format(ra, this,idx1, st); // src
2897 st->print_raw("\t! load float (4 bytes)");
2898}
2899#endif
2900#ifndef PRODUCT
2901void MoveF2LEGNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2902 // Start at oper_input_base() and count operands
2903 unsigned idx0 = 1;
2904 unsigned idx1 = 1; // src
2905 st->print_raw("movss ");
2906 opnd_array(0)->int_format(ra, this, st); // dst
2907 st->print_raw(",");
2908 opnd_array(1)->ext_format(ra, this,idx1, st); // src
2909 st->print_raw("\t# if src != dst load float (4 bytes)");
2910}
2911#endif
2912#ifndef PRODUCT
2913void MoveVL2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2914 // Start at oper_input_base() and count operands
2915 unsigned idx0 = 1;
2916 unsigned idx1 = 1; // src
2917 st->print_raw("movss ");
2918 opnd_array(0)->int_format(ra, this, st); // dst
2919 st->print_raw(",");
2920 opnd_array(1)->ext_format(ra, this,idx1, st); // src
2921 st->print_raw("\t! load float (4 bytes)");
2922}
2923#endif
2924#ifndef PRODUCT
2925void MoveLEG2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2926 // Start at oper_input_base() and count operands
2927 unsigned idx0 = 1;
2928 unsigned idx1 = 1; // src
2929 st->print_raw("movss ");
2930 opnd_array(0)->int_format(ra, this, st); // dst
2931 st->print_raw(",");
2932 opnd_array(1)->ext_format(ra, this,idx1, st); // src
2933 st->print_raw("\t# if src != dst load float (4 bytes)");
2934}
2935#endif
2936#ifndef PRODUCT
2937void loadD_partialNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2938 // Start at oper_input_base() and count operands
2939 unsigned idx0 = 2;
2940 unsigned idx1 = 2; // mem
2941 st->print_raw("movlpd ");
2942 opnd_array(0)->int_format(ra, this, st); // dst
2943 st->print_raw(", ");
2944 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2945 st->print_raw("\t# double");
2946 if (ra->C->alias_type(adr_type())->field() != NULL) {
2947 ciField* f = ra->C->alias_type(adr_type())->field();
2948 st->print(" ! Field: ");
2949 if (f->is_volatile())
2950 st->print("volatile ");
2951 f->holder()->name()->print_symbol_on(st);
2952 st->print(".");
2953 f->name()->print_symbol_on(st);
2954 if (f->is_constant())
2955 st->print(" (constant)");
2956 } else {
2957 if (ra->C->alias_type(adr_type())->is_volatile())
2958 st->print(" volatile!");
2959 }
2960}
2961#endif
2962#ifndef PRODUCT
2963void loadDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2964 // Start at oper_input_base() and count operands
2965 unsigned idx0 = 2;
2966 unsigned idx1 = 2; // mem
2967 st->print_raw("movsd ");
2968 opnd_array(0)->int_format(ra, this, st); // dst
2969 st->print_raw(", ");
2970 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
2971 st->print_raw("\t# double");
2972 if (ra->C->alias_type(adr_type())->field() != NULL) {
2973 ciField* f = ra->C->alias_type(adr_type())->field();
2974 st->print(" ! Field: ");
2975 if (f->is_volatile())
2976 st->print("volatile ");
2977 f->holder()->name()->print_symbol_on(st);
2978 st->print(".");
2979 f->name()->print_symbol_on(st);
2980 if (f->is_constant())
2981 st->print(" (constant)");
2982 } else {
2983 if (ra->C->alias_type(adr_type())->is_volatile())
2984 st->print(" volatile!");
2985 }
2986}
2987#endif
2988#ifndef PRODUCT
2989void MoveD2VLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
2990 // Start at oper_input_base() and count operands
2991 unsigned idx0 = 1;
2992 unsigned idx1 = 1; // src
2993 st->print_raw("movsd ");
2994 opnd_array(0)->int_format(ra, this, st); // dst
2995 st->print_raw(",");
2996 opnd_array(1)->ext_format(ra, this,idx1, st); // src
2997 st->print_raw("\t! load double (8 bytes)");
2998}
2999#endif
3000#ifndef PRODUCT
3001void MoveD2LEGNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3002 // Start at oper_input_base() and count operands
3003 unsigned idx0 = 1;
3004 unsigned idx1 = 1; // src
3005 st->print_raw("movsd ");
3006 opnd_array(0)->int_format(ra, this, st); // dst
3007 st->print_raw(",");
3008 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3009 st->print_raw("\t# if src != dst load double (8 bytes)");
3010}
3011#endif
3012#ifndef PRODUCT
3013void MoveVL2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3014 // Start at oper_input_base() and count operands
3015 unsigned idx0 = 1;
3016 unsigned idx1 = 1; // src
3017 st->print_raw("movsd ");
3018 opnd_array(0)->int_format(ra, this, st); // dst
3019 st->print_raw(",");
3020 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3021 st->print_raw("\t! load double (8 bytes)");
3022}
3023#endif
3024#ifndef PRODUCT
3025void MoveLEG2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3026 // Start at oper_input_base() and count operands
3027 unsigned idx0 = 1;
3028 unsigned idx1 = 1; // src
3029 st->print_raw("movsd ");
3030 opnd_array(0)->int_format(ra, this, st); // dst
3031 st->print_raw(",");
3032 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3033 st->print_raw("\t# if src != dst load double (8 bytes)");
3034}
3035#endif
3036#ifndef PRODUCT
3037void maxF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3038 // Start at oper_input_base() and count operands
3039 unsigned idx0 = 1;
3040 unsigned idx1 = 1; // a
3041 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3042 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
3043 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
3044 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
3045 st->print_raw("blendvps ");
3046 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3047 st->print_raw(",");
3048 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3049 st->print_raw(",");
3050 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3051 st->print_raw(",");
3052 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3053 st->print_raw(" \n\t");
3054 st->print_raw("blendvps ");
3055 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3056 st->print_raw(",");
3057 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3058 st->print_raw(",");
3059 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3060 st->print_raw(",");
3061 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3062 st->print_raw(" \n\t");
3063 st->print_raw("vmaxss ");
3064 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3065 st->print_raw(",");
3066 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3067 st->print_raw(",");
3068 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3069 st->print_raw(" \n\t");
3070 st->print_raw("cmpps.unordered ");
3071 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3072 st->print_raw(",");
3073 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3074 st->print_raw(",");
3075 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3076 st->print_raw(" \n\t");
3077 st->print_raw("blendvps ");
3078 opnd_array(0)->int_format(ra, this, st); // dst
3079 st->print_raw(",");
3080 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3081 st->print_raw(",");
3082 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3083 st->print_raw(",");
3084 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3085 st->print_raw(" \n\t");
3086}
3087#endif
3088#ifndef PRODUCT
3089void maxF_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3090 // Start at oper_input_base() and count operands
3091 unsigned idx0 = 1;
3092 unsigned idx1 = 1; // a
3093 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3094 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
3095 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
3096 opnd_array(0)->int_format(ra, this, st); // dst
3097 st->print_raw(" = max(");
3098 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3099 st->print_raw(", ");
3100 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3101 st->print_raw(")\t# intrinsic (float)");
3102}
3103#endif
3104#ifndef PRODUCT
3105void maxD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3106 // Start at oper_input_base() and count operands
3107 unsigned idx0 = 1;
3108 unsigned idx1 = 1; // a
3109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3110 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
3111 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
3112 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
3113 st->print_raw("blendvpd ");
3114 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3115 st->print_raw(",");
3116 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3117 st->print_raw(",");
3118 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3119 st->print_raw(",");
3120 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3121 st->print_raw(" \n\t");
3122 st->print_raw("blendvpd ");
3123 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3124 st->print_raw(",");
3125 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3126 st->print_raw(",");
3127 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3128 st->print_raw(",");
3129 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3130 st->print_raw(" \n\t");
3131 st->print_raw("vmaxsd ");
3132 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3133 st->print_raw(",");
3134 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3135 st->print_raw(",");
3136 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3137 st->print_raw(" \n\t");
3138 st->print_raw("cmppd.unordered ");
3139 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3140 st->print_raw(",");
3141 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3142 st->print_raw(",");
3143 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3144 st->print_raw(" \n\t");
3145 st->print_raw("blendvpd ");
3146 opnd_array(0)->int_format(ra, this, st); // dst
3147 st->print_raw(",");
3148 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3149 st->print_raw(",");
3150 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3151 st->print_raw(",");
3152 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3153 st->print_raw(" \n\t");
3154}
3155#endif
3156#ifndef PRODUCT
3157void maxD_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3158 // Start at oper_input_base() and count operands
3159 unsigned idx0 = 1;
3160 unsigned idx1 = 1; // a
3161 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3162 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
3163 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
3164 opnd_array(0)->int_format(ra, this, st); // dst
3165 st->print_raw(" = max(");
3166 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3167 st->print_raw(", ");
3168 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3169 st->print_raw(")\t# intrinsic (double)");
3170}
3171#endif
3172#ifndef PRODUCT
3173void minF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3174 // Start at oper_input_base() and count operands
3175 unsigned idx0 = 1;
3176 unsigned idx1 = 1; // a
3177 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3178 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
3179 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
3180 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
3181 st->print_raw("blendvps ");
3182 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3183 st->print_raw(",");
3184 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3185 st->print_raw(",");
3186 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3187 st->print_raw(",");
3188 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3189 st->print_raw(" \n\t");
3190 st->print_raw("blendvps ");
3191 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3192 st->print_raw(",");
3193 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3194 st->print_raw(",");
3195 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3196 st->print_raw(",");
3197 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3198 st->print_raw(" \n\t");
3199 st->print_raw("vminss ");
3200 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3201 st->print_raw(",");
3202 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3203 st->print_raw(",");
3204 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3205 st->print_raw(" \n\t");
3206 st->print_raw("cmpps.unordered ");
3207 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3208 st->print_raw(",");
3209 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3210 st->print_raw(",");
3211 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3212 st->print_raw(" \n\t");
3213 st->print_raw("blendvps ");
3214 opnd_array(0)->int_format(ra, this, st); // dst
3215 st->print_raw(",");
3216 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3217 st->print_raw(",");
3218 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3219 st->print_raw(",");
3220 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3221 st->print_raw(" \n\t");
3222}
3223#endif
3224#ifndef PRODUCT
3225void minF_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3226 // Start at oper_input_base() and count operands
3227 unsigned idx0 = 1;
3228 unsigned idx1 = 1; // a
3229 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3230 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
3231 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
3232 opnd_array(0)->int_format(ra, this, st); // dst
3233 st->print_raw(" = min(");
3234 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3235 st->print_raw(", ");
3236 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3237 st->print_raw(")\t# intrinsic (float)");
3238}
3239#endif
3240#ifndef PRODUCT
3241void minD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3242 // Start at oper_input_base() and count operands
3243 unsigned idx0 = 1;
3244 unsigned idx1 = 1; // a
3245 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3246 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
3247 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
3248 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
3249 st->print_raw("blendvpd ");
3250 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3251 st->print_raw(",");
3252 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3253 st->print_raw(",");
3254 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3255 st->print_raw(",");
3256 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3257 st->print_raw(" \n\t");
3258 st->print_raw("blendvpd ");
3259 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3260 st->print_raw(",");
3261 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3262 st->print_raw(",");
3263 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3264 st->print_raw(",");
3265 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3266 st->print_raw(" \n\t");
3267 st->print_raw("vminsd ");
3268 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3269 st->print_raw(",");
3270 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3271 st->print_raw(",");
3272 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3273 st->print_raw(" \n\t");
3274 st->print_raw("cmppd.unordered ");
3275 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3276 st->print_raw(",");
3277 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3278 st->print_raw(",");
3279 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3280 st->print_raw(" \n\t");
3281 st->print_raw("blendvpd ");
3282 opnd_array(0)->int_format(ra, this, st); // dst
3283 st->print_raw(",");
3284 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
3285 st->print_raw(",");
3286 opnd_array(4)->ext_format(ra, this,idx4, st); // atmp
3287 st->print_raw(",");
3288 opnd_array(5)->ext_format(ra, this,idx5, st); // btmp
3289 st->print_raw(" \n\t");
3290}
3291#endif
3292#ifndef PRODUCT
3293void minD_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3294 // Start at oper_input_base() and count operands
3295 unsigned idx0 = 1;
3296 unsigned idx1 = 1; // a
3297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
3298 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
3299 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
3300 opnd_array(0)->int_format(ra, this, st); // dst
3301 st->print_raw(" = min(");
3302 opnd_array(1)->ext_format(ra, this,idx1, st); // a
3303 st->print_raw(", ");
3304 opnd_array(2)->ext_format(ra, this,idx2, st); // b
3305 st->print_raw(")\t# intrinsic (double)");
3306}
3307#endif
3308#ifndef PRODUCT
3309void leaP8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3310 // Start at oper_input_base() and count operands
3311 unsigned idx0 = 2;
3312 unsigned idx1 = 2; // mem
3313 st->print_raw("leaq ");
3314 opnd_array(0)->int_format(ra, this, st); // dst
3315 st->print_raw(", ");
3316 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3317 st->print_raw("\t# ptr 8");
3318}
3319#endif
3320#ifndef PRODUCT
3321void leaP32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3322 // Start at oper_input_base() and count operands
3323 unsigned idx0 = 2;
3324 unsigned idx1 = 2; // mem
3325 st->print_raw("leaq ");
3326 opnd_array(0)->int_format(ra, this, st); // dst
3327 st->print_raw(", ");
3328 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3329 st->print_raw("\t# ptr 32");
3330}
3331#endif
3332#ifndef PRODUCT
3333void leaPIdxOffNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3334 // Start at oper_input_base() and count operands
3335 unsigned idx0 = 2;
3336 unsigned idx1 = 2; // mem
3337 st->print_raw("leaq ");
3338 opnd_array(0)->int_format(ra, this, st); // dst
3339 st->print_raw(", ");
3340 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3341 st->print_raw("\t# ptr idxoff");
3342}
3343#endif
3344#ifndef PRODUCT
3345void leaPIdxScaleNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3346 // Start at oper_input_base() and count operands
3347 unsigned idx0 = 2;
3348 unsigned idx1 = 2; // mem
3349 st->print_raw("leaq ");
3350 opnd_array(0)->int_format(ra, this, st); // dst
3351 st->print_raw(", ");
3352 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3353 st->print_raw("\t# ptr idxscale");
3354}
3355#endif
3356#ifndef PRODUCT
3357void leaPPosIdxScaleNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3358 // Start at oper_input_base() and count operands
3359 unsigned idx0 = 2;
3360 unsigned idx1 = 2; // mem
3361 st->print_raw("leaq ");
3362 opnd_array(0)->int_format(ra, this, st); // dst
3363 st->print_raw(", ");
3364 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3365 st->print_raw("\t# ptr idxscale");
3366}
3367#endif
3368#ifndef PRODUCT
3369void leaPIdxScaleOffNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3370 // Start at oper_input_base() and count operands
3371 unsigned idx0 = 2;
3372 unsigned idx1 = 2; // mem
3373 st->print_raw("leaq ");
3374 opnd_array(0)->int_format(ra, this, st); // dst
3375 st->print_raw(", ");
3376 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3377 st->print_raw("\t# ptr idxscaleoff");
3378}
3379#endif
3380#ifndef PRODUCT
3381void leaPPosIdxOffNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3382 // Start at oper_input_base() and count operands
3383 unsigned idx0 = 2;
3384 unsigned idx1 = 2; // mem
3385 st->print_raw("leaq ");
3386 opnd_array(0)->int_format(ra, this, st); // dst
3387 st->print_raw(", ");
3388 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3389 st->print_raw("\t# ptr posidxoff");
3390}
3391#endif
3392#ifndef PRODUCT
3393void leaPPosIdxScaleOffNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3394 // Start at oper_input_base() and count operands
3395 unsigned idx0 = 2;
3396 unsigned idx1 = 2; // mem
3397 st->print_raw("leaq ");
3398 opnd_array(0)->int_format(ra, this, st); // dst
3399 st->print_raw(", ");
3400 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3401 st->print_raw("\t# ptr posidxscaleoff");
3402}
3403#endif
3404#ifndef PRODUCT
3405void leaPCompressedOopOffsetNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3406 // Start at oper_input_base() and count operands
3407 unsigned idx0 = 2;
3408 unsigned idx1 = 2; // mem
3409 st->print_raw("leaq ");
3410 opnd_array(0)->int_format(ra, this, st); // dst
3411 st->print_raw(", ");
3412 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3413 st->print_raw("\t# ptr compressedoopoff32");
3414}
3415#endif
3416#ifndef PRODUCT
3417void leaP8NarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3418 // Start at oper_input_base() and count operands
3419 unsigned idx0 = 2;
3420 unsigned idx1 = 2; // mem
3421 st->print_raw("leaq ");
3422 opnd_array(0)->int_format(ra, this, st); // dst
3423 st->print_raw(", ");
3424 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3425 st->print_raw("\t# ptr off8narrow");
3426}
3427#endif
3428#ifndef PRODUCT
3429void leaP32NarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3430 // Start at oper_input_base() and count operands
3431 unsigned idx0 = 2;
3432 unsigned idx1 = 2; // mem
3433 st->print_raw("leaq ");
3434 opnd_array(0)->int_format(ra, this, st); // dst
3435 st->print_raw(", ");
3436 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3437 st->print_raw("\t# ptr off32narrow");
3438}
3439#endif
3440#ifndef PRODUCT
3441void leaPIdxOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3442 // Start at oper_input_base() and count operands
3443 unsigned idx0 = 2;
3444 unsigned idx1 = 2; // mem
3445 st->print_raw("leaq ");
3446 opnd_array(0)->int_format(ra, this, st); // dst
3447 st->print_raw(", ");
3448 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3449 st->print_raw("\t# ptr idxoffnarrow");
3450}
3451#endif
3452#ifndef PRODUCT
3453void leaPIdxScaleNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3454 // Start at oper_input_base() and count operands
3455 unsigned idx0 = 2;
3456 unsigned idx1 = 2; // mem
3457 st->print_raw("leaq ");
3458 opnd_array(0)->int_format(ra, this, st); // dst
3459 st->print_raw(", ");
3460 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3461 st->print_raw("\t# ptr idxscalenarrow");
3462}
3463#endif
3464#ifndef PRODUCT
3465void leaPIdxScaleOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3466 // Start at oper_input_base() and count operands
3467 unsigned idx0 = 2;
3468 unsigned idx1 = 2; // mem
3469 st->print_raw("leaq ");
3470 opnd_array(0)->int_format(ra, this, st); // dst
3471 st->print_raw(", ");
3472 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3473 st->print_raw("\t# ptr idxscaleoffnarrow");
3474}
3475#endif
3476#ifndef PRODUCT
3477void leaPPosIdxOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3478 // Start at oper_input_base() and count operands
3479 unsigned idx0 = 2;
3480 unsigned idx1 = 2; // mem
3481 st->print_raw("leaq ");
3482 opnd_array(0)->int_format(ra, this, st); // dst
3483 st->print_raw(", ");
3484 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3485 st->print_raw("\t# ptr posidxoffnarrow");
3486}
3487#endif
3488#ifndef PRODUCT
3489void leaPPosIdxScaleOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3490 // Start at oper_input_base() and count operands
3491 unsigned idx0 = 2;
3492 unsigned idx1 = 2; // mem
3493 st->print_raw("leaq ");
3494 opnd_array(0)->int_format(ra, this, st); // dst
3495 st->print_raw(", ");
3496 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3497 st->print_raw("\t# ptr posidxscaleoffnarrow");
3498}
3499#endif
3500#ifndef PRODUCT
3501void loadConINode::format(PhaseRegAlloc *ra, outputStream *st) const {
3502 // Start at oper_input_base() and count operands
3503 unsigned idx0 = 1;
3504 unsigned idx1 = 1; // src
3505 st->print_raw("movl ");
3506 opnd_array(0)->int_format(ra, this, st); // dst
3507 st->print_raw(", ");
3508 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3509 st->print_raw("\t# int");
3510}
3511#endif
3512#ifndef PRODUCT
3513void loadConI0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3514 // Start at oper_input_base() and count operands
3515 unsigned idx0 = 1;
3516 unsigned idx1 = 1; // src
3517 st->print_raw("xorl ");
3518 opnd_array(0)->int_format(ra, this, st); // dst
3519 st->print_raw(", ");
3520 opnd_array(0)->int_format(ra, this, st); // dst
3521 st->print_raw("\t# int");
3522}
3523#endif
3524#ifndef PRODUCT
3525void loadConLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3526 // Start at oper_input_base() and count operands
3527 unsigned idx0 = 1;
3528 unsigned idx1 = 1; // src
3529 st->print_raw("movq ");
3530 opnd_array(0)->int_format(ra, this, st); // dst
3531 st->print_raw(", ");
3532 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3533 st->print_raw("\t# long");
3534}
3535#endif
3536#ifndef PRODUCT
3537void loadConL0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3538 // Start at oper_input_base() and count operands
3539 unsigned idx0 = 1;
3540 unsigned idx1 = 1; // src
3541 st->print_raw("xorl ");
3542 opnd_array(0)->int_format(ra, this, st); // dst
3543 st->print_raw(", ");
3544 opnd_array(0)->int_format(ra, this, st); // dst
3545 st->print_raw("\t# long");
3546}
3547#endif
3548#ifndef PRODUCT
3549void loadConUL32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3550 // Start at oper_input_base() and count operands
3551 unsigned idx0 = 1;
3552 unsigned idx1 = 1; // src
3553 st->print_raw("movl ");
3554 opnd_array(0)->int_format(ra, this, st); // dst
3555 st->print_raw(", ");
3556 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3557 st->print_raw("\t# long (unsigned 32-bit)");
3558}
3559#endif
3560#ifndef PRODUCT
3561void loadConL32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3562 // Start at oper_input_base() and count operands
3563 unsigned idx0 = 1;
3564 unsigned idx1 = 1; // src
3565 st->print_raw("movq ");
3566 opnd_array(0)->int_format(ra, this, st); // dst
3567 st->print_raw(", ");
3568 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3569 st->print_raw("\t# long (32-bit)");
3570}
3571#endif
3572#ifndef PRODUCT
3573void loadConPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3574 // Start at oper_input_base() and count operands
3575 unsigned idx0 = 1;
3576 unsigned idx1 = 1; // con
3577 st->print_raw("movq ");
3578 opnd_array(0)->int_format(ra, this, st); // dst
3579 st->print_raw(", ");
3580 opnd_array(1)->ext_format(ra, this,idx1, st); // con
3581 st->print_raw("\t# ptr");
3582}
3583#endif
3584#ifndef PRODUCT
3585void loadConP0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3586 // Start at oper_input_base() and count operands
3587 unsigned idx0 = 1;
3588 unsigned idx1 = 1; // src
3589 st->print_raw("xorl ");
3590 opnd_array(0)->int_format(ra, this, st); // dst
3591 st->print_raw(", ");
3592 opnd_array(0)->int_format(ra, this, st); // dst
3593 st->print_raw("\t# ptr");
3594}
3595#endif
3596#ifndef PRODUCT
3597void loadConP31Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3598 // Start at oper_input_base() and count operands
3599 unsigned idx0 = 1;
3600 unsigned idx1 = 1; // src
3601 st->print_raw("movl ");
3602 opnd_array(0)->int_format(ra, this, st); // dst
3603 st->print_raw(", ");
3604 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3605 st->print_raw("\t# ptr (positive 32-bit)");
3606}
3607#endif
3608#ifndef PRODUCT
3609void loadConFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3610 // Start at oper_input_base() and count operands
3611 unsigned idx0 = 1;
3612 unsigned idx1 = 1; // con
3613 st->print_raw("movss ");
3614 opnd_array(0)->int_format(ra, this, st); // dst
3615 st->print_raw(", [");
3616 st->print("constant table base + #%d", constant_offset_unchecked());
3617 st->print_raw("]\t# load from constant table: float=");
3618 opnd_array(1)->ext_format(ra, this,idx1, st); // con
3619}
3620#endif
3621#ifndef PRODUCT
3622void loadConN0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3623 // Start at oper_input_base() and count operands
3624 unsigned idx0 = 1;
3625 unsigned idx1 = 1; // src
3626 st->print_raw("xorq ");
3627 opnd_array(0)->int_format(ra, this, st); // dst
3628 st->print_raw(", ");
3629 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3630 st->print_raw("\t# compressed NULL ptr");
3631}
3632#endif
3633#ifndef PRODUCT
3634void loadConNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3635 // Start at oper_input_base() and count operands
3636 unsigned idx0 = 1;
3637 unsigned idx1 = 1; // src
3638 st->print_raw("movl ");
3639 opnd_array(0)->int_format(ra, this, st); // dst
3640 st->print_raw(", ");
3641 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3642 st->print_raw("\t# compressed ptr");
3643}
3644#endif
3645#ifndef PRODUCT
3646void loadConNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3647 // Start at oper_input_base() and count operands
3648 unsigned idx0 = 1;
3649 unsigned idx1 = 1; // src
3650 st->print_raw("movl ");
3651 opnd_array(0)->int_format(ra, this, st); // dst
3652 st->print_raw(", ");
3653 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3654 st->print_raw("\t# compressed klass ptr");
3655}
3656#endif
3657#ifndef PRODUCT
3658void loadConF0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3659 // Start at oper_input_base() and count operands
3660 unsigned idx0 = 1;
3661 unsigned idx1 = 1; // src
3662 st->print_raw("xorps ");
3663 opnd_array(0)->int_format(ra, this, st); // dst
3664 st->print_raw(", ");
3665 opnd_array(0)->int_format(ra, this, st); // dst
3666 st->print_raw("\t# float 0.0");
3667}
3668#endif
3669#ifndef PRODUCT
3670void loadConDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3671 // Start at oper_input_base() and count operands
3672 unsigned idx0 = 1;
3673 unsigned idx1 = 1; // con
3674 st->print_raw("movsd ");
3675 opnd_array(0)->int_format(ra, this, st); // dst
3676 st->print_raw(", [");
3677 st->print("constant table base + #%d", constant_offset_unchecked());
3678 st->print_raw("]\t# load from constant table: double=");
3679 opnd_array(1)->ext_format(ra, this,idx1, st); // con
3680}
3681#endif
3682#ifndef PRODUCT
3683void loadConD0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3684 // Start at oper_input_base() and count operands
3685 unsigned idx0 = 1;
3686 unsigned idx1 = 1; // src
3687 st->print_raw("xorpd ");
3688 opnd_array(0)->int_format(ra, this, st); // dst
3689 st->print_raw(", ");
3690 opnd_array(0)->int_format(ra, this, st); // dst
3691 st->print_raw("\t# double 0.0");
3692}
3693#endif
3694#ifndef PRODUCT
3695void loadSSINode::format(PhaseRegAlloc *ra, outputStream *st) const {
3696 // Start at oper_input_base() and count operands
3697 unsigned idx0 = 1;
3698 unsigned idx1 = 1; // src
3699 st->print_raw("movl ");
3700 opnd_array(0)->int_format(ra, this, st); // dst
3701 st->print_raw(", ");
3702 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3703 st->print_raw("\t# int stk");
3704}
3705#endif
3706#ifndef PRODUCT
3707void loadSSLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3708 // Start at oper_input_base() and count operands
3709 unsigned idx0 = 1;
3710 unsigned idx1 = 1; // src
3711 st->print_raw("movq ");
3712 opnd_array(0)->int_format(ra, this, st); // dst
3713 st->print_raw(", ");
3714 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3715 st->print_raw("\t# long stk");
3716}
3717#endif
3718#ifndef PRODUCT
3719void loadSSPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3720 // Start at oper_input_base() and count operands
3721 unsigned idx0 = 1;
3722 unsigned idx1 = 1; // src
3723 st->print_raw("movq ");
3724 opnd_array(0)->int_format(ra, this, st); // dst
3725 st->print_raw(", ");
3726 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3727 st->print_raw("\t# ptr stk");
3728}
3729#endif
3730#ifndef PRODUCT
3731void loadSSFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3732 // Start at oper_input_base() and count operands
3733 unsigned idx0 = 1;
3734 unsigned idx1 = 1; // src
3735 st->print_raw("movss ");
3736 opnd_array(0)->int_format(ra, this, st); // dst
3737 st->print_raw(", ");
3738 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3739 st->print_raw("\t# float stk");
3740}
3741#endif
3742#ifndef PRODUCT
3743void loadSSDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3744 // Start at oper_input_base() and count operands
3745 unsigned idx0 = 1;
3746 unsigned idx1 = 1; // src
3747 st->print_raw("movsd ");
3748 opnd_array(0)->int_format(ra, this, st); // dst
3749 st->print_raw(", ");
3750 opnd_array(1)->ext_format(ra, this,idx1, st); // src
3751 st->print_raw("\t# double stk");
3752}
3753#endif
3754#ifndef PRODUCT
3755void prefetchAllocNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3756 // Start at oper_input_base() and count operands
3757 unsigned idx0 = 2;
3758 unsigned idx1 = 2; //
3759 st->print_raw("PREFETCHW ");
3760 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3761 st->print_raw("\t# Prefetch allocation into level 1 cache and mark modified");
3762}
3763#endif
3764#ifndef PRODUCT
3765void prefetchAllocNTANode::format(PhaseRegAlloc *ra, outputStream *st) const {
3766 // Start at oper_input_base() and count operands
3767 unsigned idx0 = 2;
3768 unsigned idx1 = 2; //
3769 st->print_raw("PREFETCHNTA ");
3770 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3771 st->print_raw("\t# Prefetch allocation to non-temporal cache for write");
3772}
3773#endif
3774#ifndef PRODUCT
3775void prefetchAllocT0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3776 // Start at oper_input_base() and count operands
3777 unsigned idx0 = 2;
3778 unsigned idx1 = 2; //
3779 st->print_raw("PREFETCHT0 ");
3780 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3781 st->print_raw("\t# Prefetch allocation to level 1 and 2 caches for write");
3782}
3783#endif
3784#ifndef PRODUCT
3785void prefetchAllocT2Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3786 // Start at oper_input_base() and count operands
3787 unsigned idx0 = 2;
3788 unsigned idx1 = 2; //
3789 st->print_raw("PREFETCHT2 ");
3790 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3791 st->print_raw("\t# Prefetch allocation to level 2 cache for write");
3792}
3793#endif
3794#ifndef PRODUCT
3795void storeBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3796 // Start at oper_input_base() and count operands
3797 unsigned idx0 = 2;
3798 unsigned idx1 = 2; // mem
3799 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3800 st->print_raw("movb ");
3801 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3802 st->print_raw(", ");
3803 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3804 st->print_raw("\t# byte");
3805 if (ra->C->alias_type(adr_type())->field() != NULL) {
3806 ciField* f = ra->C->alias_type(adr_type())->field();
3807 st->print(" ! Field: ");
3808 if (f->is_volatile())
3809 st->print("volatile ");
3810 f->holder()->name()->print_symbol_on(st);
3811 st->print(".");
3812 f->name()->print_symbol_on(st);
3813 if (f->is_constant())
3814 st->print(" (constant)");
3815 } else {
3816 if (ra->C->alias_type(adr_type())->is_volatile())
3817 st->print(" volatile!");
3818 }
3819}
3820#endif
3821#ifndef PRODUCT
3822void storeCNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3823 // Start at oper_input_base() and count operands
3824 unsigned idx0 = 2;
3825 unsigned idx1 = 2; // mem
3826 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3827 st->print_raw("movw ");
3828 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3829 st->print_raw(", ");
3830 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3831 st->print_raw("\t# char/short");
3832 if (ra->C->alias_type(adr_type())->field() != NULL) {
3833 ciField* f = ra->C->alias_type(adr_type())->field();
3834 st->print(" ! Field: ");
3835 if (f->is_volatile())
3836 st->print("volatile ");
3837 f->holder()->name()->print_symbol_on(st);
3838 st->print(".");
3839 f->name()->print_symbol_on(st);
3840 if (f->is_constant())
3841 st->print(" (constant)");
3842 } else {
3843 if (ra->C->alias_type(adr_type())->is_volatile())
3844 st->print(" volatile!");
3845 }
3846}
3847#endif
3848#ifndef PRODUCT
3849void storeINode::format(PhaseRegAlloc *ra, outputStream *st) const {
3850 // Start at oper_input_base() and count operands
3851 unsigned idx0 = 2;
3852 unsigned idx1 = 2; // mem
3853 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3854 st->print_raw("movl ");
3855 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3856 st->print_raw(", ");
3857 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3858 st->print_raw("\t# int");
3859 if (ra->C->alias_type(adr_type())->field() != NULL) {
3860 ciField* f = ra->C->alias_type(adr_type())->field();
3861 st->print(" ! Field: ");
3862 if (f->is_volatile())
3863 st->print("volatile ");
3864 f->holder()->name()->print_symbol_on(st);
3865 st->print(".");
3866 f->name()->print_symbol_on(st);
3867 if (f->is_constant())
3868 st->print(" (constant)");
3869 } else {
3870 if (ra->C->alias_type(adr_type())->is_volatile())
3871 st->print(" volatile!");
3872 }
3873}
3874#endif
3875#ifndef PRODUCT
3876void storeLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3877 // Start at oper_input_base() and count operands
3878 unsigned idx0 = 2;
3879 unsigned idx1 = 2; // mem
3880 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3881 st->print_raw("movq ");
3882 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3883 st->print_raw(", ");
3884 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3885 st->print_raw("\t# long");
3886 if (ra->C->alias_type(adr_type())->field() != NULL) {
3887 ciField* f = ra->C->alias_type(adr_type())->field();
3888 st->print(" ! Field: ");
3889 if (f->is_volatile())
3890 st->print("volatile ");
3891 f->holder()->name()->print_symbol_on(st);
3892 st->print(".");
3893 f->name()->print_symbol_on(st);
3894 if (f->is_constant())
3895 st->print(" (constant)");
3896 } else {
3897 if (ra->C->alias_type(adr_type())->is_volatile())
3898 st->print(" volatile!");
3899 }
3900}
3901#endif
3902#ifndef PRODUCT
3903void storePNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3904 // Start at oper_input_base() and count operands
3905 unsigned idx0 = 2;
3906 unsigned idx1 = 2; // mem
3907 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3908 st->print_raw("movq ");
3909 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3910 st->print_raw(", ");
3911 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3912 st->print_raw("\t# ptr");
3913 if (ra->C->alias_type(adr_type())->field() != NULL) {
3914 ciField* f = ra->C->alias_type(adr_type())->field();
3915 st->print(" ! Field: ");
3916 if (f->is_volatile())
3917 st->print("volatile ");
3918 f->holder()->name()->print_symbol_on(st);
3919 st->print(".");
3920 f->name()->print_symbol_on(st);
3921 if (f->is_constant())
3922 st->print(" (constant)");
3923 } else {
3924 if (ra->C->alias_type(adr_type())->is_volatile())
3925 st->print(" volatile!");
3926 }
3927}
3928#endif
3929#ifndef PRODUCT
3930void storeImmP0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
3931 // Start at oper_input_base() and count operands
3932 unsigned idx0 = 2;
3933 unsigned idx1 = 2; // mem
3934 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
3935 st->print_raw("movq ");
3936 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3937 st->print_raw(", R12\t# ptr (R12_heapbase==0)");
3938 if (ra->C->alias_type(adr_type())->field() != NULL) {
3939 ciField* f = ra->C->alias_type(adr_type())->field();
3940 st->print(" ! Field: ");
3941 if (f->is_volatile())
3942 st->print("volatile ");
3943 f->holder()->name()->print_symbol_on(st);
3944 st->print(".");
3945 f->name()->print_symbol_on(st);
3946 if (f->is_constant())
3947 st->print(" (constant)");
3948 } else {
3949 if (ra->C->alias_type(adr_type())->is_volatile())
3950 st->print(" volatile!");
3951 }
3952}
3953#endif
3954#ifndef PRODUCT
3955void storeImmPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3956 // Start at oper_input_base() and count operands
3957 unsigned idx0 = 2;
3958 unsigned idx1 = 2; // mem
3959 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3960 st->print_raw("movq ");
3961 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3962 st->print_raw(", ");
3963 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3964 st->print_raw("\t# ptr");
3965 if (ra->C->alias_type(adr_type())->field() != NULL) {
3966 ciField* f = ra->C->alias_type(adr_type())->field();
3967 st->print(" ! Field: ");
3968 if (f->is_volatile())
3969 st->print("volatile ");
3970 f->holder()->name()->print_symbol_on(st);
3971 st->print(".");
3972 f->name()->print_symbol_on(st);
3973 if (f->is_constant())
3974 st->print(" (constant)");
3975 } else {
3976 if (ra->C->alias_type(adr_type())->is_volatile())
3977 st->print(" volatile!");
3978 }
3979}
3980#endif
3981#ifndef PRODUCT
3982void storeNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
3983 // Start at oper_input_base() and count operands
3984 unsigned idx0 = 2;
3985 unsigned idx1 = 2; // mem
3986 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
3987 st->print_raw("movl ");
3988 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
3989 st->print_raw(", ");
3990 opnd_array(2)->ext_format(ra, this,idx2, st); // src
3991 st->print_raw("\t# compressed ptr");
3992 if (ra->C->alias_type(adr_type())->field() != NULL) {
3993 ciField* f = ra->C->alias_type(adr_type())->field();
3994 st->print(" ! Field: ");
3995 if (f->is_volatile())
3996 st->print("volatile ");
3997 f->holder()->name()->print_symbol_on(st);
3998 st->print(".");
3999 f->name()->print_symbol_on(st);
4000 if (f->is_constant())
4001 st->print(" (constant)");
4002 } else {
4003 if (ra->C->alias_type(adr_type())->is_volatile())
4004 st->print(" volatile!");
4005 }
4006}
4007#endif
4008#ifndef PRODUCT
4009void storeNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4010 // Start at oper_input_base() and count operands
4011 unsigned idx0 = 2;
4012 unsigned idx1 = 2; // mem
4013 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4014 st->print_raw("movl ");
4015 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4016 st->print_raw(", ");
4017 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4018 st->print_raw("\t# compressed klass ptr");
4019 if (ra->C->alias_type(adr_type())->field() != NULL) {
4020 ciField* f = ra->C->alias_type(adr_type())->field();
4021 st->print(" ! Field: ");
4022 if (f->is_volatile())
4023 st->print("volatile ");
4024 f->holder()->name()->print_symbol_on(st);
4025 st->print(".");
4026 f->name()->print_symbol_on(st);
4027 if (f->is_constant())
4028 st->print(" (constant)");
4029 } else {
4030 if (ra->C->alias_type(adr_type())->is_volatile())
4031 st->print(" volatile!");
4032 }
4033}
4034#endif
4035#ifndef PRODUCT
4036void storeImmN0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4037 // Start at oper_input_base() and count operands
4038 unsigned idx0 = 2;
4039 unsigned idx1 = 2; // mem
4040 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4041 st->print_raw("movl ");
4042 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4043 st->print_raw(", R12\t# compressed ptr (R12_heapbase==0)");
4044 if (ra->C->alias_type(adr_type())->field() != NULL) {
4045 ciField* f = ra->C->alias_type(adr_type())->field();
4046 st->print(" ! Field: ");
4047 if (f->is_volatile())
4048 st->print("volatile ");
4049 f->holder()->name()->print_symbol_on(st);
4050 st->print(".");
4051 f->name()->print_symbol_on(st);
4052 if (f->is_constant())
4053 st->print(" (constant)");
4054 } else {
4055 if (ra->C->alias_type(adr_type())->is_volatile())
4056 st->print(" volatile!");
4057 }
4058}
4059#endif
4060#ifndef PRODUCT
4061void storeImmNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4062 // Start at oper_input_base() and count operands
4063 unsigned idx0 = 2;
4064 unsigned idx1 = 2; // mem
4065 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4066 st->print_raw("movl ");
4067 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4068 st->print_raw(", ");
4069 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4070 st->print_raw("\t# compressed ptr");
4071 if (ra->C->alias_type(adr_type())->field() != NULL) {
4072 ciField* f = ra->C->alias_type(adr_type())->field();
4073 st->print(" ! Field: ");
4074 if (f->is_volatile())
4075 st->print("volatile ");
4076 f->holder()->name()->print_symbol_on(st);
4077 st->print(".");
4078 f->name()->print_symbol_on(st);
4079 if (f->is_constant())
4080 st->print(" (constant)");
4081 } else {
4082 if (ra->C->alias_type(adr_type())->is_volatile())
4083 st->print(" volatile!");
4084 }
4085}
4086#endif
4087#ifndef PRODUCT
4088void storeImmNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4089 // Start at oper_input_base() and count operands
4090 unsigned idx0 = 2;
4091 unsigned idx1 = 2; // mem
4092 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4093 st->print_raw("movl ");
4094 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4095 st->print_raw(", ");
4096 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4097 st->print_raw("\t# compressed klass ptr");
4098 if (ra->C->alias_type(adr_type())->field() != NULL) {
4099 ciField* f = ra->C->alias_type(adr_type())->field();
4100 st->print(" ! Field: ");
4101 if (f->is_volatile())
4102 st->print("volatile ");
4103 f->holder()->name()->print_symbol_on(st);
4104 st->print(".");
4105 f->name()->print_symbol_on(st);
4106 if (f->is_constant())
4107 st->print(" (constant)");
4108 } else {
4109 if (ra->C->alias_type(adr_type())->is_volatile())
4110 st->print(" volatile!");
4111 }
4112}
4113#endif
4114#ifndef PRODUCT
4115void storeImmI0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4116 // Start at oper_input_base() and count operands
4117 unsigned idx0 = 2;
4118 unsigned idx1 = 2; // mem
4119 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4120 st->print_raw("movl ");
4121 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4122 st->print_raw(", R12\t# int (R12_heapbase==0)");
4123 if (ra->C->alias_type(adr_type())->field() != NULL) {
4124 ciField* f = ra->C->alias_type(adr_type())->field();
4125 st->print(" ! Field: ");
4126 if (f->is_volatile())
4127 st->print("volatile ");
4128 f->holder()->name()->print_symbol_on(st);
4129 st->print(".");
4130 f->name()->print_symbol_on(st);
4131 if (f->is_constant())
4132 st->print(" (constant)");
4133 } else {
4134 if (ra->C->alias_type(adr_type())->is_volatile())
4135 st->print(" volatile!");
4136 }
4137}
4138#endif
4139#ifndef PRODUCT
4140void storeImmINode::format(PhaseRegAlloc *ra, outputStream *st) const {
4141 // Start at oper_input_base() and count operands
4142 unsigned idx0 = 2;
4143 unsigned idx1 = 2; // mem
4144 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4145 st->print_raw("movl ");
4146 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4147 st->print_raw(", ");
4148 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4149 st->print_raw("\t# int");
4150 if (ra->C->alias_type(adr_type())->field() != NULL) {
4151 ciField* f = ra->C->alias_type(adr_type())->field();
4152 st->print(" ! Field: ");
4153 if (f->is_volatile())
4154 st->print("volatile ");
4155 f->holder()->name()->print_symbol_on(st);
4156 st->print(".");
4157 f->name()->print_symbol_on(st);
4158 if (f->is_constant())
4159 st->print(" (constant)");
4160 } else {
4161 if (ra->C->alias_type(adr_type())->is_volatile())
4162 st->print(" volatile!");
4163 }
4164}
4165#endif
4166#ifndef PRODUCT
4167void storeImmL0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4168 // Start at oper_input_base() and count operands
4169 unsigned idx0 = 2;
4170 unsigned idx1 = 2; // mem
4171 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4172 st->print_raw("movq ");
4173 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4174 st->print_raw(", R12\t# long (R12_heapbase==0)");
4175 if (ra->C->alias_type(adr_type())->field() != NULL) {
4176 ciField* f = ra->C->alias_type(adr_type())->field();
4177 st->print(" ! Field: ");
4178 if (f->is_volatile())
4179 st->print("volatile ");
4180 f->holder()->name()->print_symbol_on(st);
4181 st->print(".");
4182 f->name()->print_symbol_on(st);
4183 if (f->is_constant())
4184 st->print(" (constant)");
4185 } else {
4186 if (ra->C->alias_type(adr_type())->is_volatile())
4187 st->print(" volatile!");
4188 }
4189}
4190#endif
4191#ifndef PRODUCT
4192void storeImmLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4193 // Start at oper_input_base() and count operands
4194 unsigned idx0 = 2;
4195 unsigned idx1 = 2; // mem
4196 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4197 st->print_raw("movq ");
4198 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4199 st->print_raw(", ");
4200 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4201 st->print_raw("\t# long");
4202 if (ra->C->alias_type(adr_type())->field() != NULL) {
4203 ciField* f = ra->C->alias_type(adr_type())->field();
4204 st->print(" ! Field: ");
4205 if (f->is_volatile())
4206 st->print("volatile ");
4207 f->holder()->name()->print_symbol_on(st);
4208 st->print(".");
4209 f->name()->print_symbol_on(st);
4210 if (f->is_constant())
4211 st->print(" (constant)");
4212 } else {
4213 if (ra->C->alias_type(adr_type())->is_volatile())
4214 st->print(" volatile!");
4215 }
4216}
4217#endif
4218#ifndef PRODUCT
4219void storeImmC0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4220 // Start at oper_input_base() and count operands
4221 unsigned idx0 = 2;
4222 unsigned idx1 = 2; // mem
4223 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4224 st->print_raw("movw ");
4225 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4226 st->print_raw(", R12\t# short/char (R12_heapbase==0)");
4227 if (ra->C->alias_type(adr_type())->field() != NULL) {
4228 ciField* f = ra->C->alias_type(adr_type())->field();
4229 st->print(" ! Field: ");
4230 if (f->is_volatile())
4231 st->print("volatile ");
4232 f->holder()->name()->print_symbol_on(st);
4233 st->print(".");
4234 f->name()->print_symbol_on(st);
4235 if (f->is_constant())
4236 st->print(" (constant)");
4237 } else {
4238 if (ra->C->alias_type(adr_type())->is_volatile())
4239 st->print(" volatile!");
4240 }
4241}
4242#endif
4243#ifndef PRODUCT
4244void storeImmI16Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4245 // Start at oper_input_base() and count operands
4246 unsigned idx0 = 2;
4247 unsigned idx1 = 2; // mem
4248 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4249 st->print_raw("movw ");
4250 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4251 st->print_raw(", ");
4252 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4253 st->print_raw("\t# short/char");
4254 if (ra->C->alias_type(adr_type())->field() != NULL) {
4255 ciField* f = ra->C->alias_type(adr_type())->field();
4256 st->print(" ! Field: ");
4257 if (f->is_volatile())
4258 st->print("volatile ");
4259 f->holder()->name()->print_symbol_on(st);
4260 st->print(".");
4261 f->name()->print_symbol_on(st);
4262 if (f->is_constant())
4263 st->print(" (constant)");
4264 } else {
4265 if (ra->C->alias_type(adr_type())->is_volatile())
4266 st->print(" volatile!");
4267 }
4268}
4269#endif
4270#ifndef PRODUCT
4271void storeImmB0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4272 // Start at oper_input_base() and count operands
4273 unsigned idx0 = 2;
4274 unsigned idx1 = 2; // mem
4275 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4276 st->print_raw("movb ");
4277 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4278 st->print_raw(", R12\t# short/char (R12_heapbase==0)");
4279 if (ra->C->alias_type(adr_type())->field() != NULL) {
4280 ciField* f = ra->C->alias_type(adr_type())->field();
4281 st->print(" ! Field: ");
4282 if (f->is_volatile())
4283 st->print("volatile ");
4284 f->holder()->name()->print_symbol_on(st);
4285 st->print(".");
4286 f->name()->print_symbol_on(st);
4287 if (f->is_constant())
4288 st->print(" (constant)");
4289 } else {
4290 if (ra->C->alias_type(adr_type())->is_volatile())
4291 st->print(" volatile!");
4292 }
4293}
4294#endif
4295#ifndef PRODUCT
4296void storeImmBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4297 // Start at oper_input_base() and count operands
4298 unsigned idx0 = 2;
4299 unsigned idx1 = 2; // mem
4300 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4301 st->print_raw("movb ");
4302 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4303 st->print_raw(", ");
4304 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4305 st->print_raw("\t# byte");
4306 if (ra->C->alias_type(adr_type())->field() != NULL) {
4307 ciField* f = ra->C->alias_type(adr_type())->field();
4308 st->print(" ! Field: ");
4309 if (f->is_volatile())
4310 st->print("volatile ");
4311 f->holder()->name()->print_symbol_on(st);
4312 st->print(".");
4313 f->name()->print_symbol_on(st);
4314 if (f->is_constant())
4315 st->print(" (constant)");
4316 } else {
4317 if (ra->C->alias_type(adr_type())->is_volatile())
4318 st->print(" volatile!");
4319 }
4320}
4321#endif
4322#ifndef PRODUCT
4323void storeImmCM0_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4324 // Start at oper_input_base() and count operands
4325 unsigned idx0 = 2;
4326 unsigned idx1 = 2; // mem
4327 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4328 st->print_raw("movb ");
4329 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4330 st->print_raw(", R12\t# CMS card-mark byte 0 (R12_heapbase==0)");
4331 if (ra->C->alias_type(adr_type())->field() != NULL) {
4332 ciField* f = ra->C->alias_type(adr_type())->field();
4333 st->print(" ! Field: ");
4334 if (f->is_volatile())
4335 st->print("volatile ");
4336 f->holder()->name()->print_symbol_on(st);
4337 st->print(".");
4338 f->name()->print_symbol_on(st);
4339 if (f->is_constant())
4340 st->print(" (constant)");
4341 } else {
4342 if (ra->C->alias_type(adr_type())->is_volatile())
4343 st->print(" volatile!");
4344 }
4345}
4346#endif
4347#ifndef PRODUCT
4348void storeImmCM0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4349 // Start at oper_input_base() and count operands
4350 unsigned idx0 = 2;
4351 unsigned idx1 = 2; // mem
4352 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4353 st->print_raw("movb ");
4354 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4355 st->print_raw(", ");
4356 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4357 st->print_raw("\t# CMS card-mark byte 0");
4358 if (ra->C->alias_type(adr_type())->field() != NULL) {
4359 ciField* f = ra->C->alias_type(adr_type())->field();
4360 st->print(" ! Field: ");
4361 if (f->is_volatile())
4362 st->print("volatile ");
4363 f->holder()->name()->print_symbol_on(st);
4364 st->print(".");
4365 f->name()->print_symbol_on(st);
4366 if (f->is_constant())
4367 st->print(" (constant)");
4368 } else {
4369 if (ra->C->alias_type(adr_type())->is_volatile())
4370 st->print(" volatile!");
4371 }
4372}
4373#endif
4374#ifndef PRODUCT
4375void storeFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4376 // Start at oper_input_base() and count operands
4377 unsigned idx0 = 2;
4378 unsigned idx1 = 2; // mem
4379 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4380 st->print_raw("movss ");
4381 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4382 st->print_raw(", ");
4383 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4384 st->print_raw("\t# float");
4385 if (ra->C->alias_type(adr_type())->field() != NULL) {
4386 ciField* f = ra->C->alias_type(adr_type())->field();
4387 st->print(" ! Field: ");
4388 if (f->is_volatile())
4389 st->print("volatile ");
4390 f->holder()->name()->print_symbol_on(st);
4391 st->print(".");
4392 f->name()->print_symbol_on(st);
4393 if (f->is_constant())
4394 st->print(" (constant)");
4395 } else {
4396 if (ra->C->alias_type(adr_type())->is_volatile())
4397 st->print(" volatile!");
4398 }
4399}
4400#endif
4401#ifndef PRODUCT
4402void storeF0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4403 // Start at oper_input_base() and count operands
4404 unsigned idx0 = 2;
4405 unsigned idx1 = 2; // mem
4406 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4407 st->print_raw("movl ");
4408 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4409 st->print_raw(", R12\t# float 0. (R12_heapbase==0)");
4410 if (ra->C->alias_type(adr_type())->field() != NULL) {
4411 ciField* f = ra->C->alias_type(adr_type())->field();
4412 st->print(" ! Field: ");
4413 if (f->is_volatile())
4414 st->print("volatile ");
4415 f->holder()->name()->print_symbol_on(st);
4416 st->print(".");
4417 f->name()->print_symbol_on(st);
4418 if (f->is_constant())
4419 st->print(" (constant)");
4420 } else {
4421 if (ra->C->alias_type(adr_type())->is_volatile())
4422 st->print(" volatile!");
4423 }
4424}
4425#endif
4426#ifndef PRODUCT
4427void storeF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4428 // Start at oper_input_base() and count operands
4429 unsigned idx0 = 2;
4430 unsigned idx1 = 2; // mem
4431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4432 st->print_raw("movl ");
4433 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4434 st->print_raw(", ");
4435 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4436 st->print_raw("\t# float");
4437 if (ra->C->alias_type(adr_type())->field() != NULL) {
4438 ciField* f = ra->C->alias_type(adr_type())->field();
4439 st->print(" ! Field: ");
4440 if (f->is_volatile())
4441 st->print("volatile ");
4442 f->holder()->name()->print_symbol_on(st);
4443 st->print(".");
4444 f->name()->print_symbol_on(st);
4445 if (f->is_constant())
4446 st->print(" (constant)");
4447 } else {
4448 if (ra->C->alias_type(adr_type())->is_volatile())
4449 st->print(" volatile!");
4450 }
4451}
4452#endif
4453#ifndef PRODUCT
4454void storeDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4455 // Start at oper_input_base() and count operands
4456 unsigned idx0 = 2;
4457 unsigned idx1 = 2; // mem
4458 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4459 st->print_raw("movsd ");
4460 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4461 st->print_raw(", ");
4462 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4463 st->print_raw("\t# double");
4464 if (ra->C->alias_type(adr_type())->field() != NULL) {
4465 ciField* f = ra->C->alias_type(adr_type())->field();
4466 st->print(" ! Field: ");
4467 if (f->is_volatile())
4468 st->print("volatile ");
4469 f->holder()->name()->print_symbol_on(st);
4470 st->print(".");
4471 f->name()->print_symbol_on(st);
4472 if (f->is_constant())
4473 st->print(" (constant)");
4474 } else {
4475 if (ra->C->alias_type(adr_type())->is_volatile())
4476 st->print(" volatile!");
4477 }
4478}
4479#endif
4480#ifndef PRODUCT
4481void storeD0_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4482 // Start at oper_input_base() and count operands
4483 unsigned idx0 = 2;
4484 unsigned idx1 = 2; // mem
4485 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
4486 st->print_raw("movq ");
4487 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4488 st->print_raw(", ");
4489 opnd_array(2)->ext_format(ra, this,idx2, st); // src
4490 st->print_raw("\t# double 0.");
4491 if (ra->C->alias_type(adr_type())->field() != NULL) {
4492 ciField* f = ra->C->alias_type(adr_type())->field();
4493 st->print(" ! Field: ");
4494 if (f->is_volatile())
4495 st->print("volatile ");
4496 f->holder()->name()->print_symbol_on(st);
4497 st->print(".");
4498 f->name()->print_symbol_on(st);
4499 if (f->is_constant())
4500 st->print(" (constant)");
4501 } else {
4502 if (ra->C->alias_type(adr_type())->is_volatile())
4503 st->print(" volatile!");
4504 }
4505}
4506#endif
4507#ifndef PRODUCT
4508void storeD0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4509 // Start at oper_input_base() and count operands
4510 unsigned idx0 = 2;
4511 unsigned idx1 = 2; // mem
4512 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
4513 st->print_raw("movq ");
4514 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4515 st->print_raw(", R12\t# double 0. (R12_heapbase==0)");
4516 if (ra->C->alias_type(adr_type())->field() != NULL) {
4517 ciField* f = ra->C->alias_type(adr_type())->field();
4518 st->print(" ! Field: ");
4519 if (f->is_volatile())
4520 st->print("volatile ");
4521 f->holder()->name()->print_symbol_on(st);
4522 st->print(".");
4523 f->name()->print_symbol_on(st);
4524 if (f->is_constant())
4525 st->print(" (constant)");
4526 } else {
4527 if (ra->C->alias_type(adr_type())->is_volatile())
4528 st->print(" volatile!");
4529 }
4530}
4531#endif
4532#ifndef PRODUCT
4533void storeSSINode::format(PhaseRegAlloc *ra, outputStream *st) const {
4534 // Start at oper_input_base() and count operands
4535 unsigned idx0 = 1;
4536 unsigned idx1 = 1; // src
4537 st->print_raw("movl ");
4538 opnd_array(0)->int_format(ra, this, st); // dst
4539 st->print_raw(", ");
4540 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4541 st->print_raw("\t# int stk");
4542}
4543#endif
4544#ifndef PRODUCT
4545void storeSSLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4546 // Start at oper_input_base() and count operands
4547 unsigned idx0 = 1;
4548 unsigned idx1 = 1; // src
4549 st->print_raw("movq ");
4550 opnd_array(0)->int_format(ra, this, st); // dst
4551 st->print_raw(", ");
4552 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4553 st->print_raw("\t# long stk");
4554}
4555#endif
4556#ifndef PRODUCT
4557void storeSSPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4558 // Start at oper_input_base() and count operands
4559 unsigned idx0 = 1;
4560 unsigned idx1 = 1; // src
4561 st->print_raw("movq ");
4562 opnd_array(0)->int_format(ra, this, st); // dst
4563 st->print_raw(", ");
4564 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4565 st->print_raw("\t# ptr stk");
4566}
4567#endif
4568#ifndef PRODUCT
4569void storeSSFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4570 // Start at oper_input_base() and count operands
4571 unsigned idx0 = 1;
4572 unsigned idx1 = 1; // src
4573 st->print_raw("movss ");
4574 opnd_array(0)->int_format(ra, this, st); // dst
4575 st->print_raw(", ");
4576 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4577 st->print_raw("\t# float stk");
4578}
4579#endif
4580#ifndef PRODUCT
4581void storeSSDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4582 // Start at oper_input_base() and count operands
4583 unsigned idx0 = 1;
4584 unsigned idx1 = 1; // src
4585 st->print_raw("movsd ");
4586 opnd_array(0)->int_format(ra, this, st); // dst
4587 st->print_raw(", ");
4588 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4589 st->print_raw("\t# double stk");
4590}
4591#endif
4592#ifndef PRODUCT
4593void bytes_reverse_intNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4594 // Start at oper_input_base() and count operands
4595 unsigned idx0 = 1;
4596 unsigned idx1 = 1; // dst
4597 st->print_raw("bswapl ");
4598 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4599}
4600#endif
4601#ifndef PRODUCT
4602void bytes_reverse_longNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4603 // Start at oper_input_base() and count operands
4604 unsigned idx0 = 1;
4605 unsigned idx1 = 1; // dst
4606 st->print_raw("bswapq ");
4607 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4608}
4609#endif
4610#ifndef PRODUCT
4611void bytes_reverse_unsigned_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4612 // Start at oper_input_base() and count operands
4613 unsigned idx0 = 1;
4614 unsigned idx1 = 1; // dst
4615 st->print_raw("bswapl ");
4616 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4617 st->print_raw("\n\t");
4618 st->print_raw("shrl ");
4619 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4620 st->print_raw(",16\n\t");
4621}
4622#endif
4623#ifndef PRODUCT
4624void bytes_reverse_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4625 // Start at oper_input_base() and count operands
4626 unsigned idx0 = 1;
4627 unsigned idx1 = 1; // dst
4628 st->print_raw("bswapl ");
4629 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4630 st->print_raw("\n\t");
4631 st->print_raw("sar ");
4632 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
4633 st->print_raw(",16\n\t");
4634}
4635#endif
4636#ifndef PRODUCT
4637void countLeadingZerosINode::format(PhaseRegAlloc *ra, outputStream *st) const {
4638 // Start at oper_input_base() and count operands
4639 unsigned idx0 = 1;
4640 unsigned idx1 = 1; // src
4641 st->print_raw("lzcntl ");
4642 opnd_array(0)->int_format(ra, this, st); // dst
4643 st->print_raw(", ");
4644 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4645 st->print_raw("\t# count leading zeros (int)");
4646}
4647#endif
4648#ifndef PRODUCT
4649void countLeadingZerosI_bsrNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4650 // Start at oper_input_base() and count operands
4651 unsigned idx0 = 1;
4652 unsigned idx1 = 1; // src
4653 st->print_raw("bsrl ");
4654 opnd_array(0)->int_format(ra, this, st); // dst
4655 st->print_raw(", ");
4656 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4657 st->print_raw("\t# count leading zeros (int)\n\t");
4658 st->print_raw("jnz skip\n\t");
4659 st->print_raw("movl ");
4660 opnd_array(0)->int_format(ra, this, st); // dst
4661 st->print_raw(", -1\n");
4662 st->print_raw("skip:\n\t");
4663 st->print_raw("negl ");
4664 opnd_array(0)->int_format(ra, this, st); // dst
4665 st->print_raw("\n\t");
4666 st->print_raw("addl ");
4667 opnd_array(0)->int_format(ra, this, st); // dst
4668 st->print_raw(", 31");
4669}
4670#endif
4671#ifndef PRODUCT
4672void countLeadingZerosLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4673 // Start at oper_input_base() and count operands
4674 unsigned idx0 = 1;
4675 unsigned idx1 = 1; // src
4676 st->print_raw("lzcntq ");
4677 opnd_array(0)->int_format(ra, this, st); // dst
4678 st->print_raw(", ");
4679 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4680 st->print_raw("\t# count leading zeros (long)");
4681}
4682#endif
4683#ifndef PRODUCT
4684void countLeadingZerosL_bsrNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4685 // Start at oper_input_base() and count operands
4686 unsigned idx0 = 1;
4687 unsigned idx1 = 1; // src
4688 st->print_raw("bsrq ");
4689 opnd_array(0)->int_format(ra, this, st); // dst
4690 st->print_raw(", ");
4691 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4692 st->print_raw("\t# count leading zeros (long)\n\t");
4693 st->print_raw("jnz skip\n\t");
4694 st->print_raw("movl ");
4695 opnd_array(0)->int_format(ra, this, st); // dst
4696 st->print_raw(", -1\n");
4697 st->print_raw("skip:\n\t");
4698 st->print_raw("negl ");
4699 opnd_array(0)->int_format(ra, this, st); // dst
4700 st->print_raw("\n\t");
4701 st->print_raw("addl ");
4702 opnd_array(0)->int_format(ra, this, st); // dst
4703 st->print_raw(", 63");
4704}
4705#endif
4706#ifndef PRODUCT
4707void countTrailingZerosINode::format(PhaseRegAlloc *ra, outputStream *st) const {
4708 // Start at oper_input_base() and count operands
4709 unsigned idx0 = 1;
4710 unsigned idx1 = 1; // src
4711 st->print_raw("tzcntl ");
4712 opnd_array(0)->int_format(ra, this, st); // dst
4713 st->print_raw(", ");
4714 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4715 st->print_raw("\t# count trailing zeros (int)");
4716}
4717#endif
4718#ifndef PRODUCT
4719void countTrailingZerosI_bsfNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4720 // Start at oper_input_base() and count operands
4721 unsigned idx0 = 1;
4722 unsigned idx1 = 1; // src
4723 st->print_raw("bsfl ");
4724 opnd_array(0)->int_format(ra, this, st); // dst
4725 st->print_raw(", ");
4726 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4727 st->print_raw("\t# count trailing zeros (int)\n\t");
4728 st->print_raw("jnz done\n\t");
4729 st->print_raw("movl ");
4730 opnd_array(0)->int_format(ra, this, st); // dst
4731 st->print_raw(", 32\n");
4732 st->print_raw("done:");
4733}
4734#endif
4735#ifndef PRODUCT
4736void countTrailingZerosLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4737 // Start at oper_input_base() and count operands
4738 unsigned idx0 = 1;
4739 unsigned idx1 = 1; // src
4740 st->print_raw("tzcntq ");
4741 opnd_array(0)->int_format(ra, this, st); // dst
4742 st->print_raw(", ");
4743 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4744 st->print_raw("\t# count trailing zeros (long)");
4745}
4746#endif
4747#ifndef PRODUCT
4748void countTrailingZerosL_bsfNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4749 // Start at oper_input_base() and count operands
4750 unsigned idx0 = 1;
4751 unsigned idx1 = 1; // src
4752 st->print_raw("bsfq ");
4753 opnd_array(0)->int_format(ra, this, st); // dst
4754 st->print_raw(", ");
4755 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4756 st->print_raw("\t# count trailing zeros (long)\n\t");
4757 st->print_raw("jnz done\n\t");
4758 st->print_raw("movl ");
4759 opnd_array(0)->int_format(ra, this, st); // dst
4760 st->print_raw(", 64\n");
4761 st->print_raw("done:");
4762}
4763#endif
4764#ifndef PRODUCT
4765void popCountINode::format(PhaseRegAlloc *ra, outputStream *st) const {
4766 // Start at oper_input_base() and count operands
4767 unsigned idx0 = 1;
4768 unsigned idx1 = 1; // src
4769 st->print_raw("popcnt ");
4770 opnd_array(0)->int_format(ra, this, st); // dst
4771 st->print_raw(", ");
4772 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4773}
4774#endif
4775#ifndef PRODUCT
4776void popCountI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4777 // Start at oper_input_base() and count operands
4778 unsigned idx0 = 2;
4779 unsigned idx1 = 2; // mem
4780 st->print_raw("popcnt ");
4781 opnd_array(0)->int_format(ra, this, st); // dst
4782 st->print_raw(", ");
4783 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4784}
4785#endif
4786#ifndef PRODUCT
4787void popCountLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4788 // Start at oper_input_base() and count operands
4789 unsigned idx0 = 1;
4790 unsigned idx1 = 1; // src
4791 st->print_raw("popcnt ");
4792 opnd_array(0)->int_format(ra, this, st); // dst
4793 st->print_raw(", ");
4794 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4795}
4796#endif
4797#ifndef PRODUCT
4798void popCountL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4799 // Start at oper_input_base() and count operands
4800 unsigned idx0 = 2;
4801 unsigned idx1 = 2; // mem
4802 st->print_raw("popcnt ");
4803 opnd_array(0)->int_format(ra, this, st); // dst
4804 st->print_raw(", ");
4805 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
4806}
4807#endif
4808#ifndef PRODUCT
4809void membar_acquireNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4810 st->print_raw("MEMBAR-acquire ! (empty encoding)");
4811}
4812#endif
4813#ifndef PRODUCT
4814void membar_acquire_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4815 st->print_raw("MEMBAR-acquire ! (empty encoding)");
4816}
4817#endif
4818#ifndef PRODUCT
4819void membar_acquire_lockNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4820 st->print_raw("MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)");
4821}
4822#endif
4823#ifndef PRODUCT
4824void membar_releaseNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4825 st->print_raw("MEMBAR-release ! (empty encoding)");
4826}
4827#endif
4828#ifndef PRODUCT
4829void membar_release_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
4830 st->print_raw("MEMBAR-release ! (empty encoding)");
4831}
4832#endif
4833#ifndef PRODUCT
4834void membar_release_lockNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4835 st->print_raw("MEMBAR-release (a FastUnlock follows so empty encoding)");
4836}
4837#endif
4838#ifndef PRODUCT
4839void membar_volatileNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4840 st->print_raw("lock addl [rsp + #0], 0\t! membar_volatile");
4841}
4842#endif
4843#ifndef PRODUCT
4844void unnecessary_membar_volatileNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4845 st->print_raw("MEMBAR-volatile (unnecessary so empty encoding)");
4846}
4847#endif
4848#ifndef PRODUCT
4849void membar_storestoreNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4850 st->print_raw("MEMBAR-storestore (empty encoding)");
4851}
4852#endif
4853#ifndef PRODUCT
4854void castX2PNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4855 // Start at oper_input_base() and count operands
4856 unsigned idx0 = 1;
4857 unsigned idx1 = 1; // src
4858 st->print_raw("movq ");
4859 opnd_array(0)->int_format(ra, this, st); // dst
4860 st->print_raw(", ");
4861 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4862 st->print_raw("\t# long->ptr");
4863}
4864#endif
4865#ifndef PRODUCT
4866void castP2XNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4867 // Start at oper_input_base() and count operands
4868 unsigned idx0 = 1;
4869 unsigned idx1 = 1; // src
4870 st->print_raw("movq ");
4871 opnd_array(0)->int_format(ra, this, st); // dst
4872 st->print_raw(", ");
4873 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4874 st->print_raw("\t# ptr -> long");
4875}
4876#endif
4877#ifndef PRODUCT
4878void convP2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
4879 // Start at oper_input_base() and count operands
4880 unsigned idx0 = 1;
4881 unsigned idx1 = 1; // src
4882 st->print_raw("movl ");
4883 opnd_array(0)->int_format(ra, this, st); // dst
4884 st->print_raw(", ");
4885 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4886 st->print_raw("\t# ptr -> int");
4887}
4888#endif
4889#ifndef PRODUCT
4890void convN2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
4891 // Start at oper_input_base() and count operands
4892 unsigned idx0 = 1;
4893 unsigned idx1 = 1; // src
4894 st->print_raw("movl ");
4895 opnd_array(0)->int_format(ra, this, st); // dst
4896 st->print_raw(", ");
4897 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4898 st->print_raw("\t# compressed ptr -> int");
4899}
4900#endif
4901#ifndef PRODUCT
4902void encodeHeapOopNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4903 // Start at oper_input_base() and count operands
4904 unsigned idx0 = 1;
4905 unsigned idx1 = 1; // src
4906 st->print_raw("encode_heap_oop ");
4907 opnd_array(0)->int_format(ra, this, st); // dst
4908 st->print_raw(",");
4909 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4910}
4911#endif
4912#ifndef PRODUCT
4913void encodeHeapOop_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4914 // Start at oper_input_base() and count operands
4915 unsigned idx0 = 1;
4916 unsigned idx1 = 1; // src
4917 st->print_raw("encode_heap_oop_not_null ");
4918 opnd_array(0)->int_format(ra, this, st); // dst
4919 st->print_raw(",");
4920 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4921}
4922#endif
4923#ifndef PRODUCT
4924void decodeHeapOopNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4925 // Start at oper_input_base() and count operands
4926 unsigned idx0 = 1;
4927 unsigned idx1 = 1; // src
4928 st->print_raw("decode_heap_oop ");
4929 opnd_array(0)->int_format(ra, this, st); // dst
4930 st->print_raw(",");
4931 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4932}
4933#endif
4934#ifndef PRODUCT
4935void decodeHeapOop_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4936 // Start at oper_input_base() and count operands
4937 unsigned idx0 = 1;
4938 unsigned idx1 = 1; // src
4939 st->print_raw("decode_heap_oop_not_null ");
4940 opnd_array(0)->int_format(ra, this, st); // dst
4941 st->print_raw(",");
4942 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4943}
4944#endif
4945#ifndef PRODUCT
4946void encodeKlass_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4947 // Start at oper_input_base() and count operands
4948 unsigned idx0 = 1;
4949 unsigned idx1 = 1; // src
4950 st->print_raw("encode_klass_not_null ");
4951 opnd_array(0)->int_format(ra, this, st); // dst
4952 st->print_raw(",");
4953 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4954}
4955#endif
4956#ifndef PRODUCT
4957void decodeKlass_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4958 // Start at oper_input_base() and count operands
4959 unsigned idx0 = 1;
4960 unsigned idx1 = 1; // src
4961 st->print_raw("decode_klass_not_null ");
4962 opnd_array(0)->int_format(ra, this, st); // dst
4963 st->print_raw(",");
4964 opnd_array(1)->ext_format(ra, this,idx1, st); // src
4965}
4966#endif
4967#ifndef PRODUCT
4968void jumpXtnd_offsetNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4969 // Start at oper_input_base() and count operands
4970 unsigned idx0 = 1;
4971 unsigned idx1 = 1; // shift
4972 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dest
4973 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
4974 st->print_raw("leaq ");
4975 opnd_array(3)->ext_format(ra, this,idx3, st); // dest
4976 st->print_raw(", [");
4977 st->print("constant table base + #%d", constant_offset_unchecked());
4978 st->print_raw("]\n\t");
4979 st->print_raw("jmp [");
4980 opnd_array(3)->ext_format(ra, this,idx3, st); // dest
4981 st->print_raw(" + ");
4982 opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val
4983 st->print_raw(" << ");
4984 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
4985 st->print_raw("]\n\t");
4986}
4987#endif
4988#ifndef PRODUCT
4989void jumpXtnd_addrNode::format(PhaseRegAlloc *ra, outputStream *st) const {
4990 // Start at oper_input_base() and count operands
4991 unsigned idx0 = 1;
4992 unsigned idx1 = 1; // shift
4993 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // offset
4994 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dest
4995 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
4996 st->print_raw("leaq ");
4997 opnd_array(4)->ext_format(ra, this,idx4, st); // dest
4998 st->print_raw(", [");
4999 st->print("constant table base + #%d", constant_offset_unchecked());
5000 st->print_raw("]\n\t");
5001 st->print_raw("jmp [");
5002 opnd_array(4)->ext_format(ra, this,idx4, st); // dest
5003 st->print_raw(" + ");
5004 opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val
5005 st->print_raw(" << ");
5006 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
5007 st->print_raw(" + ");
5008 opnd_array(3)->ext_format(ra, this,idx3, st); // offset
5009 st->print_raw("]\n\t");
5010}
5011#endif
5012#ifndef PRODUCT
5013void jumpXtndNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5014 // Start at oper_input_base() and count operands
5015 unsigned idx0 = 1;
5016 unsigned idx1 = 1; // dest
5017 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
5018 st->print_raw("leaq ");
5019 opnd_array(2)->ext_format(ra, this,idx2, st); // dest
5020 st->print_raw(", [");
5021 st->print("constant table base + #%d", constant_offset_unchecked());
5022 st->print_raw("]\n\t");
5023 st->print_raw("jmp [");
5024 opnd_array(2)->ext_format(ra, this,idx2, st); // dest
5025 st->print_raw(" + ");
5026 opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val
5027 st->print_raw("]\n\t");
5028}
5029#endif
5030#ifndef PRODUCT
5031void cmovI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5032 // Start at oper_input_base() and count operands
5033 unsigned idx0 = 1;
5034 unsigned idx1 = 1; // cop
5035 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5036 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5037 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5038 st->print_raw("cmovl");
5039 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5040 st->print_raw(" ");
5041 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5042 st->print_raw(", ");
5043 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5044 st->print_raw("\t# signed, int");
5045}
5046#endif
5047#ifndef PRODUCT
5048void cmovI_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5049 // Start at oper_input_base() and count operands
5050 unsigned idx0 = 1;
5051 unsigned idx1 = 1; // cop
5052 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5053 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5054 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5055 st->print_raw("cmovl");
5056 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5057 st->print_raw(" ");
5058 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5059 st->print_raw(", ");
5060 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5061 st->print_raw("\t# unsigned, int");
5062}
5063#endif
5064#ifndef PRODUCT
5065void cmovI_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5066}
5067#endif
5068#ifndef PRODUCT
5069void cmovI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5070 // Start at oper_input_base() and count operands
5071 unsigned idx0 = 2;
5072 unsigned idx1 = 2; // cop
5073 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5074 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5075 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5076 st->print_raw("cmovl");
5077 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5078 st->print_raw(" ");
5079 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5080 st->print_raw(", ");
5081 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5082 st->print_raw("\t# signed, int");
5083}
5084#endif
5085#ifndef PRODUCT
5086void cmovI_memUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5087 // Start at oper_input_base() and count operands
5088 unsigned idx0 = 2;
5089 unsigned idx1 = 2; // cop
5090 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5091 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5092 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5093 st->print_raw("cmovl");
5094 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5095 st->print_raw(" ");
5096 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5097 st->print_raw(", ");
5098 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5099 st->print_raw("\t# unsigned, int");
5100}
5101#endif
5102#ifndef PRODUCT
5103void cmovI_memUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5104}
5105#endif
5106#ifndef PRODUCT
5107void cmovN_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5108 // Start at oper_input_base() and count operands
5109 unsigned idx0 = 1;
5110 unsigned idx1 = 1; // cop
5111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5112 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5113 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5114 st->print_raw("cmovl");
5115 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5116 st->print_raw(" ");
5117 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5118 st->print_raw(", ");
5119 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5120 st->print_raw("\t# signed, compressed ptr");
5121}
5122#endif
5123#ifndef PRODUCT
5124void cmovN_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5125 // Start at oper_input_base() and count operands
5126 unsigned idx0 = 1;
5127 unsigned idx1 = 1; // cop
5128 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5129 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5130 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5131 st->print_raw("cmovl");
5132 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5133 st->print_raw(" ");
5134 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5135 st->print_raw(", ");
5136 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5137 st->print_raw("\t# unsigned, compressed ptr");
5138}
5139#endif
5140#ifndef PRODUCT
5141void cmovN_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5142}
5143#endif
5144#ifndef PRODUCT
5145void cmovP_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5146 // Start at oper_input_base() and count operands
5147 unsigned idx0 = 1;
5148 unsigned idx1 = 1; // cop
5149 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5150 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5151 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5152 st->print_raw("cmovq");
5153 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5154 st->print_raw(" ");
5155 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5156 st->print_raw(", ");
5157 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5158 st->print_raw("\t# signed, ptr");
5159}
5160#endif
5161#ifndef PRODUCT
5162void cmovP_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5163 // Start at oper_input_base() and count operands
5164 unsigned idx0 = 1;
5165 unsigned idx1 = 1; // cop
5166 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5167 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5168 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5169 st->print_raw("cmovq");
5170 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5171 st->print_raw(" ");
5172 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5173 st->print_raw(", ");
5174 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5175 st->print_raw("\t# unsigned, ptr");
5176}
5177#endif
5178#ifndef PRODUCT
5179void cmovP_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5180}
5181#endif
5182#ifndef PRODUCT
5183void cmovL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5184 // Start at oper_input_base() and count operands
5185 unsigned idx0 = 1;
5186 unsigned idx1 = 1; // cop
5187 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5188 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5189 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5190 st->print_raw("cmovq");
5191 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5192 st->print_raw(" ");
5193 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5194 st->print_raw(", ");
5195 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5196 st->print_raw("\t# signed, long");
5197}
5198#endif
5199#ifndef PRODUCT
5200void cmovL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5201 // Start at oper_input_base() and count operands
5202 unsigned idx0 = 2;
5203 unsigned idx1 = 2; // cop
5204 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5205 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5206 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5207 st->print_raw("cmovq");
5208 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5209 st->print_raw(" ");
5210 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5211 st->print_raw(", ");
5212 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5213 st->print_raw("\t# signed, long");
5214}
5215#endif
5216#ifndef PRODUCT
5217void cmovL_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5218 // Start at oper_input_base() and count operands
5219 unsigned idx0 = 1;
5220 unsigned idx1 = 1; // cop
5221 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5222 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5223 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5224 st->print_raw("cmovq");
5225 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5226 st->print_raw(" ");
5227 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5228 st->print_raw(", ");
5229 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5230 st->print_raw("\t# unsigned, long");
5231}
5232#endif
5233#ifndef PRODUCT
5234void cmovL_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5235}
5236#endif
5237#ifndef PRODUCT
5238void cmovL_memUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5239 // Start at oper_input_base() and count operands
5240 unsigned idx0 = 2;
5241 unsigned idx1 = 2; // cop
5242 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5243 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5244 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5245 st->print_raw("cmovq");
5246 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5247 st->print_raw(" ");
5248 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5249 st->print_raw(", ");
5250 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5251 st->print_raw("\t# unsigned, long");
5252}
5253#endif
5254#ifndef PRODUCT
5255void cmovL_memUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5256}
5257#endif
5258#ifndef PRODUCT
5259void cmovF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5260 // Start at oper_input_base() and count operands
5261 unsigned idx0 = 1;
5262 unsigned idx1 = 1; // cop
5263 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5264 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5265 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5266 st->print_raw("jn");
5267 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5268 st->print_raw(" skip\t# signed cmove float\n\t");
5269 st->print_raw("movss ");
5270 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5271 st->print_raw(", ");
5272 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5273 st->print_raw("\n");
5274 st->print_raw("skip:");
5275}
5276#endif
5277#ifndef PRODUCT
5278void cmovF_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5279 // Start at oper_input_base() and count operands
5280 unsigned idx0 = 1;
5281 unsigned idx1 = 1; // cop
5282 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5283 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5284 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5285 st->print_raw("jn");
5286 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5287 st->print_raw(" skip\t# unsigned cmove float\n\t");
5288 st->print_raw("movss ");
5289 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5290 st->print_raw(", ");
5291 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5292 st->print_raw("\n");
5293 st->print_raw("skip:");
5294}
5295#endif
5296#ifndef PRODUCT
5297void cmovF_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5298}
5299#endif
5300#ifndef PRODUCT
5301void cmovD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5302 // Start at oper_input_base() and count operands
5303 unsigned idx0 = 1;
5304 unsigned idx1 = 1; // cop
5305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5306 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5307 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5308 st->print_raw("jn");
5309 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5310 st->print_raw(" skip\t# signed cmove double\n\t");
5311 st->print_raw("movsd ");
5312 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5313 st->print_raw(", ");
5314 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5315 st->print_raw("\n");
5316 st->print_raw("skip:");
5317}
5318#endif
5319#ifndef PRODUCT
5320void cmovD_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5321 // Start at oper_input_base() and count operands
5322 unsigned idx0 = 1;
5323 unsigned idx1 = 1; // cop
5324 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
5325 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
5326 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
5327 st->print_raw("jn");
5328 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
5329 st->print_raw(" skip\t# unsigned cmove double\n\t");
5330 st->print_raw("movsd ");
5331 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
5332 st->print_raw(", ");
5333 opnd_array(4)->ext_format(ra, this,idx4, st); // src
5334 st->print_raw("\n");
5335 st->print_raw("skip:");
5336}
5337#endif
5338#ifndef PRODUCT
5339void cmovD_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5340}
5341#endif
5342#ifndef PRODUCT
5343void addI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5344 // Start at oper_input_base() and count operands
5345 unsigned idx0 = 1;
5346 unsigned idx1 = 1; // dst
5347 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5348 st->print_raw("addl ");
5349 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5350 st->print_raw(", ");
5351 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5352 st->print_raw("\t# int");
5353}
5354#endif
5355#ifndef PRODUCT
5356void addI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5357 // Start at oper_input_base() and count operands
5358 unsigned idx0 = 1;
5359 unsigned idx1 = 1; // dst
5360 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5361 st->print_raw("addl ");
5362 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5363 st->print_raw(", ");
5364 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5365 st->print_raw("\t# int");
5366}
5367#endif
5368#ifndef PRODUCT
5369void addI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5370 // Start at oper_input_base() and count operands
5371 unsigned idx0 = 2;
5372 unsigned idx1 = 2; // dst
5373 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5374 st->print_raw("addl ");
5375 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5376 st->print_raw(", ");
5377 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5378 st->print_raw("\t# int");
5379}
5380#endif
5381#ifndef PRODUCT
5382void addI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
5383 // Start at oper_input_base() and count operands
5384 unsigned idx0 = 2;
5385 unsigned idx1 = 2; // src
5386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
5387 st->print_raw("addl ");
5388 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
5389 st->print_raw(", ");
5390 opnd_array(1)->ext_format(ra, this,idx1, st); // src
5391 st->print_raw("\t# int");
5392}
5393#endif
5394#ifndef PRODUCT
5395void addI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5396 // Start at oper_input_base() and count operands
5397 unsigned idx0 = 2;
5398 unsigned idx1 = 2; // dst
5399 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5400 st->print_raw("addl ");
5401 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5402 st->print_raw(", ");
5403 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5404 st->print_raw("\t# int");
5405 if (ra->C->alias_type(adr_type())->field() != NULL) {
5406 ciField* f = ra->C->alias_type(adr_type())->field();
5407 st->print(" ! Field: ");
5408 if (f->is_volatile())
5409 st->print("volatile ");
5410 f->holder()->name()->print_symbol_on(st);
5411 st->print(".");
5412 f->name()->print_symbol_on(st);
5413 if (f->is_constant())
5414 st->print(" (constant)");
5415 } else {
5416 if (ra->C->alias_type(adr_type())->is_volatile())
5417 st->print(" volatile!");
5418 }
5419}
5420#endif
5421#ifndef PRODUCT
5422void addI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
5423 // Start at oper_input_base() and count operands
5424 unsigned idx0 = 2;
5425 unsigned idx1 = 2; // dst
5426 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5427 st->print_raw("addl ");
5428 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5429 st->print_raw(", ");
5430 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5431 st->print_raw("\t# int");
5432 if (ra->C->alias_type(adr_type())->field() != NULL) {
5433 ciField* f = ra->C->alias_type(adr_type())->field();
5434 st->print(" ! Field: ");
5435 if (f->is_volatile())
5436 st->print("volatile ");
5437 f->holder()->name()->print_symbol_on(st);
5438 st->print(".");
5439 f->name()->print_symbol_on(st);
5440 if (f->is_constant())
5441 st->print(" (constant)");
5442 } else {
5443 if (ra->C->alias_type(adr_type())->is_volatile())
5444 st->print(" volatile!");
5445 }
5446}
5447#endif
5448#ifndef PRODUCT
5449void addI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5450 // Start at oper_input_base() and count operands
5451 unsigned idx0 = 2;
5452 unsigned idx1 = 2; // dst
5453 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5454 st->print_raw("addl ");
5455 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5456 st->print_raw(", ");
5457 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5458 st->print_raw("\t# int");
5459 if (ra->C->alias_type(adr_type())->field() != NULL) {
5460 ciField* f = ra->C->alias_type(adr_type())->field();
5461 st->print(" ! Field: ");
5462 if (f->is_volatile())
5463 st->print("volatile ");
5464 f->holder()->name()->print_symbol_on(st);
5465 st->print(".");
5466 f->name()->print_symbol_on(st);
5467 if (f->is_constant())
5468 st->print(" (constant)");
5469 } else {
5470 if (ra->C->alias_type(adr_type())->is_volatile())
5471 st->print(" volatile!");
5472 }
5473}
5474#endif
5475#ifndef PRODUCT
5476void incI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5477 // Start at oper_input_base() and count operands
5478 unsigned idx0 = 1;
5479 unsigned idx1 = 1; // dst
5480 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5481 st->print_raw("incl ");
5482 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5483 st->print_raw("\t# int");
5484}
5485#endif
5486#ifndef PRODUCT
5487void incI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5488 // Start at oper_input_base() and count operands
5489 unsigned idx0 = 2;
5490 unsigned idx1 = 2; // dst
5491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5492 st->print_raw("incl ");
5493 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5494 st->print_raw("\t# int");
5495 if (ra->C->alias_type(adr_type())->field() != NULL) {
5496 ciField* f = ra->C->alias_type(adr_type())->field();
5497 st->print(" ! Field: ");
5498 if (f->is_volatile())
5499 st->print("volatile ");
5500 f->holder()->name()->print_symbol_on(st);
5501 st->print(".");
5502 f->name()->print_symbol_on(st);
5503 if (f->is_constant())
5504 st->print(" (constant)");
5505 } else {
5506 if (ra->C->alias_type(adr_type())->is_volatile())
5507 st->print(" volatile!");
5508 }
5509}
5510#endif
5511#ifndef PRODUCT
5512void decI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5513 // Start at oper_input_base() and count operands
5514 unsigned idx0 = 1;
5515 unsigned idx1 = 1; // dst
5516 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5517 st->print_raw("decl ");
5518 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5519 st->print_raw("\t# int");
5520}
5521#endif
5522#ifndef PRODUCT
5523void decI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5524 // Start at oper_input_base() and count operands
5525 unsigned idx0 = 2;
5526 unsigned idx1 = 2; // dst
5527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5528 st->print_raw("decl ");
5529 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5530 st->print_raw("\t# int");
5531 if (ra->C->alias_type(adr_type())->field() != NULL) {
5532 ciField* f = ra->C->alias_type(adr_type())->field();
5533 st->print(" ! Field: ");
5534 if (f->is_volatile())
5535 st->print("volatile ");
5536 f->holder()->name()->print_symbol_on(st);
5537 st->print(".");
5538 f->name()->print_symbol_on(st);
5539 if (f->is_constant())
5540 st->print(" (constant)");
5541 } else {
5542 if (ra->C->alias_type(adr_type())->is_volatile())
5543 st->print(" volatile!");
5544 }
5545}
5546#endif
5547#ifndef PRODUCT
5548void leaI_rReg_immINode::format(PhaseRegAlloc *ra, outputStream *st) const {
5549 // Start at oper_input_base() and count operands
5550 unsigned idx0 = 1;
5551 unsigned idx1 = 1; // src0
5552 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
5553 st->print_raw("addr32 leal ");
5554 opnd_array(0)->int_format(ra, this, st); // dst
5555 st->print_raw(", [");
5556 opnd_array(1)->ext_format(ra, this,idx1, st); // src0
5557 st->print_raw(" + ");
5558 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
5559 st->print_raw("]\t# int");
5560}
5561#endif
5562#ifndef PRODUCT
5563void addL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5564 // Start at oper_input_base() and count operands
5565 unsigned idx0 = 1;
5566 unsigned idx1 = 1; // dst
5567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5568 st->print_raw("addq ");
5569 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5570 st->print_raw(", ");
5571 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5572 st->print_raw("\t# long");
5573}
5574#endif
5575#ifndef PRODUCT
5576void addL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5577 // Start at oper_input_base() and count operands
5578 unsigned idx0 = 1;
5579 unsigned idx1 = 1; // dst
5580 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5581 st->print_raw("addq ");
5582 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5583 st->print_raw(", ");
5584 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5585 st->print_raw("\t# long");
5586}
5587#endif
5588#ifndef PRODUCT
5589void addL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5590 // Start at oper_input_base() and count operands
5591 unsigned idx0 = 2;
5592 unsigned idx1 = 2; // dst
5593 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5594 st->print_raw("addq ");
5595 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5596 st->print_raw(", ");
5597 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5598 st->print_raw("\t# long");
5599}
5600#endif
5601#ifndef PRODUCT
5602void addL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
5603 // Start at oper_input_base() and count operands
5604 unsigned idx0 = 2;
5605 unsigned idx1 = 2; // src
5606 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
5607 st->print_raw("addq ");
5608 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
5609 st->print_raw(", ");
5610 opnd_array(1)->ext_format(ra, this,idx1, st); // src
5611 st->print_raw("\t# long");
5612}
5613#endif
5614#ifndef PRODUCT
5615void addL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5616 // Start at oper_input_base() and count operands
5617 unsigned idx0 = 2;
5618 unsigned idx1 = 2; // dst
5619 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5620 st->print_raw("addq ");
5621 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5622 st->print_raw(", ");
5623 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5624 st->print_raw("\t# long");
5625 if (ra->C->alias_type(adr_type())->field() != NULL) {
5626 ciField* f = ra->C->alias_type(adr_type())->field();
5627 st->print(" ! Field: ");
5628 if (f->is_volatile())
5629 st->print("volatile ");
5630 f->holder()->name()->print_symbol_on(st);
5631 st->print(".");
5632 f->name()->print_symbol_on(st);
5633 if (f->is_constant())
5634 st->print(" (constant)");
5635 } else {
5636 if (ra->C->alias_type(adr_type())->is_volatile())
5637 st->print(" volatile!");
5638 }
5639}
5640#endif
5641#ifndef PRODUCT
5642void addL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
5643 // Start at oper_input_base() and count operands
5644 unsigned idx0 = 2;
5645 unsigned idx1 = 2; // dst
5646 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5647 st->print_raw("addq ");
5648 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5649 st->print_raw(", ");
5650 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5651 st->print_raw("\t# long");
5652 if (ra->C->alias_type(adr_type())->field() != NULL) {
5653 ciField* f = ra->C->alias_type(adr_type())->field();
5654 st->print(" ! Field: ");
5655 if (f->is_volatile())
5656 st->print("volatile ");
5657 f->holder()->name()->print_symbol_on(st);
5658 st->print(".");
5659 f->name()->print_symbol_on(st);
5660 if (f->is_constant())
5661 st->print(" (constant)");
5662 } else {
5663 if (ra->C->alias_type(adr_type())->is_volatile())
5664 st->print(" volatile!");
5665 }
5666}
5667#endif
5668#ifndef PRODUCT
5669void addL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5670 // Start at oper_input_base() and count operands
5671 unsigned idx0 = 2;
5672 unsigned idx1 = 2; // dst
5673 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5674 st->print_raw("addq ");
5675 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5676 st->print_raw(", ");
5677 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5678 st->print_raw("\t# long");
5679 if (ra->C->alias_type(adr_type())->field() != NULL) {
5680 ciField* f = ra->C->alias_type(adr_type())->field();
5681 st->print(" ! Field: ");
5682 if (f->is_volatile())
5683 st->print("volatile ");
5684 f->holder()->name()->print_symbol_on(st);
5685 st->print(".");
5686 f->name()->print_symbol_on(st);
5687 if (f->is_constant())
5688 st->print(" (constant)");
5689 } else {
5690 if (ra->C->alias_type(adr_type())->is_volatile())
5691 st->print(" volatile!");
5692 }
5693}
5694#endif
5695#ifndef PRODUCT
5696void incL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5697 // Start at oper_input_base() and count operands
5698 unsigned idx0 = 1;
5699 unsigned idx1 = 1; // dst
5700 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5701 st->print_raw("incq ");
5702 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5703 st->print_raw("\t# long");
5704}
5705#endif
5706#ifndef PRODUCT
5707void incL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5708 // Start at oper_input_base() and count operands
5709 unsigned idx0 = 2;
5710 unsigned idx1 = 2; // dst
5711 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5712 st->print_raw("incq ");
5713 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5714 st->print_raw("\t# long");
5715 if (ra->C->alias_type(adr_type())->field() != NULL) {
5716 ciField* f = ra->C->alias_type(adr_type())->field();
5717 st->print(" ! Field: ");
5718 if (f->is_volatile())
5719 st->print("volatile ");
5720 f->holder()->name()->print_symbol_on(st);
5721 st->print(".");
5722 f->name()->print_symbol_on(st);
5723 if (f->is_constant())
5724 st->print(" (constant)");
5725 } else {
5726 if (ra->C->alias_type(adr_type())->is_volatile())
5727 st->print(" volatile!");
5728 }
5729}
5730#endif
5731#ifndef PRODUCT
5732void decL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5733 // Start at oper_input_base() and count operands
5734 unsigned idx0 = 1;
5735 unsigned idx1 = 1; // dst
5736 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5737 st->print_raw("decq ");
5738 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5739 st->print_raw("\t# long");
5740}
5741#endif
5742#ifndef PRODUCT
5743void decL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5744 // Start at oper_input_base() and count operands
5745 unsigned idx0 = 2;
5746 unsigned idx1 = 2; // dst
5747 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5748 st->print_raw("decq ");
5749 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5750 st->print_raw("\t# long");
5751 if (ra->C->alias_type(adr_type())->field() != NULL) {
5752 ciField* f = ra->C->alias_type(adr_type())->field();
5753 st->print(" ! Field: ");
5754 if (f->is_volatile())
5755 st->print("volatile ");
5756 f->holder()->name()->print_symbol_on(st);
5757 st->print(".");
5758 f->name()->print_symbol_on(st);
5759 if (f->is_constant())
5760 st->print(" (constant)");
5761 } else {
5762 if (ra->C->alias_type(adr_type())->is_volatile())
5763 st->print(" volatile!");
5764 }
5765}
5766#endif
5767#ifndef PRODUCT
5768void leaL_rReg_immLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5769 // Start at oper_input_base() and count operands
5770 unsigned idx0 = 1;
5771 unsigned idx1 = 1; // src0
5772 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
5773 st->print_raw("leaq ");
5774 opnd_array(0)->int_format(ra, this, st); // dst
5775 st->print_raw(", [");
5776 opnd_array(1)->ext_format(ra, this,idx1, st); // src0
5777 st->print_raw(" + ");
5778 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
5779 st->print_raw("]\t# long");
5780}
5781#endif
5782#ifndef PRODUCT
5783void addP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5784 // Start at oper_input_base() and count operands
5785 unsigned idx0 = 2;
5786 unsigned idx1 = 2; // dst
5787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5788 st->print_raw("addq ");
5789 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5790 st->print_raw(", ");
5791 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5792 st->print_raw("\t# ptr");
5793}
5794#endif
5795#ifndef PRODUCT
5796void addP_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5797 // Start at oper_input_base() and count operands
5798 unsigned idx0 = 2;
5799 unsigned idx1 = 2; // dst
5800 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
5801 st->print_raw("addq ");
5802 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5803 st->print_raw(", ");
5804 opnd_array(2)->ext_format(ra, this,idx2, st); // src
5805 st->print_raw("\t# ptr");
5806}
5807#endif
5808#ifndef PRODUCT
5809void leaP_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5810 // Start at oper_input_base() and count operands
5811 unsigned idx0 = 2;
5812 unsigned idx1 = 2; // src0
5813 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
5814 st->print_raw("leaq ");
5815 opnd_array(0)->int_format(ra, this, st); // dst
5816 st->print_raw(", [");
5817 opnd_array(1)->ext_format(ra, this,idx1, st); // src0
5818 st->print_raw(" + ");
5819 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
5820 st->print_raw("]\t# ptr");
5821}
5822#endif
5823#ifndef PRODUCT
5824void checkCastPPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5825 // Start at oper_input_base() and count operands
5826 unsigned idx0 = 1;
5827 unsigned idx1 = 1; // dst
5828 st->print_raw("# checkcastPP of ");
5829 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5830}
5831#endif
5832#ifndef PRODUCT
5833void castPPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5834 // Start at oper_input_base() and count operands
5835 unsigned idx0 = 1;
5836 unsigned idx1 = 1; // dst
5837 st->print_raw("# castPP of ");
5838 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5839}
5840#endif
5841#ifndef PRODUCT
5842void castIINode::format(PhaseRegAlloc *ra, outputStream *st) const {
5843 // Start at oper_input_base() and count operands
5844 unsigned idx0 = 1;
5845 unsigned idx1 = 1; // dst
5846 st->print_raw("# castII of ");
5847 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
5848}
5849#endif
5850#ifndef PRODUCT
5851void loadPLockedNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5852 // Start at oper_input_base() and count operands
5853 unsigned idx0 = 2;
5854 unsigned idx1 = 2; // mem
5855 st->print_raw("movq ");
5856 opnd_array(0)->int_format(ra, this, st); // dst
5857 st->print_raw(", ");
5858 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5859 st->print_raw("\t# ptr locked");
5860 if (ra->C->alias_type(adr_type())->field() != NULL) {
5861 ciField* f = ra->C->alias_type(adr_type())->field();
5862 st->print(" ! Field: ");
5863 if (f->is_volatile())
5864 st->print("volatile ");
5865 f->holder()->name()->print_symbol_on(st);
5866 st->print(".");
5867 f->name()->print_symbol_on(st);
5868 if (f->is_constant())
5869 st->print(" (constant)");
5870 } else {
5871 if (ra->C->alias_type(adr_type())->is_volatile())
5872 st->print(" volatile!");
5873 }
5874}
5875#endif
5876#ifndef PRODUCT
5877void storePConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5878 // Start at oper_input_base() and count operands
5879 unsigned idx0 = 2;
5880 unsigned idx1 = 2; // heap_top_ptr
5881 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5882 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5883 st->print_raw("cmpxchgq ");
5884 opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr
5885 st->print_raw(", ");
5886 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5887 st->print_raw("\t# (ptr) ");
5888 st->print_raw("If rax == ");
5889 opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr
5890 st->print_raw(" then store ");
5891 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5892 st->print_raw(" into ");
5893 opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr
5894}
5895#endif
5896#ifndef PRODUCT
5897void storeIConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5898 // Start at oper_input_base() and count operands
5899 unsigned idx0 = 2;
5900 unsigned idx1 = 2; // mem
5901 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5902 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5903 st->print_raw("cmpxchgl ");
5904 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5905 st->print_raw(", ");
5906 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5907 st->print_raw("\t# If rax == ");
5908 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5909 st->print_raw(" then store ");
5910 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5911 st->print_raw(" into ");
5912 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5913}
5914#endif
5915#ifndef PRODUCT
5916void storeLConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5917 // Start at oper_input_base() and count operands
5918 unsigned idx0 = 2;
5919 unsigned idx1 = 2; // mem
5920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5921 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5922 st->print_raw("cmpxchgq ");
5923 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5924 st->print_raw(", ");
5925 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5926 st->print_raw("\t# If rax == ");
5927 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5928 st->print_raw(" then store ");
5929 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5930 st->print_raw(" into ");
5931 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
5932}
5933#endif
5934#ifndef PRODUCT
5935void compareAndSwapPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5936 // Start at oper_input_base() and count operands
5937 unsigned idx0 = 2;
5938 unsigned idx1 = 2; // mem_ptr
5939 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5940 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5941 st->print_raw("cmpxchgq ");
5942 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5943 st->print_raw(",");
5944 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5945 st->print_raw("\t# ");
5946 st->print_raw("If rax == ");
5947 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5948 st->print_raw(" then store ");
5949 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5950 st->print_raw(" into ");
5951 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5952 st->print_raw("\n\t");
5953 st->print_raw("sete ");
5954 opnd_array(0)->int_format(ra, this, st); // res
5955 st->print_raw("\n\t");
5956 st->print_raw("movzbl ");
5957 opnd_array(0)->int_format(ra, this, st); // res
5958 st->print_raw(", ");
5959 opnd_array(0)->int_format(ra, this, st); // res
5960}
5961#endif
5962#ifndef PRODUCT
5963void compareAndSwapP_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
5964 // Start at oper_input_base() and count operands
5965 unsigned idx0 = 2;
5966 unsigned idx1 = 2; // mem_ptr
5967 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5968 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5969 st->print_raw("cmpxchgq ");
5970 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5971 st->print_raw(",");
5972 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5973 st->print_raw("\t# ");
5974 st->print_raw("If rax == ");
5975 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5976 st->print_raw(" then store ");
5977 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
5978 st->print_raw(" into ");
5979 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5980 st->print_raw("\n\t");
5981 st->print_raw("sete ");
5982 opnd_array(0)->int_format(ra, this, st); // res
5983 st->print_raw("\n\t");
5984 st->print_raw("movzbl ");
5985 opnd_array(0)->int_format(ra, this, st); // res
5986 st->print_raw(", ");
5987 opnd_array(0)->int_format(ra, this, st); // res
5988}
5989#endif
5990#ifndef PRODUCT
5991void compareAndSwapLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
5992 // Start at oper_input_base() and count operands
5993 unsigned idx0 = 2;
5994 unsigned idx1 = 2; // mem_ptr
5995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
5996 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
5997 st->print_raw("cmpxchgq ");
5998 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
5999 st->print_raw(",");
6000 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6001 st->print_raw("\t# ");
6002 st->print_raw("If rax == ");
6003 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6004 st->print_raw(" then store ");
6005 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6006 st->print_raw(" into ");
6007 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6008 st->print_raw("\n\t");
6009 st->print_raw("sete ");
6010 opnd_array(0)->int_format(ra, this, st); // res
6011 st->print_raw("\n\t");
6012 st->print_raw("movzbl ");
6013 opnd_array(0)->int_format(ra, this, st); // res
6014 st->print_raw(", ");
6015 opnd_array(0)->int_format(ra, this, st); // res
6016}
6017#endif
6018#ifndef PRODUCT
6019void compareAndSwapL_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6020 // Start at oper_input_base() and count operands
6021 unsigned idx0 = 2;
6022 unsigned idx1 = 2; // mem_ptr
6023 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6024 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6025 st->print_raw("cmpxchgq ");
6026 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6027 st->print_raw(",");
6028 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6029 st->print_raw("\t# ");
6030 st->print_raw("If rax == ");
6031 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6032 st->print_raw(" then store ");
6033 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6034 st->print_raw(" into ");
6035 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6036 st->print_raw("\n\t");
6037 st->print_raw("sete ");
6038 opnd_array(0)->int_format(ra, this, st); // res
6039 st->print_raw("\n\t");
6040 st->print_raw("movzbl ");
6041 opnd_array(0)->int_format(ra, this, st); // res
6042 st->print_raw(", ");
6043 opnd_array(0)->int_format(ra, this, st); // res
6044}
6045#endif
6046#ifndef PRODUCT
6047void compareAndSwapINode::format(PhaseRegAlloc *ra, outputStream *st) const {
6048 // Start at oper_input_base() and count operands
6049 unsigned idx0 = 2;
6050 unsigned idx1 = 2; // mem_ptr
6051 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6052 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6053 st->print_raw("cmpxchgl ");
6054 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6055 st->print_raw(",");
6056 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6057 st->print_raw("\t# ");
6058 st->print_raw("If rax == ");
6059 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6060 st->print_raw(" then store ");
6061 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6062 st->print_raw(" into ");
6063 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6064 st->print_raw("\n\t");
6065 st->print_raw("sete ");
6066 opnd_array(0)->int_format(ra, this, st); // res
6067 st->print_raw("\n\t");
6068 st->print_raw("movzbl ");
6069 opnd_array(0)->int_format(ra, this, st); // res
6070 st->print_raw(", ");
6071 opnd_array(0)->int_format(ra, this, st); // res
6072}
6073#endif
6074#ifndef PRODUCT
6075void compareAndSwapI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6076 // Start at oper_input_base() and count operands
6077 unsigned idx0 = 2;
6078 unsigned idx1 = 2; // mem_ptr
6079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6080 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6081 st->print_raw("cmpxchgl ");
6082 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6083 st->print_raw(",");
6084 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6085 st->print_raw("\t# ");
6086 st->print_raw("If rax == ");
6087 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6088 st->print_raw(" then store ");
6089 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6090 st->print_raw(" into ");
6091 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6092 st->print_raw("\n\t");
6093 st->print_raw("sete ");
6094 opnd_array(0)->int_format(ra, this, st); // res
6095 st->print_raw("\n\t");
6096 st->print_raw("movzbl ");
6097 opnd_array(0)->int_format(ra, this, st); // res
6098 st->print_raw(", ");
6099 opnd_array(0)->int_format(ra, this, st); // res
6100}
6101#endif
6102#ifndef PRODUCT
6103void compareAndSwapBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6104 // Start at oper_input_base() and count operands
6105 unsigned idx0 = 2;
6106 unsigned idx1 = 2; // mem_ptr
6107 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6108 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6109 st->print_raw("cmpxchgb ");
6110 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6111 st->print_raw(",");
6112 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6113 st->print_raw("\t# ");
6114 st->print_raw("If rax == ");
6115 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6116 st->print_raw(" then store ");
6117 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6118 st->print_raw(" into ");
6119 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6120 st->print_raw("\n\t");
6121 st->print_raw("sete ");
6122 opnd_array(0)->int_format(ra, this, st); // res
6123 st->print_raw("\n\t");
6124 st->print_raw("movzbl ");
6125 opnd_array(0)->int_format(ra, this, st); // res
6126 st->print_raw(", ");
6127 opnd_array(0)->int_format(ra, this, st); // res
6128}
6129#endif
6130#ifndef PRODUCT
6131void compareAndSwapB_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6132 // Start at oper_input_base() and count operands
6133 unsigned idx0 = 2;
6134 unsigned idx1 = 2; // mem_ptr
6135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6136 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6137 st->print_raw("cmpxchgb ");
6138 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6139 st->print_raw(",");
6140 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6141 st->print_raw("\t# ");
6142 st->print_raw("If rax == ");
6143 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6144 st->print_raw(" then store ");
6145 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6146 st->print_raw(" into ");
6147 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6148 st->print_raw("\n\t");
6149 st->print_raw("sete ");
6150 opnd_array(0)->int_format(ra, this, st); // res
6151 st->print_raw("\n\t");
6152 st->print_raw("movzbl ");
6153 opnd_array(0)->int_format(ra, this, st); // res
6154 st->print_raw(", ");
6155 opnd_array(0)->int_format(ra, this, st); // res
6156}
6157#endif
6158#ifndef PRODUCT
6159void compareAndSwapSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6160 // Start at oper_input_base() and count operands
6161 unsigned idx0 = 2;
6162 unsigned idx1 = 2; // mem_ptr
6163 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6164 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6165 st->print_raw("cmpxchgw ");
6166 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6167 st->print_raw(",");
6168 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6169 st->print_raw("\t# ");
6170 st->print_raw("If rax == ");
6171 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6172 st->print_raw(" then store ");
6173 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6174 st->print_raw(" into ");
6175 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6176 st->print_raw("\n\t");
6177 st->print_raw("sete ");
6178 opnd_array(0)->int_format(ra, this, st); // res
6179 st->print_raw("\n\t");
6180 st->print_raw("movzbl ");
6181 opnd_array(0)->int_format(ra, this, st); // res
6182 st->print_raw(", ");
6183 opnd_array(0)->int_format(ra, this, st); // res
6184}
6185#endif
6186#ifndef PRODUCT
6187void compareAndSwapS_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6188 // Start at oper_input_base() and count operands
6189 unsigned idx0 = 2;
6190 unsigned idx1 = 2; // mem_ptr
6191 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6192 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6193 st->print_raw("cmpxchgw ");
6194 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6195 st->print_raw(",");
6196 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6197 st->print_raw("\t# ");
6198 st->print_raw("If rax == ");
6199 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6200 st->print_raw(" then store ");
6201 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6202 st->print_raw(" into ");
6203 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6204 st->print_raw("\n\t");
6205 st->print_raw("sete ");
6206 opnd_array(0)->int_format(ra, this, st); // res
6207 st->print_raw("\n\t");
6208 st->print_raw("movzbl ");
6209 opnd_array(0)->int_format(ra, this, st); // res
6210 st->print_raw(", ");
6211 opnd_array(0)->int_format(ra, this, st); // res
6212}
6213#endif
6214#ifndef PRODUCT
6215void compareAndSwapNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6216 // Start at oper_input_base() and count operands
6217 unsigned idx0 = 2;
6218 unsigned idx1 = 2; // mem_ptr
6219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6220 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6221 st->print_raw("cmpxchgl ");
6222 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6223 st->print_raw(",");
6224 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6225 st->print_raw("\t# ");
6226 st->print_raw("If rax == ");
6227 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6228 st->print_raw(" then store ");
6229 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6230 st->print_raw(" into ");
6231 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6232 st->print_raw("\n\t");
6233 st->print_raw("sete ");
6234 opnd_array(0)->int_format(ra, this, st); // res
6235 st->print_raw("\n\t");
6236 st->print_raw("movzbl ");
6237 opnd_array(0)->int_format(ra, this, st); // res
6238 st->print_raw(", ");
6239 opnd_array(0)->int_format(ra, this, st); // res
6240}
6241#endif
6242#ifndef PRODUCT
6243void compareAndSwapN_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6244 // Start at oper_input_base() and count operands
6245 unsigned idx0 = 2;
6246 unsigned idx1 = 2; // mem_ptr
6247 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6248 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6249 st->print_raw("cmpxchgl ");
6250 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6251 st->print_raw(",");
6252 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6253 st->print_raw("\t# ");
6254 st->print_raw("If rax == ");
6255 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6256 st->print_raw(" then store ");
6257 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6258 st->print_raw(" into ");
6259 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6260 st->print_raw("\n\t");
6261 st->print_raw("sete ");
6262 opnd_array(0)->int_format(ra, this, st); // res
6263 st->print_raw("\n\t");
6264 st->print_raw("movzbl ");
6265 opnd_array(0)->int_format(ra, this, st); // res
6266 st->print_raw(", ");
6267 opnd_array(0)->int_format(ra, this, st); // res
6268}
6269#endif
6270#ifndef PRODUCT
6271void compareAndExchangeBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6272 // Start at oper_input_base() and count operands
6273 unsigned idx0 = 2;
6274 unsigned idx1 = 2; // mem_ptr
6275 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6276 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6277 st->print_raw("cmpxchgb ");
6278 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6279 st->print_raw(",");
6280 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6281 st->print_raw("\t# ");
6282 st->print_raw("If rax == ");
6283 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6284 st->print_raw(" then store ");
6285 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6286 st->print_raw(" into ");
6287 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6288 st->print_raw("\n\t");
6289}
6290#endif
6291#ifndef PRODUCT
6292void compareAndExchangeSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6293 // Start at oper_input_base() and count operands
6294 unsigned idx0 = 2;
6295 unsigned idx1 = 2; // mem_ptr
6296 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6297 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6298 st->print_raw("cmpxchgw ");
6299 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6300 st->print_raw(",");
6301 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6302 st->print_raw("\t# ");
6303 st->print_raw("If rax == ");
6304 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6305 st->print_raw(" then store ");
6306 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6307 st->print_raw(" into ");
6308 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6309 st->print_raw("\n\t");
6310}
6311#endif
6312#ifndef PRODUCT
6313void compareAndExchangeINode::format(PhaseRegAlloc *ra, outputStream *st) const {
6314 // Start at oper_input_base() and count operands
6315 unsigned idx0 = 2;
6316 unsigned idx1 = 2; // mem_ptr
6317 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6318 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6319 st->print_raw("cmpxchgl ");
6320 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6321 st->print_raw(",");
6322 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6323 st->print_raw("\t# ");
6324 st->print_raw("If rax == ");
6325 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6326 st->print_raw(" then store ");
6327 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6328 st->print_raw(" into ");
6329 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6330 st->print_raw("\n\t");
6331}
6332#endif
6333#ifndef PRODUCT
6334void compareAndExchangeLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6335 // Start at oper_input_base() and count operands
6336 unsigned idx0 = 2;
6337 unsigned idx1 = 2; // mem_ptr
6338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6339 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6340 st->print_raw("cmpxchgq ");
6341 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6342 st->print_raw(",");
6343 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6344 st->print_raw("\t# ");
6345 st->print_raw("If rax == ");
6346 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6347 st->print_raw(" then store ");
6348 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6349 st->print_raw(" into ");
6350 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6351 st->print_raw("\n\t");
6352}
6353#endif
6354#ifndef PRODUCT
6355void compareAndExchangeNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6356 // Start at oper_input_base() and count operands
6357 unsigned idx0 = 2;
6358 unsigned idx1 = 2; // mem_ptr
6359 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6360 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6361 st->print_raw("cmpxchgl ");
6362 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6363 st->print_raw(",");
6364 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6365 st->print_raw("\t# ");
6366 st->print_raw("If rax == ");
6367 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6368 st->print_raw(" then store ");
6369 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6370 st->print_raw(" into ");
6371 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6372 st->print_raw("\n\t");
6373}
6374#endif
6375#ifndef PRODUCT
6376void compareAndExchangePNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6377 // Start at oper_input_base() and count operands
6378 unsigned idx0 = 2;
6379 unsigned idx1 = 2; // mem_ptr
6380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
6381 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
6382 st->print_raw("cmpxchgq ");
6383 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6384 st->print_raw(",");
6385 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6386 st->print_raw("\t# ");
6387 st->print_raw("If rax == ");
6388 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6389 st->print_raw(" then store ");
6390 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
6391 st->print_raw(" into ");
6392 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
6393 st->print_raw("\n\t");
6394}
6395#endif
6396#ifndef PRODUCT
6397void xaddB_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6398 // Start at oper_input_base() and count operands
6399 unsigned idx0 = 2;
6400 unsigned idx1 = 2; // mem
6401 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
6402 st->print_raw("ADDB [");
6403 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6404 st->print_raw("],");
6405 opnd_array(2)->ext_format(ra, this,idx2, st); // add
6406}
6407#endif
6408#ifndef PRODUCT
6409void xaddBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6410 // Start at oper_input_base() and count operands
6411 unsigned idx0 = 2;
6412 unsigned idx1 = 2; // mem
6413 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6414 st->print_raw("XADDB [");
6415 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6416 st->print_raw("],");
6417 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6418}
6419#endif
6420#ifndef PRODUCT
6421void xaddS_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6422 // Start at oper_input_base() and count operands
6423 unsigned idx0 = 2;
6424 unsigned idx1 = 2; // mem
6425 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
6426 st->print_raw("ADDW [");
6427 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6428 st->print_raw("],");
6429 opnd_array(2)->ext_format(ra, this,idx2, st); // add
6430}
6431#endif
6432#ifndef PRODUCT
6433void xaddSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6434 // Start at oper_input_base() and count operands
6435 unsigned idx0 = 2;
6436 unsigned idx1 = 2; // mem
6437 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6438 st->print_raw("XADDW [");
6439 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6440 st->print_raw("],");
6441 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6442}
6443#endif
6444#ifndef PRODUCT
6445void xaddI_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6446 // Start at oper_input_base() and count operands
6447 unsigned idx0 = 2;
6448 unsigned idx1 = 2; // mem
6449 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
6450 st->print_raw("ADDL [");
6451 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6452 st->print_raw("],");
6453 opnd_array(2)->ext_format(ra, this,idx2, st); // add
6454}
6455#endif
6456#ifndef PRODUCT
6457void xaddINode::format(PhaseRegAlloc *ra, outputStream *st) const {
6458 // Start at oper_input_base() and count operands
6459 unsigned idx0 = 2;
6460 unsigned idx1 = 2; // mem
6461 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6462 st->print_raw("XADDL [");
6463 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6464 st->print_raw("],");
6465 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6466}
6467#endif
6468#ifndef PRODUCT
6469void xaddL_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6470 // Start at oper_input_base() and count operands
6471 unsigned idx0 = 2;
6472 unsigned idx1 = 2; // mem
6473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
6474 st->print_raw("ADDQ [");
6475 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6476 st->print_raw("],");
6477 opnd_array(2)->ext_format(ra, this,idx2, st); // add
6478}
6479#endif
6480#ifndef PRODUCT
6481void xaddLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6482 // Start at oper_input_base() and count operands
6483 unsigned idx0 = 2;
6484 unsigned idx1 = 2; // mem
6485 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6486 st->print_raw("XADDQ [");
6487 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6488 st->print_raw("],");
6489 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6490}
6491#endif
6492#ifndef PRODUCT
6493void xchgBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6494 // Start at oper_input_base() and count operands
6495 unsigned idx0 = 2;
6496 unsigned idx1 = 2; // mem
6497 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6498 st->print_raw("XCHGB ");
6499 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6500 st->print_raw(",[");
6501 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6502 st->print_raw("]");
6503}
6504#endif
6505#ifndef PRODUCT
6506void xchgSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6507 // Start at oper_input_base() and count operands
6508 unsigned idx0 = 2;
6509 unsigned idx1 = 2; // mem
6510 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6511 st->print_raw("XCHGW ");
6512 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6513 st->print_raw(",[");
6514 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6515 st->print_raw("]");
6516}
6517#endif
6518#ifndef PRODUCT
6519void xchgINode::format(PhaseRegAlloc *ra, outputStream *st) const {
6520 // Start at oper_input_base() and count operands
6521 unsigned idx0 = 2;
6522 unsigned idx1 = 2; // mem
6523 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6524 st->print_raw("XCHGL ");
6525 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6526 st->print_raw(",[");
6527 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6528 st->print_raw("]");
6529}
6530#endif
6531#ifndef PRODUCT
6532void xchgLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6533 // Start at oper_input_base() and count operands
6534 unsigned idx0 = 2;
6535 unsigned idx1 = 2; // mem
6536 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6537 st->print_raw("XCHGL ");
6538 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6539 st->print_raw(",[");
6540 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6541 st->print_raw("]");
6542}
6543#endif
6544#ifndef PRODUCT
6545void xchgPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6546 // Start at oper_input_base() and count operands
6547 unsigned idx0 = 2;
6548 unsigned idx1 = 2; // mem
6549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6550 st->print_raw("XCHGQ ");
6551 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6552 st->print_raw(",[");
6553 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6554 st->print_raw("]");
6555}
6556#endif
6557#ifndef PRODUCT
6558void xchgNNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6559 // Start at oper_input_base() and count operands
6560 unsigned idx0 = 2;
6561 unsigned idx1 = 2; // mem
6562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
6563 st->print_raw("XCHGL ");
6564 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
6565 st->print_raw(",");
6566 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
6567 st->print_raw("]");
6568}
6569#endif
6570#ifndef PRODUCT
6571void absI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6572 // Start at oper_input_base() and count operands
6573 unsigned idx0 = 1;
6574 unsigned idx1 = 1; // src
6575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
6576 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
6577 st->print_raw("movl ");
6578 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6579 st->print_raw(", ");
6580 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6581 st->print_raw("\n\t");
6582 st->print_raw("sarl ");
6583 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6584 st->print_raw(", 31\n\t");
6585 st->print_raw("movl ");
6586 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6587 st->print_raw(", ");
6588 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6589 st->print_raw("\n\t");
6590 st->print_raw("xorl ");
6591 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6592 st->print_raw(", ");
6593 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6594 st->print_raw("\n\t");
6595 st->print_raw("subl ");
6596 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6597 st->print_raw(", ");
6598 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6599 st->print_raw("\n");
6600}
6601#endif
6602#ifndef PRODUCT
6603void absL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6604 // Start at oper_input_base() and count operands
6605 unsigned idx0 = 1;
6606 unsigned idx1 = 1; // src
6607 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
6608 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
6609 st->print_raw("movq ");
6610 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6611 st->print_raw(", ");
6612 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6613 st->print_raw("\n\t");
6614 st->print_raw("sarq ");
6615 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6616 st->print_raw(", 63\n\t");
6617 st->print_raw("movq ");
6618 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6619 st->print_raw(", ");
6620 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6621 st->print_raw("\n\t");
6622 st->print_raw("xorq ");
6623 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6624 st->print_raw(", ");
6625 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6626 st->print_raw("\n\t");
6627 st->print_raw("subq ");
6628 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6629 st->print_raw(", ");
6630 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
6631 st->print_raw("\n");
6632}
6633#endif
6634#ifndef PRODUCT
6635void subI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6636 // Start at oper_input_base() and count operands
6637 unsigned idx0 = 1;
6638 unsigned idx1 = 1; // dst
6639 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6640 st->print_raw("subl ");
6641 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6642 st->print_raw(", ");
6643 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6644 st->print_raw("\t# int");
6645}
6646#endif
6647#ifndef PRODUCT
6648void subI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6649 // Start at oper_input_base() and count operands
6650 unsigned idx0 = 1;
6651 unsigned idx1 = 1; // dst
6652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6653 st->print_raw("subl ");
6654 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6655 st->print_raw(", ");
6656 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6657 st->print_raw("\t# int");
6658}
6659#endif
6660#ifndef PRODUCT
6661void subI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6662 // Start at oper_input_base() and count operands
6663 unsigned idx0 = 2;
6664 unsigned idx1 = 2; // dst
6665 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6666 st->print_raw("subl ");
6667 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6668 st->print_raw(", ");
6669 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6670 st->print_raw("\t# int");
6671}
6672#endif
6673#ifndef PRODUCT
6674void subI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6675 // Start at oper_input_base() and count operands
6676 unsigned idx0 = 2;
6677 unsigned idx1 = 2; // dst
6678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6679 st->print_raw("subl ");
6680 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6681 st->print_raw(", ");
6682 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6683 st->print_raw("\t# int");
6684 if (ra->C->alias_type(adr_type())->field() != NULL) {
6685 ciField* f = ra->C->alias_type(adr_type())->field();
6686 st->print(" ! Field: ");
6687 if (f->is_volatile())
6688 st->print("volatile ");
6689 f->holder()->name()->print_symbol_on(st);
6690 st->print(".");
6691 f->name()->print_symbol_on(st);
6692 if (f->is_constant())
6693 st->print(" (constant)");
6694 } else {
6695 if (ra->C->alias_type(adr_type())->is_volatile())
6696 st->print(" volatile!");
6697 }
6698}
6699#endif
6700#ifndef PRODUCT
6701void subI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6702 // Start at oper_input_base() and count operands
6703 unsigned idx0 = 2;
6704 unsigned idx1 = 2; // dst
6705 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6706 st->print_raw("subl ");
6707 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6708 st->print_raw(", ");
6709 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6710 st->print_raw("\t# int");
6711 if (ra->C->alias_type(adr_type())->field() != NULL) {
6712 ciField* f = ra->C->alias_type(adr_type())->field();
6713 st->print(" ! Field: ");
6714 if (f->is_volatile())
6715 st->print("volatile ");
6716 f->holder()->name()->print_symbol_on(st);
6717 st->print(".");
6718 f->name()->print_symbol_on(st);
6719 if (f->is_constant())
6720 st->print(" (constant)");
6721 } else {
6722 if (ra->C->alias_type(adr_type())->is_volatile())
6723 st->print(" volatile!");
6724 }
6725}
6726#endif
6727#ifndef PRODUCT
6728void subL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6729 // Start at oper_input_base() and count operands
6730 unsigned idx0 = 1;
6731 unsigned idx1 = 1; // dst
6732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6733 st->print_raw("subq ");
6734 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6735 st->print_raw(", ");
6736 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6737 st->print_raw("\t# long");
6738}
6739#endif
6740#ifndef PRODUCT
6741void subL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6742 // Start at oper_input_base() and count operands
6743 unsigned idx0 = 1;
6744 unsigned idx1 = 1; // dst
6745 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6746 st->print_raw("subq ");
6747 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6748 st->print_raw(", ");
6749 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6750 st->print_raw("\t# long");
6751}
6752#endif
6753#ifndef PRODUCT
6754void subL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6755 // Start at oper_input_base() and count operands
6756 unsigned idx0 = 2;
6757 unsigned idx1 = 2; // dst
6758 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6759 st->print_raw("subq ");
6760 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6761 st->print_raw(", ");
6762 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6763 st->print_raw("\t# long");
6764}
6765#endif
6766#ifndef PRODUCT
6767void subL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6768 // Start at oper_input_base() and count operands
6769 unsigned idx0 = 2;
6770 unsigned idx1 = 2; // dst
6771 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6772 st->print_raw("subq ");
6773 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6774 st->print_raw(", ");
6775 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6776 st->print_raw("\t# long");
6777 if (ra->C->alias_type(adr_type())->field() != NULL) {
6778 ciField* f = ra->C->alias_type(adr_type())->field();
6779 st->print(" ! Field: ");
6780 if (f->is_volatile())
6781 st->print("volatile ");
6782 f->holder()->name()->print_symbol_on(st);
6783 st->print(".");
6784 f->name()->print_symbol_on(st);
6785 if (f->is_constant())
6786 st->print(" (constant)");
6787 } else {
6788 if (ra->C->alias_type(adr_type())->is_volatile())
6789 st->print(" volatile!");
6790 }
6791}
6792#endif
6793#ifndef PRODUCT
6794void subL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6795 // Start at oper_input_base() and count operands
6796 unsigned idx0 = 2;
6797 unsigned idx1 = 2; // dst
6798 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6799 st->print_raw("subq ");
6800 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6801 st->print_raw(", ");
6802 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6803 st->print_raw("\t# long");
6804 if (ra->C->alias_type(adr_type())->field() != NULL) {
6805 ciField* f = ra->C->alias_type(adr_type())->field();
6806 st->print(" ! Field: ");
6807 if (f->is_volatile())
6808 st->print("volatile ");
6809 f->holder()->name()->print_symbol_on(st);
6810 st->print(".");
6811 f->name()->print_symbol_on(st);
6812 if (f->is_constant())
6813 st->print(" (constant)");
6814 } else {
6815 if (ra->C->alias_type(adr_type())->is_volatile())
6816 st->print(" volatile!");
6817 }
6818}
6819#endif
6820#ifndef PRODUCT
6821void subP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6822 // Start at oper_input_base() and count operands
6823 unsigned idx0 = 2;
6824 unsigned idx1 = 2; // dst
6825 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
6826 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src
6827 st->print_raw("subq ");
6828 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6829 st->print_raw(", ");
6830 opnd_array(3)->ext_format(ra, this,idx3, st); // src
6831 st->print_raw("\t# ptr - int");
6832}
6833#endif
6834#ifndef PRODUCT
6835void negI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6836 // Start at oper_input_base() and count operands
6837 unsigned idx0 = 1;
6838 unsigned idx1 = 1; // zero
6839 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
6840 st->print_raw("negl ");
6841 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6842 st->print_raw("\t# int");
6843}
6844#endif
6845#ifndef PRODUCT
6846void negI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6847 // Start at oper_input_base() and count operands
6848 unsigned idx0 = 2;
6849 unsigned idx1 = 2; // dst
6850 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
6851 st->print_raw("negl ");
6852 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6853 st->print_raw("\t# int");
6854 if (ra->C->alias_type(adr_type())->field() != NULL) {
6855 ciField* f = ra->C->alias_type(adr_type())->field();
6856 st->print(" ! Field: ");
6857 if (f->is_volatile())
6858 st->print("volatile ");
6859 f->holder()->name()->print_symbol_on(st);
6860 st->print(".");
6861 f->name()->print_symbol_on(st);
6862 if (f->is_constant())
6863 st->print(" (constant)");
6864 } else {
6865 if (ra->C->alias_type(adr_type())->is_volatile())
6866 st->print(" volatile!");
6867 }
6868}
6869#endif
6870#ifndef PRODUCT
6871void negL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6872 // Start at oper_input_base() and count operands
6873 unsigned idx0 = 1;
6874 unsigned idx1 = 1; // zero
6875 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
6876 st->print_raw("negq ");
6877 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6878 st->print_raw("\t# long");
6879}
6880#endif
6881#ifndef PRODUCT
6882void negL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6883 // Start at oper_input_base() and count operands
6884 unsigned idx0 = 2;
6885 unsigned idx1 = 2; // dst
6886 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
6887 st->print_raw("negq ");
6888 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6889 st->print_raw("\t# long");
6890 if (ra->C->alias_type(adr_type())->field() != NULL) {
6891 ciField* f = ra->C->alias_type(adr_type())->field();
6892 st->print(" ! Field: ");
6893 if (f->is_volatile())
6894 st->print("volatile ");
6895 f->holder()->name()->print_symbol_on(st);
6896 st->print(".");
6897 f->name()->print_symbol_on(st);
6898 if (f->is_constant())
6899 st->print(" (constant)");
6900 } else {
6901 if (ra->C->alias_type(adr_type())->is_volatile())
6902 st->print(" volatile!");
6903 }
6904}
6905#endif
6906#ifndef PRODUCT
6907void mulI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6908 // Start at oper_input_base() and count operands
6909 unsigned idx0 = 1;
6910 unsigned idx1 = 1; // dst
6911 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6912 st->print_raw("imull ");
6913 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6914 st->print_raw(", ");
6915 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6916 st->print_raw("\t# int");
6917}
6918#endif
6919#ifndef PRODUCT
6920void mulI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6921 // Start at oper_input_base() and count operands
6922 unsigned idx0 = 1;
6923 unsigned idx1 = 1; // src
6924 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
6925 st->print_raw("imull ");
6926 opnd_array(0)->int_format(ra, this, st); // dst
6927 st->print_raw(", ");
6928 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6929 st->print_raw(", ");
6930 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
6931 st->print_raw("\t# int");
6932}
6933#endif
6934#ifndef PRODUCT
6935void mulI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6936 // Start at oper_input_base() and count operands
6937 unsigned idx0 = 2;
6938 unsigned idx1 = 2; // dst
6939 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6940 st->print_raw("imull ");
6941 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6942 st->print_raw(", ");
6943 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6944 st->print_raw("\t# int");
6945}
6946#endif
6947#ifndef PRODUCT
6948void mulI_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
6949 // Start at oper_input_base() and count operands
6950 unsigned idx0 = 2;
6951 unsigned idx1 = 2; // src
6952 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
6953 st->print_raw("imull ");
6954 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
6955 st->print_raw(", ");
6956 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6957 st->print_raw("\t# int");
6958}
6959#endif
6960#ifndef PRODUCT
6961void mulI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6962 // Start at oper_input_base() and count operands
6963 unsigned idx0 = 2;
6964 unsigned idx1 = 2; // src
6965 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
6966 st->print_raw("imull ");
6967 opnd_array(0)->int_format(ra, this, st); // dst
6968 st->print_raw(", ");
6969 opnd_array(1)->ext_format(ra, this,idx1, st); // src
6970 st->print_raw(", ");
6971 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
6972 st->print_raw("\t# int");
6973}
6974#endif
6975#ifndef PRODUCT
6976void mulAddS2I_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6977}
6978#endif
6979#ifndef PRODUCT
6980void mulL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6981 // Start at oper_input_base() and count operands
6982 unsigned idx0 = 1;
6983 unsigned idx1 = 1; // dst
6984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
6985 st->print_raw("imulq ");
6986 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
6987 st->print_raw(", ");
6988 opnd_array(2)->ext_format(ra, this,idx2, st); // src
6989 st->print_raw("\t# long");
6990}
6991#endif
6992#ifndef PRODUCT
6993void mulL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
6994 // Start at oper_input_base() and count operands
6995 unsigned idx0 = 1;
6996 unsigned idx1 = 1; // src
6997 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
6998 st->print_raw("imulq ");
6999 opnd_array(0)->int_format(ra, this, st); // dst
7000 st->print_raw(", ");
7001 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7002 st->print_raw(", ");
7003 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
7004 st->print_raw("\t# long");
7005}
7006#endif
7007#ifndef PRODUCT
7008void mulL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7009 // Start at oper_input_base() and count operands
7010 unsigned idx0 = 2;
7011 unsigned idx1 = 2; // dst
7012 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
7013 st->print_raw("imulq ");
7014 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7015 st->print_raw(", ");
7016 opnd_array(2)->ext_format(ra, this,idx2, st); // src
7017 st->print_raw("\t# long");
7018}
7019#endif
7020#ifndef PRODUCT
7021void mulL_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7022 // Start at oper_input_base() and count operands
7023 unsigned idx0 = 2;
7024 unsigned idx1 = 2; // src
7025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
7026 st->print_raw("imulq ");
7027 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
7028 st->print_raw(", ");
7029 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7030 st->print_raw("\t# long");
7031}
7032#endif
7033#ifndef PRODUCT
7034void mulL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7035 // Start at oper_input_base() and count operands
7036 unsigned idx0 = 2;
7037 unsigned idx1 = 2; // src
7038 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
7039 st->print_raw("imulq ");
7040 opnd_array(0)->int_format(ra, this, st); // dst
7041 st->print_raw(", ");
7042 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7043 st->print_raw(", ");
7044 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
7045 st->print_raw("\t# long");
7046}
7047#endif
7048#ifndef PRODUCT
7049void mulHiL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7050 // Start at oper_input_base() and count operands
7051 unsigned idx0 = 1;
7052 unsigned idx1 = 1; // src
7053 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
7054 st->print_raw("imulq RDX:RAX, RAX, ");
7055 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7056 st->print_raw("\t# mulhi");
7057}
7058#endif
7059#ifndef PRODUCT
7060void divI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7061 // Start at oper_input_base() and count operands
7062 unsigned idx0 = 1;
7063 unsigned idx1 = 1; // rax
7064 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
7065 st->print_raw("cmpl rax, 0x80000000\t# idiv\n\t");
7066 st->print_raw("jne,s normal\n\t");
7067 st->print_raw("xorl rdx, rdx\n\t");
7068 st->print_raw("cmpl ");
7069 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7070 st->print_raw(", -1\n\t");
7071 st->print_raw("je,s done\n");
7072 st->print_raw("normal: cdql\n\t");
7073 st->print_raw("idivl ");
7074 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7075 st->print_raw("\n");
7076 st->print_raw("done:");
7077}
7078#endif
7079#ifndef PRODUCT
7080void divL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7081 // Start at oper_input_base() and count operands
7082 unsigned idx0 = 1;
7083 unsigned idx1 = 1; // rax
7084 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
7085 st->print_raw("movq rdx, 0x8000000000000000\t# ldiv\n\t");
7086 st->print_raw("cmpq rax, rdx\n\t");
7087 st->print_raw("jne,s normal\n\t");
7088 st->print_raw("xorl rdx, rdx\n\t");
7089 st->print_raw("cmpq ");
7090 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7091 st->print_raw(", -1\n\t");
7092 st->print_raw("je,s done\n");
7093 st->print_raw("normal: cdqq\n\t");
7094 st->print_raw("idivq ");
7095 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7096 st->print_raw("\n");
7097 st->print_raw("done:");
7098}
7099#endif
7100#ifndef PRODUCT
7101void divModI_rReg_divmodNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7102 // Start at oper_input_base() and count operands
7103 unsigned idx0 = 1;
7104 unsigned idx1 = 1; // div
7105 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
7106 st->print_raw("cmpl rax, 0x80000000\t# idiv\n\t");
7107 st->print_raw("jne,s normal\n\t");
7108 st->print_raw("xorl rdx, rdx\n\t");
7109 st->print_raw("cmpl ");
7110 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7111 st->print_raw(", -1\n\t");
7112 st->print_raw("je,s done\n");
7113 st->print_raw("normal: cdql\n\t");
7114 st->print_raw("idivl ");
7115 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7116 st->print_raw("\n");
7117 st->print_raw("done:");
7118}
7119#endif
7120#ifndef PRODUCT
7121void divModL_rReg_divmodNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7122 // Start at oper_input_base() and count operands
7123 unsigned idx0 = 1;
7124 unsigned idx1 = 1; // div
7125 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
7126 st->print_raw("movq rdx, 0x8000000000000000\t# ldiv\n\t");
7127 st->print_raw("cmpq rax, rdx\n\t");
7128 st->print_raw("jne,s normal\n\t");
7129 st->print_raw("xorl rdx, rdx\n\t");
7130 st->print_raw("cmpq ");
7131 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7132 st->print_raw(", -1\n\t");
7133 st->print_raw("je,s done\n");
7134 st->print_raw("normal: cdqq\n\t");
7135 st->print_raw("idivq ");
7136 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7137 st->print_raw("\n");
7138 st->print_raw("done:");
7139}
7140#endif
7141#ifndef PRODUCT
7142void loadConL_0x6666666666666667Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7143 // Start at oper_input_base() and count operands
7144 unsigned idx0 = 1;
7145 unsigned idx1 = 1; //
7146 st->print_raw("movq ");
7147 opnd_array(0)->int_format(ra, this, st); // dst
7148 st->print_raw(", #0x666666666666667\t# Used in div-by-10");
7149}
7150#endif
7151#ifndef PRODUCT
7152void mul_hiNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7153 // Start at oper_input_base() and count operands
7154 unsigned idx0 = 1;
7155 unsigned idx1 = 1; // src
7156 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
7157 st->print_raw("imulq rdx:rax, rax, ");
7158 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7159 st->print_raw("\t# Used in div-by-10");
7160}
7161#endif
7162#ifndef PRODUCT
7163void sarL_rReg_63Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7164 // Start at oper_input_base() and count operands
7165 unsigned idx0 = 1;
7166 unsigned idx1 = 1; // cr
7167 st->print_raw("sarq ");
7168 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7169 st->print_raw(", #63\t# Used in div-by-10");
7170}
7171#endif
7172#ifndef PRODUCT
7173void sarL_rReg_2Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7174 // Start at oper_input_base() and count operands
7175 unsigned idx0 = 1;
7176 unsigned idx1 = 1; // cr
7177 st->print_raw("sarq ");
7178 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7179 st->print_raw(", #2\t# Used in div-by-10");
7180}
7181#endif
7182#ifndef PRODUCT
7183void divL_10Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7184}
7185#endif
7186#ifndef PRODUCT
7187void modI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7188 // Start at oper_input_base() and count operands
7189 unsigned idx0 = 1;
7190 unsigned idx1 = 1; // rax
7191 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
7192 st->print_raw("cmpl rax, 0x80000000\t# irem\n\t");
7193 st->print_raw("jne,s normal\n\t");
7194 st->print_raw("xorl rdx, rdx\n\t");
7195 st->print_raw("cmpl ");
7196 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7197 st->print_raw(", -1\n\t");
7198 st->print_raw("je,s done\n");
7199 st->print_raw("normal: cdql\n\t");
7200 st->print_raw("idivl ");
7201 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7202 st->print_raw("\n");
7203 st->print_raw("done:");
7204}
7205#endif
7206#ifndef PRODUCT
7207void modL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7208 // Start at oper_input_base() and count operands
7209 unsigned idx0 = 1;
7210 unsigned idx1 = 1; // rax
7211 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
7212 st->print_raw("movq rdx, 0x8000000000000000\t# lrem\n\t");
7213 st->print_raw("cmpq rax, rdx\n\t");
7214 st->print_raw("jne,s normal\n\t");
7215 st->print_raw("xorl rdx, rdx\n\t");
7216 st->print_raw("cmpq ");
7217 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7218 st->print_raw(", -1\n\t");
7219 st->print_raw("je,s done\n");
7220 st->print_raw("normal: cdqq\n\t");
7221 st->print_raw("idivq ");
7222 opnd_array(2)->ext_format(ra, this,idx2, st); // div
7223 st->print_raw("\n");
7224 st->print_raw("done:");
7225}
7226#endif
7227#ifndef PRODUCT
7228void salI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7229 // Start at oper_input_base() and count operands
7230 unsigned idx0 = 1;
7231 unsigned idx1 = 1; // dst
7232 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7233 st->print_raw("sall ");
7234 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7235 st->print_raw(", ");
7236 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7237}
7238#endif
7239#ifndef PRODUCT
7240void salI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7241 // Start at oper_input_base() and count operands
7242 unsigned idx0 = 2;
7243 unsigned idx1 = 2; // dst
7244 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7245 st->print_raw("sall ");
7246 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7247 st->print_raw(", ");
7248 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7249 st->print_raw("\t");
7250 if (ra->C->alias_type(adr_type())->field() != NULL) {
7251 ciField* f = ra->C->alias_type(adr_type())->field();
7252 st->print(" ! Field: ");
7253 if (f->is_volatile())
7254 st->print("volatile ");
7255 f->holder()->name()->print_symbol_on(st);
7256 st->print(".");
7257 f->name()->print_symbol_on(st);
7258 if (f->is_constant())
7259 st->print(" (constant)");
7260 } else {
7261 if (ra->C->alias_type(adr_type())->is_volatile())
7262 st->print(" volatile!");
7263 }
7264}
7265#endif
7266#ifndef PRODUCT
7267void salI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7268 // Start at oper_input_base() and count operands
7269 unsigned idx0 = 1;
7270 unsigned idx1 = 1; // dst
7271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7272 st->print_raw("sall ");
7273 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7274 st->print_raw(", ");
7275 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7276}
7277#endif
7278#ifndef PRODUCT
7279void salI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7280 // Start at oper_input_base() and count operands
7281 unsigned idx0 = 2;
7282 unsigned idx1 = 2; // dst
7283 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7284 st->print_raw("sall ");
7285 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7286 st->print_raw(", ");
7287 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7288 if (ra->C->alias_type(adr_type())->field() != NULL) {
7289 ciField* f = ra->C->alias_type(adr_type())->field();
7290 st->print(" ! Field: ");
7291 if (f->is_volatile())
7292 st->print("volatile ");
7293 f->holder()->name()->print_symbol_on(st);
7294 st->print(".");
7295 f->name()->print_symbol_on(st);
7296 if (f->is_constant())
7297 st->print(" (constant)");
7298 } else {
7299 if (ra->C->alias_type(adr_type())->is_volatile())
7300 st->print(" volatile!");
7301 }
7302}
7303#endif
7304#ifndef PRODUCT
7305void salI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7306 // Start at oper_input_base() and count operands
7307 unsigned idx0 = 1;
7308 unsigned idx1 = 1; // dst
7309 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7310 st->print_raw("sall ");
7311 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7312 st->print_raw(", ");
7313 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7314}
7315#endif
7316#ifndef PRODUCT
7317void salI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7318 // Start at oper_input_base() and count operands
7319 unsigned idx0 = 2;
7320 unsigned idx1 = 2; // dst
7321 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7322 st->print_raw("sall ");
7323 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7324 st->print_raw(", ");
7325 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7326 if (ra->C->alias_type(adr_type())->field() != NULL) {
7327 ciField* f = ra->C->alias_type(adr_type())->field();
7328 st->print(" ! Field: ");
7329 if (f->is_volatile())
7330 st->print("volatile ");
7331 f->holder()->name()->print_symbol_on(st);
7332 st->print(".");
7333 f->name()->print_symbol_on(st);
7334 if (f->is_constant())
7335 st->print(" (constant)");
7336 } else {
7337 if (ra->C->alias_type(adr_type())->is_volatile())
7338 st->print(" volatile!");
7339 }
7340}
7341#endif
7342#ifndef PRODUCT
7343void sarI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7344 // Start at oper_input_base() and count operands
7345 unsigned idx0 = 1;
7346 unsigned idx1 = 1; // dst
7347 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7348 st->print_raw("sarl ");
7349 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7350 st->print_raw(", ");
7351 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7352}
7353#endif
7354#ifndef PRODUCT
7355void sarI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7356 // Start at oper_input_base() and count operands
7357 unsigned idx0 = 2;
7358 unsigned idx1 = 2; // dst
7359 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7360 st->print_raw("sarl ");
7361 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7362 st->print_raw(", ");
7363 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7364 if (ra->C->alias_type(adr_type())->field() != NULL) {
7365 ciField* f = ra->C->alias_type(adr_type())->field();
7366 st->print(" ! Field: ");
7367 if (f->is_volatile())
7368 st->print("volatile ");
7369 f->holder()->name()->print_symbol_on(st);
7370 st->print(".");
7371 f->name()->print_symbol_on(st);
7372 if (f->is_constant())
7373 st->print(" (constant)");
7374 } else {
7375 if (ra->C->alias_type(adr_type())->is_volatile())
7376 st->print(" volatile!");
7377 }
7378}
7379#endif
7380#ifndef PRODUCT
7381void sarI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7382 // Start at oper_input_base() and count operands
7383 unsigned idx0 = 1;
7384 unsigned idx1 = 1; // dst
7385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7386 st->print_raw("sarl ");
7387 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7388 st->print_raw(", ");
7389 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7390}
7391#endif
7392#ifndef PRODUCT
7393void sarI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7394 // Start at oper_input_base() and count operands
7395 unsigned idx0 = 2;
7396 unsigned idx1 = 2; // dst
7397 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7398 st->print_raw("sarl ");
7399 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7400 st->print_raw(", ");
7401 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7402 if (ra->C->alias_type(adr_type())->field() != NULL) {
7403 ciField* f = ra->C->alias_type(adr_type())->field();
7404 st->print(" ! Field: ");
7405 if (f->is_volatile())
7406 st->print("volatile ");
7407 f->holder()->name()->print_symbol_on(st);
7408 st->print(".");
7409 f->name()->print_symbol_on(st);
7410 if (f->is_constant())
7411 st->print(" (constant)");
7412 } else {
7413 if (ra->C->alias_type(adr_type())->is_volatile())
7414 st->print(" volatile!");
7415 }
7416}
7417#endif
7418#ifndef PRODUCT
7419void sarI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7420 // Start at oper_input_base() and count operands
7421 unsigned idx0 = 1;
7422 unsigned idx1 = 1; // dst
7423 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7424 st->print_raw("sarl ");
7425 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7426 st->print_raw(", ");
7427 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7428}
7429#endif
7430#ifndef PRODUCT
7431void sarI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7432 // Start at oper_input_base() and count operands
7433 unsigned idx0 = 2;
7434 unsigned idx1 = 2; // dst
7435 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7436 st->print_raw("sarl ");
7437 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7438 st->print_raw(", ");
7439 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7440 if (ra->C->alias_type(adr_type())->field() != NULL) {
7441 ciField* f = ra->C->alias_type(adr_type())->field();
7442 st->print(" ! Field: ");
7443 if (f->is_volatile())
7444 st->print("volatile ");
7445 f->holder()->name()->print_symbol_on(st);
7446 st->print(".");
7447 f->name()->print_symbol_on(st);
7448 if (f->is_constant())
7449 st->print(" (constant)");
7450 } else {
7451 if (ra->C->alias_type(adr_type())->is_volatile())
7452 st->print(" volatile!");
7453 }
7454}
7455#endif
7456#ifndef PRODUCT
7457void shrI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7458 // Start at oper_input_base() and count operands
7459 unsigned idx0 = 1;
7460 unsigned idx1 = 1; // dst
7461 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7462 st->print_raw("shrl ");
7463 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7464 st->print_raw(", ");
7465 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7466}
7467#endif
7468#ifndef PRODUCT
7469void shrI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7470 // Start at oper_input_base() and count operands
7471 unsigned idx0 = 2;
7472 unsigned idx1 = 2; // dst
7473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7474 st->print_raw("shrl ");
7475 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7476 st->print_raw(", ");
7477 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7478 if (ra->C->alias_type(adr_type())->field() != NULL) {
7479 ciField* f = ra->C->alias_type(adr_type())->field();
7480 st->print(" ! Field: ");
7481 if (f->is_volatile())
7482 st->print("volatile ");
7483 f->holder()->name()->print_symbol_on(st);
7484 st->print(".");
7485 f->name()->print_symbol_on(st);
7486 if (f->is_constant())
7487 st->print(" (constant)");
7488 } else {
7489 if (ra->C->alias_type(adr_type())->is_volatile())
7490 st->print(" volatile!");
7491 }
7492}
7493#endif
7494#ifndef PRODUCT
7495void shrI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7496 // Start at oper_input_base() and count operands
7497 unsigned idx0 = 1;
7498 unsigned idx1 = 1; // dst
7499 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7500 st->print_raw("shrl ");
7501 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7502 st->print_raw(", ");
7503 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7504}
7505#endif
7506#ifndef PRODUCT
7507void shrI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7508 // Start at oper_input_base() and count operands
7509 unsigned idx0 = 2;
7510 unsigned idx1 = 2; // dst
7511 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7512 st->print_raw("shrl ");
7513 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7514 st->print_raw(", ");
7515 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7516 if (ra->C->alias_type(adr_type())->field() != NULL) {
7517 ciField* f = ra->C->alias_type(adr_type())->field();
7518 st->print(" ! Field: ");
7519 if (f->is_volatile())
7520 st->print("volatile ");
7521 f->holder()->name()->print_symbol_on(st);
7522 st->print(".");
7523 f->name()->print_symbol_on(st);
7524 if (f->is_constant())
7525 st->print(" (constant)");
7526 } else {
7527 if (ra->C->alias_type(adr_type())->is_volatile())
7528 st->print(" volatile!");
7529 }
7530}
7531#endif
7532#ifndef PRODUCT
7533void shrI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7534 // Start at oper_input_base() and count operands
7535 unsigned idx0 = 1;
7536 unsigned idx1 = 1; // dst
7537 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7538 st->print_raw("shrl ");
7539 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7540 st->print_raw(", ");
7541 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7542}
7543#endif
7544#ifndef PRODUCT
7545void shrI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7546 // Start at oper_input_base() and count operands
7547 unsigned idx0 = 2;
7548 unsigned idx1 = 2; // dst
7549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7550 st->print_raw("shrl ");
7551 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7552 st->print_raw(", ");
7553 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7554 if (ra->C->alias_type(adr_type())->field() != NULL) {
7555 ciField* f = ra->C->alias_type(adr_type())->field();
7556 st->print(" ! Field: ");
7557 if (f->is_volatile())
7558 st->print("volatile ");
7559 f->holder()->name()->print_symbol_on(st);
7560 st->print(".");
7561 f->name()->print_symbol_on(st);
7562 if (f->is_constant())
7563 st->print(" (constant)");
7564 } else {
7565 if (ra->C->alias_type(adr_type())->is_volatile())
7566 st->print(" volatile!");
7567 }
7568}
7569#endif
7570#ifndef PRODUCT
7571void salL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7572 // Start at oper_input_base() and count operands
7573 unsigned idx0 = 1;
7574 unsigned idx1 = 1; // dst
7575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7576 st->print_raw("salq ");
7577 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7578 st->print_raw(", ");
7579 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7580}
7581#endif
7582#ifndef PRODUCT
7583void salL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7584 // Start at oper_input_base() and count operands
7585 unsigned idx0 = 2;
7586 unsigned idx1 = 2; // dst
7587 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7588 st->print_raw("salq ");
7589 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7590 st->print_raw(", ");
7591 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7592 if (ra->C->alias_type(adr_type())->field() != NULL) {
7593 ciField* f = ra->C->alias_type(adr_type())->field();
7594 st->print(" ! Field: ");
7595 if (f->is_volatile())
7596 st->print("volatile ");
7597 f->holder()->name()->print_symbol_on(st);
7598 st->print(".");
7599 f->name()->print_symbol_on(st);
7600 if (f->is_constant())
7601 st->print(" (constant)");
7602 } else {
7603 if (ra->C->alias_type(adr_type())->is_volatile())
7604 st->print(" volatile!");
7605 }
7606}
7607#endif
7608#ifndef PRODUCT
7609void salL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7610 // Start at oper_input_base() and count operands
7611 unsigned idx0 = 1;
7612 unsigned idx1 = 1; // dst
7613 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7614 st->print_raw("salq ");
7615 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7616 st->print_raw(", ");
7617 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7618}
7619#endif
7620#ifndef PRODUCT
7621void salL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7622 // Start at oper_input_base() and count operands
7623 unsigned idx0 = 2;
7624 unsigned idx1 = 2; // dst
7625 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7626 st->print_raw("salq ");
7627 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7628 st->print_raw(", ");
7629 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7630 if (ra->C->alias_type(adr_type())->field() != NULL) {
7631 ciField* f = ra->C->alias_type(adr_type())->field();
7632 st->print(" ! Field: ");
7633 if (f->is_volatile())
7634 st->print("volatile ");
7635 f->holder()->name()->print_symbol_on(st);
7636 st->print(".");
7637 f->name()->print_symbol_on(st);
7638 if (f->is_constant())
7639 st->print(" (constant)");
7640 } else {
7641 if (ra->C->alias_type(adr_type())->is_volatile())
7642 st->print(" volatile!");
7643 }
7644}
7645#endif
7646#ifndef PRODUCT
7647void salL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7648 // Start at oper_input_base() and count operands
7649 unsigned idx0 = 1;
7650 unsigned idx1 = 1; // dst
7651 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7652 st->print_raw("salq ");
7653 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7654 st->print_raw(", ");
7655 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7656}
7657#endif
7658#ifndef PRODUCT
7659void salL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7660 // Start at oper_input_base() and count operands
7661 unsigned idx0 = 2;
7662 unsigned idx1 = 2; // dst
7663 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7664 st->print_raw("salq ");
7665 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7666 st->print_raw(", ");
7667 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7668 if (ra->C->alias_type(adr_type())->field() != NULL) {
7669 ciField* f = ra->C->alias_type(adr_type())->field();
7670 st->print(" ! Field: ");
7671 if (f->is_volatile())
7672 st->print("volatile ");
7673 f->holder()->name()->print_symbol_on(st);
7674 st->print(".");
7675 f->name()->print_symbol_on(st);
7676 if (f->is_constant())
7677 st->print(" (constant)");
7678 } else {
7679 if (ra->C->alias_type(adr_type())->is_volatile())
7680 st->print(" volatile!");
7681 }
7682}
7683#endif
7684#ifndef PRODUCT
7685void sarL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7686 // Start at oper_input_base() and count operands
7687 unsigned idx0 = 1;
7688 unsigned idx1 = 1; // dst
7689 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7690 st->print_raw("sarq ");
7691 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7692 st->print_raw(", ");
7693 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7694}
7695#endif
7696#ifndef PRODUCT
7697void sarL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7698 // Start at oper_input_base() and count operands
7699 unsigned idx0 = 2;
7700 unsigned idx1 = 2; // dst
7701 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7702 st->print_raw("sarq ");
7703 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7704 st->print_raw(", ");
7705 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7706 if (ra->C->alias_type(adr_type())->field() != NULL) {
7707 ciField* f = ra->C->alias_type(adr_type())->field();
7708 st->print(" ! Field: ");
7709 if (f->is_volatile())
7710 st->print("volatile ");
7711 f->holder()->name()->print_symbol_on(st);
7712 st->print(".");
7713 f->name()->print_symbol_on(st);
7714 if (f->is_constant())
7715 st->print(" (constant)");
7716 } else {
7717 if (ra->C->alias_type(adr_type())->is_volatile())
7718 st->print(" volatile!");
7719 }
7720}
7721#endif
7722#ifndef PRODUCT
7723void sarL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7724 // Start at oper_input_base() and count operands
7725 unsigned idx0 = 1;
7726 unsigned idx1 = 1; // dst
7727 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7728 st->print_raw("sarq ");
7729 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7730 st->print_raw(", ");
7731 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7732}
7733#endif
7734#ifndef PRODUCT
7735void sarL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7736 // Start at oper_input_base() and count operands
7737 unsigned idx0 = 2;
7738 unsigned idx1 = 2; // dst
7739 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7740 st->print_raw("sarq ");
7741 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7742 st->print_raw(", ");
7743 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7744 if (ra->C->alias_type(adr_type())->field() != NULL) {
7745 ciField* f = ra->C->alias_type(adr_type())->field();
7746 st->print(" ! Field: ");
7747 if (f->is_volatile())
7748 st->print("volatile ");
7749 f->holder()->name()->print_symbol_on(st);
7750 st->print(".");
7751 f->name()->print_symbol_on(st);
7752 if (f->is_constant())
7753 st->print(" (constant)");
7754 } else {
7755 if (ra->C->alias_type(adr_type())->is_volatile())
7756 st->print(" volatile!");
7757 }
7758}
7759#endif
7760#ifndef PRODUCT
7761void sarL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7762 // Start at oper_input_base() and count operands
7763 unsigned idx0 = 1;
7764 unsigned idx1 = 1; // dst
7765 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7766 st->print_raw("sarq ");
7767 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7768 st->print_raw(", ");
7769 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7770}
7771#endif
7772#ifndef PRODUCT
7773void sarL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7774 // Start at oper_input_base() and count operands
7775 unsigned idx0 = 2;
7776 unsigned idx1 = 2; // dst
7777 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7778 st->print_raw("sarq ");
7779 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7780 st->print_raw(", ");
7781 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7782 if (ra->C->alias_type(adr_type())->field() != NULL) {
7783 ciField* f = ra->C->alias_type(adr_type())->field();
7784 st->print(" ! Field: ");
7785 if (f->is_volatile())
7786 st->print("volatile ");
7787 f->holder()->name()->print_symbol_on(st);
7788 st->print(".");
7789 f->name()->print_symbol_on(st);
7790 if (f->is_constant())
7791 st->print(" (constant)");
7792 } else {
7793 if (ra->C->alias_type(adr_type())->is_volatile())
7794 st->print(" volatile!");
7795 }
7796}
7797#endif
7798#ifndef PRODUCT
7799void shrL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7800 // Start at oper_input_base() and count operands
7801 unsigned idx0 = 1;
7802 unsigned idx1 = 1; // dst
7803 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7804 st->print_raw("shrq ");
7805 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7806 st->print_raw(", ");
7807 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7808}
7809#endif
7810#ifndef PRODUCT
7811void shrL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7812 // Start at oper_input_base() and count operands
7813 unsigned idx0 = 2;
7814 unsigned idx1 = 2; // dst
7815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7816 st->print_raw("shrq ");
7817 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7818 st->print_raw(", ");
7819 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7820 if (ra->C->alias_type(adr_type())->field() != NULL) {
7821 ciField* f = ra->C->alias_type(adr_type())->field();
7822 st->print(" ! Field: ");
7823 if (f->is_volatile())
7824 st->print("volatile ");
7825 f->holder()->name()->print_symbol_on(st);
7826 st->print(".");
7827 f->name()->print_symbol_on(st);
7828 if (f->is_constant())
7829 st->print(" (constant)");
7830 } else {
7831 if (ra->C->alias_type(adr_type())->is_volatile())
7832 st->print(" volatile!");
7833 }
7834}
7835#endif
7836#ifndef PRODUCT
7837void shrL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7838 // Start at oper_input_base() and count operands
7839 unsigned idx0 = 1;
7840 unsigned idx1 = 1; // dst
7841 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7842 st->print_raw("shrq ");
7843 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7844 st->print_raw(", ");
7845 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7846}
7847#endif
7848#ifndef PRODUCT
7849void shrL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7850 // Start at oper_input_base() and count operands
7851 unsigned idx0 = 2;
7852 unsigned idx1 = 2; // dst
7853 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7854 st->print_raw("shrq ");
7855 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7856 st->print_raw(", ");
7857 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7858 if (ra->C->alias_type(adr_type())->field() != NULL) {
7859 ciField* f = ra->C->alias_type(adr_type())->field();
7860 st->print(" ! Field: ");
7861 if (f->is_volatile())
7862 st->print("volatile ");
7863 f->holder()->name()->print_symbol_on(st);
7864 st->print(".");
7865 f->name()->print_symbol_on(st);
7866 if (f->is_constant())
7867 st->print(" (constant)");
7868 } else {
7869 if (ra->C->alias_type(adr_type())->is_volatile())
7870 st->print(" volatile!");
7871 }
7872}
7873#endif
7874#ifndef PRODUCT
7875void shrL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7876 // Start at oper_input_base() and count operands
7877 unsigned idx0 = 1;
7878 unsigned idx1 = 1; // dst
7879 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7880 st->print_raw("shrq ");
7881 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7882 st->print_raw(", ");
7883 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7884}
7885#endif
7886#ifndef PRODUCT
7887void shrL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7888 // Start at oper_input_base() and count operands
7889 unsigned idx0 = 2;
7890 unsigned idx1 = 2; // dst
7891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
7892 st->print_raw("shrq ");
7893 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7894 st->print_raw(", ");
7895 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7896 if (ra->C->alias_type(adr_type())->field() != NULL) {
7897 ciField* f = ra->C->alias_type(adr_type())->field();
7898 st->print(" ! Field: ");
7899 if (f->is_volatile())
7900 st->print("volatile ");
7901 f->holder()->name()->print_symbol_on(st);
7902 st->print(".");
7903 f->name()->print_symbol_on(st);
7904 if (f->is_constant())
7905 st->print(" (constant)");
7906 } else {
7907 if (ra->C->alias_type(adr_type())->is_volatile())
7908 st->print(" volatile!");
7909 }
7910}
7911#endif
7912#ifndef PRODUCT
7913void i2bNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7914 // Start at oper_input_base() and count operands
7915 unsigned idx0 = 1;
7916 unsigned idx1 = 1; // src
7917 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
7918 st->print_raw("movsbl ");
7919 opnd_array(0)->int_format(ra, this, st); // dst
7920 st->print_raw(", ");
7921 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7922 st->print_raw("\t# i2b");
7923}
7924#endif
7925#ifndef PRODUCT
7926void i2sNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7927 // Start at oper_input_base() and count operands
7928 unsigned idx0 = 1;
7929 unsigned idx1 = 1; // src
7930 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
7931 st->print_raw("movswl ");
7932 opnd_array(0)->int_format(ra, this, st); // dst
7933 st->print_raw(", ");
7934 opnd_array(1)->ext_format(ra, this,idx1, st); // src
7935 st->print_raw("\t# i2s");
7936}
7937#endif
7938#ifndef PRODUCT
7939void rolI_rReg_imm1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7940 // Start at oper_input_base() and count operands
7941 unsigned idx0 = 1;
7942 unsigned idx1 = 1; // cr
7943 st->print_raw("roll ");
7944 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7945}
7946#endif
7947#ifndef PRODUCT
7948void rolI_rReg_imm8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7949 // Start at oper_input_base() and count operands
7950 unsigned idx0 = 1;
7951 unsigned idx1 = 1; // shift
7952 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
7953 st->print_raw("roll ");
7954 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7955 st->print_raw(", ");
7956 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7957}
7958#endif
7959#ifndef PRODUCT
7960void rolI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
7961 // Start at oper_input_base() and count operands
7962 unsigned idx0 = 1;
7963 unsigned idx1 = 1; // shift
7964 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
7965 st->print_raw("roll ");
7966 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
7967 st->print_raw(", ");
7968 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
7969}
7970#endif
7971#ifndef PRODUCT
7972void rolI_rReg_i1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7973}
7974#endif
7975#ifndef PRODUCT
7976void rolI_rReg_i1_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7977}
7978#endif
7979#ifndef PRODUCT
7980void rolI_rReg_i8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7981}
7982#endif
7983#ifndef PRODUCT
7984void rolI_rReg_i8_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7985}
7986#endif
7987#ifndef PRODUCT
7988void rolI_rReg_Var_C0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7989}
7990#endif
7991#ifndef PRODUCT
7992void rolI_rReg_Var_C0_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7993}
7994#endif
7995#ifndef PRODUCT
7996void rolI_rReg_Var_C32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
7997}
7998#endif
7999#ifndef PRODUCT
8000void rolI_rReg_Var_C32_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8001}
8002#endif
8003#ifndef PRODUCT
8004void rorI_rReg_imm1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8005 // Start at oper_input_base() and count operands
8006 unsigned idx0 = 1;
8007 unsigned idx1 = 1; // cr
8008 st->print_raw("rorl ");
8009 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8010}
8011#endif
8012#ifndef PRODUCT
8013void rorI_rReg_imm8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8014 // Start at oper_input_base() and count operands
8015 unsigned idx0 = 1;
8016 unsigned idx1 = 1; // shift
8017 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8018 st->print_raw("rorl ");
8019 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8020 st->print_raw(", ");
8021 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8022}
8023#endif
8024#ifndef PRODUCT
8025void rorI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8026 // Start at oper_input_base() and count operands
8027 unsigned idx0 = 1;
8028 unsigned idx1 = 1; // shift
8029 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8030 st->print_raw("rorl ");
8031 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8032 st->print_raw(", ");
8033 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8034}
8035#endif
8036#ifndef PRODUCT
8037void rorI_rReg_i1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8038}
8039#endif
8040#ifndef PRODUCT
8041void rorI_rReg_i1_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8042}
8043#endif
8044#ifndef PRODUCT
8045void rorI_rReg_i8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8046}
8047#endif
8048#ifndef PRODUCT
8049void rorI_rReg_i8_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8050}
8051#endif
8052#ifndef PRODUCT
8053void rorI_rReg_Var_C0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8054}
8055#endif
8056#ifndef PRODUCT
8057void rorI_rReg_Var_C0_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8058}
8059#endif
8060#ifndef PRODUCT
8061void rorI_rReg_Var_C32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8062}
8063#endif
8064#ifndef PRODUCT
8065void rorI_rReg_Var_C32_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8066}
8067#endif
8068#ifndef PRODUCT
8069void rolL_rReg_imm1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8070 // Start at oper_input_base() and count operands
8071 unsigned idx0 = 1;
8072 unsigned idx1 = 1; // cr
8073 st->print_raw("rolq ");
8074 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8075}
8076#endif
8077#ifndef PRODUCT
8078void rolL_rReg_imm8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8079 // Start at oper_input_base() and count operands
8080 unsigned idx0 = 1;
8081 unsigned idx1 = 1; // shift
8082 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8083 st->print_raw("rolq ");
8084 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8085 st->print_raw(", ");
8086 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8087}
8088#endif
8089#ifndef PRODUCT
8090void rolL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8091 // Start at oper_input_base() and count operands
8092 unsigned idx0 = 1;
8093 unsigned idx1 = 1; // shift
8094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8095 st->print_raw("rolq ");
8096 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8097 st->print_raw(", ");
8098 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8099}
8100#endif
8101#ifndef PRODUCT
8102void rolL_rReg_i1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8103}
8104#endif
8105#ifndef PRODUCT
8106void rolL_rReg_i1_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8107}
8108#endif
8109#ifndef PRODUCT
8110void rolL_rReg_i8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8111}
8112#endif
8113#ifndef PRODUCT
8114void rolL_rReg_i8_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8115}
8116#endif
8117#ifndef PRODUCT
8118void rolL_rReg_Var_C0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8119}
8120#endif
8121#ifndef PRODUCT
8122void rolL_rReg_Var_C0_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8123}
8124#endif
8125#ifndef PRODUCT
8126void rolL_rReg_Var_C64Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8127}
8128#endif
8129#ifndef PRODUCT
8130void rolL_rReg_Var_C64_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8131}
8132#endif
8133#ifndef PRODUCT
8134void rorL_rReg_imm1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8135 // Start at oper_input_base() and count operands
8136 unsigned idx0 = 1;
8137 unsigned idx1 = 1; // cr
8138 st->print_raw("rorq ");
8139 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8140}
8141#endif
8142#ifndef PRODUCT
8143void rorL_rReg_imm8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8144 // Start at oper_input_base() and count operands
8145 unsigned idx0 = 1;
8146 unsigned idx1 = 1; // shift
8147 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8148 st->print_raw("rorq ");
8149 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8150 st->print_raw(", ");
8151 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8152}
8153#endif
8154#ifndef PRODUCT
8155void rorL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8156 // Start at oper_input_base() and count operands
8157 unsigned idx0 = 1;
8158 unsigned idx1 = 1; // shift
8159 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
8160 st->print_raw("rorq ");
8161 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8162 st->print_raw(", ");
8163 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
8164}
8165#endif
8166#ifndef PRODUCT
8167void rorL_rReg_i1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8168}
8169#endif
8170#ifndef PRODUCT
8171void rorL_rReg_i1_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8172}
8173#endif
8174#ifndef PRODUCT
8175void rorL_rReg_i8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8176}
8177#endif
8178#ifndef PRODUCT
8179void rorL_rReg_i8_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8180}
8181#endif
8182#ifndef PRODUCT
8183void rorL_rReg_Var_C0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8184}
8185#endif
8186#ifndef PRODUCT
8187void rorL_rReg_Var_C0_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8188}
8189#endif
8190#ifndef PRODUCT
8191void rorL_rReg_Var_C64Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8192}
8193#endif
8194#ifndef PRODUCT
8195void rorL_rReg_Var_C64_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8196}
8197#endif
8198#ifndef PRODUCT
8199void andI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8200 // Start at oper_input_base() and count operands
8201 unsigned idx0 = 1;
8202 unsigned idx1 = 1; // dst
8203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8204 st->print_raw("andl ");
8205 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8206 st->print_raw(", ");
8207 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8208 st->print_raw("\t# int");
8209}
8210#endif
8211#ifndef PRODUCT
8212void andI_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8213 // Start at oper_input_base() and count operands
8214 unsigned idx0 = 1;
8215 unsigned idx1 = 1; // dst
8216 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8217 st->print_raw("movzbl ");
8218 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8219 st->print_raw(", ");
8220 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8221 st->print_raw("\t# int & 0xFF");
8222}
8223#endif
8224#ifndef PRODUCT
8225void andI2L_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8226 // Start at oper_input_base() and count operands
8227 unsigned idx0 = 1;
8228 unsigned idx1 = 1; // src
8229 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
8230 st->print_raw("movzbl ");
8231 opnd_array(0)->int_format(ra, this, st); // dst
8232 st->print_raw(", ");
8233 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8234 st->print_raw("\t# int & 0xFF -> long");
8235}
8236#endif
8237#ifndef PRODUCT
8238void andI_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8239 // Start at oper_input_base() and count operands
8240 unsigned idx0 = 1;
8241 unsigned idx1 = 1; // dst
8242 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8243 st->print_raw("movzwl ");
8244 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8245 st->print_raw(", ");
8246 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8247 st->print_raw("\t# int & 0xFFFF");
8248}
8249#endif
8250#ifndef PRODUCT
8251void andI2L_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8252 // Start at oper_input_base() and count operands
8253 unsigned idx0 = 1;
8254 unsigned idx1 = 1; // src
8255 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
8256 st->print_raw("movzwl ");
8257 opnd_array(0)->int_format(ra, this, st); // dst
8258 st->print_raw(", ");
8259 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8260 st->print_raw("\t# int & 0xFFFF -> long");
8261}
8262#endif
8263#ifndef PRODUCT
8264void andI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8265 // Start at oper_input_base() and count operands
8266 unsigned idx0 = 1;
8267 unsigned idx1 = 1; // dst
8268 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8269 st->print_raw("andl ");
8270 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8271 st->print_raw(", ");
8272 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8273 st->print_raw("\t# int");
8274}
8275#endif
8276#ifndef PRODUCT
8277void andI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8278 // Start at oper_input_base() and count operands
8279 unsigned idx0 = 2;
8280 unsigned idx1 = 2; // dst
8281 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8282 st->print_raw("andl ");
8283 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8284 st->print_raw(", ");
8285 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8286 st->print_raw("\t# int");
8287}
8288#endif
8289#ifndef PRODUCT
8290void andI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8291 // Start at oper_input_base() and count operands
8292 unsigned idx0 = 2;
8293 unsigned idx1 = 2; // src
8294 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
8295 st->print_raw("andl ");
8296 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
8297 st->print_raw(", ");
8298 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8299 st->print_raw("\t# int");
8300}
8301#endif
8302#ifndef PRODUCT
8303void andB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8304 // Start at oper_input_base() and count operands
8305 unsigned idx0 = 2;
8306 unsigned idx1 = 2; // dst
8307 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8308 st->print_raw("andb ");
8309 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8310 st->print_raw(", ");
8311 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8312 st->print_raw("\t# byte");
8313 if (ra->C->alias_type(adr_type())->field() != NULL) {
8314 ciField* f = ra->C->alias_type(adr_type())->field();
8315 st->print(" ! Field: ");
8316 if (f->is_volatile())
8317 st->print("volatile ");
8318 f->holder()->name()->print_symbol_on(st);
8319 st->print(".");
8320 f->name()->print_symbol_on(st);
8321 if (f->is_constant())
8322 st->print(" (constant)");
8323 } else {
8324 if (ra->C->alias_type(adr_type())->is_volatile())
8325 st->print(" volatile!");
8326 }
8327}
8328#endif
8329#ifndef PRODUCT
8330void andB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8331 // Start at oper_input_base() and count operands
8332 unsigned idx0 = 2;
8333 unsigned idx1 = 2; // dst
8334 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8335 st->print_raw("andb ");
8336 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8337 st->print_raw(", ");
8338 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8339 st->print_raw("\t# byte");
8340 if (ra->C->alias_type(adr_type())->field() != NULL) {
8341 ciField* f = ra->C->alias_type(adr_type())->field();
8342 st->print(" ! Field: ");
8343 if (f->is_volatile())
8344 st->print("volatile ");
8345 f->holder()->name()->print_symbol_on(st);
8346 st->print(".");
8347 f->name()->print_symbol_on(st);
8348 if (f->is_constant())
8349 st->print(" (constant)");
8350 } else {
8351 if (ra->C->alias_type(adr_type())->is_volatile())
8352 st->print(" volatile!");
8353 }
8354}
8355#endif
8356#ifndef PRODUCT
8357void andI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8358 // Start at oper_input_base() and count operands
8359 unsigned idx0 = 2;
8360 unsigned idx1 = 2; // dst
8361 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8362 st->print_raw("andl ");
8363 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8364 st->print_raw(", ");
8365 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8366 st->print_raw("\t# int");
8367 if (ra->C->alias_type(adr_type())->field() != NULL) {
8368 ciField* f = ra->C->alias_type(adr_type())->field();
8369 st->print(" ! Field: ");
8370 if (f->is_volatile())
8371 st->print("volatile ");
8372 f->holder()->name()->print_symbol_on(st);
8373 st->print(".");
8374 f->name()->print_symbol_on(st);
8375 if (f->is_constant())
8376 st->print(" (constant)");
8377 } else {
8378 if (ra->C->alias_type(adr_type())->is_volatile())
8379 st->print(" volatile!");
8380 }
8381}
8382#endif
8383#ifndef PRODUCT
8384void andI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8385 // Start at oper_input_base() and count operands
8386 unsigned idx0 = 2;
8387 unsigned idx1 = 2; // dst
8388 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8389 st->print_raw("andl ");
8390 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8391 st->print_raw(", ");
8392 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8393 st->print_raw("\t# int");
8394 if (ra->C->alias_type(adr_type())->field() != NULL) {
8395 ciField* f = ra->C->alias_type(adr_type())->field();
8396 st->print(" ! Field: ");
8397 if (f->is_volatile())
8398 st->print("volatile ");
8399 f->holder()->name()->print_symbol_on(st);
8400 st->print(".");
8401 f->name()->print_symbol_on(st);
8402 if (f->is_constant())
8403 st->print(" (constant)");
8404 } else {
8405 if (ra->C->alias_type(adr_type())->is_volatile())
8406 st->print(" volatile!");
8407 }
8408}
8409#endif
8410#ifndef PRODUCT
8411void andI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8412 // Start at oper_input_base() and count operands
8413 unsigned idx0 = 2;
8414 unsigned idx1 = 2; // dst
8415 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8416 st->print_raw("andl ");
8417 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8418 st->print_raw(", ");
8419 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8420 st->print_raw("\t# int");
8421 if (ra->C->alias_type(adr_type())->field() != NULL) {
8422 ciField* f = ra->C->alias_type(adr_type())->field();
8423 st->print(" ! Field: ");
8424 if (f->is_volatile())
8425 st->print("volatile ");
8426 f->holder()->name()->print_symbol_on(st);
8427 st->print(".");
8428 f->name()->print_symbol_on(st);
8429 if (f->is_constant())
8430 st->print(" (constant)");
8431 } else {
8432 if (ra->C->alias_type(adr_type())->is_volatile())
8433 st->print(" volatile!");
8434 }
8435}
8436#endif
8437#ifndef PRODUCT
8438void andnI_rReg_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8439 // Start at oper_input_base() and count operands
8440 unsigned idx0 = 2;
8441 unsigned idx1 = 2; // src1
8442 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8443 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
8444 st->print_raw("andnl ");
8445 opnd_array(0)->int_format(ra, this, st); // dst
8446 st->print_raw(", ");
8447 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
8448 st->print_raw(", ");
8449 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
8450}
8451#endif
8452#ifndef PRODUCT
8453void andnI_rReg_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8454 // Start at oper_input_base() and count operands
8455 unsigned idx0 = 2;
8456 unsigned idx1 = 2; // src2
8457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
8458 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
8459 st->print_raw("andnl ");
8460 opnd_array(0)->int_format(ra, this, st); // dst
8461 st->print_raw(", ");
8462 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
8463 st->print_raw(", ");
8464 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
8465}
8466#endif
8467#ifndef PRODUCT
8468void andnI_rReg_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8469 // Start at oper_input_base() and count operands
8470 unsigned idx0 = 1;
8471 unsigned idx1 = 1; // src1
8472 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8473 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
8474 st->print_raw("andnl ");
8475 opnd_array(0)->int_format(ra, this, st); // dst
8476 st->print_raw(", ");
8477 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
8478 st->print_raw(", ");
8479 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
8480}
8481#endif
8482#ifndef PRODUCT
8483void andnI_rReg_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8484 // Start at oper_input_base() and count operands
8485 unsigned idx0 = 1;
8486 unsigned idx1 = 1; // src2
8487 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
8488 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
8489 st->print_raw("andnl ");
8490 opnd_array(0)->int_format(ra, this, st); // dst
8491 st->print_raw(", ");
8492 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
8493 st->print_raw(", ");
8494 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
8495}
8496#endif
8497#ifndef PRODUCT
8498void blsiI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8499 // Start at oper_input_base() and count operands
8500 unsigned idx0 = 1;
8501 unsigned idx1 = 1; // imm_zero
8502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8503 st->print_raw("blsil ");
8504 opnd_array(0)->int_format(ra, this, st); // dst
8505 st->print_raw(", ");
8506 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8507}
8508#endif
8509#ifndef PRODUCT
8510void blsiI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8511 // Start at oper_input_base() and count operands
8512 unsigned idx0 = 1;
8513 unsigned idx1 = 1; // src
8514 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
8515 st->print_raw("blsil ");
8516 opnd_array(0)->int_format(ra, this, st); // dst
8517 st->print_raw(", ");
8518 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8519}
8520#endif
8521#ifndef PRODUCT
8522void blsiI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8523 // Start at oper_input_base() and count operands
8524 unsigned idx0 = 2;
8525 unsigned idx1 = 2; // imm_zero
8526 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8527 st->print_raw("blsil ");
8528 opnd_array(0)->int_format(ra, this, st); // dst
8529 st->print_raw(", ");
8530 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8531}
8532#endif
8533#ifndef PRODUCT
8534void blsiI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8535 // Start at oper_input_base() and count operands
8536 unsigned idx0 = 2;
8537 unsigned idx1 = 2; // src
8538 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
8539 st->print_raw("blsil ");
8540 opnd_array(0)->int_format(ra, this, st); // dst
8541 st->print_raw(", ");
8542 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8543}
8544#endif
8545#ifndef PRODUCT
8546void blsmskI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8547 // Start at oper_input_base() and count operands
8548 unsigned idx0 = 2;
8549 unsigned idx1 = 2; // src
8550 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8551 st->print_raw("blsmskl ");
8552 opnd_array(0)->int_format(ra, this, st); // dst
8553 st->print_raw(", ");
8554 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8555}
8556#endif
8557#ifndef PRODUCT
8558void blsmskI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8559 // Start at oper_input_base() and count operands
8560 unsigned idx0 = 2;
8561 unsigned idx1 = 2; // src
8562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8563 st->print_raw("blsmskl ");
8564 opnd_array(0)->int_format(ra, this, st); // dst
8565 st->print_raw(", ");
8566 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8567}
8568#endif
8569#ifndef PRODUCT
8570void blsmskI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8571 // Start at oper_input_base() and count operands
8572 unsigned idx0 = 1;
8573 unsigned idx1 = 1; // src
8574 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8575 st->print_raw("blsmskl ");
8576 opnd_array(0)->int_format(ra, this, st); // dst
8577 st->print_raw(", ");
8578 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8579}
8580#endif
8581#ifndef PRODUCT
8582void blsmskI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8583 // Start at oper_input_base() and count operands
8584 unsigned idx0 = 1;
8585 unsigned idx1 = 1; // src
8586 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8587 st->print_raw("blsmskl ");
8588 opnd_array(0)->int_format(ra, this, st); // dst
8589 st->print_raw(", ");
8590 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8591}
8592#endif
8593#ifndef PRODUCT
8594void blsrI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8595 // Start at oper_input_base() and count operands
8596 unsigned idx0 = 1;
8597 unsigned idx1 = 1; // src
8598 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8599 st->print_raw("blsrl ");
8600 opnd_array(0)->int_format(ra, this, st); // dst
8601 st->print_raw(", ");
8602 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8603}
8604#endif
8605#ifndef PRODUCT
8606void blsrI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8607 // Start at oper_input_base() and count operands
8608 unsigned idx0 = 1;
8609 unsigned idx1 = 1; // src
8610 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8611 st->print_raw("blsrl ");
8612 opnd_array(0)->int_format(ra, this, st); // dst
8613 st->print_raw(", ");
8614 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8615}
8616#endif
8617#ifndef PRODUCT
8618void blsrI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8619 // Start at oper_input_base() and count operands
8620 unsigned idx0 = 2;
8621 unsigned idx1 = 2; // src
8622 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8623 st->print_raw("blsrl ");
8624 opnd_array(0)->int_format(ra, this, st); // dst
8625 st->print_raw(", ");
8626 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8627}
8628#endif
8629#ifndef PRODUCT
8630void blsrI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8631 // Start at oper_input_base() and count operands
8632 unsigned idx0 = 2;
8633 unsigned idx1 = 2; // src
8634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
8635 st->print_raw("blsrl ");
8636 opnd_array(0)->int_format(ra, this, st); // dst
8637 st->print_raw(", ");
8638 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8639}
8640#endif
8641#ifndef PRODUCT
8642void orI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8643 // Start at oper_input_base() and count operands
8644 unsigned idx0 = 1;
8645 unsigned idx1 = 1; // dst
8646 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8647 st->print_raw("orl ");
8648 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8649 st->print_raw(", ");
8650 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8651 st->print_raw("\t# int");
8652}
8653#endif
8654#ifndef PRODUCT
8655void orI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8656 // Start at oper_input_base() and count operands
8657 unsigned idx0 = 1;
8658 unsigned idx1 = 1; // dst
8659 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8660 st->print_raw("orl ");
8661 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8662 st->print_raw(", ");
8663 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8664 st->print_raw("\t# int");
8665}
8666#endif
8667#ifndef PRODUCT
8668void orI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8669 // Start at oper_input_base() and count operands
8670 unsigned idx0 = 2;
8671 unsigned idx1 = 2; // dst
8672 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8673 st->print_raw("orl ");
8674 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8675 st->print_raw(", ");
8676 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8677 st->print_raw("\t# int");
8678}
8679#endif
8680#ifndef PRODUCT
8681void orI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8682 // Start at oper_input_base() and count operands
8683 unsigned idx0 = 2;
8684 unsigned idx1 = 2; // src
8685 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
8686 st->print_raw("orl ");
8687 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
8688 st->print_raw(", ");
8689 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8690 st->print_raw("\t# int");
8691}
8692#endif
8693#ifndef PRODUCT
8694void orB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8695 // Start at oper_input_base() and count operands
8696 unsigned idx0 = 2;
8697 unsigned idx1 = 2; // dst
8698 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8699 st->print_raw("orb ");
8700 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8701 st->print_raw(", ");
8702 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8703 st->print_raw("\t# byte");
8704 if (ra->C->alias_type(adr_type())->field() != NULL) {
8705 ciField* f = ra->C->alias_type(adr_type())->field();
8706 st->print(" ! Field: ");
8707 if (f->is_volatile())
8708 st->print("volatile ");
8709 f->holder()->name()->print_symbol_on(st);
8710 st->print(".");
8711 f->name()->print_symbol_on(st);
8712 if (f->is_constant())
8713 st->print(" (constant)");
8714 } else {
8715 if (ra->C->alias_type(adr_type())->is_volatile())
8716 st->print(" volatile!");
8717 }
8718}
8719#endif
8720#ifndef PRODUCT
8721void orB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8722 // Start at oper_input_base() and count operands
8723 unsigned idx0 = 2;
8724 unsigned idx1 = 2; // dst
8725 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8726 st->print_raw("orb ");
8727 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8728 st->print_raw(", ");
8729 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8730 st->print_raw("\t# byte");
8731 if (ra->C->alias_type(adr_type())->field() != NULL) {
8732 ciField* f = ra->C->alias_type(adr_type())->field();
8733 st->print(" ! Field: ");
8734 if (f->is_volatile())
8735 st->print("volatile ");
8736 f->holder()->name()->print_symbol_on(st);
8737 st->print(".");
8738 f->name()->print_symbol_on(st);
8739 if (f->is_constant())
8740 st->print(" (constant)");
8741 } else {
8742 if (ra->C->alias_type(adr_type())->is_volatile())
8743 st->print(" volatile!");
8744 }
8745}
8746#endif
8747#ifndef PRODUCT
8748void orI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8749 // Start at oper_input_base() and count operands
8750 unsigned idx0 = 2;
8751 unsigned idx1 = 2; // dst
8752 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8753 st->print_raw("orl ");
8754 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8755 st->print_raw(", ");
8756 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8757 st->print_raw("\t# int");
8758 if (ra->C->alias_type(adr_type())->field() != NULL) {
8759 ciField* f = ra->C->alias_type(adr_type())->field();
8760 st->print(" ! Field: ");
8761 if (f->is_volatile())
8762 st->print("volatile ");
8763 f->holder()->name()->print_symbol_on(st);
8764 st->print(".");
8765 f->name()->print_symbol_on(st);
8766 if (f->is_constant())
8767 st->print(" (constant)");
8768 } else {
8769 if (ra->C->alias_type(adr_type())->is_volatile())
8770 st->print(" volatile!");
8771 }
8772}
8773#endif
8774#ifndef PRODUCT
8775void orI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8776 // Start at oper_input_base() and count operands
8777 unsigned idx0 = 2;
8778 unsigned idx1 = 2; // dst
8779 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8780 st->print_raw("orl ");
8781 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8782 st->print_raw(", ");
8783 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8784 st->print_raw("\t# int");
8785 if (ra->C->alias_type(adr_type())->field() != NULL) {
8786 ciField* f = ra->C->alias_type(adr_type())->field();
8787 st->print(" ! Field: ");
8788 if (f->is_volatile())
8789 st->print("volatile ");
8790 f->holder()->name()->print_symbol_on(st);
8791 st->print(".");
8792 f->name()->print_symbol_on(st);
8793 if (f->is_constant())
8794 st->print(" (constant)");
8795 } else {
8796 if (ra->C->alias_type(adr_type())->is_volatile())
8797 st->print(" volatile!");
8798 }
8799}
8800#endif
8801#ifndef PRODUCT
8802void orI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8803 // Start at oper_input_base() and count operands
8804 unsigned idx0 = 2;
8805 unsigned idx1 = 2; // dst
8806 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8807 st->print_raw("orl ");
8808 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8809 st->print_raw(", ");
8810 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8811 st->print_raw("\t# int");
8812 if (ra->C->alias_type(adr_type())->field() != NULL) {
8813 ciField* f = ra->C->alias_type(adr_type())->field();
8814 st->print(" ! Field: ");
8815 if (f->is_volatile())
8816 st->print("volatile ");
8817 f->holder()->name()->print_symbol_on(st);
8818 st->print(".");
8819 f->name()->print_symbol_on(st);
8820 if (f->is_constant())
8821 st->print(" (constant)");
8822 } else {
8823 if (ra->C->alias_type(adr_type())->is_volatile())
8824 st->print(" volatile!");
8825 }
8826}
8827#endif
8828#ifndef PRODUCT
8829void xorI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8830 // Start at oper_input_base() and count operands
8831 unsigned idx0 = 1;
8832 unsigned idx1 = 1; // dst
8833 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8834 st->print_raw("xorl ");
8835 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8836 st->print_raw(", ");
8837 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8838 st->print_raw("\t# int");
8839}
8840#endif
8841#ifndef PRODUCT
8842void xorI_rReg_im1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8843 // Start at oper_input_base() and count operands
8844 unsigned idx0 = 1;
8845 unsigned idx1 = 1; // dst
8846 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
8847 st->print_raw("not ");
8848 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8849}
8850#endif
8851#ifndef PRODUCT
8852void xorI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8853 // Start at oper_input_base() and count operands
8854 unsigned idx0 = 1;
8855 unsigned idx1 = 1; // dst
8856 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8857 st->print_raw("xorl ");
8858 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8859 st->print_raw(", ");
8860 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8861 st->print_raw("\t# int");
8862}
8863#endif
8864#ifndef PRODUCT
8865void xorI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8866 // Start at oper_input_base() and count operands
8867 unsigned idx0 = 2;
8868 unsigned idx1 = 2; // dst
8869 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8870 st->print_raw("xorl ");
8871 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8872 st->print_raw(", ");
8873 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8874 st->print_raw("\t# int");
8875}
8876#endif
8877#ifndef PRODUCT
8878void xorI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8879 // Start at oper_input_base() and count operands
8880 unsigned idx0 = 2;
8881 unsigned idx1 = 2; // src
8882 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
8883 st->print_raw("xorl ");
8884 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
8885 st->print_raw(", ");
8886 opnd_array(1)->ext_format(ra, this,idx1, st); // src
8887 st->print_raw("\t# int");
8888}
8889#endif
8890#ifndef PRODUCT
8891void xorB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8892 // Start at oper_input_base() and count operands
8893 unsigned idx0 = 2;
8894 unsigned idx1 = 2; // dst
8895 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8896 st->print_raw("xorb ");
8897 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8898 st->print_raw(", ");
8899 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8900 st->print_raw("\t# byte");
8901 if (ra->C->alias_type(adr_type())->field() != NULL) {
8902 ciField* f = ra->C->alias_type(adr_type())->field();
8903 st->print(" ! Field: ");
8904 if (f->is_volatile())
8905 st->print("volatile ");
8906 f->holder()->name()->print_symbol_on(st);
8907 st->print(".");
8908 f->name()->print_symbol_on(st);
8909 if (f->is_constant())
8910 st->print(" (constant)");
8911 } else {
8912 if (ra->C->alias_type(adr_type())->is_volatile())
8913 st->print(" volatile!");
8914 }
8915}
8916#endif
8917#ifndef PRODUCT
8918void xorB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8919 // Start at oper_input_base() and count operands
8920 unsigned idx0 = 2;
8921 unsigned idx1 = 2; // dst
8922 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8923 st->print_raw("xorb ");
8924 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8925 st->print_raw(", ");
8926 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8927 st->print_raw("\t# byte");
8928 if (ra->C->alias_type(adr_type())->field() != NULL) {
8929 ciField* f = ra->C->alias_type(adr_type())->field();
8930 st->print(" ! Field: ");
8931 if (f->is_volatile())
8932 st->print("volatile ");
8933 f->holder()->name()->print_symbol_on(st);
8934 st->print(".");
8935 f->name()->print_symbol_on(st);
8936 if (f->is_constant())
8937 st->print(" (constant)");
8938 } else {
8939 if (ra->C->alias_type(adr_type())->is_volatile())
8940 st->print(" volatile!");
8941 }
8942}
8943#endif
8944#ifndef PRODUCT
8945void xorI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
8946 // Start at oper_input_base() and count operands
8947 unsigned idx0 = 2;
8948 unsigned idx1 = 2; // dst
8949 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8950 st->print_raw("xorl ");
8951 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8952 st->print_raw(", ");
8953 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8954 st->print_raw("\t# int");
8955 if (ra->C->alias_type(adr_type())->field() != NULL) {
8956 ciField* f = ra->C->alias_type(adr_type())->field();
8957 st->print(" ! Field: ");
8958 if (f->is_volatile())
8959 st->print("volatile ");
8960 f->holder()->name()->print_symbol_on(st);
8961 st->print(".");
8962 f->name()->print_symbol_on(st);
8963 if (f->is_constant())
8964 st->print(" (constant)");
8965 } else {
8966 if (ra->C->alias_type(adr_type())->is_volatile())
8967 st->print(" volatile!");
8968 }
8969}
8970#endif
8971#ifndef PRODUCT
8972void xorI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
8973 // Start at oper_input_base() and count operands
8974 unsigned idx0 = 2;
8975 unsigned idx1 = 2; // dst
8976 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
8977 st->print_raw("xorl ");
8978 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
8979 st->print_raw(", ");
8980 opnd_array(2)->ext_format(ra, this,idx2, st); // src
8981 st->print_raw("\t# int");
8982 if (ra->C->alias_type(adr_type())->field() != NULL) {
8983 ciField* f = ra->C->alias_type(adr_type())->field();
8984 st->print(" ! Field: ");
8985 if (f->is_volatile())
8986 st->print("volatile ");
8987 f->holder()->name()->print_symbol_on(st);
8988 st->print(".");
8989 f->name()->print_symbol_on(st);
8990 if (f->is_constant())
8991 st->print(" (constant)");
8992 } else {
8993 if (ra->C->alias_type(adr_type())->is_volatile())
8994 st->print(" volatile!");
8995 }
8996}
8997#endif
8998#ifndef PRODUCT
8999void xorI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9000 // Start at oper_input_base() and count operands
9001 unsigned idx0 = 2;
9002 unsigned idx1 = 2; // dst
9003 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9004 st->print_raw("xorl ");
9005 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9006 st->print_raw(", ");
9007 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9008 st->print_raw("\t# int");
9009 if (ra->C->alias_type(adr_type())->field() != NULL) {
9010 ciField* f = ra->C->alias_type(adr_type())->field();
9011 st->print(" ! Field: ");
9012 if (f->is_volatile())
9013 st->print("volatile ");
9014 f->holder()->name()->print_symbol_on(st);
9015 st->print(".");
9016 f->name()->print_symbol_on(st);
9017 if (f->is_constant())
9018 st->print(" (constant)");
9019 } else {
9020 if (ra->C->alias_type(adr_type())->is_volatile())
9021 st->print(" volatile!");
9022 }
9023}
9024#endif
9025#ifndef PRODUCT
9026void andL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9027 // Start at oper_input_base() and count operands
9028 unsigned idx0 = 1;
9029 unsigned idx1 = 1; // dst
9030 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9031 st->print_raw("andq ");
9032 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9033 st->print_raw(", ");
9034 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9035 st->print_raw("\t# long");
9036}
9037#endif
9038#ifndef PRODUCT
9039void andL_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9040 // Start at oper_input_base() and count operands
9041 unsigned idx0 = 1;
9042 unsigned idx1 = 1; // dst
9043 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9044 st->print_raw("movzbq ");
9045 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9046 st->print_raw(", ");
9047 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9048 st->print_raw("\t# long & 0xFF");
9049}
9050#endif
9051#ifndef PRODUCT
9052void andL_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9053 // Start at oper_input_base() and count operands
9054 unsigned idx0 = 1;
9055 unsigned idx1 = 1; // dst
9056 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9057 st->print_raw("movzwq ");
9058 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9059 st->print_raw(", ");
9060 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9061 st->print_raw("\t# long & 0xFFFF");
9062}
9063#endif
9064#ifndef PRODUCT
9065void andL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9066 // Start at oper_input_base() and count operands
9067 unsigned idx0 = 1;
9068 unsigned idx1 = 1; // dst
9069 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9070 st->print_raw("andq ");
9071 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9072 st->print_raw(", ");
9073 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9074 st->print_raw("\t# long");
9075}
9076#endif
9077#ifndef PRODUCT
9078void andL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9079 // Start at oper_input_base() and count operands
9080 unsigned idx0 = 2;
9081 unsigned idx1 = 2; // dst
9082 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9083 st->print_raw("andq ");
9084 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9085 st->print_raw(", ");
9086 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9087 st->print_raw("\t# long");
9088}
9089#endif
9090#ifndef PRODUCT
9091void andL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9092 // Start at oper_input_base() and count operands
9093 unsigned idx0 = 2;
9094 unsigned idx1 = 2; // src
9095 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
9096 st->print_raw("andq ");
9097 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
9098 st->print_raw(", ");
9099 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9100 st->print_raw("\t# long");
9101}
9102#endif
9103#ifndef PRODUCT
9104void andL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9105 // Start at oper_input_base() and count operands
9106 unsigned idx0 = 2;
9107 unsigned idx1 = 2; // dst
9108 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9109 st->print_raw("andq ");
9110 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9111 st->print_raw(", ");
9112 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9113 st->print_raw("\t# long");
9114 if (ra->C->alias_type(adr_type())->field() != NULL) {
9115 ciField* f = ra->C->alias_type(adr_type())->field();
9116 st->print(" ! Field: ");
9117 if (f->is_volatile())
9118 st->print("volatile ");
9119 f->holder()->name()->print_symbol_on(st);
9120 st->print(".");
9121 f->name()->print_symbol_on(st);
9122 if (f->is_constant())
9123 st->print(" (constant)");
9124 } else {
9125 if (ra->C->alias_type(adr_type())->is_volatile())
9126 st->print(" volatile!");
9127 }
9128}
9129#endif
9130#ifndef PRODUCT
9131void andL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9132 // Start at oper_input_base() and count operands
9133 unsigned idx0 = 2;
9134 unsigned idx1 = 2; // dst
9135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9136 st->print_raw("andq ");
9137 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9138 st->print_raw(", ");
9139 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9140 st->print_raw("\t# long");
9141 if (ra->C->alias_type(adr_type())->field() != NULL) {
9142 ciField* f = ra->C->alias_type(adr_type())->field();
9143 st->print(" ! Field: ");
9144 if (f->is_volatile())
9145 st->print("volatile ");
9146 f->holder()->name()->print_symbol_on(st);
9147 st->print(".");
9148 f->name()->print_symbol_on(st);
9149 if (f->is_constant())
9150 st->print(" (constant)");
9151 } else {
9152 if (ra->C->alias_type(adr_type())->is_volatile())
9153 st->print(" volatile!");
9154 }
9155}
9156#endif
9157#ifndef PRODUCT
9158void andL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9159 // Start at oper_input_base() and count operands
9160 unsigned idx0 = 2;
9161 unsigned idx1 = 2; // dst
9162 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9163 st->print_raw("andq ");
9164 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9165 st->print_raw(", ");
9166 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9167 st->print_raw("\t# long");
9168 if (ra->C->alias_type(adr_type())->field() != NULL) {
9169 ciField* f = ra->C->alias_type(adr_type())->field();
9170 st->print(" ! Field: ");
9171 if (f->is_volatile())
9172 st->print("volatile ");
9173 f->holder()->name()->print_symbol_on(st);
9174 st->print(".");
9175 f->name()->print_symbol_on(st);
9176 if (f->is_constant())
9177 st->print(" (constant)");
9178 } else {
9179 if (ra->C->alias_type(adr_type())->is_volatile())
9180 st->print(" volatile!");
9181 }
9182}
9183#endif
9184#ifndef PRODUCT
9185void andnL_rReg_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9186 // Start at oper_input_base() and count operands
9187 unsigned idx0 = 2;
9188 unsigned idx1 = 2; // src1
9189 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9190 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
9191 st->print_raw("andnq ");
9192 opnd_array(0)->int_format(ra, this, st); // dst
9193 st->print_raw(", ");
9194 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9195 st->print_raw(", ");
9196 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
9197}
9198#endif
9199#ifndef PRODUCT
9200void andnL_rReg_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9201 // Start at oper_input_base() and count operands
9202 unsigned idx0 = 2;
9203 unsigned idx1 = 2; // src2
9204 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
9205 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
9206 st->print_raw("andnq ");
9207 opnd_array(0)->int_format(ra, this, st); // dst
9208 st->print_raw(", ");
9209 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
9210 st->print_raw(", ");
9211 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
9212}
9213#endif
9214#ifndef PRODUCT
9215void andnL_rReg_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9216 // Start at oper_input_base() and count operands
9217 unsigned idx0 = 1;
9218 unsigned idx1 = 1; // src1
9219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9220 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
9221 st->print_raw("andnq ");
9222 opnd_array(0)->int_format(ra, this, st); // dst
9223 st->print_raw(", ");
9224 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9225 st->print_raw(", ");
9226 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
9227}
9228#endif
9229#ifndef PRODUCT
9230void andnL_rReg_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9231 // Start at oper_input_base() and count operands
9232 unsigned idx0 = 1;
9233 unsigned idx1 = 1; // src2
9234 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
9235 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
9236 st->print_raw("andnq ");
9237 opnd_array(0)->int_format(ra, this, st); // dst
9238 st->print_raw(", ");
9239 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
9240 st->print_raw(", ");
9241 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
9242}
9243#endif
9244#ifndef PRODUCT
9245void blsiL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9246 // Start at oper_input_base() and count operands
9247 unsigned idx0 = 1;
9248 unsigned idx1 = 1; // imm_zero
9249 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9250 st->print_raw("blsiq ");
9251 opnd_array(0)->int_format(ra, this, st); // dst
9252 st->print_raw(", ");
9253 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9254}
9255#endif
9256#ifndef PRODUCT
9257void blsiL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9258 // Start at oper_input_base() and count operands
9259 unsigned idx0 = 1;
9260 unsigned idx1 = 1; // src
9261 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
9262 st->print_raw("blsiq ");
9263 opnd_array(0)->int_format(ra, this, st); // dst
9264 st->print_raw(", ");
9265 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9266}
9267#endif
9268#ifndef PRODUCT
9269void blsiL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9270 // Start at oper_input_base() and count operands
9271 unsigned idx0 = 2;
9272 unsigned idx1 = 2; // imm_zero
9273 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9274 st->print_raw("blsiq ");
9275 opnd_array(0)->int_format(ra, this, st); // dst
9276 st->print_raw(", ");
9277 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9278}
9279#endif
9280#ifndef PRODUCT
9281void blsiL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9282 // Start at oper_input_base() and count operands
9283 unsigned idx0 = 2;
9284 unsigned idx1 = 2; // src
9285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
9286 st->print_raw("blsiq ");
9287 opnd_array(0)->int_format(ra, this, st); // dst
9288 st->print_raw(", ");
9289 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9290}
9291#endif
9292#ifndef PRODUCT
9293void blsmskL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9294 // Start at oper_input_base() and count operands
9295 unsigned idx0 = 2;
9296 unsigned idx1 = 2; // src
9297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9298 st->print_raw("blsmskq ");
9299 opnd_array(0)->int_format(ra, this, st); // dst
9300 st->print_raw(", ");
9301 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9302}
9303#endif
9304#ifndef PRODUCT
9305void blsmskL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9306 // Start at oper_input_base() and count operands
9307 unsigned idx0 = 2;
9308 unsigned idx1 = 2; // src
9309 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9310 st->print_raw("blsmskq ");
9311 opnd_array(0)->int_format(ra, this, st); // dst
9312 st->print_raw(", ");
9313 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9314}
9315#endif
9316#ifndef PRODUCT
9317void blsmskL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9318 // Start at oper_input_base() and count operands
9319 unsigned idx0 = 1;
9320 unsigned idx1 = 1; // src
9321 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9322 st->print_raw("blsmskq ");
9323 opnd_array(0)->int_format(ra, this, st); // dst
9324 st->print_raw(", ");
9325 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9326}
9327#endif
9328#ifndef PRODUCT
9329void blsmskL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9330 // Start at oper_input_base() and count operands
9331 unsigned idx0 = 1;
9332 unsigned idx1 = 1; // src
9333 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9334 st->print_raw("blsmskq ");
9335 opnd_array(0)->int_format(ra, this, st); // dst
9336 st->print_raw(", ");
9337 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9338}
9339#endif
9340#ifndef PRODUCT
9341void blsrL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9342 // Start at oper_input_base() and count operands
9343 unsigned idx0 = 1;
9344 unsigned idx1 = 1; // src
9345 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9346 st->print_raw("blsrq ");
9347 opnd_array(0)->int_format(ra, this, st); // dst
9348 st->print_raw(", ");
9349 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9350}
9351#endif
9352#ifndef PRODUCT
9353void blsrL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9354 // Start at oper_input_base() and count operands
9355 unsigned idx0 = 1;
9356 unsigned idx1 = 1; // src
9357 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9358 st->print_raw("blsrq ");
9359 opnd_array(0)->int_format(ra, this, st); // dst
9360 st->print_raw(", ");
9361 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9362}
9363#endif
9364#ifndef PRODUCT
9365void blsrL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9366 // Start at oper_input_base() and count operands
9367 unsigned idx0 = 2;
9368 unsigned idx1 = 2; // src
9369 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9370 st->print_raw("blsrq ");
9371 opnd_array(0)->int_format(ra, this, st); // dst
9372 st->print_raw(", ");
9373 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9374}
9375#endif
9376#ifndef PRODUCT
9377void blsrL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9378 // Start at oper_input_base() and count operands
9379 unsigned idx0 = 2;
9380 unsigned idx1 = 2; // src
9381 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
9382 st->print_raw("blsrq ");
9383 opnd_array(0)->int_format(ra, this, st); // dst
9384 st->print_raw(", ");
9385 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9386}
9387#endif
9388#ifndef PRODUCT
9389void orL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9390 // Start at oper_input_base() and count operands
9391 unsigned idx0 = 1;
9392 unsigned idx1 = 1; // dst
9393 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9394 st->print_raw("orq ");
9395 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9396 st->print_raw(", ");
9397 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9398 st->print_raw("\t# long");
9399}
9400#endif
9401#ifndef PRODUCT
9402void orL_rReg_castP2XNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9403 // Start at oper_input_base() and count operands
9404 unsigned idx0 = 1;
9405 unsigned idx1 = 1; // dst
9406 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9407 st->print_raw("orq ");
9408 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9409 st->print_raw(", ");
9410 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9411 st->print_raw("\t# long");
9412}
9413#endif
9414#ifndef PRODUCT
9415void orL_rReg_castP2X_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9416 // Start at oper_input_base() and count operands
9417 unsigned idx0 = 1;
9418 unsigned idx1 = 1; // src
9419 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
9420 st->print_raw("orq ");
9421 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
9422 st->print_raw(", ");
9423 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9424 st->print_raw("\t# long");
9425}
9426#endif
9427#ifndef PRODUCT
9428void orL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9429 // Start at oper_input_base() and count operands
9430 unsigned idx0 = 1;
9431 unsigned idx1 = 1; // dst
9432 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9433 st->print_raw("orq ");
9434 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9435 st->print_raw(", ");
9436 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9437 st->print_raw("\t# long");
9438}
9439#endif
9440#ifndef PRODUCT
9441void orL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9442 // Start at oper_input_base() and count operands
9443 unsigned idx0 = 2;
9444 unsigned idx1 = 2; // dst
9445 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9446 st->print_raw("orq ");
9447 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9448 st->print_raw(", ");
9449 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9450 st->print_raw("\t# long");
9451}
9452#endif
9453#ifndef PRODUCT
9454void orL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9455 // Start at oper_input_base() and count operands
9456 unsigned idx0 = 2;
9457 unsigned idx1 = 2; // src
9458 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
9459 st->print_raw("orq ");
9460 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
9461 st->print_raw(", ");
9462 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9463 st->print_raw("\t# long");
9464}
9465#endif
9466#ifndef PRODUCT
9467void orL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9468 // Start at oper_input_base() and count operands
9469 unsigned idx0 = 2;
9470 unsigned idx1 = 2; // dst
9471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9472 st->print_raw("orq ");
9473 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9474 st->print_raw(", ");
9475 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9476 st->print_raw("\t# long");
9477 if (ra->C->alias_type(adr_type())->field() != NULL) {
9478 ciField* f = ra->C->alias_type(adr_type())->field();
9479 st->print(" ! Field: ");
9480 if (f->is_volatile())
9481 st->print("volatile ");
9482 f->holder()->name()->print_symbol_on(st);
9483 st->print(".");
9484 f->name()->print_symbol_on(st);
9485 if (f->is_constant())
9486 st->print(" (constant)");
9487 } else {
9488 if (ra->C->alias_type(adr_type())->is_volatile())
9489 st->print(" volatile!");
9490 }
9491}
9492#endif
9493#ifndef PRODUCT
9494void orL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9495 // Start at oper_input_base() and count operands
9496 unsigned idx0 = 2;
9497 unsigned idx1 = 2; // dst
9498 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9499 st->print_raw("orq ");
9500 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9501 st->print_raw(", ");
9502 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9503 st->print_raw("\t# long");
9504 if (ra->C->alias_type(adr_type())->field() != NULL) {
9505 ciField* f = ra->C->alias_type(adr_type())->field();
9506 st->print(" ! Field: ");
9507 if (f->is_volatile())
9508 st->print("volatile ");
9509 f->holder()->name()->print_symbol_on(st);
9510 st->print(".");
9511 f->name()->print_symbol_on(st);
9512 if (f->is_constant())
9513 st->print(" (constant)");
9514 } else {
9515 if (ra->C->alias_type(adr_type())->is_volatile())
9516 st->print(" volatile!");
9517 }
9518}
9519#endif
9520#ifndef PRODUCT
9521void orL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9522 // Start at oper_input_base() and count operands
9523 unsigned idx0 = 2;
9524 unsigned idx1 = 2; // dst
9525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9526 st->print_raw("orq ");
9527 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9528 st->print_raw(", ");
9529 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9530 st->print_raw("\t# long");
9531 if (ra->C->alias_type(adr_type())->field() != NULL) {
9532 ciField* f = ra->C->alias_type(adr_type())->field();
9533 st->print(" ! Field: ");
9534 if (f->is_volatile())
9535 st->print("volatile ");
9536 f->holder()->name()->print_symbol_on(st);
9537 st->print(".");
9538 f->name()->print_symbol_on(st);
9539 if (f->is_constant())
9540 st->print(" (constant)");
9541 } else {
9542 if (ra->C->alias_type(adr_type())->is_volatile())
9543 st->print(" volatile!");
9544 }
9545}
9546#endif
9547#ifndef PRODUCT
9548void xorL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9549 // Start at oper_input_base() and count operands
9550 unsigned idx0 = 1;
9551 unsigned idx1 = 1; // dst
9552 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9553 st->print_raw("xorq ");
9554 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9555 st->print_raw(", ");
9556 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9557 st->print_raw("\t# long");
9558}
9559#endif
9560#ifndef PRODUCT
9561void xorL_rReg_im1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9562 // Start at oper_input_base() and count operands
9563 unsigned idx0 = 1;
9564 unsigned idx1 = 1; // dst
9565 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
9566 st->print_raw("notq ");
9567 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9568}
9569#endif
9570#ifndef PRODUCT
9571void xorL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9572 // Start at oper_input_base() and count operands
9573 unsigned idx0 = 1;
9574 unsigned idx1 = 1; // dst
9575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9576 st->print_raw("xorq ");
9577 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9578 st->print_raw(", ");
9579 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9580 st->print_raw("\t# long");
9581}
9582#endif
9583#ifndef PRODUCT
9584void xorL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9585 // Start at oper_input_base() and count operands
9586 unsigned idx0 = 2;
9587 unsigned idx1 = 2; // dst
9588 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9589 st->print_raw("xorq ");
9590 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9591 st->print_raw(", ");
9592 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9593 st->print_raw("\t# long");
9594}
9595#endif
9596#ifndef PRODUCT
9597void xorL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9598 // Start at oper_input_base() and count operands
9599 unsigned idx0 = 2;
9600 unsigned idx1 = 2; // src
9601 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
9602 st->print_raw("xorq ");
9603 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
9604 st->print_raw(", ");
9605 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9606 st->print_raw("\t# long");
9607}
9608#endif
9609#ifndef PRODUCT
9610void xorL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9611 // Start at oper_input_base() and count operands
9612 unsigned idx0 = 2;
9613 unsigned idx1 = 2; // dst
9614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9615 st->print_raw("xorq ");
9616 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9617 st->print_raw(", ");
9618 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9619 st->print_raw("\t# long");
9620 if (ra->C->alias_type(adr_type())->field() != NULL) {
9621 ciField* f = ra->C->alias_type(adr_type())->field();
9622 st->print(" ! Field: ");
9623 if (f->is_volatile())
9624 st->print("volatile ");
9625 f->holder()->name()->print_symbol_on(st);
9626 st->print(".");
9627 f->name()->print_symbol_on(st);
9628 if (f->is_constant())
9629 st->print(" (constant)");
9630 } else {
9631 if (ra->C->alias_type(adr_type())->is_volatile())
9632 st->print(" volatile!");
9633 }
9634}
9635#endif
9636#ifndef PRODUCT
9637void xorL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9638 // Start at oper_input_base() and count operands
9639 unsigned idx0 = 2;
9640 unsigned idx1 = 2; // dst
9641 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9642 st->print_raw("xorq ");
9643 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9644 st->print_raw(", ");
9645 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9646 st->print_raw("\t# long");
9647 if (ra->C->alias_type(adr_type())->field() != NULL) {
9648 ciField* f = ra->C->alias_type(adr_type())->field();
9649 st->print(" ! Field: ");
9650 if (f->is_volatile())
9651 st->print("volatile ");
9652 f->holder()->name()->print_symbol_on(st);
9653 st->print(".");
9654 f->name()->print_symbol_on(st);
9655 if (f->is_constant())
9656 st->print(" (constant)");
9657 } else {
9658 if (ra->C->alias_type(adr_type())->is_volatile())
9659 st->print(" volatile!");
9660 }
9661}
9662#endif
9663#ifndef PRODUCT
9664void xorL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9665 // Start at oper_input_base() and count operands
9666 unsigned idx0 = 2;
9667 unsigned idx1 = 2; // dst
9668 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
9669 st->print_raw("xorq ");
9670 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9671 st->print_raw(", ");
9672 opnd_array(2)->ext_format(ra, this,idx2, st); // src
9673 st->print_raw("\t# long");
9674 if (ra->C->alias_type(adr_type())->field() != NULL) {
9675 ciField* f = ra->C->alias_type(adr_type())->field();
9676 st->print(" ! Field: ");
9677 if (f->is_volatile())
9678 st->print("volatile ");
9679 f->holder()->name()->print_symbol_on(st);
9680 st->print(".");
9681 f->name()->print_symbol_on(st);
9682 if (f->is_constant())
9683 st->print(" (constant)");
9684 } else {
9685 if (ra->C->alias_type(adr_type())->is_volatile())
9686 st->print(" volatile!");
9687 }
9688}
9689#endif
9690#ifndef PRODUCT
9691void convI2BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9692 // Start at oper_input_base() and count operands
9693 unsigned idx0 = 1;
9694 unsigned idx1 = 1; // src
9695 st->print_raw("testl ");
9696 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9697 st->print_raw(", ");
9698 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9699 st->print_raw("\t# ci2b\n\t");
9700 st->print_raw("setnz ");
9701 opnd_array(0)->int_format(ra, this, st); // dst
9702 st->print_raw("\n\t");
9703 st->print_raw("movzbl ");
9704 opnd_array(0)->int_format(ra, this, st); // dst
9705 st->print_raw(", ");
9706 opnd_array(0)->int_format(ra, this, st); // dst
9707}
9708#endif
9709#ifndef PRODUCT
9710void convP2BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9711 // Start at oper_input_base() and count operands
9712 unsigned idx0 = 1;
9713 unsigned idx1 = 1; // src
9714 st->print_raw("testq ");
9715 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9716 st->print_raw(", ");
9717 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9718 st->print_raw("\t# cp2b\n\t");
9719 st->print_raw("setnz ");
9720 opnd_array(0)->int_format(ra, this, st); // dst
9721 st->print_raw("\n\t");
9722 st->print_raw("movzbl ");
9723 opnd_array(0)->int_format(ra, this, st); // dst
9724 st->print_raw(", ");
9725 opnd_array(0)->int_format(ra, this, st); // dst
9726}
9727#endif
9728#ifndef PRODUCT
9729void cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9730 // Start at oper_input_base() and count operands
9731 unsigned idx0 = 1;
9732 unsigned idx1 = 1; // p
9733 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
9734 st->print_raw("cmpl ");
9735 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9736 st->print_raw(", ");
9737 opnd_array(2)->ext_format(ra, this,idx2, st); // q
9738 st->print_raw("\t# cmpLTMask\n\t");
9739 st->print_raw("setlt ");
9740 opnd_array(0)->int_format(ra, this, st); // dst
9741 st->print_raw("\n\t");
9742 st->print_raw("movzbl ");
9743 opnd_array(0)->int_format(ra, this, st); // dst
9744 st->print_raw(", ");
9745 opnd_array(0)->int_format(ra, this, st); // dst
9746 st->print_raw("\n\t");
9747 st->print_raw("negl ");
9748 opnd_array(0)->int_format(ra, this, st); // dst
9749}
9750#endif
9751#ifndef PRODUCT
9752void cmpLTMask0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9753 // Start at oper_input_base() and count operands
9754 unsigned idx0 = 1;
9755 unsigned idx1 = 1; // dst
9756 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
9757 st->print_raw("sarl ");
9758 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
9759 st->print_raw(", #31\t# cmpLTMask0");
9760}
9761#endif
9762#ifndef PRODUCT
9763void cadd_cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9764 // Start at oper_input_base() and count operands
9765 unsigned idx0 = 1;
9766 unsigned idx1 = 1; // p
9767 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
9768 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
9769 st->print_raw("subl ");
9770 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9771 st->print_raw(",");
9772 opnd_array(2)->ext_format(ra, this,idx2, st); // q
9773 st->print_raw("\t# cadd_cmpLTMask\n\t");
9774 st->print_raw("jge done\n\t");
9775 st->print_raw("addl ");
9776 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9777 st->print_raw(",");
9778 opnd_array(3)->ext_format(ra, this,idx3, st); // y
9779 st->print_raw("\n");
9780 st->print_raw("done: ");
9781}
9782#endif
9783#ifndef PRODUCT
9784void cadd_cmpLTMask_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9785 // Start at oper_input_base() and count operands
9786 unsigned idx0 = 1;
9787 unsigned idx1 = 1; // p
9788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
9789 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
9790 st->print_raw("subl ");
9791 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9792 st->print_raw(",");
9793 opnd_array(2)->ext_format(ra, this,idx2, st); // q
9794 st->print_raw("\t# cadd_cmpLTMask\n\t");
9795 st->print_raw("jge done\n\t");
9796 st->print_raw("addl ");
9797 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9798 st->print_raw(",");
9799 opnd_array(3)->ext_format(ra, this,idx3, st); // y
9800 st->print_raw("\n");
9801 st->print_raw("done: ");
9802}
9803#endif
9804#ifndef PRODUCT
9805void cadd_cmpLTMask_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9806 // Start at oper_input_base() and count operands
9807 unsigned idx0 = 1;
9808 unsigned idx1 = 1; // y
9809 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
9810 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
9811 st->print_raw("subl ");
9812 opnd_array(2)->ext_format(ra, this,idx2, st); // p
9813 st->print_raw(",");
9814 opnd_array(3)->ext_format(ra, this,idx3, st); // q
9815 st->print_raw("\t# cadd_cmpLTMask\n\t");
9816 st->print_raw("jge done\n\t");
9817 st->print_raw("addl ");
9818 opnd_array(2)->ext_format(ra, this,idx2, st); // p
9819 st->print_raw(",");
9820 opnd_array(1)->ext_format(ra, this,idx1, st); // y
9821 st->print_raw("\n");
9822 st->print_raw("done: ");
9823}
9824#endif
9825#ifndef PRODUCT
9826void cadd_cmpLTMask_2Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9827 // Start at oper_input_base() and count operands
9828 unsigned idx0 = 1;
9829 unsigned idx1 = 1; // p
9830 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
9831 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
9832 st->print_raw("subl ");
9833 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9834 st->print_raw(",");
9835 opnd_array(2)->ext_format(ra, this,idx2, st); // q
9836 st->print_raw("\t# cadd_cmpLTMask\n\t");
9837 st->print_raw("jge done\n\t");
9838 st->print_raw("addl ");
9839 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9840 st->print_raw(",");
9841 opnd_array(3)->ext_format(ra, this,idx3, st); // y
9842 st->print_raw("\n");
9843 st->print_raw("done: ");
9844}
9845#endif
9846#ifndef PRODUCT
9847void and_cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9848 // Start at oper_input_base() and count operands
9849 unsigned idx0 = 1;
9850 unsigned idx1 = 1; // p
9851 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
9852 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
9853 st->print_raw("cmpl ");
9854 opnd_array(1)->ext_format(ra, this,idx1, st); // p
9855 st->print_raw(", ");
9856 opnd_array(2)->ext_format(ra, this,idx2, st); // q
9857 st->print_raw("\t# and_cmpLTMask\n\t");
9858 st->print_raw("jlt done\n\t");
9859 st->print_raw("xorl ");
9860 opnd_array(3)->ext_format(ra, this,idx3, st); // y
9861 st->print_raw(", ");
9862 opnd_array(3)->ext_format(ra, this,idx3, st); // y
9863 st->print_raw("\n");
9864 st->print_raw("done: ");
9865}
9866#endif
9867#ifndef PRODUCT
9868void and_cmpLTMask_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
9869 // Start at oper_input_base() and count operands
9870 unsigned idx0 = 1;
9871 unsigned idx1 = 1; // y
9872 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
9873 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
9874 st->print_raw("cmpl ");
9875 opnd_array(2)->ext_format(ra, this,idx2, st); // p
9876 st->print_raw(", ");
9877 opnd_array(3)->ext_format(ra, this,idx3, st); // q
9878 st->print_raw("\t# and_cmpLTMask\n\t");
9879 st->print_raw("jlt done\n\t");
9880 st->print_raw("xorl ");
9881 opnd_array(1)->ext_format(ra, this,idx1, st); // y
9882 st->print_raw(", ");
9883 opnd_array(1)->ext_format(ra, this,idx1, st); // y
9884 st->print_raw("\n");
9885 st->print_raw("done: ");
9886}
9887#endif
9888#ifndef PRODUCT
9889void cmpF_cc_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9890 // Start at oper_input_base() and count operands
9891 unsigned idx0 = 1;
9892 unsigned idx1 = 1; // src1
9893 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
9894 st->print_raw("ucomiss ");
9895 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9896 st->print_raw(", ");
9897 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
9898 st->print_raw("\n\t");
9899 st->print_raw("jnp,s exit\n\t");
9900 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
9901 st->print_raw("andq [rsp], #0xffffff2b\n\t");
9902 st->print_raw("popfq\n");
9903 st->print_raw("exit:");
9904}
9905#endif
9906#ifndef PRODUCT
9907void cmpF_cc_reg_CFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9908 // Start at oper_input_base() and count operands
9909 unsigned idx0 = 1;
9910 unsigned idx1 = 1; // src1
9911 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
9912 st->print_raw("ucomiss ");
9913 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9914 st->print_raw(", ");
9915 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
9916}
9917#endif
9918#ifndef PRODUCT
9919void cmpF_cc_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9920 // Start at oper_input_base() and count operands
9921 unsigned idx0 = 2;
9922 unsigned idx1 = 2; // src1
9923 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
9924 st->print_raw("ucomiss ");
9925 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9926 st->print_raw(", ");
9927 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
9928 st->print_raw("\n\t");
9929 st->print_raw("jnp,s exit\n\t");
9930 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
9931 st->print_raw("andq [rsp], #0xffffff2b\n\t");
9932 st->print_raw("popfq\n");
9933 st->print_raw("exit:");
9934}
9935#endif
9936#ifndef PRODUCT
9937void cmpF_cc_memCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9938 // Start at oper_input_base() and count operands
9939 unsigned idx0 = 2;
9940 unsigned idx1 = 2; // src1
9941 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
9942 st->print_raw("ucomiss ");
9943 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9944 st->print_raw(", ");
9945 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
9946}
9947#endif
9948#ifndef PRODUCT
9949void cmpF_cc_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9950 // Start at oper_input_base() and count operands
9951 unsigned idx0 = 1;
9952 unsigned idx1 = 1; // src
9953 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
9954 st->print_raw("ucomiss ");
9955 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9956 st->print_raw(", [");
9957 st->print("constant table base + #%d", constant_offset_unchecked());
9958 st->print_raw("]\t# load from constant table: float=");
9959 opnd_array(2)->ext_format(ra, this,idx2, st); // con
9960 st->print_raw("\n\t");
9961 st->print_raw("jnp,s exit\n\t");
9962 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
9963 st->print_raw("andq [rsp], #0xffffff2b\n\t");
9964 st->print_raw("popfq\n");
9965 st->print_raw("exit:");
9966}
9967#endif
9968#ifndef PRODUCT
9969void cmpF_cc_immCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9970 // Start at oper_input_base() and count operands
9971 unsigned idx0 = 1;
9972 unsigned idx1 = 1; // src
9973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
9974 st->print_raw("ucomiss ");
9975 opnd_array(1)->ext_format(ra, this,idx1, st); // src
9976 st->print_raw(", [");
9977 st->print("constant table base + #%d", constant_offset_unchecked());
9978 st->print_raw("]\t# load from constant table: float=");
9979 opnd_array(2)->ext_format(ra, this,idx2, st); // con
9980}
9981#endif
9982#ifndef PRODUCT
9983void cmpD_cc_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
9984 // Start at oper_input_base() and count operands
9985 unsigned idx0 = 1;
9986 unsigned idx1 = 1; // src1
9987 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
9988 st->print_raw("ucomisd ");
9989 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
9990 st->print_raw(", ");
9991 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
9992 st->print_raw("\n\t");
9993 st->print_raw("jnp,s exit\n\t");
9994 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
9995 st->print_raw("andq [rsp], #0xffffff2b\n\t");
9996 st->print_raw("popfq\n");
9997 st->print_raw("exit:");
9998}
9999#endif
10000#ifndef PRODUCT
10001void cmpD_cc_reg_CFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10002 // Start at oper_input_base() and count operands
10003 unsigned idx0 = 1;
10004 unsigned idx1 = 1; // src1
10005 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10006 st->print_raw("ucomisd ");
10007 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10008 st->print_raw(", ");
10009 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10010 st->print_raw(" test");
10011}
10012#endif
10013#ifndef PRODUCT
10014void cmpD_cc_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10015 // Start at oper_input_base() and count operands
10016 unsigned idx0 = 2;
10017 unsigned idx1 = 2; // src1
10018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10019 st->print_raw("ucomisd ");
10020 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10021 st->print_raw(", ");
10022 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10023 st->print_raw("\n\t");
10024 st->print_raw("jnp,s exit\n\t");
10025 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
10026 st->print_raw("andq [rsp], #0xffffff2b\n\t");
10027 st->print_raw("popfq\n");
10028 st->print_raw("exit:");
10029}
10030#endif
10031#ifndef PRODUCT
10032void cmpD_cc_memCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10033 // Start at oper_input_base() and count operands
10034 unsigned idx0 = 2;
10035 unsigned idx1 = 2; // src1
10036 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10037 st->print_raw("ucomisd ");
10038 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10039 st->print_raw(", ");
10040 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10041}
10042#endif
10043#ifndef PRODUCT
10044void cmpD_cc_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10045 // Start at oper_input_base() and count operands
10046 unsigned idx0 = 1;
10047 unsigned idx1 = 1; // src
10048 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
10049 st->print_raw("ucomisd ");
10050 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10051 st->print_raw(", [");
10052 st->print("constant table base + #%d", constant_offset_unchecked());
10053 st->print_raw("]\t# load from constant table: double=");
10054 opnd_array(2)->ext_format(ra, this,idx2, st); // con
10055 st->print_raw("\n\t");
10056 st->print_raw("jnp,s exit\n\t");
10057 st->print_raw("pushfq\t# saw NaN, set CF\n\t");
10058 st->print_raw("andq [rsp], #0xffffff2b\n\t");
10059 st->print_raw("popfq\n");
10060 st->print_raw("exit:");
10061}
10062#endif
10063#ifndef PRODUCT
10064void cmpD_cc_immCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10065 // Start at oper_input_base() and count operands
10066 unsigned idx0 = 1;
10067 unsigned idx1 = 1; // src
10068 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
10069 st->print_raw("ucomisd ");
10070 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10071 st->print_raw(", [");
10072 st->print("constant table base + #%d", constant_offset_unchecked());
10073 st->print_raw("]\t# load from constant table: double=");
10074 opnd_array(2)->ext_format(ra, this,idx2, st); // con
10075}
10076#endif
10077#ifndef PRODUCT
10078void cmpF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10079 // Start at oper_input_base() and count operands
10080 unsigned idx0 = 1;
10081 unsigned idx1 = 1; // src1
10082 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10083 st->print_raw("ucomiss ");
10084 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10085 st->print_raw(", ");
10086 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10087 st->print_raw("\n\t");
10088 st->print_raw("movl ");
10089 opnd_array(0)->int_format(ra, this, st); // dst
10090 st->print_raw(", #-1\n\t");
10091 st->print_raw("jp,s done\n\t");
10092 st->print_raw("jb,s done\n\t");
10093 st->print_raw("setne ");
10094 opnd_array(0)->int_format(ra, this, st); // dst
10095 st->print_raw("\n\t");
10096 st->print_raw("movzbl ");
10097 opnd_array(0)->int_format(ra, this, st); // dst
10098 st->print_raw(", ");
10099 opnd_array(0)->int_format(ra, this, st); // dst
10100 st->print_raw("\n");
10101 st->print_raw("done:");
10102}
10103#endif
10104#ifndef PRODUCT
10105void cmpF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10106 // Start at oper_input_base() and count operands
10107 unsigned idx0 = 2;
10108 unsigned idx1 = 2; // src1
10109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10110 st->print_raw("ucomiss ");
10111 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10112 st->print_raw(", ");
10113 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10114 st->print_raw("\n\t");
10115 st->print_raw("movl ");
10116 opnd_array(0)->int_format(ra, this, st); // dst
10117 st->print_raw(", #-1\n\t");
10118 st->print_raw("jp,s done\n\t");
10119 st->print_raw("jb,s done\n\t");
10120 st->print_raw("setne ");
10121 opnd_array(0)->int_format(ra, this, st); // dst
10122 st->print_raw("\n\t");
10123 st->print_raw("movzbl ");
10124 opnd_array(0)->int_format(ra, this, st); // dst
10125 st->print_raw(", ");
10126 opnd_array(0)->int_format(ra, this, st); // dst
10127 st->print_raw("\n");
10128 st->print_raw("done:");
10129}
10130#endif
10131#ifndef PRODUCT
10132void cmpF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10133 // Start at oper_input_base() and count operands
10134 unsigned idx0 = 1;
10135 unsigned idx1 = 1; // src
10136 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
10137 st->print_raw("ucomiss ");
10138 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10139 st->print_raw(", [");
10140 st->print("constant table base + #%d", constant_offset_unchecked());
10141 st->print_raw("]\t# load from constant table: float=");
10142 opnd_array(2)->ext_format(ra, this,idx2, st); // con
10143 st->print_raw("\n\t");
10144 st->print_raw("movl ");
10145 opnd_array(0)->int_format(ra, this, st); // dst
10146 st->print_raw(", #-1\n\t");
10147 st->print_raw("jp,s done\n\t");
10148 st->print_raw("jb,s done\n\t");
10149 st->print_raw("setne ");
10150 opnd_array(0)->int_format(ra, this, st); // dst
10151 st->print_raw("\n\t");
10152 st->print_raw("movzbl ");
10153 opnd_array(0)->int_format(ra, this, st); // dst
10154 st->print_raw(", ");
10155 opnd_array(0)->int_format(ra, this, st); // dst
10156 st->print_raw("\n");
10157 st->print_raw("done:");
10158}
10159#endif
10160#ifndef PRODUCT
10161void cmpD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10162 // Start at oper_input_base() and count operands
10163 unsigned idx0 = 1;
10164 unsigned idx1 = 1; // src1
10165 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10166 st->print_raw("ucomisd ");
10167 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10168 st->print_raw(", ");
10169 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10170 st->print_raw("\n\t");
10171 st->print_raw("movl ");
10172 opnd_array(0)->int_format(ra, this, st); // dst
10173 st->print_raw(", #-1\n\t");
10174 st->print_raw("jp,s done\n\t");
10175 st->print_raw("jb,s done\n\t");
10176 st->print_raw("setne ");
10177 opnd_array(0)->int_format(ra, this, st); // dst
10178 st->print_raw("\n\t");
10179 st->print_raw("movzbl ");
10180 opnd_array(0)->int_format(ra, this, st); // dst
10181 st->print_raw(", ");
10182 opnd_array(0)->int_format(ra, this, st); // dst
10183 st->print_raw("\n");
10184 st->print_raw("done:");
10185}
10186#endif
10187#ifndef PRODUCT
10188void cmpD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10189 // Start at oper_input_base() and count operands
10190 unsigned idx0 = 2;
10191 unsigned idx1 = 2; // src1
10192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
10193 st->print_raw("ucomisd ");
10194 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
10195 st->print_raw(", ");
10196 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
10197 st->print_raw("\n\t");
10198 st->print_raw("movl ");
10199 opnd_array(0)->int_format(ra, this, st); // dst
10200 st->print_raw(", #-1\n\t");
10201 st->print_raw("jp,s done\n\t");
10202 st->print_raw("jb,s done\n\t");
10203 st->print_raw("setne ");
10204 opnd_array(0)->int_format(ra, this, st); // dst
10205 st->print_raw("\n\t");
10206 st->print_raw("movzbl ");
10207 opnd_array(0)->int_format(ra, this, st); // dst
10208 st->print_raw(", ");
10209 opnd_array(0)->int_format(ra, this, st); // dst
10210 st->print_raw("\n");
10211 st->print_raw("done:");
10212}
10213#endif
10214#ifndef PRODUCT
10215void cmpD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10216 // Start at oper_input_base() and count operands
10217 unsigned idx0 = 1;
10218 unsigned idx1 = 1; // src
10219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
10220 st->print_raw("ucomisd ");
10221 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10222 st->print_raw(", [");
10223 st->print("constant table base + #%d", constant_offset_unchecked());
10224 st->print_raw("]\t# load from constant table: double=");
10225 opnd_array(2)->ext_format(ra, this,idx2, st); // con
10226 st->print_raw("\n\t");
10227 st->print_raw("movl ");
10228 opnd_array(0)->int_format(ra, this, st); // dst
10229 st->print_raw(", #-1\n\t");
10230 st->print_raw("jp,s done\n\t");
10231 st->print_raw("jb,s done\n\t");
10232 st->print_raw("setne ");
10233 opnd_array(0)->int_format(ra, this, st); // dst
10234 st->print_raw("\n\t");
10235 st->print_raw("movzbl ");
10236 opnd_array(0)->int_format(ra, this, st); // dst
10237 st->print_raw(", ");
10238 opnd_array(0)->int_format(ra, this, st); // dst
10239 st->print_raw("\n");
10240 st->print_raw("done:");
10241}
10242#endif
10243#ifndef PRODUCT
10244void roundFloat_nopNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10245}
10246#endif
10247#ifndef PRODUCT
10248void roundDouble_nopNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10249}
10250#endif
10251#ifndef PRODUCT
10252void convF2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10253 // Start at oper_input_base() and count operands
10254 unsigned idx0 = 1;
10255 unsigned idx1 = 1; // src
10256 st->print_raw("cvtss2sd ");
10257 opnd_array(0)->int_format(ra, this, st); // dst
10258 st->print_raw(", ");
10259 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10260}
10261#endif
10262#ifndef PRODUCT
10263void convF2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10264 // Start at oper_input_base() and count operands
10265 unsigned idx0 = 2;
10266 unsigned idx1 = 2; // src
10267 st->print_raw("cvtss2sd ");
10268 opnd_array(0)->int_format(ra, this, st); // dst
10269 st->print_raw(", ");
10270 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10271}
10272#endif
10273#ifndef PRODUCT
10274void convD2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10275 // Start at oper_input_base() and count operands
10276 unsigned idx0 = 1;
10277 unsigned idx1 = 1; // src
10278 st->print_raw("cvtsd2ss ");
10279 opnd_array(0)->int_format(ra, this, st); // dst
10280 st->print_raw(", ");
10281 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10282}
10283#endif
10284#ifndef PRODUCT
10285void convD2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10286 // Start at oper_input_base() and count operands
10287 unsigned idx0 = 2;
10288 unsigned idx1 = 2; // src
10289 st->print_raw("cvtsd2ss ");
10290 opnd_array(0)->int_format(ra, this, st); // dst
10291 st->print_raw(", ");
10292 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10293}
10294#endif
10295#ifndef PRODUCT
10296void convF2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10297 // Start at oper_input_base() and count operands
10298 unsigned idx0 = 1;
10299 unsigned idx1 = 1; // src
10300 st->print_raw("cvttss2sil ");
10301 opnd_array(0)->int_format(ra, this, st); // dst
10302 st->print_raw(", ");
10303 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10304 st->print_raw("\t# f2i\n\t");
10305 st->print_raw("cmpl ");
10306 opnd_array(0)->int_format(ra, this, st); // dst
10307 st->print_raw(", #0x80000000\n\t");
10308 st->print_raw("jne,s done\n\t");
10309 st->print_raw("subq rsp, #8\n\t");
10310 st->print_raw("movss [rsp], ");
10311 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10312 st->print_raw("\n\t");
10313 st->print_raw("call f2i_fixup\n\t");
10314 st->print_raw("popq ");
10315 opnd_array(0)->int_format(ra, this, st); // dst
10316 st->print_raw("\n");
10317 st->print_raw("done: ");
10318}
10319#endif
10320#ifndef PRODUCT
10321void convF2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10322 // Start at oper_input_base() and count operands
10323 unsigned idx0 = 1;
10324 unsigned idx1 = 1; // src
10325 st->print_raw("cvttss2siq ");
10326 opnd_array(0)->int_format(ra, this, st); // dst
10327 st->print_raw(", ");
10328 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10329 st->print_raw("\t# f2l\n\t");
10330 st->print_raw("cmpq ");
10331 opnd_array(0)->int_format(ra, this, st); // dst
10332 st->print_raw(", [0x8000000000000000]\n\t");
10333 st->print_raw("jne,s done\n\t");
10334 st->print_raw("subq rsp, #8\n\t");
10335 st->print_raw("movss [rsp], ");
10336 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10337 st->print_raw("\n\t");
10338 st->print_raw("call f2l_fixup\n\t");
10339 st->print_raw("popq ");
10340 opnd_array(0)->int_format(ra, this, st); // dst
10341 st->print_raw("\n");
10342 st->print_raw("done: ");
10343}
10344#endif
10345#ifndef PRODUCT
10346void convD2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10347 // Start at oper_input_base() and count operands
10348 unsigned idx0 = 1;
10349 unsigned idx1 = 1; // src
10350 st->print_raw("cvttsd2sil ");
10351 opnd_array(0)->int_format(ra, this, st); // dst
10352 st->print_raw(", ");
10353 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10354 st->print_raw("\t# d2i\n\t");
10355 st->print_raw("cmpl ");
10356 opnd_array(0)->int_format(ra, this, st); // dst
10357 st->print_raw(", #0x80000000\n\t");
10358 st->print_raw("jne,s done\n\t");
10359 st->print_raw("subq rsp, #8\n\t");
10360 st->print_raw("movsd [rsp], ");
10361 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10362 st->print_raw("\n\t");
10363 st->print_raw("call d2i_fixup\n\t");
10364 st->print_raw("popq ");
10365 opnd_array(0)->int_format(ra, this, st); // dst
10366 st->print_raw("\n");
10367 st->print_raw("done: ");
10368}
10369#endif
10370#ifndef PRODUCT
10371void convD2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10372 // Start at oper_input_base() and count operands
10373 unsigned idx0 = 1;
10374 unsigned idx1 = 1; // src
10375 st->print_raw("cvttsd2siq ");
10376 opnd_array(0)->int_format(ra, this, st); // dst
10377 st->print_raw(", ");
10378 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10379 st->print_raw("\t# d2l\n\t");
10380 st->print_raw("cmpq ");
10381 opnd_array(0)->int_format(ra, this, st); // dst
10382 st->print_raw(", [0x8000000000000000]\n\t");
10383 st->print_raw("jne,s done\n\t");
10384 st->print_raw("subq rsp, #8\n\t");
10385 st->print_raw("movsd [rsp], ");
10386 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10387 st->print_raw("\n\t");
10388 st->print_raw("call d2l_fixup\n\t");
10389 st->print_raw("popq ");
10390 opnd_array(0)->int_format(ra, this, st); // dst
10391 st->print_raw("\n");
10392 st->print_raw("done: ");
10393}
10394#endif
10395#ifndef PRODUCT
10396void convI2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10397 // Start at oper_input_base() and count operands
10398 unsigned idx0 = 1;
10399 unsigned idx1 = 1; // src
10400 st->print_raw("cvtsi2ssl ");
10401 opnd_array(0)->int_format(ra, this, st); // dst
10402 st->print_raw(", ");
10403 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10404 st->print_raw("\t# i2f");
10405}
10406#endif
10407#ifndef PRODUCT
10408void convI2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10409 // Start at oper_input_base() and count operands
10410 unsigned idx0 = 2;
10411 unsigned idx1 = 2; // src
10412 st->print_raw("cvtsi2ssl ");
10413 opnd_array(0)->int_format(ra, this, st); // dst
10414 st->print_raw(", ");
10415 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10416 st->print_raw("\t# i2f");
10417}
10418#endif
10419#ifndef PRODUCT
10420void convI2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10421 // Start at oper_input_base() and count operands
10422 unsigned idx0 = 1;
10423 unsigned idx1 = 1; // src
10424 st->print_raw("cvtsi2sdl ");
10425 opnd_array(0)->int_format(ra, this, st); // dst
10426 st->print_raw(", ");
10427 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10428 st->print_raw("\t# i2d");
10429}
10430#endif
10431#ifndef PRODUCT
10432void convI2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10433 // Start at oper_input_base() and count operands
10434 unsigned idx0 = 2;
10435 unsigned idx1 = 2; // src
10436 st->print_raw("cvtsi2sdl ");
10437 opnd_array(0)->int_format(ra, this, st); // dst
10438 st->print_raw(", ");
10439 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10440 st->print_raw("\t# i2d");
10441}
10442#endif
10443#ifndef PRODUCT
10444void convXI2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10445 // Start at oper_input_base() and count operands
10446 unsigned idx0 = 1;
10447 unsigned idx1 = 1; // src
10448 st->print_raw("movdl ");
10449 opnd_array(0)->int_format(ra, this, st); // dst
10450 st->print_raw(", ");
10451 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10452 st->print_raw("\n\t");
10453 st->print_raw("cvtdq2psl ");
10454 opnd_array(0)->int_format(ra, this, st); // dst
10455 st->print_raw(", ");
10456 opnd_array(0)->int_format(ra, this, st); // dst
10457 st->print_raw("\t# i2f");
10458}
10459#endif
10460#ifndef PRODUCT
10461void convXI2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10462 // Start at oper_input_base() and count operands
10463 unsigned idx0 = 1;
10464 unsigned idx1 = 1; // src
10465 st->print_raw("movdl ");
10466 opnd_array(0)->int_format(ra, this, st); // dst
10467 st->print_raw(", ");
10468 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10469 st->print_raw("\n\t");
10470 st->print_raw("cvtdq2pdl ");
10471 opnd_array(0)->int_format(ra, this, st); // dst
10472 st->print_raw(", ");
10473 opnd_array(0)->int_format(ra, this, st); // dst
10474 st->print_raw("\t# i2d");
10475}
10476#endif
10477#ifndef PRODUCT
10478void convL2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10479 // Start at oper_input_base() and count operands
10480 unsigned idx0 = 1;
10481 unsigned idx1 = 1; // src
10482 st->print_raw("cvtsi2ssq ");
10483 opnd_array(0)->int_format(ra, this, st); // dst
10484 st->print_raw(", ");
10485 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10486 st->print_raw("\t# l2f");
10487}
10488#endif
10489#ifndef PRODUCT
10490void convL2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10491 // Start at oper_input_base() and count operands
10492 unsigned idx0 = 2;
10493 unsigned idx1 = 2; // src
10494 st->print_raw("cvtsi2ssq ");
10495 opnd_array(0)->int_format(ra, this, st); // dst
10496 st->print_raw(", ");
10497 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10498 st->print_raw("\t# l2f");
10499}
10500#endif
10501#ifndef PRODUCT
10502void convL2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10503 // Start at oper_input_base() and count operands
10504 unsigned idx0 = 1;
10505 unsigned idx1 = 1; // src
10506 st->print_raw("cvtsi2sdq ");
10507 opnd_array(0)->int_format(ra, this, st); // dst
10508 st->print_raw(", ");
10509 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10510 st->print_raw("\t# l2d");
10511}
10512#endif
10513#ifndef PRODUCT
10514void convL2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10515 // Start at oper_input_base() and count operands
10516 unsigned idx0 = 2;
10517 unsigned idx1 = 2; // src
10518 st->print_raw("cvtsi2sdq ");
10519 opnd_array(0)->int_format(ra, this, st); // dst
10520 st->print_raw(", ");
10521 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10522 st->print_raw("\t# l2d");
10523}
10524#endif
10525#ifndef PRODUCT
10526void convI2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10527 // Start at oper_input_base() and count operands
10528 unsigned idx0 = 1;
10529 unsigned idx1 = 1; // src
10530 st->print_raw("movslq ");
10531 opnd_array(0)->int_format(ra, this, st); // dst
10532 st->print_raw(", ");
10533 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10534 st->print_raw("\t# i2l");
10535}
10536#endif
10537#ifndef PRODUCT
10538void convI2L_reg_reg_zexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10539 // Start at oper_input_base() and count operands
10540 unsigned idx0 = 1;
10541 unsigned idx1 = 1; // src
10542 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
10543 st->print_raw("movl ");
10544 opnd_array(0)->int_format(ra, this, st); // dst
10545 st->print_raw(", ");
10546 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10547 st->print_raw("\t# i2l zero-extend\n\t");
10548}
10549#endif
10550#ifndef PRODUCT
10551void convI2L_reg_mem_zexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10552 // Start at oper_input_base() and count operands
10553 unsigned idx0 = 2;
10554 unsigned idx1 = 2; // src
10555 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
10556 st->print_raw("movl ");
10557 opnd_array(0)->int_format(ra, this, st); // dst
10558 st->print_raw(", ");
10559 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10560 st->print_raw("\t# i2l zero-extend\n\t");
10561}
10562#endif
10563#ifndef PRODUCT
10564void zerox_long_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10565 // Start at oper_input_base() and count operands
10566 unsigned idx0 = 1;
10567 unsigned idx1 = 1; // src
10568 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
10569 st->print_raw("movl ");
10570 opnd_array(0)->int_format(ra, this, st); // dst
10571 st->print_raw(", ");
10572 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10573 st->print_raw("\t# zero-extend long");
10574}
10575#endif
10576#ifndef PRODUCT
10577void convL2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10578 // Start at oper_input_base() and count operands
10579 unsigned idx0 = 1;
10580 unsigned idx1 = 1; // src
10581 st->print_raw("movl ");
10582 opnd_array(0)->int_format(ra, this, st); // dst
10583 st->print_raw(", ");
10584 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10585 st->print_raw("\t# l2i");
10586}
10587#endif
10588#ifndef PRODUCT
10589void MoveF2I_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10590 // Start at oper_input_base() and count operands
10591 unsigned idx0 = 1;
10592 unsigned idx1 = 1; // src
10593 st->print_raw("movl ");
10594 opnd_array(0)->int_format(ra, this, st); // dst
10595 st->print_raw(", ");
10596 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10597 st->print_raw("\t# MoveF2I_stack_reg");
10598}
10599#endif
10600#ifndef PRODUCT
10601void MoveI2F_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10602 // Start at oper_input_base() and count operands
10603 unsigned idx0 = 1;
10604 unsigned idx1 = 1; // src
10605 st->print_raw("movss ");
10606 opnd_array(0)->int_format(ra, this, st); // dst
10607 st->print_raw(", ");
10608 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10609 st->print_raw("\t# MoveI2F_stack_reg");
10610}
10611#endif
10612#ifndef PRODUCT
10613void MoveD2L_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10614 // Start at oper_input_base() and count operands
10615 unsigned idx0 = 1;
10616 unsigned idx1 = 1; // src
10617 st->print_raw("movq ");
10618 opnd_array(0)->int_format(ra, this, st); // dst
10619 st->print_raw(", ");
10620 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10621 st->print_raw("\t# MoveD2L_stack_reg");
10622}
10623#endif
10624#ifndef PRODUCT
10625void MoveL2D_stack_reg_partialNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10626 // Start at oper_input_base() and count operands
10627 unsigned idx0 = 1;
10628 unsigned idx1 = 1; // src
10629 st->print_raw("movlpd ");
10630 opnd_array(0)->int_format(ra, this, st); // dst
10631 st->print_raw(", ");
10632 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10633 st->print_raw("\t# MoveL2D_stack_reg");
10634}
10635#endif
10636#ifndef PRODUCT
10637void MoveL2D_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10638 // Start at oper_input_base() and count operands
10639 unsigned idx0 = 1;
10640 unsigned idx1 = 1; // src
10641 st->print_raw("movsd ");
10642 opnd_array(0)->int_format(ra, this, st); // dst
10643 st->print_raw(", ");
10644 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10645 st->print_raw("\t# MoveL2D_stack_reg");
10646}
10647#endif
10648#ifndef PRODUCT
10649void MoveF2I_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10650 // Start at oper_input_base() and count operands
10651 unsigned idx0 = 1;
10652 unsigned idx1 = 1; // src
10653 st->print_raw("movss ");
10654 opnd_array(0)->int_format(ra, this, st); // dst
10655 st->print_raw(", ");
10656 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10657 st->print_raw("\t# MoveF2I_reg_stack");
10658}
10659#endif
10660#ifndef PRODUCT
10661void MoveI2F_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10662 // Start at oper_input_base() and count operands
10663 unsigned idx0 = 1;
10664 unsigned idx1 = 1; // src
10665 st->print_raw("movl ");
10666 opnd_array(0)->int_format(ra, this, st); // dst
10667 st->print_raw(", ");
10668 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10669 st->print_raw("\t# MoveI2F_reg_stack");
10670}
10671#endif
10672#ifndef PRODUCT
10673void MoveD2L_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10674 // Start at oper_input_base() and count operands
10675 unsigned idx0 = 1;
10676 unsigned idx1 = 1; // src
10677 st->print_raw("movsd ");
10678 opnd_array(0)->int_format(ra, this, st); // dst
10679 st->print_raw(", ");
10680 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10681 st->print_raw("\t# MoveL2D_reg_stack");
10682}
10683#endif
10684#ifndef PRODUCT
10685void MoveL2D_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10686 // Start at oper_input_base() and count operands
10687 unsigned idx0 = 1;
10688 unsigned idx1 = 1; // src
10689 st->print_raw("movq ");
10690 opnd_array(0)->int_format(ra, this, st); // dst
10691 st->print_raw(", ");
10692 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10693 st->print_raw("\t# MoveL2D_reg_stack");
10694}
10695#endif
10696#ifndef PRODUCT
10697void MoveF2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10698 // Start at oper_input_base() and count operands
10699 unsigned idx0 = 1;
10700 unsigned idx1 = 1; // src
10701 st->print_raw("movd ");
10702 opnd_array(0)->int_format(ra, this, st); // dst
10703 st->print_raw(",");
10704 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10705 st->print_raw("\t# MoveF2I");
10706}
10707#endif
10708#ifndef PRODUCT
10709void MoveD2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10710 // Start at oper_input_base() and count operands
10711 unsigned idx0 = 1;
10712 unsigned idx1 = 1; // src
10713 st->print_raw("movd ");
10714 opnd_array(0)->int_format(ra, this, st); // dst
10715 st->print_raw(",");
10716 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10717 st->print_raw("\t# MoveD2L");
10718}
10719#endif
10720#ifndef PRODUCT
10721void MoveI2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10722 // Start at oper_input_base() and count operands
10723 unsigned idx0 = 1;
10724 unsigned idx1 = 1; // src
10725 st->print_raw("movd ");
10726 opnd_array(0)->int_format(ra, this, st); // dst
10727 st->print_raw(",");
10728 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10729 st->print_raw("\t# MoveI2F");
10730}
10731#endif
10732#ifndef PRODUCT
10733void MoveL2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10734 // Start at oper_input_base() and count operands
10735 unsigned idx0 = 1;
10736 unsigned idx1 = 1; // src
10737 st->print_raw("movd ");
10738 opnd_array(0)->int_format(ra, this, st); // dst
10739 st->print_raw(",");
10740 opnd_array(1)->ext_format(ra, this,idx1, st); // src
10741 st->print_raw("\t# MoveL2D");
10742}
10743#endif
10744#ifndef PRODUCT
10745void rep_stosNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10746 st->print_raw("xorq rax, rax\t# ClearArray:\n\t");
10747 st->print_raw("cmp InitArrayShortSize,rcx\n\t");
10748 st->print_raw("jg LARGE\n\t");
10749 st->print_raw("dec rcx\n\t");
10750 st->print_raw("js DONE\t# Zero length\n\t");
10751 st->print_raw("mov rax,(rdi,rcx,8)\t# LOOP\n\t");
10752 st->print_raw("dec rcx\n\t");
10753 st->print_raw("jge LOOP\n\t");
10754 st->print_raw("jmp DONE\n\t");
10755 st->print_raw("# LARGE:\n\t");
10756 if (UseFastStosb) {
10757 st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t");
10758 st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--\n\t");
10759 } else if (UseXMMForObjInit) {
10760 st->print_raw("mov rdi,rax\n\t");
10761 st->print_raw("vpxor ymm0,ymm0,ymm0\n\t");
10762 st->print_raw("jmpq L_zero_64_bytes\n\t");
10763 st->print_raw("# L_loop:\t# 64-byte LOOP\n\t");
10764 st->print_raw("vmovdqu ymm0,(rax)\n\t");
10765 st->print_raw("vmovdqu ymm0,0x20(rax)\n\t");
10766 st->print_raw("add 0x40,rax\n\t");
10767 st->print_raw("# L_zero_64_bytes:\n\t");
10768 st->print_raw("sub 0x8,rcx\n\t");
10769 st->print_raw("jge L_loop\n\t");
10770 st->print_raw("add 0x4,rcx\n\t");
10771 st->print_raw("jl L_tail\n\t");
10772 st->print_raw("vmovdqu ymm0,(rax)\n\t");
10773 st->print_raw("add 0x20,rax\n\t");
10774 st->print_raw("sub 0x4,rcx\n\t");
10775 st->print_raw("# L_tail:\t# Clearing tail bytes\n\t");
10776 st->print_raw("add 0x4,rcx\n\t");
10777 st->print_raw("jle L_end\n\t");
10778 st->print_raw("dec rcx\n\t");
10779 st->print_raw("# L_sloop:\t# 8-byte short loop\n\t");
10780 st->print_raw("vmovq xmm0,(rax)\n\t");
10781 st->print_raw("add 0x8,rax\n\t");
10782 st->print_raw("dec rcx\n\t");
10783 st->print_raw("jge L_sloop\n\t");
10784 st->print_raw("# L_end:\n\t");
10785 } else {
10786 st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--\n\t");
10787 }
10788 st->print_raw("# DONE");
10789}
10790#endif
10791#ifndef PRODUCT
10792void rep_stos_largeNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10793 if (UseFastStosb) {
10794 st->print_raw("xorq rax, rax\t# ClearArray:\n\t");
10795 st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t");
10796 st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--");
10797 } else if (UseXMMForObjInit) {
10798 st->print_raw("mov rdi,rax\t# ClearArray:\n\t");
10799 st->print_raw("vpxor ymm0,ymm0,ymm0\n\t");
10800 st->print_raw("jmpq L_zero_64_bytes\n\t");
10801 st->print_raw("# L_loop:\t# 64-byte LOOP\n\t");
10802 st->print_raw("vmovdqu ymm0,(rax)\n\t");
10803 st->print_raw("vmovdqu ymm0,0x20(rax)\n\t");
10804 st->print_raw("add 0x40,rax\n\t");
10805 st->print_raw("# L_zero_64_bytes:\n\t");
10806 st->print_raw("sub 0x8,rcx\n\t");
10807 st->print_raw("jge L_loop\n\t");
10808 st->print_raw("add 0x4,rcx\n\t");
10809 st->print_raw("jl L_tail\n\t");
10810 st->print_raw("vmovdqu ymm0,(rax)\n\t");
10811 st->print_raw("add 0x20,rax\n\t");
10812 st->print_raw("sub 0x4,rcx\n\t");
10813 st->print_raw("# L_tail:\t# Clearing tail bytes\n\t");
10814 st->print_raw("add 0x4,rcx\n\t");
10815 st->print_raw("jle L_end\n\t");
10816 st->print_raw("dec rcx\n\t");
10817 st->print_raw("# L_sloop:\t# 8-byte short loop\n\t");
10818 st->print_raw("vmovq xmm0,(rax)\n\t");
10819 st->print_raw("add 0x8,rax\n\t");
10820 st->print_raw("dec rcx\n\t");
10821 st->print_raw("jge L_sloop\n\t");
10822 st->print_raw("# L_end:\n\t");
10823 } else {
10824 st->print_raw("xorq rax, rax\t# ClearArray:\n\t");
10825 st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--");
10826 }
10827 }
10828#endif
10829#ifndef PRODUCT
10830void string_compareLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10831 // Start at oper_input_base() and count operands
10832 unsigned idx0 = 2;
10833 unsigned idx1 = 2; // str1
10834 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10835 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10836 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
10837 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
10838 st->print_raw("String Compare byte[] ");
10839 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10840 st->print_raw(",");
10841 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10842 st->print_raw(",");
10843 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10844 st->print_raw(",");
10845 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
10846 st->print_raw(" -> ");
10847 opnd_array(0)->int_format(ra, this, st); // result
10848 st->print_raw(" // KILL ");
10849 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1
10850}
10851#endif
10852#ifndef PRODUCT
10853void string_compareUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10854 // Start at oper_input_base() and count operands
10855 unsigned idx0 = 2;
10856 unsigned idx1 = 2; // str1
10857 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10858 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10859 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
10860 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
10861 st->print_raw("String Compare char[] ");
10862 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10863 st->print_raw(",");
10864 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10865 st->print_raw(",");
10866 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10867 st->print_raw(",");
10868 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
10869 st->print_raw(" -> ");
10870 opnd_array(0)->int_format(ra, this, st); // result
10871 st->print_raw(" // KILL ");
10872 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1
10873}
10874#endif
10875#ifndef PRODUCT
10876void string_compareLUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10877 // Start at oper_input_base() and count operands
10878 unsigned idx0 = 2;
10879 unsigned idx1 = 2; // str1
10880 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10881 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10882 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
10883 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
10884 st->print_raw("String Compare byte[] ");
10885 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10886 st->print_raw(",");
10887 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10888 st->print_raw(",");
10889 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10890 st->print_raw(",");
10891 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
10892 st->print_raw(" -> ");
10893 opnd_array(0)->int_format(ra, this, st); // result
10894 st->print_raw(" // KILL ");
10895 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1
10896}
10897#endif
10898#ifndef PRODUCT
10899void string_compareULNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10900 // Start at oper_input_base() and count operands
10901 unsigned idx0 = 2;
10902 unsigned idx1 = 2; // str1
10903 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10904 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10905 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
10906 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
10907 st->print_raw("String Compare byte[] ");
10908 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10909 st->print_raw(",");
10910 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10911 st->print_raw(",");
10912 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10913 st->print_raw(",");
10914 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
10915 st->print_raw(" -> ");
10916 opnd_array(0)->int_format(ra, this, st); // result
10917 st->print_raw(" // KILL ");
10918 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1
10919}
10920#endif
10921#ifndef PRODUCT
10922void string_indexof_conLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10923 // Start at oper_input_base() and count operands
10924 unsigned idx0 = 2;
10925 unsigned idx1 = 2; // str1
10926 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10927 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10928 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
10929 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
10930 st->print_raw("String IndexOf byte[] ");
10931 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10932 st->print_raw(",");
10933 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10934 st->print_raw(",");
10935 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10936 st->print_raw(",");
10937 opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2
10938 st->print_raw(" -> ");
10939 opnd_array(0)->int_format(ra, this, st); // result
10940 st->print_raw(" // KILL ");
10941 opnd_array(5)->ext_format(ra, this,idx5, st); // vec
10942 st->print_raw(", ");
10943 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10944 st->print_raw(", ");
10945 st->print_raw("RAX");
10946 st->print_raw(", ");
10947 st->print_raw("RCX");
10948}
10949#endif
10950#ifndef PRODUCT
10951void string_indexof_conUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10952 // Start at oper_input_base() and count operands
10953 unsigned idx0 = 2;
10954 unsigned idx1 = 2; // str1
10955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10956 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10957 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
10958 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
10959 st->print_raw("String IndexOf char[] ");
10960 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10961 st->print_raw(",");
10962 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10963 st->print_raw(",");
10964 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10965 st->print_raw(",");
10966 opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2
10967 st->print_raw(" -> ");
10968 opnd_array(0)->int_format(ra, this, st); // result
10969 st->print_raw(" // KILL ");
10970 opnd_array(5)->ext_format(ra, this,idx5, st); // vec
10971 st->print_raw(", ");
10972 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10973 st->print_raw(", ");
10974 st->print_raw("RAX");
10975 st->print_raw(", ");
10976 st->print_raw("RCX");
10977}
10978#endif
10979#ifndef PRODUCT
10980void string_indexof_conULNode::format(PhaseRegAlloc *ra, outputStream *st) const {
10981 // Start at oper_input_base() and count operands
10982 unsigned idx0 = 2;
10983 unsigned idx1 = 2; // str1
10984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
10985 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
10986 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
10987 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
10988 st->print_raw("String IndexOf char[] ");
10989 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
10990 st->print_raw(",");
10991 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
10992 st->print_raw(",");
10993 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
10994 st->print_raw(",");
10995 opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2
10996 st->print_raw(" -> ");
10997 opnd_array(0)->int_format(ra, this, st); // result
10998 st->print_raw(" // KILL ");
10999 opnd_array(5)->ext_format(ra, this,idx5, st); // vec
11000 st->print_raw(", ");
11001 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
11002 st->print_raw(", ");
11003 st->print_raw("RAX");
11004 st->print_raw(", ");
11005 st->print_raw("RCX");
11006}
11007#endif
11008#ifndef PRODUCT
11009void string_indexofLNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11010 // Start at oper_input_base() and count operands
11011 unsigned idx0 = 2;
11012 unsigned idx1 = 2; // str1
11013 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
11014 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
11015 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
11016 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
11017 st->print_raw("String IndexOf byte[] ");
11018 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
11019 st->print_raw(",");
11020 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
11021 st->print_raw(",");
11022 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
11023 st->print_raw(",");
11024 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
11025 st->print_raw(" -> ");
11026 opnd_array(0)->int_format(ra, this, st); // result
11027 st->print_raw(" // KILL all");
11028}
11029#endif
11030#ifndef PRODUCT
11031void string_indexofUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11032 // Start at oper_input_base() and count operands
11033 unsigned idx0 = 2;
11034 unsigned idx1 = 2; // str1
11035 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
11036 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
11037 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
11038 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
11039 st->print_raw("String IndexOf char[] ");
11040 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
11041 st->print_raw(",");
11042 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
11043 st->print_raw(",");
11044 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
11045 st->print_raw(",");
11046 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
11047 st->print_raw(" -> ");
11048 opnd_array(0)->int_format(ra, this, st); // result
11049 st->print_raw(" // KILL all");
11050}
11051#endif
11052#ifndef PRODUCT
11053void string_indexofULNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11054 // Start at oper_input_base() and count operands
11055 unsigned idx0 = 2;
11056 unsigned idx1 = 2; // str1
11057 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
11058 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
11059 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
11060 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec
11061 st->print_raw("String IndexOf char[] ");
11062 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
11063 st->print_raw(",");
11064 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
11065 st->print_raw(",");
11066 opnd_array(3)->ext_format(ra, this,idx3, st); // str2
11067 st->print_raw(",");
11068 opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2
11069 st->print_raw(" -> ");
11070 opnd_array(0)->int_format(ra, this, st); // result
11071 st->print_raw(" // KILL all");
11072}
11073#endif
11074#ifndef PRODUCT
11075void string_indexofU_charNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11076 // Start at oper_input_base() and count operands
11077 unsigned idx0 = 2;
11078 unsigned idx1 = 2; // str1
11079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
11080 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch
11081 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vec1
11082 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vec2
11083 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vec3
11084 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp
11085 st->print_raw("String IndexOf char[] ");
11086 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
11087 st->print_raw(",");
11088 opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1
11089 st->print_raw(",");
11090 opnd_array(3)->ext_format(ra, this,idx3, st); // ch
11091 st->print_raw(" -> ");
11092 opnd_array(0)->int_format(ra, this, st); // result
11093 st->print_raw(" // KILL all");
11094}
11095#endif
11096#ifndef PRODUCT
11097void string_equalsNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11098 // Start at oper_input_base() and count operands
11099 unsigned idx0 = 2;
11100 unsigned idx1 = 2; // str1
11101 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2
11102 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt
11103 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
11104 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
11105 st->print_raw("String Equals ");
11106 opnd_array(1)->ext_format(ra, this,idx1, st); // str1
11107 st->print_raw(",");
11108 opnd_array(2)->ext_format(ra, this,idx2, st); // str2
11109 st->print_raw(",");
11110 opnd_array(3)->ext_format(ra, this,idx3, st); // cnt
11111 st->print_raw(" -> ");
11112 opnd_array(0)->int_format(ra, this, st); // result
11113 st->print_raw(" // KILL ");
11114 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
11115 st->print_raw(", ");
11116 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
11117 st->print_raw(", ");
11118 st->print_raw("RBX");
11119}
11120#endif
11121#ifndef PRODUCT
11122void array_equalsBNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11123 // Start at oper_input_base() and count operands
11124 unsigned idx0 = 2;
11125 unsigned idx1 = 2; // ary1
11126 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
11127 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
11128 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
11129 st->print_raw("Array Equals byte[] ");
11130 opnd_array(1)->ext_format(ra, this,idx1, st); // ary1
11131 st->print_raw(",");
11132 opnd_array(2)->ext_format(ra, this,idx2, st); // ary2
11133 st->print_raw(" -> ");
11134 opnd_array(0)->int_format(ra, this, st); // result
11135 st->print_raw(" // KILL ");
11136 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1
11137 st->print_raw(", ");
11138 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
11139 st->print_raw(", ");
11140 st->print_raw("RCX");
11141 st->print_raw(", ");
11142 st->print_raw("RBX");
11143}
11144#endif
11145#ifndef PRODUCT
11146void array_equalsCNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11147 // Start at oper_input_base() and count operands
11148 unsigned idx0 = 2;
11149 unsigned idx1 = 2; // ary1
11150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
11151 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
11152 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
11153 st->print_raw("Array Equals char[] ");
11154 opnd_array(1)->ext_format(ra, this,idx1, st); // ary1
11155 st->print_raw(",");
11156 opnd_array(2)->ext_format(ra, this,idx2, st); // ary2
11157 st->print_raw(" -> ");
11158 opnd_array(0)->int_format(ra, this, st); // result
11159 st->print_raw(" // KILL ");
11160 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1
11161 st->print_raw(", ");
11162 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
11163 st->print_raw(", ");
11164 st->print_raw("RCX");
11165 st->print_raw(", ");
11166 st->print_raw("RBX");
11167}
11168#endif
11169#ifndef PRODUCT
11170void has_negativesNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11171 // Start at oper_input_base() and count operands
11172 unsigned idx0 = 2;
11173 unsigned idx1 = 2; // ary1
11174 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len
11175 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
11176 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
11177 st->print_raw("has negatives byte[] ");
11178 opnd_array(1)->ext_format(ra, this,idx1, st); // ary1
11179 st->print_raw(",");
11180 opnd_array(2)->ext_format(ra, this,idx2, st); // len
11181 st->print_raw(" -> ");
11182 opnd_array(0)->int_format(ra, this, st); // result
11183 st->print_raw(" // KILL ");
11184 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1
11185 st->print_raw(", ");
11186 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
11187 st->print_raw(", ");
11188 st->print_raw("RBX");
11189}
11190#endif
11191#ifndef PRODUCT
11192void string_compressNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11193 // Start at oper_input_base() and count operands
11194 unsigned idx0 = 2;
11195 unsigned idx1 = 2; // src
11196 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
11197 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
11198 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
11199 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
11200 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
11201 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
11202 st->print_raw("String Compress ");
11203 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11204 st->print_raw(",");
11205 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
11206 st->print_raw(" -> ");
11207 opnd_array(0)->int_format(ra, this, st); // result
11208 st->print_raw(" // KILL RAX, RCX, RDX");
11209}
11210#endif
11211#ifndef PRODUCT
11212void string_inflateNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11213 // Start at oper_input_base() and count operands
11214 unsigned idx0 = 2;
11215 unsigned idx1 = 2; // src
11216 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
11217 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
11218 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
11219 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
11220 st->print_raw("String Inflate ");
11221 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11222 st->print_raw(",");
11223 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
11224 st->print_raw(" // KILL ");
11225 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
11226 st->print_raw(", ");
11227 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
11228}
11229#endif
11230#ifndef PRODUCT
11231void encode_iso_arrayNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11232 // Start at oper_input_base() and count operands
11233 unsigned idx0 = 2;
11234 unsigned idx1 = 2; // src
11235 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
11236 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
11237 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
11238 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
11239 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
11240 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
11241 st->print_raw("Encode array ");
11242 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11243 st->print_raw(",");
11244 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
11245 st->print_raw(",");
11246 opnd_array(3)->ext_format(ra, this,idx3, st); // len
11247 st->print_raw(" -> ");
11248 opnd_array(0)->int_format(ra, this, st); // result
11249 st->print_raw(" // KILL RCX, RDX, ");
11250 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
11251 st->print_raw(", ");
11252 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
11253 st->print_raw(", ");
11254 opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3
11255 st->print_raw(", ");
11256 opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4
11257 st->print_raw(", RSI, RDI ");
11258}
11259#endif
11260#ifndef PRODUCT
11261void overflowAddI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11262 // Start at oper_input_base() and count operands
11263 unsigned idx0 = 1;
11264 unsigned idx1 = 1; // op1
11265 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11266 st->print_raw("addl ");
11267 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11268 st->print_raw(", ");
11269 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11270 st->print_raw("\t# overflow check int");
11271}
11272#endif
11273#ifndef PRODUCT
11274void overflowAddI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11275 // Start at oper_input_base() and count operands
11276 unsigned idx0 = 1;
11277 unsigned idx1 = 1; // op1
11278 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11279 st->print_raw("addl ");
11280 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11281 st->print_raw(", ");
11282 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11283 st->print_raw("\t# overflow check int");
11284}
11285#endif
11286#ifndef PRODUCT
11287void overflowAddL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11288 // Start at oper_input_base() and count operands
11289 unsigned idx0 = 1;
11290 unsigned idx1 = 1; // op1
11291 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11292 st->print_raw("addq ");
11293 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11294 st->print_raw(", ");
11295 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11296 st->print_raw("\t# overflow check long");
11297}
11298#endif
11299#ifndef PRODUCT
11300void overflowAddL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11301 // Start at oper_input_base() and count operands
11302 unsigned idx0 = 1;
11303 unsigned idx1 = 1; // op1
11304 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11305 st->print_raw("addq ");
11306 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11307 st->print_raw(", ");
11308 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11309 st->print_raw("\t# overflow check long");
11310}
11311#endif
11312#ifndef PRODUCT
11313void overflowSubI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11314 // Start at oper_input_base() and count operands
11315 unsigned idx0 = 1;
11316 unsigned idx1 = 1; // op1
11317 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11318 st->print_raw("cmpl ");
11319 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11320 st->print_raw(", ");
11321 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11322 st->print_raw("\t# overflow check int");
11323}
11324#endif
11325#ifndef PRODUCT
11326void overflowSubI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11327 // Start at oper_input_base() and count operands
11328 unsigned idx0 = 1;
11329 unsigned idx1 = 1; // op1
11330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11331 st->print_raw("cmpl ");
11332 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11333 st->print_raw(", ");
11334 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11335 st->print_raw("\t# overflow check int");
11336}
11337#endif
11338#ifndef PRODUCT
11339void overflowSubL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11340 // Start at oper_input_base() and count operands
11341 unsigned idx0 = 1;
11342 unsigned idx1 = 1; // op1
11343 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11344 st->print_raw("cmpq ");
11345 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11346 st->print_raw(", ");
11347 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11348 st->print_raw("\t# overflow check long");
11349}
11350#endif
11351#ifndef PRODUCT
11352void overflowSubL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11353 // Start at oper_input_base() and count operands
11354 unsigned idx0 = 1;
11355 unsigned idx1 = 1; // op1
11356 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11357 st->print_raw("cmpq ");
11358 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11359 st->print_raw(", ");
11360 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11361 st->print_raw("\t# overflow check long");
11362}
11363#endif
11364#ifndef PRODUCT
11365void overflowNegI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11366 // Start at oper_input_base() and count operands
11367 unsigned idx0 = 1;
11368 unsigned idx1 = 1; // zero
11369 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11370 st->print_raw("negl ");
11371 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11372 st->print_raw("\t# overflow check int");
11373}
11374#endif
11375#ifndef PRODUCT
11376void overflowNegL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11377 // Start at oper_input_base() and count operands
11378 unsigned idx0 = 1;
11379 unsigned idx1 = 1; // zero
11380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11381 st->print_raw("negq ");
11382 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11383 st->print_raw("\t# overflow check long");
11384}
11385#endif
11386#ifndef PRODUCT
11387void overflowMulI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11388 // Start at oper_input_base() and count operands
11389 unsigned idx0 = 1;
11390 unsigned idx1 = 1; // op1
11391 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11392 st->print_raw("imull ");
11393 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11394 st->print_raw(", ");
11395 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11396 st->print_raw("\t# overflow check int");
11397}
11398#endif
11399#ifndef PRODUCT
11400void overflowMulI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11401 // Start at oper_input_base() and count operands
11402 unsigned idx0 = 1;
11403 unsigned idx1 = 1; // op1
11404 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11405 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
11406 st->print_raw("imull ");
11407 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
11408 st->print_raw(", ");
11409 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11410 st->print_raw(", ");
11411 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11412 st->print_raw("\t# overflow check int");
11413}
11414#endif
11415#ifndef PRODUCT
11416void overflowMulL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11417 // Start at oper_input_base() and count operands
11418 unsigned idx0 = 1;
11419 unsigned idx1 = 1; // op1
11420 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11421 st->print_raw("imulq ");
11422 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11423 st->print_raw(", ");
11424 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11425 st->print_raw("\t# overflow check long");
11426}
11427#endif
11428#ifndef PRODUCT
11429void overflowMulL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11430 // Start at oper_input_base() and count operands
11431 unsigned idx0 = 1;
11432 unsigned idx1 = 1; // op1
11433 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11434 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
11435 st->print_raw("imulq ");
11436 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
11437 st->print_raw(", ");
11438 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11439 st->print_raw(", ");
11440 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11441 st->print_raw("\t# overflow check long");
11442}
11443#endif
11444#ifndef PRODUCT
11445void compI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11446 // Start at oper_input_base() and count operands
11447 unsigned idx0 = 1;
11448 unsigned idx1 = 1; // op1
11449 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11450 st->print_raw("cmpl ");
11451 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11452 st->print_raw(", ");
11453 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11454}
11455#endif
11456#ifndef PRODUCT
11457void compI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11458 // Start at oper_input_base() and count operands
11459 unsigned idx0 = 1;
11460 unsigned idx1 = 1; // op1
11461 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11462 st->print_raw("cmpl ");
11463 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11464 st->print_raw(", ");
11465 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11466}
11467#endif
11468#ifndef PRODUCT
11469void compI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11470 // Start at oper_input_base() and count operands
11471 unsigned idx0 = 2;
11472 unsigned idx1 = 2; // op1
11473 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11474 st->print_raw("cmpl ");
11475 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11476 st->print_raw(", ");
11477 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11478}
11479#endif
11480#ifndef PRODUCT
11481void testI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11482 // Start at oper_input_base() and count operands
11483 unsigned idx0 = 1;
11484 unsigned idx1 = 1; // src
11485 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11486 st->print_raw("testl ");
11487 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11488 st->print_raw(", ");
11489 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11490}
11491#endif
11492#ifndef PRODUCT
11493void testI_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11494 // Start at oper_input_base() and count operands
11495 unsigned idx0 = 1;
11496 unsigned idx1 = 1; // src
11497 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
11498 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11499 st->print_raw("testl ");
11500 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11501 st->print_raw(", ");
11502 opnd_array(2)->ext_format(ra, this,idx2, st); // con
11503}
11504#endif
11505#ifndef PRODUCT
11506void testI_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11507 // Start at oper_input_base() and count operands
11508 unsigned idx0 = 2;
11509 unsigned idx1 = 2; // src
11510 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11511 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11512 st->print_raw("testl ");
11513 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11514 st->print_raw(", ");
11515 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11516}
11517#endif
11518#ifndef PRODUCT
11519void testI_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11520 // Start at oper_input_base() and count operands
11521 unsigned idx0 = 2;
11522 unsigned idx1 = 2; // mem
11523 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
11524 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11525 st->print_raw("testl ");
11526 opnd_array(2)->ext_format(ra, this,idx2, st); // src
11527 st->print_raw(", ");
11528 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11529}
11530#endif
11531#ifndef PRODUCT
11532void compU_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11533 // Start at oper_input_base() and count operands
11534 unsigned idx0 = 1;
11535 unsigned idx1 = 1; // op1
11536 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11537 st->print_raw("cmpl ");
11538 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11539 st->print_raw(", ");
11540 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11541 st->print_raw("\t# unsigned");
11542}
11543#endif
11544#ifndef PRODUCT
11545void compU_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11546 // Start at oper_input_base() and count operands
11547 unsigned idx0 = 1;
11548 unsigned idx1 = 1; // op1
11549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11550 st->print_raw("cmpl ");
11551 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11552 st->print_raw(", ");
11553 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11554 st->print_raw("\t# unsigned");
11555}
11556#endif
11557#ifndef PRODUCT
11558void compU_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11559 // Start at oper_input_base() and count operands
11560 unsigned idx0 = 2;
11561 unsigned idx1 = 2; // op1
11562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11563 st->print_raw("cmpl ");
11564 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11565 st->print_raw(", ");
11566 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11567 st->print_raw("\t# unsigned");
11568}
11569#endif
11570#ifndef PRODUCT
11571void testU_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11572 // Start at oper_input_base() and count operands
11573 unsigned idx0 = 1;
11574 unsigned idx1 = 1; // src
11575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11576 st->print_raw("testl ");
11577 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11578 st->print_raw(", ");
11579 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11580 st->print_raw("\t# unsigned");
11581}
11582#endif
11583#ifndef PRODUCT
11584void compP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11585 // Start at oper_input_base() and count operands
11586 unsigned idx0 = 1;
11587 unsigned idx1 = 1; // op1
11588 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11589 st->print_raw("cmpq ");
11590 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11591 st->print_raw(", ");
11592 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11593 st->print_raw("\t# ptr");
11594}
11595#endif
11596#ifndef PRODUCT
11597void compP_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11598 // Start at oper_input_base() and count operands
11599 unsigned idx0 = 2;
11600 unsigned idx1 = 2; // op1
11601 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11602 st->print_raw("cmpq ");
11603 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11604 st->print_raw(", ");
11605 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11606 st->print_raw("\t# ptr");
11607}
11608#endif
11609#ifndef PRODUCT
11610void compP_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11611 // Start at oper_input_base() and count operands
11612 unsigned idx0 = 2;
11613 unsigned idx1 = 2; // op1
11614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11615 st->print_raw("cmpq ");
11616 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11617 st->print_raw(", ");
11618 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11619 st->print_raw("\t# raw ptr");
11620}
11621#endif
11622#ifndef PRODUCT
11623void testP_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11624 // Start at oper_input_base() and count operands
11625 unsigned idx0 = 1;
11626 unsigned idx1 = 1; // src
11627 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11628 st->print_raw("testq ");
11629 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11630 st->print_raw(", ");
11631 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11632 st->print_raw("\t# ptr");
11633}
11634#endif
11635#ifndef PRODUCT
11636void testP_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11637 // Start at oper_input_base() and count operands
11638 unsigned idx0 = 2;
11639 unsigned idx1 = 2; // op
11640 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11641 st->print_raw("testq ");
11642 opnd_array(1)->ext_format(ra, this,idx1, st); // op
11643 st->print_raw(", 0xffffffffffffffff\t# ptr");
11644}
11645#endif
11646#ifndef PRODUCT
11647void testP_mem_reg0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11648 // Start at oper_input_base() and count operands
11649 unsigned idx0 = 2;
11650 unsigned idx1 = 2; // mem
11651 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11652 st->print_raw("cmpq R12, ");
11653 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11654 st->print_raw("\t# ptr (R12_heapbase==0)");
11655}
11656#endif
11657#ifndef PRODUCT
11658void compN_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11659 // Start at oper_input_base() and count operands
11660 unsigned idx0 = 1;
11661 unsigned idx1 = 1; // op1
11662 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11663 st->print_raw("cmpl ");
11664 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11665 st->print_raw(", ");
11666 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11667 st->print_raw("\t# compressed ptr");
11668}
11669#endif
11670#ifndef PRODUCT
11671void compN_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11672 // Start at oper_input_base() and count operands
11673 unsigned idx0 = 2;
11674 unsigned idx1 = 2; // src
11675 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11676 st->print_raw("cmpl ");
11677 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11678 st->print_raw(", ");
11679 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11680 st->print_raw("\t# compressed ptr");
11681}
11682#endif
11683#ifndef PRODUCT
11684void compN_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11685 // Start at oper_input_base() and count operands
11686 unsigned idx0 = 1;
11687 unsigned idx1 = 1; // op1
11688 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11689 st->print_raw("cmpl ");
11690 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11691 st->print_raw(", ");
11692 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11693 st->print_raw("\t# compressed ptr");
11694}
11695#endif
11696#ifndef PRODUCT
11697void compN_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11698 // Start at oper_input_base() and count operands
11699 unsigned idx0 = 2;
11700 unsigned idx1 = 2; // src
11701 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11702 st->print_raw("cmpl ");
11703 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11704 st->print_raw(", ");
11705 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11706 st->print_raw("\t# compressed ptr");
11707}
11708#endif
11709#ifndef PRODUCT
11710void compN_rReg_imm_klassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11711 // Start at oper_input_base() and count operands
11712 unsigned idx0 = 1;
11713 unsigned idx1 = 1; // op1
11714 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11715 st->print_raw("cmpl ");
11716 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11717 st->print_raw(", ");
11718 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11719 st->print_raw("\t# compressed klass ptr");
11720}
11721#endif
11722#ifndef PRODUCT
11723void compN_mem_imm_klassNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11724 // Start at oper_input_base() and count operands
11725 unsigned idx0 = 2;
11726 unsigned idx1 = 2; // src
11727 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11728 st->print_raw("cmpl ");
11729 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11730 st->print_raw(", ");
11731 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11732 st->print_raw("\t# compressed klass ptr");
11733}
11734#endif
11735#ifndef PRODUCT
11736void testN_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11737 // Start at oper_input_base() and count operands
11738 unsigned idx0 = 1;
11739 unsigned idx1 = 1; // src
11740 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11741 st->print_raw("testl ");
11742 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11743 st->print_raw(", ");
11744 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11745 st->print_raw("\t# compressed ptr");
11746}
11747#endif
11748#ifndef PRODUCT
11749void testN_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11750 // Start at oper_input_base() and count operands
11751 unsigned idx0 = 2;
11752 unsigned idx1 = 2; // mem
11753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11754 st->print_raw("testl ");
11755 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11756 st->print_raw(", 0xffffffff\t# compressed ptr");
11757}
11758#endif
11759#ifndef PRODUCT
11760void testN_mem_reg0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11761 // Start at oper_input_base() and count operands
11762 unsigned idx0 = 2;
11763 unsigned idx1 = 2; // mem
11764 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11765 st->print_raw("cmpl R12, ");
11766 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11767 st->print_raw("\t# compressed ptr (R12_heapbase==0)");
11768}
11769#endif
11770#ifndef PRODUCT
11771void compL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11772 // Start at oper_input_base() and count operands
11773 unsigned idx0 = 1;
11774 unsigned idx1 = 1; // op1
11775 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11776 st->print_raw("cmpq ");
11777 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11778 st->print_raw(", ");
11779 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11780}
11781#endif
11782#ifndef PRODUCT
11783void compL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11784 // Start at oper_input_base() and count operands
11785 unsigned idx0 = 1;
11786 unsigned idx1 = 1; // op1
11787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11788 st->print_raw("cmpq ");
11789 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11790 st->print_raw(", ");
11791 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11792}
11793#endif
11794#ifndef PRODUCT
11795void compL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11796 // Start at oper_input_base() and count operands
11797 unsigned idx0 = 2;
11798 unsigned idx1 = 2; // op1
11799 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11800 st->print_raw("cmpq ");
11801 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11802 st->print_raw(", ");
11803 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11804}
11805#endif
11806#ifndef PRODUCT
11807void testL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11808 // Start at oper_input_base() and count operands
11809 unsigned idx0 = 1;
11810 unsigned idx1 = 1; // src
11811 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11812 st->print_raw("testq ");
11813 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11814 st->print_raw(", ");
11815 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11816}
11817#endif
11818#ifndef PRODUCT
11819void testL_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11820 // Start at oper_input_base() and count operands
11821 unsigned idx0 = 1;
11822 unsigned idx1 = 1; // src
11823 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
11824 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11825 st->print_raw("testq ");
11826 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11827 st->print_raw(", ");
11828 opnd_array(2)->ext_format(ra, this,idx2, st); // con
11829 st->print_raw("\t# long");
11830}
11831#endif
11832#ifndef PRODUCT
11833void testL_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11834 // Start at oper_input_base() and count operands
11835 unsigned idx0 = 2;
11836 unsigned idx1 = 2; // src
11837 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11838 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11839 st->print_raw("testq ");
11840 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11841 st->print_raw(", ");
11842 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11843}
11844#endif
11845#ifndef PRODUCT
11846void testL_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11847 // Start at oper_input_base() and count operands
11848 unsigned idx0 = 2;
11849 unsigned idx1 = 2; // mem
11850 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
11851 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11852 st->print_raw("testq ");
11853 opnd_array(2)->ext_format(ra, this,idx2, st); // src
11854 st->print_raw(", ");
11855 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11856}
11857#endif
11858#ifndef PRODUCT
11859void testL_reg_mem2Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11860 // Start at oper_input_base() and count operands
11861 unsigned idx0 = 2;
11862 unsigned idx1 = 2; // src
11863 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
11864 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11865 st->print_raw("testq ");
11866 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11867 st->print_raw(", ");
11868 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
11869}
11870#endif
11871#ifndef PRODUCT
11872void testL_reg_mem2_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
11873 // Start at oper_input_base() and count operands
11874 unsigned idx0 = 2;
11875 unsigned idx1 = 2; // mem
11876 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
11877 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11878 st->print_raw("testq ");
11879 opnd_array(2)->ext_format(ra, this,idx2, st); // src
11880 st->print_raw(", ");
11881 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11882}
11883#endif
11884#ifndef PRODUCT
11885void cmpL3_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11886 // Start at oper_input_base() and count operands
11887 unsigned idx0 = 1;
11888 unsigned idx1 = 1; // src1
11889 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
11890 st->print_raw("cmpq ");
11891 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
11892 st->print_raw(", ");
11893 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
11894 st->print_raw("\t# CmpL3\n\t");
11895 st->print_raw("movl ");
11896 opnd_array(0)->int_format(ra, this, st); // dst
11897 st->print_raw(", -1\n\t");
11898 st->print_raw("jl,s done\n\t");
11899 st->print_raw("setne ");
11900 opnd_array(0)->int_format(ra, this, st); // dst
11901 st->print_raw("\n\t");
11902 st->print_raw("movzbl ");
11903 opnd_array(0)->int_format(ra, this, st); // dst
11904 st->print_raw(", ");
11905 opnd_array(0)->int_format(ra, this, st); // dst
11906 st->print_raw("\n\t");
11907 st->print_raw("done:");
11908}
11909#endif
11910#ifndef PRODUCT
11911void compUL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11912 // Start at oper_input_base() and count operands
11913 unsigned idx0 = 1;
11914 unsigned idx1 = 1; // op1
11915 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11916 st->print_raw("cmpq ");
11917 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11918 st->print_raw(", ");
11919 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11920 st->print_raw("\t# unsigned");
11921}
11922#endif
11923#ifndef PRODUCT
11924void compUL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11925 // Start at oper_input_base() and count operands
11926 unsigned idx0 = 1;
11927 unsigned idx1 = 1; // op1
11928 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11929 st->print_raw("cmpq ");
11930 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11931 st->print_raw(", ");
11932 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11933 st->print_raw("\t# unsigned");
11934}
11935#endif
11936#ifndef PRODUCT
11937void compUL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11938 // Start at oper_input_base() and count operands
11939 unsigned idx0 = 2;
11940 unsigned idx1 = 2; // op1
11941 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
11942 st->print_raw("cmpq ");
11943 opnd_array(1)->ext_format(ra, this,idx1, st); // op1
11944 st->print_raw(", ");
11945 opnd_array(2)->ext_format(ra, this,idx2, st); // op2
11946 st->print_raw("\t# unsigned");
11947}
11948#endif
11949#ifndef PRODUCT
11950void testUL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11951 // Start at oper_input_base() and count operands
11952 unsigned idx0 = 1;
11953 unsigned idx1 = 1; // src
11954 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
11955 st->print_raw("testq ");
11956 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11957 st->print_raw(", ");
11958 opnd_array(1)->ext_format(ra, this,idx1, st); // src
11959 st->print_raw("\t# unsigned");
11960}
11961#endif
11962#ifndef PRODUCT
11963void compB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11964 // Start at oper_input_base() and count operands
11965 unsigned idx0 = 2;
11966 unsigned idx1 = 2; // mem
11967 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
11968 st->print_raw("cmpb ");
11969 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11970 st->print_raw(", ");
11971 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
11972}
11973#endif
11974#ifndef PRODUCT
11975void testUB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11976 // Start at oper_input_base() and count operands
11977 unsigned idx0 = 2;
11978 unsigned idx1 = 2; // mem
11979 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
11980 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11981 st->print_raw("testb ");
11982 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11983 st->print_raw(", ");
11984 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
11985 st->print_raw("\t# ubyte");
11986}
11987#endif
11988#ifndef PRODUCT
11989void testB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
11990 // Start at oper_input_base() and count operands
11991 unsigned idx0 = 2;
11992 unsigned idx1 = 2; // mem
11993 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
11994 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
11995 st->print_raw("testb ");
11996 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
11997 st->print_raw(", ");
11998 opnd_array(2)->ext_format(ra, this,idx2, st); // imm
11999 st->print_raw("\t# byte");
12000}
12001#endif
12002#ifndef PRODUCT
12003void cmovI_reg_gNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12004 // Start at oper_input_base() and count operands
12005 unsigned idx0 = 1;
12006 unsigned idx1 = 1; // src
12007 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
12008 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12009 st->print_raw("cmovlgt ");
12010 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12011 st->print_raw(", ");
12012 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12013 st->print_raw("\t# min");
12014}
12015#endif
12016#ifndef PRODUCT
12017void minI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12018}
12019#endif
12020#ifndef PRODUCT
12021void cmovI_reg_lNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12022 // Start at oper_input_base() and count operands
12023 unsigned idx0 = 1;
12024 unsigned idx1 = 1; // src
12025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
12026 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12027 st->print_raw("cmovllt ");
12028 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12029 st->print_raw(", ");
12030 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12031 st->print_raw("\t# max");
12032}
12033#endif
12034#ifndef PRODUCT
12035void maxI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12036}
12037#endif
12038#ifndef PRODUCT
12039void jmpDirNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12040 // Start at oper_input_base() and count operands
12041 unsigned idx0 = 1;
12042 unsigned idx1 = 1; //
12043 st->print_raw("jmp ");
12044 opnd_array(1)->ext_format(ra, this,idx1, st); // labl
12045}
12046#endif
12047#ifndef PRODUCT
12048void jmpConNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12049 // Start at oper_input_base() and count operands
12050 unsigned idx0 = 1;
12051 unsigned idx1 = 1; // cr
12052 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12053 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12054 st->print_raw("j");
12055 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12056 st->print_raw(" ");
12057 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12058 st->print(" P=%f C=%f",_prob,_fcnt);
12059}
12060#endif
12061#ifndef PRODUCT
12062void jmpLoopEndNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12063 // Start at oper_input_base() and count operands
12064 unsigned idx0 = 1;
12065 unsigned idx1 = 1; // cr
12066 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12067 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12068 st->print_raw("j");
12069 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12070 st->print_raw(" ");
12071 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12072 st->print_raw("\t# loop end");
12073 st->print(" P=%f C=%f",_prob,_fcnt);
12074}
12075#endif
12076#ifndef PRODUCT
12077void jmpLoopEndUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12078 // Start at oper_input_base() and count operands
12079 unsigned idx0 = 1;
12080 unsigned idx1 = 1; // cmp
12081 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12082 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12083 st->print_raw("j");
12084 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12085 st->print_raw(",u ");
12086 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12087 st->print_raw("\t# loop end");
12088 st->print(" P=%f C=%f",_prob,_fcnt);
12089}
12090#endif
12091#ifndef PRODUCT
12092void jmpLoopEndUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12093 // Start at oper_input_base() and count operands
12094 unsigned idx0 = 1;
12095 unsigned idx1 = 1; // cmp
12096 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12097 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12098 st->print_raw("j");
12099 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12100 st->print_raw(",u ");
12101 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12102 st->print_raw("\t# loop end");
12103 st->print(" P=%f C=%f",_prob,_fcnt);
12104}
12105#endif
12106#ifndef PRODUCT
12107void jmpLoopEnd_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12108 // Start at oper_input_base() and count operands
12109 unsigned idx0 = 1;
12110 unsigned idx1 = 1; // cr
12111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12112 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12113 st->print_raw("j");
12114 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12115 st->print_raw(" ");
12116 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12117 st->print_raw("\t# loop end\n\t");
12118 st->print_raw("restorevectmask \t# vector mask restore for loops");
12119 st->print(" P=%f C=%f",_prob,_fcnt);
12120}
12121#endif
12122#ifndef PRODUCT
12123void jmpLoopEndU_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12124 // Start at oper_input_base() and count operands
12125 unsigned idx0 = 1;
12126 unsigned idx1 = 1; // cmp
12127 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12128 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12129 st->print_raw("j");
12130 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12131 st->print_raw(",u ");
12132 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12133 st->print_raw("\t# loop end\n\t");
12134 st->print_raw("restorevectmask \t# vector mask restore for loops");
12135 st->print(" P=%f C=%f",_prob,_fcnt);
12136}
12137#endif
12138#ifndef PRODUCT
12139void jmpLoopEndUCF_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12140 // Start at oper_input_base() and count operands
12141 unsigned idx0 = 1;
12142 unsigned idx1 = 1; // cmp
12143 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12144 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12145 st->print_raw("j");
12146 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12147 st->print_raw(",u ");
12148 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12149 st->print_raw("\t# loop end\n\t");
12150 st->print_raw("restorevectmask \t# vector mask restore for loops");
12151 st->print(" P=%f C=%f",_prob,_fcnt);
12152}
12153#endif
12154#ifndef PRODUCT
12155void jmpConUNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12156 // Start at oper_input_base() and count operands
12157 unsigned idx0 = 1;
12158 unsigned idx1 = 1; // cmp
12159 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12160 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12161 st->print_raw("j");
12162 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12163 st->print_raw(",u ");
12164 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12165 st->print(" P=%f C=%f",_prob,_fcnt);
12166}
12167#endif
12168#ifndef PRODUCT
12169void jmpConUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12170 // Start at oper_input_base() and count operands
12171 unsigned idx0 = 1;
12172 unsigned idx1 = 1; // cmp
12173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12174 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12175 st->print_raw("j");
12176 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12177 st->print_raw(",u ");
12178 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12179 st->print(" P=%f C=%f",_prob,_fcnt);
12180}
12181#endif
12182#ifndef PRODUCT
12183void jmpConUCF2Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12184 // Start at oper_input_base() and count operands
12185 unsigned idx0 = 1;
12186 unsigned idx1 = 1; // cmp
12187 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12188 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12189 if ( opnd_array(1)->ccode() == Assembler::notEqual) {
12190 st->print_raw("jp,u ");
12191 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12192 st->print_raw("\n\t");
12193 st->print_raw("j");
12194 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12195 st->print_raw(",u ");
12196 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12197 } else {
12198 st->print_raw("jp,u done\n\t");
12199 st->print_raw("j");
12200 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12201 st->print_raw(",u ");
12202 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12203 st->print_raw("\n\t");
12204 st->print_raw("done:");
12205 }
12206 st->print(" P=%f C=%f",_prob,_fcnt);
12207}
12208#endif
12209#ifndef PRODUCT
12210void partialSubtypeCheckNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12211 // Start at oper_input_base() and count operands
12212 unsigned idx0 = 1;
12213 unsigned idx1 = 1; // sub
12214 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
12215 st->print_raw("movq rdi, [");
12216 opnd_array(1)->ext_format(ra, this,idx1, st); // sub
12217 st->print_raw(" + in_bytes(Klass::secondary_supers_offset())]\n\t");
12218 st->print_raw("movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t");
12219 st->print_raw("addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t");
12220 st->print_raw("repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t");
12221 st->print_raw("jne,s miss\t\t# Missed: rdi not-zero\n\t");
12222 st->print_raw("movq [");
12223 opnd_array(1)->ext_format(ra, this,idx1, st); // sub
12224 st->print_raw(" + in_bytes(Klass::secondary_super_cache_offset())], ");
12225 opnd_array(2)->ext_format(ra, this,idx2, st); // super
12226 st->print_raw("\t# Hit: update cache\n\t");
12227 st->print_raw("xorq ");
12228 opnd_array(0)->int_format(ra, this, st); // result
12229 st->print_raw(", ");
12230 opnd_array(0)->int_format(ra, this, st); // result
12231 st->print_raw("\t\t Hit: rdi zero\n\t");
12232 st->print_raw("miss:\t");
12233}
12234#endif
12235#ifndef PRODUCT
12236void partialSubtypeCheck_vs_ZeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12237 // Start at oper_input_base() and count operands
12238 unsigned idx0 = 1;
12239 unsigned idx1 = 1; // sub
12240 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
12241 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
12242 st->print_raw("movq rdi, [");
12243 opnd_array(1)->ext_format(ra, this,idx1, st); // sub
12244 st->print_raw(" + in_bytes(Klass::secondary_supers_offset())]\n\t");
12245 st->print_raw("movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t");
12246 st->print_raw("addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t");
12247 st->print_raw("repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t");
12248 st->print_raw("jne,s miss\t\t# Missed: flags nz\n\t");
12249 st->print_raw("movq [");
12250 opnd_array(1)->ext_format(ra, this,idx1, st); // sub
12251 st->print_raw(" + in_bytes(Klass::secondary_super_cache_offset())], ");
12252 opnd_array(2)->ext_format(ra, this,idx2, st); // super
12253 st->print_raw("\t# Hit: update cache\n\t");
12254 st->print_raw("miss:\t");
12255}
12256#endif
12257#ifndef PRODUCT
12258void jmpDir_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12259 // Start at oper_input_base() and count operands
12260 unsigned idx0 = 1;
12261 unsigned idx1 = 1; //
12262 st->print_raw("jmp,s ");
12263 opnd_array(1)->ext_format(ra, this,idx1, st); // labl
12264}
12265#endif
12266#ifndef PRODUCT
12267void jmpCon_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12268 // Start at oper_input_base() and count operands
12269 unsigned idx0 = 1;
12270 unsigned idx1 = 1; // cr
12271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12272 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12273 st->print_raw("j");
12274 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12275 st->print_raw(",s ");
12276 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12277 st->print(" P=%f C=%f",_prob,_fcnt);
12278}
12279#endif
12280#ifndef PRODUCT
12281void jmpLoopEnd_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12282 // Start at oper_input_base() and count operands
12283 unsigned idx0 = 1;
12284 unsigned idx1 = 1; // cr
12285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12286 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12287 st->print_raw("j");
12288 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12289 st->print_raw(",s ");
12290 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12291 st->print_raw("\t# loop end");
12292 st->print(" P=%f C=%f",_prob,_fcnt);
12293}
12294#endif
12295#ifndef PRODUCT
12296void jmpLoopEndU_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12297 // Start at oper_input_base() and count operands
12298 unsigned idx0 = 1;
12299 unsigned idx1 = 1; // cmp
12300 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12301 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12302 st->print_raw("j");
12303 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12304 st->print_raw(",us ");
12305 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12306 st->print_raw("\t# loop end");
12307 st->print(" P=%f C=%f",_prob,_fcnt);
12308}
12309#endif
12310#ifndef PRODUCT
12311void jmpLoopEndUCF_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12312 // Start at oper_input_base() and count operands
12313 unsigned idx0 = 1;
12314 unsigned idx1 = 1; // cmp
12315 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12316 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12317 st->print_raw("j");
12318 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12319 st->print_raw(",us ");
12320 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12321 st->print_raw("\t# loop end");
12322 st->print(" P=%f C=%f",_prob,_fcnt);
12323}
12324#endif
12325#ifndef PRODUCT
12326void jmpConU_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12327 // Start at oper_input_base() and count operands
12328 unsigned idx0 = 1;
12329 unsigned idx1 = 1; // cmp
12330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12331 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12332 st->print_raw("j");
12333 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12334 st->print_raw(",us ");
12335 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12336 st->print(" P=%f C=%f",_prob,_fcnt);
12337}
12338#endif
12339#ifndef PRODUCT
12340void jmpConUCF_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12341 // Start at oper_input_base() and count operands
12342 unsigned idx0 = 1;
12343 unsigned idx1 = 1; // cmp
12344 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12345 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12346 st->print_raw("j");
12347 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12348 st->print_raw(",us ");
12349 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12350 st->print(" P=%f C=%f",_prob,_fcnt);
12351}
12352#endif
12353#ifndef PRODUCT
12354void jmpConUCF2_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12355 // Start at oper_input_base() and count operands
12356 unsigned idx0 = 1;
12357 unsigned idx1 = 1; // cmp
12358 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
12359 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
12360 if ( opnd_array(1)->ccode() == Assembler::notEqual) {
12361 st->print_raw("jp,u,s ");
12362 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12363 st->print_raw("\n\t");
12364 st->print_raw("j");
12365 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12366 st->print_raw(",u,s ");
12367 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12368 } else {
12369 st->print_raw("jp,u,s done\n\t");
12370 st->print_raw("j");
12371 opnd_array(1)->ext_format(ra, this,idx1, st); // cop
12372 st->print_raw(",u,s ");
12373 opnd_array(3)->ext_format(ra, this,idx3, st); // labl
12374 st->print_raw("\n\t");
12375 st->print_raw("done:");
12376 }
12377 st->print(" P=%f C=%f",_prob,_fcnt);
12378}
12379#endif
12380#ifndef PRODUCT
12381void cmpFastLockRTMNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12382 // Start at oper_input_base() and count operands
12383 unsigned idx0 = 1;
12384 unsigned idx1 = 1; // object
12385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
12386 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
12387 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
12388 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1
12389 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // cx2
12390 st->print_raw("fastlock ");
12391 opnd_array(1)->ext_format(ra, this,idx1, st); // object
12392 st->print_raw(",");
12393 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12394 st->print_raw("\t! kills ");
12395 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12396 st->print_raw(",");
12397 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
12398 st->print_raw(",");
12399 opnd_array(4)->ext_format(ra, this,idx4, st); // scr
12400 st->print_raw(",");
12401 opnd_array(5)->ext_format(ra, this,idx5, st); // cx1
12402 st->print_raw(",");
12403 opnd_array(6)->ext_format(ra, this,idx6, st); // cx2
12404}
12405#endif
12406#ifndef PRODUCT
12407void cmpFastLockNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12408 // Start at oper_input_base() and count operands
12409 unsigned idx0 = 1;
12410 unsigned idx1 = 1; // object
12411 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
12412 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
12413 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
12414 st->print_raw("fastlock ");
12415 opnd_array(1)->ext_format(ra, this,idx1, st); // object
12416 st->print_raw(",");
12417 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12418 st->print_raw("\t! kills ");
12419 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12420 st->print_raw(",");
12421 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
12422 st->print_raw(",");
12423 opnd_array(4)->ext_format(ra, this,idx4, st); // scr
12424}
12425#endif
12426#ifndef PRODUCT
12427void cmpFastUnlockNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12428 // Start at oper_input_base() and count operands
12429 unsigned idx0 = 1;
12430 unsigned idx1 = 1; // object
12431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
12432 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
12433 st->print_raw("fastunlock ");
12434 opnd_array(1)->ext_format(ra, this,idx1, st); // object
12435 st->print_raw(",");
12436 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12437 st->print_raw("\t! kills ");
12438 opnd_array(2)->ext_format(ra, this,idx2, st); // box
12439 st->print_raw(",");
12440 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
12441}
12442#endif
12443#ifndef PRODUCT
12444void safePoint_pollNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12445 st->print_raw("testl rax, [rip + #offset_to_poll_page]\t");
12446 st->print_raw("# Safepoint: poll for GC");
12447 st->print_raw("");
12448 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12449 st->print(" # ");
12450 if( _jvms && _oop_map ) _oop_map->print_on(st);
12451}
12452#endif
12453#ifndef PRODUCT
12454void safePoint_poll_farNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12455 // Start at oper_input_base() and count operands
12456 unsigned idx0 = 5;
12457 unsigned idx1 = 5; // cr
12458 st->print_raw("testl rax, [");
12459 opnd_array(1)->ext_format(ra, this,idx1, st); // poll
12460 st->print_raw("]\t");
12461 st->print_raw("# Safepoint: poll for GC");
12462 st->print_raw("");
12463 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12464 st->print(" # ");
12465 if( _jvms && _oop_map ) _oop_map->print_on(st);
12466}
12467#endif
12468#ifndef PRODUCT
12469void safePoint_poll_tlsNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12470 // Start at oper_input_base() and count operands
12471 unsigned idx0 = 5;
12472 unsigned idx1 = 5; // cr
12473 st->print_raw("testl rax, [");
12474 opnd_array(1)->ext_format(ra, this,idx1, st); // poll
12475 st->print_raw("]\t");
12476 st->print_raw("# Safepoint: poll for GC");
12477 st->print_raw("");
12478 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12479 st->print(" # ");
12480 if( _jvms && _oop_map ) _oop_map->print_on(st);
12481}
12482#endif
12483#ifndef PRODUCT
12484void CallStaticJavaDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12485 st->print_raw("call,static ");
12486 if( _method ) _method->print_short_name(st);
12487 else st->print(" wrapper for: %s", _name);
12488 if( !_method ) dump_trap_args(st);
12489 st->cr();
12490 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12491 st->print(" # ");
12492 if( _jvms && _oop_map ) _oop_map->print_on(st);
12493}
12494#endif
12495#ifndef PRODUCT
12496void CallDynamicJavaDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12497 st->print_raw("movq rax, #Universe::non_oop_word()\n\t");
12498 st->print_raw("call,dynamic ");
12499 _method->print_short_name(st);
12500 st->cr();
12501 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12502 st->print(" # ");
12503 if( _jvms && _oop_map ) _oop_map->print_on(st);
12504}
12505#endif
12506#ifndef PRODUCT
12507void CallRuntimeDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12508 st->print_raw("call,runtime ");
12509 st->print(" %s", _name); st->cr();
12510 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12511 st->print(" # ");
12512 if( _jvms && _oop_map ) _oop_map->print_on(st);
12513}
12514#endif
12515#ifndef PRODUCT
12516void CallLeafDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12517 st->print_raw("call_leaf,runtime ");
12518 st->print(" %s", _name); st->cr();
12519 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12520 st->print(" # ");
12521 if( _jvms && _oop_map ) _oop_map->print_on(st);
12522}
12523#endif
12524#ifndef PRODUCT
12525void CallLeafNoFPDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12526 st->print_raw("call_leaf_nofp,runtime ");
12527 st->print(" %s", _name); st->cr();
12528 if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info");
12529 st->print(" # ");
12530 if( _jvms && _oop_map ) _oop_map->print_on(st);
12531}
12532#endif
12533#ifndef PRODUCT
12534void RetNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12535 st->print_raw("ret");
12536}
12537#endif
12538#ifndef PRODUCT
12539void TailCalljmpIndNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12540 // Start at oper_input_base() and count operands
12541 unsigned idx0 = 5;
12542 unsigned idx1 = 5; // method_oop
12543 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
12544 st->print_raw("jmp ");
12545 opnd_array(1)->ext_format(ra, this,idx1, st); // jump_target
12546 st->print_raw("\t# rbx holds method oop");
12547}
12548#endif
12549#ifndef PRODUCT
12550void tailjmpIndNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12551 // Start at oper_input_base() and count operands
12552 unsigned idx0 = 5;
12553 unsigned idx1 = 5; // ex_oop
12554 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
12555 st->print_raw("popq rdx\t# pop return address\n\t");
12556 st->print_raw("jmp ");
12557 opnd_array(1)->ext_format(ra, this,idx1, st); // jump_target
12558}
12559#endif
12560#ifndef PRODUCT
12561void CreateExceptionNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12562 st->print_raw("# exception oop is in rax; no code emitted");
12563}
12564#endif
12565#ifndef PRODUCT
12566void RethrowExceptionNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12567 st->print_raw("jmp rethrow_stub");
12568}
12569#endif
12570#ifndef PRODUCT
12571void tlsLoadPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12572 st->print_raw("# TLS is in R15");
12573}
12574#endif
12575#ifndef PRODUCT
12576void ShouldNotReachHereNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12577 st->print_raw("ud2\t# ShouldNotReachHere");
12578}
12579#endif
12580#ifndef PRODUCT
12581void setMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12582 // Start at oper_input_base() and count operands
12583 unsigned idx0 = 1;
12584 unsigned idx1 = 1; // src
12585 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
12586 st->print_raw("setvectmask ");
12587 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
12588 st->print_raw(", ");
12589 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12590}
12591#endif
12592#ifndef PRODUCT
12593void addF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12594 // Start at oper_input_base() and count operands
12595 unsigned idx0 = 1;
12596 unsigned idx1 = 1; // dst
12597 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12598 st->print_raw("addss ");
12599 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12600 st->print_raw(", ");
12601 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12602}
12603#endif
12604#ifndef PRODUCT
12605void addF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12606 // Start at oper_input_base() and count operands
12607 unsigned idx0 = 2;
12608 unsigned idx1 = 2; // dst
12609 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12610 st->print_raw("addss ");
12611 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12612 st->print_raw(", ");
12613 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12614}
12615#endif
12616#ifndef PRODUCT
12617void addF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12618 // Start at oper_input_base() and count operands
12619 unsigned idx0 = 2;
12620 unsigned idx1 = 2; // src
12621 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
12622 st->print_raw("addss ");
12623 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
12624 st->print_raw(", ");
12625 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12626}
12627#endif
12628#ifndef PRODUCT
12629void addF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12630 // Start at oper_input_base() and count operands
12631 unsigned idx0 = 1;
12632 unsigned idx1 = 1; // dst
12633 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12634 st->print_raw("addss ");
12635 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12636 st->print_raw(", [");
12637 st->print("constant table base + #%d", constant_offset_unchecked());
12638 st->print_raw("]\t# load from constant table: float=");
12639 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12640}
12641#endif
12642#ifndef PRODUCT
12643void addF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12644 // Start at oper_input_base() and count operands
12645 unsigned idx0 = 1;
12646 unsigned idx1 = 1; // src1
12647 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12648 st->print_raw("vaddss ");
12649 opnd_array(0)->int_format(ra, this, st); // dst
12650 st->print_raw(", ");
12651 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12652 st->print_raw(", ");
12653 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12654}
12655#endif
12656#ifndef PRODUCT
12657void addF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12658 // Start at oper_input_base() and count operands
12659 unsigned idx0 = 2;
12660 unsigned idx1 = 2; // src1
12661 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12662 st->print_raw("vaddss ");
12663 opnd_array(0)->int_format(ra, this, st); // dst
12664 st->print_raw(", ");
12665 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12666 st->print_raw(", ");
12667 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12668}
12669#endif
12670#ifndef PRODUCT
12671void addF_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12672 // Start at oper_input_base() and count operands
12673 unsigned idx0 = 2;
12674 unsigned idx1 = 2; // src2
12675 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
12676 st->print_raw("vaddss ");
12677 opnd_array(0)->int_format(ra, this, st); // dst
12678 st->print_raw(", ");
12679 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
12680 st->print_raw(", ");
12681 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
12682}
12683#endif
12684#ifndef PRODUCT
12685void addF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12686 // Start at oper_input_base() and count operands
12687 unsigned idx0 = 1;
12688 unsigned idx1 = 1; // src
12689 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12690 st->print_raw("vaddss ");
12691 opnd_array(0)->int_format(ra, this, st); // dst
12692 st->print_raw(", ");
12693 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12694 st->print_raw(", [");
12695 st->print("constant table base + #%d", constant_offset_unchecked());
12696 st->print_raw("]\t# load from constant table: float=");
12697 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12698}
12699#endif
12700#ifndef PRODUCT
12701void addD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12702 // Start at oper_input_base() and count operands
12703 unsigned idx0 = 1;
12704 unsigned idx1 = 1; // dst
12705 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12706 st->print_raw("addsd ");
12707 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12708 st->print_raw(", ");
12709 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12710}
12711#endif
12712#ifndef PRODUCT
12713void addD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12714 // Start at oper_input_base() and count operands
12715 unsigned idx0 = 2;
12716 unsigned idx1 = 2; // dst
12717 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12718 st->print_raw("addsd ");
12719 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12720 st->print_raw(", ");
12721 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12722}
12723#endif
12724#ifndef PRODUCT
12725void addD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12726 // Start at oper_input_base() and count operands
12727 unsigned idx0 = 2;
12728 unsigned idx1 = 2; // src
12729 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
12730 st->print_raw("addsd ");
12731 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
12732 st->print_raw(", ");
12733 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12734}
12735#endif
12736#ifndef PRODUCT
12737void addD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12738 // Start at oper_input_base() and count operands
12739 unsigned idx0 = 1;
12740 unsigned idx1 = 1; // dst
12741 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12742 st->print_raw("addsd ");
12743 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12744 st->print_raw(", [");
12745 st->print("constant table base + #%d", constant_offset_unchecked());
12746 st->print_raw("]\t# load from constant table: double=");
12747 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12748}
12749#endif
12750#ifndef PRODUCT
12751void addD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12752 // Start at oper_input_base() and count operands
12753 unsigned idx0 = 1;
12754 unsigned idx1 = 1; // src1
12755 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12756 st->print_raw("vaddsd ");
12757 opnd_array(0)->int_format(ra, this, st); // dst
12758 st->print_raw(", ");
12759 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12760 st->print_raw(", ");
12761 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12762}
12763#endif
12764#ifndef PRODUCT
12765void addD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12766 // Start at oper_input_base() and count operands
12767 unsigned idx0 = 2;
12768 unsigned idx1 = 2; // src1
12769 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12770 st->print_raw("vaddsd ");
12771 opnd_array(0)->int_format(ra, this, st); // dst
12772 st->print_raw(", ");
12773 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12774 st->print_raw(", ");
12775 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12776}
12777#endif
12778#ifndef PRODUCT
12779void addD_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12780 // Start at oper_input_base() and count operands
12781 unsigned idx0 = 2;
12782 unsigned idx1 = 2; // src2
12783 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
12784 st->print_raw("vaddsd ");
12785 opnd_array(0)->int_format(ra, this, st); // dst
12786 st->print_raw(", ");
12787 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
12788 st->print_raw(", ");
12789 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
12790}
12791#endif
12792#ifndef PRODUCT
12793void addD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12794 // Start at oper_input_base() and count operands
12795 unsigned idx0 = 1;
12796 unsigned idx1 = 1; // src
12797 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12798 st->print_raw("vaddsd ");
12799 opnd_array(0)->int_format(ra, this, st); // dst
12800 st->print_raw(", ");
12801 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12802 st->print_raw(", [");
12803 st->print("constant table base + #%d", constant_offset_unchecked());
12804 st->print_raw("]\t# load from constant table: double=");
12805 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12806}
12807#endif
12808#ifndef PRODUCT
12809void subF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12810 // Start at oper_input_base() and count operands
12811 unsigned idx0 = 1;
12812 unsigned idx1 = 1; // dst
12813 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12814 st->print_raw("subss ");
12815 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12816 st->print_raw(", ");
12817 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12818}
12819#endif
12820#ifndef PRODUCT
12821void subF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12822 // Start at oper_input_base() and count operands
12823 unsigned idx0 = 2;
12824 unsigned idx1 = 2; // dst
12825 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12826 st->print_raw("subss ");
12827 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12828 st->print_raw(", ");
12829 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12830}
12831#endif
12832#ifndef PRODUCT
12833void subF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12834 // Start at oper_input_base() and count operands
12835 unsigned idx0 = 1;
12836 unsigned idx1 = 1; // dst
12837 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12838 st->print_raw("subss ");
12839 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12840 st->print_raw(", [");
12841 st->print("constant table base + #%d", constant_offset_unchecked());
12842 st->print_raw("]\t# load from constant table: float=");
12843 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12844}
12845#endif
12846#ifndef PRODUCT
12847void subF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12848 // Start at oper_input_base() and count operands
12849 unsigned idx0 = 1;
12850 unsigned idx1 = 1; // src1
12851 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12852 st->print_raw("vsubss ");
12853 opnd_array(0)->int_format(ra, this, st); // dst
12854 st->print_raw(", ");
12855 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12856 st->print_raw(", ");
12857 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12858}
12859#endif
12860#ifndef PRODUCT
12861void subF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12862 // Start at oper_input_base() and count operands
12863 unsigned idx0 = 2;
12864 unsigned idx1 = 2; // src1
12865 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12866 st->print_raw("vsubss ");
12867 opnd_array(0)->int_format(ra, this, st); // dst
12868 st->print_raw(", ");
12869 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12870 st->print_raw(", ");
12871 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12872}
12873#endif
12874#ifndef PRODUCT
12875void subF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12876 // Start at oper_input_base() and count operands
12877 unsigned idx0 = 1;
12878 unsigned idx1 = 1; // src
12879 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12880 st->print_raw("vsubss ");
12881 opnd_array(0)->int_format(ra, this, st); // dst
12882 st->print_raw(", ");
12883 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12884 st->print_raw(", [");
12885 st->print("constant table base + #%d", constant_offset_unchecked());
12886 st->print_raw("]\t# load from constant table: float=");
12887 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12888}
12889#endif
12890#ifndef PRODUCT
12891void subD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12892 // Start at oper_input_base() and count operands
12893 unsigned idx0 = 1;
12894 unsigned idx1 = 1; // dst
12895 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12896 st->print_raw("subsd ");
12897 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12898 st->print_raw(", ");
12899 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12900}
12901#endif
12902#ifndef PRODUCT
12903void subD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12904 // Start at oper_input_base() and count operands
12905 unsigned idx0 = 2;
12906 unsigned idx1 = 2; // dst
12907 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12908 st->print_raw("subsd ");
12909 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12910 st->print_raw(", ");
12911 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12912}
12913#endif
12914#ifndef PRODUCT
12915void subD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12916 // Start at oper_input_base() and count operands
12917 unsigned idx0 = 1;
12918 unsigned idx1 = 1; // dst
12919 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12920 st->print_raw("subsd ");
12921 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12922 st->print_raw(", [");
12923 st->print("constant table base + #%d", constant_offset_unchecked());
12924 st->print_raw("]\t# load from constant table: double=");
12925 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12926}
12927#endif
12928#ifndef PRODUCT
12929void subD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12930 // Start at oper_input_base() and count operands
12931 unsigned idx0 = 1;
12932 unsigned idx1 = 1; // src1
12933 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12934 st->print_raw("vsubsd ");
12935 opnd_array(0)->int_format(ra, this, st); // dst
12936 st->print_raw(", ");
12937 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12938 st->print_raw(", ");
12939 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12940}
12941#endif
12942#ifndef PRODUCT
12943void subD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12944 // Start at oper_input_base() and count operands
12945 unsigned idx0 = 2;
12946 unsigned idx1 = 2; // src1
12947 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
12948 st->print_raw("vsubsd ");
12949 opnd_array(0)->int_format(ra, this, st); // dst
12950 st->print_raw(", ");
12951 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
12952 st->print_raw(", ");
12953 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
12954}
12955#endif
12956#ifndef PRODUCT
12957void subD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12958 // Start at oper_input_base() and count operands
12959 unsigned idx0 = 1;
12960 unsigned idx1 = 1; // src
12961 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
12962 st->print_raw("vsubsd ");
12963 opnd_array(0)->int_format(ra, this, st); // dst
12964 st->print_raw(", ");
12965 opnd_array(1)->ext_format(ra, this,idx1, st); // src
12966 st->print_raw(", [");
12967 st->print("constant table base + #%d", constant_offset_unchecked());
12968 st->print_raw("]\t# load from constant table: double=");
12969 opnd_array(2)->ext_format(ra, this,idx2, st); // con
12970}
12971#endif
12972#ifndef PRODUCT
12973void mulF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12974 // Start at oper_input_base() and count operands
12975 unsigned idx0 = 1;
12976 unsigned idx1 = 1; // dst
12977 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12978 st->print_raw("mulss ");
12979 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12980 st->print_raw(", ");
12981 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12982}
12983#endif
12984#ifndef PRODUCT
12985void mulF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
12986 // Start at oper_input_base() and count operands
12987 unsigned idx0 = 2;
12988 unsigned idx1 = 2; // dst
12989 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
12990 st->print_raw("mulss ");
12991 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
12992 st->print_raw(", ");
12993 opnd_array(2)->ext_format(ra, this,idx2, st); // src
12994}
12995#endif
12996#ifndef PRODUCT
12997void mulF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
12998 // Start at oper_input_base() and count operands
12999 unsigned idx0 = 2;
13000 unsigned idx1 = 2; // src
13001 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
13002 st->print_raw("mulss ");
13003 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
13004 st->print_raw(", ");
13005 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13006}
13007#endif
13008#ifndef PRODUCT
13009void mulF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13010 // Start at oper_input_base() and count operands
13011 unsigned idx0 = 1;
13012 unsigned idx1 = 1; // dst
13013 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13014 st->print_raw("mulss ");
13015 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13016 st->print_raw(", [");
13017 st->print("constant table base + #%d", constant_offset_unchecked());
13018 st->print_raw("]\t# load from constant table: float=");
13019 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13020}
13021#endif
13022#ifndef PRODUCT
13023void mulF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13024 // Start at oper_input_base() and count operands
13025 unsigned idx0 = 1;
13026 unsigned idx1 = 1; // src1
13027 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13028 st->print_raw("vmulss ");
13029 opnd_array(0)->int_format(ra, this, st); // dst
13030 st->print_raw(", ");
13031 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13032 st->print_raw(", ");
13033 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13034}
13035#endif
13036#ifndef PRODUCT
13037void mulF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13038 // Start at oper_input_base() and count operands
13039 unsigned idx0 = 2;
13040 unsigned idx1 = 2; // src1
13041 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13042 st->print_raw("vmulss ");
13043 opnd_array(0)->int_format(ra, this, st); // dst
13044 st->print_raw(", ");
13045 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13046 st->print_raw(", ");
13047 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13048}
13049#endif
13050#ifndef PRODUCT
13051void mulF_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13052 // Start at oper_input_base() and count operands
13053 unsigned idx0 = 2;
13054 unsigned idx1 = 2; // src2
13055 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
13056 st->print_raw("vmulss ");
13057 opnd_array(0)->int_format(ra, this, st); // dst
13058 st->print_raw(", ");
13059 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
13060 st->print_raw(", ");
13061 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
13062}
13063#endif
13064#ifndef PRODUCT
13065void mulF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13066 // Start at oper_input_base() and count operands
13067 unsigned idx0 = 1;
13068 unsigned idx1 = 1; // src
13069 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13070 st->print_raw("vmulss ");
13071 opnd_array(0)->int_format(ra, this, st); // dst
13072 st->print_raw(", ");
13073 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13074 st->print_raw(", [");
13075 st->print("constant table base + #%d", constant_offset_unchecked());
13076 st->print_raw("]\t# load from constant table: float=");
13077 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13078}
13079#endif
13080#ifndef PRODUCT
13081void mulD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13082 // Start at oper_input_base() and count operands
13083 unsigned idx0 = 1;
13084 unsigned idx1 = 1; // dst
13085 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13086 st->print_raw("mulsd ");
13087 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13088 st->print_raw(", ");
13089 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13090}
13091#endif
13092#ifndef PRODUCT
13093void mulD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13094 // Start at oper_input_base() and count operands
13095 unsigned idx0 = 2;
13096 unsigned idx1 = 2; // dst
13097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13098 st->print_raw("mulsd ");
13099 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13100 st->print_raw(", ");
13101 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13102}
13103#endif
13104#ifndef PRODUCT
13105void mulD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13106 // Start at oper_input_base() and count operands
13107 unsigned idx0 = 2;
13108 unsigned idx1 = 2; // src
13109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
13110 st->print_raw("mulsd ");
13111 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
13112 st->print_raw(", ");
13113 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13114}
13115#endif
13116#ifndef PRODUCT
13117void mulD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13118 // Start at oper_input_base() and count operands
13119 unsigned idx0 = 1;
13120 unsigned idx1 = 1; // dst
13121 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13122 st->print_raw("mulsd ");
13123 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13124 st->print_raw(", [");
13125 st->print("constant table base + #%d", constant_offset_unchecked());
13126 st->print_raw("]\t# load from constant table: double=");
13127 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13128}
13129#endif
13130#ifndef PRODUCT
13131void mulD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13132 // Start at oper_input_base() and count operands
13133 unsigned idx0 = 1;
13134 unsigned idx1 = 1; // src1
13135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13136 st->print_raw("vmulsd ");
13137 opnd_array(0)->int_format(ra, this, st); // dst
13138 st->print_raw(", ");
13139 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13140 st->print_raw(", ");
13141 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13142}
13143#endif
13144#ifndef PRODUCT
13145void mulD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13146 // Start at oper_input_base() and count operands
13147 unsigned idx0 = 2;
13148 unsigned idx1 = 2; // src1
13149 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13150 st->print_raw("vmulsd ");
13151 opnd_array(0)->int_format(ra, this, st); // dst
13152 st->print_raw(", ");
13153 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13154 st->print_raw(", ");
13155 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13156}
13157#endif
13158#ifndef PRODUCT
13159void mulD_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13160 // Start at oper_input_base() and count operands
13161 unsigned idx0 = 2;
13162 unsigned idx1 = 2; // src2
13163 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
13164 st->print_raw("vmulsd ");
13165 opnd_array(0)->int_format(ra, this, st); // dst
13166 st->print_raw(", ");
13167 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
13168 st->print_raw(", ");
13169 opnd_array(1)->ext_format(ra, this,idx1, st); // src2
13170}
13171#endif
13172#ifndef PRODUCT
13173void mulD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13174 // Start at oper_input_base() and count operands
13175 unsigned idx0 = 1;
13176 unsigned idx1 = 1; // src
13177 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13178 st->print_raw("vmulsd ");
13179 opnd_array(0)->int_format(ra, this, st); // dst
13180 st->print_raw(", ");
13181 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13182 st->print_raw(", [");
13183 st->print("constant table base + #%d", constant_offset_unchecked());
13184 st->print_raw("]\t# load from constant table: double=");
13185 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13186}
13187#endif
13188#ifndef PRODUCT
13189void divF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13190 // Start at oper_input_base() and count operands
13191 unsigned idx0 = 1;
13192 unsigned idx1 = 1; // dst
13193 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13194 st->print_raw("divss ");
13195 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13196 st->print_raw(", ");
13197 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13198}
13199#endif
13200#ifndef PRODUCT
13201void divF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13202 // Start at oper_input_base() and count operands
13203 unsigned idx0 = 2;
13204 unsigned idx1 = 2; // dst
13205 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13206 st->print_raw("divss ");
13207 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13208 st->print_raw(", ");
13209 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13210}
13211#endif
13212#ifndef PRODUCT
13213void divF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13214 // Start at oper_input_base() and count operands
13215 unsigned idx0 = 1;
13216 unsigned idx1 = 1; // dst
13217 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13218 st->print_raw("divss ");
13219 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13220 st->print_raw(", [");
13221 st->print("constant table base + #%d", constant_offset_unchecked());
13222 st->print_raw("]\t# load from constant table: float=");
13223 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13224}
13225#endif
13226#ifndef PRODUCT
13227void divF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13228 // Start at oper_input_base() and count operands
13229 unsigned idx0 = 1;
13230 unsigned idx1 = 1; // src1
13231 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13232 st->print_raw("vdivss ");
13233 opnd_array(0)->int_format(ra, this, st); // dst
13234 st->print_raw(", ");
13235 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13236 st->print_raw(", ");
13237 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13238}
13239#endif
13240#ifndef PRODUCT
13241void divF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13242 // Start at oper_input_base() and count operands
13243 unsigned idx0 = 2;
13244 unsigned idx1 = 2; // src1
13245 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13246 st->print_raw("vdivss ");
13247 opnd_array(0)->int_format(ra, this, st); // dst
13248 st->print_raw(", ");
13249 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13250 st->print_raw(", ");
13251 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13252}
13253#endif
13254#ifndef PRODUCT
13255void divF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13256 // Start at oper_input_base() and count operands
13257 unsigned idx0 = 1;
13258 unsigned idx1 = 1; // src
13259 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13260 st->print_raw("vdivss ");
13261 opnd_array(0)->int_format(ra, this, st); // dst
13262 st->print_raw(", ");
13263 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13264 st->print_raw(", [");
13265 st->print("constant table base + #%d", constant_offset_unchecked());
13266 st->print_raw("]\t# load from constant table: float=");
13267 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13268}
13269#endif
13270#ifndef PRODUCT
13271void divD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13272 // Start at oper_input_base() and count operands
13273 unsigned idx0 = 1;
13274 unsigned idx1 = 1; // dst
13275 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13276 st->print_raw("divsd ");
13277 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13278 st->print_raw(", ");
13279 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13280}
13281#endif
13282#ifndef PRODUCT
13283void divD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13284 // Start at oper_input_base() and count operands
13285 unsigned idx0 = 2;
13286 unsigned idx1 = 2; // dst
13287 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13288 st->print_raw("divsd ");
13289 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13290 st->print_raw(", ");
13291 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13292}
13293#endif
13294#ifndef PRODUCT
13295void divD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13296 // Start at oper_input_base() and count operands
13297 unsigned idx0 = 1;
13298 unsigned idx1 = 1; // dst
13299 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13300 st->print_raw("divsd ");
13301 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13302 st->print_raw(", [");
13303 st->print("constant table base + #%d", constant_offset_unchecked());
13304 st->print_raw("]\t# load from constant table: double=");
13305 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13306}
13307#endif
13308#ifndef PRODUCT
13309void divD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13310 // Start at oper_input_base() and count operands
13311 unsigned idx0 = 1;
13312 unsigned idx1 = 1; // src1
13313 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13314 st->print_raw("vdivsd ");
13315 opnd_array(0)->int_format(ra, this, st); // dst
13316 st->print_raw(", ");
13317 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13318 st->print_raw(", ");
13319 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13320}
13321#endif
13322#ifndef PRODUCT
13323void divD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13324 // Start at oper_input_base() and count operands
13325 unsigned idx0 = 2;
13326 unsigned idx1 = 2; // src1
13327 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
13328 st->print_raw("vdivsd ");
13329 opnd_array(0)->int_format(ra, this, st); // dst
13330 st->print_raw(", ");
13331 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
13332 st->print_raw(", ");
13333 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
13334}
13335#endif
13336#ifndef PRODUCT
13337void divD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13338 // Start at oper_input_base() and count operands
13339 unsigned idx0 = 1;
13340 unsigned idx1 = 1; // src
13341 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
13342 st->print_raw("vdivsd ");
13343 opnd_array(0)->int_format(ra, this, st); // dst
13344 st->print_raw(", ");
13345 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13346 st->print_raw(", [");
13347 st->print("constant table base + #%d", constant_offset_unchecked());
13348 st->print_raw("]\t# load from constant table: double=");
13349 opnd_array(2)->ext_format(ra, this,idx2, st); // con
13350}
13351#endif
13352#ifndef PRODUCT
13353void absF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13354 // Start at oper_input_base() and count operands
13355 unsigned idx0 = 1;
13356 unsigned idx1 = 1; // dst
13357 st->print_raw("andps ");
13358 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13359 st->print_raw(", [0x7fffffff]\t# abs float by sign masking");
13360}
13361#endif
13362#ifndef PRODUCT
13363void absF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13364 // Start at oper_input_base() and count operands
13365 unsigned idx0 = 1;
13366 unsigned idx1 = 1; // src
13367 st->print_raw("vandps ");
13368 opnd_array(0)->int_format(ra, this, st); // dst
13369 st->print_raw(", ");
13370 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13371 st->print_raw(", [0x7fffffff]\t# abs float by sign masking");
13372}
13373#endif
13374#ifndef PRODUCT
13375void absD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13376 // Start at oper_input_base() and count operands
13377 unsigned idx0 = 1;
13378 unsigned idx1 = 1; // dst
13379 st->print_raw("andpd ");
13380 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13381 st->print_raw(", [0x7fffffffffffffff]\t");
13382 st->print_raw("# abs double by sign masking");
13383}
13384#endif
13385#ifndef PRODUCT
13386void absD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13387 // Start at oper_input_base() and count operands
13388 unsigned idx0 = 1;
13389 unsigned idx1 = 1; // src
13390 st->print_raw("vandpd ");
13391 opnd_array(0)->int_format(ra, this, st); // dst
13392 st->print_raw(", ");
13393 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13394 st->print_raw(", [0x7fffffffffffffff]\t");
13395 st->print_raw("# abs double by sign masking");
13396}
13397#endif
13398#ifndef PRODUCT
13399void negF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13400 // Start at oper_input_base() and count operands
13401 unsigned idx0 = 1;
13402 unsigned idx1 = 1; // dst
13403 st->print_raw("xorps ");
13404 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13405 st->print_raw(", [0x80000000]\t# neg float by sign flipping");
13406}
13407#endif
13408#ifndef PRODUCT
13409void negF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13410 // Start at oper_input_base() and count operands
13411 unsigned idx0 = 1;
13412 unsigned idx1 = 1; // src
13413 st->print_raw("vnegatess ");
13414 opnd_array(0)->int_format(ra, this, st); // dst
13415 st->print_raw(", ");
13416 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13417 st->print_raw(", [0x80000000]\t# neg float by sign flipping");
13418}
13419#endif
13420#ifndef PRODUCT
13421void negD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13422 // Start at oper_input_base() and count operands
13423 unsigned idx0 = 1;
13424 unsigned idx1 = 1; // dst
13425 st->print_raw("xorpd ");
13426 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
13427 st->print_raw(", [0x8000000000000000]\t");
13428 st->print_raw("# neg double by sign flipping");
13429}
13430#endif
13431#ifndef PRODUCT
13432void negD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13433 // Start at oper_input_base() and count operands
13434 unsigned idx0 = 1;
13435 unsigned idx1 = 1; // src
13436 st->print_raw("vnegatesd ");
13437 opnd_array(0)->int_format(ra, this, st); // dst
13438 st->print_raw(", ");
13439 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13440 st->print_raw(", [0x8000000000000000]\t");
13441 st->print_raw("# neg double by sign flipping");
13442}
13443#endif
13444#ifndef PRODUCT
13445void sqrtF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13446 // Start at oper_input_base() and count operands
13447 unsigned idx0 = 1;
13448 unsigned idx1 = 1; // src
13449 st->print_raw("sqrtss ");
13450 opnd_array(0)->int_format(ra, this, st); // dst
13451 st->print_raw(", ");
13452 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13453}
13454#endif
13455#ifndef PRODUCT
13456void sqrtF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13457 // Start at oper_input_base() and count operands
13458 unsigned idx0 = 2;
13459 unsigned idx1 = 2; // src
13460 st->print_raw("sqrtss ");
13461 opnd_array(0)->int_format(ra, this, st); // dst
13462 st->print_raw(", ");
13463 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13464}
13465#endif
13466#ifndef PRODUCT
13467void sqrtF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13468 // Start at oper_input_base() and count operands
13469 unsigned idx0 = 1;
13470 unsigned idx1 = 1; // con
13471 st->print_raw("sqrtss ");
13472 opnd_array(0)->int_format(ra, this, st); // dst
13473 st->print_raw(", [");
13474 st->print("constant table base + #%d", constant_offset_unchecked());
13475 st->print_raw("]\t# load from constant table: float=");
13476 opnd_array(1)->ext_format(ra, this,idx1, st); // con
13477}
13478#endif
13479#ifndef PRODUCT
13480void sqrtD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13481 // Start at oper_input_base() and count operands
13482 unsigned idx0 = 1;
13483 unsigned idx1 = 1; // src
13484 st->print_raw("sqrtsd ");
13485 opnd_array(0)->int_format(ra, this, st); // dst
13486 st->print_raw(", ");
13487 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13488}
13489#endif
13490#ifndef PRODUCT
13491void sqrtD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13492 // Start at oper_input_base() and count operands
13493 unsigned idx0 = 2;
13494 unsigned idx1 = 2; // src
13495 st->print_raw("sqrtsd ");
13496 opnd_array(0)->int_format(ra, this, st); // dst
13497 st->print_raw(", ");
13498 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13499}
13500#endif
13501#ifndef PRODUCT
13502void sqrtD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13503 // Start at oper_input_base() and count operands
13504 unsigned idx0 = 1;
13505 unsigned idx1 = 1; // con
13506 st->print_raw("sqrtsd ");
13507 opnd_array(0)->int_format(ra, this, st); // dst
13508 st->print_raw(", [");
13509 st->print("constant table base + #%d", constant_offset_unchecked());
13510 st->print_raw("]\t# load from constant table: double=");
13511 opnd_array(1)->ext_format(ra, this,idx1, st); // con
13512}
13513#endif
13514#ifndef PRODUCT
13515void onspinwaitNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13516 st->print_raw("pause\t! membar_onspinwait");
13517}
13518#endif
13519#ifndef PRODUCT
13520void fmaD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13521 // Start at oper_input_base() and count operands
13522 unsigned idx0 = 1;
13523 unsigned idx1 = 1; // c
13524 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
13525 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
13526 st->print_raw("fmasd ");
13527 opnd_array(2)->ext_format(ra, this,idx2, st); // a
13528 st->print_raw(",");
13529 opnd_array(3)->ext_format(ra, this,idx3, st); // b
13530 st->print_raw(",");
13531 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13532 st->print_raw("\t# ");
13533 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13534 st->print_raw(" = ");
13535 opnd_array(2)->ext_format(ra, this,idx2, st); // a
13536 st->print_raw(" * ");
13537 opnd_array(3)->ext_format(ra, this,idx3, st); // b
13538 st->print_raw(" + ");
13539 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13540}
13541#endif
13542#ifndef PRODUCT
13543void fmaF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13544 // Start at oper_input_base() and count operands
13545 unsigned idx0 = 1;
13546 unsigned idx1 = 1; // c
13547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
13548 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
13549 st->print_raw("fmass ");
13550 opnd_array(2)->ext_format(ra, this,idx2, st); // a
13551 st->print_raw(",");
13552 opnd_array(3)->ext_format(ra, this,idx3, st); // b
13553 st->print_raw(",");
13554 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13555 st->print_raw("\t# ");
13556 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13557 st->print_raw(" = ");
13558 opnd_array(2)->ext_format(ra, this,idx2, st); // a
13559 st->print_raw(" * ");
13560 opnd_array(3)->ext_format(ra, this,idx3, st); // b
13561 st->print_raw(" + ");
13562 opnd_array(1)->ext_format(ra, this,idx1, st); // c
13563}
13564#endif
13565#ifndef PRODUCT
13566void loadV4Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13567 // Start at oper_input_base() and count operands
13568 unsigned idx0 = 2;
13569 unsigned idx1 = 2; // mem
13570 st->print_raw("movd ");
13571 opnd_array(0)->int_format(ra, this, st); // dst
13572 st->print_raw(",");
13573 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13574 st->print_raw("\t! load vector (4 bytes)");
13575 if (ra->C->alias_type(adr_type())->field() != NULL) {
13576 ciField* f = ra->C->alias_type(adr_type())->field();
13577 st->print(" ! Field: ");
13578 if (f->is_volatile())
13579 st->print("volatile ");
13580 f->holder()->name()->print_symbol_on(st);
13581 st->print(".");
13582 f->name()->print_symbol_on(st);
13583 if (f->is_constant())
13584 st->print(" (constant)");
13585 } else {
13586 if (ra->C->alias_type(adr_type())->is_volatile())
13587 st->print(" volatile!");
13588 }
13589}
13590#endif
13591#ifndef PRODUCT
13592void MoveVecS2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13593 // Start at oper_input_base() and count operands
13594 unsigned idx0 = 1;
13595 unsigned idx1 = 1; // src
13596 st->print_raw("movss ");
13597 opnd_array(0)->int_format(ra, this, st); // dst
13598 st->print_raw(",");
13599 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13600 st->print_raw("\t! load vector (4 bytes)");
13601}
13602#endif
13603#ifndef PRODUCT
13604void MoveLeg2VecSNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13605 // Start at oper_input_base() and count operands
13606 unsigned idx0 = 1;
13607 unsigned idx1 = 1; // src
13608 st->print_raw("movss ");
13609 opnd_array(0)->int_format(ra, this, st); // dst
13610 st->print_raw(",");
13611 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13612 st->print_raw("\t! load vector (4 bytes)");
13613}
13614#endif
13615#ifndef PRODUCT
13616void loadV8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13617 // Start at oper_input_base() and count operands
13618 unsigned idx0 = 2;
13619 unsigned idx1 = 2; // mem
13620 st->print_raw("movq ");
13621 opnd_array(0)->int_format(ra, this, st); // dst
13622 st->print_raw(",");
13623 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13624 st->print_raw("\t! load vector (8 bytes)");
13625 if (ra->C->alias_type(adr_type())->field() != NULL) {
13626 ciField* f = ra->C->alias_type(adr_type())->field();
13627 st->print(" ! Field: ");
13628 if (f->is_volatile())
13629 st->print("volatile ");
13630 f->holder()->name()->print_symbol_on(st);
13631 st->print(".");
13632 f->name()->print_symbol_on(st);
13633 if (f->is_constant())
13634 st->print(" (constant)");
13635 } else {
13636 if (ra->C->alias_type(adr_type())->is_volatile())
13637 st->print(" volatile!");
13638 }
13639}
13640#endif
13641#ifndef PRODUCT
13642void MoveVecD2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13643 // Start at oper_input_base() and count operands
13644 unsigned idx0 = 1;
13645 unsigned idx1 = 1; // src
13646 st->print_raw("movsd ");
13647 opnd_array(0)->int_format(ra, this, st); // dst
13648 st->print_raw(",");
13649 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13650 st->print_raw("\t! load vector (8 bytes)");
13651}
13652#endif
13653#ifndef PRODUCT
13654void MoveLeg2VecDNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13655 // Start at oper_input_base() and count operands
13656 unsigned idx0 = 1;
13657 unsigned idx1 = 1; // src
13658 st->print_raw("movsd ");
13659 opnd_array(0)->int_format(ra, this, st); // dst
13660 st->print_raw(",");
13661 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13662 st->print_raw("\t! load vector (8 bytes)");
13663}
13664#endif
13665#ifndef PRODUCT
13666void loadV16Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13667 // Start at oper_input_base() and count operands
13668 unsigned idx0 = 2;
13669 unsigned idx1 = 2; // mem
13670 st->print_raw("movdqu ");
13671 opnd_array(0)->int_format(ra, this, st); // dst
13672 st->print_raw(",");
13673 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13674 st->print_raw("\t! load vector (16 bytes)");
13675 if (ra->C->alias_type(adr_type())->field() != NULL) {
13676 ciField* f = ra->C->alias_type(adr_type())->field();
13677 st->print(" ! Field: ");
13678 if (f->is_volatile())
13679 st->print("volatile ");
13680 f->holder()->name()->print_symbol_on(st);
13681 st->print(".");
13682 f->name()->print_symbol_on(st);
13683 if (f->is_constant())
13684 st->print(" (constant)");
13685 } else {
13686 if (ra->C->alias_type(adr_type())->is_volatile())
13687 st->print(" volatile!");
13688 }
13689}
13690#endif
13691#ifndef PRODUCT
13692void MoveVecX2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13693 // Start at oper_input_base() and count operands
13694 unsigned idx0 = 1;
13695 unsigned idx1 = 1; // src
13696 st->print_raw("movdqu ");
13697 opnd_array(0)->int_format(ra, this, st); // dst
13698 st->print_raw(",");
13699 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13700 st->print_raw("\t! load vector (16 bytes)");
13701}
13702#endif
13703#ifndef PRODUCT
13704void MoveLeg2VecXNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13705 // Start at oper_input_base() and count operands
13706 unsigned idx0 = 1;
13707 unsigned idx1 = 1; // src
13708 st->print_raw("movdqu ");
13709 opnd_array(0)->int_format(ra, this, st); // dst
13710 st->print_raw(",");
13711 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13712 st->print_raw("\t! load vector (16 bytes)");
13713}
13714#endif
13715#ifndef PRODUCT
13716void loadV32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13717 // Start at oper_input_base() and count operands
13718 unsigned idx0 = 2;
13719 unsigned idx1 = 2; // mem
13720 st->print_raw("vmovdqu ");
13721 opnd_array(0)->int_format(ra, this, st); // dst
13722 st->print_raw(",");
13723 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13724 st->print_raw("\t! load vector (32 bytes)");
13725 if (ra->C->alias_type(adr_type())->field() != NULL) {
13726 ciField* f = ra->C->alias_type(adr_type())->field();
13727 st->print(" ! Field: ");
13728 if (f->is_volatile())
13729 st->print("volatile ");
13730 f->holder()->name()->print_symbol_on(st);
13731 st->print(".");
13732 f->name()->print_symbol_on(st);
13733 if (f->is_constant())
13734 st->print(" (constant)");
13735 } else {
13736 if (ra->C->alias_type(adr_type())->is_volatile())
13737 st->print(" volatile!");
13738 }
13739}
13740#endif
13741#ifndef PRODUCT
13742void MoveVecY2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13743 // Start at oper_input_base() and count operands
13744 unsigned idx0 = 1;
13745 unsigned idx1 = 1; // src
13746 st->print_raw("vmovdqu ");
13747 opnd_array(0)->int_format(ra, this, st); // dst
13748 st->print_raw(",");
13749 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13750 st->print_raw("\t! load vector (32 bytes)");
13751}
13752#endif
13753#ifndef PRODUCT
13754void MoveLeg2VecYNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13755 // Start at oper_input_base() and count operands
13756 unsigned idx0 = 1;
13757 unsigned idx1 = 1; // src
13758 st->print_raw("vmovdqu ");
13759 opnd_array(0)->int_format(ra, this, st); // dst
13760 st->print_raw(",");
13761 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13762 st->print_raw("\t! load vector (32 bytes)");
13763}
13764#endif
13765#ifndef PRODUCT
13766void loadV64_dwordNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13767 // Start at oper_input_base() and count operands
13768 unsigned idx0 = 2;
13769 unsigned idx1 = 2; // mem
13770 st->print_raw("vmovdqul ");
13771 opnd_array(0)->int_format(ra, this, st); // dst
13772 st->print_raw(" k0,");
13773 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13774 st->print_raw("\t! load vector (64 bytes)");
13775 if (ra->C->alias_type(adr_type())->field() != NULL) {
13776 ciField* f = ra->C->alias_type(adr_type())->field();
13777 st->print(" ! Field: ");
13778 if (f->is_volatile())
13779 st->print("volatile ");
13780 f->holder()->name()->print_symbol_on(st);
13781 st->print(".");
13782 f->name()->print_symbol_on(st);
13783 if (f->is_constant())
13784 st->print(" (constant)");
13785 } else {
13786 if (ra->C->alias_type(adr_type())->is_volatile())
13787 st->print(" volatile!");
13788 }
13789}
13790#endif
13791#ifndef PRODUCT
13792void loadV64_qwordNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13793 // Start at oper_input_base() and count operands
13794 unsigned idx0 = 2;
13795 unsigned idx1 = 2; // mem
13796 st->print_raw("vmovdquq ");
13797 opnd_array(0)->int_format(ra, this, st); // dst
13798 st->print_raw(" k0,");
13799 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13800 st->print_raw("\t! load vector (64 bytes)");
13801 if (ra->C->alias_type(adr_type())->field() != NULL) {
13802 ciField* f = ra->C->alias_type(adr_type())->field();
13803 st->print(" ! Field: ");
13804 if (f->is_volatile())
13805 st->print("volatile ");
13806 f->holder()->name()->print_symbol_on(st);
13807 st->print(".");
13808 f->name()->print_symbol_on(st);
13809 if (f->is_constant())
13810 st->print(" (constant)");
13811 } else {
13812 if (ra->C->alias_type(adr_type())->is_volatile())
13813 st->print(" volatile!");
13814 }
13815}
13816#endif
13817#ifndef PRODUCT
13818void MoveVecZ2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13819 // Start at oper_input_base() and count operands
13820 unsigned idx0 = 1;
13821 unsigned idx1 = 1; // src
13822 st->print_raw("vmovdquq ");
13823 opnd_array(0)->int_format(ra, this, st); // dst
13824 st->print_raw(" k0,");
13825 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13826 st->print_raw("\t! Move vector (64 bytes)");
13827}
13828#endif
13829#ifndef PRODUCT
13830void MoveLeg2VecZNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13831 // Start at oper_input_base() and count operands
13832 unsigned idx0 = 1;
13833 unsigned idx1 = 1; // src
13834 st->print_raw("vmovdquq ");
13835 opnd_array(0)->int_format(ra, this, st); // dst
13836 st->print_raw(" k0,");
13837 opnd_array(1)->ext_format(ra, this,idx1, st); // src
13838 st->print_raw("\t! Move vector (64 bytes)");
13839}
13840#endif
13841#ifndef PRODUCT
13842void storeV4Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13843 // Start at oper_input_base() and count operands
13844 unsigned idx0 = 2;
13845 unsigned idx1 = 2; // mem
13846 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13847 st->print_raw("movd ");
13848 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13849 st->print_raw(",");
13850 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13851 st->print_raw("\t! store vector (4 bytes)");
13852 if (ra->C->alias_type(adr_type())->field() != NULL) {
13853 ciField* f = ra->C->alias_type(adr_type())->field();
13854 st->print(" ! Field: ");
13855 if (f->is_volatile())
13856 st->print("volatile ");
13857 f->holder()->name()->print_symbol_on(st);
13858 st->print(".");
13859 f->name()->print_symbol_on(st);
13860 if (f->is_constant())
13861 st->print(" (constant)");
13862 } else {
13863 if (ra->C->alias_type(adr_type())->is_volatile())
13864 st->print(" volatile!");
13865 }
13866}
13867#endif
13868#ifndef PRODUCT
13869void storeV8Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13870 // Start at oper_input_base() and count operands
13871 unsigned idx0 = 2;
13872 unsigned idx1 = 2; // mem
13873 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13874 st->print_raw("movq ");
13875 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13876 st->print_raw(",");
13877 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13878 st->print_raw("\t! store vector (8 bytes)");
13879 if (ra->C->alias_type(adr_type())->field() != NULL) {
13880 ciField* f = ra->C->alias_type(adr_type())->field();
13881 st->print(" ! Field: ");
13882 if (f->is_volatile())
13883 st->print("volatile ");
13884 f->holder()->name()->print_symbol_on(st);
13885 st->print(".");
13886 f->name()->print_symbol_on(st);
13887 if (f->is_constant())
13888 st->print(" (constant)");
13889 } else {
13890 if (ra->C->alias_type(adr_type())->is_volatile())
13891 st->print(" volatile!");
13892 }
13893}
13894#endif
13895#ifndef PRODUCT
13896void storeV16Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13897 // Start at oper_input_base() and count operands
13898 unsigned idx0 = 2;
13899 unsigned idx1 = 2; // mem
13900 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13901 st->print_raw("movdqu ");
13902 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13903 st->print_raw(",");
13904 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13905 st->print_raw("\t! store vector (16 bytes)");
13906 if (ra->C->alias_type(adr_type())->field() != NULL) {
13907 ciField* f = ra->C->alias_type(adr_type())->field();
13908 st->print(" ! Field: ");
13909 if (f->is_volatile())
13910 st->print("volatile ");
13911 f->holder()->name()->print_symbol_on(st);
13912 st->print(".");
13913 f->name()->print_symbol_on(st);
13914 if (f->is_constant())
13915 st->print(" (constant)");
13916 } else {
13917 if (ra->C->alias_type(adr_type())->is_volatile())
13918 st->print(" volatile!");
13919 }
13920}
13921#endif
13922#ifndef PRODUCT
13923void storeV32Node::format(PhaseRegAlloc *ra, outputStream *st) const {
13924 // Start at oper_input_base() and count operands
13925 unsigned idx0 = 2;
13926 unsigned idx1 = 2; // mem
13927 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13928 st->print_raw("vmovdqu ");
13929 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13930 st->print_raw(",");
13931 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13932 st->print_raw("\t! store vector (32 bytes)");
13933 if (ra->C->alias_type(adr_type())->field() != NULL) {
13934 ciField* f = ra->C->alias_type(adr_type())->field();
13935 st->print(" ! Field: ");
13936 if (f->is_volatile())
13937 st->print("volatile ");
13938 f->holder()->name()->print_symbol_on(st);
13939 st->print(".");
13940 f->name()->print_symbol_on(st);
13941 if (f->is_constant())
13942 st->print(" (constant)");
13943 } else {
13944 if (ra->C->alias_type(adr_type())->is_volatile())
13945 st->print(" volatile!");
13946 }
13947}
13948#endif
13949#ifndef PRODUCT
13950void storeV64_dwordNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13951 // Start at oper_input_base() and count operands
13952 unsigned idx0 = 2;
13953 unsigned idx1 = 2; // mem
13954 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13955 st->print_raw("vmovdqul ");
13956 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13957 st->print_raw(" k0,");
13958 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13959 st->print_raw("\t! store vector (64 bytes)");
13960 if (ra->C->alias_type(adr_type())->field() != NULL) {
13961 ciField* f = ra->C->alias_type(adr_type())->field();
13962 st->print(" ! Field: ");
13963 if (f->is_volatile())
13964 st->print("volatile ");
13965 f->holder()->name()->print_symbol_on(st);
13966 st->print(".");
13967 f->name()->print_symbol_on(st);
13968 if (f->is_constant())
13969 st->print(" (constant)");
13970 } else {
13971 if (ra->C->alias_type(adr_type())->is_volatile())
13972 st->print(" volatile!");
13973 }
13974}
13975#endif
13976#ifndef PRODUCT
13977void storeV64_qwordNode::format(PhaseRegAlloc *ra, outputStream *st) const {
13978 // Start at oper_input_base() and count operands
13979 unsigned idx0 = 2;
13980 unsigned idx1 = 2; // mem
13981 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
13982 st->print_raw("vmovdquq ");
13983 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
13984 st->print_raw(" k0,");
13985 opnd_array(2)->ext_format(ra, this,idx2, st); // src
13986 st->print_raw("\t! store vector (64 bytes)");
13987 if (ra->C->alias_type(adr_type())->field() != NULL) {
13988 ciField* f = ra->C->alias_type(adr_type())->field();
13989 st->print(" ! Field: ");
13990 if (f->is_volatile())
13991 st->print("volatile ");
13992 f->holder()->name()->print_symbol_on(st);
13993 st->print(".");
13994 f->name()->print_symbol_on(st);
13995 if (f->is_constant())
13996 st->print(" (constant)");
13997 } else {
13998 if (ra->C->alias_type(adr_type())->is_volatile())
13999 st->print(" volatile!");
14000 }
14001}
14002#endif
14003#ifndef PRODUCT
14004void Repl16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14005 // Start at oper_input_base() and count operands
14006 unsigned idx0 = 1;
14007 unsigned idx1 = 1; // src
14008 st->print_raw("movd ");
14009 opnd_array(0)->int_format(ra, this, st); // dst
14010 st->print_raw(",");
14011 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14012 st->print_raw("\n\t");
14013 st->print_raw("punpcklbw ");
14014 opnd_array(0)->int_format(ra, this, st); // dst
14015 st->print_raw(",");
14016 opnd_array(0)->int_format(ra, this, st); // dst
14017 st->print_raw("\n\t");
14018 st->print_raw("pshuflw ");
14019 opnd_array(0)->int_format(ra, this, st); // dst
14020 st->print_raw(",");
14021 opnd_array(0)->int_format(ra, this, st); // dst
14022 st->print_raw(",0x00\n\t");
14023 st->print_raw("punpcklqdq ");
14024 opnd_array(0)->int_format(ra, this, st); // dst
14025 st->print_raw(",");
14026 opnd_array(0)->int_format(ra, this, st); // dst
14027 st->print_raw("\t! replicate16B");
14028}
14029#endif
14030#ifndef PRODUCT
14031void Repl32BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14032 // Start at oper_input_base() and count operands
14033 unsigned idx0 = 1;
14034 unsigned idx1 = 1; // src
14035 st->print_raw("movd ");
14036 opnd_array(0)->int_format(ra, this, st); // dst
14037 st->print_raw(",");
14038 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14039 st->print_raw("\n\t");
14040 st->print_raw("punpcklbw ");
14041 opnd_array(0)->int_format(ra, this, st); // dst
14042 st->print_raw(",");
14043 opnd_array(0)->int_format(ra, this, st); // dst
14044 st->print_raw("\n\t");
14045 st->print_raw("pshuflw ");
14046 opnd_array(0)->int_format(ra, this, st); // dst
14047 st->print_raw(",");
14048 opnd_array(0)->int_format(ra, this, st); // dst
14049 st->print_raw(",0x00\n\t");
14050 st->print_raw("punpcklqdq ");
14051 opnd_array(0)->int_format(ra, this, st); // dst
14052 st->print_raw(",");
14053 opnd_array(0)->int_format(ra, this, st); // dst
14054 st->print_raw("\n\t");
14055 st->print_raw("vinserti128_high ");
14056 opnd_array(0)->int_format(ra, this, st); // dst
14057 st->print_raw(",");
14058 opnd_array(0)->int_format(ra, this, st); // dst
14059 st->print_raw("\t! replicate32B");
14060}
14061#endif
14062#ifndef PRODUCT
14063void Repl64BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14064 // Start at oper_input_base() and count operands
14065 unsigned idx0 = 1;
14066 unsigned idx1 = 1; // src
14067 st->print_raw("movd ");
14068 opnd_array(0)->int_format(ra, this, st); // dst
14069 st->print_raw(",");
14070 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14071 st->print_raw("\n\t");
14072 st->print_raw("punpcklbw ");
14073 opnd_array(0)->int_format(ra, this, st); // dst
14074 st->print_raw(",");
14075 opnd_array(0)->int_format(ra, this, st); // dst
14076 st->print_raw("\n\t");
14077 st->print_raw("pshuflw ");
14078 opnd_array(0)->int_format(ra, this, st); // dst
14079 st->print_raw(",");
14080 opnd_array(0)->int_format(ra, this, st); // dst
14081 st->print_raw(",0x00\n\t");
14082 st->print_raw("punpcklqdq ");
14083 opnd_array(0)->int_format(ra, this, st); // dst
14084 st->print_raw(",");
14085 opnd_array(0)->int_format(ra, this, st); // dst
14086 st->print_raw("\n\t");
14087 st->print_raw("vinserti128_high ");
14088 opnd_array(0)->int_format(ra, this, st); // dst
14089 st->print_raw(",");
14090 opnd_array(0)->int_format(ra, this, st); // dst
14091 st->print_raw("\t");
14092 st->print_raw("vinserti64x4 ");
14093 opnd_array(0)->int_format(ra, this, st); // dst
14094 st->print_raw(",");
14095 opnd_array(0)->int_format(ra, this, st); // dst
14096 st->print_raw(",");
14097 opnd_array(0)->int_format(ra, this, st); // dst
14098 st->print_raw(",0x1\t! replicate64B");
14099}
14100#endif
14101#ifndef PRODUCT
14102void Repl16B_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14103 // Start at oper_input_base() and count operands
14104 unsigned idx0 = 1;
14105 unsigned idx1 = 1; // con
14106 st->print_raw("movq ");
14107 opnd_array(0)->int_format(ra, this, st); // dst
14108 st->print_raw(",[");
14109 st->print("constant table base + #%d", constant_offset_unchecked());
14110 st->print_raw("]\n\t");
14111 st->print_raw("punpcklqdq ");
14112 opnd_array(0)->int_format(ra, this, st); // dst
14113 st->print_raw(",");
14114 opnd_array(0)->int_format(ra, this, st); // dst
14115 st->print_raw("\t! replicate16B(");
14116 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14117 st->print_raw(")");
14118}
14119#endif
14120#ifndef PRODUCT
14121void Repl32B_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14122 // Start at oper_input_base() and count operands
14123 unsigned idx0 = 1;
14124 unsigned idx1 = 1; // con
14125 st->print_raw("movq ");
14126 opnd_array(0)->int_format(ra, this, st); // dst
14127 st->print_raw(",[");
14128 st->print("constant table base + #%d", constant_offset_unchecked());
14129 st->print_raw("]\n\t");
14130 st->print_raw("punpcklqdq ");
14131 opnd_array(0)->int_format(ra, this, st); // dst
14132 st->print_raw(",");
14133 opnd_array(0)->int_format(ra, this, st); // dst
14134 st->print_raw("\n\t");
14135 st->print_raw("vinserti128_high ");
14136 opnd_array(0)->int_format(ra, this, st); // dst
14137 st->print_raw(",");
14138 opnd_array(0)->int_format(ra, this, st); // dst
14139 st->print_raw("\t! lreplicate32B(");
14140 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14141 st->print_raw(")");
14142}
14143#endif
14144#ifndef PRODUCT
14145void Repl64B_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14146 // Start at oper_input_base() and count operands
14147 unsigned idx0 = 1;
14148 unsigned idx1 = 1; // con
14149 st->print_raw("movq ");
14150 opnd_array(0)->int_format(ra, this, st); // dst
14151 st->print_raw(",[");
14152 st->print("constant table base + #%d", constant_offset_unchecked());
14153 st->print_raw("]\n\t");
14154 st->print_raw("punpcklqdq ");
14155 opnd_array(0)->int_format(ra, this, st); // dst
14156 st->print_raw(",");
14157 opnd_array(0)->int_format(ra, this, st); // dst
14158 st->print_raw("\n\t");
14159 st->print_raw("vinserti128_high ");
14160 opnd_array(0)->int_format(ra, this, st); // dst
14161 st->print_raw(",");
14162 opnd_array(0)->int_format(ra, this, st); // dst
14163 st->print_raw("\t");
14164 st->print_raw("vinserti64x4 ");
14165 opnd_array(0)->int_format(ra, this, st); // dst
14166 st->print_raw(",");
14167 opnd_array(0)->int_format(ra, this, st); // dst
14168 st->print_raw(",");
14169 opnd_array(0)->int_format(ra, this, st); // dst
14170 st->print_raw(",0x1\t! replicate64B(");
14171 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14172 st->print_raw(")");
14173}
14174#endif
14175#ifndef PRODUCT
14176void Repl4SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14177 // Start at oper_input_base() and count operands
14178 unsigned idx0 = 1;
14179 unsigned idx1 = 1; // src
14180 st->print_raw("movd ");
14181 opnd_array(0)->int_format(ra, this, st); // dst
14182 st->print_raw(",");
14183 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14184 st->print_raw("\n\t");
14185 st->print_raw("pshuflw ");
14186 opnd_array(0)->int_format(ra, this, st); // dst
14187 st->print_raw(",");
14188 opnd_array(0)->int_format(ra, this, st); // dst
14189 st->print_raw(",0x00\t! replicate4S");
14190}
14191#endif
14192#ifndef PRODUCT
14193void Repl4S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14194 // Start at oper_input_base() and count operands
14195 unsigned idx0 = 2;
14196 unsigned idx1 = 2; // mem
14197 st->print_raw("pshuflw ");
14198 opnd_array(0)->int_format(ra, this, st); // dst
14199 st->print_raw(",");
14200 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14201 st->print_raw(",0x00\t! replicate4S");
14202}
14203#endif
14204#ifndef PRODUCT
14205void Repl8SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14206 // Start at oper_input_base() and count operands
14207 unsigned idx0 = 1;
14208 unsigned idx1 = 1; // src
14209 st->print_raw("movd ");
14210 opnd_array(0)->int_format(ra, this, st); // dst
14211 st->print_raw(",");
14212 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14213 st->print_raw("\n\t");
14214 st->print_raw("pshuflw ");
14215 opnd_array(0)->int_format(ra, this, st); // dst
14216 st->print_raw(",");
14217 opnd_array(0)->int_format(ra, this, st); // dst
14218 st->print_raw(",0x00\n\t");
14219 st->print_raw("punpcklqdq ");
14220 opnd_array(0)->int_format(ra, this, st); // dst
14221 st->print_raw(",");
14222 opnd_array(0)->int_format(ra, this, st); // dst
14223 st->print_raw("\t! replicate8S");
14224}
14225#endif
14226#ifndef PRODUCT
14227void Repl8S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14228 // Start at oper_input_base() and count operands
14229 unsigned idx0 = 2;
14230 unsigned idx1 = 2; // mem
14231 st->print_raw("pshuflw ");
14232 opnd_array(0)->int_format(ra, this, st); // dst
14233 st->print_raw(",");
14234 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14235 st->print_raw(",0x00\n\t");
14236 st->print_raw("punpcklqdq ");
14237 opnd_array(0)->int_format(ra, this, st); // dst
14238 st->print_raw(",");
14239 opnd_array(0)->int_format(ra, this, st); // dst
14240 st->print_raw("\t! replicate8S");
14241}
14242#endif
14243#ifndef PRODUCT
14244void Repl8S_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14245 // Start at oper_input_base() and count operands
14246 unsigned idx0 = 1;
14247 unsigned idx1 = 1; // con
14248 st->print_raw("movq ");
14249 opnd_array(0)->int_format(ra, this, st); // dst
14250 st->print_raw(",[");
14251 st->print("constant table base + #%d", constant_offset_unchecked());
14252 st->print_raw("]\n\t");
14253 st->print_raw("punpcklqdq ");
14254 opnd_array(0)->int_format(ra, this, st); // dst
14255 st->print_raw(",");
14256 opnd_array(0)->int_format(ra, this, st); // dst
14257 st->print_raw("\t! replicate8S(");
14258 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14259 st->print_raw(")");
14260}
14261#endif
14262#ifndef PRODUCT
14263void Repl16SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14264 // Start at oper_input_base() and count operands
14265 unsigned idx0 = 1;
14266 unsigned idx1 = 1; // src
14267 st->print_raw("movd ");
14268 opnd_array(0)->int_format(ra, this, st); // dst
14269 st->print_raw(",");
14270 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14271 st->print_raw("\n\t");
14272 st->print_raw("pshuflw ");
14273 opnd_array(0)->int_format(ra, this, st); // dst
14274 st->print_raw(",");
14275 opnd_array(0)->int_format(ra, this, st); // dst
14276 st->print_raw(",0x00\n\t");
14277 st->print_raw("punpcklqdq ");
14278 opnd_array(0)->int_format(ra, this, st); // dst
14279 st->print_raw(",");
14280 opnd_array(0)->int_format(ra, this, st); // dst
14281 st->print_raw("\n\t");
14282 st->print_raw("vinserti128_high ");
14283 opnd_array(0)->int_format(ra, this, st); // dst
14284 st->print_raw(",");
14285 opnd_array(0)->int_format(ra, this, st); // dst
14286 st->print_raw("\t! replicate16S");
14287}
14288#endif
14289#ifndef PRODUCT
14290void Repl16S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14291 // Start at oper_input_base() and count operands
14292 unsigned idx0 = 2;
14293 unsigned idx1 = 2; // mem
14294 st->print_raw("pshuflw ");
14295 opnd_array(0)->int_format(ra, this, st); // dst
14296 st->print_raw(",");
14297 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14298 st->print_raw(",0x00\n\t");
14299 st->print_raw("punpcklqdq ");
14300 opnd_array(0)->int_format(ra, this, st); // dst
14301 st->print_raw(",");
14302 opnd_array(0)->int_format(ra, this, st); // dst
14303 st->print_raw("\n\t");
14304 st->print_raw("vinserti128_high ");
14305 opnd_array(0)->int_format(ra, this, st); // dst
14306 st->print_raw(",");
14307 opnd_array(0)->int_format(ra, this, st); // dst
14308 st->print_raw("\t! replicate16S");
14309}
14310#endif
14311#ifndef PRODUCT
14312void Repl16S_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14313 // Start at oper_input_base() and count operands
14314 unsigned idx0 = 1;
14315 unsigned idx1 = 1; // con
14316 st->print_raw("movq ");
14317 opnd_array(0)->int_format(ra, this, st); // dst
14318 st->print_raw(",[");
14319 st->print("constant table base + #%d", constant_offset_unchecked());
14320 st->print_raw("]\n\t");
14321 st->print_raw("punpcklqdq ");
14322 opnd_array(0)->int_format(ra, this, st); // dst
14323 st->print_raw(",");
14324 opnd_array(0)->int_format(ra, this, st); // dst
14325 st->print_raw("\n\t");
14326 st->print_raw("vinserti128_high ");
14327 opnd_array(0)->int_format(ra, this, st); // dst
14328 st->print_raw(",");
14329 opnd_array(0)->int_format(ra, this, st); // dst
14330 st->print_raw("\t! replicate16S(");
14331 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14332 st->print_raw(")");
14333}
14334#endif
14335#ifndef PRODUCT
14336void Repl32SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14337 // Start at oper_input_base() and count operands
14338 unsigned idx0 = 1;
14339 unsigned idx1 = 1; // src
14340 st->print_raw("movd ");
14341 opnd_array(0)->int_format(ra, this, st); // dst
14342 st->print_raw(",");
14343 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14344 st->print_raw("\n\t");
14345 st->print_raw("pshuflw ");
14346 opnd_array(0)->int_format(ra, this, st); // dst
14347 st->print_raw(",");
14348 opnd_array(0)->int_format(ra, this, st); // dst
14349 st->print_raw(",0x00\n\t");
14350 st->print_raw("punpcklqdq ");
14351 opnd_array(0)->int_format(ra, this, st); // dst
14352 st->print_raw(",");
14353 opnd_array(0)->int_format(ra, this, st); // dst
14354 st->print_raw("\n\t");
14355 st->print_raw("vinserti128_high ");
14356 opnd_array(0)->int_format(ra, this, st); // dst
14357 st->print_raw(",");
14358 opnd_array(0)->int_format(ra, this, st); // dst
14359 st->print_raw("\t");
14360 st->print_raw("vinserti64x4 ");
14361 opnd_array(0)->int_format(ra, this, st); // dst
14362 st->print_raw(",");
14363 opnd_array(0)->int_format(ra, this, st); // dst
14364 st->print_raw(",");
14365 opnd_array(0)->int_format(ra, this, st); // dst
14366 st->print_raw(",0x1\t! replicate32S");
14367}
14368#endif
14369#ifndef PRODUCT
14370void Repl32S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14371 // Start at oper_input_base() and count operands
14372 unsigned idx0 = 2;
14373 unsigned idx1 = 2; // mem
14374 st->print_raw("pshuflw ");
14375 opnd_array(0)->int_format(ra, this, st); // dst
14376 st->print_raw(",");
14377 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14378 st->print_raw(",0x00\n\t");
14379 st->print_raw("punpcklqdq ");
14380 opnd_array(0)->int_format(ra, this, st); // dst
14381 st->print_raw(",");
14382 opnd_array(0)->int_format(ra, this, st); // dst
14383 st->print_raw("\n\t");
14384 st->print_raw("vinserti128_high ");
14385 opnd_array(0)->int_format(ra, this, st); // dst
14386 st->print_raw(",");
14387 opnd_array(0)->int_format(ra, this, st); // dst
14388 st->print_raw("\t");
14389 st->print_raw("vinserti64x4 ");
14390 opnd_array(0)->int_format(ra, this, st); // dst
14391 st->print_raw(",");
14392 opnd_array(0)->int_format(ra, this, st); // dst
14393 st->print_raw(",");
14394 opnd_array(0)->int_format(ra, this, st); // dst
14395 st->print_raw(",0x1\t! replicate32S");
14396}
14397#endif
14398#ifndef PRODUCT
14399void Repl32S_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14400 // Start at oper_input_base() and count operands
14401 unsigned idx0 = 1;
14402 unsigned idx1 = 1; // con
14403 st->print_raw("movq ");
14404 opnd_array(0)->int_format(ra, this, st); // dst
14405 st->print_raw(",[");
14406 st->print("constant table base + #%d", constant_offset_unchecked());
14407 st->print_raw("]\n\t");
14408 st->print_raw("punpcklqdq ");
14409 opnd_array(0)->int_format(ra, this, st); // dst
14410 st->print_raw(",");
14411 opnd_array(0)->int_format(ra, this, st); // dst
14412 st->print_raw("\n\t");
14413 st->print_raw("vinserti128_high ");
14414 opnd_array(0)->int_format(ra, this, st); // dst
14415 st->print_raw(",");
14416 opnd_array(0)->int_format(ra, this, st); // dst
14417 st->print_raw("\t");
14418 st->print_raw("vinserti64x4 ");
14419 opnd_array(0)->int_format(ra, this, st); // dst
14420 st->print_raw(",");
14421 opnd_array(0)->int_format(ra, this, st); // dst
14422 st->print_raw(",");
14423 opnd_array(0)->int_format(ra, this, st); // dst
14424 st->print_raw(",0x1\t! replicate32S(");
14425 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14426 st->print_raw(")");
14427}
14428#endif
14429#ifndef PRODUCT
14430void Repl4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
14431 // Start at oper_input_base() and count operands
14432 unsigned idx0 = 1;
14433 unsigned idx1 = 1; // src
14434 st->print_raw("movd ");
14435 opnd_array(0)->int_format(ra, this, st); // dst
14436 st->print_raw(",");
14437 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14438 st->print_raw("\n\t");
14439 st->print_raw("pshufd ");
14440 opnd_array(0)->int_format(ra, this, st); // dst
14441 st->print_raw(",");
14442 opnd_array(0)->int_format(ra, this, st); // dst
14443 st->print_raw(",0x00\t! replicate4I");
14444}
14445#endif
14446#ifndef PRODUCT
14447void Repl4I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14448 // Start at oper_input_base() and count operands
14449 unsigned idx0 = 2;
14450 unsigned idx1 = 2; // mem
14451 st->print_raw("pshufd ");
14452 opnd_array(0)->int_format(ra, this, st); // dst
14453 st->print_raw(",");
14454 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14455 st->print_raw(",0x00\t! replicate4I");
14456}
14457#endif
14458#ifndef PRODUCT
14459void Repl8INode::format(PhaseRegAlloc *ra, outputStream *st) const {
14460 // Start at oper_input_base() and count operands
14461 unsigned idx0 = 1;
14462 unsigned idx1 = 1; // src
14463 st->print_raw("movd ");
14464 opnd_array(0)->int_format(ra, this, st); // dst
14465 st->print_raw(",");
14466 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14467 st->print_raw("\n\t");
14468 st->print_raw("pshufd ");
14469 opnd_array(0)->int_format(ra, this, st); // dst
14470 st->print_raw(",");
14471 opnd_array(0)->int_format(ra, this, st); // dst
14472 st->print_raw(",0x00\n\t");
14473 st->print_raw("vinserti128_high ");
14474 opnd_array(0)->int_format(ra, this, st); // dst
14475 st->print_raw(",");
14476 opnd_array(0)->int_format(ra, this, st); // dst
14477 st->print_raw("\t! replicate8I");
14478}
14479#endif
14480#ifndef PRODUCT
14481void Repl8I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14482 // Start at oper_input_base() and count operands
14483 unsigned idx0 = 2;
14484 unsigned idx1 = 2; // mem
14485 st->print_raw("pshufd ");
14486 opnd_array(0)->int_format(ra, this, st); // dst
14487 st->print_raw(",");
14488 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14489 st->print_raw(",0x00\n\t");
14490 st->print_raw("vinserti128_high ");
14491 opnd_array(0)->int_format(ra, this, st); // dst
14492 st->print_raw(",");
14493 opnd_array(0)->int_format(ra, this, st); // dst
14494 st->print_raw("\t! replicate8I");
14495}
14496#endif
14497#ifndef PRODUCT
14498void Repl16INode::format(PhaseRegAlloc *ra, outputStream *st) const {
14499 // Start at oper_input_base() and count operands
14500 unsigned idx0 = 1;
14501 unsigned idx1 = 1; // src
14502 st->print_raw("movd ");
14503 opnd_array(0)->int_format(ra, this, st); // dst
14504 st->print_raw(",");
14505 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14506 st->print_raw("\n\t");
14507 st->print_raw("pshufd ");
14508 opnd_array(0)->int_format(ra, this, st); // dst
14509 st->print_raw(",");
14510 opnd_array(0)->int_format(ra, this, st); // dst
14511 st->print_raw(",0x00\n\t");
14512 st->print_raw("vinserti128_high ");
14513 opnd_array(0)->int_format(ra, this, st); // dst
14514 st->print_raw(",");
14515 opnd_array(0)->int_format(ra, this, st); // dst
14516 st->print_raw("\t");
14517 st->print_raw("vinserti64x4 ");
14518 opnd_array(0)->int_format(ra, this, st); // dst
14519 st->print_raw(",");
14520 opnd_array(0)->int_format(ra, this, st); // dst
14521 st->print_raw(",");
14522 opnd_array(0)->int_format(ra, this, st); // dst
14523 st->print_raw(",0x1\t! replicate16I");
14524}
14525#endif
14526#ifndef PRODUCT
14527void Repl16I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14528 // Start at oper_input_base() and count operands
14529 unsigned idx0 = 2;
14530 unsigned idx1 = 2; // mem
14531 st->print_raw("pshufd ");
14532 opnd_array(0)->int_format(ra, this, st); // dst
14533 st->print_raw(",");
14534 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14535 st->print_raw(",0x00\n\t");
14536 st->print_raw("vinserti128_high ");
14537 opnd_array(0)->int_format(ra, this, st); // dst
14538 st->print_raw(",");
14539 opnd_array(0)->int_format(ra, this, st); // dst
14540 st->print_raw("\t");
14541 st->print_raw("vinserti64x4 ");
14542 opnd_array(0)->int_format(ra, this, st); // dst
14543 st->print_raw(",");
14544 opnd_array(0)->int_format(ra, this, st); // dst
14545 st->print_raw(",");
14546 opnd_array(0)->int_format(ra, this, st); // dst
14547 st->print_raw(",0x1\t! replicate16I");
14548}
14549#endif
14550#ifndef PRODUCT
14551void Repl4I_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14552 // Start at oper_input_base() and count operands
14553 unsigned idx0 = 1;
14554 unsigned idx1 = 1; // con
14555 st->print_raw("movq ");
14556 opnd_array(0)->int_format(ra, this, st); // dst
14557 st->print_raw(",[");
14558 st->print("constant table base + #%d", constant_offset_unchecked());
14559 st->print_raw("]\t! replicate4I(");
14560 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14561 st->print_raw(")\n\t");
14562 st->print_raw("punpcklqdq ");
14563 opnd_array(0)->int_format(ra, this, st); // dst
14564 st->print_raw(",");
14565 opnd_array(0)->int_format(ra, this, st); // dst
14566}
14567#endif
14568#ifndef PRODUCT
14569void Repl8I_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14570 // Start at oper_input_base() and count operands
14571 unsigned idx0 = 1;
14572 unsigned idx1 = 1; // con
14573 st->print_raw("movq ");
14574 opnd_array(0)->int_format(ra, this, st); // dst
14575 st->print_raw(",[");
14576 st->print("constant table base + #%d", constant_offset_unchecked());
14577 st->print_raw("]\t! replicate8I(");
14578 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14579 st->print_raw(")\n\t");
14580 st->print_raw("punpcklqdq ");
14581 opnd_array(0)->int_format(ra, this, st); // dst
14582 st->print_raw(",");
14583 opnd_array(0)->int_format(ra, this, st); // dst
14584 st->print_raw("\n\t");
14585 st->print_raw("vinserti128_high ");
14586 opnd_array(0)->int_format(ra, this, st); // dst
14587 st->print_raw(",");
14588 opnd_array(0)->int_format(ra, this, st); // dst
14589}
14590#endif
14591#ifndef PRODUCT
14592void Repl16I_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14593 // Start at oper_input_base() and count operands
14594 unsigned idx0 = 1;
14595 unsigned idx1 = 1; // con
14596 st->print_raw("movq ");
14597 opnd_array(0)->int_format(ra, this, st); // dst
14598 st->print_raw(",[");
14599 st->print("constant table base + #%d", constant_offset_unchecked());
14600 st->print_raw("]\t");
14601 st->print_raw("punpcklqdq ");
14602 opnd_array(0)->int_format(ra, this, st); // dst
14603 st->print_raw(",");
14604 opnd_array(0)->int_format(ra, this, st); // dst
14605 st->print_raw("\n\t");
14606 st->print_raw("vinserti128_high ");
14607 opnd_array(0)->int_format(ra, this, st); // dst
14608 st->print_raw(",");
14609 opnd_array(0)->int_format(ra, this, st); // dst
14610 st->print_raw("vinserti64x4 ");
14611 opnd_array(0)->int_format(ra, this, st); // dst
14612 st->print_raw(",");
14613 opnd_array(0)->int_format(ra, this, st); // dst
14614 st->print_raw(",");
14615 opnd_array(0)->int_format(ra, this, st); // dst
14616 st->print_raw(",0x1\t! replicate16I(");
14617 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14618 st->print_raw(")");
14619}
14620#endif
14621#ifndef PRODUCT
14622void Repl2L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14623 // Start at oper_input_base() and count operands
14624 unsigned idx0 = 2;
14625 unsigned idx1 = 2; // mem
14626 st->print_raw("movq ");
14627 opnd_array(0)->int_format(ra, this, st); // dst
14628 st->print_raw(",");
14629 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14630 st->print_raw("\n\t");
14631 st->print_raw("punpcklqdq ");
14632 opnd_array(0)->int_format(ra, this, st); // dst
14633 st->print_raw(",");
14634 opnd_array(0)->int_format(ra, this, st); // dst
14635 st->print_raw("\t! replicate2L");
14636}
14637#endif
14638#ifndef PRODUCT
14639void Repl4LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14640 // Start at oper_input_base() and count operands
14641 unsigned idx0 = 1;
14642 unsigned idx1 = 1; // src
14643 st->print_raw("movdq ");
14644 opnd_array(0)->int_format(ra, this, st); // dst
14645 st->print_raw(",");
14646 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14647 st->print_raw("\n\t");
14648 st->print_raw("punpcklqdq ");
14649 opnd_array(0)->int_format(ra, this, st); // dst
14650 st->print_raw(",");
14651 opnd_array(0)->int_format(ra, this, st); // dst
14652 st->print_raw("\n\t");
14653 st->print_raw("vinserti128_high ");
14654 opnd_array(0)->int_format(ra, this, st); // dst
14655 st->print_raw(",");
14656 opnd_array(0)->int_format(ra, this, st); // dst
14657 st->print_raw("\t! replicate4L");
14658}
14659#endif
14660#ifndef PRODUCT
14661void Repl8LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14662 // Start at oper_input_base() and count operands
14663 unsigned idx0 = 1;
14664 unsigned idx1 = 1; // src
14665 st->print_raw("movdq ");
14666 opnd_array(0)->int_format(ra, this, st); // dst
14667 st->print_raw(",");
14668 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14669 st->print_raw("\n\t");
14670 st->print_raw("punpcklqdq ");
14671 opnd_array(0)->int_format(ra, this, st); // dst
14672 st->print_raw(",");
14673 opnd_array(0)->int_format(ra, this, st); // dst
14674 st->print_raw("\n\t");
14675 st->print_raw("vinserti128_high ");
14676 opnd_array(0)->int_format(ra, this, st); // dst
14677 st->print_raw(",");
14678 opnd_array(0)->int_format(ra, this, st); // dst
14679 st->print_raw("\t");
14680 st->print_raw("vinserti64x4 ");
14681 opnd_array(0)->int_format(ra, this, st); // dst
14682 st->print_raw(",");
14683 opnd_array(0)->int_format(ra, this, st); // dst
14684 st->print_raw(",");
14685 opnd_array(0)->int_format(ra, this, st); // dst
14686 st->print_raw(",0x1\t! replicate8L");
14687}
14688#endif
14689#ifndef PRODUCT
14690void Repl4L_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14691 // Start at oper_input_base() and count operands
14692 unsigned idx0 = 1;
14693 unsigned idx1 = 1; // con
14694 st->print_raw("movq ");
14695 opnd_array(0)->int_format(ra, this, st); // dst
14696 st->print_raw(",[");
14697 st->print("constant table base + #%d", constant_offset_unchecked());
14698 st->print_raw("]\n\t");
14699 st->print_raw("punpcklqdq ");
14700 opnd_array(0)->int_format(ra, this, st); // dst
14701 st->print_raw(",");
14702 opnd_array(0)->int_format(ra, this, st); // dst
14703 st->print_raw("\n\t");
14704 st->print_raw("vinserti128_high ");
14705 opnd_array(0)->int_format(ra, this, st); // dst
14706 st->print_raw(",");
14707 opnd_array(0)->int_format(ra, this, st); // dst
14708 st->print_raw("\t! replicate4L(");
14709 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14710 st->print_raw(")");
14711}
14712#endif
14713#ifndef PRODUCT
14714void Repl8L_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14715 // Start at oper_input_base() and count operands
14716 unsigned idx0 = 1;
14717 unsigned idx1 = 1; // con
14718 st->print_raw("movq ");
14719 opnd_array(0)->int_format(ra, this, st); // dst
14720 st->print_raw(",[");
14721 st->print("constant table base + #%d", constant_offset_unchecked());
14722 st->print_raw("]\n\t");
14723 st->print_raw("punpcklqdq ");
14724 opnd_array(0)->int_format(ra, this, st); // dst
14725 st->print_raw(",");
14726 opnd_array(0)->int_format(ra, this, st); // dst
14727 st->print_raw("\n\t");
14728 st->print_raw("vinserti128_high ");
14729 opnd_array(0)->int_format(ra, this, st); // dst
14730 st->print_raw(",");
14731 opnd_array(0)->int_format(ra, this, st); // dst
14732 st->print_raw("\t");
14733 st->print_raw("vinserti64x4 ");
14734 opnd_array(0)->int_format(ra, this, st); // dst
14735 st->print_raw(",");
14736 opnd_array(0)->int_format(ra, this, st); // dst
14737 st->print_raw(",");
14738 opnd_array(0)->int_format(ra, this, st); // dst
14739 st->print_raw(",0x1\t! replicate8L(");
14740 opnd_array(1)->ext_format(ra, this,idx1, st); // con
14741 st->print_raw(")");
14742}
14743#endif
14744#ifndef PRODUCT
14745void Repl4L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14746 // Start at oper_input_base() and count operands
14747 unsigned idx0 = 2;
14748 unsigned idx1 = 2; // mem
14749 st->print_raw("movq ");
14750 opnd_array(0)->int_format(ra, this, st); // dst
14751 st->print_raw(",");
14752 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14753 st->print_raw("\n\t");
14754 st->print_raw("punpcklqdq ");
14755 opnd_array(0)->int_format(ra, this, st); // dst
14756 st->print_raw(",");
14757 opnd_array(0)->int_format(ra, this, st); // dst
14758 st->print_raw("\n\t");
14759 st->print_raw("vinserti128_high ");
14760 opnd_array(0)->int_format(ra, this, st); // dst
14761 st->print_raw(",");
14762 opnd_array(0)->int_format(ra, this, st); // dst
14763 st->print_raw("\t! replicate4L");
14764}
14765#endif
14766#ifndef PRODUCT
14767void Repl8L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14768 // Start at oper_input_base() and count operands
14769 unsigned idx0 = 2;
14770 unsigned idx1 = 2; // mem
14771 st->print_raw("movq ");
14772 opnd_array(0)->int_format(ra, this, st); // dst
14773 st->print_raw(",");
14774 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14775 st->print_raw("\n\t");
14776 st->print_raw("punpcklqdq ");
14777 opnd_array(0)->int_format(ra, this, st); // dst
14778 st->print_raw(",");
14779 opnd_array(0)->int_format(ra, this, st); // dst
14780 st->print_raw("\n\t");
14781 st->print_raw("vinserti128_high ");
14782 opnd_array(0)->int_format(ra, this, st); // dst
14783 st->print_raw(",");
14784 opnd_array(0)->int_format(ra, this, st); // dst
14785 st->print_raw("\t");
14786 st->print_raw("vinserti64x4 ");
14787 opnd_array(0)->int_format(ra, this, st); // dst
14788 st->print_raw(",");
14789 opnd_array(0)->int_format(ra, this, st); // dst
14790 st->print_raw(",");
14791 opnd_array(0)->int_format(ra, this, st); // dst
14792 st->print_raw(",0x1\t! replicate8L");
14793}
14794#endif
14795#ifndef PRODUCT
14796void Repl2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14797 // Start at oper_input_base() and count operands
14798 unsigned idx0 = 2;
14799 unsigned idx1 = 2; // mem
14800 st->print_raw("pshufd ");
14801 opnd_array(0)->int_format(ra, this, st); // dst
14802 st->print_raw(",");
14803 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14804 st->print_raw(",0x00\t! replicate2F");
14805}
14806#endif
14807#ifndef PRODUCT
14808void Repl4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14809 // Start at oper_input_base() and count operands
14810 unsigned idx0 = 2;
14811 unsigned idx1 = 2; // mem
14812 st->print_raw("pshufd ");
14813 opnd_array(0)->int_format(ra, this, st); // dst
14814 st->print_raw(",");
14815 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14816 st->print_raw(",0x00\t! replicate4F");
14817}
14818#endif
14819#ifndef PRODUCT
14820void Repl8FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14821 // Start at oper_input_base() and count operands
14822 unsigned idx0 = 1;
14823 unsigned idx1 = 1; // src
14824 st->print_raw("pshufd ");
14825 opnd_array(0)->int_format(ra, this, st); // dst
14826 st->print_raw(",");
14827 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14828 st->print_raw(",0x00\n\t");
14829 st->print_raw("vinsertf128_high ");
14830 opnd_array(0)->int_format(ra, this, st); // dst
14831 st->print_raw(",");
14832 opnd_array(0)->int_format(ra, this, st); // dst
14833 st->print_raw("\t! replicate8F");
14834}
14835#endif
14836#ifndef PRODUCT
14837void Repl8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14838 // Start at oper_input_base() and count operands
14839 unsigned idx0 = 2;
14840 unsigned idx1 = 2; // mem
14841 st->print_raw("pshufd ");
14842 opnd_array(0)->int_format(ra, this, st); // dst
14843 st->print_raw(",");
14844 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14845 st->print_raw(",0x00\n\t");
14846 st->print_raw("vinsertf128_high ");
14847 opnd_array(0)->int_format(ra, this, st); // dst
14848 st->print_raw(",");
14849 opnd_array(0)->int_format(ra, this, st); // dst
14850 st->print_raw("\t! replicate8F");
14851}
14852#endif
14853#ifndef PRODUCT
14854void Repl16FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14855 // Start at oper_input_base() and count operands
14856 unsigned idx0 = 1;
14857 unsigned idx1 = 1; // src
14858 st->print_raw("pshufd ");
14859 opnd_array(0)->int_format(ra, this, st); // dst
14860 st->print_raw(",");
14861 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14862 st->print_raw(",0x00\n\t");
14863 st->print_raw("vinsertf128_high ");
14864 opnd_array(0)->int_format(ra, this, st); // dst
14865 st->print_raw(",");
14866 opnd_array(0)->int_format(ra, this, st); // dst
14867 st->print_raw("\t");
14868 st->print_raw("vinserti64x4 ");
14869 opnd_array(0)->int_format(ra, this, st); // dst
14870 st->print_raw(",");
14871 opnd_array(0)->int_format(ra, this, st); // dst
14872 st->print_raw(",");
14873 opnd_array(0)->int_format(ra, this, st); // dst
14874 st->print_raw(",0x1\t! replicate16F");
14875}
14876#endif
14877#ifndef PRODUCT
14878void Repl16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14879 // Start at oper_input_base() and count operands
14880 unsigned idx0 = 2;
14881 unsigned idx1 = 2; // mem
14882 st->print_raw("pshufd ");
14883 opnd_array(0)->int_format(ra, this, st); // dst
14884 st->print_raw(",");
14885 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14886 st->print_raw(",0x00\n\t");
14887 st->print_raw("vinsertf128_high ");
14888 opnd_array(0)->int_format(ra, this, st); // dst
14889 st->print_raw(",");
14890 opnd_array(0)->int_format(ra, this, st); // dst
14891 st->print_raw("\t");
14892 st->print_raw("vinserti64x4 ");
14893 opnd_array(0)->int_format(ra, this, st); // dst
14894 st->print_raw(",");
14895 opnd_array(0)->int_format(ra, this, st); // dst
14896 st->print_raw(",");
14897 opnd_array(0)->int_format(ra, this, st); // dst
14898 st->print_raw(",0x1\t! replicate16F");
14899}
14900#endif
14901#ifndef PRODUCT
14902void Repl2F_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14903 // Start at oper_input_base() and count operands
14904 unsigned idx0 = 1;
14905 unsigned idx1 = 1; // zero
14906 st->print_raw("xorps ");
14907 opnd_array(0)->int_format(ra, this, st); // dst
14908 st->print_raw(",");
14909 opnd_array(0)->int_format(ra, this, st); // dst
14910 st->print_raw("\t! replicate2F zero");
14911}
14912#endif
14913#ifndef PRODUCT
14914void Repl4F_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14915 // Start at oper_input_base() and count operands
14916 unsigned idx0 = 1;
14917 unsigned idx1 = 1; // zero
14918 st->print_raw("xorps ");
14919 opnd_array(0)->int_format(ra, this, st); // dst
14920 st->print_raw(",");
14921 opnd_array(0)->int_format(ra, this, st); // dst
14922 st->print_raw("\t! replicate4F zero");
14923}
14924#endif
14925#ifndef PRODUCT
14926void Repl8F_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14927 // Start at oper_input_base() and count operands
14928 unsigned idx0 = 1;
14929 unsigned idx1 = 1; // zero
14930 st->print_raw("vxorps ");
14931 opnd_array(0)->int_format(ra, this, st); // dst
14932 st->print_raw(",");
14933 opnd_array(0)->int_format(ra, this, st); // dst
14934 st->print_raw(",");
14935 opnd_array(0)->int_format(ra, this, st); // dst
14936 st->print_raw("\t! replicate8F zero");
14937}
14938#endif
14939#ifndef PRODUCT
14940void Repl2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14941 // Start at oper_input_base() and count operands
14942 unsigned idx0 = 2;
14943 unsigned idx1 = 2; // mem
14944 st->print_raw("pshufd ");
14945 opnd_array(0)->int_format(ra, this, st); // dst
14946 st->print_raw(",");
14947 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14948 st->print_raw(",0x44\t! replicate2D");
14949}
14950#endif
14951#ifndef PRODUCT
14952void Repl4DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14953 // Start at oper_input_base() and count operands
14954 unsigned idx0 = 1;
14955 unsigned idx1 = 1; // src
14956 st->print_raw("pshufd ");
14957 opnd_array(0)->int_format(ra, this, st); // dst
14958 st->print_raw(",");
14959 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14960 st->print_raw(",0x44\n\t");
14961 st->print_raw("vinsertf128_high ");
14962 opnd_array(0)->int_format(ra, this, st); // dst
14963 st->print_raw(",");
14964 opnd_array(0)->int_format(ra, this, st); // dst
14965 st->print_raw("\t! replicate4D");
14966}
14967#endif
14968#ifndef PRODUCT
14969void Repl4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14970 // Start at oper_input_base() and count operands
14971 unsigned idx0 = 2;
14972 unsigned idx1 = 2; // mem
14973 st->print_raw("pshufd ");
14974 opnd_array(0)->int_format(ra, this, st); // dst
14975 st->print_raw(",");
14976 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
14977 st->print_raw(",0x44\n\t");
14978 st->print_raw("vinsertf128_high ");
14979 opnd_array(0)->int_format(ra, this, st); // dst
14980 st->print_raw(",");
14981 opnd_array(0)->int_format(ra, this, st); // dst
14982 st->print_raw("\t! replicate4D");
14983}
14984#endif
14985#ifndef PRODUCT
14986void Repl8DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
14987 // Start at oper_input_base() and count operands
14988 unsigned idx0 = 1;
14989 unsigned idx1 = 1; // src
14990 st->print_raw("pshufd ");
14991 opnd_array(0)->int_format(ra, this, st); // dst
14992 st->print_raw(",");
14993 opnd_array(1)->ext_format(ra, this,idx1, st); // src
14994 st->print_raw(",0x44\n\t");
14995 st->print_raw("vinsertf128_high ");
14996 opnd_array(0)->int_format(ra, this, st); // dst
14997 st->print_raw(",");
14998 opnd_array(0)->int_format(ra, this, st); // dst
14999 st->print_raw("\t");
15000 st->print_raw("vinserti64x4 ");
15001 opnd_array(0)->int_format(ra, this, st); // dst
15002 st->print_raw(",");
15003 opnd_array(0)->int_format(ra, this, st); // dst
15004 st->print_raw(",");
15005 opnd_array(0)->int_format(ra, this, st); // dst
15006 st->print_raw(",0x1\t! replicate8D");
15007}
15008#endif
15009#ifndef PRODUCT
15010void Repl8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15011 // Start at oper_input_base() and count operands
15012 unsigned idx0 = 2;
15013 unsigned idx1 = 2; // mem
15014 st->print_raw("pshufd ");
15015 opnd_array(0)->int_format(ra, this, st); // dst
15016 st->print_raw(",");
15017 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15018 st->print_raw(",0x44\n\t");
15019 st->print_raw("vinsertf128_high ");
15020 opnd_array(0)->int_format(ra, this, st); // dst
15021 st->print_raw(",");
15022 opnd_array(0)->int_format(ra, this, st); // dst
15023 st->print_raw("\t");
15024 st->print_raw("vinserti64x4 ");
15025 opnd_array(0)->int_format(ra, this, st); // dst
15026 st->print_raw(",");
15027 opnd_array(0)->int_format(ra, this, st); // dst
15028 st->print_raw(",");
15029 opnd_array(0)->int_format(ra, this, st); // dst
15030 st->print_raw(",0x1\t! replicate8D");
15031}
15032#endif
15033#ifndef PRODUCT
15034void Repl2D_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15035 // Start at oper_input_base() and count operands
15036 unsigned idx0 = 1;
15037 unsigned idx1 = 1; // zero
15038 st->print_raw("xorpd ");
15039 opnd_array(0)->int_format(ra, this, st); // dst
15040 st->print_raw(",");
15041 opnd_array(0)->int_format(ra, this, st); // dst
15042 st->print_raw("\t! replicate2D zero");
15043}
15044#endif
15045#ifndef PRODUCT
15046void Repl4D_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15047 // Start at oper_input_base() and count operands
15048 unsigned idx0 = 1;
15049 unsigned idx1 = 1; // zero
15050 st->print_raw("vxorpd ");
15051 opnd_array(0)->int_format(ra, this, st); // dst
15052 st->print_raw(",");
15053 opnd_array(0)->int_format(ra, this, st); // dst
15054 st->print_raw(",");
15055 opnd_array(0)->int_format(ra, this, st); // dst
15056 st->print_raw(",vect256\t! replicate4D zero");
15057}
15058#endif
15059#ifndef PRODUCT
15060void Repl4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15061 // Start at oper_input_base() and count operands
15062 unsigned idx0 = 1;
15063 unsigned idx1 = 1; // src
15064 st->print_raw("movd ");
15065 opnd_array(0)->int_format(ra, this, st); // dst
15066 st->print_raw(",");
15067 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15068 st->print_raw("\n\t");
15069 st->print_raw("punpcklbw ");
15070 opnd_array(0)->int_format(ra, this, st); // dst
15071 st->print_raw(",");
15072 opnd_array(0)->int_format(ra, this, st); // dst
15073 st->print_raw("\n\t");
15074 st->print_raw("pshuflw ");
15075 opnd_array(0)->int_format(ra, this, st); // dst
15076 st->print_raw(",");
15077 opnd_array(0)->int_format(ra, this, st); // dst
15078 st->print_raw(",0x00\t! replicate4B");
15079}
15080#endif
15081#ifndef PRODUCT
15082void Repl8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15083 // Start at oper_input_base() and count operands
15084 unsigned idx0 = 1;
15085 unsigned idx1 = 1; // src
15086 st->print_raw("movd ");
15087 opnd_array(0)->int_format(ra, this, st); // dst
15088 st->print_raw(",");
15089 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15090 st->print_raw("\n\t");
15091 st->print_raw("punpcklbw ");
15092 opnd_array(0)->int_format(ra, this, st); // dst
15093 st->print_raw(",");
15094 opnd_array(0)->int_format(ra, this, st); // dst
15095 st->print_raw("\n\t");
15096 st->print_raw("pshuflw ");
15097 opnd_array(0)->int_format(ra, this, st); // dst
15098 st->print_raw(",");
15099 opnd_array(0)->int_format(ra, this, st); // dst
15100 st->print_raw(",0x00\t! replicate8B");
15101}
15102#endif
15103#ifndef PRODUCT
15104void Repl4B_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15105 // Start at oper_input_base() and count operands
15106 unsigned idx0 = 1;
15107 unsigned idx1 = 1; // con
15108 st->print_raw("movdl ");
15109 opnd_array(0)->int_format(ra, this, st); // dst
15110 st->print_raw(",[");
15111 st->print("constant table base + #%d", constant_offset_unchecked());
15112 st->print_raw("]\t! replicate4B(");
15113 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15114 st->print_raw(")");
15115}
15116#endif
15117#ifndef PRODUCT
15118void Repl8B_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15119 // Start at oper_input_base() and count operands
15120 unsigned idx0 = 1;
15121 unsigned idx1 = 1; // con
15122 st->print_raw("movq ");
15123 opnd_array(0)->int_format(ra, this, st); // dst
15124 st->print_raw(",[");
15125 st->print("constant table base + #%d", constant_offset_unchecked());
15126 st->print_raw("]\t! replicate8B(");
15127 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15128 st->print_raw(")");
15129}
15130#endif
15131#ifndef PRODUCT
15132void Repl4B_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15133 // Start at oper_input_base() and count operands
15134 unsigned idx0 = 1;
15135 unsigned idx1 = 1; // zero
15136 st->print_raw("pxor ");
15137 opnd_array(0)->int_format(ra, this, st); // dst
15138 st->print_raw(",");
15139 opnd_array(0)->int_format(ra, this, st); // dst
15140 st->print_raw("\t! replicate4B zero");
15141}
15142#endif
15143#ifndef PRODUCT
15144void Repl8B_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15145 // Start at oper_input_base() and count operands
15146 unsigned idx0 = 1;
15147 unsigned idx1 = 1; // zero
15148 st->print_raw("pxor ");
15149 opnd_array(0)->int_format(ra, this, st); // dst
15150 st->print_raw(",");
15151 opnd_array(0)->int_format(ra, this, st); // dst
15152 st->print_raw("\t! replicate8B zero");
15153}
15154#endif
15155#ifndef PRODUCT
15156void Repl16B_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15157 // Start at oper_input_base() and count operands
15158 unsigned idx0 = 1;
15159 unsigned idx1 = 1; // zero
15160 st->print_raw("pxor ");
15161 opnd_array(0)->int_format(ra, this, st); // dst
15162 st->print_raw(",");
15163 opnd_array(0)->int_format(ra, this, st); // dst
15164 st->print_raw("\t! replicate16B zero");
15165}
15166#endif
15167#ifndef PRODUCT
15168void Repl32B_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15169 // Start at oper_input_base() and count operands
15170 unsigned idx0 = 1;
15171 unsigned idx1 = 1; // zero
15172 st->print_raw("vpxor ");
15173 opnd_array(0)->int_format(ra, this, st); // dst
15174 st->print_raw(",");
15175 opnd_array(0)->int_format(ra, this, st); // dst
15176 st->print_raw(",");
15177 opnd_array(0)->int_format(ra, this, st); // dst
15178 st->print_raw("\t! replicate32B zero");
15179}
15180#endif
15181#ifndef PRODUCT
15182void Repl2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15183 // Start at oper_input_base() and count operands
15184 unsigned idx0 = 1;
15185 unsigned idx1 = 1; // src
15186 st->print_raw("movd ");
15187 opnd_array(0)->int_format(ra, this, st); // dst
15188 st->print_raw(",");
15189 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15190 st->print_raw("\n\t");
15191 st->print_raw("pshuflw ");
15192 opnd_array(0)->int_format(ra, this, st); // dst
15193 st->print_raw(",");
15194 opnd_array(0)->int_format(ra, this, st); // dst
15195 st->print_raw(",0x00\t! replicate2S");
15196}
15197#endif
15198#ifndef PRODUCT
15199void Repl2S_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15200 // Start at oper_input_base() and count operands
15201 unsigned idx0 = 1;
15202 unsigned idx1 = 1; // con
15203 st->print_raw("movdl ");
15204 opnd_array(0)->int_format(ra, this, st); // dst
15205 st->print_raw(",[");
15206 st->print("constant table base + #%d", constant_offset_unchecked());
15207 st->print_raw("]\t! replicate2S(");
15208 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15209 st->print_raw(")");
15210}
15211#endif
15212#ifndef PRODUCT
15213void Repl4S_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15214 // Start at oper_input_base() and count operands
15215 unsigned idx0 = 1;
15216 unsigned idx1 = 1; // con
15217 st->print_raw("movq ");
15218 opnd_array(0)->int_format(ra, this, st); // dst
15219 st->print_raw(",[");
15220 st->print("constant table base + #%d", constant_offset_unchecked());
15221 st->print_raw("]\t! replicate4S(");
15222 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15223 st->print_raw(")");
15224}
15225#endif
15226#ifndef PRODUCT
15227void Repl2S_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15228 // Start at oper_input_base() and count operands
15229 unsigned idx0 = 1;
15230 unsigned idx1 = 1; // zero
15231 st->print_raw("pxor ");
15232 opnd_array(0)->int_format(ra, this, st); // dst
15233 st->print_raw(",");
15234 opnd_array(0)->int_format(ra, this, st); // dst
15235 st->print_raw("\t! replicate2S zero");
15236}
15237#endif
15238#ifndef PRODUCT
15239void Repl4S_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15240 // Start at oper_input_base() and count operands
15241 unsigned idx0 = 1;
15242 unsigned idx1 = 1; // zero
15243 st->print_raw("pxor ");
15244 opnd_array(0)->int_format(ra, this, st); // dst
15245 st->print_raw(",");
15246 opnd_array(0)->int_format(ra, this, st); // dst
15247 st->print_raw("\t! replicate4S zero");
15248}
15249#endif
15250#ifndef PRODUCT
15251void Repl8S_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15252 // Start at oper_input_base() and count operands
15253 unsigned idx0 = 1;
15254 unsigned idx1 = 1; // zero
15255 st->print_raw("pxor ");
15256 opnd_array(0)->int_format(ra, this, st); // dst
15257 st->print_raw(",");
15258 opnd_array(0)->int_format(ra, this, st); // dst
15259 st->print_raw("\t! replicate8S zero");
15260}
15261#endif
15262#ifndef PRODUCT
15263void Repl16S_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15264 // Start at oper_input_base() and count operands
15265 unsigned idx0 = 1;
15266 unsigned idx1 = 1; // zero
15267 st->print_raw("vpxor ");
15268 opnd_array(0)->int_format(ra, this, st); // dst
15269 st->print_raw(",");
15270 opnd_array(0)->int_format(ra, this, st); // dst
15271 st->print_raw(",");
15272 opnd_array(0)->int_format(ra, this, st); // dst
15273 st->print_raw("\t! replicate16S zero");
15274}
15275#endif
15276#ifndef PRODUCT
15277void Repl2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
15278 // Start at oper_input_base() and count operands
15279 unsigned idx0 = 1;
15280 unsigned idx1 = 1; // src
15281 st->print_raw("movd ");
15282 opnd_array(0)->int_format(ra, this, st); // dst
15283 st->print_raw(",");
15284 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15285 st->print_raw("\n\t");
15286 st->print_raw("pshufd ");
15287 opnd_array(0)->int_format(ra, this, st); // dst
15288 st->print_raw(",");
15289 opnd_array(0)->int_format(ra, this, st); // dst
15290 st->print_raw(",0x00\t! replicate2I");
15291}
15292#endif
15293#ifndef PRODUCT
15294void Repl2I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15295 // Start at oper_input_base() and count operands
15296 unsigned idx0 = 2;
15297 unsigned idx1 = 2; // mem
15298 st->print_raw("movd ");
15299 opnd_array(0)->int_format(ra, this, st); // dst
15300 st->print_raw(",");
15301 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15302 st->print_raw("\n\t");
15303 st->print_raw("pshufd ");
15304 opnd_array(0)->int_format(ra, this, st); // dst
15305 st->print_raw(",");
15306 opnd_array(0)->int_format(ra, this, st); // dst
15307 st->print_raw(",0x00\t! replicate2I");
15308}
15309#endif
15310#ifndef PRODUCT
15311void Repl2I_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15312 // Start at oper_input_base() and count operands
15313 unsigned idx0 = 1;
15314 unsigned idx1 = 1; // con
15315 st->print_raw("movq ");
15316 opnd_array(0)->int_format(ra, this, st); // dst
15317 st->print_raw(",[");
15318 st->print("constant table base + #%d", constant_offset_unchecked());
15319 st->print_raw("]\t! replicate2I(");
15320 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15321 st->print_raw(")");
15322}
15323#endif
15324#ifndef PRODUCT
15325void Repl2I_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15326 // Start at oper_input_base() and count operands
15327 unsigned idx0 = 1;
15328 unsigned idx1 = 1; // zero
15329 st->print_raw("pxor ");
15330 opnd_array(0)->int_format(ra, this, st); // dst
15331 st->print_raw(",");
15332 opnd_array(0)->int_format(ra, this, st); // dst
15333 st->print_raw("\t! replicate2I");
15334}
15335#endif
15336#ifndef PRODUCT
15337void Repl4I_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15338 // Start at oper_input_base() and count operands
15339 unsigned idx0 = 1;
15340 unsigned idx1 = 1; // zero
15341 st->print_raw("pxor ");
15342 opnd_array(0)->int_format(ra, this, st); // dst
15343 st->print_raw(",");
15344 opnd_array(0)->int_format(ra, this, st); // dst
15345 st->print_raw("\t! replicate4I zero)");
15346}
15347#endif
15348#ifndef PRODUCT
15349void Repl8I_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15350 // Start at oper_input_base() and count operands
15351 unsigned idx0 = 1;
15352 unsigned idx1 = 1; // zero
15353 st->print_raw("vpxor ");
15354 opnd_array(0)->int_format(ra, this, st); // dst
15355 st->print_raw(",");
15356 opnd_array(0)->int_format(ra, this, st); // dst
15357 st->print_raw(",");
15358 opnd_array(0)->int_format(ra, this, st); // dst
15359 st->print_raw("\t! replicate8I zero");
15360}
15361#endif
15362#ifndef PRODUCT
15363void Repl2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15364 // Start at oper_input_base() and count operands
15365 unsigned idx0 = 1;
15366 unsigned idx1 = 1; // src
15367 st->print_raw("movdq ");
15368 opnd_array(0)->int_format(ra, this, st); // dst
15369 st->print_raw(",");
15370 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15371 st->print_raw("\n\t");
15372 st->print_raw("punpcklqdq ");
15373 opnd_array(0)->int_format(ra, this, st); // dst
15374 st->print_raw(",");
15375 opnd_array(0)->int_format(ra, this, st); // dst
15376 st->print_raw("\t! replicate2L");
15377}
15378#endif
15379#ifndef PRODUCT
15380void Repl2L_immNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15381 // Start at oper_input_base() and count operands
15382 unsigned idx0 = 1;
15383 unsigned idx1 = 1; // con
15384 st->print_raw("movq ");
15385 opnd_array(0)->int_format(ra, this, st); // dst
15386 st->print_raw(",[");
15387 st->print("constant table base + #%d", constant_offset_unchecked());
15388 st->print_raw("]\n\t");
15389 st->print_raw("punpcklqdq ");
15390 opnd_array(0)->int_format(ra, this, st); // dst
15391 st->print_raw(",");
15392 opnd_array(0)->int_format(ra, this, st); // dst
15393 st->print_raw("\t! replicate2L(");
15394 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15395 st->print_raw(")");
15396}
15397#endif
15398#ifndef PRODUCT
15399void Repl2L_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15400 // Start at oper_input_base() and count operands
15401 unsigned idx0 = 1;
15402 unsigned idx1 = 1; // zero
15403 st->print_raw("pxor ");
15404 opnd_array(0)->int_format(ra, this, st); // dst
15405 st->print_raw(",");
15406 opnd_array(0)->int_format(ra, this, st); // dst
15407 st->print_raw("\t! replicate2L zero");
15408}
15409#endif
15410#ifndef PRODUCT
15411void Repl4L_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15412 // Start at oper_input_base() and count operands
15413 unsigned idx0 = 1;
15414 unsigned idx1 = 1; // zero
15415 st->print_raw("vpxor ");
15416 opnd_array(0)->int_format(ra, this, st); // dst
15417 st->print_raw(",");
15418 opnd_array(0)->int_format(ra, this, st); // dst
15419 st->print_raw(",");
15420 opnd_array(0)->int_format(ra, this, st); // dst
15421 st->print_raw("\t! replicate4L zero");
15422}
15423#endif
15424#ifndef PRODUCT
15425void Repl2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15426 // Start at oper_input_base() and count operands
15427 unsigned idx0 = 1;
15428 unsigned idx1 = 1; // src
15429 st->print_raw("pshufd ");
15430 opnd_array(0)->int_format(ra, this, st); // dst
15431 st->print_raw(",");
15432 opnd_array(0)->int_format(ra, this, st); // dst
15433 st->print_raw(",0x00\t! replicate2F");
15434}
15435#endif
15436#ifndef PRODUCT
15437void Repl4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15438 // Start at oper_input_base() and count operands
15439 unsigned idx0 = 1;
15440 unsigned idx1 = 1; // src
15441 st->print_raw("pshufd ");
15442 opnd_array(0)->int_format(ra, this, st); // dst
15443 st->print_raw(",");
15444 opnd_array(0)->int_format(ra, this, st); // dst
15445 st->print_raw(",0x00\t! replicate4F");
15446}
15447#endif
15448#ifndef PRODUCT
15449void Repl2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15450 // Start at oper_input_base() and count operands
15451 unsigned idx0 = 1;
15452 unsigned idx1 = 1; // src
15453 st->print_raw("pshufd ");
15454 opnd_array(0)->int_format(ra, this, st); // dst
15455 st->print_raw(",");
15456 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15457 st->print_raw(",0x44\t! replicate2D");
15458}
15459#endif
15460#ifndef PRODUCT
15461void Repl4B_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15462 // Start at oper_input_base() and count operands
15463 unsigned idx0 = 2;
15464 unsigned idx1 = 2; // mem
15465 st->print_raw("vpbroadcastb ");
15466 opnd_array(0)->int_format(ra, this, st); // dst
15467 st->print_raw(",");
15468 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15469 st->print_raw("\t! replicate4B");
15470}
15471#endif
15472#ifndef PRODUCT
15473void Repl8B_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15474 // Start at oper_input_base() and count operands
15475 unsigned idx0 = 2;
15476 unsigned idx1 = 2; // mem
15477 st->print_raw("vpbroadcastb ");
15478 opnd_array(0)->int_format(ra, this, st); // dst
15479 st->print_raw(",");
15480 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15481 st->print_raw("\t! replicate8B");
15482}
15483#endif
15484#ifndef PRODUCT
15485void Repl16B_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15486 // Start at oper_input_base() and count operands
15487 unsigned idx0 = 1;
15488 unsigned idx1 = 1; // src
15489 st->print_raw("evpbroadcastb ");
15490 opnd_array(0)->int_format(ra, this, st); // dst
15491 st->print_raw(",");
15492 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15493 st->print_raw("\t! replicate16B");
15494}
15495#endif
15496#ifndef PRODUCT
15497void Repl16B_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15498 // Start at oper_input_base() and count operands
15499 unsigned idx0 = 2;
15500 unsigned idx1 = 2; // mem
15501 st->print_raw("vpbroadcastb ");
15502 opnd_array(0)->int_format(ra, this, st); // dst
15503 st->print_raw(",");
15504 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15505 st->print_raw("\t! replicate16B");
15506}
15507#endif
15508#ifndef PRODUCT
15509void Repl32B_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15510 // Start at oper_input_base() and count operands
15511 unsigned idx0 = 1;
15512 unsigned idx1 = 1; // src
15513 st->print_raw("evpbroadcastb ");
15514 opnd_array(0)->int_format(ra, this, st); // dst
15515 st->print_raw(",");
15516 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15517 st->print_raw("\t! replicate32B");
15518}
15519#endif
15520#ifndef PRODUCT
15521void Repl32B_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15522 // Start at oper_input_base() and count operands
15523 unsigned idx0 = 2;
15524 unsigned idx1 = 2; // mem
15525 st->print_raw("vpbroadcastb ");
15526 opnd_array(0)->int_format(ra, this, st); // dst
15527 st->print_raw(",");
15528 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15529 st->print_raw("\t! replicate32B");
15530}
15531#endif
15532#ifndef PRODUCT
15533void Repl64B_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15534 // Start at oper_input_base() and count operands
15535 unsigned idx0 = 1;
15536 unsigned idx1 = 1; // src
15537 st->print_raw("evpbroadcastb ");
15538 opnd_array(0)->int_format(ra, this, st); // dst
15539 st->print_raw(",");
15540 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15541 st->print_raw("\t! upper replicate64B");
15542}
15543#endif
15544#ifndef PRODUCT
15545void Repl64B_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15546 // Start at oper_input_base() and count operands
15547 unsigned idx0 = 2;
15548 unsigned idx1 = 2; // mem
15549 st->print_raw("vpbroadcastb ");
15550 opnd_array(0)->int_format(ra, this, st); // dst
15551 st->print_raw(",");
15552 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15553 st->print_raw("\t! replicate64B");
15554}
15555#endif
15556#ifndef PRODUCT
15557void Repl16B_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15558 // Start at oper_input_base() and count operands
15559 unsigned idx0 = 1;
15560 unsigned idx1 = 1; // con
15561 st->print_raw("movq ");
15562 opnd_array(0)->int_format(ra, this, st); // dst
15563 st->print_raw(",[");
15564 st->print("constant table base + #%d", constant_offset_unchecked());
15565 st->print_raw("]\n\t");
15566 st->print_raw("vpbroadcastb ");
15567 opnd_array(0)->int_format(ra, this, st); // dst
15568 st->print_raw(",");
15569 opnd_array(0)->int_format(ra, this, st); // dst
15570 st->print_raw("\t! replicate16B");
15571}
15572#endif
15573#ifndef PRODUCT
15574void Repl32B_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15575 // Start at oper_input_base() and count operands
15576 unsigned idx0 = 1;
15577 unsigned idx1 = 1; // con
15578 st->print_raw("movq ");
15579 opnd_array(0)->int_format(ra, this, st); // dst
15580 st->print_raw(",[");
15581 st->print("constant table base + #%d", constant_offset_unchecked());
15582 st->print_raw("]\n\t");
15583 st->print_raw("vpbroadcastb ");
15584 opnd_array(0)->int_format(ra, this, st); // dst
15585 st->print_raw(",");
15586 opnd_array(0)->int_format(ra, this, st); // dst
15587 st->print_raw("\t! replicate32B");
15588}
15589#endif
15590#ifndef PRODUCT
15591void Repl64B_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15592 // Start at oper_input_base() and count operands
15593 unsigned idx0 = 1;
15594 unsigned idx1 = 1; // con
15595 st->print_raw("movq ");
15596 opnd_array(0)->int_format(ra, this, st); // dst
15597 st->print_raw(",[");
15598 st->print("constant table base + #%d", constant_offset_unchecked());
15599 st->print_raw("]\n\t");
15600 st->print_raw("vpbroadcastb ");
15601 opnd_array(0)->int_format(ra, this, st); // dst
15602 st->print_raw(",");
15603 opnd_array(0)->int_format(ra, this, st); // dst
15604 st->print_raw("\t! upper replicate64B");
15605}
15606#endif
15607#ifndef PRODUCT
15608void Repl64B_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15609 // Start at oper_input_base() and count operands
15610 unsigned idx0 = 1;
15611 unsigned idx1 = 1; // zero
15612 st->print_raw("vpxor ");
15613 opnd_array(0)->int_format(ra, this, st); // dst
15614 st->print_raw(" k0,");
15615 opnd_array(0)->int_format(ra, this, st); // dst
15616 st->print_raw(",");
15617 opnd_array(0)->int_format(ra, this, st); // dst
15618 st->print_raw("\t! replicate64B zero");
15619}
15620#endif
15621#ifndef PRODUCT
15622void Repl4S_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15623 // Start at oper_input_base() and count operands
15624 unsigned idx0 = 1;
15625 unsigned idx1 = 1; // src
15626 st->print_raw("evpbroadcastw ");
15627 opnd_array(0)->int_format(ra, this, st); // dst
15628 st->print_raw(",");
15629 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15630 st->print_raw("\t! replicate4S");
15631}
15632#endif
15633#ifndef PRODUCT
15634void Repl4S_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15635 // Start at oper_input_base() and count operands
15636 unsigned idx0 = 2;
15637 unsigned idx1 = 2; // mem
15638 st->print_raw("vpbroadcastw ");
15639 opnd_array(0)->int_format(ra, this, st); // dst
15640 st->print_raw(",");
15641 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15642 st->print_raw("\t! replicate4S");
15643}
15644#endif
15645#ifndef PRODUCT
15646void Repl8S_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15647 // Start at oper_input_base() and count operands
15648 unsigned idx0 = 1;
15649 unsigned idx1 = 1; // src
15650 st->print_raw("evpbroadcastw ");
15651 opnd_array(0)->int_format(ra, this, st); // dst
15652 st->print_raw(",");
15653 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15654 st->print_raw("\t! replicate8S");
15655}
15656#endif
15657#ifndef PRODUCT
15658void Repl8S_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15659 // Start at oper_input_base() and count operands
15660 unsigned idx0 = 2;
15661 unsigned idx1 = 2; // mem
15662 st->print_raw("vpbroadcastw ");
15663 opnd_array(0)->int_format(ra, this, st); // dst
15664 st->print_raw(",");
15665 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15666 st->print_raw("\t! replicate8S");
15667}
15668#endif
15669#ifndef PRODUCT
15670void Repl16S_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15671 // Start at oper_input_base() and count operands
15672 unsigned idx0 = 1;
15673 unsigned idx1 = 1; // src
15674 st->print_raw("evpbroadcastw ");
15675 opnd_array(0)->int_format(ra, this, st); // dst
15676 st->print_raw(",");
15677 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15678 st->print_raw("\t! replicate16S");
15679}
15680#endif
15681#ifndef PRODUCT
15682void Repl16S_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15683 // Start at oper_input_base() and count operands
15684 unsigned idx0 = 2;
15685 unsigned idx1 = 2; // mem
15686 st->print_raw("vpbroadcastw ");
15687 opnd_array(0)->int_format(ra, this, st); // dst
15688 st->print_raw(",");
15689 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15690 st->print_raw("\t! replicate16S");
15691}
15692#endif
15693#ifndef PRODUCT
15694void Repl32S_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15695 // Start at oper_input_base() and count operands
15696 unsigned idx0 = 1;
15697 unsigned idx1 = 1; // src
15698 st->print_raw("evpbroadcastw ");
15699 opnd_array(0)->int_format(ra, this, st); // dst
15700 st->print_raw(",");
15701 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15702 st->print_raw("\t! replicate32S");
15703}
15704#endif
15705#ifndef PRODUCT
15706void Repl32S_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15707 // Start at oper_input_base() and count operands
15708 unsigned idx0 = 2;
15709 unsigned idx1 = 2; // mem
15710 st->print_raw("vpbroadcastw ");
15711 opnd_array(0)->int_format(ra, this, st); // dst
15712 st->print_raw(",");
15713 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15714 st->print_raw("\t! replicate32S");
15715}
15716#endif
15717#ifndef PRODUCT
15718void Repl8S_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15719 // Start at oper_input_base() and count operands
15720 unsigned idx0 = 1;
15721 unsigned idx1 = 1; // con
15722 st->print_raw("movq ");
15723 opnd_array(0)->int_format(ra, this, st); // dst
15724 st->print_raw(",[");
15725 st->print("constant table base + #%d", constant_offset_unchecked());
15726 st->print_raw("]\n\t");
15727 st->print_raw("vpbroadcastw ");
15728 opnd_array(0)->int_format(ra, this, st); // dst
15729 st->print_raw(",");
15730 opnd_array(0)->int_format(ra, this, st); // dst
15731 st->print_raw("\t! replicate8S");
15732}
15733#endif
15734#ifndef PRODUCT
15735void Repl16S_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15736 // Start at oper_input_base() and count operands
15737 unsigned idx0 = 1;
15738 unsigned idx1 = 1; // con
15739 st->print_raw("movq ");
15740 opnd_array(0)->int_format(ra, this, st); // dst
15741 st->print_raw(",[");
15742 st->print("constant table base + #%d", constant_offset_unchecked());
15743 st->print_raw("]\n\t");
15744 st->print_raw("vpbroadcastw ");
15745 opnd_array(0)->int_format(ra, this, st); // dst
15746 st->print_raw(",");
15747 opnd_array(0)->int_format(ra, this, st); // dst
15748 st->print_raw("\t! replicate16S");
15749}
15750#endif
15751#ifndef PRODUCT
15752void Repl32S_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15753 // Start at oper_input_base() and count operands
15754 unsigned idx0 = 1;
15755 unsigned idx1 = 1; // con
15756 st->print_raw("movq ");
15757 opnd_array(0)->int_format(ra, this, st); // dst
15758 st->print_raw(",[");
15759 st->print("constant table base + #%d", constant_offset_unchecked());
15760 st->print_raw("]\n\t");
15761 st->print_raw("vpbroadcastw ");
15762 opnd_array(0)->int_format(ra, this, st); // dst
15763 st->print_raw(",");
15764 opnd_array(0)->int_format(ra, this, st); // dst
15765 st->print_raw("\t! replicate32S");
15766}
15767#endif
15768#ifndef PRODUCT
15769void Repl32S_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15770 // Start at oper_input_base() and count operands
15771 unsigned idx0 = 1;
15772 unsigned idx1 = 1; // zero
15773 st->print_raw("vpxor ");
15774 opnd_array(0)->int_format(ra, this, st); // dst
15775 st->print_raw(" k0,");
15776 opnd_array(0)->int_format(ra, this, st); // dst
15777 st->print_raw(",");
15778 opnd_array(0)->int_format(ra, this, st); // dst
15779 st->print_raw("\t! replicate32S zero");
15780}
15781#endif
15782#ifndef PRODUCT
15783void Repl4I_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15784 // Start at oper_input_base() and count operands
15785 unsigned idx0 = 1;
15786 unsigned idx1 = 1; // src
15787 st->print_raw("evpbroadcastd ");
15788 opnd_array(0)->int_format(ra, this, st); // dst
15789 st->print_raw(",");
15790 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15791 st->print_raw("\t! replicate4I");
15792}
15793#endif
15794#ifndef PRODUCT
15795void Repl4I_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15796 // Start at oper_input_base() and count operands
15797 unsigned idx0 = 2;
15798 unsigned idx1 = 2; // mem
15799 st->print_raw("vpbroadcastd ");
15800 opnd_array(0)->int_format(ra, this, st); // dst
15801 st->print_raw(",");
15802 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15803 st->print_raw("\t! replicate4I");
15804}
15805#endif
15806#ifndef PRODUCT
15807void Repl8I_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15808 // Start at oper_input_base() and count operands
15809 unsigned idx0 = 1;
15810 unsigned idx1 = 1; // src
15811 st->print_raw("evpbroadcastd ");
15812 opnd_array(0)->int_format(ra, this, st); // dst
15813 st->print_raw(",");
15814 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15815 st->print_raw("\t! replicate8I");
15816}
15817#endif
15818#ifndef PRODUCT
15819void Repl8I_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15820 // Start at oper_input_base() and count operands
15821 unsigned idx0 = 2;
15822 unsigned idx1 = 2; // mem
15823 st->print_raw("vpbroadcastd ");
15824 opnd_array(0)->int_format(ra, this, st); // dst
15825 st->print_raw(",");
15826 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15827 st->print_raw("\t! replicate8I");
15828}
15829#endif
15830#ifndef PRODUCT
15831void Repl16I_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15832 // Start at oper_input_base() and count operands
15833 unsigned idx0 = 1;
15834 unsigned idx1 = 1; // src
15835 st->print_raw("evpbroadcastd ");
15836 opnd_array(0)->int_format(ra, this, st); // dst
15837 st->print_raw(",");
15838 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15839 st->print_raw("\t! replicate16I");
15840}
15841#endif
15842#ifndef PRODUCT
15843void Repl16I_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15844 // Start at oper_input_base() and count operands
15845 unsigned idx0 = 2;
15846 unsigned idx1 = 2; // mem
15847 st->print_raw("vpbroadcastd ");
15848 opnd_array(0)->int_format(ra, this, st); // dst
15849 st->print_raw(",");
15850 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15851 st->print_raw("\t! replicate16I");
15852}
15853#endif
15854#ifndef PRODUCT
15855void Repl4I_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15856 // Start at oper_input_base() and count operands
15857 unsigned idx0 = 1;
15858 unsigned idx1 = 1; // con
15859 st->print_raw("movq ");
15860 opnd_array(0)->int_format(ra, this, st); // dst
15861 st->print_raw(",[");
15862 st->print("constant table base + #%d", constant_offset_unchecked());
15863 st->print_raw("]\t! replicate8I(");
15864 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15865 st->print_raw(")\n\t");
15866 st->print_raw("vpbroadcastd ");
15867 opnd_array(0)->int_format(ra, this, st); // dst
15868 st->print_raw(",");
15869 opnd_array(0)->int_format(ra, this, st); // dst
15870 st->print_raw("\t! replicate4I");
15871}
15872#endif
15873#ifndef PRODUCT
15874void Repl8I_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15875 // Start at oper_input_base() and count operands
15876 unsigned idx0 = 1;
15877 unsigned idx1 = 1; // con
15878 st->print_raw("movq ");
15879 opnd_array(0)->int_format(ra, this, st); // dst
15880 st->print_raw(",[");
15881 st->print("constant table base + #%d", constant_offset_unchecked());
15882 st->print_raw("]\t! replicate8I(");
15883 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15884 st->print_raw(")\n\t");
15885 st->print_raw("vpbroadcastd ");
15886 opnd_array(0)->int_format(ra, this, st); // dst
15887 st->print_raw(",");
15888 opnd_array(0)->int_format(ra, this, st); // dst
15889 st->print_raw("\t! replicate8I");
15890}
15891#endif
15892#ifndef PRODUCT
15893void Repl16I_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15894 // Start at oper_input_base() and count operands
15895 unsigned idx0 = 1;
15896 unsigned idx1 = 1; // con
15897 st->print_raw("movq ");
15898 opnd_array(0)->int_format(ra, this, st); // dst
15899 st->print_raw(",[");
15900 st->print("constant table base + #%d", constant_offset_unchecked());
15901 st->print_raw("]\t! replicate16I(");
15902 opnd_array(1)->ext_format(ra, this,idx1, st); // con
15903 st->print_raw(")\n\t");
15904 st->print_raw("vpbroadcastd ");
15905 opnd_array(0)->int_format(ra, this, st); // dst
15906 st->print_raw(",");
15907 opnd_array(0)->int_format(ra, this, st); // dst
15908 st->print_raw("\t! replicate16I");
15909}
15910#endif
15911#ifndef PRODUCT
15912void Repl16I_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15913 // Start at oper_input_base() and count operands
15914 unsigned idx0 = 1;
15915 unsigned idx1 = 1; // zero
15916 st->print_raw("vpxor ");
15917 opnd_array(0)->int_format(ra, this, st); // dst
15918 st->print_raw(" k0,");
15919 opnd_array(0)->int_format(ra, this, st); // dst
15920 st->print_raw(",");
15921 opnd_array(0)->int_format(ra, this, st); // dst
15922 st->print_raw("\t! replicate16I zero");
15923}
15924#endif
15925#ifndef PRODUCT
15926void Repl4L_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15927 // Start at oper_input_base() and count operands
15928 unsigned idx0 = 1;
15929 unsigned idx1 = 1; // src
15930 st->print_raw("evpbroadcastq ");
15931 opnd_array(0)->int_format(ra, this, st); // dst
15932 st->print_raw(",");
15933 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15934 st->print_raw("\t! replicate4L");
15935}
15936#endif
15937#ifndef PRODUCT
15938void Repl8L_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15939 // Start at oper_input_base() and count operands
15940 unsigned idx0 = 1;
15941 unsigned idx1 = 1; // src
15942 st->print_raw("evpbroadcastq ");
15943 opnd_array(0)->int_format(ra, this, st); // dst
15944 st->print_raw(",");
15945 opnd_array(1)->ext_format(ra, this,idx1, st); // src
15946 st->print_raw("\t! replicate8L");
15947}
15948#endif
15949#ifndef PRODUCT
15950void Repl4L_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15951 // Start at oper_input_base() and count operands
15952 unsigned idx0 = 1;
15953 unsigned idx1 = 1; // con
15954 st->print_raw("movq ");
15955 opnd_array(0)->int_format(ra, this, st); // dst
15956 st->print_raw(",[");
15957 st->print("constant table base + #%d", constant_offset_unchecked());
15958 st->print_raw("]\n\t");
15959 st->print_raw("vpbroadcastq ");
15960 opnd_array(0)->int_format(ra, this, st); // dst
15961 st->print_raw(",");
15962 opnd_array(0)->int_format(ra, this, st); // dst
15963 st->print_raw("\t! replicate4L");
15964}
15965#endif
15966#ifndef PRODUCT
15967void Repl8L_imm_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15968 // Start at oper_input_base() and count operands
15969 unsigned idx0 = 1;
15970 unsigned idx1 = 1; // con
15971 st->print_raw("movq ");
15972 opnd_array(0)->int_format(ra, this, st); // dst
15973 st->print_raw(",[");
15974 st->print("constant table base + #%d", constant_offset_unchecked());
15975 st->print_raw("]\n\t");
15976 st->print_raw("vpbroadcastq ");
15977 opnd_array(0)->int_format(ra, this, st); // dst
15978 st->print_raw(",");
15979 opnd_array(0)->int_format(ra, this, st); // dst
15980 st->print_raw("\t! replicate8L");
15981}
15982#endif
15983#ifndef PRODUCT
15984void Repl2L_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15985 // Start at oper_input_base() and count operands
15986 unsigned idx0 = 2;
15987 unsigned idx1 = 2; // mem
15988 st->print_raw("vpbroadcastd ");
15989 opnd_array(0)->int_format(ra, this, st); // dst
15990 st->print_raw(",");
15991 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
15992 st->print_raw("\t! replicate2L");
15993}
15994#endif
15995#ifndef PRODUCT
15996void Repl4L_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
15997 // Start at oper_input_base() and count operands
15998 unsigned idx0 = 2;
15999 unsigned idx1 = 2; // mem
16000 st->print_raw("vpbroadcastd ");
16001 opnd_array(0)->int_format(ra, this, st); // dst
16002 st->print_raw(",");
16003 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16004 st->print_raw("\t! replicate4L");
16005}
16006#endif
16007#ifndef PRODUCT
16008void Repl8L_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16009 // Start at oper_input_base() and count operands
16010 unsigned idx0 = 2;
16011 unsigned idx1 = 2; // mem
16012 st->print_raw("vpbroadcastd ");
16013 opnd_array(0)->int_format(ra, this, st); // dst
16014 st->print_raw(",");
16015 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16016 st->print_raw("\t! replicate8L");
16017}
16018#endif
16019#ifndef PRODUCT
16020void Repl8L_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16021 // Start at oper_input_base() and count operands
16022 unsigned idx0 = 1;
16023 unsigned idx1 = 1; // zero
16024 st->print_raw("vpxor ");
16025 opnd_array(0)->int_format(ra, this, st); // dst
16026 st->print_raw(" k0,");
16027 opnd_array(0)->int_format(ra, this, st); // dst
16028 st->print_raw(",");
16029 opnd_array(0)->int_format(ra, this, st); // dst
16030 st->print_raw("\t! replicate8L zero");
16031}
16032#endif
16033#ifndef PRODUCT
16034void Repl8F_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16035 // Start at oper_input_base() and count operands
16036 unsigned idx0 = 1;
16037 unsigned idx1 = 1; // src
16038 st->print_raw("vpbroadcastss ");
16039 opnd_array(0)->int_format(ra, this, st); // dst
16040 st->print_raw(",");
16041 opnd_array(1)->ext_format(ra, this,idx1, st); // src
16042 st->print_raw("\t! replicate8F");
16043}
16044#endif
16045#ifndef PRODUCT
16046void Repl8F_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16047 // Start at oper_input_base() and count operands
16048 unsigned idx0 = 2;
16049 unsigned idx1 = 2; // mem
16050 st->print_raw("vbroadcastss ");
16051 opnd_array(0)->int_format(ra, this, st); // dst
16052 st->print_raw(",");
16053 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16054 st->print_raw("\t! replicate8F");
16055}
16056#endif
16057#ifndef PRODUCT
16058void Repl16F_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16059 // Start at oper_input_base() and count operands
16060 unsigned idx0 = 1;
16061 unsigned idx1 = 1; // src
16062 st->print_raw("vpbroadcastss ");
16063 opnd_array(0)->int_format(ra, this, st); // dst
16064 st->print_raw(",");
16065 opnd_array(1)->ext_format(ra, this,idx1, st); // src
16066 st->print_raw("\t! replicate16F");
16067}
16068#endif
16069#ifndef PRODUCT
16070void Repl16F_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16071 // Start at oper_input_base() and count operands
16072 unsigned idx0 = 2;
16073 unsigned idx1 = 2; // mem
16074 st->print_raw("vbroadcastss ");
16075 opnd_array(0)->int_format(ra, this, st); // dst
16076 st->print_raw(",");
16077 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16078 st->print_raw("\t! replicate16F");
16079}
16080#endif
16081#ifndef PRODUCT
16082void Repl2F_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16083 // Start at oper_input_base() and count operands
16084 unsigned idx0 = 1;
16085 unsigned idx1 = 1; // zero
16086 st->print_raw("vpxor ");
16087 opnd_array(0)->int_format(ra, this, st); // dst
16088 st->print_raw(" k0,");
16089 opnd_array(0)->int_format(ra, this, st); // dst
16090 st->print_raw(",");
16091 opnd_array(0)->int_format(ra, this, st); // dst
16092 st->print_raw("\t! replicate2F zero");
16093}
16094#endif
16095#ifndef PRODUCT
16096void Repl4F_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16097 // Start at oper_input_base() and count operands
16098 unsigned idx0 = 1;
16099 unsigned idx1 = 1; // zero
16100 st->print_raw("vpxor ");
16101 opnd_array(0)->int_format(ra, this, st); // dst
16102 st->print_raw(" k0,");
16103 opnd_array(0)->int_format(ra, this, st); // dst
16104 st->print_raw(",");
16105 opnd_array(0)->int_format(ra, this, st); // dst
16106 st->print_raw("\t! replicate4F zero");
16107}
16108#endif
16109#ifndef PRODUCT
16110void Repl8F_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16111 // Start at oper_input_base() and count operands
16112 unsigned idx0 = 1;
16113 unsigned idx1 = 1; // zero
16114 st->print_raw("vpxor ");
16115 opnd_array(0)->int_format(ra, this, st); // dst
16116 st->print_raw(" k0,");
16117 opnd_array(0)->int_format(ra, this, st); // dst
16118 st->print_raw(",");
16119 opnd_array(0)->int_format(ra, this, st); // dst
16120 st->print_raw("\t! replicate8F zero");
16121}
16122#endif
16123#ifndef PRODUCT
16124void Repl16F_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16125 // Start at oper_input_base() and count operands
16126 unsigned idx0 = 1;
16127 unsigned idx1 = 1; // zero
16128 st->print_raw("vpxor ");
16129 opnd_array(0)->int_format(ra, this, st); // dst
16130 st->print_raw(" k0,");
16131 opnd_array(0)->int_format(ra, this, st); // dst
16132 st->print_raw(",");
16133 opnd_array(0)->int_format(ra, this, st); // dst
16134 st->print_raw("\t! replicate16F zero");
16135}
16136#endif
16137#ifndef PRODUCT
16138void Repl4D_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16139 // Start at oper_input_base() and count operands
16140 unsigned idx0 = 1;
16141 unsigned idx1 = 1; // src
16142 st->print_raw("vpbroadcastsd ");
16143 opnd_array(0)->int_format(ra, this, st); // dst
16144 st->print_raw(",");
16145 opnd_array(1)->ext_format(ra, this,idx1, st); // src
16146 st->print_raw("\t! replicate4D");
16147}
16148#endif
16149#ifndef PRODUCT
16150void Repl4D_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16151 // Start at oper_input_base() and count operands
16152 unsigned idx0 = 2;
16153 unsigned idx1 = 2; // mem
16154 st->print_raw("vbroadcastsd ");
16155 opnd_array(0)->int_format(ra, this, st); // dst
16156 st->print_raw(",");
16157 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16158 st->print_raw("\t! replicate4D");
16159}
16160#endif
16161#ifndef PRODUCT
16162void Repl8D_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16163 // Start at oper_input_base() and count operands
16164 unsigned idx0 = 1;
16165 unsigned idx1 = 1; // src
16166 st->print_raw("vpbroadcastsd ");
16167 opnd_array(0)->int_format(ra, this, st); // dst
16168 st->print_raw(",");
16169 opnd_array(1)->ext_format(ra, this,idx1, st); // src
16170 st->print_raw("\t! replicate8D");
16171}
16172#endif
16173#ifndef PRODUCT
16174void Repl8D_mem_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16175 // Start at oper_input_base() and count operands
16176 unsigned idx0 = 2;
16177 unsigned idx1 = 2; // mem
16178 st->print_raw("vbroadcastsd ");
16179 opnd_array(0)->int_format(ra, this, st); // dst
16180 st->print_raw(",");
16181 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
16182 st->print_raw("\t! replicate8D");
16183}
16184#endif
16185#ifndef PRODUCT
16186void Repl2D_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16187 // Start at oper_input_base() and count operands
16188 unsigned idx0 = 1;
16189 unsigned idx1 = 1; // zero
16190 st->print_raw("vpxor ");
16191 opnd_array(0)->int_format(ra, this, st); // dst
16192 st->print_raw(" k0,");
16193 opnd_array(0)->int_format(ra, this, st); // dst
16194 st->print_raw(",");
16195 opnd_array(0)->int_format(ra, this, st); // dst
16196 st->print_raw("\t! replicate2D zero");
16197}
16198#endif
16199#ifndef PRODUCT
16200void Repl4D_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16201 // Start at oper_input_base() and count operands
16202 unsigned idx0 = 1;
16203 unsigned idx1 = 1; // zero
16204 st->print_raw("vpxor ");
16205 opnd_array(0)->int_format(ra, this, st); // dst
16206 st->print_raw(" k0,");
16207 opnd_array(0)->int_format(ra, this, st); // dst
16208 st->print_raw(",");
16209 opnd_array(0)->int_format(ra, this, st); // dst
16210 st->print_raw("\t! replicate4D zero");
16211}
16212#endif
16213#ifndef PRODUCT
16214void Repl8D_zero_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16215 // Start at oper_input_base() and count operands
16216 unsigned idx0 = 1;
16217 unsigned idx1 = 1; // zero
16218 st->print_raw("vpxor ");
16219 opnd_array(0)->int_format(ra, this, st); // dst
16220 st->print_raw(" k0,");
16221 opnd_array(0)->int_format(ra, this, st); // dst
16222 st->print_raw(",");
16223 opnd_array(0)->int_format(ra, this, st); // dst
16224 st->print_raw(",vect512\t! replicate8D zero");
16225}
16226#endif
16227#ifndef PRODUCT
16228void rsadd2I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16229 // Start at oper_input_base() and count operands
16230 unsigned idx0 = 1;
16231 unsigned idx1 = 1; // src1
16232 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16233 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16234 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16235 st->print_raw("movdqu ");
16236 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16237 st->print_raw(",");
16238 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16239 st->print_raw("\n\t");
16240 st->print_raw("phaddd ");
16241 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16242 st->print_raw(",");
16243 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16244 st->print_raw("\n\t");
16245 st->print_raw("movd ");
16246 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16247 st->print_raw(",");
16248 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16249 st->print_raw("\n\t");
16250 st->print_raw("paddd ");
16251 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16252 st->print_raw(",");
16253 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16254 st->print_raw("\n\t");
16255 st->print_raw("movd ");
16256 opnd_array(0)->int_format(ra, this, st); // dst
16257 st->print_raw(",");
16258 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16259 st->print_raw("\t! add reduction2I");
16260}
16261#endif
16262#ifndef PRODUCT
16263void rvadd2I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16264 // Start at oper_input_base() and count operands
16265 unsigned idx0 = 1;
16266 unsigned idx1 = 1; // src1
16267 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16268 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16269 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16270 st->print_raw("vphaddd ");
16271 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16272 st->print_raw(",");
16273 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16274 st->print_raw(",");
16275 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16276 st->print_raw("\n\t");
16277 st->print_raw("movd ");
16278 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16279 st->print_raw(",");
16280 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16281 st->print_raw("\n\t");
16282 st->print_raw("vpaddd ");
16283 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16284 st->print_raw(",");
16285 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16286 st->print_raw(",");
16287 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16288 st->print_raw("\n\t");
16289 st->print_raw("movd ");
16290 opnd_array(0)->int_format(ra, this, st); // dst
16291 st->print_raw(",");
16292 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16293 st->print_raw("\t! add reduction2I");
16294}
16295#endif
16296#ifndef PRODUCT
16297void rvadd2I_reduction_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16298 // Start at oper_input_base() and count operands
16299 unsigned idx0 = 1;
16300 unsigned idx1 = 1; // src1
16301 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16302 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16303 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16304 st->print_raw("pshufd ");
16305 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16306 st->print_raw(",");
16307 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16308 st->print_raw(",0x1\n\t");
16309 st->print_raw("vpaddd ");
16310 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16311 st->print_raw(",");
16312 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16313 st->print_raw(",");
16314 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16315 st->print_raw("\n\t");
16316 st->print_raw("movd ");
16317 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16318 st->print_raw(",");
16319 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16320 st->print_raw("\n\t");
16321 st->print_raw("vpaddd ");
16322 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16323 st->print_raw(",");
16324 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16325 st->print_raw(",");
16326 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16327 st->print_raw("\n\t");
16328 st->print_raw("movd ");
16329 opnd_array(0)->int_format(ra, this, st); // dst
16330 st->print_raw(",");
16331 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16332 st->print_raw("\t! add reduction2I");
16333}
16334#endif
16335#ifndef PRODUCT
16336void rsadd4I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16337 // Start at oper_input_base() and count operands
16338 unsigned idx0 = 1;
16339 unsigned idx1 = 1; // src1
16340 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16341 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16342 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16343 st->print_raw("movdqu ");
16344 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16345 st->print_raw(",");
16346 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16347 st->print_raw("\n\t");
16348 st->print_raw("phaddd ");
16349 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16350 st->print_raw(",");
16351 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16352 st->print_raw("\n\t");
16353 st->print_raw("phaddd ");
16354 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16355 st->print_raw(",");
16356 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16357 st->print_raw("\n\t");
16358 st->print_raw("movd ");
16359 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16360 st->print_raw(",");
16361 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16362 st->print_raw("\n\t");
16363 st->print_raw("paddd ");
16364 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16365 st->print_raw(",");
16366 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16367 st->print_raw("\n\t");
16368 st->print_raw("movd ");
16369 opnd_array(0)->int_format(ra, this, st); // dst
16370 st->print_raw(",");
16371 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16372 st->print_raw("\t! add reduction4I");
16373}
16374#endif
16375#ifndef PRODUCT
16376void rvadd4I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16377 // Start at oper_input_base() and count operands
16378 unsigned idx0 = 1;
16379 unsigned idx1 = 1; // src1
16380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16381 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16382 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16383 st->print_raw("vphaddd ");
16384 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16385 st->print_raw(",");
16386 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16387 st->print_raw(",");
16388 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16389 st->print_raw("\n\t");
16390 st->print_raw("vphaddd ");
16391 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16392 st->print_raw(",");
16393 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16394 st->print_raw(",");
16395 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16396 st->print_raw("\n\t");
16397 st->print_raw("movd ");
16398 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16399 st->print_raw(",");
16400 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16401 st->print_raw("\n\t");
16402 st->print_raw("vpaddd ");
16403 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16404 st->print_raw(",");
16405 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16406 st->print_raw(",");
16407 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16408 st->print_raw("\n\t");
16409 st->print_raw("movd ");
16410 opnd_array(0)->int_format(ra, this, st); // dst
16411 st->print_raw(",");
16412 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16413 st->print_raw("\t! add reduction4I");
16414}
16415#endif
16416#ifndef PRODUCT
16417void rvadd4I_reduction_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16418 // Start at oper_input_base() and count operands
16419 unsigned idx0 = 1;
16420 unsigned idx1 = 1; // src1
16421 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16422 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16423 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16424 st->print_raw("pshufd ");
16425 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16426 st->print_raw(",");
16427 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16428 st->print_raw(",0xE\n\t");
16429 st->print_raw("vpaddd ");
16430 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16431 st->print_raw(",");
16432 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16433 st->print_raw(",");
16434 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16435 st->print_raw("\n\t");
16436 st->print_raw("pshufd ");
16437 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16438 st->print_raw(",");
16439 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16440 st->print_raw(",0x1\n\t");
16441 st->print_raw("vpaddd ");
16442 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16443 st->print_raw(",");
16444 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16445 st->print_raw(",");
16446 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16447 st->print_raw("\n\t");
16448 st->print_raw("movd ");
16449 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16450 st->print_raw(",");
16451 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16452 st->print_raw("\n\t");
16453 st->print_raw("vpaddd ");
16454 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16455 st->print_raw(",");
16456 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16457 st->print_raw(",");
16458 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16459 st->print_raw("\n\t");
16460 st->print_raw("movd ");
16461 opnd_array(0)->int_format(ra, this, st); // dst
16462 st->print_raw(",");
16463 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16464 st->print_raw("\t! add reduction4I");
16465}
16466#endif
16467#ifndef PRODUCT
16468void rvadd8I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16469 // Start at oper_input_base() and count operands
16470 unsigned idx0 = 1;
16471 unsigned idx1 = 1; // src1
16472 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16473 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16474 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16475 st->print_raw("vphaddd ");
16476 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16477 st->print_raw(",");
16478 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16479 st->print_raw(",");
16480 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16481 st->print_raw("\n\t");
16482 st->print_raw("vphaddd ");
16483 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16484 st->print_raw(",");
16485 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16486 st->print_raw(",");
16487 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16488 st->print_raw("\n\t");
16489 st->print_raw("vextracti128_high ");
16490 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16491 st->print_raw(",");
16492 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16493 st->print_raw("\n\t");
16494 st->print_raw("vpaddd ");
16495 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16496 st->print_raw(",");
16497 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16498 st->print_raw(",");
16499 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16500 st->print_raw("\n\t");
16501 st->print_raw("movd ");
16502 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16503 st->print_raw(",");
16504 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16505 st->print_raw("\n\t");
16506 st->print_raw("vpaddd ");
16507 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16508 st->print_raw(",");
16509 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16510 st->print_raw(",");
16511 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16512 st->print_raw("\n\t");
16513 st->print_raw("movd ");
16514 opnd_array(0)->int_format(ra, this, st); // dst
16515 st->print_raw(",");
16516 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16517 st->print_raw("\t! add reduction8I");
16518}
16519#endif
16520#ifndef PRODUCT
16521void rvadd8I_reduction_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16522 // Start at oper_input_base() and count operands
16523 unsigned idx0 = 1;
16524 unsigned idx1 = 1; // src1
16525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16526 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16527 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16528 st->print_raw("vextracti128_high ");
16529 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16530 st->print_raw(",");
16531 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16532 st->print_raw("\n\t");
16533 st->print_raw("vpaddd ");
16534 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16535 st->print_raw(",");
16536 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16537 st->print_raw(",");
16538 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16539 st->print_raw("\n\t");
16540 st->print_raw("pshufd ");
16541 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16542 st->print_raw(",");
16543 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16544 st->print_raw(",0xE\n\t");
16545 st->print_raw("vpaddd ");
16546 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16547 st->print_raw(",");
16548 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16549 st->print_raw(",");
16550 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16551 st->print_raw("\n\t");
16552 st->print_raw("pshufd ");
16553 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16554 st->print_raw(",");
16555 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16556 st->print_raw(",0x1\n\t");
16557 st->print_raw("vpaddd ");
16558 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16559 st->print_raw(",");
16560 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16561 st->print_raw(",");
16562 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16563 st->print_raw("\n\t");
16564 st->print_raw("movd ");
16565 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16566 st->print_raw(",");
16567 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16568 st->print_raw("\n\t");
16569 st->print_raw("vpaddd ");
16570 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16571 st->print_raw(",");
16572 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16573 st->print_raw(",");
16574 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16575 st->print_raw("\n\t");
16576 st->print_raw("movd ");
16577 opnd_array(0)->int_format(ra, this, st); // dst
16578 st->print_raw(",");
16579 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16580 st->print_raw("\t! add reduction8I");
16581}
16582#endif
16583#ifndef PRODUCT
16584void rvadd16I_reduction_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16585 // Start at oper_input_base() and count operands
16586 unsigned idx0 = 1;
16587 unsigned idx1 = 1; // src1
16588 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16589 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16590 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16591 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
16592 st->print_raw("vextracti64x4_high ");
16593 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
16594 st->print_raw(",");
16595 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16596 st->print_raw("\n\t");
16597 st->print_raw("vpaddd ");
16598 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
16599 st->print_raw(",");
16600 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
16601 st->print_raw(",");
16602 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16603 st->print_raw("\n\t");
16604 st->print_raw("vextracti128_high ");
16605 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16606 st->print_raw(",");
16607 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
16608 st->print_raw("\n\t");
16609 st->print_raw("vpaddd ");
16610 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16611 st->print_raw(",");
16612 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16613 st->print_raw(",");
16614 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
16615 st->print_raw("\n\t");
16616 st->print_raw("pshufd ");
16617 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16618 st->print_raw(",");
16619 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16620 st->print_raw(",0xE\n\t");
16621 st->print_raw("vpaddd ");
16622 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16623 st->print_raw(",");
16624 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16625 st->print_raw(",");
16626 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16627 st->print_raw("\n\t");
16628 st->print_raw("pshufd ");
16629 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16630 st->print_raw(",");
16631 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16632 st->print_raw(",0x1\n\t");
16633 st->print_raw("vpaddd ");
16634 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16635 st->print_raw(",");
16636 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16637 st->print_raw(",");
16638 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16639 st->print_raw("\n\t");
16640 st->print_raw("movd ");
16641 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16642 st->print_raw(",");
16643 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16644 st->print_raw("\n\t");
16645 st->print_raw("vpaddd ");
16646 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16647 st->print_raw(",");
16648 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16649 st->print_raw(",");
16650 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16651 st->print_raw("\n\t");
16652 st->print_raw("movd ");
16653 opnd_array(0)->int_format(ra, this, st); // dst
16654 st->print_raw(",");
16655 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16656 st->print_raw("\t! mul reduction16I");
16657}
16658#endif
16659#ifndef PRODUCT
16660void rvadd2L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16661 // Start at oper_input_base() and count operands
16662 unsigned idx0 = 1;
16663 unsigned idx1 = 1; // src1
16664 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16665 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16666 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16667 st->print_raw("pshufd ");
16668 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16669 st->print_raw(",");
16670 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16671 st->print_raw(",0xE\n\t");
16672 st->print_raw("vpaddq ");
16673 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16674 st->print_raw(",");
16675 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16676 st->print_raw(",");
16677 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16678 st->print_raw("\n\t");
16679 st->print_raw("movdq ");
16680 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16681 st->print_raw(",");
16682 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16683 st->print_raw("\n\t");
16684 st->print_raw("vpaddq ");
16685 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16686 st->print_raw(",");
16687 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16688 st->print_raw(",");
16689 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16690 st->print_raw("\n\t");
16691 st->print_raw("movdq ");
16692 opnd_array(0)->int_format(ra, this, st); // dst
16693 st->print_raw(",");
16694 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16695 st->print_raw("\t! add reduction2L");
16696}
16697#endif
16698#ifndef PRODUCT
16699void rvadd4L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16700 // Start at oper_input_base() and count operands
16701 unsigned idx0 = 1;
16702 unsigned idx1 = 1; // src1
16703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16704 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16705 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16706 st->print_raw("vextracti128_high ");
16707 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16708 st->print_raw(",");
16709 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16710 st->print_raw("\n\t");
16711 st->print_raw("vpaddq ");
16712 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16713 st->print_raw(",");
16714 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16715 st->print_raw(",");
16716 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16717 st->print_raw("\n\t");
16718 st->print_raw("pshufd ");
16719 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16720 st->print_raw(",");
16721 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16722 st->print_raw(",0xE\n\t");
16723 st->print_raw("vpaddq ");
16724 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16725 st->print_raw(",");
16726 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16727 st->print_raw(",");
16728 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16729 st->print_raw("\n\t");
16730 st->print_raw("movdq ");
16731 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16732 st->print_raw(",");
16733 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16734 st->print_raw("\n\t");
16735 st->print_raw("vpaddq ");
16736 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16737 st->print_raw(",");
16738 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16739 st->print_raw(",");
16740 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16741 st->print_raw("\n\t");
16742 st->print_raw("movdq ");
16743 opnd_array(0)->int_format(ra, this, st); // dst
16744 st->print_raw(",");
16745 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16746 st->print_raw("\t! add reduction4L");
16747}
16748#endif
16749#ifndef PRODUCT
16750void rvadd8L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16751 // Start at oper_input_base() and count operands
16752 unsigned idx0 = 1;
16753 unsigned idx1 = 1; // src1
16754 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16755 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16756 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16757 st->print_raw("vextracti64x4_high ");
16758 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16759 st->print_raw(",");
16760 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16761 st->print_raw("\n\t");
16762 st->print_raw("vpaddq ");
16763 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16764 st->print_raw(",");
16765 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16766 st->print_raw(",");
16767 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16768 st->print_raw("\n\t");
16769 st->print_raw("vextracti128_high ");
16770 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16771 st->print_raw(",");
16772 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16773 st->print_raw("\n\t");
16774 st->print_raw("vpaddq ");
16775 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16776 st->print_raw(",");
16777 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16778 st->print_raw(",");
16779 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16780 st->print_raw("\n\t");
16781 st->print_raw("pshufd ");
16782 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16783 st->print_raw(",");
16784 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16785 st->print_raw(",0xE\n\t");
16786 st->print_raw("vpaddq ");
16787 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16788 st->print_raw(",");
16789 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16790 st->print_raw(",");
16791 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16792 st->print_raw("\n\t");
16793 st->print_raw("movdq ");
16794 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16795 st->print_raw(",");
16796 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
16797 st->print_raw("\n\t");
16798 st->print_raw("vpaddq ");
16799 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16800 st->print_raw(",");
16801 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16802 st->print_raw(",");
16803 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16804 st->print_raw("\n\t");
16805 st->print_raw("movdq ");
16806 opnd_array(0)->int_format(ra, this, st); // dst
16807 st->print_raw(",");
16808 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
16809 st->print_raw("\t! add reduction8L");
16810}
16811#endif
16812#ifndef PRODUCT
16813void rsadd2F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16814 // Start at oper_input_base() and count operands
16815 unsigned idx0 = 1;
16816 unsigned idx1 = 1; // dst
16817 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16818 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16819 st->print_raw("addss ");
16820 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16821 st->print_raw(",");
16822 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16823 st->print_raw("\n\t");
16824 st->print_raw("pshufd ");
16825 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16826 st->print_raw(",");
16827 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16828 st->print_raw(",0x01\n\t");
16829 st->print_raw("addss ");
16830 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16831 st->print_raw(",");
16832 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16833 st->print_raw("\t! add reduction2F");
16834}
16835#endif
16836#ifndef PRODUCT
16837void rvadd2F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16838 // Start at oper_input_base() and count operands
16839 unsigned idx0 = 1;
16840 unsigned idx1 = 1; // dst
16841 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16842 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16843 st->print_raw("vaddss ");
16844 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16845 st->print_raw(",");
16846 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16847 st->print_raw(",");
16848 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16849 st->print_raw("\n\t");
16850 st->print_raw("pshufd ");
16851 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16852 st->print_raw(",");
16853 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16854 st->print_raw(",0x01\n\t");
16855 st->print_raw("vaddss ");
16856 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16857 st->print_raw(",");
16858 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16859 st->print_raw(",");
16860 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16861 st->print_raw("\t! add reduction2F");
16862}
16863#endif
16864#ifndef PRODUCT
16865void rsadd4F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16866 // Start at oper_input_base() and count operands
16867 unsigned idx0 = 1;
16868 unsigned idx1 = 1; // dst
16869 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16870 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16871 st->print_raw("addss ");
16872 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16873 st->print_raw(",");
16874 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16875 st->print_raw("\n\t");
16876 st->print_raw("pshufd ");
16877 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16878 st->print_raw(",");
16879 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16880 st->print_raw(",0x01\n\t");
16881 st->print_raw("addss ");
16882 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16883 st->print_raw(",");
16884 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16885 st->print_raw("\n\t");
16886 st->print_raw("pshufd ");
16887 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16888 st->print_raw(",");
16889 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16890 st->print_raw(",0x02\n\t");
16891 st->print_raw("addss ");
16892 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16893 st->print_raw(",");
16894 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16895 st->print_raw("\n\t");
16896 st->print_raw("pshufd ");
16897 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16898 st->print_raw(",");
16899 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16900 st->print_raw(",0x03\n\t");
16901 st->print_raw("addss ");
16902 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16903 st->print_raw(",");
16904 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16905 st->print_raw("\t! add reduction4F");
16906}
16907#endif
16908#ifndef PRODUCT
16909void rvadd4F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16910 // Start at oper_input_base() and count operands
16911 unsigned idx0 = 1;
16912 unsigned idx1 = 1; // dst
16913 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16914 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16915 st->print_raw("vaddss ");
16916 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16917 st->print_raw(",dst,");
16918 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16919 st->print_raw("\n\t");
16920 st->print_raw("pshufd ");
16921 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16922 st->print_raw(",");
16923 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16924 st->print_raw(",0x01\n\t");
16925 st->print_raw("vaddss ");
16926 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16927 st->print_raw(",");
16928 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16929 st->print_raw(",");
16930 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16931 st->print_raw("\n\t");
16932 st->print_raw("pshufd ");
16933 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16934 st->print_raw(",");
16935 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16936 st->print_raw(",0x02\n\t");
16937 st->print_raw("vaddss ");
16938 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16939 st->print_raw(",");
16940 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16941 st->print_raw(",");
16942 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16943 st->print_raw("\n\t");
16944 st->print_raw("pshufd ");
16945 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16946 st->print_raw(",");
16947 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16948 st->print_raw(",0x03\n\t");
16949 st->print_raw("vaddss ");
16950 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16951 st->print_raw(",");
16952 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16953 st->print_raw(",");
16954 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16955 st->print_raw("\t! add reduction4F");
16956}
16957#endif
16958#ifndef PRODUCT
16959void radd8F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
16960 // Start at oper_input_base() and count operands
16961 unsigned idx0 = 1;
16962 unsigned idx1 = 1; // dst
16963 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
16964 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
16965 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
16966 st->print_raw("vaddss ");
16967 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16968 st->print_raw(",");
16969 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16970 st->print_raw(",");
16971 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16972 st->print_raw("\n\t");
16973 st->print_raw("pshufd ");
16974 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16975 st->print_raw(",");
16976 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16977 st->print_raw(",0x01\n\t");
16978 st->print_raw("vaddss ");
16979 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16980 st->print_raw(",");
16981 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16982 st->print_raw(",");
16983 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16984 st->print_raw("\n\t");
16985 st->print_raw("pshufd ");
16986 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16987 st->print_raw(",");
16988 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
16989 st->print_raw(",0x02\n\t");
16990 st->print_raw("vaddss ");
16991 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16992 st->print_raw(",");
16993 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
16994 st->print_raw(",");
16995 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16996 st->print_raw("\n\t");
16997 st->print_raw("pshufd ");
16998 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
16999 st->print_raw(",");
17000 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17001 st->print_raw(",0x03\n\t");
17002 st->print_raw("vaddss ");
17003 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17004 st->print_raw(",");
17005 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17006 st->print_raw(",");
17007 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17008 st->print_raw("\n\t");
17009 st->print_raw("vextractf128_high ");
17010 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17011 st->print_raw(",");
17012 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17013 st->print_raw("\n\t");
17014 st->print_raw("vaddss ");
17015 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17016 st->print_raw(",");
17017 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17018 st->print_raw(",");
17019 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17020 st->print_raw("\n\t");
17021 st->print_raw("pshufd ");
17022 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17023 st->print_raw(",");
17024 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17025 st->print_raw(",0x01\n\t");
17026 st->print_raw("vaddss ");
17027 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17028 st->print_raw(",");
17029 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17030 st->print_raw(",");
17031 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17032 st->print_raw("\n\t");
17033 st->print_raw("pshufd ");
17034 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17035 st->print_raw(",");
17036 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17037 st->print_raw(",0x02\n\t");
17038 st->print_raw("vaddss ");
17039 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17040 st->print_raw(",");
17041 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17042 st->print_raw(",");
17043 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17044 st->print_raw("\n\t");
17045 st->print_raw("pshufd ");
17046 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17047 st->print_raw(",");
17048 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17049 st->print_raw(",0x03\n\t");
17050 st->print_raw("vaddss ");
17051 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17052 st->print_raw(",");
17053 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17054 st->print_raw(",");
17055 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17056 st->print_raw("\t! add reduction8F");
17057}
17058#endif
17059#ifndef PRODUCT
17060void radd16F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17061 // Start at oper_input_base() and count operands
17062 unsigned idx0 = 1;
17063 unsigned idx1 = 1; // dst
17064 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17065 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17066 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17067 st->print_raw("vaddss ");
17068 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17069 st->print_raw(",");
17070 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17071 st->print_raw(",");
17072 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17073 st->print_raw("\n\t");
17074 st->print_raw("pshufd ");
17075 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17076 st->print_raw(",");
17077 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17078 st->print_raw(",0x01\n\t");
17079 st->print_raw("vaddss ");
17080 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17081 st->print_raw(",");
17082 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17083 st->print_raw(",");
17084 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17085 st->print_raw("\n\t");
17086 st->print_raw("pshufd ");
17087 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17088 st->print_raw(",");
17089 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17090 st->print_raw(",0x02\n\t");
17091 st->print_raw("vaddss ");
17092 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17093 st->print_raw(",");
17094 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17095 st->print_raw(",");
17096 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17097 st->print_raw("\n\t");
17098 st->print_raw("pshufd ");
17099 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17100 st->print_raw(",");
17101 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17102 st->print_raw(",0x03\n\t");
17103 st->print_raw("vaddss ");
17104 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17105 st->print_raw(",");
17106 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17107 st->print_raw(",");
17108 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17109 st->print_raw("\n\t");
17110 st->print_raw("vextractf32x4 ");
17111 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17112 st->print_raw(",");
17113 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17114 st->print_raw(",0x1\n\t");
17115 st->print_raw("vaddss ");
17116 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17117 st->print_raw(",");
17118 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17119 st->print_raw(",");
17120 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17121 st->print_raw("\n\t");
17122 st->print_raw("pshufd ");
17123 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17124 st->print_raw(",");
17125 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17126 st->print_raw(",0x01\n\t");
17127 st->print_raw("vaddss ");
17128 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17129 st->print_raw(",");
17130 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17131 st->print_raw(",");
17132 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17133 st->print_raw("\n\t");
17134 st->print_raw("pshufd ");
17135 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17136 st->print_raw(",");
17137 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17138 st->print_raw(",0x02\n\t");
17139 st->print_raw("vaddss ");
17140 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17141 st->print_raw(",");
17142 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17143 st->print_raw(",");
17144 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17145 st->print_raw("\n\t");
17146 st->print_raw("pshufd ");
17147 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17148 st->print_raw(",");
17149 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17150 st->print_raw(",0x03\n\t");
17151 st->print_raw("vaddss ");
17152 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17153 st->print_raw(",");
17154 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17155 st->print_raw(",");
17156 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17157 st->print_raw("\n\t");
17158 st->print_raw("vextractf32x4 ");
17159 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17160 st->print_raw(",");
17161 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17162 st->print_raw(",0x2\n\t");
17163 st->print_raw("vaddss ");
17164 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17165 st->print_raw(",");
17166 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17167 st->print_raw(",");
17168 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17169 st->print_raw("\n\t");
17170 st->print_raw("pshufd ");
17171 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17172 st->print_raw(",");
17173 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17174 st->print_raw(",0x01\n\t");
17175 st->print_raw("vaddss ");
17176 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17177 st->print_raw(",");
17178 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17179 st->print_raw(",");
17180 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17181 st->print_raw("\n\t");
17182 st->print_raw("pshufd ");
17183 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17184 st->print_raw(",");
17185 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17186 st->print_raw(",0x02\n\t");
17187 st->print_raw("vaddss ");
17188 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17189 st->print_raw(",");
17190 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17191 st->print_raw(",");
17192 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17193 st->print_raw("\n\t");
17194 st->print_raw("pshufd ");
17195 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17196 st->print_raw(",");
17197 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17198 st->print_raw(",0x03\n\t");
17199 st->print_raw("vaddss ");
17200 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17201 st->print_raw(",");
17202 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17203 st->print_raw(",");
17204 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17205 st->print_raw("\n\t");
17206 st->print_raw("vextractf32x4 ");
17207 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17208 st->print_raw(",");
17209 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17210 st->print_raw(",0x3\n\t");
17211 st->print_raw("vaddss ");
17212 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17213 st->print_raw(",");
17214 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17215 st->print_raw(",");
17216 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17217 st->print_raw("\n\t");
17218 st->print_raw("pshufd ");
17219 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17220 st->print_raw(",");
17221 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17222 st->print_raw(",0x01\n\t");
17223 st->print_raw("vaddss ");
17224 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17225 st->print_raw(",");
17226 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17227 st->print_raw(",");
17228 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17229 st->print_raw("\n\t");
17230 st->print_raw("pshufd ");
17231 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17232 st->print_raw(",");
17233 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17234 st->print_raw(",0x02\n\t");
17235 st->print_raw("vaddss ");
17236 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17237 st->print_raw(",");
17238 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17239 st->print_raw(",");
17240 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17241 st->print_raw("\n\t");
17242 st->print_raw("pshufd ");
17243 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17244 st->print_raw(",");
17245 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17246 st->print_raw(",0x03\n\t");
17247 st->print_raw("vaddss ");
17248 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17249 st->print_raw(",");
17250 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17251 st->print_raw(",");
17252 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17253 st->print_raw("\t! add reduction16F");
17254}
17255#endif
17256#ifndef PRODUCT
17257void rsadd2D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17258 // Start at oper_input_base() and count operands
17259 unsigned idx0 = 1;
17260 unsigned idx1 = 1; // dst
17261 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17262 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17263 st->print_raw("addsd ");
17264 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17265 st->print_raw(",");
17266 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17267 st->print_raw("\n\t");
17268 st->print_raw("pshufd ");
17269 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17270 st->print_raw(",");
17271 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17272 st->print_raw(",0xE\n\t");
17273 st->print_raw("addsd ");
17274 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17275 st->print_raw(",");
17276 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17277 st->print_raw("\t! add reduction2D");
17278}
17279#endif
17280#ifndef PRODUCT
17281void rvadd2D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17282 // Start at oper_input_base() and count operands
17283 unsigned idx0 = 1;
17284 unsigned idx1 = 1; // dst
17285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17286 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17287 st->print_raw("vaddsd ");
17288 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17289 st->print_raw(",");
17290 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17291 st->print_raw(",");
17292 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17293 st->print_raw("\n\t");
17294 st->print_raw("pshufd ");
17295 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17296 st->print_raw(",");
17297 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17298 st->print_raw(",0xE\n\t");
17299 st->print_raw("vaddsd ");
17300 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17301 st->print_raw(",");
17302 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17303 st->print_raw(",");
17304 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17305 st->print_raw("\t! add reduction2D");
17306}
17307#endif
17308#ifndef PRODUCT
17309void rvadd4D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17310 // Start at oper_input_base() and count operands
17311 unsigned idx0 = 1;
17312 unsigned idx1 = 1; // dst
17313 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17314 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17315 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17316 st->print_raw("vaddsd ");
17317 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17318 st->print_raw(",");
17319 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17320 st->print_raw(",");
17321 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17322 st->print_raw("\n\t");
17323 st->print_raw("pshufd ");
17324 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17325 st->print_raw(",");
17326 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17327 st->print_raw(",0xE\n\t");
17328 st->print_raw("vaddsd ");
17329 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17330 st->print_raw(",");
17331 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17332 st->print_raw(",");
17333 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17334 st->print_raw("\n\t");
17335 st->print_raw("vextractf128 ");
17336 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17337 st->print_raw(",");
17338 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17339 st->print_raw(",0x1\n\t");
17340 st->print_raw("vaddsd ");
17341 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17342 st->print_raw(",");
17343 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17344 st->print_raw(",");
17345 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17346 st->print_raw("\n\t");
17347 st->print_raw("pshufd ");
17348 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17349 st->print_raw(",");
17350 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17351 st->print_raw(",0xE\n\t");
17352 st->print_raw("vaddsd ");
17353 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17354 st->print_raw(",");
17355 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17356 st->print_raw(",");
17357 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17358 st->print_raw("\t! add reduction4D");
17359}
17360#endif
17361#ifndef PRODUCT
17362void rvadd8D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17363 // Start at oper_input_base() and count operands
17364 unsigned idx0 = 1;
17365 unsigned idx1 = 1; // dst
17366 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17367 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17368 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17369 st->print_raw("vaddsd ");
17370 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17371 st->print_raw(",");
17372 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17373 st->print_raw(",");
17374 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17375 st->print_raw("\n\t");
17376 st->print_raw("pshufd ");
17377 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17378 st->print_raw(",");
17379 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17380 st->print_raw(",0xE\n\t");
17381 st->print_raw("vaddsd ");
17382 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17383 st->print_raw(",");
17384 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17385 st->print_raw(",");
17386 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17387 st->print_raw("\n\t");
17388 st->print_raw("vextractf32x4 ");
17389 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17390 st->print_raw(",");
17391 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17392 st->print_raw(",0x1\n\t");
17393 st->print_raw("vaddsd ");
17394 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17395 st->print_raw(",");
17396 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17397 st->print_raw(",");
17398 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17399 st->print_raw("\n\t");
17400 st->print_raw("pshufd ");
17401 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17402 st->print_raw(",");
17403 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17404 st->print_raw(",0xE\n\t");
17405 st->print_raw("vaddsd ");
17406 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17407 st->print_raw(",");
17408 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17409 st->print_raw(",");
17410 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17411 st->print_raw("\n\t");
17412 st->print_raw("vextractf32x4 ");
17413 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17414 st->print_raw(",");
17415 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17416 st->print_raw(",0x2\n\t");
17417 st->print_raw("vaddsd ");
17418 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17419 st->print_raw(",");
17420 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17421 st->print_raw(",");
17422 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17423 st->print_raw("\n\t");
17424 st->print_raw("pshufd ");
17425 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17426 st->print_raw(",");
17427 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17428 st->print_raw(",0xE\n\t");
17429 st->print_raw("vaddsd ");
17430 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17431 st->print_raw(",");
17432 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17433 st->print_raw(",");
17434 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17435 st->print_raw("\n\t");
17436 st->print_raw("vextractf32x4 ");
17437 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17438 st->print_raw(",");
17439 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17440 st->print_raw(",0x3\n\t");
17441 st->print_raw("vaddsd ");
17442 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17443 st->print_raw(",");
17444 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17445 st->print_raw(",");
17446 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17447 st->print_raw("\n\t");
17448 st->print_raw("pshufd ");
17449 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17450 st->print_raw(",");
17451 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17452 st->print_raw(",0xE\n\t");
17453 st->print_raw("vaddsd ");
17454 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17455 st->print_raw(",");
17456 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17457 st->print_raw(",");
17458 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17459 st->print_raw("\t! add reduction8D");
17460}
17461#endif
17462#ifndef PRODUCT
17463void rsmul2I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17464 // Start at oper_input_base() and count operands
17465 unsigned idx0 = 1;
17466 unsigned idx1 = 1; // src1
17467 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17468 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17469 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17470 st->print_raw("pshufd ");
17471 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17472 st->print_raw(",");
17473 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17474 st->print_raw(",0x1\n\t");
17475 st->print_raw("pmulld ");
17476 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17477 st->print_raw(",");
17478 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17479 st->print_raw("\n\t");
17480 st->print_raw("movd ");
17481 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17482 st->print_raw(",");
17483 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17484 st->print_raw("\n\t");
17485 st->print_raw("pmulld ");
17486 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17487 st->print_raw(",");
17488 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17489 st->print_raw("\n\t");
17490 st->print_raw("movd ");
17491 opnd_array(0)->int_format(ra, this, st); // dst
17492 st->print_raw(",");
17493 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17494 st->print_raw("\t! mul reduction2I");
17495}
17496#endif
17497#ifndef PRODUCT
17498void rvmul2I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17499 // Start at oper_input_base() and count operands
17500 unsigned idx0 = 1;
17501 unsigned idx1 = 1; // src1
17502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17503 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17504 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17505 st->print_raw("pshufd ");
17506 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17507 st->print_raw(",");
17508 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17509 st->print_raw(",0x1\n\t");
17510 st->print_raw("vpmulld ");
17511 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17512 st->print_raw(",");
17513 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17514 st->print_raw(",");
17515 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17516 st->print_raw("\n\t");
17517 st->print_raw("movd ");
17518 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17519 st->print_raw(",");
17520 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17521 st->print_raw("\n\t");
17522 st->print_raw("vpmulld ");
17523 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17524 st->print_raw(",");
17525 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17526 st->print_raw(",");
17527 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17528 st->print_raw("\n\t");
17529 st->print_raw("movd ");
17530 opnd_array(0)->int_format(ra, this, st); // dst
17531 st->print_raw(",");
17532 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17533 st->print_raw("\t! mul reduction2I");
17534}
17535#endif
17536#ifndef PRODUCT
17537void rsmul4I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17538 // Start at oper_input_base() and count operands
17539 unsigned idx0 = 1;
17540 unsigned idx1 = 1; // src1
17541 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17542 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17543 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17544 st->print_raw("pshufd ");
17545 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17546 st->print_raw(",");
17547 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17548 st->print_raw(",0xE\n\t");
17549 st->print_raw("pmulld ");
17550 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17551 st->print_raw(",");
17552 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17553 st->print_raw("\n\t");
17554 st->print_raw("pshufd ");
17555 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17556 st->print_raw(",");
17557 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17558 st->print_raw(",0x1\n\t");
17559 st->print_raw("pmulld ");
17560 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17561 st->print_raw(",");
17562 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17563 st->print_raw("\n\t");
17564 st->print_raw("movd ");
17565 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17566 st->print_raw(",");
17567 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17568 st->print_raw("\n\t");
17569 st->print_raw("pmulld ");
17570 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17571 st->print_raw(",");
17572 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17573 st->print_raw("\n\t");
17574 st->print_raw("movd ");
17575 opnd_array(0)->int_format(ra, this, st); // dst
17576 st->print_raw(",");
17577 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17578 st->print_raw("\t! mul reduction4I");
17579}
17580#endif
17581#ifndef PRODUCT
17582void rvmul4I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17583 // Start at oper_input_base() and count operands
17584 unsigned idx0 = 1;
17585 unsigned idx1 = 1; // src1
17586 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17587 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17588 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17589 st->print_raw("pshufd ");
17590 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17591 st->print_raw(",");
17592 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17593 st->print_raw(",0xE\n\t");
17594 st->print_raw("vpmulld ");
17595 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17596 st->print_raw(",");
17597 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17598 st->print_raw(",");
17599 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17600 st->print_raw("\n\t");
17601 st->print_raw("pshufd ");
17602 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17603 st->print_raw(",");
17604 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17605 st->print_raw(",0x1\n\t");
17606 st->print_raw("vpmulld ");
17607 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17608 st->print_raw(",");
17609 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17610 st->print_raw(",");
17611 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17612 st->print_raw("\n\t");
17613 st->print_raw("movd ");
17614 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17615 st->print_raw(",");
17616 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17617 st->print_raw("\n\t");
17618 st->print_raw("vpmulld ");
17619 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17620 st->print_raw(",");
17621 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17622 st->print_raw(",");
17623 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17624 st->print_raw("\n\t");
17625 st->print_raw("movd ");
17626 opnd_array(0)->int_format(ra, this, st); // dst
17627 st->print_raw(",");
17628 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17629 st->print_raw("\t! mul reduction4I");
17630}
17631#endif
17632#ifndef PRODUCT
17633void rvmul8I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17634 // Start at oper_input_base() and count operands
17635 unsigned idx0 = 1;
17636 unsigned idx1 = 1; // src1
17637 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17638 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17639 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17640 st->print_raw("vextracti128_high ");
17641 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17642 st->print_raw(",");
17643 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17644 st->print_raw("\n\t");
17645 st->print_raw("vpmulld ");
17646 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17647 st->print_raw(",");
17648 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17649 st->print_raw(",");
17650 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17651 st->print_raw("\n\t");
17652 st->print_raw("pshufd ");
17653 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17654 st->print_raw(",");
17655 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17656 st->print_raw(",0xE\n\t");
17657 st->print_raw("vpmulld ");
17658 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17659 st->print_raw(",");
17660 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17661 st->print_raw(",");
17662 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17663 st->print_raw("\n\t");
17664 st->print_raw("pshufd ");
17665 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17666 st->print_raw(",");
17667 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17668 st->print_raw(",0x1\n\t");
17669 st->print_raw("vpmulld ");
17670 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17671 st->print_raw(",");
17672 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17673 st->print_raw(",");
17674 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17675 st->print_raw("\n\t");
17676 st->print_raw("movd ");
17677 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17678 st->print_raw(",");
17679 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17680 st->print_raw("\n\t");
17681 st->print_raw("vpmulld ");
17682 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17683 st->print_raw(",");
17684 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17685 st->print_raw(",");
17686 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17687 st->print_raw("\n\t");
17688 st->print_raw("movd ");
17689 opnd_array(0)->int_format(ra, this, st); // dst
17690 st->print_raw(",");
17691 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17692 st->print_raw("\t! mul reduction8I");
17693}
17694#endif
17695#ifndef PRODUCT
17696void rvmul16I_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17697 // Start at oper_input_base() and count operands
17698 unsigned idx0 = 1;
17699 unsigned idx1 = 1; // src1
17700 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17701 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17702 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17703 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
17704 st->print_raw("vextracti64x4_high ");
17705 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
17706 st->print_raw(",");
17707 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17708 st->print_raw("\n\t");
17709 st->print_raw("vpmulld ");
17710 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
17711 st->print_raw(",");
17712 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
17713 st->print_raw(",");
17714 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17715 st->print_raw("\n\t");
17716 st->print_raw("vextracti128_high ");
17717 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17718 st->print_raw(",");
17719 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3
17720 st->print_raw("\n\t");
17721 st->print_raw("vpmulld ");
17722 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17723 st->print_raw(",");
17724 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17725 st->print_raw(",");
17726 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17727 st->print_raw("\n\t");
17728 st->print_raw("pshufd ");
17729 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17730 st->print_raw(",");
17731 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17732 st->print_raw(",0xE\n\t");
17733 st->print_raw("vpmulld ");
17734 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17735 st->print_raw(",");
17736 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17737 st->print_raw(",");
17738 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17739 st->print_raw("\n\t");
17740 st->print_raw("pshufd ");
17741 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17742 st->print_raw(",");
17743 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17744 st->print_raw(",0x1\n\t");
17745 st->print_raw("vpmulld ");
17746 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17747 st->print_raw(",");
17748 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17749 st->print_raw(",");
17750 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17751 st->print_raw("\n\t");
17752 st->print_raw("movd ");
17753 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17754 st->print_raw(",");
17755 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17756 st->print_raw("\n\t");
17757 st->print_raw("vpmulld ");
17758 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17759 st->print_raw(",");
17760 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17761 st->print_raw(",");
17762 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17763 st->print_raw("\n\t");
17764 st->print_raw("movd ");
17765 opnd_array(0)->int_format(ra, this, st); // dst
17766 st->print_raw(",");
17767 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17768 st->print_raw("\t! mul reduction16I");
17769}
17770#endif
17771#ifndef PRODUCT
17772void rvmul2L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17773 // Start at oper_input_base() and count operands
17774 unsigned idx0 = 1;
17775 unsigned idx1 = 1; // src1
17776 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17777 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17778 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17779 st->print_raw("pshufd ");
17780 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17781 st->print_raw(",");
17782 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17783 st->print_raw(",0xE\n\t");
17784 st->print_raw("vpmullq ");
17785 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17786 st->print_raw(",");
17787 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17788 st->print_raw(",");
17789 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17790 st->print_raw("\n\t");
17791 st->print_raw("movdq ");
17792 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17793 st->print_raw(",");
17794 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17795 st->print_raw("\n\t");
17796 st->print_raw("vpmullq ");
17797 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17798 st->print_raw(",");
17799 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17800 st->print_raw(",");
17801 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17802 st->print_raw("\n\t");
17803 st->print_raw("movdq ");
17804 opnd_array(0)->int_format(ra, this, st); // dst
17805 st->print_raw(",");
17806 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17807 st->print_raw("\t! mul reduction2L");
17808}
17809#endif
17810#ifndef PRODUCT
17811void rvmul4L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17812 // Start at oper_input_base() and count operands
17813 unsigned idx0 = 1;
17814 unsigned idx1 = 1; // src1
17815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17816 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17817 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17818 st->print_raw("vextracti128_high ");
17819 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17820 st->print_raw(",");
17821 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17822 st->print_raw("\n\t");
17823 st->print_raw("vpmullq ");
17824 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17825 st->print_raw(",");
17826 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17827 st->print_raw(",");
17828 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17829 st->print_raw("\n\t");
17830 st->print_raw("pshufd ");
17831 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17832 st->print_raw(",");
17833 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17834 st->print_raw(",0xE\n\t");
17835 st->print_raw("vpmullq ");
17836 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17837 st->print_raw(",");
17838 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17839 st->print_raw(",");
17840 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17841 st->print_raw("\n\t");
17842 st->print_raw("movdq ");
17843 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17844 st->print_raw(",");
17845 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17846 st->print_raw("\n\t");
17847 st->print_raw("vpmullq ");
17848 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17849 st->print_raw(",");
17850 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17851 st->print_raw(",");
17852 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17853 st->print_raw("\n\t");
17854 st->print_raw("movdq ");
17855 opnd_array(0)->int_format(ra, this, st); // dst
17856 st->print_raw(",");
17857 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17858 st->print_raw("\t! mul reduction4L");
17859}
17860#endif
17861#ifndef PRODUCT
17862void rvmul8L_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17863 // Start at oper_input_base() and count operands
17864 unsigned idx0 = 1;
17865 unsigned idx1 = 1; // src1
17866 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17867 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17868 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
17869 st->print_raw("vextracti64x4_high ");
17870 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17871 st->print_raw(",");
17872 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17873 st->print_raw("\n\t");
17874 st->print_raw("vpmullq ");
17875 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17876 st->print_raw(",");
17877 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17878 st->print_raw(",");
17879 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17880 st->print_raw("\n\t");
17881 st->print_raw("vextracti128_high ");
17882 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17883 st->print_raw(",");
17884 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17885 st->print_raw("\n\t");
17886 st->print_raw("vpmullq ");
17887 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17888 st->print_raw(",");
17889 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17890 st->print_raw(",");
17891 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17892 st->print_raw("\n\t");
17893 st->print_raw("pshufd ");
17894 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17895 st->print_raw(",");
17896 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17897 st->print_raw(",0xE\n\t");
17898 st->print_raw("vpmullq ");
17899 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17900 st->print_raw(",");
17901 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17902 st->print_raw(",");
17903 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17904 st->print_raw("\n\t");
17905 st->print_raw("movdq ");
17906 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17907 st->print_raw(",");
17908 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
17909 st->print_raw("\n\t");
17910 st->print_raw("vpmullq ");
17911 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17912 st->print_raw(",");
17913 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17914 st->print_raw(",");
17915 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17916 st->print_raw("\n\t");
17917 st->print_raw("movdq ");
17918 opnd_array(0)->int_format(ra, this, st); // dst
17919 st->print_raw(",");
17920 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
17921 st->print_raw("\t! mul reduction8L");
17922}
17923#endif
17924#ifndef PRODUCT
17925void rsmul2F_reductionNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17926 // Start at oper_input_base() and count operands
17927 unsigned idx0 = 1;
17928 unsigned idx1 = 1; // dst
17929 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17930 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17931 st->print_raw("mulss ");
17932 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17933 st->print_raw(",");
17934 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17935 st->print_raw("\n\t");
17936 st->print_raw("pshufd ");
17937 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17938 st->print_raw(",");
17939 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17940 st->print_raw(",0x01\n\t");
17941 st->print_raw("mulss ");
17942 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17943 st->print_raw(",");
17944 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17945 st->print_raw("\t! mul reduction2F");
17946}
17947#endif
17948#ifndef PRODUCT
17949void rvmul2F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17950 // Start at oper_input_base() and count operands
17951 unsigned idx0 = 1;
17952 unsigned idx1 = 1; // dst
17953 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17954 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17955 st->print_raw("vmulss ");
17956 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17957 st->print_raw(",");
17958 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17959 st->print_raw(",");
17960 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17961 st->print_raw("\n\t");
17962 st->print_raw("pshufd ");
17963 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17964 st->print_raw(",");
17965 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17966 st->print_raw(",0x01\n\t");
17967 st->print_raw("vmulss ");
17968 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17969 st->print_raw(",");
17970 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17971 st->print_raw(",");
17972 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17973 st->print_raw("\t! mul reduction2F");
17974}
17975#endif
17976#ifndef PRODUCT
17977void rsmul4F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
17978 // Start at oper_input_base() and count operands
17979 unsigned idx0 = 1;
17980 unsigned idx1 = 1; // dst
17981 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
17982 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
17983 st->print_raw("mulss ");
17984 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17985 st->print_raw(",");
17986 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17987 st->print_raw("\n\t");
17988 st->print_raw("pshufd ");
17989 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17990 st->print_raw(",");
17991 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
17992 st->print_raw(",0x01\n\t");
17993 st->print_raw("mulss ");
17994 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
17995 st->print_raw(",");
17996 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
17997 st->print_raw("\n\t");
17998 st->print_raw("pshufd ");
17999 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18000 st->print_raw(",");
18001 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18002 st->print_raw(",0x02\n\t");
18003 st->print_raw("mulss ");
18004 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18005 st->print_raw(",");
18006 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18007 st->print_raw("\n\t");
18008 st->print_raw("pshufd ");
18009 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18010 st->print_raw(",");
18011 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18012 st->print_raw(",0x03\n\t");
18013 st->print_raw("mulss ");
18014 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18015 st->print_raw(",");
18016 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18017 st->print_raw("\t! mul reduction4F");
18018}
18019#endif
18020#ifndef PRODUCT
18021void rvmul4F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18022 // Start at oper_input_base() and count operands
18023 unsigned idx0 = 1;
18024 unsigned idx1 = 1; // dst
18025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18026 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18027 st->print_raw("vmulss ");
18028 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18029 st->print_raw(",");
18030 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18031 st->print_raw(",");
18032 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18033 st->print_raw("\n\t");
18034 st->print_raw("pshufd ");
18035 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18036 st->print_raw(",");
18037 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18038 st->print_raw(",0x01\n\t");
18039 st->print_raw("vmulss ");
18040 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18041 st->print_raw(",");
18042 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18043 st->print_raw(",");
18044 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18045 st->print_raw("\n\t");
18046 st->print_raw("pshufd ");
18047 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18048 st->print_raw(",");
18049 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18050 st->print_raw(",0x02\n\t");
18051 st->print_raw("vmulss ");
18052 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18053 st->print_raw(",");
18054 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18055 st->print_raw(",");
18056 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18057 st->print_raw("\n\t");
18058 st->print_raw("pshufd ");
18059 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18060 st->print_raw(",");
18061 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18062 st->print_raw(",0x03\n\t");
18063 st->print_raw("vmulss ");
18064 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18065 st->print_raw(",");
18066 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18067 st->print_raw(",");
18068 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18069 st->print_raw("\t! mul reduction4F");
18070}
18071#endif
18072#ifndef PRODUCT
18073void rvmul8F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18074 // Start at oper_input_base() and count operands
18075 unsigned idx0 = 1;
18076 unsigned idx1 = 1; // dst
18077 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18078 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18079 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
18080 st->print_raw("vmulss ");
18081 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18082 st->print_raw(",");
18083 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18084 st->print_raw(",");
18085 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18086 st->print_raw("\n\t");
18087 st->print_raw("pshufd ");
18088 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18089 st->print_raw(",");
18090 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18091 st->print_raw(",0x01\n\t");
18092 st->print_raw("vmulss ");
18093 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18094 st->print_raw(",");
18095 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18096 st->print_raw(",");
18097 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18098 st->print_raw("\n\t");
18099 st->print_raw("pshufd ");
18100 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18101 st->print_raw(",");
18102 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18103 st->print_raw(",0x02\n\t");
18104 st->print_raw("vmulss ");
18105 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18106 st->print_raw(",");
18107 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18108 st->print_raw(",");
18109 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18110 st->print_raw("\n\t");
18111 st->print_raw("pshufd ");
18112 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18113 st->print_raw(",");
18114 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18115 st->print_raw(",0x03\n\t");
18116 st->print_raw("vmulss ");
18117 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18118 st->print_raw(",");
18119 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18120 st->print_raw(",");
18121 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18122 st->print_raw("\n\t");
18123 st->print_raw("vextractf128_high ");
18124 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18125 st->print_raw(",");
18126 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18127 st->print_raw("\n\t");
18128 st->print_raw("vmulss ");
18129 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18130 st->print_raw(",");
18131 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18132 st->print_raw(",");
18133 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18134 st->print_raw("\n\t");
18135 st->print_raw("pshufd ");
18136 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18137 st->print_raw(",");
18138 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18139 st->print_raw(",0x01\n\t");
18140 st->print_raw("vmulss ");
18141 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18142 st->print_raw(",");
18143 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18144 st->print_raw(",");
18145 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18146 st->print_raw("\n\t");
18147 st->print_raw("pshufd ");
18148 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18149 st->print_raw(",");
18150 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18151 st->print_raw(",0x02\n\t");
18152 st->print_raw("vmulss ");
18153 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18154 st->print_raw(",");
18155 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18156 st->print_raw(",");
18157 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18158 st->print_raw("\n\t");
18159 st->print_raw("pshufd ");
18160 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18161 st->print_raw(",");
18162 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18163 st->print_raw(",0x03\n\t");
18164 st->print_raw("vmulss ");
18165 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18166 st->print_raw(",");
18167 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18168 st->print_raw(",");
18169 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18170 st->print_raw("\t! mul reduction8F");
18171}
18172#endif
18173#ifndef PRODUCT
18174void rvmul16F_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18175 // Start at oper_input_base() and count operands
18176 unsigned idx0 = 1;
18177 unsigned idx1 = 1; // dst
18178 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18179 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18180 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
18181 st->print_raw("vmulss ");
18182 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18183 st->print_raw(",");
18184 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18185 st->print_raw(",");
18186 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18187 st->print_raw("\n\t");
18188 st->print_raw("pshufd ");
18189 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18190 st->print_raw(",");
18191 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18192 st->print_raw(",0x01\n\t");
18193 st->print_raw("vmulss ");
18194 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18195 st->print_raw(",");
18196 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18197 st->print_raw(",");
18198 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18199 st->print_raw("\n\t");
18200 st->print_raw("pshufd ");
18201 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18202 st->print_raw(",");
18203 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18204 st->print_raw(",0x02\n\t");
18205 st->print_raw("vmulss ");
18206 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18207 st->print_raw(",");
18208 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18209 st->print_raw(",");
18210 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18211 st->print_raw("\n\t");
18212 st->print_raw("pshufd ");
18213 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18214 st->print_raw(",");
18215 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18216 st->print_raw(",0x03\n\t");
18217 st->print_raw("vmulss ");
18218 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18219 st->print_raw(",");
18220 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18221 st->print_raw(",");
18222 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18223 st->print_raw("\n\t");
18224 st->print_raw("vextractf32x4 ");
18225 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18226 st->print_raw(",");
18227 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18228 st->print_raw(",0x1\n\t");
18229 st->print_raw("vmulss ");
18230 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18231 st->print_raw(",");
18232 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18233 st->print_raw(",");
18234 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18235 st->print_raw("\n\t");
18236 st->print_raw("pshufd ");
18237 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18238 st->print_raw(",");
18239 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18240 st->print_raw(",0x01\n\t");
18241 st->print_raw("vmulss ");
18242 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18243 st->print_raw(",");
18244 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18245 st->print_raw(",");
18246 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18247 st->print_raw("\n\t");
18248 st->print_raw("pshufd ");
18249 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18250 st->print_raw(",");
18251 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18252 st->print_raw(",0x02\n\t");
18253 st->print_raw("vmulss ");
18254 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18255 st->print_raw(",");
18256 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18257 st->print_raw(",");
18258 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18259 st->print_raw("\n\t");
18260 st->print_raw("pshufd ");
18261 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18262 st->print_raw(",");
18263 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18264 st->print_raw(",0x03\n\t");
18265 st->print_raw("vmulss ");
18266 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18267 st->print_raw(",");
18268 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18269 st->print_raw(",");
18270 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18271 st->print_raw("\n\t");
18272 st->print_raw("vextractf32x4 ");
18273 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18274 st->print_raw(",");
18275 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18276 st->print_raw(",0x2\n\t");
18277 st->print_raw("vmulss ");
18278 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18279 st->print_raw(",");
18280 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18281 st->print_raw(",");
18282 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18283 st->print_raw("\n\t");
18284 st->print_raw("pshufd ");
18285 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18286 st->print_raw(",");
18287 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18288 st->print_raw(",0x01\n\t");
18289 st->print_raw("vmulss ");
18290 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18291 st->print_raw(",");
18292 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18293 st->print_raw(",");
18294 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18295 st->print_raw("\n\t");
18296 st->print_raw("pshufd ");
18297 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18298 st->print_raw(",");
18299 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18300 st->print_raw(",0x02\n\t");
18301 st->print_raw("vmulss ");
18302 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18303 st->print_raw(",");
18304 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18305 st->print_raw(",");
18306 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18307 st->print_raw("\n\t");
18308 st->print_raw("pshufd ");
18309 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18310 st->print_raw(",");
18311 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18312 st->print_raw(",0x03\n\t");
18313 st->print_raw("vmulss ");
18314 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18315 st->print_raw(",");
18316 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18317 st->print_raw(",");
18318 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18319 st->print_raw("\n\t");
18320 st->print_raw("vextractf32x4 ");
18321 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18322 st->print_raw(",");
18323 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18324 st->print_raw(",0x3\n\t");
18325 st->print_raw("vmulss ");
18326 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18327 st->print_raw(",");
18328 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18329 st->print_raw(",");
18330 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18331 st->print_raw("\n\t");
18332 st->print_raw("pshufd ");
18333 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18334 st->print_raw(",");
18335 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18336 st->print_raw(",0x01\n\t");
18337 st->print_raw("vmulss ");
18338 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18339 st->print_raw(",");
18340 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18341 st->print_raw(",");
18342 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18343 st->print_raw("\n\t");
18344 st->print_raw("pshufd ");
18345 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18346 st->print_raw(",");
18347 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18348 st->print_raw(",0x02\n\t");
18349 st->print_raw("vmulss ");
18350 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18351 st->print_raw(",");
18352 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18353 st->print_raw(",");
18354 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18355 st->print_raw("\n\t");
18356 st->print_raw("pshufd ");
18357 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18358 st->print_raw(",");
18359 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18360 st->print_raw(",0x03\n\t");
18361 st->print_raw("vmulss ");
18362 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18363 st->print_raw(",");
18364 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18365 st->print_raw(",");
18366 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18367 st->print_raw("\t! mul reduction16F");
18368}
18369#endif
18370#ifndef PRODUCT
18371void rsmul2D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18372 // Start at oper_input_base() and count operands
18373 unsigned idx0 = 1;
18374 unsigned idx1 = 1; // dst
18375 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18376 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18377 st->print_raw("mulsd ");
18378 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18379 st->print_raw(",");
18380 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18381 st->print_raw("\n\t");
18382 st->print_raw("pshufd ");
18383 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18384 st->print_raw(",");
18385 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18386 st->print_raw(",0xE\n\t");
18387 st->print_raw("mulsd ");
18388 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18389 st->print_raw(",");
18390 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18391 st->print_raw("\t! mul reduction2D");
18392}
18393#endif
18394#ifndef PRODUCT
18395void rvmul2D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18396 // Start at oper_input_base() and count operands
18397 unsigned idx0 = 1;
18398 unsigned idx1 = 1; // dst
18399 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18400 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18401 st->print_raw("vmulsd ");
18402 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18403 st->print_raw(",");
18404 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18405 st->print_raw(",");
18406 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18407 st->print_raw("\n\t");
18408 st->print_raw("pshufd ");
18409 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18410 st->print_raw(",");
18411 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18412 st->print_raw(",0xE\n\t");
18413 st->print_raw("vmulsd ");
18414 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18415 st->print_raw(",");
18416 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18417 st->print_raw(",");
18418 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18419 st->print_raw("\t! mul reduction2D");
18420}
18421#endif
18422#ifndef PRODUCT
18423void rvmul4D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18424 // Start at oper_input_base() and count operands
18425 unsigned idx0 = 1;
18426 unsigned idx1 = 1; // dst
18427 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18428 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18429 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
18430 st->print_raw("vmulsd ");
18431 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18432 st->print_raw(",");
18433 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18434 st->print_raw(",");
18435 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18436 st->print_raw("\n\t");
18437 st->print_raw("pshufd ");
18438 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18439 st->print_raw(",");
18440 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18441 st->print_raw(",0xE\n\t");
18442 st->print_raw("vmulsd ");
18443 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18444 st->print_raw(",");
18445 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18446 st->print_raw(",");
18447 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18448 st->print_raw("\n\t");
18449 st->print_raw("vextractf128_high ");
18450 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18451 st->print_raw(",");
18452 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18453 st->print_raw("\n\t");
18454 st->print_raw("vmulsd ");
18455 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18456 st->print_raw(",");
18457 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18458 st->print_raw(",");
18459 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18460 st->print_raw("\n\t");
18461 st->print_raw("pshufd ");
18462 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18463 st->print_raw(",");
18464 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18465 st->print_raw(",0xE\n\t");
18466 st->print_raw("vmulsd ");
18467 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18468 st->print_raw(",");
18469 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18470 st->print_raw(",");
18471 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18472 st->print_raw("\t! mul reduction4D");
18473}
18474#endif
18475#ifndef PRODUCT
18476void rvmul8D_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18477 // Start at oper_input_base() and count operands
18478 unsigned idx0 = 1;
18479 unsigned idx1 = 1; // dst
18480 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18481 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
18482 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
18483 st->print_raw("vmulsd ");
18484 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18485 st->print_raw(",");
18486 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18487 st->print_raw(",");
18488 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18489 st->print_raw("\n\t");
18490 st->print_raw("pshufd ");
18491 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18492 st->print_raw(",");
18493 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18494 st->print_raw(",0xE\n\t");
18495 st->print_raw("vmulsd ");
18496 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18497 st->print_raw(",");
18498 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18499 st->print_raw(",");
18500 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18501 st->print_raw("\n\t");
18502 st->print_raw("vextractf32x4 ");
18503 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18504 st->print_raw(",");
18505 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18506 st->print_raw(",0x1\n\t");
18507 st->print_raw("vmulsd ");
18508 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18509 st->print_raw(",");
18510 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18511 st->print_raw(",");
18512 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18513 st->print_raw("\n\t");
18514 st->print_raw("pshufd ");
18515 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18516 st->print_raw(",");
18517 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18518 st->print_raw(",0xE\n\t");
18519 st->print_raw("vmulsd ");
18520 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18521 st->print_raw(",");
18522 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18523 st->print_raw(",");
18524 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18525 st->print_raw("\n\t");
18526 st->print_raw("vextractf32x4 ");
18527 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18528 st->print_raw(",");
18529 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18530 st->print_raw(",0x2\n\t");
18531 st->print_raw("vmulsd ");
18532 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18533 st->print_raw(",");
18534 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18535 st->print_raw(",");
18536 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18537 st->print_raw("\n\t");
18538 st->print_raw("pshufd ");
18539 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18540 st->print_raw(",");
18541 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18542 st->print_raw(",0xE\n\t");
18543 st->print_raw("vmulsd ");
18544 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18545 st->print_raw(",");
18546 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18547 st->print_raw(",");
18548 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18549 st->print_raw("\n\t");
18550 st->print_raw("vextractf32x4 ");
18551 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18552 st->print_raw(",");
18553 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18554 st->print_raw(",0x3\n\t");
18555 st->print_raw("vmulsd ");
18556 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18557 st->print_raw(",");
18558 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18559 st->print_raw(",");
18560 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18561 st->print_raw("\n\t");
18562 st->print_raw("pshufd ");
18563 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18564 st->print_raw(",");
18565 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2
18566 st->print_raw(",0xE\n\t");
18567 st->print_raw("vmulsd ");
18568 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18569 st->print_raw(",");
18570 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18571 st->print_raw(",");
18572 opnd_array(3)->ext_format(ra, this,idx3, st); // tmp
18573 st->print_raw("\t! mul reduction8D");
18574}
18575#endif
18576#ifndef PRODUCT
18577void vadd4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18578 // Start at oper_input_base() and count operands
18579 unsigned idx0 = 1;
18580 unsigned idx1 = 1; // dst
18581 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18582 st->print_raw("paddb ");
18583 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18584 st->print_raw(",");
18585 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18586 st->print_raw("\t! add packed4B");
18587}
18588#endif
18589#ifndef PRODUCT
18590void vadd4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18591 // Start at oper_input_base() and count operands
18592 unsigned idx0 = 1;
18593 unsigned idx1 = 1; // src1
18594 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18595 st->print_raw("vpaddb ");
18596 opnd_array(0)->int_format(ra, this, st); // dst
18597 st->print_raw(",");
18598 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18599 st->print_raw(",");
18600 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18601 st->print_raw("\t! add packed4B");
18602}
18603#endif
18604#ifndef PRODUCT
18605void vadd4B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18606 // Start at oper_input_base() and count operands
18607 unsigned idx0 = 2;
18608 unsigned idx1 = 2; // src
18609 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18610 st->print_raw("vpaddb ");
18611 opnd_array(0)->int_format(ra, this, st); // dst
18612 st->print_raw(",");
18613 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18614 st->print_raw(",");
18615 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18616 st->print_raw("\t! add packed4B");
18617}
18618#endif
18619#ifndef PRODUCT
18620void vadd4B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18621 // Start at oper_input_base() and count operands
18622 unsigned idx0 = 2;
18623 unsigned idx1 = 2; // mem
18624 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18625 st->print_raw("vpaddb ");
18626 opnd_array(0)->int_format(ra, this, st); // dst
18627 st->print_raw(",");
18628 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18629 st->print_raw(",");
18630 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18631 st->print_raw("\t! add packed4B");
18632}
18633#endif
18634#ifndef PRODUCT
18635void vadd8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18636 // Start at oper_input_base() and count operands
18637 unsigned idx0 = 1;
18638 unsigned idx1 = 1; // dst
18639 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18640 st->print_raw("paddb ");
18641 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18642 st->print_raw(",");
18643 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18644 st->print_raw("\t! add packed8B");
18645}
18646#endif
18647#ifndef PRODUCT
18648void vadd8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18649 // Start at oper_input_base() and count operands
18650 unsigned idx0 = 1;
18651 unsigned idx1 = 1; // src1
18652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18653 st->print_raw("vpaddb ");
18654 opnd_array(0)->int_format(ra, this, st); // dst
18655 st->print_raw(",");
18656 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18657 st->print_raw(",");
18658 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18659 st->print_raw("\t! add packed8B");
18660}
18661#endif
18662#ifndef PRODUCT
18663void vadd8B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18664 // Start at oper_input_base() and count operands
18665 unsigned idx0 = 2;
18666 unsigned idx1 = 2; // src
18667 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18668 st->print_raw("vpaddb ");
18669 opnd_array(0)->int_format(ra, this, st); // dst
18670 st->print_raw(",");
18671 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18672 st->print_raw(",");
18673 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18674 st->print_raw("\t! add packed8B");
18675}
18676#endif
18677#ifndef PRODUCT
18678void vadd8B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18679 // Start at oper_input_base() and count operands
18680 unsigned idx0 = 2;
18681 unsigned idx1 = 2; // mem
18682 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18683 st->print_raw("vpaddb ");
18684 opnd_array(0)->int_format(ra, this, st); // dst
18685 st->print_raw(",");
18686 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18687 st->print_raw(",");
18688 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18689 st->print_raw("\t! add packed8B");
18690}
18691#endif
18692#ifndef PRODUCT
18693void vadd16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18694 // Start at oper_input_base() and count operands
18695 unsigned idx0 = 1;
18696 unsigned idx1 = 1; // dst
18697 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18698 st->print_raw("paddb ");
18699 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18700 st->print_raw(",");
18701 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18702 st->print_raw("\t! add packed16B");
18703}
18704#endif
18705#ifndef PRODUCT
18706void vadd16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18707 // Start at oper_input_base() and count operands
18708 unsigned idx0 = 1;
18709 unsigned idx1 = 1; // src1
18710 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18711 st->print_raw("vpaddb ");
18712 opnd_array(0)->int_format(ra, this, st); // dst
18713 st->print_raw(",");
18714 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18715 st->print_raw(",");
18716 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18717 st->print_raw("\t! add packed16B");
18718}
18719#endif
18720#ifndef PRODUCT
18721void vadd16B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18722 // Start at oper_input_base() and count operands
18723 unsigned idx0 = 2;
18724 unsigned idx1 = 2; // src
18725 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18726 st->print_raw("vpaddb ");
18727 opnd_array(0)->int_format(ra, this, st); // dst
18728 st->print_raw(",");
18729 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18730 st->print_raw(",");
18731 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18732 st->print_raw("\t! add packed16B");
18733}
18734#endif
18735#ifndef PRODUCT
18736void vadd16B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18737 // Start at oper_input_base() and count operands
18738 unsigned idx0 = 2;
18739 unsigned idx1 = 2; // mem
18740 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18741 st->print_raw("vpaddb ");
18742 opnd_array(0)->int_format(ra, this, st); // dst
18743 st->print_raw(",");
18744 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18745 st->print_raw(",");
18746 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18747 st->print_raw("\t! add packed16B");
18748}
18749#endif
18750#ifndef PRODUCT
18751void vadd32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18752 // Start at oper_input_base() and count operands
18753 unsigned idx0 = 1;
18754 unsigned idx1 = 1; // src1
18755 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18756 st->print_raw("vpaddb ");
18757 opnd_array(0)->int_format(ra, this, st); // dst
18758 st->print_raw(",");
18759 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18760 st->print_raw(",");
18761 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18762 st->print_raw("\t! add packed32B");
18763}
18764#endif
18765#ifndef PRODUCT
18766void vadd32B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18767 // Start at oper_input_base() and count operands
18768 unsigned idx0 = 2;
18769 unsigned idx1 = 2; // src
18770 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18771 st->print_raw("vpaddb ");
18772 opnd_array(0)->int_format(ra, this, st); // dst
18773 st->print_raw(",");
18774 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18775 st->print_raw(",");
18776 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18777 st->print_raw("\t! add packed32B");
18778}
18779#endif
18780#ifndef PRODUCT
18781void vadd32B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18782 // Start at oper_input_base() and count operands
18783 unsigned idx0 = 2;
18784 unsigned idx1 = 2; // mem
18785 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18786 st->print_raw("vpaddb ");
18787 opnd_array(0)->int_format(ra, this, st); // dst
18788 st->print_raw(",");
18789 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18790 st->print_raw(",");
18791 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18792 st->print_raw("\t! add packed32B");
18793}
18794#endif
18795#ifndef PRODUCT
18796void vadd64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18797 // Start at oper_input_base() and count operands
18798 unsigned idx0 = 1;
18799 unsigned idx1 = 1; // src1
18800 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18801 st->print_raw("vpaddb ");
18802 opnd_array(0)->int_format(ra, this, st); // dst
18803 st->print_raw(",");
18804 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18805 st->print_raw(",");
18806 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18807 st->print_raw("\t! add packed64B");
18808}
18809#endif
18810#ifndef PRODUCT
18811void vadd64B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18812 // Start at oper_input_base() and count operands
18813 unsigned idx0 = 2;
18814 unsigned idx1 = 2; // src
18815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18816 st->print_raw("vpaddb ");
18817 opnd_array(0)->int_format(ra, this, st); // dst
18818 st->print_raw(",");
18819 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18820 st->print_raw(",");
18821 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18822 st->print_raw("\t! add packed64B");
18823}
18824#endif
18825#ifndef PRODUCT
18826void vadd64B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18827 // Start at oper_input_base() and count operands
18828 unsigned idx0 = 2;
18829 unsigned idx1 = 2; // mem
18830 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18831 st->print_raw("vpaddb ");
18832 opnd_array(0)->int_format(ra, this, st); // dst
18833 st->print_raw(",");
18834 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18835 st->print_raw(",");
18836 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18837 st->print_raw("\t! add packed64B");
18838}
18839#endif
18840#ifndef PRODUCT
18841void vadd2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18842 // Start at oper_input_base() and count operands
18843 unsigned idx0 = 1;
18844 unsigned idx1 = 1; // dst
18845 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18846 st->print_raw("paddw ");
18847 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18848 st->print_raw(",");
18849 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18850 st->print_raw("\t! add packed2S");
18851}
18852#endif
18853#ifndef PRODUCT
18854void vadd2S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18855 // Start at oper_input_base() and count operands
18856 unsigned idx0 = 1;
18857 unsigned idx1 = 1; // src1
18858 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18859 st->print_raw("vpaddw ");
18860 opnd_array(0)->int_format(ra, this, st); // dst
18861 st->print_raw(",");
18862 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18863 st->print_raw(",");
18864 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18865 st->print_raw("\t! add packed2S");
18866}
18867#endif
18868#ifndef PRODUCT
18869void vadd2S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18870 // Start at oper_input_base() and count operands
18871 unsigned idx0 = 2;
18872 unsigned idx1 = 2; // src
18873 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18874 st->print_raw("vpaddw ");
18875 opnd_array(0)->int_format(ra, this, st); // dst
18876 st->print_raw(",");
18877 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18878 st->print_raw(",");
18879 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18880 st->print_raw("\t! add packed2S");
18881}
18882#endif
18883#ifndef PRODUCT
18884void vadd2S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18885 // Start at oper_input_base() and count operands
18886 unsigned idx0 = 2;
18887 unsigned idx1 = 2; // mem
18888 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18889 st->print_raw("vpaddw ");
18890 opnd_array(0)->int_format(ra, this, st); // dst
18891 st->print_raw(",");
18892 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18893 st->print_raw(",");
18894 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18895 st->print_raw("\t! add packed2S");
18896}
18897#endif
18898#ifndef PRODUCT
18899void vadd4SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18900 // Start at oper_input_base() and count operands
18901 unsigned idx0 = 1;
18902 unsigned idx1 = 1; // dst
18903 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18904 st->print_raw("paddw ");
18905 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18906 st->print_raw(",");
18907 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18908 st->print_raw("\t! add packed4S");
18909}
18910#endif
18911#ifndef PRODUCT
18912void vadd4S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18913 // Start at oper_input_base() and count operands
18914 unsigned idx0 = 1;
18915 unsigned idx1 = 1; // src1
18916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18917 st->print_raw("vpaddw ");
18918 opnd_array(0)->int_format(ra, this, st); // dst
18919 st->print_raw(",");
18920 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18921 st->print_raw(",");
18922 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18923 st->print_raw("\t! add packed4S");
18924}
18925#endif
18926#ifndef PRODUCT
18927void vadd4S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18928 // Start at oper_input_base() and count operands
18929 unsigned idx0 = 2;
18930 unsigned idx1 = 2; // src
18931 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18932 st->print_raw("vpaddw ");
18933 opnd_array(0)->int_format(ra, this, st); // dst
18934 st->print_raw(",");
18935 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18936 st->print_raw(",");
18937 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18938 st->print_raw("\t! add packed4S");
18939}
18940#endif
18941#ifndef PRODUCT
18942void vadd4S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
18943 // Start at oper_input_base() and count operands
18944 unsigned idx0 = 2;
18945 unsigned idx1 = 2; // mem
18946 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18947 st->print_raw("vpaddw ");
18948 opnd_array(0)->int_format(ra, this, st); // dst
18949 st->print_raw(",");
18950 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18951 st->print_raw(",");
18952 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
18953 st->print_raw("\t! add packed4S");
18954}
18955#endif
18956#ifndef PRODUCT
18957void vadd8SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18958 // Start at oper_input_base() and count operands
18959 unsigned idx0 = 1;
18960 unsigned idx1 = 1; // dst
18961 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
18962 st->print_raw("paddw ");
18963 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
18964 st->print_raw(",");
18965 opnd_array(2)->ext_format(ra, this,idx2, st); // src
18966 st->print_raw("\t! add packed8S");
18967}
18968#endif
18969#ifndef PRODUCT
18970void vadd8S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18971 // Start at oper_input_base() and count operands
18972 unsigned idx0 = 1;
18973 unsigned idx1 = 1; // src1
18974 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
18975 st->print_raw("vpaddw ");
18976 opnd_array(0)->int_format(ra, this, st); // dst
18977 st->print_raw(",");
18978 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
18979 st->print_raw(",");
18980 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
18981 st->print_raw("\t! add packed8S");
18982}
18983#endif
18984#ifndef PRODUCT
18985void vadd8S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
18986 // Start at oper_input_base() and count operands
18987 unsigned idx0 = 2;
18988 unsigned idx1 = 2; // src
18989 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
18990 st->print_raw("vpaddw ");
18991 opnd_array(0)->int_format(ra, this, st); // dst
18992 st->print_raw(",");
18993 opnd_array(1)->ext_format(ra, this,idx1, st); // src
18994 st->print_raw(",");
18995 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
18996 st->print_raw("\t! add packed8S");
18997}
18998#endif
18999#ifndef PRODUCT
19000void vadd8S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19001 // Start at oper_input_base() and count operands
19002 unsigned idx0 = 2;
19003 unsigned idx1 = 2; // mem
19004 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19005 st->print_raw("vpaddw ");
19006 opnd_array(0)->int_format(ra, this, st); // dst
19007 st->print_raw(",");
19008 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19009 st->print_raw(",");
19010 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19011 st->print_raw("\t! add packed8S");
19012}
19013#endif
19014#ifndef PRODUCT
19015void vadd16S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19016 // Start at oper_input_base() and count operands
19017 unsigned idx0 = 1;
19018 unsigned idx1 = 1; // src1
19019 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19020 st->print_raw("vpaddw ");
19021 opnd_array(0)->int_format(ra, this, st); // dst
19022 st->print_raw(",");
19023 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19024 st->print_raw(",");
19025 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19026 st->print_raw("\t! add packed16S");
19027}
19028#endif
19029#ifndef PRODUCT
19030void vadd16S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19031 // Start at oper_input_base() and count operands
19032 unsigned idx0 = 2;
19033 unsigned idx1 = 2; // src
19034 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19035 st->print_raw("vpaddw ");
19036 opnd_array(0)->int_format(ra, this, st); // dst
19037 st->print_raw(",");
19038 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19039 st->print_raw(",");
19040 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19041 st->print_raw("\t! add packed16S");
19042}
19043#endif
19044#ifndef PRODUCT
19045void vadd16S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19046 // Start at oper_input_base() and count operands
19047 unsigned idx0 = 2;
19048 unsigned idx1 = 2; // mem
19049 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19050 st->print_raw("vpaddw ");
19051 opnd_array(0)->int_format(ra, this, st); // dst
19052 st->print_raw(",");
19053 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19054 st->print_raw(",");
19055 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19056 st->print_raw("\t! add packed16S");
19057}
19058#endif
19059#ifndef PRODUCT
19060void vadd32S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19061 // Start at oper_input_base() and count operands
19062 unsigned idx0 = 1;
19063 unsigned idx1 = 1; // src1
19064 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19065 st->print_raw("vpaddw ");
19066 opnd_array(0)->int_format(ra, this, st); // dst
19067 st->print_raw(",");
19068 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19069 st->print_raw(",");
19070 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19071 st->print_raw("\t! add packed32S");
19072}
19073#endif
19074#ifndef PRODUCT
19075void vadd32S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19076 // Start at oper_input_base() and count operands
19077 unsigned idx0 = 2;
19078 unsigned idx1 = 2; // src
19079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19080 st->print_raw("vpaddw ");
19081 opnd_array(0)->int_format(ra, this, st); // dst
19082 st->print_raw(",");
19083 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19084 st->print_raw(",");
19085 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19086 st->print_raw("\t! add packed32S");
19087}
19088#endif
19089#ifndef PRODUCT
19090void vadd32S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19091 // Start at oper_input_base() and count operands
19092 unsigned idx0 = 2;
19093 unsigned idx1 = 2; // mem
19094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19095 st->print_raw("vpaddw ");
19096 opnd_array(0)->int_format(ra, this, st); // dst
19097 st->print_raw(",");
19098 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19099 st->print_raw(",");
19100 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19101 st->print_raw("\t! add packed32S");
19102}
19103#endif
19104#ifndef PRODUCT
19105void vadd2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
19106 // Start at oper_input_base() and count operands
19107 unsigned idx0 = 1;
19108 unsigned idx1 = 1; // dst
19109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19110 st->print_raw("paddd ");
19111 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19112 st->print_raw(",");
19113 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19114 st->print_raw("\t! add packed2I");
19115}
19116#endif
19117#ifndef PRODUCT
19118void vadd2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19119 // Start at oper_input_base() and count operands
19120 unsigned idx0 = 1;
19121 unsigned idx1 = 1; // src1
19122 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19123 st->print_raw("vpaddd ");
19124 opnd_array(0)->int_format(ra, this, st); // dst
19125 st->print_raw(",");
19126 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19127 st->print_raw(",");
19128 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19129 st->print_raw("\t! add packed2I");
19130}
19131#endif
19132#ifndef PRODUCT
19133void vadd2I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19134 // Start at oper_input_base() and count operands
19135 unsigned idx0 = 2;
19136 unsigned idx1 = 2; // src
19137 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19138 st->print_raw("vpaddd ");
19139 opnd_array(0)->int_format(ra, this, st); // dst
19140 st->print_raw(",");
19141 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19142 st->print_raw(",");
19143 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19144 st->print_raw("\t! add packed2I");
19145}
19146#endif
19147#ifndef PRODUCT
19148void vadd2I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19149 // Start at oper_input_base() and count operands
19150 unsigned idx0 = 2;
19151 unsigned idx1 = 2; // mem
19152 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19153 st->print_raw("vpaddd ");
19154 opnd_array(0)->int_format(ra, this, st); // dst
19155 st->print_raw(",");
19156 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19157 st->print_raw(",");
19158 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19159 st->print_raw("\t! add packed2I");
19160}
19161#endif
19162#ifndef PRODUCT
19163void vadd4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
19164 // Start at oper_input_base() and count operands
19165 unsigned idx0 = 1;
19166 unsigned idx1 = 1; // dst
19167 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19168 st->print_raw("paddd ");
19169 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19170 st->print_raw(",");
19171 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19172 st->print_raw("\t! add packed4I");
19173}
19174#endif
19175#ifndef PRODUCT
19176void vadd4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19177 // Start at oper_input_base() and count operands
19178 unsigned idx0 = 1;
19179 unsigned idx1 = 1; // src1
19180 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19181 st->print_raw("vpaddd ");
19182 opnd_array(0)->int_format(ra, this, st); // dst
19183 st->print_raw(",");
19184 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19185 st->print_raw(",");
19186 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19187 st->print_raw("\t! add packed4I");
19188}
19189#endif
19190#ifndef PRODUCT
19191void vadd4I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19192 // Start at oper_input_base() and count operands
19193 unsigned idx0 = 2;
19194 unsigned idx1 = 2; // src
19195 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19196 st->print_raw("vpaddd ");
19197 opnd_array(0)->int_format(ra, this, st); // dst
19198 st->print_raw(",");
19199 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19200 st->print_raw(",");
19201 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19202 st->print_raw("\t! add packed4I");
19203}
19204#endif
19205#ifndef PRODUCT
19206void vadd4I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19207 // Start at oper_input_base() and count operands
19208 unsigned idx0 = 2;
19209 unsigned idx1 = 2; // mem
19210 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19211 st->print_raw("vpaddd ");
19212 opnd_array(0)->int_format(ra, this, st); // dst
19213 st->print_raw(",");
19214 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19215 st->print_raw(",");
19216 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19217 st->print_raw("\t! add packed4I");
19218}
19219#endif
19220#ifndef PRODUCT
19221void vadd8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19222 // Start at oper_input_base() and count operands
19223 unsigned idx0 = 1;
19224 unsigned idx1 = 1; // src1
19225 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19226 st->print_raw("vpaddd ");
19227 opnd_array(0)->int_format(ra, this, st); // dst
19228 st->print_raw(",");
19229 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19230 st->print_raw(",");
19231 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19232 st->print_raw("\t! add packed8I");
19233}
19234#endif
19235#ifndef PRODUCT
19236void vadd8I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19237 // Start at oper_input_base() and count operands
19238 unsigned idx0 = 2;
19239 unsigned idx1 = 2; // src
19240 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19241 st->print_raw("vpaddd ");
19242 opnd_array(0)->int_format(ra, this, st); // dst
19243 st->print_raw(",");
19244 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19245 st->print_raw(",");
19246 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19247 st->print_raw("\t! add packed8I");
19248}
19249#endif
19250#ifndef PRODUCT
19251void vadd8I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19252 // Start at oper_input_base() and count operands
19253 unsigned idx0 = 2;
19254 unsigned idx1 = 2; // mem
19255 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19256 st->print_raw("vpaddd ");
19257 opnd_array(0)->int_format(ra, this, st); // dst
19258 st->print_raw(",");
19259 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19260 st->print_raw(",");
19261 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19262 st->print_raw("\t! add packed8I");
19263}
19264#endif
19265#ifndef PRODUCT
19266void vadd16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19267 // Start at oper_input_base() and count operands
19268 unsigned idx0 = 1;
19269 unsigned idx1 = 1; // src1
19270 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19271 st->print_raw("vpaddd ");
19272 opnd_array(0)->int_format(ra, this, st); // dst
19273 st->print_raw(",");
19274 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19275 st->print_raw(",");
19276 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19277 st->print_raw("\t! add packed16I");
19278}
19279#endif
19280#ifndef PRODUCT
19281void vadd16I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19282 // Start at oper_input_base() and count operands
19283 unsigned idx0 = 2;
19284 unsigned idx1 = 2; // src
19285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19286 st->print_raw("vpaddd ");
19287 opnd_array(0)->int_format(ra, this, st); // dst
19288 st->print_raw(",");
19289 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19290 st->print_raw(",");
19291 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19292 st->print_raw("\t! add packed16I");
19293}
19294#endif
19295#ifndef PRODUCT
19296void vadd16I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19297 // Start at oper_input_base() and count operands
19298 unsigned idx0 = 2;
19299 unsigned idx1 = 2; // mem
19300 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19301 st->print_raw("vpaddd ");
19302 opnd_array(0)->int_format(ra, this, st); // dst
19303 st->print_raw(",");
19304 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19305 st->print_raw(",");
19306 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19307 st->print_raw("\t! add packed16I");
19308}
19309#endif
19310#ifndef PRODUCT
19311void vadd2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19312 // Start at oper_input_base() and count operands
19313 unsigned idx0 = 1;
19314 unsigned idx1 = 1; // dst
19315 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19316 st->print_raw("paddq ");
19317 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19318 st->print_raw(",");
19319 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19320 st->print_raw("\t! add packed2L");
19321}
19322#endif
19323#ifndef PRODUCT
19324void vadd2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19325 // Start at oper_input_base() and count operands
19326 unsigned idx0 = 1;
19327 unsigned idx1 = 1; // src1
19328 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19329 st->print_raw("vpaddq ");
19330 opnd_array(0)->int_format(ra, this, st); // dst
19331 st->print_raw(",");
19332 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19333 st->print_raw(",");
19334 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19335 st->print_raw("\t! add packed2L");
19336}
19337#endif
19338#ifndef PRODUCT
19339void vadd2L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19340 // Start at oper_input_base() and count operands
19341 unsigned idx0 = 2;
19342 unsigned idx1 = 2; // src
19343 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19344 st->print_raw("vpaddq ");
19345 opnd_array(0)->int_format(ra, this, st); // dst
19346 st->print_raw(",");
19347 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19348 st->print_raw(",");
19349 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19350 st->print_raw("\t! add packed2L");
19351}
19352#endif
19353#ifndef PRODUCT
19354void vadd2L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19355 // Start at oper_input_base() and count operands
19356 unsigned idx0 = 2;
19357 unsigned idx1 = 2; // mem
19358 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19359 st->print_raw("vpaddq ");
19360 opnd_array(0)->int_format(ra, this, st); // dst
19361 st->print_raw(",");
19362 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19363 st->print_raw(",");
19364 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19365 st->print_raw("\t! add packed2L");
19366}
19367#endif
19368#ifndef PRODUCT
19369void vadd4L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19370 // Start at oper_input_base() and count operands
19371 unsigned idx0 = 1;
19372 unsigned idx1 = 1; // src1
19373 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19374 st->print_raw("vpaddq ");
19375 opnd_array(0)->int_format(ra, this, st); // dst
19376 st->print_raw(",");
19377 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19378 st->print_raw(",");
19379 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19380 st->print_raw("\t! add packed4L");
19381}
19382#endif
19383#ifndef PRODUCT
19384void vadd4L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19385 // Start at oper_input_base() and count operands
19386 unsigned idx0 = 2;
19387 unsigned idx1 = 2; // src
19388 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19389 st->print_raw("vpaddq ");
19390 opnd_array(0)->int_format(ra, this, st); // dst
19391 st->print_raw(",");
19392 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19393 st->print_raw(",");
19394 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19395 st->print_raw("\t! add packed4L");
19396}
19397#endif
19398#ifndef PRODUCT
19399void vadd4L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19400 // Start at oper_input_base() and count operands
19401 unsigned idx0 = 2;
19402 unsigned idx1 = 2; // mem
19403 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19404 st->print_raw("vpaddq ");
19405 opnd_array(0)->int_format(ra, this, st); // dst
19406 st->print_raw(",");
19407 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19408 st->print_raw(",");
19409 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19410 st->print_raw("\t! add packed4L");
19411}
19412#endif
19413#ifndef PRODUCT
19414void vadd8L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19415 // Start at oper_input_base() and count operands
19416 unsigned idx0 = 1;
19417 unsigned idx1 = 1; // src1
19418 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19419 st->print_raw("vpaddq ");
19420 opnd_array(0)->int_format(ra, this, st); // dst
19421 st->print_raw(",");
19422 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19423 st->print_raw(",");
19424 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19425 st->print_raw("\t! add packed8L");
19426}
19427#endif
19428#ifndef PRODUCT
19429void vadd8L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19430 // Start at oper_input_base() and count operands
19431 unsigned idx0 = 2;
19432 unsigned idx1 = 2; // src
19433 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19434 st->print_raw("vpaddq ");
19435 opnd_array(0)->int_format(ra, this, st); // dst
19436 st->print_raw(",");
19437 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19438 st->print_raw(",");
19439 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19440 st->print_raw("\t! add packed8L");
19441}
19442#endif
19443#ifndef PRODUCT
19444void vadd8L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19445 // Start at oper_input_base() and count operands
19446 unsigned idx0 = 2;
19447 unsigned idx1 = 2; // mem
19448 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19449 st->print_raw("vpaddq ");
19450 opnd_array(0)->int_format(ra, this, st); // dst
19451 st->print_raw(",");
19452 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19453 st->print_raw(",");
19454 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19455 st->print_raw("\t! add packed8L");
19456}
19457#endif
19458#ifndef PRODUCT
19459void vadd2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19460 // Start at oper_input_base() and count operands
19461 unsigned idx0 = 1;
19462 unsigned idx1 = 1; // dst
19463 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19464 st->print_raw("addps ");
19465 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19466 st->print_raw(",");
19467 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19468 st->print_raw("\t! add packed2F");
19469}
19470#endif
19471#ifndef PRODUCT
19472void vadd2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19473 // Start at oper_input_base() and count operands
19474 unsigned idx0 = 1;
19475 unsigned idx1 = 1; // src1
19476 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19477 st->print_raw("vaddps ");
19478 opnd_array(0)->int_format(ra, this, st); // dst
19479 st->print_raw(",");
19480 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19481 st->print_raw(",");
19482 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19483 st->print_raw("\t! add packed2F");
19484}
19485#endif
19486#ifndef PRODUCT
19487void vadd2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19488 // Start at oper_input_base() and count operands
19489 unsigned idx0 = 2;
19490 unsigned idx1 = 2; // src
19491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19492 st->print_raw("vaddps ");
19493 opnd_array(0)->int_format(ra, this, st); // dst
19494 st->print_raw(",");
19495 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19496 st->print_raw(",");
19497 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19498 st->print_raw("\t! add packed2F");
19499}
19500#endif
19501#ifndef PRODUCT
19502void vadd2F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19503 // Start at oper_input_base() and count operands
19504 unsigned idx0 = 2;
19505 unsigned idx1 = 2; // mem
19506 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19507 st->print_raw("vaddps ");
19508 opnd_array(0)->int_format(ra, this, st); // dst
19509 st->print_raw(",");
19510 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19511 st->print_raw(",");
19512 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19513 st->print_raw("\t! add packed2F");
19514}
19515#endif
19516#ifndef PRODUCT
19517void vadd4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19518 // Start at oper_input_base() and count operands
19519 unsigned idx0 = 1;
19520 unsigned idx1 = 1; // dst
19521 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19522 st->print_raw("addps ");
19523 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19524 st->print_raw(",");
19525 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19526 st->print_raw("\t! add packed4F");
19527}
19528#endif
19529#ifndef PRODUCT
19530void vadd4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19531 // Start at oper_input_base() and count operands
19532 unsigned idx0 = 1;
19533 unsigned idx1 = 1; // src1
19534 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19535 st->print_raw("vaddps ");
19536 opnd_array(0)->int_format(ra, this, st); // dst
19537 st->print_raw(",");
19538 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19539 st->print_raw(",");
19540 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19541 st->print_raw("\t! add packed4F");
19542}
19543#endif
19544#ifndef PRODUCT
19545void vadd4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19546 // Start at oper_input_base() and count operands
19547 unsigned idx0 = 2;
19548 unsigned idx1 = 2; // src
19549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19550 st->print_raw("vaddps ");
19551 opnd_array(0)->int_format(ra, this, st); // dst
19552 st->print_raw(",");
19553 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19554 st->print_raw(",");
19555 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19556 st->print_raw("\t! add packed4F");
19557}
19558#endif
19559#ifndef PRODUCT
19560void vadd4F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19561 // Start at oper_input_base() and count operands
19562 unsigned idx0 = 2;
19563 unsigned idx1 = 2; // mem
19564 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19565 st->print_raw("vaddps ");
19566 opnd_array(0)->int_format(ra, this, st); // dst
19567 st->print_raw(",");
19568 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19569 st->print_raw(",");
19570 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19571 st->print_raw("\t! add packed4F");
19572}
19573#endif
19574#ifndef PRODUCT
19575void vadd8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19576 // Start at oper_input_base() and count operands
19577 unsigned idx0 = 1;
19578 unsigned idx1 = 1; // src1
19579 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19580 st->print_raw("vaddps ");
19581 opnd_array(0)->int_format(ra, this, st); // dst
19582 st->print_raw(",");
19583 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19584 st->print_raw(",");
19585 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19586 st->print_raw("\t! add packed8F");
19587}
19588#endif
19589#ifndef PRODUCT
19590void vadd8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19591 // Start at oper_input_base() and count operands
19592 unsigned idx0 = 2;
19593 unsigned idx1 = 2; // src
19594 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19595 st->print_raw("vaddps ");
19596 opnd_array(0)->int_format(ra, this, st); // dst
19597 st->print_raw(",");
19598 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19599 st->print_raw(",");
19600 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19601 st->print_raw("\t! add packed8F");
19602}
19603#endif
19604#ifndef PRODUCT
19605void vadd8F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19606 // Start at oper_input_base() and count operands
19607 unsigned idx0 = 2;
19608 unsigned idx1 = 2; // mem
19609 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19610 st->print_raw("vaddps ");
19611 opnd_array(0)->int_format(ra, this, st); // dst
19612 st->print_raw(",");
19613 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19614 st->print_raw(",");
19615 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19616 st->print_raw("\t! add packed8F");
19617}
19618#endif
19619#ifndef PRODUCT
19620void vadd16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19621 // Start at oper_input_base() and count operands
19622 unsigned idx0 = 1;
19623 unsigned idx1 = 1; // src1
19624 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19625 st->print_raw("vaddps ");
19626 opnd_array(0)->int_format(ra, this, st); // dst
19627 st->print_raw(",");
19628 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19629 st->print_raw(",");
19630 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19631 st->print_raw("\t! add packed16F");
19632}
19633#endif
19634#ifndef PRODUCT
19635void vadd16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19636 // Start at oper_input_base() and count operands
19637 unsigned idx0 = 2;
19638 unsigned idx1 = 2; // src
19639 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19640 st->print_raw("vaddps ");
19641 opnd_array(0)->int_format(ra, this, st); // dst
19642 st->print_raw(",");
19643 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19644 st->print_raw(",");
19645 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19646 st->print_raw("\t! add packed16F");
19647}
19648#endif
19649#ifndef PRODUCT
19650void vadd16F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19651 // Start at oper_input_base() and count operands
19652 unsigned idx0 = 2;
19653 unsigned idx1 = 2; // mem
19654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19655 st->print_raw("vaddps ");
19656 opnd_array(0)->int_format(ra, this, st); // dst
19657 st->print_raw(",");
19658 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19659 st->print_raw(",");
19660 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19661 st->print_raw("\t! add packed16F");
19662}
19663#endif
19664#ifndef PRODUCT
19665void vadd2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19666 // Start at oper_input_base() and count operands
19667 unsigned idx0 = 1;
19668 unsigned idx1 = 1; // dst
19669 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19670 st->print_raw("addpd ");
19671 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19672 st->print_raw(",");
19673 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19674 st->print_raw("\t! add packed2D");
19675}
19676#endif
19677#ifndef PRODUCT
19678void vadd2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19679 // Start at oper_input_base() and count operands
19680 unsigned idx0 = 1;
19681 unsigned idx1 = 1; // src1
19682 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19683 st->print_raw("vaddpd ");
19684 opnd_array(0)->int_format(ra, this, st); // dst
19685 st->print_raw(",");
19686 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19687 st->print_raw(",");
19688 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19689 st->print_raw("\t! add packed2D");
19690}
19691#endif
19692#ifndef PRODUCT
19693void vadd2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19694 // Start at oper_input_base() and count operands
19695 unsigned idx0 = 2;
19696 unsigned idx1 = 2; // src
19697 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19698 st->print_raw("vaddpd ");
19699 opnd_array(0)->int_format(ra, this, st); // dst
19700 st->print_raw(",");
19701 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19702 st->print_raw(",");
19703 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19704 st->print_raw("\t! add packed2D");
19705}
19706#endif
19707#ifndef PRODUCT
19708void vadd2D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19709 // Start at oper_input_base() and count operands
19710 unsigned idx0 = 2;
19711 unsigned idx1 = 2; // mem
19712 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19713 st->print_raw("vaddpd ");
19714 opnd_array(0)->int_format(ra, this, st); // dst
19715 st->print_raw(",");
19716 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19717 st->print_raw(",");
19718 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19719 st->print_raw("\t! add packed2D");
19720}
19721#endif
19722#ifndef PRODUCT
19723void vadd4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19724 // Start at oper_input_base() and count operands
19725 unsigned idx0 = 1;
19726 unsigned idx1 = 1; // src1
19727 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19728 st->print_raw("vaddpd ");
19729 opnd_array(0)->int_format(ra, this, st); // dst
19730 st->print_raw(",");
19731 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19732 st->print_raw(",");
19733 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19734 st->print_raw("\t! add packed4D");
19735}
19736#endif
19737#ifndef PRODUCT
19738void vadd4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19739 // Start at oper_input_base() and count operands
19740 unsigned idx0 = 2;
19741 unsigned idx1 = 2; // src
19742 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19743 st->print_raw("vaddpd ");
19744 opnd_array(0)->int_format(ra, this, st); // dst
19745 st->print_raw(",");
19746 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19747 st->print_raw(",");
19748 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19749 st->print_raw("\t! add packed4D");
19750}
19751#endif
19752#ifndef PRODUCT
19753void vadd4D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19754 // Start at oper_input_base() and count operands
19755 unsigned idx0 = 2;
19756 unsigned idx1 = 2; // mem
19757 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19758 st->print_raw("vaddpd ");
19759 opnd_array(0)->int_format(ra, this, st); // dst
19760 st->print_raw(",");
19761 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19762 st->print_raw(",");
19763 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19764 st->print_raw("\t! add packed4D");
19765}
19766#endif
19767#ifndef PRODUCT
19768void vadd8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19769 // Start at oper_input_base() and count operands
19770 unsigned idx0 = 1;
19771 unsigned idx1 = 1; // src1
19772 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19773 st->print_raw("vaddpd ");
19774 opnd_array(0)->int_format(ra, this, st); // dst
19775 st->print_raw(",");
19776 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19777 st->print_raw(",");
19778 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19779 st->print_raw("\t! add packed8D");
19780}
19781#endif
19782#ifndef PRODUCT
19783void vadd8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19784 // Start at oper_input_base() and count operands
19785 unsigned idx0 = 2;
19786 unsigned idx1 = 2; // src
19787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19788 st->print_raw("vaddpd ");
19789 opnd_array(0)->int_format(ra, this, st); // dst
19790 st->print_raw(",");
19791 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19792 st->print_raw(",");
19793 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19794 st->print_raw("\t! add packed8D");
19795}
19796#endif
19797#ifndef PRODUCT
19798void vadd8D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
19799 // Start at oper_input_base() and count operands
19800 unsigned idx0 = 2;
19801 unsigned idx1 = 2; // mem
19802 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19803 st->print_raw("vaddpd ");
19804 opnd_array(0)->int_format(ra, this, st); // dst
19805 st->print_raw(",");
19806 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19807 st->print_raw(",");
19808 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
19809 st->print_raw("\t! add packed8D");
19810}
19811#endif
19812#ifndef PRODUCT
19813void vsub4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19814 // Start at oper_input_base() and count operands
19815 unsigned idx0 = 1;
19816 unsigned idx1 = 1; // dst
19817 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19818 st->print_raw("psubb ");
19819 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19820 st->print_raw(",");
19821 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19822 st->print_raw("\t! sub packed4B");
19823}
19824#endif
19825#ifndef PRODUCT
19826void vsub4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19827 // Start at oper_input_base() and count operands
19828 unsigned idx0 = 1;
19829 unsigned idx1 = 1; // src1
19830 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19831 st->print_raw("vpsubb ");
19832 opnd_array(0)->int_format(ra, this, st); // dst
19833 st->print_raw(",");
19834 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19835 st->print_raw(",");
19836 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19837 st->print_raw("\t! sub packed4B");
19838}
19839#endif
19840#ifndef PRODUCT
19841void vsub4B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19842 // Start at oper_input_base() and count operands
19843 unsigned idx0 = 2;
19844 unsigned idx1 = 2; // src
19845 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19846 st->print_raw("vpsubb ");
19847 opnd_array(0)->int_format(ra, this, st); // dst
19848 st->print_raw(",");
19849 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19850 st->print_raw(",");
19851 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19852 st->print_raw("\t! sub packed4B");
19853}
19854#endif
19855#ifndef PRODUCT
19856void vsub8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19857 // Start at oper_input_base() and count operands
19858 unsigned idx0 = 1;
19859 unsigned idx1 = 1; // dst
19860 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19861 st->print_raw("psubb ");
19862 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19863 st->print_raw(",");
19864 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19865 st->print_raw("\t! sub packed8B");
19866}
19867#endif
19868#ifndef PRODUCT
19869void vsub8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19870 // Start at oper_input_base() and count operands
19871 unsigned idx0 = 1;
19872 unsigned idx1 = 1; // src1
19873 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19874 st->print_raw("vpsubb ");
19875 opnd_array(0)->int_format(ra, this, st); // dst
19876 st->print_raw(",");
19877 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19878 st->print_raw(",");
19879 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19880 st->print_raw("\t! sub packed8B");
19881}
19882#endif
19883#ifndef PRODUCT
19884void vsub8B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19885 // Start at oper_input_base() and count operands
19886 unsigned idx0 = 2;
19887 unsigned idx1 = 2; // src
19888 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19889 st->print_raw("vpsubb ");
19890 opnd_array(0)->int_format(ra, this, st); // dst
19891 st->print_raw(",");
19892 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19893 st->print_raw(",");
19894 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19895 st->print_raw("\t! sub packed8B");
19896}
19897#endif
19898#ifndef PRODUCT
19899void vsub16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19900 // Start at oper_input_base() and count operands
19901 unsigned idx0 = 1;
19902 unsigned idx1 = 1; // dst
19903 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
19904 st->print_raw("psubb ");
19905 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
19906 st->print_raw(",");
19907 opnd_array(2)->ext_format(ra, this,idx2, st); // src
19908 st->print_raw("\t! sub packed16B");
19909}
19910#endif
19911#ifndef PRODUCT
19912void vsub16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19913 // Start at oper_input_base() and count operands
19914 unsigned idx0 = 1;
19915 unsigned idx1 = 1; // src1
19916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19917 st->print_raw("vpsubb ");
19918 opnd_array(0)->int_format(ra, this, st); // dst
19919 st->print_raw(",");
19920 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19921 st->print_raw(",");
19922 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19923 st->print_raw("\t! sub packed16B");
19924}
19925#endif
19926#ifndef PRODUCT
19927void vsub16B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19928 // Start at oper_input_base() and count operands
19929 unsigned idx0 = 2;
19930 unsigned idx1 = 2; // src
19931 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19932 st->print_raw("vpsubb ");
19933 opnd_array(0)->int_format(ra, this, st); // dst
19934 st->print_raw(",");
19935 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19936 st->print_raw(",");
19937 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19938 st->print_raw("\t! sub packed16B");
19939}
19940#endif
19941#ifndef PRODUCT
19942void vsub32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19943 // Start at oper_input_base() and count operands
19944 unsigned idx0 = 1;
19945 unsigned idx1 = 1; // src1
19946 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19947 st->print_raw("vpsubb ");
19948 opnd_array(0)->int_format(ra, this, st); // dst
19949 st->print_raw(",");
19950 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19951 st->print_raw(",");
19952 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19953 st->print_raw("\t! sub packed32B");
19954}
19955#endif
19956#ifndef PRODUCT
19957void vsub32B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19958 // Start at oper_input_base() and count operands
19959 unsigned idx0 = 2;
19960 unsigned idx1 = 2; // src
19961 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19962 st->print_raw("vpsubb ");
19963 opnd_array(0)->int_format(ra, this, st); // dst
19964 st->print_raw(",");
19965 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19966 st->print_raw(",");
19967 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19968 st->print_raw("\t! sub packed32B");
19969}
19970#endif
19971#ifndef PRODUCT
19972void vsub64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19973 // Start at oper_input_base() and count operands
19974 unsigned idx0 = 1;
19975 unsigned idx1 = 1; // src1
19976 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
19977 st->print_raw("vpsubb ");
19978 opnd_array(0)->int_format(ra, this, st); // dst
19979 st->print_raw(",");
19980 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
19981 st->print_raw(",");
19982 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
19983 st->print_raw("\t! sub packed64B");
19984}
19985#endif
19986#ifndef PRODUCT
19987void vsub64B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
19988 // Start at oper_input_base() and count operands
19989 unsigned idx0 = 2;
19990 unsigned idx1 = 2; // src
19991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
19992 st->print_raw("vpsubb ");
19993 opnd_array(0)->int_format(ra, this, st); // dst
19994 st->print_raw(",");
19995 opnd_array(1)->ext_format(ra, this,idx1, st); // src
19996 st->print_raw(",");
19997 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
19998 st->print_raw("\t! sub packed64B");
19999}
20000#endif
20001#ifndef PRODUCT
20002void vsub2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20003 // Start at oper_input_base() and count operands
20004 unsigned idx0 = 1;
20005 unsigned idx1 = 1; // dst
20006 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20007 st->print_raw("psubw ");
20008 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20009 st->print_raw(",");
20010 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20011 st->print_raw("\t! sub packed2S");
20012}
20013#endif
20014#ifndef PRODUCT
20015void vsub2S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20016 // Start at oper_input_base() and count operands
20017 unsigned idx0 = 1;
20018 unsigned idx1 = 1; // src1
20019 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20020 st->print_raw("vpsubw ");
20021 opnd_array(0)->int_format(ra, this, st); // dst
20022 st->print_raw(",");
20023 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20024 st->print_raw(",");
20025 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20026 st->print_raw("\t! sub packed2S");
20027}
20028#endif
20029#ifndef PRODUCT
20030void vsub2S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20031 // Start at oper_input_base() and count operands
20032 unsigned idx0 = 2;
20033 unsigned idx1 = 2; // src
20034 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20035 st->print_raw("vpsubw ");
20036 opnd_array(0)->int_format(ra, this, st); // dst
20037 st->print_raw(",");
20038 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20039 st->print_raw(",");
20040 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20041 st->print_raw("\t! sub packed2S");
20042}
20043#endif
20044#ifndef PRODUCT
20045void vsub4SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20046 // Start at oper_input_base() and count operands
20047 unsigned idx0 = 1;
20048 unsigned idx1 = 1; // dst
20049 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20050 st->print_raw("psubw ");
20051 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20052 st->print_raw(",");
20053 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20054 st->print_raw("\t! sub packed4S");
20055}
20056#endif
20057#ifndef PRODUCT
20058void vsub4S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20059 // Start at oper_input_base() and count operands
20060 unsigned idx0 = 1;
20061 unsigned idx1 = 1; // src1
20062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20063 st->print_raw("vpsubw ");
20064 opnd_array(0)->int_format(ra, this, st); // dst
20065 st->print_raw(",");
20066 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20067 st->print_raw(",");
20068 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20069 st->print_raw("\t! sub packed4S");
20070}
20071#endif
20072#ifndef PRODUCT
20073void vsub4S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20074 // Start at oper_input_base() and count operands
20075 unsigned idx0 = 2;
20076 unsigned idx1 = 2; // src
20077 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20078 st->print_raw("vpsubw ");
20079 opnd_array(0)->int_format(ra, this, st); // dst
20080 st->print_raw(",");
20081 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20082 st->print_raw(",");
20083 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20084 st->print_raw("\t! sub packed4S");
20085}
20086#endif
20087#ifndef PRODUCT
20088void vsub8SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20089 // Start at oper_input_base() and count operands
20090 unsigned idx0 = 1;
20091 unsigned idx1 = 1; // dst
20092 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20093 st->print_raw("psubw ");
20094 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20095 st->print_raw(",");
20096 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20097 st->print_raw("\t! sub packed8S");
20098}
20099#endif
20100#ifndef PRODUCT
20101void vsub8S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20102 // Start at oper_input_base() and count operands
20103 unsigned idx0 = 1;
20104 unsigned idx1 = 1; // src1
20105 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20106 st->print_raw("vpsubw ");
20107 opnd_array(0)->int_format(ra, this, st); // dst
20108 st->print_raw(",");
20109 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20110 st->print_raw(",");
20111 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20112 st->print_raw("\t! sub packed8S");
20113}
20114#endif
20115#ifndef PRODUCT
20116void vsub8S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20117 // Start at oper_input_base() and count operands
20118 unsigned idx0 = 2;
20119 unsigned idx1 = 2; // src
20120 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20121 st->print_raw("vpsubw ");
20122 opnd_array(0)->int_format(ra, this, st); // dst
20123 st->print_raw(",");
20124 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20125 st->print_raw(",");
20126 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20127 st->print_raw("\t! sub packed8S");
20128}
20129#endif
20130#ifndef PRODUCT
20131void vsub16S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20132 // Start at oper_input_base() and count operands
20133 unsigned idx0 = 1;
20134 unsigned idx1 = 1; // src1
20135 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20136 st->print_raw("vpsubw ");
20137 opnd_array(0)->int_format(ra, this, st); // dst
20138 st->print_raw(",");
20139 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20140 st->print_raw(",");
20141 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20142 st->print_raw("\t! sub packed16S");
20143}
20144#endif
20145#ifndef PRODUCT
20146void vsub16S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20147 // Start at oper_input_base() and count operands
20148 unsigned idx0 = 2;
20149 unsigned idx1 = 2; // src
20150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20151 st->print_raw("vpsubw ");
20152 opnd_array(0)->int_format(ra, this, st); // dst
20153 st->print_raw(",");
20154 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20155 st->print_raw(",");
20156 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20157 st->print_raw("\t! sub packed16S");
20158}
20159#endif
20160#ifndef PRODUCT
20161void vsub32S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20162 // Start at oper_input_base() and count operands
20163 unsigned idx0 = 1;
20164 unsigned idx1 = 1; // src1
20165 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20166 st->print_raw("vpsubw ");
20167 opnd_array(0)->int_format(ra, this, st); // dst
20168 st->print_raw(",");
20169 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20170 st->print_raw(",");
20171 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20172 st->print_raw("\t! sub packed32S");
20173}
20174#endif
20175#ifndef PRODUCT
20176void vsub32S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20177 // Start at oper_input_base() and count operands
20178 unsigned idx0 = 2;
20179 unsigned idx1 = 2; // src
20180 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20181 st->print_raw("vpsubw ");
20182 opnd_array(0)->int_format(ra, this, st); // dst
20183 st->print_raw(",");
20184 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20185 st->print_raw(",");
20186 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20187 st->print_raw("\t! sub packed32S");
20188}
20189#endif
20190#ifndef PRODUCT
20191void vsub2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
20192 // Start at oper_input_base() and count operands
20193 unsigned idx0 = 1;
20194 unsigned idx1 = 1; // dst
20195 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20196 st->print_raw("psubd ");
20197 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20198 st->print_raw(",");
20199 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20200 st->print_raw("\t! sub packed2I");
20201}
20202#endif
20203#ifndef PRODUCT
20204void vsub2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20205 // Start at oper_input_base() and count operands
20206 unsigned idx0 = 1;
20207 unsigned idx1 = 1; // src1
20208 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20209 st->print_raw("vpsubd ");
20210 opnd_array(0)->int_format(ra, this, st); // dst
20211 st->print_raw(",");
20212 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20213 st->print_raw(",");
20214 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20215 st->print_raw("\t! sub packed2I");
20216}
20217#endif
20218#ifndef PRODUCT
20219void vsub2I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20220 // Start at oper_input_base() and count operands
20221 unsigned idx0 = 2;
20222 unsigned idx1 = 2; // src
20223 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20224 st->print_raw("vpsubd ");
20225 opnd_array(0)->int_format(ra, this, st); // dst
20226 st->print_raw(",");
20227 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20228 st->print_raw(",");
20229 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20230 st->print_raw("\t! sub packed2I");
20231}
20232#endif
20233#ifndef PRODUCT
20234void vsub4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
20235 // Start at oper_input_base() and count operands
20236 unsigned idx0 = 1;
20237 unsigned idx1 = 1; // dst
20238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20239 st->print_raw("psubd ");
20240 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20241 st->print_raw(",");
20242 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20243 st->print_raw("\t! sub packed4I");
20244}
20245#endif
20246#ifndef PRODUCT
20247void vsub4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20248 // Start at oper_input_base() and count operands
20249 unsigned idx0 = 1;
20250 unsigned idx1 = 1; // src1
20251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20252 st->print_raw("vpsubd ");
20253 opnd_array(0)->int_format(ra, this, st); // dst
20254 st->print_raw(",");
20255 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20256 st->print_raw(",");
20257 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20258 st->print_raw("\t! sub packed4I");
20259}
20260#endif
20261#ifndef PRODUCT
20262void vsub4I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20263 // Start at oper_input_base() and count operands
20264 unsigned idx0 = 2;
20265 unsigned idx1 = 2; // src
20266 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20267 st->print_raw("vpsubd ");
20268 opnd_array(0)->int_format(ra, this, st); // dst
20269 st->print_raw(",");
20270 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20271 st->print_raw(",");
20272 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20273 st->print_raw("\t! sub packed4I");
20274}
20275#endif
20276#ifndef PRODUCT
20277void vsub8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20278 // Start at oper_input_base() and count operands
20279 unsigned idx0 = 1;
20280 unsigned idx1 = 1; // src1
20281 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20282 st->print_raw("vpsubd ");
20283 opnd_array(0)->int_format(ra, this, st); // dst
20284 st->print_raw(",");
20285 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20286 st->print_raw(",");
20287 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20288 st->print_raw("\t! sub packed8I");
20289}
20290#endif
20291#ifndef PRODUCT
20292void vsub8I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20293 // Start at oper_input_base() and count operands
20294 unsigned idx0 = 2;
20295 unsigned idx1 = 2; // src
20296 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20297 st->print_raw("vpsubd ");
20298 opnd_array(0)->int_format(ra, this, st); // dst
20299 st->print_raw(",");
20300 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20301 st->print_raw(",");
20302 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20303 st->print_raw("\t! sub packed8I");
20304}
20305#endif
20306#ifndef PRODUCT
20307void vsub16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20308 // Start at oper_input_base() and count operands
20309 unsigned idx0 = 1;
20310 unsigned idx1 = 1; // src1
20311 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20312 st->print_raw("vpsubd ");
20313 opnd_array(0)->int_format(ra, this, st); // dst
20314 st->print_raw(",");
20315 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20316 st->print_raw(",");
20317 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20318 st->print_raw("\t! sub packed16I");
20319}
20320#endif
20321#ifndef PRODUCT
20322void vsub16I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20323 // Start at oper_input_base() and count operands
20324 unsigned idx0 = 2;
20325 unsigned idx1 = 2; // src
20326 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20327 st->print_raw("vpsubd ");
20328 opnd_array(0)->int_format(ra, this, st); // dst
20329 st->print_raw(",");
20330 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20331 st->print_raw(",");
20332 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20333 st->print_raw("\t! sub packed16I");
20334}
20335#endif
20336#ifndef PRODUCT
20337void vsub2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20338 // Start at oper_input_base() and count operands
20339 unsigned idx0 = 1;
20340 unsigned idx1 = 1; // dst
20341 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20342 st->print_raw("psubq ");
20343 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20344 st->print_raw(",");
20345 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20346 st->print_raw("\t! sub packed2L");
20347}
20348#endif
20349#ifndef PRODUCT
20350void vsub2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20351 // Start at oper_input_base() and count operands
20352 unsigned idx0 = 1;
20353 unsigned idx1 = 1; // src1
20354 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20355 st->print_raw("vpsubq ");
20356 opnd_array(0)->int_format(ra, this, st); // dst
20357 st->print_raw(",");
20358 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20359 st->print_raw(",");
20360 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20361 st->print_raw("\t! sub packed2L");
20362}
20363#endif
20364#ifndef PRODUCT
20365void vsub2L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20366 // Start at oper_input_base() and count operands
20367 unsigned idx0 = 2;
20368 unsigned idx1 = 2; // src
20369 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20370 st->print_raw("vpsubq ");
20371 opnd_array(0)->int_format(ra, this, st); // dst
20372 st->print_raw(",");
20373 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20374 st->print_raw(",");
20375 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20376 st->print_raw("\t! sub packed2L");
20377}
20378#endif
20379#ifndef PRODUCT
20380void vsub4L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20381 // Start at oper_input_base() and count operands
20382 unsigned idx0 = 1;
20383 unsigned idx1 = 1; // src1
20384 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20385 st->print_raw("vpsubq ");
20386 opnd_array(0)->int_format(ra, this, st); // dst
20387 st->print_raw(",");
20388 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20389 st->print_raw(",");
20390 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20391 st->print_raw("\t! sub packed4L");
20392}
20393#endif
20394#ifndef PRODUCT
20395void vsub4L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20396 // Start at oper_input_base() and count operands
20397 unsigned idx0 = 2;
20398 unsigned idx1 = 2; // src
20399 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20400 st->print_raw("vpsubq ");
20401 opnd_array(0)->int_format(ra, this, st); // dst
20402 st->print_raw(",");
20403 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20404 st->print_raw(",");
20405 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20406 st->print_raw("\t! sub packed4L");
20407}
20408#endif
20409#ifndef PRODUCT
20410void vsub8L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20411 // Start at oper_input_base() and count operands
20412 unsigned idx0 = 1;
20413 unsigned idx1 = 1; // src1
20414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20415 st->print_raw("vpsubq ");
20416 opnd_array(0)->int_format(ra, this, st); // dst
20417 st->print_raw(",");
20418 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20419 st->print_raw(",");
20420 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20421 st->print_raw("\t! sub packed8L");
20422}
20423#endif
20424#ifndef PRODUCT
20425void vsub8L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20426 // Start at oper_input_base() and count operands
20427 unsigned idx0 = 2;
20428 unsigned idx1 = 2; // src
20429 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20430 st->print_raw("vpsubq ");
20431 opnd_array(0)->int_format(ra, this, st); // dst
20432 st->print_raw(",");
20433 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20434 st->print_raw(",");
20435 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20436 st->print_raw("\t! sub packed8L");
20437}
20438#endif
20439#ifndef PRODUCT
20440void vsub2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20441 // Start at oper_input_base() and count operands
20442 unsigned idx0 = 1;
20443 unsigned idx1 = 1; // dst
20444 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20445 st->print_raw("subps ");
20446 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20447 st->print_raw(",");
20448 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20449 st->print_raw("\t! sub packed2F");
20450}
20451#endif
20452#ifndef PRODUCT
20453void vsub2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20454 // Start at oper_input_base() and count operands
20455 unsigned idx0 = 1;
20456 unsigned idx1 = 1; // src1
20457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20458 st->print_raw("vsubps ");
20459 opnd_array(0)->int_format(ra, this, st); // dst
20460 st->print_raw(",");
20461 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20462 st->print_raw(",");
20463 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20464 st->print_raw("\t! sub packed2F");
20465}
20466#endif
20467#ifndef PRODUCT
20468void vsub2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20469 // Start at oper_input_base() and count operands
20470 unsigned idx0 = 2;
20471 unsigned idx1 = 2; // src
20472 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20473 st->print_raw("vsubps ");
20474 opnd_array(0)->int_format(ra, this, st); // dst
20475 st->print_raw(",");
20476 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20477 st->print_raw(",");
20478 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20479 st->print_raw("\t! sub packed2F");
20480}
20481#endif
20482#ifndef PRODUCT
20483void vsub4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20484 // Start at oper_input_base() and count operands
20485 unsigned idx0 = 1;
20486 unsigned idx1 = 1; // dst
20487 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20488 st->print_raw("subps ");
20489 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20490 st->print_raw(",");
20491 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20492 st->print_raw("\t! sub packed4F");
20493}
20494#endif
20495#ifndef PRODUCT
20496void vsub4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20497 // Start at oper_input_base() and count operands
20498 unsigned idx0 = 1;
20499 unsigned idx1 = 1; // src1
20500 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20501 st->print_raw("vsubps ");
20502 opnd_array(0)->int_format(ra, this, st); // dst
20503 st->print_raw(",");
20504 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20505 st->print_raw(",");
20506 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20507 st->print_raw("\t! sub packed4F");
20508}
20509#endif
20510#ifndef PRODUCT
20511void vsub4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20512 // Start at oper_input_base() and count operands
20513 unsigned idx0 = 2;
20514 unsigned idx1 = 2; // src
20515 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20516 st->print_raw("vsubps ");
20517 opnd_array(0)->int_format(ra, this, st); // dst
20518 st->print_raw(",");
20519 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20520 st->print_raw(",");
20521 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20522 st->print_raw("\t! sub packed4F");
20523}
20524#endif
20525#ifndef PRODUCT
20526void vsub8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20527 // Start at oper_input_base() and count operands
20528 unsigned idx0 = 1;
20529 unsigned idx1 = 1; // src1
20530 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20531 st->print_raw("vsubps ");
20532 opnd_array(0)->int_format(ra, this, st); // dst
20533 st->print_raw(",");
20534 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20535 st->print_raw(",");
20536 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20537 st->print_raw("\t! sub packed8F");
20538}
20539#endif
20540#ifndef PRODUCT
20541void vsub8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20542 // Start at oper_input_base() and count operands
20543 unsigned idx0 = 2;
20544 unsigned idx1 = 2; // src
20545 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20546 st->print_raw("vsubps ");
20547 opnd_array(0)->int_format(ra, this, st); // dst
20548 st->print_raw(",");
20549 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20550 st->print_raw(",");
20551 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20552 st->print_raw("\t! sub packed8F");
20553}
20554#endif
20555#ifndef PRODUCT
20556void vsub16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20557 // Start at oper_input_base() and count operands
20558 unsigned idx0 = 1;
20559 unsigned idx1 = 1; // src1
20560 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20561 st->print_raw("vsubps ");
20562 opnd_array(0)->int_format(ra, this, st); // dst
20563 st->print_raw(",");
20564 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20565 st->print_raw(",");
20566 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20567 st->print_raw("\t! sub packed16F");
20568}
20569#endif
20570#ifndef PRODUCT
20571void vsub16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20572 // Start at oper_input_base() and count operands
20573 unsigned idx0 = 2;
20574 unsigned idx1 = 2; // src
20575 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20576 st->print_raw("vsubps ");
20577 opnd_array(0)->int_format(ra, this, st); // dst
20578 st->print_raw(",");
20579 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20580 st->print_raw(",");
20581 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20582 st->print_raw("\t! sub packed16F");
20583}
20584#endif
20585#ifndef PRODUCT
20586void vsub2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20587 // Start at oper_input_base() and count operands
20588 unsigned idx0 = 1;
20589 unsigned idx1 = 1; // dst
20590 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20591 st->print_raw("subpd ");
20592 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
20593 st->print_raw(",");
20594 opnd_array(2)->ext_format(ra, this,idx2, st); // src
20595 st->print_raw("\t! sub packed2D");
20596}
20597#endif
20598#ifndef PRODUCT
20599void vsub2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20600 // Start at oper_input_base() and count operands
20601 unsigned idx0 = 1;
20602 unsigned idx1 = 1; // src1
20603 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20604 st->print_raw("vsubpd ");
20605 opnd_array(0)->int_format(ra, this, st); // dst
20606 st->print_raw(",");
20607 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20608 st->print_raw(",");
20609 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20610 st->print_raw("\t! sub packed2D");
20611}
20612#endif
20613#ifndef PRODUCT
20614void vsub2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20615 // Start at oper_input_base() and count operands
20616 unsigned idx0 = 2;
20617 unsigned idx1 = 2; // src
20618 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20619 st->print_raw("vsubpd ");
20620 opnd_array(0)->int_format(ra, this, st); // dst
20621 st->print_raw(",");
20622 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20623 st->print_raw(",");
20624 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20625 st->print_raw("\t! sub packed2D");
20626}
20627#endif
20628#ifndef PRODUCT
20629void vsub4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20630 // Start at oper_input_base() and count operands
20631 unsigned idx0 = 1;
20632 unsigned idx1 = 1; // src1
20633 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20634 st->print_raw("vsubpd ");
20635 opnd_array(0)->int_format(ra, this, st); // dst
20636 st->print_raw(",");
20637 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20638 st->print_raw(",");
20639 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20640 st->print_raw("\t! sub packed4D");
20641}
20642#endif
20643#ifndef PRODUCT
20644void vsub4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20645 // Start at oper_input_base() and count operands
20646 unsigned idx0 = 2;
20647 unsigned idx1 = 2; // src
20648 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20649 st->print_raw("vsubpd ");
20650 opnd_array(0)->int_format(ra, this, st); // dst
20651 st->print_raw(",");
20652 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20653 st->print_raw(",");
20654 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20655 st->print_raw("\t! sub packed4D");
20656}
20657#endif
20658#ifndef PRODUCT
20659void vsub8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20660 // Start at oper_input_base() and count operands
20661 unsigned idx0 = 1;
20662 unsigned idx1 = 1; // src1
20663 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20664 st->print_raw("vsubpd ");
20665 opnd_array(0)->int_format(ra, this, st); // dst
20666 st->print_raw(",");
20667 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20668 st->print_raw(",");
20669 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20670 st->print_raw("\t! sub packed8D");
20671}
20672#endif
20673#ifndef PRODUCT
20674void vsub8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20675 // Start at oper_input_base() and count operands
20676 unsigned idx0 = 2;
20677 unsigned idx1 = 2; // src
20678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
20679 st->print_raw("vsubpd ");
20680 opnd_array(0)->int_format(ra, this, st); // dst
20681 st->print_raw(",");
20682 opnd_array(1)->ext_format(ra, this,idx1, st); // src
20683 st->print_raw(",");
20684 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
20685 st->print_raw("\t! sub packed8D");
20686}
20687#endif
20688#ifndef PRODUCT
20689void mul4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20690 // Start at oper_input_base() and count operands
20691 unsigned idx0 = 1;
20692 unsigned idx1 = 1; // src1
20693 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20694 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20695 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
20696 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
20697 st->print_raw("pmovsxbw ");
20698 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20699 st->print_raw(",");
20700 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20701 st->print_raw("\n\t");
20702 st->print_raw("pmovsxbw ");
20703 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20704 st->print_raw(",");
20705 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20706 st->print_raw("\n\t");
20707 st->print_raw("pmullw ");
20708 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20709 st->print_raw(",");
20710 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20711 st->print_raw("\n\t");
20712 st->print_raw("movdqu ");
20713 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20714 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
20715 st->print_raw("pand ");
20716 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20717 st->print_raw(",");
20718 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20719 st->print_raw("\n\t");
20720 st->print_raw("packuswb ");
20721 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20722 st->print_raw(",");
20723 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20724 st->print_raw("\t! mul packed4B");
20725}
20726#endif
20727#ifndef PRODUCT
20728void mul8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20729 // Start at oper_input_base() and count operands
20730 unsigned idx0 = 1;
20731 unsigned idx1 = 1; // src1
20732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20733 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20734 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
20735 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
20736 st->print_raw("pmovsxbw ");
20737 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20738 st->print_raw(",");
20739 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20740 st->print_raw("\n\t");
20741 st->print_raw("pmovsxbw ");
20742 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20743 st->print_raw(",");
20744 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20745 st->print_raw("\n\t");
20746 st->print_raw("pmullw ");
20747 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20748 st->print_raw(",");
20749 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20750 st->print_raw("\n\t");
20751 st->print_raw("movdqu ");
20752 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20753 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
20754 st->print_raw("pand ");
20755 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20756 st->print_raw(",");
20757 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20758 st->print_raw("\n\t");
20759 st->print_raw("packuswb ");
20760 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20761 st->print_raw(",");
20762 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20763 st->print_raw("\t! mul packed8B");
20764}
20765#endif
20766#ifndef PRODUCT
20767void mul16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20768 // Start at oper_input_base() and count operands
20769 unsigned idx0 = 1;
20770 unsigned idx1 = 1; // src1
20771 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20772 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20773 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
20774 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
20775 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
20776 st->print_raw("pmovsxbw ");
20777 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20778 st->print_raw(",");
20779 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20780 st->print_raw("\n\t");
20781 st->print_raw("pmovsxbw ");
20782 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20783 st->print_raw(",");
20784 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20785 st->print_raw("\n\t");
20786 st->print_raw("pmullw ");
20787 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20788 st->print_raw(",");
20789 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20790 st->print_raw("\n\t");
20791 st->print_raw("pshufd ");
20792 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20793 st->print_raw(",");
20794 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20795 st->print_raw(",0xEE\n\t");
20796 st->print_raw("pshufd ");
20797 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20798 st->print_raw(",");
20799 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20800 st->print_raw(",0xEE\n\t");
20801 st->print_raw("pmovsxbw ");
20802 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20803 st->print_raw(",");
20804 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20805 st->print_raw("\n\t");
20806 st->print_raw("pmovsxbw ");
20807 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20808 st->print_raw(",");
20809 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20810 st->print_raw("\n\t");
20811 st->print_raw("pmullw ");
20812 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20813 st->print_raw(",");
20814 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20815 st->print_raw("\n\t");
20816 st->print_raw("movdqu ");
20817 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20818 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
20819 st->print_raw("pand ");
20820 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20821 st->print_raw(",");
20822 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20823 st->print_raw("\n\t");
20824 st->print_raw("pand ");
20825 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20826 st->print_raw(",");
20827 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20828 st->print_raw("\n\t");
20829 st->print_raw("packuswb ");
20830 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20831 st->print_raw(",");
20832 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20833 st->print_raw("\t! mul packed16B");
20834}
20835#endif
20836#ifndef PRODUCT
20837void vmul16B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20838 // Start at oper_input_base() and count operands
20839 unsigned idx0 = 1;
20840 unsigned idx1 = 1; // src1
20841 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20842 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20843 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
20844 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
20845 st->print_raw("vpmovsxbw ");
20846 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20847 st->print_raw(",");
20848 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20849 st->print_raw("\n\t");
20850 st->print_raw("vpmovsxbw ");
20851 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20852 st->print_raw(",");
20853 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20854 st->print_raw("\n\t");
20855 st->print_raw("vpmullw ");
20856 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20857 st->print_raw(",");
20858 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20859 st->print_raw(",");
20860 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20861 st->print_raw("\n\t");
20862 st->print_raw("vmovdqu ");
20863 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20864 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
20865 st->print_raw("vpand ");
20866 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20867 st->print_raw(",");
20868 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20869 st->print_raw(",");
20870 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20871 st->print_raw("\n\t");
20872 st->print_raw("vextracti128_high ");
20873 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
20874 st->print_raw(",");
20875 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20876 st->print_raw("\n\t");
20877 st->print_raw("vpackuswb ");
20878 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20879 st->print_raw(",");
20880 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20881 st->print_raw(",");
20882 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20883 st->print_raw("\n\t! mul packed16B");
20884}
20885#endif
20886#ifndef PRODUCT
20887void vmul32B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20888 // Start at oper_input_base() and count operands
20889 unsigned idx0 = 1;
20890 unsigned idx1 = 1; // src1
20891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20893 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
20894 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
20895 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
20896 st->print_raw("vextracti128_high ");
20897 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20898 st->print_raw(",");
20899 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20900 st->print_raw("\n\t");
20901 st->print_raw("vextracti128_high ");
20902 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20903 st->print_raw(",");
20904 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20905 st->print_raw("\n\t");
20906 st->print_raw("vpmovsxbw ");
20907 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20908 st->print_raw(",");
20909 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20910 st->print_raw("\n\t");
20911 st->print_raw("vpmovsxbw ");
20912 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20913 st->print_raw(",");
20914 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20915 st->print_raw("\n\t");
20916 st->print_raw("vpmullw ");
20917 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20918 st->print_raw(",");
20919 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20920 st->print_raw(",");
20921 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20922 st->print_raw("\n\t");
20923 st->print_raw("vpmovsxbw ");
20924 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20925 st->print_raw(",");
20926 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20927 st->print_raw("\n\t");
20928 st->print_raw("vpmovsxbw ");
20929 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20930 st->print_raw(",");
20931 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20932 st->print_raw("\n\t");
20933 st->print_raw("vpmullw ");
20934 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20935 st->print_raw(",");
20936 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20937 st->print_raw(",");
20938 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20939 st->print_raw("\n\t");
20940 st->print_raw("vmovdqu ");
20941 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20942 st->print_raw(", [0x00ff00ff0x00ff00ff]\n\t");
20943 st->print_raw("vpbroadcastd ");
20944 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20945 st->print_raw(", ");
20946 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20947 st->print_raw("\n\t");
20948 st->print_raw("vpand ");
20949 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20950 st->print_raw(",");
20951 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20952 st->print_raw(",");
20953 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20954 st->print_raw("\n\t");
20955 st->print_raw("vpand ");
20956 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20957 st->print_raw(",");
20958 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20959 st->print_raw(",");
20960 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
20961 st->print_raw("\n\t");
20962 st->print_raw("vpackuswb ");
20963 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20964 st->print_raw(",");
20965 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20966 st->print_raw(",");
20967 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20968 st->print_raw("\n\t");
20969 st->print_raw("vpermq ");
20970 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20971 st->print_raw(", ");
20972 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20973 st->print_raw(", 0xD8\t! mul packed32B");
20974}
20975#endif
20976#ifndef PRODUCT
20977void vmul64B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
20978 // Start at oper_input_base() and count operands
20979 unsigned idx0 = 1;
20980 unsigned idx1 = 1; // src1
20981 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
20982 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
20983 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
20984 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
20985 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
20986 st->print_raw("vextracti64x4_high ");
20987 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20988 st->print_raw(",");
20989 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
20990 st->print_raw("\n\t");
20991 st->print_raw("vextracti64x4_high ");
20992 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
20993 st->print_raw(",");
20994 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
20995 st->print_raw("\n\t");
20996 st->print_raw("vpmovsxbw ");
20997 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
20998 st->print_raw(",");
20999 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21000 st->print_raw("\n\t");
21001 st->print_raw("vpmovsxbw ");
21002 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21003 st->print_raw(",");
21004 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21005 st->print_raw("\n\t");
21006 st->print_raw("vpmullw ");
21007 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21008 st->print_raw(",");
21009 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21010 st->print_raw(",");
21011 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21012 st->print_raw("\n\t");
21013 st->print_raw("vpmovsxbw ");
21014 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21015 st->print_raw(",");
21016 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21017 st->print_raw("\n\t");
21018 st->print_raw("vpmovsxbw ");
21019 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21020 st->print_raw(",");
21021 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21022 st->print_raw("\n\t");
21023 st->print_raw("vpmullw ");
21024 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21025 st->print_raw(",");
21026 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21027 st->print_raw(",");
21028 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21029 st->print_raw("\n\t");
21030 st->print_raw("vmovdqu ");
21031 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21032 st->print_raw(", [0x00ff00ff0x00ff00ff]\n\t");
21033 st->print_raw("vpbroadcastd ");
21034 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21035 st->print_raw(", ");
21036 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21037 st->print_raw("\n\t");
21038 st->print_raw("vpand ");
21039 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21040 st->print_raw(",");
21041 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21042 st->print_raw(",");
21043 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21044 st->print_raw("\n\t");
21045 st->print_raw("vpand ");
21046 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21047 st->print_raw(",");
21048 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21049 st->print_raw(",");
21050 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21051 st->print_raw("\n\t");
21052 st->print_raw("vpackuswb ");
21053 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21054 st->print_raw(",");
21055 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
21056 st->print_raw(",");
21057 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21058 st->print_raw("\n\t");
21059 st->print_raw("evmovdquq ");
21060 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21061 st->print_raw(",[0x0604020007050301]\n\t");
21062 st->print_raw("vpermq ");
21063 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21064 st->print_raw(",");
21065 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
21066 st->print_raw(",");
21067 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
21068 st->print_raw(",0x01\t! mul packed64B");
21069}
21070#endif
21071#ifndef PRODUCT
21072void vmul2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21073 // Start at oper_input_base() and count operands
21074 unsigned idx0 = 1;
21075 unsigned idx1 = 1; // dst
21076 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21077 st->print_raw("pmullw ");
21078 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21079 st->print_raw(",");
21080 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21081 st->print_raw("\t! mul packed2S");
21082}
21083#endif
21084#ifndef PRODUCT
21085void vmul2S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21086 // Start at oper_input_base() and count operands
21087 unsigned idx0 = 1;
21088 unsigned idx1 = 1; // src1
21089 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21090 st->print_raw("vpmullw ");
21091 opnd_array(0)->int_format(ra, this, st); // dst
21092 st->print_raw(",");
21093 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21094 st->print_raw(",");
21095 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21096 st->print_raw("\t! mul packed2S");
21097}
21098#endif
21099#ifndef PRODUCT
21100void vmul2S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21101 // Start at oper_input_base() and count operands
21102 unsigned idx0 = 2;
21103 unsigned idx1 = 2; // src
21104 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21105 st->print_raw("vpmullw ");
21106 opnd_array(0)->int_format(ra, this, st); // dst
21107 st->print_raw(",");
21108 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21109 st->print_raw(",");
21110 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21111 st->print_raw("\t! mul packed2S");
21112}
21113#endif
21114#ifndef PRODUCT
21115void vmul2S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21116 // Start at oper_input_base() and count operands
21117 unsigned idx0 = 2;
21118 unsigned idx1 = 2; // mem
21119 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21120 st->print_raw("vpmullw ");
21121 opnd_array(0)->int_format(ra, this, st); // dst
21122 st->print_raw(",");
21123 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21124 st->print_raw(",");
21125 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21126 st->print_raw("\t! mul packed2S");
21127}
21128#endif
21129#ifndef PRODUCT
21130void vmul4SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21131 // Start at oper_input_base() and count operands
21132 unsigned idx0 = 1;
21133 unsigned idx1 = 1; // dst
21134 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21135 st->print_raw("pmullw ");
21136 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21137 st->print_raw(",");
21138 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21139 st->print_raw("\t! mul packed4S");
21140}
21141#endif
21142#ifndef PRODUCT
21143void vmul4S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21144 // Start at oper_input_base() and count operands
21145 unsigned idx0 = 1;
21146 unsigned idx1 = 1; // src1
21147 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21148 st->print_raw("vpmullw ");
21149 opnd_array(0)->int_format(ra, this, st); // dst
21150 st->print_raw(",");
21151 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21152 st->print_raw(",");
21153 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21154 st->print_raw("\t! mul packed4S");
21155}
21156#endif
21157#ifndef PRODUCT
21158void vmul4S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21159 // Start at oper_input_base() and count operands
21160 unsigned idx0 = 2;
21161 unsigned idx1 = 2; // src
21162 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21163 st->print_raw("vpmullw ");
21164 opnd_array(0)->int_format(ra, this, st); // dst
21165 st->print_raw(",");
21166 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21167 st->print_raw(",");
21168 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21169 st->print_raw("\t! mul packed4S");
21170}
21171#endif
21172#ifndef PRODUCT
21173void vmul4S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21174 // Start at oper_input_base() and count operands
21175 unsigned idx0 = 2;
21176 unsigned idx1 = 2; // mem
21177 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21178 st->print_raw("vpmullw ");
21179 opnd_array(0)->int_format(ra, this, st); // dst
21180 st->print_raw(",");
21181 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21182 st->print_raw(",");
21183 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21184 st->print_raw("\t! mul packed4S");
21185}
21186#endif
21187#ifndef PRODUCT
21188void vmul8SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21189 // Start at oper_input_base() and count operands
21190 unsigned idx0 = 1;
21191 unsigned idx1 = 1; // dst
21192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21193 st->print_raw("pmullw ");
21194 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21195 st->print_raw(",");
21196 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21197 st->print_raw("\t! mul packed8S");
21198}
21199#endif
21200#ifndef PRODUCT
21201void vmul8S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21202 // Start at oper_input_base() and count operands
21203 unsigned idx0 = 1;
21204 unsigned idx1 = 1; // src1
21205 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21206 st->print_raw("vpmullw ");
21207 opnd_array(0)->int_format(ra, this, st); // dst
21208 st->print_raw(",");
21209 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21210 st->print_raw(",");
21211 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21212 st->print_raw("\t! mul packed8S");
21213}
21214#endif
21215#ifndef PRODUCT
21216void vmul8S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21217 // Start at oper_input_base() and count operands
21218 unsigned idx0 = 2;
21219 unsigned idx1 = 2; // src
21220 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21221 st->print_raw("vpmullw ");
21222 opnd_array(0)->int_format(ra, this, st); // dst
21223 st->print_raw(",");
21224 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21225 st->print_raw(",");
21226 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21227 st->print_raw("\t! mul packed8S");
21228}
21229#endif
21230#ifndef PRODUCT
21231void vmul8S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21232 // Start at oper_input_base() and count operands
21233 unsigned idx0 = 2;
21234 unsigned idx1 = 2; // mem
21235 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21236 st->print_raw("vpmullw ");
21237 opnd_array(0)->int_format(ra, this, st); // dst
21238 st->print_raw(",");
21239 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21240 st->print_raw(",");
21241 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21242 st->print_raw("\t! mul packed8S");
21243}
21244#endif
21245#ifndef PRODUCT
21246void vmul16S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21247 // Start at oper_input_base() and count operands
21248 unsigned idx0 = 1;
21249 unsigned idx1 = 1; // src1
21250 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21251 st->print_raw("vpmullw ");
21252 opnd_array(0)->int_format(ra, this, st); // dst
21253 st->print_raw(",");
21254 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21255 st->print_raw(",");
21256 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21257 st->print_raw("\t! mul packed16S");
21258}
21259#endif
21260#ifndef PRODUCT
21261void vmul16S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21262 // Start at oper_input_base() and count operands
21263 unsigned idx0 = 2;
21264 unsigned idx1 = 2; // src
21265 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21266 st->print_raw("vpmullw ");
21267 opnd_array(0)->int_format(ra, this, st); // dst
21268 st->print_raw(",");
21269 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21270 st->print_raw(",");
21271 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21272 st->print_raw("\t! mul packed16S");
21273}
21274#endif
21275#ifndef PRODUCT
21276void vmul16S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21277 // Start at oper_input_base() and count operands
21278 unsigned idx0 = 2;
21279 unsigned idx1 = 2; // mem
21280 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21281 st->print_raw("vpmullw ");
21282 opnd_array(0)->int_format(ra, this, st); // dst
21283 st->print_raw(",");
21284 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21285 st->print_raw(",");
21286 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21287 st->print_raw("\t! mul packed16S");
21288}
21289#endif
21290#ifndef PRODUCT
21291void vmul32S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21292 // Start at oper_input_base() and count operands
21293 unsigned idx0 = 1;
21294 unsigned idx1 = 1; // src1
21295 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21296 st->print_raw("vpmullw ");
21297 opnd_array(0)->int_format(ra, this, st); // dst
21298 st->print_raw(",");
21299 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21300 st->print_raw(",");
21301 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21302 st->print_raw("\t! mul packed32S");
21303}
21304#endif
21305#ifndef PRODUCT
21306void vmul32S_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21307 // Start at oper_input_base() and count operands
21308 unsigned idx0 = 2;
21309 unsigned idx1 = 2; // src
21310 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21311 st->print_raw("vpmullw ");
21312 opnd_array(0)->int_format(ra, this, st); // dst
21313 st->print_raw(",");
21314 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21315 st->print_raw(",");
21316 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21317 st->print_raw("\t! mul packed32S");
21318}
21319#endif
21320#ifndef PRODUCT
21321void vmul32S_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21322 // Start at oper_input_base() and count operands
21323 unsigned idx0 = 2;
21324 unsigned idx1 = 2; // mem
21325 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21326 st->print_raw("vpmullw ");
21327 opnd_array(0)->int_format(ra, this, st); // dst
21328 st->print_raw(",");
21329 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21330 st->print_raw(",");
21331 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21332 st->print_raw("\t! mul packed32S");
21333}
21334#endif
21335#ifndef PRODUCT
21336void vmul2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
21337 // Start at oper_input_base() and count operands
21338 unsigned idx0 = 1;
21339 unsigned idx1 = 1; // dst
21340 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21341 st->print_raw("pmulld ");
21342 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21343 st->print_raw(",");
21344 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21345 st->print_raw("\t! mul packed2I");
21346}
21347#endif
21348#ifndef PRODUCT
21349void vmul2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21350 // Start at oper_input_base() and count operands
21351 unsigned idx0 = 1;
21352 unsigned idx1 = 1; // src1
21353 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21354 st->print_raw("vpmulld ");
21355 opnd_array(0)->int_format(ra, this, st); // dst
21356 st->print_raw(",");
21357 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21358 st->print_raw(",");
21359 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21360 st->print_raw("\t! mul packed2I");
21361}
21362#endif
21363#ifndef PRODUCT
21364void vmul2I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21365 // Start at oper_input_base() and count operands
21366 unsigned idx0 = 2;
21367 unsigned idx1 = 2; // src
21368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21369 st->print_raw("vpmulld ");
21370 opnd_array(0)->int_format(ra, this, st); // dst
21371 st->print_raw(",");
21372 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21373 st->print_raw(",");
21374 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21375 st->print_raw("\t! mul packed2I");
21376}
21377#endif
21378#ifndef PRODUCT
21379void vmul2I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21380 // Start at oper_input_base() and count operands
21381 unsigned idx0 = 2;
21382 unsigned idx1 = 2; // mem
21383 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21384 st->print_raw("vpmulld ");
21385 opnd_array(0)->int_format(ra, this, st); // dst
21386 st->print_raw(",");
21387 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21388 st->print_raw(",");
21389 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21390 st->print_raw("\t! mul packed2I");
21391}
21392#endif
21393#ifndef PRODUCT
21394void vmul4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
21395 // Start at oper_input_base() and count operands
21396 unsigned idx0 = 1;
21397 unsigned idx1 = 1; // dst
21398 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21399 st->print_raw("pmulld ");
21400 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21401 st->print_raw(",");
21402 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21403 st->print_raw("\t! mul packed4I");
21404}
21405#endif
21406#ifndef PRODUCT
21407void vmul4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21408 // Start at oper_input_base() and count operands
21409 unsigned idx0 = 1;
21410 unsigned idx1 = 1; // src1
21411 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21412 st->print_raw("vpmulld ");
21413 opnd_array(0)->int_format(ra, this, st); // dst
21414 st->print_raw(",");
21415 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21416 st->print_raw(",");
21417 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21418 st->print_raw("\t! mul packed4I");
21419}
21420#endif
21421#ifndef PRODUCT
21422void vmul4I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21423 // Start at oper_input_base() and count operands
21424 unsigned idx0 = 2;
21425 unsigned idx1 = 2; // src
21426 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21427 st->print_raw("vpmulld ");
21428 opnd_array(0)->int_format(ra, this, st); // dst
21429 st->print_raw(",");
21430 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21431 st->print_raw(",");
21432 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21433 st->print_raw("\t! mul packed4I");
21434}
21435#endif
21436#ifndef PRODUCT
21437void vmul4I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21438 // Start at oper_input_base() and count operands
21439 unsigned idx0 = 2;
21440 unsigned idx1 = 2; // mem
21441 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21442 st->print_raw("vpmulld ");
21443 opnd_array(0)->int_format(ra, this, st); // dst
21444 st->print_raw(",");
21445 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21446 st->print_raw(",");
21447 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21448 st->print_raw("\t! mul packed4I");
21449}
21450#endif
21451#ifndef PRODUCT
21452void vmul2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21453 // Start at oper_input_base() and count operands
21454 unsigned idx0 = 1;
21455 unsigned idx1 = 1; // src1
21456 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21457 st->print_raw("vpmullq ");
21458 opnd_array(0)->int_format(ra, this, st); // dst
21459 st->print_raw(",");
21460 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21461 st->print_raw(",");
21462 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21463 st->print_raw("\t! mul packed2L");
21464}
21465#endif
21466#ifndef PRODUCT
21467void vmul2L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21468 // Start at oper_input_base() and count operands
21469 unsigned idx0 = 2;
21470 unsigned idx1 = 2; // src
21471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21472 st->print_raw("vpmullq ");
21473 opnd_array(0)->int_format(ra, this, st); // dst
21474 st->print_raw(",");
21475 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21476 st->print_raw(",");
21477 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21478 st->print_raw("\t! mul packed2L");
21479}
21480#endif
21481#ifndef PRODUCT
21482void vmul2L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21483 // Start at oper_input_base() and count operands
21484 unsigned idx0 = 2;
21485 unsigned idx1 = 2; // mem
21486 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21487 st->print_raw("vpmullq ");
21488 opnd_array(0)->int_format(ra, this, st); // dst
21489 st->print_raw(",");
21490 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21491 st->print_raw(",");
21492 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21493 st->print_raw("\t! mul packed2L");
21494}
21495#endif
21496#ifndef PRODUCT
21497void vmul4L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21498 // Start at oper_input_base() and count operands
21499 unsigned idx0 = 1;
21500 unsigned idx1 = 1; // src1
21501 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21502 st->print_raw("vpmullq ");
21503 opnd_array(0)->int_format(ra, this, st); // dst
21504 st->print_raw(",");
21505 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21506 st->print_raw(",");
21507 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21508 st->print_raw("\t! mul packed4L");
21509}
21510#endif
21511#ifndef PRODUCT
21512void vmul4L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21513 // Start at oper_input_base() and count operands
21514 unsigned idx0 = 2;
21515 unsigned idx1 = 2; // src
21516 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21517 st->print_raw("vpmullq ");
21518 opnd_array(0)->int_format(ra, this, st); // dst
21519 st->print_raw(",");
21520 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21521 st->print_raw(",");
21522 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21523 st->print_raw("\t! mul packed4L");
21524}
21525#endif
21526#ifndef PRODUCT
21527void vmul4L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21528 // Start at oper_input_base() and count operands
21529 unsigned idx0 = 2;
21530 unsigned idx1 = 2; // mem
21531 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21532 st->print_raw("vpmullq ");
21533 opnd_array(0)->int_format(ra, this, st); // dst
21534 st->print_raw(",");
21535 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21536 st->print_raw(",");
21537 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21538 st->print_raw("\t! mul packed4L");
21539}
21540#endif
21541#ifndef PRODUCT
21542void vmul8L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21543 // Start at oper_input_base() and count operands
21544 unsigned idx0 = 1;
21545 unsigned idx1 = 1; // src1
21546 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21547 st->print_raw("vpmullq ");
21548 opnd_array(0)->int_format(ra, this, st); // dst
21549 st->print_raw(",");
21550 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21551 st->print_raw(",");
21552 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21553 st->print_raw("\t! mul packed8L");
21554}
21555#endif
21556#ifndef PRODUCT
21557void vmul8L_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21558 // Start at oper_input_base() and count operands
21559 unsigned idx0 = 2;
21560 unsigned idx1 = 2; // src
21561 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21562 st->print_raw("vpmullq ");
21563 opnd_array(0)->int_format(ra, this, st); // dst
21564 st->print_raw(",");
21565 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21566 st->print_raw(",");
21567 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21568 st->print_raw("\t! mul packed8L");
21569}
21570#endif
21571#ifndef PRODUCT
21572void vmul8L_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21573 // Start at oper_input_base() and count operands
21574 unsigned idx0 = 2;
21575 unsigned idx1 = 2; // mem
21576 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21577 st->print_raw("vpmullq ");
21578 opnd_array(0)->int_format(ra, this, st); // dst
21579 st->print_raw(",");
21580 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21581 st->print_raw(",");
21582 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21583 st->print_raw("\t! mul packed8L");
21584}
21585#endif
21586#ifndef PRODUCT
21587void vmul8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21588 // Start at oper_input_base() and count operands
21589 unsigned idx0 = 1;
21590 unsigned idx1 = 1; // src1
21591 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21592 st->print_raw("vpmulld ");
21593 opnd_array(0)->int_format(ra, this, st); // dst
21594 st->print_raw(",");
21595 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21596 st->print_raw(",");
21597 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21598 st->print_raw("\t! mul packed8I");
21599}
21600#endif
21601#ifndef PRODUCT
21602void vmul8I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21603 // Start at oper_input_base() and count operands
21604 unsigned idx0 = 2;
21605 unsigned idx1 = 2; // src
21606 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21607 st->print_raw("vpmulld ");
21608 opnd_array(0)->int_format(ra, this, st); // dst
21609 st->print_raw(",");
21610 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21611 st->print_raw(",");
21612 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21613 st->print_raw("\t! mul packed8I");
21614}
21615#endif
21616#ifndef PRODUCT
21617void vmul8I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21618 // Start at oper_input_base() and count operands
21619 unsigned idx0 = 2;
21620 unsigned idx1 = 2; // mem
21621 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21622 st->print_raw("vpmulld ");
21623 opnd_array(0)->int_format(ra, this, st); // dst
21624 st->print_raw(",");
21625 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21626 st->print_raw(",");
21627 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21628 st->print_raw("\t! mul packed8I");
21629}
21630#endif
21631#ifndef PRODUCT
21632void vmul16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21633 // Start at oper_input_base() and count operands
21634 unsigned idx0 = 1;
21635 unsigned idx1 = 1; // src1
21636 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21637 st->print_raw("vpmulld ");
21638 opnd_array(0)->int_format(ra, this, st); // dst
21639 st->print_raw(",");
21640 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21641 st->print_raw(",");
21642 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21643 st->print_raw("\t! mul packed16I");
21644}
21645#endif
21646#ifndef PRODUCT
21647void vmul16I_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21648 // Start at oper_input_base() and count operands
21649 unsigned idx0 = 2;
21650 unsigned idx1 = 2; // src
21651 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21652 st->print_raw("vpmulld ");
21653 opnd_array(0)->int_format(ra, this, st); // dst
21654 st->print_raw(",");
21655 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21656 st->print_raw(",");
21657 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21658 st->print_raw("\t! mul packed16I");
21659}
21660#endif
21661#ifndef PRODUCT
21662void vmul16I_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21663 // Start at oper_input_base() and count operands
21664 unsigned idx0 = 2;
21665 unsigned idx1 = 2; // mem
21666 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21667 st->print_raw("vpmulld ");
21668 opnd_array(0)->int_format(ra, this, st); // dst
21669 st->print_raw(",");
21670 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21671 st->print_raw(",");
21672 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21673 st->print_raw("\t! mul packed16I");
21674}
21675#endif
21676#ifndef PRODUCT
21677void vmul2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21678 // Start at oper_input_base() and count operands
21679 unsigned idx0 = 1;
21680 unsigned idx1 = 1; // dst
21681 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21682 st->print_raw("mulps ");
21683 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21684 st->print_raw(",");
21685 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21686 st->print_raw("\t! mul packed2F");
21687}
21688#endif
21689#ifndef PRODUCT
21690void vmul2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21691 // Start at oper_input_base() and count operands
21692 unsigned idx0 = 1;
21693 unsigned idx1 = 1; // src1
21694 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21695 st->print_raw("vmulps ");
21696 opnd_array(0)->int_format(ra, this, st); // dst
21697 st->print_raw(",");
21698 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21699 st->print_raw(",");
21700 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21701 st->print_raw("\t! mul packed2F");
21702}
21703#endif
21704#ifndef PRODUCT
21705void vmul2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21706 // Start at oper_input_base() and count operands
21707 unsigned idx0 = 2;
21708 unsigned idx1 = 2; // src
21709 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21710 st->print_raw("vmulps ");
21711 opnd_array(0)->int_format(ra, this, st); // dst
21712 st->print_raw(",");
21713 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21714 st->print_raw(",");
21715 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21716 st->print_raw("\t! mul packed2F");
21717}
21718#endif
21719#ifndef PRODUCT
21720void vmul2F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21721 // Start at oper_input_base() and count operands
21722 unsigned idx0 = 2;
21723 unsigned idx1 = 2; // mem
21724 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21725 st->print_raw("vmulps ");
21726 opnd_array(0)->int_format(ra, this, st); // dst
21727 st->print_raw(",");
21728 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21729 st->print_raw(",");
21730 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21731 st->print_raw("\t! mul packed2F");
21732}
21733#endif
21734#ifndef PRODUCT
21735void vmul4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21736 // Start at oper_input_base() and count operands
21737 unsigned idx0 = 1;
21738 unsigned idx1 = 1; // dst
21739 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21740 st->print_raw("mulps ");
21741 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21742 st->print_raw(",");
21743 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21744 st->print_raw("\t! mul packed4F");
21745}
21746#endif
21747#ifndef PRODUCT
21748void vmul4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21749 // Start at oper_input_base() and count operands
21750 unsigned idx0 = 1;
21751 unsigned idx1 = 1; // src1
21752 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21753 st->print_raw("vmulps ");
21754 opnd_array(0)->int_format(ra, this, st); // dst
21755 st->print_raw(",");
21756 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21757 st->print_raw(",");
21758 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21759 st->print_raw("\t! mul packed4F");
21760}
21761#endif
21762#ifndef PRODUCT
21763void vmul4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21764 // Start at oper_input_base() and count operands
21765 unsigned idx0 = 2;
21766 unsigned idx1 = 2; // src
21767 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21768 st->print_raw("vmulps ");
21769 opnd_array(0)->int_format(ra, this, st); // dst
21770 st->print_raw(",");
21771 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21772 st->print_raw(",");
21773 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21774 st->print_raw("\t! mul packed4F");
21775}
21776#endif
21777#ifndef PRODUCT
21778void vmul4F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21779 // Start at oper_input_base() and count operands
21780 unsigned idx0 = 2;
21781 unsigned idx1 = 2; // mem
21782 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21783 st->print_raw("vmulps ");
21784 opnd_array(0)->int_format(ra, this, st); // dst
21785 st->print_raw(",");
21786 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21787 st->print_raw(",");
21788 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21789 st->print_raw("\t! mul packed4F");
21790}
21791#endif
21792#ifndef PRODUCT
21793void vmul8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21794 // Start at oper_input_base() and count operands
21795 unsigned idx0 = 1;
21796 unsigned idx1 = 1; // src1
21797 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21798 st->print_raw("vmulps ");
21799 opnd_array(0)->int_format(ra, this, st); // dst
21800 st->print_raw(",");
21801 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21802 st->print_raw(",");
21803 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21804 st->print_raw("\t! mul packed8F");
21805}
21806#endif
21807#ifndef PRODUCT
21808void vmul8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21809 // Start at oper_input_base() and count operands
21810 unsigned idx0 = 2;
21811 unsigned idx1 = 2; // src
21812 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21813 st->print_raw("vmulps ");
21814 opnd_array(0)->int_format(ra, this, st); // dst
21815 st->print_raw(",");
21816 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21817 st->print_raw(",");
21818 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21819 st->print_raw("\t! mul packed8F");
21820}
21821#endif
21822#ifndef PRODUCT
21823void vmul8F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21824 // Start at oper_input_base() and count operands
21825 unsigned idx0 = 2;
21826 unsigned idx1 = 2; // mem
21827 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21828 st->print_raw("vmulps ");
21829 opnd_array(0)->int_format(ra, this, st); // dst
21830 st->print_raw(",");
21831 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21832 st->print_raw(",");
21833 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21834 st->print_raw("\t! mul packed8F");
21835}
21836#endif
21837#ifndef PRODUCT
21838void vmul16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21839 // Start at oper_input_base() and count operands
21840 unsigned idx0 = 1;
21841 unsigned idx1 = 1; // src1
21842 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21843 st->print_raw("vmulps ");
21844 opnd_array(0)->int_format(ra, this, st); // dst
21845 st->print_raw(",");
21846 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21847 st->print_raw(",");
21848 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21849 st->print_raw("\t! mul packed16F");
21850}
21851#endif
21852#ifndef PRODUCT
21853void vmul16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21854 // Start at oper_input_base() and count operands
21855 unsigned idx0 = 2;
21856 unsigned idx1 = 2; // src
21857 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21858 st->print_raw("vmulps ");
21859 opnd_array(0)->int_format(ra, this, st); // dst
21860 st->print_raw(",");
21861 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21862 st->print_raw(",");
21863 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21864 st->print_raw("\t! mul packed16F");
21865}
21866#endif
21867#ifndef PRODUCT
21868void vmul16F_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21869 // Start at oper_input_base() and count operands
21870 unsigned idx0 = 2;
21871 unsigned idx1 = 2; // mem
21872 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21873 st->print_raw("vmulps ");
21874 opnd_array(0)->int_format(ra, this, st); // dst
21875 st->print_raw(",");
21876 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21877 st->print_raw(",");
21878 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21879 st->print_raw("\t! mul packed16F");
21880}
21881#endif
21882#ifndef PRODUCT
21883void vmul2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21884 // Start at oper_input_base() and count operands
21885 unsigned idx0 = 1;
21886 unsigned idx1 = 1; // dst
21887 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21888 st->print_raw("mulpd ");
21889 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
21890 st->print_raw(",");
21891 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21892 st->print_raw("\t! mul packed2D");
21893}
21894#endif
21895#ifndef PRODUCT
21896void vmul2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21897 // Start at oper_input_base() and count operands
21898 unsigned idx0 = 1;
21899 unsigned idx1 = 1; // src1
21900 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21901 st->print_raw("vmulpd ");
21902 opnd_array(0)->int_format(ra, this, st); // dst
21903 st->print_raw(",");
21904 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21905 st->print_raw(",");
21906 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21907 st->print_raw("\t! mul packed2D");
21908}
21909#endif
21910#ifndef PRODUCT
21911void vmul2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21912 // Start at oper_input_base() and count operands
21913 unsigned idx0 = 2;
21914 unsigned idx1 = 2; // src
21915 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21916 st->print_raw("vmulpd ");
21917 opnd_array(0)->int_format(ra, this, st); // dst
21918 st->print_raw(",");
21919 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21920 st->print_raw(",");
21921 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21922 st->print_raw("\t! mul packed2D");
21923}
21924#endif
21925#ifndef PRODUCT
21926void vmul2D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21927 // Start at oper_input_base() and count operands
21928 unsigned idx0 = 2;
21929 unsigned idx1 = 2; // mem
21930 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21931 st->print_raw("vmulpd ");
21932 opnd_array(0)->int_format(ra, this, st); // dst
21933 st->print_raw(",");
21934 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21935 st->print_raw(",");
21936 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21937 st->print_raw("\t! mul packed2D");
21938}
21939#endif
21940#ifndef PRODUCT
21941void vmul4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21942 // Start at oper_input_base() and count operands
21943 unsigned idx0 = 1;
21944 unsigned idx1 = 1; // src1
21945 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21946 st->print_raw("vmulpd ");
21947 opnd_array(0)->int_format(ra, this, st); // dst
21948 st->print_raw(",");
21949 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21950 st->print_raw(",");
21951 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21952 st->print_raw("\t! mul packed4D");
21953}
21954#endif
21955#ifndef PRODUCT
21956void vmul4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21957 // Start at oper_input_base() and count operands
21958 unsigned idx0 = 2;
21959 unsigned idx1 = 2; // src
21960 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
21961 st->print_raw("vmulpd ");
21962 opnd_array(0)->int_format(ra, this, st); // dst
21963 st->print_raw(",");
21964 opnd_array(1)->ext_format(ra, this,idx1, st); // src
21965 st->print_raw(",");
21966 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
21967 st->print_raw("\t! mul packed4D");
21968}
21969#endif
21970#ifndef PRODUCT
21971void vmul4D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
21972 // Start at oper_input_base() and count operands
21973 unsigned idx0 = 2;
21974 unsigned idx1 = 2; // mem
21975 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21976 st->print_raw("vmulpd ");
21977 opnd_array(0)->int_format(ra, this, st); // dst
21978 st->print_raw(",");
21979 opnd_array(2)->ext_format(ra, this,idx2, st); // src
21980 st->print_raw(",");
21981 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
21982 st->print_raw("\t! mul packed4D");
21983}
21984#endif
21985#ifndef PRODUCT
21986void vmul8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
21987 // Start at oper_input_base() and count operands
21988 unsigned idx0 = 1;
21989 unsigned idx1 = 1; // src1
21990 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
21991 st->print_raw("vmulpd ");
21992 opnd_array(0)->int_format(ra, this, st); // dst
21993 st->print_raw(" k0,");
21994 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
21995 st->print_raw(",");
21996 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
21997 st->print_raw("\t! mul packed8D");
21998}
21999#endif
22000#ifndef PRODUCT
22001void vmul8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22002 // Start at oper_input_base() and count operands
22003 unsigned idx0 = 2;
22004 unsigned idx1 = 2; // src
22005 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22006 st->print_raw("vmulpd ");
22007 opnd_array(0)->int_format(ra, this, st); // dst
22008 st->print_raw(" k0,");
22009 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22010 st->print_raw(",");
22011 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22012 st->print_raw("\t! mul packed8D");
22013}
22014#endif
22015#ifndef PRODUCT
22016void vmul8D_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22017 // Start at oper_input_base() and count operands
22018 unsigned idx0 = 2;
22019 unsigned idx1 = 2; // mem
22020 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22021 st->print_raw("vmulpd ");
22022 opnd_array(0)->int_format(ra, this, st); // dst
22023 st->print_raw(" k0,");
22024 opnd_array(2)->ext_format(ra, this,idx2, st); // src
22025 st->print_raw(",");
22026 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22027 st->print_raw("\t! mul packed8D");
22028}
22029#endif
22030#ifndef PRODUCT
22031void vcmov8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22032 // Start at oper_input_base() and count operands
22033 unsigned idx0 = 1;
22034 unsigned idx1 = 1; // copnd
22035 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
22036 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
22037 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
22038 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
22039 st->print_raw("cmpps.");
22040 opnd_array(1)->ext_format(ra, this,idx1, st); // copnd
22041 st->print_raw(" ");
22042 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22043 st->print_raw(", ");
22044 opnd_array(3)->ext_format(ra, this,idx3, st); // src1
22045 st->print_raw(", ");
22046 opnd_array(4)->ext_format(ra, this,idx4, st); // src2
22047 st->print_raw(" ! vcmovevf, cond=");
22048 opnd_array(2)->ext_format(ra, this,idx2, st); // cop
22049 st->print_raw("\n\t");
22050 st->print_raw("blendvps ");
22051 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22052 st->print_raw(",");
22053 opnd_array(3)->ext_format(ra, this,idx3, st); // src1
22054 st->print_raw(",");
22055 opnd_array(4)->ext_format(ra, this,idx4, st); // src2
22056 st->print_raw(",");
22057 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22058 st->print_raw(" ! vcmovevf\n\t");
22059}
22060#endif
22061#ifndef PRODUCT
22062void vcmov4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22063 // Start at oper_input_base() and count operands
22064 unsigned idx0 = 1;
22065 unsigned idx1 = 1; // copnd
22066 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
22067 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
22068 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
22069 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
22070 st->print_raw("cmppd.");
22071 opnd_array(1)->ext_format(ra, this,idx1, st); // copnd
22072 st->print_raw(" ");
22073 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22074 st->print_raw(", ");
22075 opnd_array(3)->ext_format(ra, this,idx3, st); // src1
22076 st->print_raw(", ");
22077 opnd_array(4)->ext_format(ra, this,idx4, st); // src2
22078 st->print_raw(" ! vcmovevd, cond=");
22079 opnd_array(2)->ext_format(ra, this,idx2, st); // cop
22080 st->print_raw("\n\t");
22081 st->print_raw("blendvpd ");
22082 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22083 st->print_raw(",");
22084 opnd_array(3)->ext_format(ra, this,idx3, st); // src1
22085 st->print_raw(",");
22086 opnd_array(4)->ext_format(ra, this,idx4, st); // src2
22087 st->print_raw(",");
22088 opnd_array(5)->ext_format(ra, this,idx5, st); // dst
22089 st->print_raw(" ! vcmovevd\n\t");
22090}
22091#endif
22092#ifndef PRODUCT
22093void vdiv2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22094 // Start at oper_input_base() and count operands
22095 unsigned idx0 = 1;
22096 unsigned idx1 = 1; // dst
22097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22098 st->print_raw("divps ");
22099 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
22100 st->print_raw(",");
22101 opnd_array(2)->ext_format(ra, this,idx2, st); // src
22102 st->print_raw("\t! div packed2F");
22103}
22104#endif
22105#ifndef PRODUCT
22106void vdiv2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22107 // Start at oper_input_base() and count operands
22108 unsigned idx0 = 1;
22109 unsigned idx1 = 1; // src1
22110 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22111 st->print_raw("vdivps ");
22112 opnd_array(0)->int_format(ra, this, st); // dst
22113 st->print_raw(",");
22114 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22115 st->print_raw(",");
22116 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22117 st->print_raw("\t! div packed2F");
22118}
22119#endif
22120#ifndef PRODUCT
22121void vdiv2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22122 // Start at oper_input_base() and count operands
22123 unsigned idx0 = 2;
22124 unsigned idx1 = 2; // src
22125 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22126 st->print_raw("vdivps ");
22127 opnd_array(0)->int_format(ra, this, st); // dst
22128 st->print_raw(",");
22129 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22130 st->print_raw(",");
22131 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22132 st->print_raw("\t! div packed2F");
22133}
22134#endif
22135#ifndef PRODUCT
22136void vdiv4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22137 // Start at oper_input_base() and count operands
22138 unsigned idx0 = 1;
22139 unsigned idx1 = 1; // dst
22140 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22141 st->print_raw("divps ");
22142 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
22143 st->print_raw(",");
22144 opnd_array(2)->ext_format(ra, this,idx2, st); // src
22145 st->print_raw("\t! div packed4F");
22146}
22147#endif
22148#ifndef PRODUCT
22149void vdiv4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22150 // Start at oper_input_base() and count operands
22151 unsigned idx0 = 1;
22152 unsigned idx1 = 1; // src1
22153 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22154 st->print_raw("vdivps ");
22155 opnd_array(0)->int_format(ra, this, st); // dst
22156 st->print_raw(",");
22157 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22158 st->print_raw(",");
22159 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22160 st->print_raw("\t! div packed4F");
22161}
22162#endif
22163#ifndef PRODUCT
22164void vdiv4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22165 // Start at oper_input_base() and count operands
22166 unsigned idx0 = 2;
22167 unsigned idx1 = 2; // src
22168 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22169 st->print_raw("vdivps ");
22170 opnd_array(0)->int_format(ra, this, st); // dst
22171 st->print_raw(",");
22172 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22173 st->print_raw(",");
22174 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22175 st->print_raw("\t! div packed4F");
22176}
22177#endif
22178#ifndef PRODUCT
22179void vdiv8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22180 // Start at oper_input_base() and count operands
22181 unsigned idx0 = 1;
22182 unsigned idx1 = 1; // src1
22183 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22184 st->print_raw("vdivps ");
22185 opnd_array(0)->int_format(ra, this, st); // dst
22186 st->print_raw(",");
22187 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22188 st->print_raw(",");
22189 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22190 st->print_raw("\t! div packed8F");
22191}
22192#endif
22193#ifndef PRODUCT
22194void vdiv8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22195 // Start at oper_input_base() and count operands
22196 unsigned idx0 = 2;
22197 unsigned idx1 = 2; // src
22198 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22199 st->print_raw("vdivps ");
22200 opnd_array(0)->int_format(ra, this, st); // dst
22201 st->print_raw(",");
22202 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22203 st->print_raw(",");
22204 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22205 st->print_raw("\t! div packed8F");
22206}
22207#endif
22208#ifndef PRODUCT
22209void vdiv16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22210 // Start at oper_input_base() and count operands
22211 unsigned idx0 = 1;
22212 unsigned idx1 = 1; // src1
22213 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22214 st->print_raw("vdivps ");
22215 opnd_array(0)->int_format(ra, this, st); // dst
22216 st->print_raw(",");
22217 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22218 st->print_raw(",");
22219 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22220 st->print_raw("\t! div packed16F");
22221}
22222#endif
22223#ifndef PRODUCT
22224void vdiv16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22225 // Start at oper_input_base() and count operands
22226 unsigned idx0 = 2;
22227 unsigned idx1 = 2; // src
22228 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22229 st->print_raw("vdivps ");
22230 opnd_array(0)->int_format(ra, this, st); // dst
22231 st->print_raw(",");
22232 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22233 st->print_raw(",");
22234 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22235 st->print_raw("\t! div packed16F");
22236}
22237#endif
22238#ifndef PRODUCT
22239void vdiv2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22240 // Start at oper_input_base() and count operands
22241 unsigned idx0 = 1;
22242 unsigned idx1 = 1; // dst
22243 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22244 st->print_raw("divpd ");
22245 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
22246 st->print_raw(",");
22247 opnd_array(2)->ext_format(ra, this,idx2, st); // src
22248 st->print_raw("\t! div packed2D");
22249}
22250#endif
22251#ifndef PRODUCT
22252void vdiv2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22253 // Start at oper_input_base() and count operands
22254 unsigned idx0 = 1;
22255 unsigned idx1 = 1; // src1
22256 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22257 st->print_raw("vdivpd ");
22258 opnd_array(0)->int_format(ra, this, st); // dst
22259 st->print_raw(",");
22260 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22261 st->print_raw(",");
22262 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22263 st->print_raw("\t! div packed2D");
22264}
22265#endif
22266#ifndef PRODUCT
22267void vdiv2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22268 // Start at oper_input_base() and count operands
22269 unsigned idx0 = 2;
22270 unsigned idx1 = 2; // src
22271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22272 st->print_raw("vdivpd ");
22273 opnd_array(0)->int_format(ra, this, st); // dst
22274 st->print_raw(",");
22275 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22276 st->print_raw(",");
22277 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22278 st->print_raw("\t! div packed2D");
22279}
22280#endif
22281#ifndef PRODUCT
22282void vdiv4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22283 // Start at oper_input_base() and count operands
22284 unsigned idx0 = 1;
22285 unsigned idx1 = 1; // src1
22286 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22287 st->print_raw("vdivpd ");
22288 opnd_array(0)->int_format(ra, this, st); // dst
22289 st->print_raw(",");
22290 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22291 st->print_raw(",");
22292 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22293 st->print_raw("\t! div packed4D");
22294}
22295#endif
22296#ifndef PRODUCT
22297void vdiv4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22298 // Start at oper_input_base() and count operands
22299 unsigned idx0 = 2;
22300 unsigned idx1 = 2; // src
22301 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22302 st->print_raw("vdivpd ");
22303 opnd_array(0)->int_format(ra, this, st); // dst
22304 st->print_raw(",");
22305 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22306 st->print_raw(",");
22307 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22308 st->print_raw("\t! div packed4D");
22309}
22310#endif
22311#ifndef PRODUCT
22312void vdiv8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22313 // Start at oper_input_base() and count operands
22314 unsigned idx0 = 1;
22315 unsigned idx1 = 1; // src1
22316 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
22317 st->print_raw("vdivpd ");
22318 opnd_array(0)->int_format(ra, this, st); // dst
22319 st->print_raw(",");
22320 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
22321 st->print_raw(",");
22322 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
22323 st->print_raw("\t! div packed8D");
22324}
22325#endif
22326#ifndef PRODUCT
22327void vdiv8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22328 // Start at oper_input_base() and count operands
22329 unsigned idx0 = 2;
22330 unsigned idx1 = 2; // src
22331 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
22332 st->print_raw("vdivpd ");
22333 opnd_array(0)->int_format(ra, this, st); // dst
22334 st->print_raw(",");
22335 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22336 st->print_raw(",");
22337 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
22338 st->print_raw("\t! div packed8D");
22339}
22340#endif
22341#ifndef PRODUCT
22342void vsqrt2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22343 // Start at oper_input_base() and count operands
22344 unsigned idx0 = 1;
22345 unsigned idx1 = 1; // src
22346 st->print_raw("vsqrtpd ");
22347 opnd_array(0)->int_format(ra, this, st); // dst
22348 st->print_raw(",");
22349 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22350 st->print_raw("\t! sqrt packed2D");
22351}
22352#endif
22353#ifndef PRODUCT
22354void vsqrt2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22355 // Start at oper_input_base() and count operands
22356 unsigned idx0 = 2;
22357 unsigned idx1 = 2; // mem
22358 st->print_raw("vsqrtpd ");
22359 opnd_array(0)->int_format(ra, this, st); // dst
22360 st->print_raw(",");
22361 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22362 st->print_raw("\t! sqrt packed2D");
22363}
22364#endif
22365#ifndef PRODUCT
22366void vsqrt4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22367 // Start at oper_input_base() and count operands
22368 unsigned idx0 = 1;
22369 unsigned idx1 = 1; // src
22370 st->print_raw("vsqrtpd ");
22371 opnd_array(0)->int_format(ra, this, st); // dst
22372 st->print_raw(",");
22373 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22374 st->print_raw("\t! sqrt packed4D");
22375}
22376#endif
22377#ifndef PRODUCT
22378void vsqrt4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22379 // Start at oper_input_base() and count operands
22380 unsigned idx0 = 2;
22381 unsigned idx1 = 2; // mem
22382 st->print_raw("vsqrtpd ");
22383 opnd_array(0)->int_format(ra, this, st); // dst
22384 st->print_raw(",");
22385 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22386 st->print_raw("\t! sqrt packed4D");
22387}
22388#endif
22389#ifndef PRODUCT
22390void vsqrt8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22391 // Start at oper_input_base() and count operands
22392 unsigned idx0 = 1;
22393 unsigned idx1 = 1; // src
22394 st->print_raw("vsqrtpd ");
22395 opnd_array(0)->int_format(ra, this, st); // dst
22396 st->print_raw(",");
22397 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22398 st->print_raw("\t! sqrt packed8D");
22399}
22400#endif
22401#ifndef PRODUCT
22402void vsqrt8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22403 // Start at oper_input_base() and count operands
22404 unsigned idx0 = 2;
22405 unsigned idx1 = 2; // mem
22406 st->print_raw("vsqrtpd ");
22407 opnd_array(0)->int_format(ra, this, st); // dst
22408 st->print_raw(",");
22409 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22410 st->print_raw("\t! sqrt packed8D");
22411}
22412#endif
22413#ifndef PRODUCT
22414void vsqrt2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22415 // Start at oper_input_base() and count operands
22416 unsigned idx0 = 1;
22417 unsigned idx1 = 1; // src
22418 st->print_raw("vsqrtps ");
22419 opnd_array(0)->int_format(ra, this, st); // dst
22420 st->print_raw(",");
22421 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22422 st->print_raw("\t! sqrt packed2F");
22423}
22424#endif
22425#ifndef PRODUCT
22426void vsqrt2F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22427 // Start at oper_input_base() and count operands
22428 unsigned idx0 = 2;
22429 unsigned idx1 = 2; // mem
22430 st->print_raw("vsqrtps ");
22431 opnd_array(0)->int_format(ra, this, st); // dst
22432 st->print_raw(",");
22433 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22434 st->print_raw("\t! sqrt packed2F");
22435}
22436#endif
22437#ifndef PRODUCT
22438void vsqrt4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22439 // Start at oper_input_base() and count operands
22440 unsigned idx0 = 1;
22441 unsigned idx1 = 1; // src
22442 st->print_raw("vsqrtps ");
22443 opnd_array(0)->int_format(ra, this, st); // dst
22444 st->print_raw(",");
22445 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22446 st->print_raw("\t! sqrt packed4F");
22447}
22448#endif
22449#ifndef PRODUCT
22450void vsqrt4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22451 // Start at oper_input_base() and count operands
22452 unsigned idx0 = 2;
22453 unsigned idx1 = 2; // mem
22454 st->print_raw("vsqrtps ");
22455 opnd_array(0)->int_format(ra, this, st); // dst
22456 st->print_raw(",");
22457 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22458 st->print_raw("\t! sqrt packed4F");
22459}
22460#endif
22461#ifndef PRODUCT
22462void vsqrt8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22463 // Start at oper_input_base() and count operands
22464 unsigned idx0 = 1;
22465 unsigned idx1 = 1; // src
22466 st->print_raw("vsqrtps ");
22467 opnd_array(0)->int_format(ra, this, st); // dst
22468 st->print_raw(",");
22469 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22470 st->print_raw("\t! sqrt packed8F");
22471}
22472#endif
22473#ifndef PRODUCT
22474void vsqrt8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22475 // Start at oper_input_base() and count operands
22476 unsigned idx0 = 2;
22477 unsigned idx1 = 2; // mem
22478 st->print_raw("vsqrtps ");
22479 opnd_array(0)->int_format(ra, this, st); // dst
22480 st->print_raw(",");
22481 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22482 st->print_raw("\t! sqrt packed8F");
22483}
22484#endif
22485#ifndef PRODUCT
22486void vsqrt16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22487 // Start at oper_input_base() and count operands
22488 unsigned idx0 = 1;
22489 unsigned idx1 = 1; // src
22490 st->print_raw("vsqrtps ");
22491 opnd_array(0)->int_format(ra, this, st); // dst
22492 st->print_raw(",");
22493 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22494 st->print_raw("\t! sqrt packed16F");
22495}
22496#endif
22497#ifndef PRODUCT
22498void vsqrt16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22499 // Start at oper_input_base() and count operands
22500 unsigned idx0 = 2;
22501 unsigned idx1 = 2; // mem
22502 st->print_raw("vsqrtps ");
22503 opnd_array(0)->int_format(ra, this, st); // dst
22504 st->print_raw(",");
22505 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
22506 st->print_raw("\t! sqrt packed16F");
22507}
22508#endif
22509#ifndef PRODUCT
22510void vshiftcntNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22511 // Start at oper_input_base() and count operands
22512 unsigned idx0 = 1;
22513 unsigned idx1 = 1; // cnt
22514 st->print_raw("movdl ");
22515 opnd_array(0)->int_format(ra, this, st); // dst
22516 st->print_raw(",");
22517 opnd_array(1)->ext_format(ra, this,idx1, st); // cnt
22518 st->print_raw("\t! load shift count");
22519}
22520#endif
22521#ifndef PRODUCT
22522void vshiftcnt_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22523 // Start at oper_input_base() and count operands
22524 unsigned idx0 = 1;
22525 unsigned idx1 = 1; // cnt
22526 st->print_raw("movdl ");
22527 opnd_array(0)->int_format(ra, this, st); // dst
22528 st->print_raw(",");
22529 opnd_array(1)->ext_format(ra, this,idx1, st); // cnt
22530 st->print_raw("\t! load shift count");
22531}
22532#endif
22533#ifndef PRODUCT
22534void vshiftcntimmNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22535 // Start at oper_input_base() and count operands
22536 unsigned idx0 = 1;
22537 unsigned idx1 = 1; // cnt
22538 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // tmp
22539 st->print_raw("movl ");
22540 opnd_array(2)->ext_format(ra, this,idx2, st); // tmp
22541 st->print_raw(",");
22542 opnd_array(1)->ext_format(ra, this,idx1, st); // cnt
22543 st->print_raw("\t");
22544 st->print_raw("movdl ");
22545 opnd_array(0)->int_format(ra, this, st); // dst
22546 st->print_raw(",");
22547 opnd_array(2)->ext_format(ra, this,idx2, st); // tmp
22548 st->print_raw("\t! load shift count");
22549}
22550#endif
22551#ifndef PRODUCT
22552void vshift4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22553 // Start at oper_input_base() and count operands
22554 unsigned idx0 = 1;
22555 unsigned idx1 = 1; // src
22556 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22557 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22558 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22559 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22560 st->print_raw("vextendbw ");
22561 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22562 st->print_raw(",");
22563 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22564 st->print_raw("\n\t");
22565 st->print_raw("vshiftw ");
22566 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22567 st->print_raw(",");
22568 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22569 st->print_raw("\n\t");
22570 st->print_raw("movdqu ");
22571 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22572 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22573 st->print_raw("pand ");
22574 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22575 st->print_raw(",");
22576 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22577 st->print_raw("\n\t");
22578 st->print_raw("packuswb ");
22579 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22580 st->print_raw(",");
22581 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22582 st->print_raw("\n\t ! packed4B shift");
22583}
22584#endif
22585#ifndef PRODUCT
22586void vshift4B_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22587 // Start at oper_input_base() and count operands
22588 unsigned idx0 = 1;
22589 unsigned idx1 = 1; // src
22590 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22591 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22592 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22593 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22594 st->print_raw("vextendbw ");
22595 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22596 st->print_raw(",");
22597 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22598 st->print_raw("\n\t");
22599 st->print_raw("vshiftw ");
22600 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22601 st->print_raw(",");
22602 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22603 st->print_raw("\n\t");
22604 st->print_raw("movdqu ");
22605 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22606 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22607 st->print_raw("pand ");
22608 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22609 st->print_raw(",");
22610 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22611 st->print_raw("\n\t");
22612 st->print_raw("packuswb ");
22613 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22614 st->print_raw(",");
22615 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22616 st->print_raw("\n\t ! packed4B shift");
22617}
22618#endif
22619#ifndef PRODUCT
22620void vshift4B_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22621 // Start at oper_input_base() and count operands
22622 unsigned idx0 = 1;
22623 unsigned idx1 = 1; // src
22624 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22625 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22626 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22627 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22628 st->print_raw("vextendbw ");
22629 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22630 st->print_raw(",");
22631 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22632 st->print_raw("\n\t");
22633 st->print_raw("vshiftw ");
22634 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22635 st->print_raw(",");
22636 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22637 st->print_raw("\n\t");
22638 st->print_raw("movdqu ");
22639 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22640 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22641 st->print_raw("pand ");
22642 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22643 st->print_raw(",");
22644 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22645 st->print_raw("\n\t");
22646 st->print_raw("packuswb ");
22647 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22648 st->print_raw(",");
22649 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22650 st->print_raw("\n\t ! packed4B shift");
22651}
22652#endif
22653#ifndef PRODUCT
22654void vshift8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22655 // Start at oper_input_base() and count operands
22656 unsigned idx0 = 1;
22657 unsigned idx1 = 1; // src
22658 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22659 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22660 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22661 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22662 st->print_raw("vextendbw ");
22663 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22664 st->print_raw(",");
22665 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22666 st->print_raw("\n\t");
22667 st->print_raw("vshiftw ");
22668 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22669 st->print_raw(",");
22670 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22671 st->print_raw("\n\t");
22672 st->print_raw("movdqu ");
22673 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22674 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22675 st->print_raw("pand ");
22676 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22677 st->print_raw(",");
22678 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22679 st->print_raw("\n\t");
22680 st->print_raw("packuswb ");
22681 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22682 st->print_raw(",");
22683 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22684 st->print_raw("\n\t ! packed8B shift");
22685}
22686#endif
22687#ifndef PRODUCT
22688void vshift8B_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22689 // Start at oper_input_base() and count operands
22690 unsigned idx0 = 1;
22691 unsigned idx1 = 1; // src
22692 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22693 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22694 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22695 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22696 st->print_raw("vextendbw ");
22697 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22698 st->print_raw(",");
22699 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22700 st->print_raw("\n\t");
22701 st->print_raw("vshiftw ");
22702 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22703 st->print_raw(",");
22704 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22705 st->print_raw("\n\t");
22706 st->print_raw("movdqu ");
22707 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22708 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22709 st->print_raw("pand ");
22710 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22711 st->print_raw(",");
22712 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22713 st->print_raw("\n\t");
22714 st->print_raw("packuswb ");
22715 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22716 st->print_raw(",");
22717 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22718 st->print_raw("\n\t ! packed8B shift");
22719}
22720#endif
22721#ifndef PRODUCT
22722void vshift8B_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22723 // Start at oper_input_base() and count operands
22724 unsigned idx0 = 1;
22725 unsigned idx1 = 1; // src
22726 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22727 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22728 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22729 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22730 st->print_raw("vextendbw ");
22731 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22732 st->print_raw(",");
22733 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22734 st->print_raw("\n\t");
22735 st->print_raw("vshiftw ");
22736 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22737 st->print_raw(",");
22738 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22739 st->print_raw("\n\t");
22740 st->print_raw("movdqu ");
22741 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22742 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22743 st->print_raw("pand ");
22744 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22745 st->print_raw(",");
22746 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22747 st->print_raw("\n\t");
22748 st->print_raw("packuswb ");
22749 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22750 st->print_raw(",");
22751 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22752 st->print_raw("\n\t ! packed8B shift");
22753}
22754#endif
22755#ifndef PRODUCT
22756void vshift16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22757 // Start at oper_input_base() and count operands
22758 unsigned idx0 = 1;
22759 unsigned idx1 = 1; // src
22760 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22761 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22762 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
22763 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
22764 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
22765 st->print_raw("vextendbw ");
22766 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22767 st->print_raw(",");
22768 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22769 st->print_raw("\n\t");
22770 st->print_raw("vshiftw ");
22771 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22772 st->print_raw(",");
22773 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22774 st->print_raw("\n\t");
22775 st->print_raw("pshufd ");
22776 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22777 st->print_raw(",");
22778 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22779 st->print_raw("\n\t");
22780 st->print_raw("vextendbw ");
22781 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22782 st->print_raw(",");
22783 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22784 st->print_raw("\n\t");
22785 st->print_raw("vshiftw ");
22786 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22787 st->print_raw(",");
22788 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22789 st->print_raw("\n\t");
22790 st->print_raw("movdqu ");
22791 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22792 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22793 st->print_raw("pand ");
22794 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22795 st->print_raw(",");
22796 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22797 st->print_raw("\n\t");
22798 st->print_raw("pand ");
22799 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22800 st->print_raw(",");
22801 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22802 st->print_raw("\n\t");
22803 st->print_raw("packuswb ");
22804 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22805 st->print_raw(",");
22806 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22807 st->print_raw("\n\t! packed16B shift");
22808}
22809#endif
22810#ifndef PRODUCT
22811void vshift16B_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22812 // Start at oper_input_base() and count operands
22813 unsigned idx0 = 1;
22814 unsigned idx1 = 1; // src
22815 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22816 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22817 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
22818 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
22819 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
22820 st->print_raw("vextendbw ");
22821 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22822 st->print_raw(",");
22823 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22824 st->print_raw("\n\t");
22825 st->print_raw("vshiftw ");
22826 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22827 st->print_raw(",");
22828 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22829 st->print_raw("\n\t");
22830 st->print_raw("pshufd ");
22831 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22832 st->print_raw(",");
22833 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22834 st->print_raw("\n\t");
22835 st->print_raw("vextendbw ");
22836 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22837 st->print_raw(",");
22838 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22839 st->print_raw("\n\t");
22840 st->print_raw("vshiftw ");
22841 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22842 st->print_raw(",");
22843 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22844 st->print_raw("\n\t");
22845 st->print_raw("movdqu ");
22846 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22847 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22848 st->print_raw("pand ");
22849 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22850 st->print_raw(",");
22851 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22852 st->print_raw("\n\t");
22853 st->print_raw("pand ");
22854 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22855 st->print_raw(",");
22856 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22857 st->print_raw("\n\t");
22858 st->print_raw("packuswb ");
22859 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22860 st->print_raw(",");
22861 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22862 st->print_raw("\n\t! packed16B shift");
22863}
22864#endif
22865#ifndef PRODUCT
22866void vshift16B_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22867 // Start at oper_input_base() and count operands
22868 unsigned idx0 = 1;
22869 unsigned idx1 = 1; // src
22870 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22871 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22872 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
22873 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
22874 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
22875 st->print_raw("vextendbw ");
22876 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22877 st->print_raw(",");
22878 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22879 st->print_raw("\n\t");
22880 st->print_raw("vshiftw ");
22881 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22882 st->print_raw(",");
22883 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22884 st->print_raw("\n\t");
22885 st->print_raw("pshufd ");
22886 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22887 st->print_raw(",");
22888 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22889 st->print_raw("\n\t");
22890 st->print_raw("vextendbw ");
22891 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22892 st->print_raw(",");
22893 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22894 st->print_raw("\n\t");
22895 st->print_raw("vshiftw ");
22896 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22897 st->print_raw(",");
22898 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22899 st->print_raw("\n\t");
22900 st->print_raw("movdqu ");
22901 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22902 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22903 st->print_raw("pand ");
22904 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22905 st->print_raw(",");
22906 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22907 st->print_raw("\n\t");
22908 st->print_raw("pand ");
22909 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22910 st->print_raw(",");
22911 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
22912 st->print_raw("\n\t");
22913 st->print_raw("packuswb ");
22914 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22915 st->print_raw(",");
22916 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
22917 st->print_raw("\n\t! packed16B shift");
22918}
22919#endif
22920#ifndef PRODUCT
22921void vshift16B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
22922 // Start at oper_input_base() and count operands
22923 unsigned idx0 = 1;
22924 unsigned idx1 = 1; // src
22925 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22926 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22927 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22928 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22929 st->print_raw("vextendbw ");
22930 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22931 st->print_raw(",");
22932 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22933 st->print_raw("\n\t");
22934 st->print_raw("vshiftw ");
22935 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22936 st->print_raw(",");
22937 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22938 st->print_raw(",");
22939 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22940 st->print_raw("\n\t");
22941 st->print_raw("vpand ");
22942 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22943 st->print_raw(",");
22944 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22945 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22946 st->print_raw("vextracti128_high ");
22947 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22948 st->print_raw(",");
22949 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22950 st->print_raw("\n\t");
22951 st->print_raw("vpackuswb ");
22952 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22953 st->print_raw(",");
22954 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22955 st->print_raw(",");
22956 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22957 st->print_raw("\n\t! packed16B shift");
22958}
22959#endif
22960#ifndef PRODUCT
22961void vshift16B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
22962 // Start at oper_input_base() and count operands
22963 unsigned idx0 = 1;
22964 unsigned idx1 = 1; // src
22965 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
22966 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
22967 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
22968 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
22969 st->print_raw("vextendbw ");
22970 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22971 st->print_raw(",");
22972 opnd_array(1)->ext_format(ra, this,idx1, st); // src
22973 st->print_raw("\n\t");
22974 st->print_raw("vshiftw ");
22975 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22976 st->print_raw(",");
22977 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22978 st->print_raw(",");
22979 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
22980 st->print_raw("\n\t");
22981 st->print_raw("vpand ");
22982 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22983 st->print_raw(",");
22984 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22985 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
22986 st->print_raw("vextracti128_high ");
22987 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22988 st->print_raw(",");
22989 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22990 st->print_raw("\n\t");
22991 st->print_raw("vpackuswb ");
22992 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22993 st->print_raw(",");
22994 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
22995 st->print_raw(",");
22996 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
22997 st->print_raw("\n\t! packed16B shift");
22998}
22999#endif
23000#ifndef PRODUCT
23001void vshift16B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23002 // Start at oper_input_base() and count operands
23003 unsigned idx0 = 1;
23004 unsigned idx1 = 1; // src
23005 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23006 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23007 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
23008 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
23009 st->print_raw("vextendbw ");
23010 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23011 st->print_raw(",");
23012 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23013 st->print_raw("\n\t");
23014 st->print_raw("vshiftw ");
23015 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23016 st->print_raw(",");
23017 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23018 st->print_raw(",");
23019 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23020 st->print_raw("\n\t");
23021 st->print_raw("vpand ");
23022 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23023 st->print_raw(",");
23024 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23025 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23026 st->print_raw("vextracti128_high ");
23027 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23028 st->print_raw(",");
23029 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23030 st->print_raw("\n\t");
23031 st->print_raw("vpackuswb ");
23032 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23033 st->print_raw(",");
23034 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23035 st->print_raw(",");
23036 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23037 st->print_raw("\n\t! packed16B shift");
23038}
23039#endif
23040#ifndef PRODUCT
23041void vshift32B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23042 // Start at oper_input_base() and count operands
23043 unsigned idx0 = 1;
23044 unsigned idx1 = 1; // src
23045 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23046 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23047 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
23048 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
23049 st->print_raw("vextracti128_high ");
23050 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23051 st->print_raw(",");
23052 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23053 st->print_raw("\n\t");
23054 st->print_raw("vextendbw ");
23055 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23056 st->print_raw(",");
23057 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23058 st->print_raw("\n\t");
23059 st->print_raw("vextendbw ");
23060 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23061 st->print_raw(",");
23062 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23063 st->print_raw("\n\t");
23064 st->print_raw("vshiftw ");
23065 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23066 st->print_raw(",");
23067 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23068 st->print_raw(",");
23069 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23070 st->print_raw("\n\t");
23071 st->print_raw("vshiftw ");
23072 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23073 st->print_raw(",");
23074 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23075 st->print_raw(",");
23076 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23077 st->print_raw("\n\t");
23078 st->print_raw("vpand ");
23079 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23080 st->print_raw(",");
23081 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23082 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23083 st->print_raw("vpand ");
23084 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23085 st->print_raw(",");
23086 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23087 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23088 st->print_raw("vpackuswb ");
23089 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23090 st->print_raw(",");
23091 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23092 st->print_raw(",");
23093 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23094 st->print_raw("\n\t");
23095 st->print_raw("vpermq ");
23096 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23097 st->print_raw(",");
23098 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23099 st->print_raw(",0xD8\n\t! packed32B shift");
23100}
23101#endif
23102#ifndef PRODUCT
23103void vshift32B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23104 // Start at oper_input_base() and count operands
23105 unsigned idx0 = 1;
23106 unsigned idx1 = 1; // src
23107 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23108 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23109 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
23110 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
23111 st->print_raw("vextracti128_high ");
23112 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23113 st->print_raw(",");
23114 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23115 st->print_raw("\n\t");
23116 st->print_raw("vextendbw ");
23117 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23118 st->print_raw(",");
23119 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23120 st->print_raw("\n\t");
23121 st->print_raw("vextendbw ");
23122 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23123 st->print_raw(",");
23124 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23125 st->print_raw("\n\t");
23126 st->print_raw("vshiftw ");
23127 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23128 st->print_raw(",");
23129 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23130 st->print_raw(",");
23131 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23132 st->print_raw("\n\t");
23133 st->print_raw("vshiftw ");
23134 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23135 st->print_raw(",");
23136 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23137 st->print_raw(",");
23138 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23139 st->print_raw("\n\t");
23140 st->print_raw("vpand ");
23141 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23142 st->print_raw(",");
23143 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23144 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23145 st->print_raw("vpand ");
23146 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23147 st->print_raw(",");
23148 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23149 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23150 st->print_raw("vpackuswb ");
23151 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23152 st->print_raw(",");
23153 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23154 st->print_raw(",");
23155 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23156 st->print_raw("\n\t");
23157 st->print_raw("vpermq ");
23158 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23159 st->print_raw(",");
23160 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23161 st->print_raw(",0xD8\n\t! packed32B shift");
23162}
23163#endif
23164#ifndef PRODUCT
23165void vshift32B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23166 // Start at oper_input_base() and count operands
23167 unsigned idx0 = 1;
23168 unsigned idx1 = 1; // src
23169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23170 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23171 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
23172 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
23173 st->print_raw("vextracti128_high ");
23174 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23175 st->print_raw(",");
23176 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23177 st->print_raw("\n\t");
23178 st->print_raw("vextendbw ");
23179 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23180 st->print_raw(",");
23181 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23182 st->print_raw("\n\t");
23183 st->print_raw("vextendbw ");
23184 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23185 st->print_raw(",");
23186 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23187 st->print_raw("\n\t");
23188 st->print_raw("vshiftw ");
23189 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23190 st->print_raw(",");
23191 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23192 st->print_raw(",");
23193 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23194 st->print_raw("\n\t");
23195 st->print_raw("vshiftw ");
23196 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23197 st->print_raw(",");
23198 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23199 st->print_raw(",");
23200 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23201 st->print_raw("\n\t");
23202 st->print_raw("vpand ");
23203 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23204 st->print_raw(",");
23205 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23206 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23207 st->print_raw("vpand ");
23208 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23209 st->print_raw(",");
23210 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23211 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23212 st->print_raw("vpackuswb ");
23213 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23214 st->print_raw(",");
23215 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23216 st->print_raw(",");
23217 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
23218 st->print_raw("\n\t");
23219 st->print_raw("vpermq ");
23220 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23221 st->print_raw(",");
23222 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23223 st->print_raw(",0xD8\n\t! packed32B shift");
23224}
23225#endif
23226#ifndef PRODUCT
23227void vshift64B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23228 // Start at oper_input_base() and count operands
23229 unsigned idx0 = 1;
23230 unsigned idx1 = 1; // src
23231 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23232 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23233 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
23234 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
23235 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
23236 st->print_raw("vextracti64x4 ");
23237 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23238 st->print_raw(",");
23239 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23240 st->print_raw("\n\t");
23241 st->print_raw("vextendbw ");
23242 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23243 st->print_raw(",");
23244 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23245 st->print_raw("\n\t");
23246 st->print_raw("vextendbw ");
23247 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23248 st->print_raw(",");
23249 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23250 st->print_raw("\n\t");
23251 st->print_raw("vshiftw ");
23252 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23253 st->print_raw(",");
23254 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23255 st->print_raw(",");
23256 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23257 st->print_raw("\n\t");
23258 st->print_raw("vshiftw ");
23259 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23260 st->print_raw(",");
23261 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23262 st->print_raw(",");
23263 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23264 st->print_raw("\n\t");
23265 st->print_raw("vmovdqu ");
23266 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23267 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23268 st->print_raw("vpbroadcastd ");
23269 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23270 st->print_raw(",");
23271 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23272 st->print_raw("\n\t");
23273 st->print_raw("vpand ");
23274 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23275 st->print_raw(",");
23276 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23277 st->print_raw(",");
23278 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23279 st->print_raw("\n\t");
23280 st->print_raw("vpand ");
23281 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23282 st->print_raw(",");
23283 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23284 st->print_raw(",");
23285 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23286 st->print_raw("\n\t");
23287 st->print_raw("vpackuswb ");
23288 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23289 st->print_raw(",");
23290 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23291 st->print_raw(",");
23292 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23293 st->print_raw("\n\t");
23294 st->print_raw("evmovdquq ");
23295 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23296 st->print_raw(", [0x0604020007050301]\n\t");
23297 st->print_raw("vpermq ");
23298 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23299 st->print_raw(",");
23300 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23301 st->print_raw(",");
23302 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23303 st->print_raw("\n\t! packed64B shift");
23304}
23305#endif
23306#ifndef PRODUCT
23307void vshift64B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23308 // Start at oper_input_base() and count operands
23309 unsigned idx0 = 1;
23310 unsigned idx1 = 1; // src
23311 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23312 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23313 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
23314 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
23315 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
23316 st->print_raw("vextracti64x4 ");
23317 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23318 st->print_raw(",");
23319 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23320 st->print_raw("\n\t");
23321 st->print_raw("vextendbw ");
23322 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23323 st->print_raw(",");
23324 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23325 st->print_raw("\n\t");
23326 st->print_raw("vextendbw ");
23327 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23328 st->print_raw(",");
23329 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23330 st->print_raw("\n\t");
23331 st->print_raw("vshiftw ");
23332 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23333 st->print_raw(",");
23334 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23335 st->print_raw(",");
23336 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23337 st->print_raw("\n\t");
23338 st->print_raw("vshiftw ");
23339 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23340 st->print_raw(",");
23341 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23342 st->print_raw(",");
23343 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23344 st->print_raw("\n\t");
23345 st->print_raw("vmovdqu ");
23346 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23347 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23348 st->print_raw("vpbroadcastd ");
23349 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23350 st->print_raw(",");
23351 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23352 st->print_raw("\n\t");
23353 st->print_raw("vpand ");
23354 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23355 st->print_raw(",");
23356 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23357 st->print_raw(",");
23358 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23359 st->print_raw("\n\t");
23360 st->print_raw("vpand ");
23361 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23362 st->print_raw(",");
23363 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23364 st->print_raw(",");
23365 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23366 st->print_raw("\n\t");
23367 st->print_raw("vpackuswb ");
23368 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23369 st->print_raw(",");
23370 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23371 st->print_raw(",");
23372 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23373 st->print_raw("\n\t");
23374 st->print_raw("evmovdquq ");
23375 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23376 st->print_raw(", [0x0604020007050301]\n\t");
23377 st->print_raw("vpermq ");
23378 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23379 st->print_raw(",");
23380 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23381 st->print_raw(",");
23382 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23383 st->print_raw("\n\t! packed64B shift");
23384}
23385#endif
23386#ifndef PRODUCT
23387void vshift64B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23388 // Start at oper_input_base() and count operands
23389 unsigned idx0 = 1;
23390 unsigned idx1 = 1; // src
23391 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23392 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23393 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
23394 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
23395 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
23396 st->print_raw("vextracti64x4 ");
23397 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23398 st->print_raw(",");
23399 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23400 st->print_raw("\n\t");
23401 st->print_raw("vextendbw ");
23402 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23403 st->print_raw(",");
23404 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23405 st->print_raw("\n\t");
23406 st->print_raw("vextendbw ");
23407 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23408 st->print_raw(",");
23409 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23410 st->print_raw("\n\t");
23411 st->print_raw("vshiftw ");
23412 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23413 st->print_raw(",");
23414 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23415 st->print_raw(",");
23416 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23417 st->print_raw("\n\t");
23418 st->print_raw("vshiftw ");
23419 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23420 st->print_raw(",");
23421 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23422 st->print_raw(",");
23423 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23424 st->print_raw("\n\t");
23425 st->print_raw("vmovdqu ");
23426 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23427 st->print_raw(",[0x00ff00ff0x00ff00ff]\n\t");
23428 st->print_raw("vpbroadcastd ");
23429 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23430 st->print_raw(",");
23431 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23432 st->print_raw("\n\t");
23433 st->print_raw("vpand ");
23434 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23435 st->print_raw(",");
23436 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23437 st->print_raw(",");
23438 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23439 st->print_raw("\n\t");
23440 st->print_raw("vpand ");
23441 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23442 st->print_raw(",");
23443 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23444 st->print_raw(",");
23445 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23446 st->print_raw("\n\t");
23447 st->print_raw("vpackuswb ");
23448 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23449 st->print_raw(",");
23450 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1
23451 st->print_raw(",");
23452 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23453 st->print_raw("\n\t");
23454 st->print_raw("evmovdquq ");
23455 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23456 st->print_raw(", [0x0604020007050301]\n\t");
23457 st->print_raw("vpermq ");
23458 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23459 st->print_raw(",");
23460 opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2
23461 st->print_raw(",");
23462 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23463 st->print_raw("\n\t! packed64B shift");
23464}
23465#endif
23466#ifndef PRODUCT
23467void vshist2SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23468 // Start at oper_input_base() and count operands
23469 unsigned idx0 = 1;
23470 unsigned idx1 = 1; // src
23471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23472 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23473 st->print_raw("vshiftw ");
23474 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23475 st->print_raw(",");
23476 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23477 st->print_raw(",");
23478 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23479 st->print_raw("\t! shift packed2S");
23480}
23481#endif
23482#ifndef PRODUCT
23483void vshist2S_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23484 // Start at oper_input_base() and count operands
23485 unsigned idx0 = 1;
23486 unsigned idx1 = 1; // src
23487 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23488 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23489 st->print_raw("vshiftw ");
23490 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23491 st->print_raw(",");
23492 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23493 st->print_raw(",");
23494 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23495 st->print_raw("\t! shift packed2S");
23496}
23497#endif
23498#ifndef PRODUCT
23499void vshist2S_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23500 // Start at oper_input_base() and count operands
23501 unsigned idx0 = 1;
23502 unsigned idx1 = 1; // src
23503 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23504 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23505 st->print_raw("vshiftw ");
23506 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23507 st->print_raw(",");
23508 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23509 st->print_raw(",");
23510 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23511 st->print_raw("\t! shift packed2S");
23512}
23513#endif
23514#ifndef PRODUCT
23515void vshift4SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23516 // Start at oper_input_base() and count operands
23517 unsigned idx0 = 1;
23518 unsigned idx1 = 1; // src
23519 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23520 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23521 st->print_raw("vshiftw ");
23522 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23523 st->print_raw(",");
23524 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23525 st->print_raw(",");
23526 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23527 st->print_raw("\t! shift packed4S");
23528}
23529#endif
23530#ifndef PRODUCT
23531void vshift4S_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23532 // Start at oper_input_base() and count operands
23533 unsigned idx0 = 1;
23534 unsigned idx1 = 1; // src
23535 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23536 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23537 st->print_raw("vshiftw ");
23538 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23539 st->print_raw(",");
23540 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23541 st->print_raw(",");
23542 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23543 st->print_raw("\t! shift packed4S");
23544}
23545#endif
23546#ifndef PRODUCT
23547void vshift4S_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23548 // Start at oper_input_base() and count operands
23549 unsigned idx0 = 1;
23550 unsigned idx1 = 1; // src
23551 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23552 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23553 st->print_raw("vshiftw ");
23554 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23555 st->print_raw(",");
23556 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23557 st->print_raw(",");
23558 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23559 st->print_raw("\t! shift packed4S");
23560}
23561#endif
23562#ifndef PRODUCT
23563void vshift8SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23564 // Start at oper_input_base() and count operands
23565 unsigned idx0 = 1;
23566 unsigned idx1 = 1; // src
23567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23568 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23569 st->print_raw("vshiftw ");
23570 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23571 st->print_raw(",");
23572 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23573 st->print_raw(",");
23574 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23575 st->print_raw("\t! shift packed8S");
23576}
23577#endif
23578#ifndef PRODUCT
23579void vshift8S_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23580 // Start at oper_input_base() and count operands
23581 unsigned idx0 = 1;
23582 unsigned idx1 = 1; // src
23583 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23584 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23585 st->print_raw("vshiftw ");
23586 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23587 st->print_raw(",");
23588 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23589 st->print_raw(",");
23590 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23591 st->print_raw("\t! shift packed8S");
23592}
23593#endif
23594#ifndef PRODUCT
23595void vshift8S_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23596 // Start at oper_input_base() and count operands
23597 unsigned idx0 = 1;
23598 unsigned idx1 = 1; // src
23599 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23600 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23601 st->print_raw("vshiftw ");
23602 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23603 st->print_raw(",");
23604 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23605 st->print_raw(",");
23606 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23607 st->print_raw("\t! shift packed8S");
23608}
23609#endif
23610#ifndef PRODUCT
23611void vshift16SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23612 // Start at oper_input_base() and count operands
23613 unsigned idx0 = 1;
23614 unsigned idx1 = 1; // src
23615 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23616 st->print_raw("vshiftw ");
23617 opnd_array(0)->int_format(ra, this, st); // dst
23618 st->print_raw(",");
23619 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23620 st->print_raw(",");
23621 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23622 st->print_raw("\t! shift packed16S");
23623}
23624#endif
23625#ifndef PRODUCT
23626void vshift16S_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23627 // Start at oper_input_base() and count operands
23628 unsigned idx0 = 1;
23629 unsigned idx1 = 1; // src
23630 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23631 st->print_raw("vshiftw ");
23632 opnd_array(0)->int_format(ra, this, st); // dst
23633 st->print_raw(",");
23634 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23635 st->print_raw(",");
23636 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23637 st->print_raw("\t! shift packed16S");
23638}
23639#endif
23640#ifndef PRODUCT
23641void vshift16S_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23642 // Start at oper_input_base() and count operands
23643 unsigned idx0 = 1;
23644 unsigned idx1 = 1; // src
23645 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23646 st->print_raw("vshiftw ");
23647 opnd_array(0)->int_format(ra, this, st); // dst
23648 st->print_raw(",");
23649 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23650 st->print_raw(",");
23651 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23652 st->print_raw("\t! shift packed16S");
23653}
23654#endif
23655#ifndef PRODUCT
23656void vshift32SNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23657 // Start at oper_input_base() and count operands
23658 unsigned idx0 = 1;
23659 unsigned idx1 = 1; // src
23660 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23661 st->print_raw("vshiftw ");
23662 opnd_array(0)->int_format(ra, this, st); // dst
23663 st->print_raw(",");
23664 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23665 st->print_raw(",");
23666 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23667 st->print_raw("\t! shift packed32S");
23668}
23669#endif
23670#ifndef PRODUCT
23671void vshift32S_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23672 // Start at oper_input_base() and count operands
23673 unsigned idx0 = 1;
23674 unsigned idx1 = 1; // src
23675 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23676 st->print_raw("vshiftw ");
23677 opnd_array(0)->int_format(ra, this, st); // dst
23678 st->print_raw(",");
23679 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23680 st->print_raw(",");
23681 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23682 st->print_raw("\t! shift packed32S");
23683}
23684#endif
23685#ifndef PRODUCT
23686void vshift32S_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23687 // Start at oper_input_base() and count operands
23688 unsigned idx0 = 1;
23689 unsigned idx1 = 1; // src
23690 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23691 st->print_raw("vshiftw ");
23692 opnd_array(0)->int_format(ra, this, st); // dst
23693 st->print_raw(",");
23694 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23695 st->print_raw(",");
23696 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23697 st->print_raw("\t! shift packed32S");
23698}
23699#endif
23700#ifndef PRODUCT
23701void vshift2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
23702 // Start at oper_input_base() and count operands
23703 unsigned idx0 = 1;
23704 unsigned idx1 = 1; // src
23705 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23706 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23707 st->print_raw("vshiftd ");
23708 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23709 st->print_raw(",");
23710 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23711 st->print_raw(",");
23712 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23713 st->print_raw("\t! shift packed2I");
23714}
23715#endif
23716#ifndef PRODUCT
23717void vshift2I_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23718 // Start at oper_input_base() and count operands
23719 unsigned idx0 = 1;
23720 unsigned idx1 = 1; // src
23721 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23722 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23723 st->print_raw("vshiftd ");
23724 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23725 st->print_raw(",");
23726 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23727 st->print_raw(",");
23728 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23729 st->print_raw("\t! shift packed2I");
23730}
23731#endif
23732#ifndef PRODUCT
23733void vshift2I_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23734 // Start at oper_input_base() and count operands
23735 unsigned idx0 = 1;
23736 unsigned idx1 = 1; // src
23737 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23738 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23739 st->print_raw("vshiftd ");
23740 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23741 st->print_raw(",");
23742 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23743 st->print_raw(",");
23744 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23745 st->print_raw("\t! shift packed2I");
23746}
23747#endif
23748#ifndef PRODUCT
23749void vshift4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
23750 // Start at oper_input_base() and count operands
23751 unsigned idx0 = 1;
23752 unsigned idx1 = 1; // src
23753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23754 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23755 st->print_raw("vshiftd ");
23756 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23757 st->print_raw(",");
23758 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23759 st->print_raw(",");
23760 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23761 st->print_raw("\t! shift packed4I");
23762}
23763#endif
23764#ifndef PRODUCT
23765void vshift4I_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23766 // Start at oper_input_base() and count operands
23767 unsigned idx0 = 1;
23768 unsigned idx1 = 1; // src
23769 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23770 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23771 st->print_raw("vshiftd ");
23772 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23773 st->print_raw(",");
23774 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23775 st->print_raw(",");
23776 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23777 st->print_raw("\t! shift packed4I");
23778}
23779#endif
23780#ifndef PRODUCT
23781void vshift4I_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23782 // Start at oper_input_base() and count operands
23783 unsigned idx0 = 1;
23784 unsigned idx1 = 1; // src
23785 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23786 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23787 st->print_raw("vshiftd ");
23788 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23789 st->print_raw(",");
23790 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23791 st->print_raw(",");
23792 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23793 st->print_raw("\t! shift packed4I");
23794}
23795#endif
23796#ifndef PRODUCT
23797void vshift8INode::format(PhaseRegAlloc *ra, outputStream *st) const {
23798 // Start at oper_input_base() and count operands
23799 unsigned idx0 = 1;
23800 unsigned idx1 = 1; // src
23801 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23802 st->print_raw("vshiftd ");
23803 opnd_array(0)->int_format(ra, this, st); // dst
23804 st->print_raw(",");
23805 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23806 st->print_raw(",");
23807 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23808 st->print_raw("\t! shift packed8I");
23809}
23810#endif
23811#ifndef PRODUCT
23812void vshift8I_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23813 // Start at oper_input_base() and count operands
23814 unsigned idx0 = 1;
23815 unsigned idx1 = 1; // src
23816 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23817 st->print_raw("vshiftd ");
23818 opnd_array(0)->int_format(ra, this, st); // dst
23819 st->print_raw(",");
23820 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23821 st->print_raw(",");
23822 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23823 st->print_raw("\t! shift packed8I");
23824}
23825#endif
23826#ifndef PRODUCT
23827void vshift8I_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23828 // Start at oper_input_base() and count operands
23829 unsigned idx0 = 1;
23830 unsigned idx1 = 1; // src
23831 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23832 st->print_raw("vshiftd ");
23833 opnd_array(0)->int_format(ra, this, st); // dst
23834 st->print_raw(",");
23835 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23836 st->print_raw(",");
23837 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23838 st->print_raw("\t! shift packed8I");
23839}
23840#endif
23841#ifndef PRODUCT
23842void vshift16INode::format(PhaseRegAlloc *ra, outputStream *st) const {
23843 // Start at oper_input_base() and count operands
23844 unsigned idx0 = 1;
23845 unsigned idx1 = 1; // src
23846 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23847 st->print_raw("vshiftd ");
23848 opnd_array(0)->int_format(ra, this, st); // dst
23849 st->print_raw(",");
23850 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23851 st->print_raw(",");
23852 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23853 st->print_raw("\t! shift packed16I");
23854}
23855#endif
23856#ifndef PRODUCT
23857void vshift16I_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23858 // Start at oper_input_base() and count operands
23859 unsigned idx0 = 1;
23860 unsigned idx1 = 1; // src
23861 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23862 st->print_raw("vshiftd ");
23863 opnd_array(0)->int_format(ra, this, st); // dst
23864 st->print_raw(",");
23865 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23866 st->print_raw(",");
23867 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23868 st->print_raw("\t! shift packed16I");
23869}
23870#endif
23871#ifndef PRODUCT
23872void vshift16I_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23873 // Start at oper_input_base() and count operands
23874 unsigned idx0 = 1;
23875 unsigned idx1 = 1; // src
23876 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23877 st->print_raw("vshiftd ");
23878 opnd_array(0)->int_format(ra, this, st); // dst
23879 st->print_raw(",");
23880 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23881 st->print_raw(",");
23882 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23883 st->print_raw("\t! shift packed16I");
23884}
23885#endif
23886#ifndef PRODUCT
23887void vshift2LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23888 // Start at oper_input_base() and count operands
23889 unsigned idx0 = 1;
23890 unsigned idx1 = 1; // src
23891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23893 st->print_raw("vshiftq ");
23894 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23895 st->print_raw(",");
23896 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23897 st->print_raw(",");
23898 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23899 st->print_raw("\t! shift packed2L");
23900}
23901#endif
23902#ifndef PRODUCT
23903void vshift2L_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23904 // Start at oper_input_base() and count operands
23905 unsigned idx0 = 1;
23906 unsigned idx1 = 1; // src
23907 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23908 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
23909 st->print_raw("vshiftq ");
23910 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
23911 st->print_raw(",");
23912 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23913 st->print_raw(",");
23914 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23915 st->print_raw("\t! shift packed2L");
23916}
23917#endif
23918#ifndef PRODUCT
23919void vshift4LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23920 // Start at oper_input_base() and count operands
23921 unsigned idx0 = 1;
23922 unsigned idx1 = 1; // src
23923 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23924 st->print_raw("vshiftq ");
23925 opnd_array(0)->int_format(ra, this, st); // dst
23926 st->print_raw(",");
23927 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23928 st->print_raw(",");
23929 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23930 st->print_raw("\t! left shift packed4L");
23931}
23932#endif
23933#ifndef PRODUCT
23934void vshift4L_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23935 // Start at oper_input_base() and count operands
23936 unsigned idx0 = 1;
23937 unsigned idx1 = 1; // src
23938 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23939 st->print_raw("vshiftq ");
23940 opnd_array(0)->int_format(ra, this, st); // dst
23941 st->print_raw(",");
23942 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23943 st->print_raw(",");
23944 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23945 st->print_raw("\t! left shift packed4L");
23946}
23947#endif
23948#ifndef PRODUCT
23949void vshift8LNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23950 // Start at oper_input_base() and count operands
23951 unsigned idx0 = 1;
23952 unsigned idx1 = 1; // src
23953 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23954 st->print_raw("vshiftq ");
23955 opnd_array(0)->int_format(ra, this, st); // dst
23956 st->print_raw(",");
23957 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23958 st->print_raw(",");
23959 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23960 st->print_raw("\t! shift packed8L");
23961}
23962#endif
23963#ifndef PRODUCT
23964void vshift8L_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23965 // Start at oper_input_base() and count operands
23966 unsigned idx0 = 1;
23967 unsigned idx1 = 1; // src
23968 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23969 st->print_raw("vshiftq ");
23970 opnd_array(0)->int_format(ra, this, st); // dst
23971 st->print_raw(",");
23972 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23973 st->print_raw(",");
23974 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23975 st->print_raw("\t! shift packed8L");
23976}
23977#endif
23978#ifndef PRODUCT
23979void vshift8L_1Node::format(PhaseRegAlloc *ra, outputStream *st) const {
23980 // Start at oper_input_base() and count operands
23981 unsigned idx0 = 1;
23982 unsigned idx1 = 1; // src
23983 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23984 st->print_raw("vshiftq ");
23985 opnd_array(0)->int_format(ra, this, st); // dst
23986 st->print_raw(",");
23987 opnd_array(1)->ext_format(ra, this,idx1, st); // src
23988 st->print_raw(",");
23989 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
23990 st->print_raw("\t! shift packed8L");
23991}
23992#endif
23993#ifndef PRODUCT
23994void vsra2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
23995 // Start at oper_input_base() and count operands
23996 unsigned idx0 = 1;
23997 unsigned idx1 = 1; // src
23998 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
23999 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24000 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
24001 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
24002 st->print_raw("movdqu ");
24003 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24004 st->print_raw(",");
24005 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24006 st->print_raw("\n\t");
24007 st->print_raw("psrlq ");
24008 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24009 st->print_raw(",");
24010 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24011 st->print_raw("\n\t");
24012 st->print_raw("movdqu ");
24013 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24014 st->print_raw(",[0x8000000000000000]\n\t");
24015 st->print_raw("psrlq ");
24016 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24017 st->print_raw(",");
24018 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24019 st->print_raw("\n\t");
24020 st->print_raw("pxor ");
24021 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24022 st->print_raw(",");
24023 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24024 st->print_raw("\n\t");
24025 st->print_raw("psubq ");
24026 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24027 st->print_raw(",");
24028 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24029 st->print_raw("\t! arithmetic right shift packed2L");
24030}
24031#endif
24032#ifndef PRODUCT
24033void vsra2L_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24034 // Start at oper_input_base() and count operands
24035 unsigned idx0 = 1;
24036 unsigned idx1 = 1; // src
24037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24038 st->print_raw("evpsraq ");
24039 opnd_array(0)->int_format(ra, this, st); // dst
24040 st->print_raw(",");
24041 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24042 st->print_raw(",");
24043 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24044 st->print_raw("\t! arithmetic right shift packed2L");
24045}
24046#endif
24047#ifndef PRODUCT
24048void vsra4L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24049 // Start at oper_input_base() and count operands
24050 unsigned idx0 = 1;
24051 unsigned idx1 = 1; // src
24052 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24053 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
24054 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
24055 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
24056 st->print_raw("vpsrlq ");
24057 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24058 st->print_raw(",");
24059 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24060 st->print_raw(",");
24061 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24062 st->print_raw("\n\t");
24063 st->print_raw("vmovdqu ");
24064 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24065 st->print_raw(",[0x8000000000000000]\n\t");
24066 st->print_raw("vpsrlq ");
24067 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24068 st->print_raw(",");
24069 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24070 st->print_raw(",");
24071 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24072 st->print_raw("\n\t");
24073 st->print_raw("vpxor ");
24074 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24075 st->print_raw(",");
24076 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24077 st->print_raw(",");
24078 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24079 st->print_raw("\n\t");
24080 st->print_raw("vpsubq ");
24081 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24082 st->print_raw(",");
24083 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
24084 st->print_raw(",");
24085 opnd_array(4)->ext_format(ra, this,idx4, st); // tmp
24086 st->print_raw("\t! arithmetic right shift packed4L");
24087}
24088#endif
24089#ifndef PRODUCT
24090void vsra4L_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24091 // Start at oper_input_base() and count operands
24092 unsigned idx0 = 1;
24093 unsigned idx1 = 1; // src
24094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24095 st->print_raw("evpsraq ");
24096 opnd_array(0)->int_format(ra, this, st); // dst
24097 st->print_raw(",");
24098 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24099 st->print_raw(",");
24100 opnd_array(2)->ext_format(ra, this,idx2, st); // shift
24101 st->print_raw("\t! arithmetic right shift packed4L");
24102}
24103#endif
24104#ifndef PRODUCT
24105void vand4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24106 // Start at oper_input_base() and count operands
24107 unsigned idx0 = 1;
24108 unsigned idx1 = 1; // dst
24109 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24110 st->print_raw("pand ");
24111 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24112 st->print_raw(",");
24113 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24114 st->print_raw("\t! and vectors (4 bytes)");
24115}
24116#endif
24117#ifndef PRODUCT
24118void vand4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24119 // Start at oper_input_base() and count operands
24120 unsigned idx0 = 1;
24121 unsigned idx1 = 1; // src1
24122 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24123 st->print_raw("vpand ");
24124 opnd_array(0)->int_format(ra, this, st); // dst
24125 st->print_raw(",");
24126 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24127 st->print_raw(",");
24128 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24129 st->print_raw("\t! and vectors (4 bytes)");
24130}
24131#endif
24132#ifndef PRODUCT
24133void vand4B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24134 // Start at oper_input_base() and count operands
24135 unsigned idx0 = 2;
24136 unsigned idx1 = 2; // src
24137 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24138 st->print_raw("vpand ");
24139 opnd_array(0)->int_format(ra, this, st); // dst
24140 st->print_raw(",");
24141 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24142 st->print_raw(",");
24143 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24144 st->print_raw("\t! and vectors (4 bytes)");
24145}
24146#endif
24147#ifndef PRODUCT
24148void vand4B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24149 // Start at oper_input_base() and count operands
24150 unsigned idx0 = 2;
24151 unsigned idx1 = 2; // mem
24152 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24153 st->print_raw("vpand ");
24154 opnd_array(0)->int_format(ra, this, st); // dst
24155 st->print_raw(",");
24156 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24157 st->print_raw(",");
24158 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24159 st->print_raw("\t! and vectors (4 bytes)");
24160}
24161#endif
24162#ifndef PRODUCT
24163void vand8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24164 // Start at oper_input_base() and count operands
24165 unsigned idx0 = 1;
24166 unsigned idx1 = 1; // dst
24167 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24168 st->print_raw("pand ");
24169 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24170 st->print_raw(",");
24171 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24172 st->print_raw("\t! and vectors (8 bytes)");
24173}
24174#endif
24175#ifndef PRODUCT
24176void vand8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24177 // Start at oper_input_base() and count operands
24178 unsigned idx0 = 1;
24179 unsigned idx1 = 1; // src1
24180 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24181 st->print_raw("vpand ");
24182 opnd_array(0)->int_format(ra, this, st); // dst
24183 st->print_raw(",");
24184 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24185 st->print_raw(",");
24186 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24187 st->print_raw("\t! and vectors (8 bytes)");
24188}
24189#endif
24190#ifndef PRODUCT
24191void vand8B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24192 // Start at oper_input_base() and count operands
24193 unsigned idx0 = 2;
24194 unsigned idx1 = 2; // src
24195 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24196 st->print_raw("vpand ");
24197 opnd_array(0)->int_format(ra, this, st); // dst
24198 st->print_raw(",");
24199 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24200 st->print_raw(",");
24201 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24202 st->print_raw("\t! and vectors (8 bytes)");
24203}
24204#endif
24205#ifndef PRODUCT
24206void vand8B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24207 // Start at oper_input_base() and count operands
24208 unsigned idx0 = 2;
24209 unsigned idx1 = 2; // mem
24210 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24211 st->print_raw("vpand ");
24212 opnd_array(0)->int_format(ra, this, st); // dst
24213 st->print_raw(",");
24214 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24215 st->print_raw(",");
24216 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24217 st->print_raw("\t! and vectors (8 bytes)");
24218}
24219#endif
24220#ifndef PRODUCT
24221void vand16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24222 // Start at oper_input_base() and count operands
24223 unsigned idx0 = 1;
24224 unsigned idx1 = 1; // dst
24225 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24226 st->print_raw("pand ");
24227 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24228 st->print_raw(",");
24229 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24230 st->print_raw("\t! and vectors (16 bytes)");
24231}
24232#endif
24233#ifndef PRODUCT
24234void vand16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24235 // Start at oper_input_base() and count operands
24236 unsigned idx0 = 1;
24237 unsigned idx1 = 1; // src1
24238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24239 st->print_raw("vpand ");
24240 opnd_array(0)->int_format(ra, this, st); // dst
24241 st->print_raw(",");
24242 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24243 st->print_raw(",");
24244 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24245 st->print_raw("\t! and vectors (16 bytes)");
24246}
24247#endif
24248#ifndef PRODUCT
24249void vand16B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24250 // Start at oper_input_base() and count operands
24251 unsigned idx0 = 2;
24252 unsigned idx1 = 2; // src
24253 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24254 st->print_raw("vpand ");
24255 opnd_array(0)->int_format(ra, this, st); // dst
24256 st->print_raw(",");
24257 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24258 st->print_raw(",");
24259 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24260 st->print_raw("\t! and vectors (16 bytes)");
24261}
24262#endif
24263#ifndef PRODUCT
24264void vand16B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24265 // Start at oper_input_base() and count operands
24266 unsigned idx0 = 2;
24267 unsigned idx1 = 2; // mem
24268 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24269 st->print_raw("vpand ");
24270 opnd_array(0)->int_format(ra, this, st); // dst
24271 st->print_raw(",");
24272 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24273 st->print_raw(",");
24274 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24275 st->print_raw("\t! and vectors (16 bytes)");
24276}
24277#endif
24278#ifndef PRODUCT
24279void vand32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24280 // Start at oper_input_base() and count operands
24281 unsigned idx0 = 1;
24282 unsigned idx1 = 1; // src1
24283 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24284 st->print_raw("vpand ");
24285 opnd_array(0)->int_format(ra, this, st); // dst
24286 st->print_raw(",");
24287 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24288 st->print_raw(",");
24289 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24290 st->print_raw("\t! and vectors (32 bytes)");
24291}
24292#endif
24293#ifndef PRODUCT
24294void vand32B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24295 // Start at oper_input_base() and count operands
24296 unsigned idx0 = 2;
24297 unsigned idx1 = 2; // src
24298 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24299 st->print_raw("vpand ");
24300 opnd_array(0)->int_format(ra, this, st); // dst
24301 st->print_raw(",");
24302 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24303 st->print_raw(",");
24304 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24305 st->print_raw("\t! and vectors (32 bytes)");
24306}
24307#endif
24308#ifndef PRODUCT
24309void vand32B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24310 // Start at oper_input_base() and count operands
24311 unsigned idx0 = 2;
24312 unsigned idx1 = 2; // mem
24313 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24314 st->print_raw("vpand ");
24315 opnd_array(0)->int_format(ra, this, st); // dst
24316 st->print_raw(",");
24317 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24318 st->print_raw(",");
24319 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24320 st->print_raw("\t! and vectors (32 bytes)");
24321}
24322#endif
24323#ifndef PRODUCT
24324void vand64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24325 // Start at oper_input_base() and count operands
24326 unsigned idx0 = 1;
24327 unsigned idx1 = 1; // src1
24328 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24329 st->print_raw("vpand ");
24330 opnd_array(0)->int_format(ra, this, st); // dst
24331 st->print_raw(",");
24332 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24333 st->print_raw(",");
24334 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24335 st->print_raw("\t! and vectors (64 bytes)");
24336}
24337#endif
24338#ifndef PRODUCT
24339void vand64B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24340 // Start at oper_input_base() and count operands
24341 unsigned idx0 = 2;
24342 unsigned idx1 = 2; // src
24343 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24344 st->print_raw("vpand ");
24345 opnd_array(0)->int_format(ra, this, st); // dst
24346 st->print_raw(",");
24347 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24348 st->print_raw(",");
24349 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24350 st->print_raw("\t! and vectors (64 bytes)");
24351}
24352#endif
24353#ifndef PRODUCT
24354void vand64B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24355 // Start at oper_input_base() and count operands
24356 unsigned idx0 = 2;
24357 unsigned idx1 = 2; // mem
24358 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24359 st->print_raw("vpand ");
24360 opnd_array(0)->int_format(ra, this, st); // dst
24361 st->print_raw(",");
24362 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24363 st->print_raw(",");
24364 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24365 st->print_raw("\t! and vectors (64 bytes)");
24366}
24367#endif
24368#ifndef PRODUCT
24369void vor4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24370 // Start at oper_input_base() and count operands
24371 unsigned idx0 = 1;
24372 unsigned idx1 = 1; // dst
24373 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24374 st->print_raw("por ");
24375 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24376 st->print_raw(",");
24377 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24378 st->print_raw("\t! or vectors (4 bytes)");
24379}
24380#endif
24381#ifndef PRODUCT
24382void vor4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24383 // Start at oper_input_base() and count operands
24384 unsigned idx0 = 1;
24385 unsigned idx1 = 1; // src1
24386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24387 st->print_raw("vpor ");
24388 opnd_array(0)->int_format(ra, this, st); // dst
24389 st->print_raw(",");
24390 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24391 st->print_raw(",");
24392 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24393 st->print_raw("\t! or vectors (4 bytes)");
24394}
24395#endif
24396#ifndef PRODUCT
24397void vor4B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24398 // Start at oper_input_base() and count operands
24399 unsigned idx0 = 2;
24400 unsigned idx1 = 2; // src
24401 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24402 st->print_raw("vpor ");
24403 opnd_array(0)->int_format(ra, this, st); // dst
24404 st->print_raw(",");
24405 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24406 st->print_raw(",");
24407 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24408 st->print_raw("\t! or vectors (4 bytes)");
24409}
24410#endif
24411#ifndef PRODUCT
24412void vor4B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24413 // Start at oper_input_base() and count operands
24414 unsigned idx0 = 2;
24415 unsigned idx1 = 2; // mem
24416 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24417 st->print_raw("vpor ");
24418 opnd_array(0)->int_format(ra, this, st); // dst
24419 st->print_raw(",");
24420 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24421 st->print_raw(",");
24422 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24423 st->print_raw("\t! or vectors (4 bytes)");
24424}
24425#endif
24426#ifndef PRODUCT
24427void vor8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24428 // Start at oper_input_base() and count operands
24429 unsigned idx0 = 1;
24430 unsigned idx1 = 1; // dst
24431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24432 st->print_raw("por ");
24433 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24434 st->print_raw(",");
24435 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24436 st->print_raw("\t! or vectors (8 bytes)");
24437}
24438#endif
24439#ifndef PRODUCT
24440void vor8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24441 // Start at oper_input_base() and count operands
24442 unsigned idx0 = 1;
24443 unsigned idx1 = 1; // src1
24444 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24445 st->print_raw("vpor ");
24446 opnd_array(0)->int_format(ra, this, st); // dst
24447 st->print_raw(",");
24448 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24449 st->print_raw(",");
24450 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24451 st->print_raw("\t! or vectors (8 bytes)");
24452}
24453#endif
24454#ifndef PRODUCT
24455void vor8B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24456 // Start at oper_input_base() and count operands
24457 unsigned idx0 = 2;
24458 unsigned idx1 = 2; // src
24459 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24460 st->print_raw("vpor ");
24461 opnd_array(0)->int_format(ra, this, st); // dst
24462 st->print_raw(",");
24463 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24464 st->print_raw(",");
24465 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24466 st->print_raw("\t! or vectors (8 bytes)");
24467}
24468#endif
24469#ifndef PRODUCT
24470void vor8B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24471 // Start at oper_input_base() and count operands
24472 unsigned idx0 = 2;
24473 unsigned idx1 = 2; // mem
24474 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24475 st->print_raw("vpor ");
24476 opnd_array(0)->int_format(ra, this, st); // dst
24477 st->print_raw(",");
24478 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24479 st->print_raw(",");
24480 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24481 st->print_raw("\t! or vectors (8 bytes)");
24482}
24483#endif
24484#ifndef PRODUCT
24485void vor16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24486 // Start at oper_input_base() and count operands
24487 unsigned idx0 = 1;
24488 unsigned idx1 = 1; // dst
24489 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24490 st->print_raw("por ");
24491 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24492 st->print_raw(",");
24493 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24494 st->print_raw("\t! or vectors (16 bytes)");
24495}
24496#endif
24497#ifndef PRODUCT
24498void vor16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24499 // Start at oper_input_base() and count operands
24500 unsigned idx0 = 1;
24501 unsigned idx1 = 1; // src1
24502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24503 st->print_raw("vpor ");
24504 opnd_array(0)->int_format(ra, this, st); // dst
24505 st->print_raw(",");
24506 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24507 st->print_raw(",");
24508 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24509 st->print_raw("\t! or vectors (16 bytes)");
24510}
24511#endif
24512#ifndef PRODUCT
24513void vor16B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24514 // Start at oper_input_base() and count operands
24515 unsigned idx0 = 2;
24516 unsigned idx1 = 2; // src
24517 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24518 st->print_raw("vpor ");
24519 opnd_array(0)->int_format(ra, this, st); // dst
24520 st->print_raw(",");
24521 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24522 st->print_raw(",");
24523 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24524 st->print_raw("\t! or vectors (16 bytes)");
24525}
24526#endif
24527#ifndef PRODUCT
24528void vor16B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24529 // Start at oper_input_base() and count operands
24530 unsigned idx0 = 2;
24531 unsigned idx1 = 2; // mem
24532 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24533 st->print_raw("vpor ");
24534 opnd_array(0)->int_format(ra, this, st); // dst
24535 st->print_raw(",");
24536 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24537 st->print_raw(",");
24538 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24539 st->print_raw("\t! or vectors (16 bytes)");
24540}
24541#endif
24542#ifndef PRODUCT
24543void vor32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24544 // Start at oper_input_base() and count operands
24545 unsigned idx0 = 1;
24546 unsigned idx1 = 1; // src1
24547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24548 st->print_raw("vpor ");
24549 opnd_array(0)->int_format(ra, this, st); // dst
24550 st->print_raw(",");
24551 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24552 st->print_raw(",");
24553 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24554 st->print_raw("\t! or vectors (32 bytes)");
24555}
24556#endif
24557#ifndef PRODUCT
24558void vor32B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24559 // Start at oper_input_base() and count operands
24560 unsigned idx0 = 2;
24561 unsigned idx1 = 2; // src
24562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24563 st->print_raw("vpor ");
24564 opnd_array(0)->int_format(ra, this, st); // dst
24565 st->print_raw(",");
24566 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24567 st->print_raw(",");
24568 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24569 st->print_raw("\t! or vectors (32 bytes)");
24570}
24571#endif
24572#ifndef PRODUCT
24573void vor32B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24574 // Start at oper_input_base() and count operands
24575 unsigned idx0 = 2;
24576 unsigned idx1 = 2; // mem
24577 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24578 st->print_raw("vpor ");
24579 opnd_array(0)->int_format(ra, this, st); // dst
24580 st->print_raw(",");
24581 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24582 st->print_raw(",");
24583 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24584 st->print_raw("\t! or vectors (32 bytes)");
24585}
24586#endif
24587#ifndef PRODUCT
24588void vor64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24589 // Start at oper_input_base() and count operands
24590 unsigned idx0 = 1;
24591 unsigned idx1 = 1; // src1
24592 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24593 st->print_raw("vpor ");
24594 opnd_array(0)->int_format(ra, this, st); // dst
24595 st->print_raw(",");
24596 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24597 st->print_raw(",");
24598 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24599 st->print_raw("\t! or vectors (64 bytes)");
24600}
24601#endif
24602#ifndef PRODUCT
24603void vor64B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24604 // Start at oper_input_base() and count operands
24605 unsigned idx0 = 2;
24606 unsigned idx1 = 2; // src
24607 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24608 st->print_raw("vpor ");
24609 opnd_array(0)->int_format(ra, this, st); // dst
24610 st->print_raw(",");
24611 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24612 st->print_raw(",");
24613 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24614 st->print_raw("\t! or vectors (64 bytes)");
24615}
24616#endif
24617#ifndef PRODUCT
24618void vor64B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24619 // Start at oper_input_base() and count operands
24620 unsigned idx0 = 2;
24621 unsigned idx1 = 2; // mem
24622 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24623 st->print_raw("vpor ");
24624 opnd_array(0)->int_format(ra, this, st); // dst
24625 st->print_raw(",");
24626 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24627 st->print_raw(",");
24628 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24629 st->print_raw("\t! or vectors (64 bytes)");
24630}
24631#endif
24632#ifndef PRODUCT
24633void vxor4BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24634 // Start at oper_input_base() and count operands
24635 unsigned idx0 = 1;
24636 unsigned idx1 = 1; // dst
24637 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24638 st->print_raw("pxor ");
24639 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24640 st->print_raw(",");
24641 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24642 st->print_raw("\t! xor vectors (4 bytes)");
24643}
24644#endif
24645#ifndef PRODUCT
24646void vxor4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24647 // Start at oper_input_base() and count operands
24648 unsigned idx0 = 1;
24649 unsigned idx1 = 1; // src1
24650 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24651 st->print_raw("vpxor ");
24652 opnd_array(0)->int_format(ra, this, st); // dst
24653 st->print_raw(",");
24654 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24655 st->print_raw(",");
24656 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24657 st->print_raw("\t! xor vectors (4 bytes)");
24658}
24659#endif
24660#ifndef PRODUCT
24661void vxor4B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24662 // Start at oper_input_base() and count operands
24663 unsigned idx0 = 2;
24664 unsigned idx1 = 2; // src
24665 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24666 st->print_raw("vpxor ");
24667 opnd_array(0)->int_format(ra, this, st); // dst
24668 st->print_raw(",");
24669 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24670 st->print_raw(",");
24671 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24672 st->print_raw("\t! xor vectors (4 bytes)");
24673}
24674#endif
24675#ifndef PRODUCT
24676void vxor4B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24677 // Start at oper_input_base() and count operands
24678 unsigned idx0 = 2;
24679 unsigned idx1 = 2; // mem
24680 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24681 st->print_raw("vpxor ");
24682 opnd_array(0)->int_format(ra, this, st); // dst
24683 st->print_raw(",");
24684 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24685 st->print_raw(",");
24686 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24687 st->print_raw("\t! xor vectors (4 bytes)");
24688}
24689#endif
24690#ifndef PRODUCT
24691void vxor8BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24692 // Start at oper_input_base() and count operands
24693 unsigned idx0 = 1;
24694 unsigned idx1 = 1; // dst
24695 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24696 st->print_raw("pxor ");
24697 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24698 st->print_raw(",");
24699 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24700 st->print_raw("\t! xor vectors (8 bytes)");
24701}
24702#endif
24703#ifndef PRODUCT
24704void vxor8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24705 // Start at oper_input_base() and count operands
24706 unsigned idx0 = 1;
24707 unsigned idx1 = 1; // src1
24708 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24709 st->print_raw("vpxor ");
24710 opnd_array(0)->int_format(ra, this, st); // dst
24711 st->print_raw(",");
24712 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24713 st->print_raw(",");
24714 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24715 st->print_raw("\t! xor vectors (8 bytes)");
24716}
24717#endif
24718#ifndef PRODUCT
24719void vxor8B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24720 // Start at oper_input_base() and count operands
24721 unsigned idx0 = 2;
24722 unsigned idx1 = 2; // src
24723 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24724 st->print_raw("vpxor ");
24725 opnd_array(0)->int_format(ra, this, st); // dst
24726 st->print_raw(",");
24727 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24728 st->print_raw(",");
24729 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24730 st->print_raw("\t! xor vectors (8 bytes)");
24731}
24732#endif
24733#ifndef PRODUCT
24734void vxor8B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24735 // Start at oper_input_base() and count operands
24736 unsigned idx0 = 2;
24737 unsigned idx1 = 2; // mem
24738 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24739 st->print_raw("vpxor ");
24740 opnd_array(0)->int_format(ra, this, st); // dst
24741 st->print_raw(",");
24742 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24743 st->print_raw(",");
24744 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24745 st->print_raw("\t! xor vectors (8 bytes)");
24746}
24747#endif
24748#ifndef PRODUCT
24749void vxor16BNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24750 // Start at oper_input_base() and count operands
24751 unsigned idx0 = 1;
24752 unsigned idx1 = 1; // dst
24753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24754 st->print_raw("pxor ");
24755 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
24756 st->print_raw(",");
24757 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24758 st->print_raw("\t! xor vectors (16 bytes)");
24759}
24760#endif
24761#ifndef PRODUCT
24762void vxor16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24763 // Start at oper_input_base() and count operands
24764 unsigned idx0 = 1;
24765 unsigned idx1 = 1; // src1
24766 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24767 st->print_raw("vpxor ");
24768 opnd_array(0)->int_format(ra, this, st); // dst
24769 st->print_raw(",");
24770 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24771 st->print_raw(",");
24772 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24773 st->print_raw("\t! xor vectors (16 bytes)");
24774}
24775#endif
24776#ifndef PRODUCT
24777void vxor16B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24778 // Start at oper_input_base() and count operands
24779 unsigned idx0 = 2;
24780 unsigned idx1 = 2; // src
24781 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24782 st->print_raw("vpxor ");
24783 opnd_array(0)->int_format(ra, this, st); // dst
24784 st->print_raw(",");
24785 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24786 st->print_raw(",");
24787 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24788 st->print_raw("\t! xor vectors (16 bytes)");
24789}
24790#endif
24791#ifndef PRODUCT
24792void vxor16B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24793 // Start at oper_input_base() and count operands
24794 unsigned idx0 = 2;
24795 unsigned idx1 = 2; // mem
24796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24797 st->print_raw("vpxor ");
24798 opnd_array(0)->int_format(ra, this, st); // dst
24799 st->print_raw(",");
24800 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24801 st->print_raw(",");
24802 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24803 st->print_raw("\t! xor vectors (16 bytes)");
24804}
24805#endif
24806#ifndef PRODUCT
24807void vxor32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24808 // Start at oper_input_base() and count operands
24809 unsigned idx0 = 1;
24810 unsigned idx1 = 1; // src1
24811 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24812 st->print_raw("vpxor ");
24813 opnd_array(0)->int_format(ra, this, st); // dst
24814 st->print_raw(",");
24815 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24816 st->print_raw(",");
24817 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24818 st->print_raw("\t! xor vectors (32 bytes)");
24819}
24820#endif
24821#ifndef PRODUCT
24822void vxor32B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24823 // Start at oper_input_base() and count operands
24824 unsigned idx0 = 2;
24825 unsigned idx1 = 2; // src
24826 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24827 st->print_raw("vpxor ");
24828 opnd_array(0)->int_format(ra, this, st); // dst
24829 st->print_raw(",");
24830 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24831 st->print_raw(",");
24832 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24833 st->print_raw("\t! xor vectors (32 bytes)");
24834}
24835#endif
24836#ifndef PRODUCT
24837void vxor32B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24838 // Start at oper_input_base() and count operands
24839 unsigned idx0 = 2;
24840 unsigned idx1 = 2; // mem
24841 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24842 st->print_raw("vpxor ");
24843 opnd_array(0)->int_format(ra, this, st); // dst
24844 st->print_raw(",");
24845 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24846 st->print_raw(",");
24847 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24848 st->print_raw("\t! xor vectors (32 bytes)");
24849}
24850#endif
24851#ifndef PRODUCT
24852void vxor64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24853 // Start at oper_input_base() and count operands
24854 unsigned idx0 = 1;
24855 unsigned idx1 = 1; // src1
24856 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
24857 st->print_raw("vpxor ");
24858 opnd_array(0)->int_format(ra, this, st); // dst
24859 st->print_raw(",");
24860 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
24861 st->print_raw(",");
24862 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
24863 st->print_raw("\t! xor vectors (64 bytes)");
24864}
24865#endif
24866#ifndef PRODUCT
24867void vxor64B_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24868 // Start at oper_input_base() and count operands
24869 unsigned idx0 = 2;
24870 unsigned idx1 = 2; // src
24871 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
24872 st->print_raw("vpxor ");
24873 opnd_array(0)->int_format(ra, this, st); // dst
24874 st->print_raw(",");
24875 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24876 st->print_raw(",");
24877 opnd_array(2)->ext_format(ra, this,idx2, st); // mem
24878 st->print_raw("\t! xor vectors (64 bytes)");
24879}
24880#endif
24881#ifndef PRODUCT
24882void vxor64B_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
24883 // Start at oper_input_base() and count operands
24884 unsigned idx0 = 2;
24885 unsigned idx1 = 2; // mem
24886 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
24887 st->print_raw("vpxor ");
24888 opnd_array(0)->int_format(ra, this, st); // dst
24889 st->print_raw(",");
24890 opnd_array(2)->ext_format(ra, this,idx2, st); // src
24891 st->print_raw(",");
24892 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
24893 st->print_raw("\t! xor vectors (64 bytes)");
24894}
24895#endif
24896#ifndef PRODUCT
24897void vabs4B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24898 // Start at oper_input_base() and count operands
24899 unsigned idx0 = 1;
24900 unsigned idx1 = 1; // src
24901 st->print_raw("pabsb ");
24902 opnd_array(0)->int_format(ra, this, st); // dst
24903 st->print_raw(",");
24904 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24905 st->print_raw("\t# ");
24906 opnd_array(0)->int_format(ra, this, st); // dst
24907 st->print_raw(" = |");
24908 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24909 st->print_raw("| abs packed4B");
24910}
24911#endif
24912#ifndef PRODUCT
24913void vabs8B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24914 // Start at oper_input_base() and count operands
24915 unsigned idx0 = 1;
24916 unsigned idx1 = 1; // src
24917 st->print_raw("pabsb ");
24918 opnd_array(0)->int_format(ra, this, st); // dst
24919 st->print_raw(",");
24920 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24921 st->print_raw("\t# ");
24922 opnd_array(0)->int_format(ra, this, st); // dst
24923 st->print_raw(" = |");
24924 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24925 st->print_raw("| abs packed8B");
24926}
24927#endif
24928#ifndef PRODUCT
24929void vabs16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24930 // Start at oper_input_base() and count operands
24931 unsigned idx0 = 1;
24932 unsigned idx1 = 1; // src
24933 st->print_raw("pabsb ");
24934 opnd_array(0)->int_format(ra, this, st); // dst
24935 st->print_raw(",");
24936 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24937 st->print_raw("\t# ");
24938 opnd_array(0)->int_format(ra, this, st); // dst
24939 st->print_raw(" = |");
24940 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24941 st->print_raw("| abs packed16B");
24942}
24943#endif
24944#ifndef PRODUCT
24945void vabs32B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24946 // Start at oper_input_base() and count operands
24947 unsigned idx0 = 1;
24948 unsigned idx1 = 1; // src
24949 st->print_raw("vpabsb ");
24950 opnd_array(0)->int_format(ra, this, st); // dst
24951 st->print_raw(",");
24952 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24953 st->print_raw("\t# ");
24954 opnd_array(0)->int_format(ra, this, st); // dst
24955 st->print_raw(" = |");
24956 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24957 st->print_raw("| abs packed32B");
24958}
24959#endif
24960#ifndef PRODUCT
24961void vabs64B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24962 // Start at oper_input_base() and count operands
24963 unsigned idx0 = 1;
24964 unsigned idx1 = 1; // src
24965 st->print_raw("vpabsb ");
24966 opnd_array(0)->int_format(ra, this, st); // dst
24967 st->print_raw(",");
24968 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24969 st->print_raw("\t# ");
24970 opnd_array(0)->int_format(ra, this, st); // dst
24971 st->print_raw(" = |");
24972 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24973 st->print_raw("| abs packed64B");
24974}
24975#endif
24976#ifndef PRODUCT
24977void vabs2S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24978 // Start at oper_input_base() and count operands
24979 unsigned idx0 = 1;
24980 unsigned idx1 = 1; // src
24981 st->print_raw("pabsw ");
24982 opnd_array(0)->int_format(ra, this, st); // dst
24983 st->print_raw(",");
24984 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24985 st->print_raw("\t# ");
24986 opnd_array(0)->int_format(ra, this, st); // dst
24987 st->print_raw(" = |");
24988 opnd_array(1)->ext_format(ra, this,idx1, st); // src
24989 st->print_raw("| abs packed2S");
24990}
24991#endif
24992#ifndef PRODUCT
24993void vabs4S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
24994 // Start at oper_input_base() and count operands
24995 unsigned idx0 = 1;
24996 unsigned idx1 = 1; // src
24997 st->print_raw("pabsw ");
24998 opnd_array(0)->int_format(ra, this, st); // dst
24999 st->print_raw(",");
25000 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25001 st->print_raw("\t# ");
25002 opnd_array(0)->int_format(ra, this, st); // dst
25003 st->print_raw(" = |");
25004 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25005 st->print_raw("| abs packed4S");
25006}
25007#endif
25008#ifndef PRODUCT
25009void vabs8S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25010 // Start at oper_input_base() and count operands
25011 unsigned idx0 = 1;
25012 unsigned idx1 = 1; // src
25013 st->print_raw("pabsw ");
25014 opnd_array(0)->int_format(ra, this, st); // dst
25015 st->print_raw(",");
25016 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25017 st->print_raw("\t# ");
25018 opnd_array(0)->int_format(ra, this, st); // dst
25019 st->print_raw(" = |");
25020 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25021 st->print_raw("| abs packed8S");
25022}
25023#endif
25024#ifndef PRODUCT
25025void vabs16S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25026 // Start at oper_input_base() and count operands
25027 unsigned idx0 = 1;
25028 unsigned idx1 = 1; // src
25029 st->print_raw("vpabsw ");
25030 opnd_array(0)->int_format(ra, this, st); // dst
25031 st->print_raw(",");
25032 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25033 st->print_raw("\t# ");
25034 opnd_array(0)->int_format(ra, this, st); // dst
25035 st->print_raw(" = |");
25036 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25037 st->print_raw("| abs packed16S");
25038}
25039#endif
25040#ifndef PRODUCT
25041void vabs32S_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25042 // Start at oper_input_base() and count operands
25043 unsigned idx0 = 1;
25044 unsigned idx1 = 1; // src
25045 st->print_raw("vpabsw ");
25046 opnd_array(0)->int_format(ra, this, st); // dst
25047 st->print_raw(",");
25048 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25049 st->print_raw("\t# ");
25050 opnd_array(0)->int_format(ra, this, st); // dst
25051 st->print_raw(" = |");
25052 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25053 st->print_raw("| abs packed32S");
25054}
25055#endif
25056#ifndef PRODUCT
25057void vabs2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25058 // Start at oper_input_base() and count operands
25059 unsigned idx0 = 1;
25060 unsigned idx1 = 1; // src
25061 st->print_raw("pabsd ");
25062 opnd_array(0)->int_format(ra, this, st); // dst
25063 st->print_raw(",");
25064 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25065 st->print_raw("\t# ");
25066 opnd_array(0)->int_format(ra, this, st); // dst
25067 st->print_raw(" = |");
25068 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25069 st->print_raw("| abs packed2I");
25070}
25071#endif
25072#ifndef PRODUCT
25073void vabs4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25074 // Start at oper_input_base() and count operands
25075 unsigned idx0 = 1;
25076 unsigned idx1 = 1; // src
25077 st->print_raw("pabsd ");
25078 opnd_array(0)->int_format(ra, this, st); // dst
25079 st->print_raw(",");
25080 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25081 st->print_raw("\t# ");
25082 opnd_array(0)->int_format(ra, this, st); // dst
25083 st->print_raw(" = |");
25084 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25085 st->print_raw("| abs packed4I");
25086}
25087#endif
25088#ifndef PRODUCT
25089void vabs8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25090 // Start at oper_input_base() and count operands
25091 unsigned idx0 = 1;
25092 unsigned idx1 = 1; // src
25093 st->print_raw("vpabsd ");
25094 opnd_array(0)->int_format(ra, this, st); // dst
25095 st->print_raw(",");
25096 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25097 st->print_raw("\t# ");
25098 opnd_array(0)->int_format(ra, this, st); // dst
25099 st->print_raw(" = |");
25100 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25101 st->print_raw("| abs packed8I");
25102}
25103#endif
25104#ifndef PRODUCT
25105void vabs16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25106 // Start at oper_input_base() and count operands
25107 unsigned idx0 = 1;
25108 unsigned idx1 = 1; // src
25109 st->print_raw("vpabsd ");
25110 opnd_array(0)->int_format(ra, this, st); // dst
25111 st->print_raw(",");
25112 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25113 st->print_raw("\t# ");
25114 opnd_array(0)->int_format(ra, this, st); // dst
25115 st->print_raw(" = |");
25116 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25117 st->print_raw("| abs packed16I");
25118}
25119#endif
25120#ifndef PRODUCT
25121void vabs2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25122 // Start at oper_input_base() and count operands
25123 unsigned idx0 = 1;
25124 unsigned idx1 = 1; // src
25125 st->print_raw("evpabsq ");
25126 opnd_array(0)->int_format(ra, this, st); // dst
25127 st->print_raw(",");
25128 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25129 st->print_raw("\t# ");
25130 opnd_array(0)->int_format(ra, this, st); // dst
25131 st->print_raw(" = |");
25132 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25133 st->print_raw("| abs packed2L");
25134}
25135#endif
25136#ifndef PRODUCT
25137void vabs4L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25138 // Start at oper_input_base() and count operands
25139 unsigned idx0 = 1;
25140 unsigned idx1 = 1; // src
25141 st->print_raw("evpabsq ");
25142 opnd_array(0)->int_format(ra, this, st); // dst
25143 st->print_raw(",");
25144 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25145 st->print_raw("\t# ");
25146 opnd_array(0)->int_format(ra, this, st); // dst
25147 st->print_raw(" = |");
25148 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25149 st->print_raw("| abs packed4L");
25150}
25151#endif
25152#ifndef PRODUCT
25153void vabs8L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25154 // Start at oper_input_base() and count operands
25155 unsigned idx0 = 1;
25156 unsigned idx1 = 1; // src
25157 st->print_raw("evpabsq ");
25158 opnd_array(0)->int_format(ra, this, st); // dst
25159 st->print_raw(",");
25160 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25161 st->print_raw("\t# ");
25162 opnd_array(0)->int_format(ra, this, st); // dst
25163 st->print_raw(" = |");
25164 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25165 st->print_raw("| abs packed8L");
25166}
25167#endif
25168#ifndef PRODUCT
25169void vabsneg2DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25170 // Start at oper_input_base() and count operands
25171 unsigned idx0 = 1;
25172 unsigned idx1 = 1; // src
25173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25174 st->print_raw("vabsnegd ");
25175 opnd_array(0)->int_format(ra, this, st); // dst
25176 st->print_raw(",");
25177 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25178 st->print_raw(",[mask]\t# absneg packed2D");
25179}
25180#endif
25181#ifndef PRODUCT
25182void vabsneg2D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25183 // Start at oper_input_base() and count operands
25184 unsigned idx0 = 1;
25185 unsigned idx1 = 1; // src
25186 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25187 st->print_raw("vabsnegd ");
25188 opnd_array(0)->int_format(ra, this, st); // dst
25189 st->print_raw(",");
25190 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25191 st->print_raw(",[mask]\t# absneg packed2D");
25192}
25193#endif
25194#ifndef PRODUCT
25195void vabsneg4DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25196 // Start at oper_input_base() and count operands
25197 unsigned idx0 = 1;
25198 unsigned idx1 = 1; // src
25199 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25200 st->print_raw("vabsnegd ");
25201 opnd_array(0)->int_format(ra, this, st); // dst
25202 st->print_raw(",");
25203 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25204 st->print_raw(",[mask]\t# absneg packed4D");
25205}
25206#endif
25207#ifndef PRODUCT
25208void vabsneg4D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25209 // Start at oper_input_base() and count operands
25210 unsigned idx0 = 1;
25211 unsigned idx1 = 1; // src
25212 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25213 st->print_raw("vabsnegd ");
25214 opnd_array(0)->int_format(ra, this, st); // dst
25215 st->print_raw(",");
25216 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25217 st->print_raw(",[mask]\t# absneg packed4D");
25218}
25219#endif
25220#ifndef PRODUCT
25221void vabsneg8DNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25222 // Start at oper_input_base() and count operands
25223 unsigned idx0 = 1;
25224 unsigned idx1 = 1; // src
25225 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25226 st->print_raw("vabsnegd ");
25227 opnd_array(0)->int_format(ra, this, st); // dst
25228 st->print_raw(",");
25229 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25230 st->print_raw(",[mask]\t# absneg packed8D");
25231}
25232#endif
25233#ifndef PRODUCT
25234void vabsneg8D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25235 // Start at oper_input_base() and count operands
25236 unsigned idx0 = 1;
25237 unsigned idx1 = 1; // src
25238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25239 st->print_raw("vabsnegd ");
25240 opnd_array(0)->int_format(ra, this, st); // dst
25241 st->print_raw(",");
25242 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25243 st->print_raw(",[mask]\t# absneg packed8D");
25244}
25245#endif
25246#ifndef PRODUCT
25247void vabsneg2FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25248 // Start at oper_input_base() and count operands
25249 unsigned idx0 = 1;
25250 unsigned idx1 = 1; // src
25251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25252 st->print_raw("vabsnegf ");
25253 opnd_array(0)->int_format(ra, this, st); // dst
25254 st->print_raw(",");
25255 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25256 st->print_raw(",[mask]\t# absneg packed2F");
25257}
25258#endif
25259#ifndef PRODUCT
25260void vabsneg2F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25261 // Start at oper_input_base() and count operands
25262 unsigned idx0 = 1;
25263 unsigned idx1 = 1; // src
25264 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25265 st->print_raw("vabsnegf ");
25266 opnd_array(0)->int_format(ra, this, st); // dst
25267 st->print_raw(",");
25268 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25269 st->print_raw(",[mask]\t# absneg packed2F");
25270}
25271#endif
25272#ifndef PRODUCT
25273void vabsneg4FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25274 // Start at oper_input_base() and count operands
25275 unsigned idx0 = 1;
25276 unsigned idx1 = 1; // dst
25277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25278 st->print_raw("vabsnegf ");
25279 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25280 st->print_raw(",[mask]\t# absneg packed4F");
25281}
25282#endif
25283#ifndef PRODUCT
25284void vabsneg4F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25285 // Start at oper_input_base() and count operands
25286 unsigned idx0 = 1;
25287 unsigned idx1 = 1; // dst
25288 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25289 st->print_raw("vabsnegf ");
25290 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25291 st->print_raw(",[mask]\t# absneg packed4F");
25292}
25293#endif
25294#ifndef PRODUCT
25295void vabsneg8FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25296 // Start at oper_input_base() and count operands
25297 unsigned idx0 = 1;
25298 unsigned idx1 = 1; // src
25299 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25300 st->print_raw("vabsnegf ");
25301 opnd_array(0)->int_format(ra, this, st); // dst
25302 st->print_raw(",");
25303 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25304 st->print_raw(",[mask]\t# absneg packed8F");
25305}
25306#endif
25307#ifndef PRODUCT
25308void vabsneg8F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25309 // Start at oper_input_base() and count operands
25310 unsigned idx0 = 1;
25311 unsigned idx1 = 1; // src
25312 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25313 st->print_raw("vabsnegf ");
25314 opnd_array(0)->int_format(ra, this, st); // dst
25315 st->print_raw(",");
25316 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25317 st->print_raw(",[mask]\t# absneg packed8F");
25318}
25319#endif
25320#ifndef PRODUCT
25321void vabsneg16FNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25322 // Start at oper_input_base() and count operands
25323 unsigned idx0 = 1;
25324 unsigned idx1 = 1; // src
25325 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25326 st->print_raw("vabsnegf ");
25327 opnd_array(0)->int_format(ra, this, st); // dst
25328 st->print_raw(",");
25329 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25330 st->print_raw(",[mask]\t# absneg packed16F");
25331}
25332#endif
25333#ifndef PRODUCT
25334void vabsneg16F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25335 // Start at oper_input_base() and count operands
25336 unsigned idx0 = 1;
25337 unsigned idx1 = 1; // src
25338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
25339 st->print_raw("vabsnegf ");
25340 opnd_array(0)->int_format(ra, this, st); // dst
25341 st->print_raw(",");
25342 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25343 st->print_raw(",[mask]\t# absneg packed16F");
25344}
25345#endif
25346#ifndef PRODUCT
25347void vfma2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25348 // Start at oper_input_base() and count operands
25349 unsigned idx0 = 1;
25350 unsigned idx1 = 1; // c
25351 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25352 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25353 st->print_raw("fmapd ");
25354 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25355 st->print_raw(",");
25356 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25357 st->print_raw(",");
25358 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25359 st->print_raw("\t# ");
25360 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25361 st->print_raw(" = ");
25362 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25363 st->print_raw(" * ");
25364 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25365 st->print_raw(" + ");
25366 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25367 st->print_raw(" fma packed2D");
25368}
25369#endif
25370#ifndef PRODUCT
25371void vfma2D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25372 // Start at oper_input_base() and count operands
25373 unsigned idx0 = 2;
25374 unsigned idx1 = 2; // c
25375 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25376 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25377 st->print_raw("fmapd ");
25378 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25379 st->print_raw(",");
25380 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25381 st->print_raw(",");
25382 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25383 st->print_raw("\t# ");
25384 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25385 st->print_raw(" = ");
25386 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25387 st->print_raw(" * ");
25388 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25389 st->print_raw(" + ");
25390 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25391 st->print_raw(" fma packed2D");
25392}
25393#endif
25394#ifndef PRODUCT
25395void vfma4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25396 // Start at oper_input_base() and count operands
25397 unsigned idx0 = 1;
25398 unsigned idx1 = 1; // c
25399 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25400 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25401 st->print_raw("fmapd ");
25402 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25403 st->print_raw(",");
25404 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25405 st->print_raw(",");
25406 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25407 st->print_raw("\t# ");
25408 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25409 st->print_raw(" = ");
25410 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25411 st->print_raw(" * ");
25412 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25413 st->print_raw(" + ");
25414 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25415 st->print_raw(" fma packed4D");
25416}
25417#endif
25418#ifndef PRODUCT
25419void vfma4D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25420 // Start at oper_input_base() and count operands
25421 unsigned idx0 = 2;
25422 unsigned idx1 = 2; // c
25423 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25424 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25425 st->print_raw("fmapd ");
25426 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25427 st->print_raw(",");
25428 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25429 st->print_raw(",");
25430 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25431 st->print_raw("\t# ");
25432 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25433 st->print_raw(" = ");
25434 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25435 st->print_raw(" * ");
25436 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25437 st->print_raw(" + ");
25438 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25439 st->print_raw(" fma packed4D");
25440}
25441#endif
25442#ifndef PRODUCT
25443void vfma8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25444 // Start at oper_input_base() and count operands
25445 unsigned idx0 = 1;
25446 unsigned idx1 = 1; // c
25447 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25448 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25449 st->print_raw("fmapd ");
25450 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25451 st->print_raw(",");
25452 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25453 st->print_raw(",");
25454 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25455 st->print_raw("\t# ");
25456 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25457 st->print_raw(" = ");
25458 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25459 st->print_raw(" * ");
25460 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25461 st->print_raw(" + ");
25462 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25463 st->print_raw(" fma packed8D");
25464}
25465#endif
25466#ifndef PRODUCT
25467void vfma8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25468 // Start at oper_input_base() and count operands
25469 unsigned idx0 = 2;
25470 unsigned idx1 = 2; // c
25471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25472 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25473 st->print_raw("fmapd ");
25474 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25475 st->print_raw(",");
25476 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25477 st->print_raw(",");
25478 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25479 st->print_raw("\t# ");
25480 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25481 st->print_raw(" = ");
25482 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25483 st->print_raw(" * ");
25484 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25485 st->print_raw(" + ");
25486 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25487 st->print_raw(" fma packed8D");
25488}
25489#endif
25490#ifndef PRODUCT
25491void vfma4F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25492 // Start at oper_input_base() and count operands
25493 unsigned idx0 = 1;
25494 unsigned idx1 = 1; // c
25495 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25496 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25497 st->print_raw("fmaps ");
25498 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25499 st->print_raw(",");
25500 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25501 st->print_raw(",");
25502 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25503 st->print_raw("\t# ");
25504 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25505 st->print_raw(" = ");
25506 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25507 st->print_raw(" * ");
25508 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25509 st->print_raw(" + ");
25510 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25511 st->print_raw(" fma packed4F");
25512}
25513#endif
25514#ifndef PRODUCT
25515void vfma4F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25516 // Start at oper_input_base() and count operands
25517 unsigned idx0 = 2;
25518 unsigned idx1 = 2; // c
25519 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25520 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25521 st->print_raw("fmaps ");
25522 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25523 st->print_raw(",");
25524 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25525 st->print_raw(",");
25526 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25527 st->print_raw("\t# ");
25528 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25529 st->print_raw(" = ");
25530 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25531 st->print_raw(" * ");
25532 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25533 st->print_raw(" + ");
25534 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25535 st->print_raw(" fma packed4F");
25536}
25537#endif
25538#ifndef PRODUCT
25539void vfma8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25540 // Start at oper_input_base() and count operands
25541 unsigned idx0 = 1;
25542 unsigned idx1 = 1; // c
25543 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25544 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25545 st->print_raw("fmaps ");
25546 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25547 st->print_raw(",");
25548 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25549 st->print_raw(",");
25550 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25551 st->print_raw("\t# ");
25552 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25553 st->print_raw(" = ");
25554 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25555 st->print_raw(" * ");
25556 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25557 st->print_raw(" + ");
25558 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25559 st->print_raw(" fma packed8F");
25560}
25561#endif
25562#ifndef PRODUCT
25563void vfma8F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25564 // Start at oper_input_base() and count operands
25565 unsigned idx0 = 2;
25566 unsigned idx1 = 2; // c
25567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25568 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25569 st->print_raw("fmaps ");
25570 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25571 st->print_raw(",");
25572 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25573 st->print_raw(",");
25574 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25575 st->print_raw("\t# ");
25576 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25577 st->print_raw(" = ");
25578 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25579 st->print_raw(" * ");
25580 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25581 st->print_raw(" + ");
25582 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25583 st->print_raw(" fma packed8F");
25584}
25585#endif
25586#ifndef PRODUCT
25587void vfma16F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25588 // Start at oper_input_base() and count operands
25589 unsigned idx0 = 1;
25590 unsigned idx1 = 1; // c
25591 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25592 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25593 st->print_raw("fmaps ");
25594 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25595 st->print_raw(",");
25596 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25597 st->print_raw(",");
25598 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25599 st->print_raw("\t# ");
25600 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25601 st->print_raw(" = ");
25602 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25603 st->print_raw(" * ");
25604 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25605 st->print_raw(" + ");
25606 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25607 st->print_raw(" fma packed16F");
25608}
25609#endif
25610#ifndef PRODUCT
25611void vfma16F_memNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25612 // Start at oper_input_base() and count operands
25613 unsigned idx0 = 2;
25614 unsigned idx1 = 2; // c
25615 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
25616 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
25617 st->print_raw("fmaps ");
25618 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25619 st->print_raw(",");
25620 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25621 st->print_raw(",");
25622 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25623 st->print_raw("\t# ");
25624 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25625 st->print_raw(" = ");
25626 opnd_array(2)->ext_format(ra, this,idx2, st); // a
25627 st->print_raw(" * ");
25628 opnd_array(3)->ext_format(ra, this,idx3, st); // b
25629 st->print_raw(" + ");
25630 opnd_array(1)->ext_format(ra, this,idx1, st); // c
25631 st->print_raw(" fma packed16F");
25632}
25633#endif
25634#ifndef PRODUCT
25635void smuladd4S2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25636 // Start at oper_input_base() and count operands
25637 unsigned idx0 = 1;
25638 unsigned idx1 = 1; // dst
25639 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25640 st->print_raw("pmaddwd ");
25641 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25642 st->print_raw(",");
25643 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25644 st->print_raw(",");
25645 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25646 st->print_raw("\t! muladd packed4Sto2I");
25647}
25648#endif
25649#ifndef PRODUCT
25650void vmuladd4S2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25651 // Start at oper_input_base() and count operands
25652 unsigned idx0 = 1;
25653 unsigned idx1 = 1; // src1
25654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25655 st->print_raw("vpmaddwd ");
25656 opnd_array(0)->int_format(ra, this, st); // dst
25657 st->print_raw(",");
25658 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25659 st->print_raw(",");
25660 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25661 st->print_raw("\t! muladd packed4Sto2I");
25662}
25663#endif
25664#ifndef PRODUCT
25665void smuladd8S4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25666 // Start at oper_input_base() and count operands
25667 unsigned idx0 = 1;
25668 unsigned idx1 = 1; // dst
25669 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25670 st->print_raw("pmaddwd ");
25671 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25672 st->print_raw(",");
25673 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25674 st->print_raw(",");
25675 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25676 st->print_raw("\t! muladd packed8Sto4I");
25677}
25678#endif
25679#ifndef PRODUCT
25680void vmuladd8S4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25681 // Start at oper_input_base() and count operands
25682 unsigned idx0 = 1;
25683 unsigned idx1 = 1; // src1
25684 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25685 st->print_raw("vpmaddwd ");
25686 opnd_array(0)->int_format(ra, this, st); // dst
25687 st->print_raw(",");
25688 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25689 st->print_raw(",");
25690 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25691 st->print_raw("\t! muladd packed8Sto4I");
25692}
25693#endif
25694#ifndef PRODUCT
25695void vmuladd16S8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25696 // Start at oper_input_base() and count operands
25697 unsigned idx0 = 1;
25698 unsigned idx1 = 1; // src1
25699 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25700 st->print_raw("vpmaddwd ");
25701 opnd_array(0)->int_format(ra, this, st); // dst
25702 st->print_raw(",");
25703 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25704 st->print_raw(",");
25705 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25706 st->print_raw("\t! muladd packed16Sto8I");
25707}
25708#endif
25709#ifndef PRODUCT
25710void vmuladd32S16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25711 // Start at oper_input_base() and count operands
25712 unsigned idx0 = 1;
25713 unsigned idx1 = 1; // src1
25714 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25715 st->print_raw("vpmaddwd ");
25716 opnd_array(0)->int_format(ra, this, st); // dst
25717 st->print_raw(",");
25718 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25719 st->print_raw(",");
25720 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25721 st->print_raw("\t! muladd packed32Sto16I");
25722}
25723#endif
25724#ifndef PRODUCT
25725void vmuladdadd4S2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25726 // Start at oper_input_base() and count operands
25727 unsigned idx0 = 1;
25728 unsigned idx1 = 1; // src1
25729 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25730 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
25731 st->print_raw("evpdpwssd ");
25732 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
25733 st->print_raw(",");
25734 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25735 st->print_raw(",");
25736 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25737 st->print_raw("\t! muladdadd packed4Sto2I");
25738}
25739#endif
25740#ifndef PRODUCT
25741void vmuladdadd4S2I_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25742 // Start at oper_input_base() and count operands
25743 unsigned idx0 = 1;
25744 unsigned idx1 = 1; // dst
25745 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25746 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25747 st->print_raw("evpdpwssd ");
25748 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25749 st->print_raw(",");
25750 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25751 st->print_raw(",");
25752 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
25753 st->print_raw("\t! muladdadd packed4Sto2I");
25754}
25755#endif
25756#ifndef PRODUCT
25757void vmuladdadd8S4I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25758 // Start at oper_input_base() and count operands
25759 unsigned idx0 = 1;
25760 unsigned idx1 = 1; // src1
25761 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25762 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
25763 st->print_raw("evpdpwssd ");
25764 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
25765 st->print_raw(",");
25766 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25767 st->print_raw(",");
25768 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25769 st->print_raw("\t! muladdadd packed8Sto4I");
25770}
25771#endif
25772#ifndef PRODUCT
25773void vmuladdadd8S4I_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25774 // Start at oper_input_base() and count operands
25775 unsigned idx0 = 1;
25776 unsigned idx1 = 1; // dst
25777 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25778 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25779 st->print_raw("evpdpwssd ");
25780 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25781 st->print_raw(",");
25782 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25783 st->print_raw(",");
25784 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
25785 st->print_raw("\t! muladdadd packed8Sto4I");
25786}
25787#endif
25788#ifndef PRODUCT
25789void vmuladdadd16S8I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25790 // Start at oper_input_base() and count operands
25791 unsigned idx0 = 1;
25792 unsigned idx1 = 1; // src1
25793 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25794 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
25795 st->print_raw("evpdpwssd ");
25796 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
25797 st->print_raw(",");
25798 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25799 st->print_raw(",");
25800 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25801 st->print_raw("\t! muladdadd packed16Sto8I");
25802}
25803#endif
25804#ifndef PRODUCT
25805void vmuladdadd16S8I_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25806 // Start at oper_input_base() and count operands
25807 unsigned idx0 = 1;
25808 unsigned idx1 = 1; // dst
25809 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25810 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25811 st->print_raw("evpdpwssd ");
25812 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25813 st->print_raw(",");
25814 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25815 st->print_raw(",");
25816 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
25817 st->print_raw("\t! muladdadd packed16Sto8I");
25818}
25819#endif
25820#ifndef PRODUCT
25821void vmuladdadd32S16I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25822 // Start at oper_input_base() and count operands
25823 unsigned idx0 = 1;
25824 unsigned idx1 = 1; // src1
25825 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
25826 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
25827 st->print_raw("evpdpwssd ");
25828 opnd_array(3)->ext_format(ra, this,idx3, st); // dst
25829 st->print_raw(",");
25830 opnd_array(1)->ext_format(ra, this,idx1, st); // src1
25831 st->print_raw(",");
25832 opnd_array(2)->ext_format(ra, this,idx2, st); // src2
25833 st->print_raw("\t! muladdadd packed32Sto16I");
25834}
25835#endif
25836#ifndef PRODUCT
25837void vmuladdadd32S16I_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25838 // Start at oper_input_base() and count operands
25839 unsigned idx0 = 1;
25840 unsigned idx1 = 1; // dst
25841 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25842 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25843 st->print_raw("evpdpwssd ");
25844 opnd_array(1)->ext_format(ra, this,idx1, st); // dst
25845 st->print_raw(",");
25846 opnd_array(2)->ext_format(ra, this,idx2, st); // src1
25847 st->print_raw(",");
25848 opnd_array(3)->ext_format(ra, this,idx3, st); // src2
25849 st->print_raw("\t! muladdadd packed32Sto16I");
25850}
25851#endif
25852#ifndef PRODUCT
25853void vpopcount2INode::format(PhaseRegAlloc *ra, outputStream *st) const {
25854 // Start at oper_input_base() and count operands
25855 unsigned idx0 = 1;
25856 unsigned idx1 = 1; // src
25857 st->print_raw("vpopcntd ");
25858 opnd_array(0)->int_format(ra, this, st); // dst
25859 st->print_raw(",");
25860 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25861 st->print_raw("\t! vector popcount packed2I");
25862}
25863#endif
25864#ifndef PRODUCT
25865void vpopcount4INode::format(PhaseRegAlloc *ra, outputStream *st) const {
25866 // Start at oper_input_base() and count operands
25867 unsigned idx0 = 1;
25868 unsigned idx1 = 1; // src
25869 st->print_raw("vpopcntd ");
25870 opnd_array(0)->int_format(ra, this, st); // dst
25871 st->print_raw(",");
25872 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25873 st->print_raw("\t! vector popcount packed4I");
25874}
25875#endif
25876#ifndef PRODUCT
25877void vpopcount8INode::format(PhaseRegAlloc *ra, outputStream *st) const {
25878 // Start at oper_input_base() and count operands
25879 unsigned idx0 = 1;
25880 unsigned idx1 = 1; // src
25881 st->print_raw("vpopcntd ");
25882 opnd_array(0)->int_format(ra, this, st); // dst
25883 st->print_raw(",");
25884 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25885 st->print_raw("\t! vector popcount packed8I");
25886}
25887#endif
25888#ifndef PRODUCT
25889void vpopcount16INode::format(PhaseRegAlloc *ra, outputStream *st) const {
25890 // Start at oper_input_base() and count operands
25891 unsigned idx0 = 1;
25892 unsigned idx1 = 1; // src
25893 st->print_raw("vpopcntd ");
25894 opnd_array(0)->int_format(ra, this, st); // dst
25895 st->print_raw(",");
25896 opnd_array(1)->ext_format(ra, this,idx1, st); // src
25897 st->print_raw("\t! vector popcount packed16I");
25898}
25899#endif
25900#ifndef PRODUCT
25901void compareAndSwapP_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25902 // Start at oper_input_base() and count operands
25903 unsigned idx0 = 2;
25904 unsigned idx1 = 2; // mem_ptr
25905 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25906 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25907 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25908 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25909 st->print_raw("shenandoah_cas_oop ");
25910 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25911 st->print_raw(",");
25912 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25913}
25914#endif
25915#ifndef PRODUCT
25916void compareAndSwapP_shenandoah_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25917 // Start at oper_input_base() and count operands
25918 unsigned idx0 = 2;
25919 unsigned idx1 = 2; // mem_ptr
25920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25921 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25922 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25923 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25924 st->print_raw("shenandoah_cas_oop ");
25925 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25926 st->print_raw(",");
25927 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25928}
25929#endif
25930#ifndef PRODUCT
25931void compareAndSwapN_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25932 // Start at oper_input_base() and count operands
25933 unsigned idx0 = 2;
25934 unsigned idx1 = 2; // mem_ptr
25935 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25936 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25937 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25938 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25939 st->print_raw("shenandoah_cas_oop ");
25940 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25941 st->print_raw(",");
25942 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25943}
25944#endif
25945#ifndef PRODUCT
25946void compareAndSwapN_shenandoah_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
25947 // Start at oper_input_base() and count operands
25948 unsigned idx0 = 2;
25949 unsigned idx1 = 2; // mem_ptr
25950 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25951 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25952 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25953 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25954 st->print_raw("shenandoah_cas_oop ");
25955 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25956 st->print_raw(",");
25957 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25958}
25959#endif
25960#ifndef PRODUCT
25961void compareAndExchangeN_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25962 // Start at oper_input_base() and count operands
25963 unsigned idx0 = 2;
25964 unsigned idx1 = 2; // mem_ptr
25965 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25966 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25967 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25968 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25969 st->print_raw("shenandoah_cas_oop ");
25970 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25971 st->print_raw(",");
25972 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25973}
25974#endif
25975#ifndef PRODUCT
25976void compareAndExchangeP_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25977 // Start at oper_input_base() and count operands
25978 unsigned idx0 = 2;
25979 unsigned idx1 = 2; // mem_ptr
25980 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
25981 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
25982 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
25983 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
25984 st->print_raw("shenandoah_cas_oop ");
25985 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
25986 st->print_raw(",");
25987 opnd_array(3)->ext_format(ra, this,idx3, st); // newval
25988}
25989#endif
25990#ifndef PRODUCT
25991void zLoadBarrierSlowRegXmmAndYmmNode::format(PhaseRegAlloc *ra, outputStream *st) const {
25992 // Start at oper_input_base() and count operands
25993 unsigned idx0 = 1;
25994 unsigned idx1 = 1; // src
25995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
25996 st->print_raw("lea ");
25997 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
25998 st->print_raw(", ");
25999 opnd_array(1)->ext_format(ra, this,idx1, st); // src
26000 st->print_raw("\n\t");
26001 st->print_raw("call #ZLoadBarrierSlowPath");
26002}
26003#endif
26004#ifndef PRODUCT
26005void zLoadBarrierSlowRegZmmNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26006 // Start at oper_input_base() and count operands
26007 unsigned idx0 = 1;
26008 unsigned idx1 = 1; // src
26009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26010 st->print_raw("lea ");
26011 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
26012 st->print_raw(", ");
26013 opnd_array(1)->ext_format(ra, this,idx1, st); // src
26014 st->print_raw("\n\t");
26015 st->print_raw("call #ZLoadBarrierSlowPath");
26016}
26017#endif
26018#ifndef PRODUCT
26019void zLoadBarrierWeakSlowRegXmmAndYmmNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26020 // Start at oper_input_base() and count operands
26021 unsigned idx0 = 1;
26022 unsigned idx1 = 1; // src
26023 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26024 st->print_raw("lea ");
26025 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
26026 st->print_raw(", ");
26027 opnd_array(1)->ext_format(ra, this,idx1, st); // src
26028 st->print_raw("\n\t");
26029 st->print_raw("call #ZLoadBarrierSlowPath");
26030}
26031#endif
26032#ifndef PRODUCT
26033void zLoadBarrierWeakSlowRegZmmNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26034 // Start at oper_input_base() and count operands
26035 unsigned idx0 = 1;
26036 unsigned idx1 = 1; // src
26037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26038 st->print_raw("lea ");
26039 opnd_array(2)->ext_format(ra, this,idx2, st); // dst
26040 st->print_raw(", ");
26041 opnd_array(1)->ext_format(ra, this,idx1, st); // src
26042 st->print_raw("\n\t");
26043 st->print_raw("call #ZLoadBarrierSlowPath");
26044}
26045#endif
26046#ifndef PRODUCT
26047void z_compareAndExchangePNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26048 // Start at oper_input_base() and count operands
26049 unsigned idx0 = 2;
26050 unsigned idx1 = 2; // mem_ptr
26051 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
26052 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
26053 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
26054 st->print_raw("cmpxchgq ");
26055 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26056 st->print_raw(",");
26057 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26058 st->print_raw("\t# ");
26059 st->print_raw("If rax == ");
26060 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26061 st->print_raw(" then store ");
26062 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26063 st->print_raw(" into ");
26064 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26065 st->print_raw("\n\t");
26066}
26067#endif
26068#ifndef PRODUCT
26069void z_compareAndSwapPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26070 // Start at oper_input_base() and count operands
26071 unsigned idx0 = 2;
26072 unsigned idx1 = 2; // mem_ptr
26073 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
26074 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
26075 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
26076 st->print_raw("cmpxchgq ");
26077 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26078 st->print_raw(",");
26079 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26080 st->print_raw("\t# ");
26081 st->print_raw("If rax == ");
26082 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26083 st->print_raw(" then store ");
26084 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26085 st->print_raw(" into ");
26086 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26087 st->print_raw("\n\t");
26088 st->print_raw("sete ");
26089 opnd_array(0)->int_format(ra, this, st); // res
26090 st->print_raw("\n\t");
26091 st->print_raw("movzbl ");
26092 opnd_array(0)->int_format(ra, this, st); // res
26093 st->print_raw(", ");
26094 opnd_array(0)->int_format(ra, this, st); // res
26095}
26096#endif
26097#ifndef PRODUCT
26098void z_compareAndSwapP_0Node::format(PhaseRegAlloc *ra, outputStream *st) const {
26099 // Start at oper_input_base() and count operands
26100 unsigned idx0 = 2;
26101 unsigned idx1 = 2; // mem_ptr
26102 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // keepalive
26103 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // oldval
26104 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // newval
26105 st->print_raw("cmpxchgq ");
26106 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26107 st->print_raw(",");
26108 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26109 st->print_raw("\t# ");
26110 st->print_raw("If rax == ");
26111 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26112 st->print_raw(" then store ");
26113 opnd_array(4)->ext_format(ra, this,idx4, st); // newval
26114 st->print_raw(" into ");
26115 opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr
26116 st->print_raw("\n\t");
26117 st->print_raw("sete ");
26118 opnd_array(0)->int_format(ra, this, st); // res
26119 st->print_raw("\n\t");
26120 st->print_raw("movzbl ");
26121 opnd_array(0)->int_format(ra, this, st); // res
26122 st->print_raw(", ");
26123 opnd_array(0)->int_format(ra, this, st); // res
26124}
26125#endif
26126#ifndef PRODUCT
26127void z_xchgPNode::format(PhaseRegAlloc *ra, outputStream *st) const {
26128 // Start at oper_input_base() and count operands
26129 unsigned idx0 = 2;
26130 unsigned idx1 = 2; // mem
26131 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
26132 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // keepalive
26133 st->print_raw("XCHGQ ");
26134 opnd_array(2)->ext_format(ra, this,idx2, st); // newval
26135 st->print_raw(",[");
26136 opnd_array(1)->ext_format(ra, this,idx1, st); // mem
26137 st->print_raw("]");
26138}
26139#endif
26140// Check consistency of C++ compilation with ADLC options:
26141// Check adlc -DLINUX=1
26142#ifndef LINUX
26143# error "LINUX must be defined"
26144#endif // LINUX
26145// Check adlc -D_GNU_SOURCE=1
26146#ifndef _GNU_SOURCE
26147# error "_GNU_SOURCE must be defined"
26148#endif // _GNU_SOURCE
26149// Check adlc -DAMD64=1
26150#ifndef AMD64
26151# error "AMD64 must be defined"
26152#endif // AMD64
26153// Check adlc -D_LP64=1
26154#ifndef _LP64
26155# error "_LP64 must be defined"
26156#endif // _LP64
26157