| 1 | #line 1 "ad_x86.hpp" |
|---|---|
| 2 | // |
| 3 | // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. |
| 4 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 5 | // |
| 6 | // This code is free software; you can redistribute it and/or modify it |
| 7 | // under the terms of the GNU General Public License version 2 only, as |
| 8 | // published by the Free Software Foundation. |
| 9 | // |
| 10 | // This code is distributed in the hope that it will be useful, but WITHOUT |
| 11 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | // version 2 for more details (a copy is included in the LICENSE file that |
| 14 | // accompanied this code). |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License version |
| 17 | // 2 along with this work; if not, write to the Free Software Foundation, |
| 18 | // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | // |
| 20 | // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| 21 | // or visit www.oracle.com if you need additional information or have any |
| 22 | // questions. |
| 23 | // |
| 24 | // |
| 25 | |
| 26 | // Machine Generated File. Do Not Edit! |
| 27 | |
| 28 | |
| 29 | #ifndef GENERATED_ADFILES_AD_HPP |
| 30 | #define GENERATED_ADFILES_AD_HPP |
| 31 | |
| 32 | #include "memory/allocation.hpp" |
| 33 | #include "oops/compressedOops.hpp" |
| 34 | #include "code/nativeInst.hpp" |
| 35 | #include "opto/machnode.hpp" |
| 36 | #include "opto/node.hpp" |
| 37 | #include "opto/regalloc.hpp" |
| 38 | #include "opto/subnode.hpp" |
| 39 | #include "opto/vectornode.hpp" |
| 40 | |
| 41 | |
| 42 | enum MachOperands { |
| 43 | /* 0 */ UNIVERSE, |
| 44 | /* 1 */ LABEL, |
| 45 | /* 2 */ SREGI, |
| 46 | /* 3 */ SREGP, |
| 47 | /* 4 */ SREGF, |
| 48 | /* 5 */ SREGD, |
| 49 | /* 6 */ SREGL, |
| 50 | /* 7 */ METHOD, |
| 51 | /* 8 */ IMMI, |
| 52 | /* 9 */ IMMI0, |
| 53 | /* 10 */ IMMI1, |
| 54 | /* 11 */ IMMI_M1, |
| 55 | /* 12 */ IMMI2, |
| 56 | /* 13 */ IMMI8, |
| 57 | /* 14 */ IMMU8, |
| 58 | /* 15 */ IMMI16, |
| 59 | /* 16 */ IMMU31, |
| 60 | /* 17 */ IMMI_32, |
| 61 | /* 18 */ IMMI_64, |
| 62 | /* 19 */ IMMP, |
| 63 | /* 20 */ IMMP0, |
| 64 | /* 21 */ IMMN, |
| 65 | /* 22 */ IMMNKLASS, |
| 66 | /* 23 */ IMMN0, |
| 67 | /* 24 */ IMMP31, |
| 68 | /* 25 */ IMML, |
| 69 | /* 26 */ IMML8, |
| 70 | /* 27 */ IMMUL32, |
| 71 | /* 28 */ IMML32, |
| 72 | /* 29 */ IMML0, |
| 73 | /* 30 */ IMML1, |
| 74 | /* 31 */ IMML_M1, |
| 75 | /* 32 */ IMML10, |
| 76 | /* 33 */ IMML_127, |
| 77 | /* 34 */ IMML_32BITS, |
| 78 | /* 35 */ IMMF0, |
| 79 | /* 36 */ IMMF, |
| 80 | /* 37 */ IMMD0, |
| 81 | /* 38 */ IMMD, |
| 82 | /* 39 */ IMMI_16, |
| 83 | /* 40 */ IMMI_24, |
| 84 | /* 41 */ IMMI_255, |
| 85 | /* 42 */ IMMI_65535, |
| 86 | /* 43 */ IMML_255, |
| 87 | /* 44 */ IMML_65535, |
| 88 | /* 45 */ RREGI, |
| 89 | /* 46 */ RAX_REGI, |
| 90 | /* 47 */ RBX_REGI, |
| 91 | /* 48 */ RCX_REGI, |
| 92 | /* 49 */ RDX_REGI, |
| 93 | /* 50 */ RDI_REGI, |
| 94 | /* 51 */ NO_RCX_REGI, |
| 95 | /* 52 */ NO_RAX_RDX_REGI, |
| 96 | /* 53 */ ANY_REGP, |
| 97 | /* 54 */ RREGP, |
| 98 | /* 55 */ RREGN, |
| 99 | /* 56 */ NO_RAX_REGP, |
| 100 | /* 57 */ NO_RBP_REGP, |
| 101 | /* 58 */ NO_RAX_RBX_REGP, |
| 102 | /* 59 */ RAX_REGP, |
| 103 | /* 60 */ RAX_REGN, |
| 104 | /* 61 */ RBX_REGP, |
| 105 | /* 62 */ RSI_REGP, |
| 106 | /* 63 */ RDI_REGP, |
| 107 | /* 64 */ R15_REGP, |
| 108 | /* 65 */ RREGL, |
| 109 | /* 66 */ NO_RAX_RDX_REGL, |
| 110 | /* 67 */ NO_RAX_REGL, |
| 111 | /* 68 */ NO_RCX_REGL, |
| 112 | /* 69 */ RAX_REGL, |
| 113 | /* 70 */ RCX_REGL, |
| 114 | /* 71 */ RDX_REGL, |
| 115 | /* 72 */ RFLAGSREG, |
| 116 | /* 73 */ RFLAGSREGU, |
| 117 | /* 74 */ RFLAGSREGUCF, |
| 118 | /* 75 */ REGF, |
| 119 | /* 76 */ LEGREGF, |
| 120 | /* 77 */ VLREGF, |
| 121 | /* 78 */ REGD, |
| 122 | /* 79 */ LEGREGD, |
| 123 | /* 80 */ VLREGD, |
| 124 | /* 81 */ VECS, |
| 125 | /* 82 */ LEGVECS, |
| 126 | /* 83 */ VECD, |
| 127 | /* 84 */ LEGVECD, |
| 128 | /* 85 */ VECX, |
| 129 | /* 86 */ LEGVECX, |
| 130 | /* 87 */ VECY, |
| 131 | /* 88 */ LEGVECY, |
| 132 | /* 89 */ INDIRECT, |
| 133 | /* 90 */ INDOFFSET8, |
| 134 | /* 91 */ INDOFFSET32, |
| 135 | /* 92 */ INDINDEXOFFSET, |
| 136 | /* 93 */ INDINDEX, |
| 137 | /* 94 */ INDINDEXSCALE, |
| 138 | /* 95 */ INDPOSINDEXSCALE, |
| 139 | /* 96 */ INDINDEXSCALEOFFSET, |
| 140 | /* 97 */ INDPOSINDEXOFFSET, |
| 141 | /* 98 */ INDPOSINDEXSCALEOFFSET, |
| 142 | /* 99 */ INDCOMPRESSEDOOPOFFSET, |
| 143 | /* 100 */ INDIRECTNARROW, |
| 144 | /* 101 */ INDOFFSET8NARROW, |
| 145 | /* 102 */ INDOFFSET32NARROW, |
| 146 | /* 103 */ INDINDEXOFFSETNARROW, |
| 147 | /* 104 */ INDINDEXNARROW, |
| 148 | /* 105 */ INDINDEXSCALENARROW, |
| 149 | /* 106 */ INDINDEXSCALEOFFSETNARROW, |
| 150 | /* 107 */ INDPOSINDEXOFFSETNARROW, |
| 151 | /* 108 */ INDPOSINDEXSCALEOFFSETNARROW, |
| 152 | /* 109 */ STACKSLOTP, |
| 153 | /* 110 */ STACKSLOTI, |
| 154 | /* 111 */ STACKSLOTF, |
| 155 | /* 112 */ STACKSLOTD, |
| 156 | /* 113 */ STACKSLOTL, |
| 157 | /* 114 */ CMPOP, |
| 158 | /* 115 */ CMPOPU, |
| 159 | /* 116 */ CMPOPUCF, |
| 160 | /* 117 */ CMPOPUCF2, |
| 161 | /* 118 */ RXMM0, |
| 162 | /* 119 */ RXMM1, |
| 163 | /* 120 */ RXMM2, |
| 164 | /* 121 */ RXMM3, |
| 165 | /* 122 */ RXMM4, |
| 166 | /* 123 */ RXMM5, |
| 167 | /* 124 */ RXMM6, |
| 168 | /* 125 */ RXMM7, |
| 169 | /* 126 */ RXMM8, |
| 170 | /* 127 */ RXMM9, |
| 171 | /* 128 */ RXMM10, |
| 172 | /* 129 */ RXMM11, |
| 173 | /* 130 */ RXMM12, |
| 174 | /* 131 */ RXMM13, |
| 175 | /* 132 */ RXMM14, |
| 176 | /* 133 */ RXMM15, |
| 177 | /* 134 */ RXMM16, |
| 178 | /* 135 */ RXMM17, |
| 179 | /* 136 */ RXMM18, |
| 180 | /* 137 */ RXMM19, |
| 181 | /* 138 */ RXMM20, |
| 182 | /* 139 */ RXMM21, |
| 183 | /* 140 */ RXMM22, |
| 184 | /* 141 */ RXMM23, |
| 185 | /* 142 */ RXMM24, |
| 186 | /* 143 */ RXMM25, |
| 187 | /* 144 */ RXMM26, |
| 188 | /* 145 */ RXMM27, |
| 189 | /* 146 */ RXMM28, |
| 190 | /* 147 */ RXMM29, |
| 191 | /* 148 */ RXMM30, |
| 192 | /* 149 */ RXMM31, |
| 193 | /* 150 */ VECZ, |
| 194 | /* 151 */ LEGVECZ, |
| 195 | /* 152 */ CMPOP_VCMPPD, |
| 196 | // last operand |
| 197 | /* 153 */ MEMORY, |
| 198 | // last operand class |
| 199 | /* 154 */ _ADDP_ANY_REGP_RREGL, |
| 200 | /* 155 */ _LSHIFTL_RREGL_IMMI2, |
| 201 | /* 156 */ _CONVI2L_RREGI_, |
| 202 | /* 157 */ _LSHIFTL__CONVI2L_RREGI__IMMI2, |
| 203 | /* 158 */ _ADDP_ANY_REGP__LSHIFTL_RREGL_IMMI2, |
| 204 | /* 159 */ _ADDP_ANY_REGP__CONVI2L_RREGI_, |
| 205 | /* 160 */ _ADDP_ANY_REGP__LSHIFTL__CONVI2L_RREGI__IMMI2, |
| 206 | /* 161 */ _DECODEN_RREGN_, |
| 207 | /* 162 */ _ADDP__DECODEN_RREGN__RREGL, |
| 208 | /* 163 */ _ADDP__DECODEN_RREGN___LSHIFTL_RREGL_IMMI2, |
| 209 | /* 164 */ _ADDP__DECODEN_RREGN___CONVI2L_RREGI_, |
| 210 | /* 165 */ _ADDP__DECODEN_RREGN___LSHIFTL__CONVI2L_RREGI__IMMI2, |
| 211 | /* 166 */ _LOADB_MEMORY_, |
| 212 | /* 167 */ _LOADUB_MEMORY_, |
| 213 | /* 168 */ _ANDI__LOADUB_MEMORY__IMMI, |
| 214 | /* 169 */ _LOADS_MEMORY_, |
| 215 | /* 170 */ _LSHIFTI__LOADS_MEMORY__IMMI_24, |
| 216 | /* 171 */ _LOADUS_MEMORY_, |
| 217 | /* 172 */ _LSHIFTI__LOADUS_MEMORY__IMMI_24, |
| 218 | /* 173 */ _ANDI__LOADUS_MEMORY__IMMI_255, |
| 219 | /* 174 */ _ANDI__LOADUS_MEMORY__IMMI, |
| 220 | /* 175 */ _LOADI_MEMORY_, |
| 221 | /* 176 */ _LSHIFTI__LOADI_MEMORY__IMMI_24, |
| 222 | /* 177 */ _LSHIFTI__LOADI_MEMORY__IMMI_16, |
| 223 | /* 178 */ _ANDI__LOADI_MEMORY__IMMI_255, |
| 224 | /* 179 */ _ANDI__LOADI_MEMORY__IMMI_65535, |
| 225 | /* 180 */ _ANDI__LOADI_MEMORY__IMMU31, |
| 226 | /* 181 */ _CONVI2L__LOADI_MEMORY__, |
| 227 | /* 182 */ _LOADL_MEMORY_, |
| 228 | /* 183 */ _CASTP2X_RREGP_, |
| 229 | /* 184 */ _CASTP2X__DECODEN_RREGN__, |
| 230 | /* 185 */ _ADDL__LSHIFTL_RREGL_IMMI2_IMML32, |
| 231 | /* 186 */ _BINARY_CMPOP_RFLAGSREG, |
| 232 | /* 187 */ _BINARY_RREGI_RREGI, |
| 233 | /* 188 */ _BINARY_CMPOPU_RFLAGSREGU, |
| 234 | /* 189 */ _BINARY_CMPOPUCF_RFLAGSREGUCF, |
| 235 | /* 190 */ _BINARY_RREGI__LOADI_MEMORY_, |
| 236 | /* 191 */ _BINARY_RREGN_RREGN, |
| 237 | /* 192 */ _BINARY_RREGP_RREGP, |
| 238 | /* 193 */ _BINARY_RREGL_RREGL, |
| 239 | /* 194 */ _BINARY_RREGL__LOADL_MEMORY_, |
| 240 | /* 195 */ _BINARY_REGF_REGF, |
| 241 | /* 196 */ _BINARY_REGD_REGD, |
| 242 | /* 197 */ _ADDI__LOADI_MEMORY__RREGI, |
| 243 | /* 198 */ _ADDI_RREGI__LOADI_MEMORY_, |
| 244 | /* 199 */ _ADDI__LOADI_MEMORY__IMMI, |
| 245 | /* 200 */ _ADDI__LOADI_MEMORY__IMMI1, |
| 246 | /* 201 */ _ADDI__LOADI_MEMORY__IMMI_M1, |
| 247 | /* 202 */ _ADDL__LOADL_MEMORY__RREGL, |
| 248 | /* 203 */ _ADDL_RREGL__LOADL_MEMORY_, |
| 249 | /* 204 */ _ADDL__LOADL_MEMORY__IMML32, |
| 250 | /* 205 */ _ADDL__LOADL_MEMORY__IMML1, |
| 251 | /* 206 */ _ADDL__LOADL_MEMORY__IMML_M1, |
| 252 | /* 207 */ _BINARY_RAX_REGP_RREGP, |
| 253 | /* 208 */ _BINARY_RAX_REGI_RREGI, |
| 254 | /* 209 */ _BINARY_RAX_REGL_RREGL, |
| 255 | /* 210 */ _BINARY_RAX_REGN_RREGN, |
| 256 | /* 211 */ _SUBI__LOADI_MEMORY__RREGI, |
| 257 | /* 212 */ _SUBI__LOADI_MEMORY__IMMI, |
| 258 | /* 213 */ _SUBL__LOADL_MEMORY__RREGL, |
| 259 | /* 214 */ _SUBL__LOADL_MEMORY__IMML32, |
| 260 | /* 215 */ _SUBI_IMMI0_RREGI, |
| 261 | /* 216 */ _SUBI_IMMI0__LOADI_MEMORY_, |
| 262 | /* 217 */ _SUBL_IMML0__LOADL_MEMORY_, |
| 263 | /* 218 */ _LSHIFTI__LOADI_MEMORY__IMMI1, |
| 264 | /* 219 */ _LSHIFTI__LOADI_MEMORY__IMMI8, |
| 265 | /* 220 */ _LSHIFTI__LOADI_MEMORY__RCX_REGI, |
| 266 | /* 221 */ _RSHIFTI__LOADI_MEMORY__IMMI1, |
| 267 | /* 222 */ _RSHIFTI__LOADI_MEMORY__IMMI8, |
| 268 | /* 223 */ _RSHIFTI__LOADI_MEMORY__RCX_REGI, |
| 269 | /* 224 */ _URSHIFTI__LOADI_MEMORY__IMMI1, |
| 270 | /* 225 */ _URSHIFTI__LOADI_MEMORY__IMMI8, |
| 271 | /* 226 */ _URSHIFTI__LOADI_MEMORY__RCX_REGI, |
| 272 | /* 227 */ _LSHIFTL__LOADL_MEMORY__IMMI1, |
| 273 | /* 228 */ _LSHIFTL__LOADL_MEMORY__IMMI8, |
| 274 | /* 229 */ _LSHIFTL__LOADL_MEMORY__RCX_REGI, |
| 275 | /* 230 */ _RSHIFTL__LOADL_MEMORY__IMMI1, |
| 276 | /* 231 */ _RSHIFTL__LOADL_MEMORY__IMMI8, |
| 277 | /* 232 */ _RSHIFTL__LOADL_MEMORY__RCX_REGI, |
| 278 | /* 233 */ _URSHIFTL__LOADL_MEMORY__IMMI1, |
| 279 | /* 234 */ _URSHIFTL__LOADL_MEMORY__IMMI8, |
| 280 | /* 235 */ _URSHIFTL__LOADL_MEMORY__RCX_REGI, |
| 281 | /* 236 */ _LSHIFTI_RREGI_IMMI_24, |
| 282 | /* 237 */ _LSHIFTI_RREGI_IMMI_16, |
| 283 | /* 238 */ _LSHIFTI_RREGI_IMMI1, |
| 284 | /* 239 */ _URSHIFTI_RREGI_IMMI_M1, |
| 285 | /* 240 */ _LSHIFTI_RREGI_IMMI8, |
| 286 | /* 241 */ _URSHIFTI_RREGI_IMMI8, |
| 287 | /* 242 */ _LSHIFTI_NO_RCX_REGI_RCX_REGI, |
| 288 | /* 243 */ _SUBI_IMMI0_RCX_REGI, |
| 289 | /* 244 */ _URSHIFTI_NO_RCX_REGI__SUBI_IMMI0_RCX_REGI, |
| 290 | /* 245 */ _SUBI_IMMI_32_RCX_REGI, |
| 291 | /* 246 */ _URSHIFTI_NO_RCX_REGI__SUBI_IMMI_32_RCX_REGI, |
| 292 | /* 247 */ _URSHIFTI_RREGI_IMMI1, |
| 293 | /* 248 */ _LSHIFTI_RREGI_IMMI_M1, |
| 294 | /* 249 */ _URSHIFTI_NO_RCX_REGI_RCX_REGI, |
| 295 | /* 250 */ _LSHIFTI_NO_RCX_REGI__SUBI_IMMI0_RCX_REGI, |
| 296 | /* 251 */ _LSHIFTI_NO_RCX_REGI__SUBI_IMMI_32_RCX_REGI, |
| 297 | /* 252 */ _LSHIFTL_RREGL_IMMI1, |
| 298 | /* 253 */ _URSHIFTL_RREGL_IMMI_M1, |
| 299 | /* 254 */ _LSHIFTL_RREGL_IMMI8, |
| 300 | /* 255 */ _URSHIFTL_RREGL_IMMI8, |
| 301 | /* 256 */ _LSHIFTL_NO_RCX_REGL_RCX_REGI, |
| 302 | /* 257 */ _URSHIFTL_NO_RCX_REGL__SUBI_IMMI0_RCX_REGI, |
| 303 | /* 258 */ _SUBI_IMMI_64_RCX_REGI, |
| 304 | /* 259 */ _URSHIFTL_NO_RCX_REGL__SUBI_IMMI_64_RCX_REGI, |
| 305 | /* 260 */ _URSHIFTL_RREGL_IMMI1, |
| 306 | /* 261 */ _LSHIFTL_RREGL_IMMI_M1, |
| 307 | /* 262 */ _URSHIFTL_NO_RCX_REGL_RCX_REGI, |
| 308 | /* 263 */ _LSHIFTL_NO_RCX_REGL__SUBI_IMMI0_RCX_REGI, |
| 309 | /* 264 */ _LSHIFTL_NO_RCX_REGL__SUBI_IMMI_64_RCX_REGI, |
| 310 | /* 265 */ _ANDI_RREGI_IMMI_255, |
| 311 | /* 266 */ _ANDI_RREGI_IMMI_65535, |
| 312 | /* 267 */ _ANDI__LOADB_MEMORY__RREGI, |
| 313 | /* 268 */ _ANDI_RREGI__LOADB_MEMORY_, |
| 314 | /* 269 */ _ANDI__LOADI_MEMORY__RREGI, |
| 315 | /* 270 */ _ANDI_RREGI__LOADI_MEMORY_, |
| 316 | /* 271 */ _ANDI__LOADI_MEMORY__IMMI, |
| 317 | /* 272 */ _XORI_RREGI_IMMI_M1, |
| 318 | /* 273 */ _ADDI_RREGI_IMMI_M1, |
| 319 | /* 274 */ _ORI__LOADB_MEMORY__RREGI, |
| 320 | /* 275 */ _ORI_RREGI__LOADB_MEMORY_, |
| 321 | /* 276 */ _ORI__LOADI_MEMORY__RREGI, |
| 322 | /* 277 */ _ORI_RREGI__LOADI_MEMORY_, |
| 323 | /* 278 */ _ORI__LOADI_MEMORY__IMMI, |
| 324 | /* 279 */ _XORI__LOADB_MEMORY__RREGI, |
| 325 | /* 280 */ _XORI_RREGI__LOADB_MEMORY_, |
| 326 | /* 281 */ _XORI__LOADI_MEMORY__RREGI, |
| 327 | /* 282 */ _XORI_RREGI__LOADI_MEMORY_, |
| 328 | /* 283 */ _XORI__LOADI_MEMORY__IMMI, |
| 329 | /* 284 */ _ANDL__LOADL_MEMORY__RREGL, |
| 330 | /* 285 */ _ANDL_RREGL__LOADL_MEMORY_, |
| 331 | /* 286 */ _ANDL__LOADL_MEMORY__IMML32, |
| 332 | /* 287 */ _XORL_RREGL_IMML_M1, |
| 333 | /* 288 */ _SUBL_IMML0_RREGL, |
| 334 | /* 289 */ _ADDL_RREGL_IMML_M1, |
| 335 | /* 290 */ _CASTP2X_ANY_REGP_, |
| 336 | /* 291 */ _ORL__LOADL_MEMORY__RREGL, |
| 337 | /* 292 */ _ORL_RREGL__LOADL_MEMORY_, |
| 338 | /* 293 */ _ORL__LOADL_MEMORY__IMML32, |
| 339 | /* 294 */ _XORL__LOADL_MEMORY__RREGL, |
| 340 | /* 295 */ _XORL_RREGL__LOADL_MEMORY_, |
| 341 | /* 296 */ _XORL__LOADL_MEMORY__IMML32, |
| 342 | /* 297 */ _CMPLTMASK_RREGI_RREGI, |
| 343 | /* 298 */ _ANDI__CMPLTMASK_RREGI_RREGI_RREGI, |
| 344 | /* 299 */ _SUBI_RREGI_RREGI, |
| 345 | /* 300 */ _ANDI_RREGI__CMPLTMASK_RREGI_RREGI, |
| 346 | /* 301 */ _LOADF_MEMORY_, |
| 347 | /* 302 */ _LOADD_MEMORY_, |
| 348 | /* 303 */ _BINARY_RDI_REGP_RCX_REGI, |
| 349 | /* 304 */ _BINARY_RSI_REGP_RDX_REGI, |
| 350 | /* 305 */ _BINARY_RDI_REGP_RDX_REGI, |
| 351 | /* 306 */ _BINARY_RSI_REGP_IMMI, |
| 352 | /* 307 */ _BINARY_RSI_REGP_RAX_REGI, |
| 353 | /* 308 */ _BINARY_RDI_REGP_RSI_REGP, |
| 354 | /* 309 */ _ANDI_RREGI_IMMI, |
| 355 | /* 310 */ _LOADP_MEMORY_, |
| 356 | /* 311 */ _LOADN_MEMORY_, |
| 357 | /* 312 */ _LOADNKLASS_MEMORY_, |
| 358 | /* 313 */ _ANDL_RREGL_IMML32, |
| 359 | /* 314 */ _ANDL__CASTP2X_RREGP___LOADL_MEMORY_, |
| 360 | /* 315 */ _ANDL__LOADL_MEMORY___CASTP2X_RREGP_, |
| 361 | /* 316 */ _ANDI__LOADUB_MEMORY__IMMU8, |
| 362 | /* 317 */ _ANDI__LOADB_MEMORY__IMMI8, |
| 363 | /* 318 */ _PARTIALSUBTYPECHECK_RSI_REGP_RAX_REGP, |
| 364 | /* 319 */ _LOADVECTOR_MEMORY_, |
| 365 | /* 320 */ _BINARY_CMPOP_VCMPPD_IMMI8, |
| 366 | /* 321 */ _BINARY_LEGVECY_LEGVECY, |
| 367 | /* 322 */ _BINARY_VECX_VECX, |
| 368 | /* 323 */ _BINARY_VECX__LOADVECTOR_MEMORY_, |
| 369 | /* 324 */ _BINARY_VECY_VECY, |
| 370 | /* 325 */ _BINARY_VECY__LOADVECTOR_MEMORY_, |
| 371 | /* 326 */ _BINARY_VECZ_VECZ, |
| 372 | /* 327 */ _BINARY_VECZ__LOADVECTOR_MEMORY_, |
| 373 | /* 328 */ _MULADDVS2VI_VECD_VECD, |
| 374 | /* 329 */ _MULADDVS2VI_VECX_VECX, |
| 375 | /* 330 */ _MULADDVS2VI_VECY_VECY, |
| 376 | /* 331 */ _MULADDVS2VI_VECZ_VECZ, |
| 377 | /* 332 */ _BINARY_MEMORY_RREGP, |
| 378 | // last internally defined operand |
| 379 | _LAST_MACH_OPER |
| 380 | }; |
| 381 | |
| 382 | enum MachOpcodes { |
| 383 | /* 0 */ Universe_rule, |
| 384 | /* 1 */ label_rule, |
| 385 | /* 2 */ sRegI_rule, |
| 386 | /* 3 */ sRegP_rule, |
| 387 | /* 4 */ sRegF_rule, |
| 388 | /* 5 */ sRegD_rule, |
| 389 | /* 6 */ sRegL_rule, |
| 390 | /* 7 */ method_rule, |
| 391 | /* 8 */ immI_rule, |
| 392 | /* 9 */ immI0_rule, |
| 393 | /* 10 */ immI1_rule, |
| 394 | /* 11 */ immI_M1_rule, |
| 395 | /* 12 */ immI2_rule, |
| 396 | /* 13 */ immI8_rule, |
| 397 | /* 14 */ immU8_rule, |
| 398 | /* 15 */ immI16_rule, |
| 399 | /* 16 */ immU31_rule, |
| 400 | /* 17 */ immI_32_rule, |
| 401 | /* 18 */ immI_64_rule, |
| 402 | /* 19 */ immP_rule, |
| 403 | /* 20 */ immP0_rule, |
| 404 | /* 21 */ immN_rule, |
| 405 | /* 22 */ immNKlass_rule, |
| 406 | /* 23 */ immN0_rule, |
| 407 | /* 24 */ immP31_rule, |
| 408 | /* 25 */ immL_rule, |
| 409 | /* 26 */ immL8_rule, |
| 410 | /* 27 */ immUL32_rule, |
| 411 | /* 28 */ immL32_rule, |
| 412 | /* 29 */ immL0_rule, |
| 413 | /* 30 */ immL1_rule, |
| 414 | /* 31 */ immL_M1_rule, |
| 415 | /* 32 */ immL10_rule, |
| 416 | /* 33 */ immL_127_rule, |
| 417 | /* 34 */ immL_32bits_rule, |
| 418 | /* 35 */ immF0_rule, |
| 419 | /* 36 */ immF_rule, |
| 420 | /* 37 */ immD0_rule, |
| 421 | /* 38 */ immD_rule, |
| 422 | /* 39 */ immI_16_rule, |
| 423 | /* 40 */ immI_24_rule, |
| 424 | /* 41 */ immI_255_rule, |
| 425 | /* 42 */ immI_65535_rule, |
| 426 | /* 43 */ immL_255_rule, |
| 427 | /* 44 */ immL_65535_rule, |
| 428 | /* 45 */ rRegI_rule, |
| 429 | /* 46 */ rax_RegI_rule, |
| 430 | /* 47 */ rbx_RegI_rule, |
| 431 | /* 48 */ rcx_RegI_rule, |
| 432 | /* 49 */ rdx_RegI_rule, |
| 433 | /* 50 */ rdi_RegI_rule, |
| 434 | /* 51 */ no_rcx_RegI_rule, |
| 435 | /* 52 */ no_rax_rdx_RegI_rule, |
| 436 | /* 53 */ any_RegP_rule, |
| 437 | /* 54 */ rRegP_rule, |
| 438 | /* 55 */ rRegN_rule, |
| 439 | /* 56 */ no_rax_RegP_rule, |
| 440 | /* 57 */ no_rbp_RegP_rule, |
| 441 | /* 58 */ no_rax_rbx_RegP_rule, |
| 442 | /* 59 */ rax_RegP_rule, |
| 443 | /* 60 */ rax_RegN_rule, |
| 444 | /* 61 */ rbx_RegP_rule, |
| 445 | /* 62 */ rsi_RegP_rule, |
| 446 | /* 63 */ rdi_RegP_rule, |
| 447 | /* 64 */ r15_RegP_rule, |
| 448 | /* 65 */ rRegL_rule, |
| 449 | /* 66 */ no_rax_rdx_RegL_rule, |
| 450 | /* 67 */ no_rax_RegL_rule, |
| 451 | /* 68 */ no_rcx_RegL_rule, |
| 452 | /* 69 */ rax_RegL_rule, |
| 453 | /* 70 */ rcx_RegL_rule, |
| 454 | /* 71 */ rdx_RegL_rule, |
| 455 | /* 72 */ rFlagsReg_rule, |
| 456 | /* 73 */ rFlagsRegU_rule, |
| 457 | /* 74 */ rFlagsRegUCF_rule, |
| 458 | /* 75 */ regF_rule, |
| 459 | /* 76 */ legRegF_rule, |
| 460 | /* 77 */ vlRegF_rule, |
| 461 | /* 78 */ regD_rule, |
| 462 | /* 79 */ legRegD_rule, |
| 463 | /* 80 */ vlRegD_rule, |
| 464 | /* 81 */ vecS_rule, |
| 465 | /* 82 */ legVecS_rule, |
| 466 | /* 83 */ vecD_rule, |
| 467 | /* 84 */ legVecD_rule, |
| 468 | /* 85 */ vecX_rule, |
| 469 | /* 86 */ legVecX_rule, |
| 470 | /* 87 */ vecY_rule, |
| 471 | /* 88 */ legVecY_rule, |
| 472 | /* 89 */ indirect_rule, |
| 473 | /* 90 */ indOffset8_rule, |
| 474 | /* 91 */ indOffset32_rule, |
| 475 | /* 92 */ indIndexOffset_rule, |
| 476 | /* 93 */ indIndex_rule, |
| 477 | /* 94 */ indIndexScale_rule, |
| 478 | /* 95 */ indPosIndexScale_rule, |
| 479 | /* 96 */ indIndexScaleOffset_rule, |
| 480 | /* 97 */ indPosIndexOffset_rule, |
| 481 | /* 98 */ indPosIndexScaleOffset_rule, |
| 482 | /* 99 */ indCompressedOopOffset_rule, |
| 483 | /* 100 */ indirectNarrow_rule, |
| 484 | /* 101 */ indOffset8Narrow_rule, |
| 485 | /* 102 */ indOffset32Narrow_rule, |
| 486 | /* 103 */ indIndexOffsetNarrow_rule, |
| 487 | /* 104 */ indIndexNarrow_rule, |
| 488 | /* 105 */ indIndexScaleNarrow_rule, |
| 489 | /* 106 */ indIndexScaleOffsetNarrow_rule, |
| 490 | /* 107 */ indPosIndexOffsetNarrow_rule, |
| 491 | /* 108 */ indPosIndexScaleOffsetNarrow_rule, |
| 492 | /* 109 */ stackSlotP_rule, |
| 493 | /* 110 */ stackSlotI_rule, |
| 494 | /* 111 */ stackSlotF_rule, |
| 495 | /* 112 */ stackSlotD_rule, |
| 496 | /* 113 */ stackSlotL_rule, |
| 497 | /* 114 */ cmpOp_rule, |
| 498 | /* 115 */ cmpOpU_rule, |
| 499 | /* 116 */ cmpOpUCF_rule, |
| 500 | /* 117 */ cmpOpUCF2_rule, |
| 501 | /* 118 */ rxmm0_rule, |
| 502 | /* 119 */ rxmm1_rule, |
| 503 | /* 120 */ rxmm2_rule, |
| 504 | /* 121 */ rxmm3_rule, |
| 505 | /* 122 */ rxmm4_rule, |
| 506 | /* 123 */ rxmm5_rule, |
| 507 | /* 124 */ rxmm6_rule, |
| 508 | /* 125 */ rxmm7_rule, |
| 509 | /* 126 */ rxmm8_rule, |
| 510 | /* 127 */ rxmm9_rule, |
| 511 | /* 128 */ rxmm10_rule, |
| 512 | /* 129 */ rxmm11_rule, |
| 513 | /* 130 */ rxmm12_rule, |
| 514 | /* 131 */ rxmm13_rule, |
| 515 | /* 132 */ rxmm14_rule, |
| 516 | /* 133 */ rxmm15_rule, |
| 517 | /* 134 */ rxmm16_rule, |
| 518 | /* 135 */ rxmm17_rule, |
| 519 | /* 136 */ rxmm18_rule, |
| 520 | /* 137 */ rxmm19_rule, |
| 521 | /* 138 */ rxmm20_rule, |
| 522 | /* 139 */ rxmm21_rule, |
| 523 | /* 140 */ rxmm22_rule, |
| 524 | /* 141 */ rxmm23_rule, |
| 525 | /* 142 */ rxmm24_rule, |
| 526 | /* 143 */ rxmm25_rule, |
| 527 | /* 144 */ rxmm26_rule, |
| 528 | /* 145 */ rxmm27_rule, |
| 529 | /* 146 */ rxmm28_rule, |
| 530 | /* 147 */ rxmm29_rule, |
| 531 | /* 148 */ rxmm30_rule, |
| 532 | /* 149 */ rxmm31_rule, |
| 533 | /* 150 */ vecZ_rule, |
| 534 | /* 151 */ legVecZ_rule, |
| 535 | /* 152 */ cmpOp_vcmppd_rule, |
| 536 | // last operand |
| 537 | /* 153 */ memory_rule, |
| 538 | // last operand class |
| 539 | /* 154 */ _AddP_any_RegP_rRegL_rule, |
| 540 | /* 155 */ _LShiftL_rRegL_immI2_rule, |
| 541 | /* 156 */ _ConvI2L_rRegI__rule, |
| 542 | /* 157 */ _LShiftL__ConvI2L_rRegI__immI2_rule, |
| 543 | /* 158 */ _AddP_any_RegP__LShiftL_rRegL_immI2_rule, |
| 544 | /* 159 */ _AddP_any_RegP__ConvI2L_rRegI__rule, |
| 545 | /* 160 */ _AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2_rule, |
| 546 | /* 161 */ _DecodeN_rRegN__rule, |
| 547 | /* 162 */ _AddP__DecodeN_rRegN__rRegL_rule, |
| 548 | /* 163 */ _AddP__DecodeN_rRegN___LShiftL_rRegL_immI2_rule, |
| 549 | /* 164 */ _AddP__DecodeN_rRegN___ConvI2L_rRegI__rule, |
| 550 | /* 165 */ _AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2_rule, |
| 551 | /* 166 */ _LoadB_memory__rule, |
| 552 | /* 167 */ _LoadUB_memory__rule, |
| 553 | /* 168 */ _AndI__LoadUB_memory__immI_rule, |
| 554 | /* 169 */ _LoadS_memory__rule, |
| 555 | /* 170 */ _LShiftI__LoadS_memory__immI_24_rule, |
| 556 | /* 171 */ _LoadUS_memory__rule, |
| 557 | /* 172 */ _LShiftI__LoadUS_memory__immI_24_rule, |
| 558 | /* 173 */ _AndI__LoadUS_memory__immI_255_rule, |
| 559 | /* 174 */ _AndI__LoadUS_memory__immI_rule, |
| 560 | /* 175 */ _LoadI_memory__rule, |
| 561 | /* 176 */ _LShiftI__LoadI_memory__immI_24_rule, |
| 562 | /* 177 */ _LShiftI__LoadI_memory__immI_16_rule, |
| 563 | /* 178 */ _AndI__LoadI_memory__immI_255_rule, |
| 564 | /* 179 */ _AndI__LoadI_memory__immI_65535_rule, |
| 565 | /* 180 */ _AndI__LoadI_memory__immU31_rule, |
| 566 | /* 181 */ _ConvI2L__LoadI_memory___rule, |
| 567 | /* 182 */ _LoadL_memory__rule, |
| 568 | /* 183 */ _CastP2X_rRegP__rule, |
| 569 | /* 184 */ _CastP2X__DecodeN_rRegN___rule, |
| 570 | /* 185 */ _AddL__LShiftL_rRegL_immI2_immL32_rule, |
| 571 | /* 186 */ _Binary_cmpOp_rFlagsReg_rule, |
| 572 | /* 187 */ _Binary_rRegI_rRegI_rule, |
| 573 | /* 188 */ _Binary_cmpOpU_rFlagsRegU_rule, |
| 574 | /* 189 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule, |
| 575 | /* 190 */ _Binary_rRegI__LoadI_memory__rule, |
| 576 | /* 191 */ _Binary_rRegN_rRegN_rule, |
| 577 | /* 192 */ _Binary_rRegP_rRegP_rule, |
| 578 | /* 193 */ _Binary_rRegL_rRegL_rule, |
| 579 | /* 194 */ _Binary_rRegL__LoadL_memory__rule, |
| 580 | /* 195 */ _Binary_regF_regF_rule, |
| 581 | /* 196 */ _Binary_regD_regD_rule, |
| 582 | /* 197 */ _AddI__LoadI_memory__rRegI_rule, |
| 583 | /* 198 */ _AddI_rRegI__LoadI_memory__rule, |
| 584 | /* 199 */ _AddI__LoadI_memory__immI_rule, |
| 585 | /* 200 */ _AddI__LoadI_memory__immI1_rule, |
| 586 | /* 201 */ _AddI__LoadI_memory__immI_M1_rule, |
| 587 | /* 202 */ _AddL__LoadL_memory__rRegL_rule, |
| 588 | /* 203 */ _AddL_rRegL__LoadL_memory__rule, |
| 589 | /* 204 */ _AddL__LoadL_memory__immL32_rule, |
| 590 | /* 205 */ _AddL__LoadL_memory__immL1_rule, |
| 591 | /* 206 */ _AddL__LoadL_memory__immL_M1_rule, |
| 592 | /* 207 */ _Binary_rax_RegP_rRegP_rule, |
| 593 | /* 208 */ _Binary_rax_RegI_rRegI_rule, |
| 594 | /* 209 */ _Binary_rax_RegL_rRegL_rule, |
| 595 | /* 210 */ _Binary_rax_RegN_rRegN_rule, |
| 596 | /* 211 */ _SubI__LoadI_memory__rRegI_rule, |
| 597 | /* 212 */ _SubI__LoadI_memory__immI_rule, |
| 598 | /* 213 */ _SubL__LoadL_memory__rRegL_rule, |
| 599 | /* 214 */ _SubL__LoadL_memory__immL32_rule, |
| 600 | /* 215 */ _SubI_immI0_rRegI_rule, |
| 601 | /* 216 */ _SubI_immI0__LoadI_memory__rule, |
| 602 | /* 217 */ _SubL_immL0__LoadL_memory__rule, |
| 603 | /* 218 */ _LShiftI__LoadI_memory__immI1_rule, |
| 604 | /* 219 */ _LShiftI__LoadI_memory__immI8_rule, |
| 605 | /* 220 */ _LShiftI__LoadI_memory__rcx_RegI_rule, |
| 606 | /* 221 */ _RShiftI__LoadI_memory__immI1_rule, |
| 607 | /* 222 */ _RShiftI__LoadI_memory__immI8_rule, |
| 608 | /* 223 */ _RShiftI__LoadI_memory__rcx_RegI_rule, |
| 609 | /* 224 */ _URShiftI__LoadI_memory__immI1_rule, |
| 610 | /* 225 */ _URShiftI__LoadI_memory__immI8_rule, |
| 611 | /* 226 */ _URShiftI__LoadI_memory__rcx_RegI_rule, |
| 612 | /* 227 */ _LShiftL__LoadL_memory__immI1_rule, |
| 613 | /* 228 */ _LShiftL__LoadL_memory__immI8_rule, |
| 614 | /* 229 */ _LShiftL__LoadL_memory__rcx_RegI_rule, |
| 615 | /* 230 */ _RShiftL__LoadL_memory__immI1_rule, |
| 616 | /* 231 */ _RShiftL__LoadL_memory__immI8_rule, |
| 617 | /* 232 */ _RShiftL__LoadL_memory__rcx_RegI_rule, |
| 618 | /* 233 */ _URShiftL__LoadL_memory__immI1_rule, |
| 619 | /* 234 */ _URShiftL__LoadL_memory__immI8_rule, |
| 620 | /* 235 */ _URShiftL__LoadL_memory__rcx_RegI_rule, |
| 621 | /* 236 */ _LShiftI_rRegI_immI_24_rule, |
| 622 | /* 237 */ _LShiftI_rRegI_immI_16_rule, |
| 623 | /* 238 */ _LShiftI_rRegI_immI1_rule, |
| 624 | /* 239 */ _URShiftI_rRegI_immI_M1_rule, |
| 625 | /* 240 */ _LShiftI_rRegI_immI8_rule, |
| 626 | /* 241 */ _URShiftI_rRegI_immI8_rule, |
| 627 | /* 242 */ _LShiftI_no_rcx_RegI_rcx_RegI_rule, |
| 628 | /* 243 */ _SubI_immI0_rcx_RegI_rule, |
| 629 | /* 244 */ _URShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule, |
| 630 | /* 245 */ _SubI_immI_32_rcx_RegI_rule, |
| 631 | /* 246 */ _URShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule, |
| 632 | /* 247 */ _URShiftI_rRegI_immI1_rule, |
| 633 | /* 248 */ _LShiftI_rRegI_immI_M1_rule, |
| 634 | /* 249 */ _URShiftI_no_rcx_RegI_rcx_RegI_rule, |
| 635 | /* 250 */ _LShiftI_no_rcx_RegI__SubI_immI0_rcx_RegI_rule, |
| 636 | /* 251 */ _LShiftI_no_rcx_RegI__SubI_immI_32_rcx_RegI_rule, |
| 637 | /* 252 */ _LShiftL_rRegL_immI1_rule, |
| 638 | /* 253 */ _URShiftL_rRegL_immI_M1_rule, |
| 639 | /* 254 */ _LShiftL_rRegL_immI8_rule, |
| 640 | /* 255 */ _URShiftL_rRegL_immI8_rule, |
| 641 | /* 256 */ _LShiftL_no_rcx_RegL_rcx_RegI_rule, |
| 642 | /* 257 */ _URShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule, |
| 643 | /* 258 */ _SubI_immI_64_rcx_RegI_rule, |
| 644 | /* 259 */ _URShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule, |
| 645 | /* 260 */ _URShiftL_rRegL_immI1_rule, |
| 646 | /* 261 */ _LShiftL_rRegL_immI_M1_rule, |
| 647 | /* 262 */ _URShiftL_no_rcx_RegL_rcx_RegI_rule, |
| 648 | /* 263 */ _LShiftL_no_rcx_RegL__SubI_immI0_rcx_RegI_rule, |
| 649 | /* 264 */ _LShiftL_no_rcx_RegL__SubI_immI_64_rcx_RegI_rule, |
| 650 | /* 265 */ _AndI_rRegI_immI_255_rule, |
| 651 | /* 266 */ _AndI_rRegI_immI_65535_rule, |
| 652 | /* 267 */ _AndI__LoadB_memory__rRegI_rule, |
| 653 | /* 268 */ _AndI_rRegI__LoadB_memory__rule, |
| 654 | /* 269 */ _AndI__LoadI_memory__rRegI_rule, |
| 655 | /* 270 */ _AndI_rRegI__LoadI_memory__rule, |
| 656 | /* 271 */ _AndI__LoadI_memory__immI_rule, |
| 657 | /* 272 */ _XorI_rRegI_immI_M1_rule, |
| 658 | /* 273 */ _AddI_rRegI_immI_M1_rule, |
| 659 | /* 274 */ _OrI__LoadB_memory__rRegI_rule, |
| 660 | /* 275 */ _OrI_rRegI__LoadB_memory__rule, |
| 661 | /* 276 */ _OrI__LoadI_memory__rRegI_rule, |
| 662 | /* 277 */ _OrI_rRegI__LoadI_memory__rule, |
| 663 | /* 278 */ _OrI__LoadI_memory__immI_rule, |
| 664 | /* 279 */ _XorI__LoadB_memory__rRegI_rule, |
| 665 | /* 280 */ _XorI_rRegI__LoadB_memory__rule, |
| 666 | /* 281 */ _XorI__LoadI_memory__rRegI_rule, |
| 667 | /* 282 */ _XorI_rRegI__LoadI_memory__rule, |
| 668 | /* 283 */ _XorI__LoadI_memory__immI_rule, |
| 669 | /* 284 */ _AndL__LoadL_memory__rRegL_rule, |
| 670 | /* 285 */ _AndL_rRegL__LoadL_memory__rule, |
| 671 | /* 286 */ _AndL__LoadL_memory__immL32_rule, |
| 672 | /* 287 */ _XorL_rRegL_immL_M1_rule, |
| 673 | /* 288 */ _SubL_immL0_rRegL_rule, |
| 674 | /* 289 */ _AddL_rRegL_immL_M1_rule, |
| 675 | /* 290 */ _CastP2X_any_RegP__rule, |
| 676 | /* 291 */ _OrL__LoadL_memory__rRegL_rule, |
| 677 | /* 292 */ _OrL_rRegL__LoadL_memory__rule, |
| 678 | /* 293 */ _OrL__LoadL_memory__immL32_rule, |
| 679 | /* 294 */ _XorL__LoadL_memory__rRegL_rule, |
| 680 | /* 295 */ _XorL_rRegL__LoadL_memory__rule, |
| 681 | /* 296 */ _XorL__LoadL_memory__immL32_rule, |
| 682 | /* 297 */ _CmpLTMask_rRegI_rRegI_rule, |
| 683 | /* 298 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule, |
| 684 | /* 299 */ _SubI_rRegI_rRegI_rule, |
| 685 | /* 300 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule, |
| 686 | /* 301 */ _LoadF_memory__rule, |
| 687 | /* 302 */ _LoadD_memory__rule, |
| 688 | /* 303 */ _Binary_rdi_RegP_rcx_RegI_rule, |
| 689 | /* 304 */ _Binary_rsi_RegP_rdx_RegI_rule, |
| 690 | /* 305 */ _Binary_rdi_RegP_rdx_RegI_rule, |
| 691 | /* 306 */ _Binary_rsi_RegP_immI_rule, |
| 692 | /* 307 */ _Binary_rsi_RegP_rax_RegI_rule, |
| 693 | /* 308 */ _Binary_rdi_RegP_rsi_RegP_rule, |
| 694 | /* 309 */ _AndI_rRegI_immI_rule, |
| 695 | /* 310 */ _LoadP_memory__rule, |
| 696 | /* 311 */ _LoadN_memory__rule, |
| 697 | /* 312 */ _LoadNKlass_memory__rule, |
| 698 | /* 313 */ _AndL_rRegL_immL32_rule, |
| 699 | /* 314 */ _AndL__CastP2X_rRegP___LoadL_memory__rule, |
| 700 | /* 315 */ _AndL__LoadL_memory___CastP2X_rRegP__rule, |
| 701 | /* 316 */ _AndI__LoadUB_memory__immU8_rule, |
| 702 | /* 317 */ _AndI__LoadB_memory__immI8_rule, |
| 703 | /* 318 */ _PartialSubtypeCheck_rsi_RegP_rax_RegP_rule, |
| 704 | /* 319 */ _LoadVector_memory__rule, |
| 705 | /* 320 */ _Binary_cmpOp_vcmppd_immI8_rule, |
| 706 | /* 321 */ _Binary_legVecY_legVecY_rule, |
| 707 | /* 322 */ _Binary_vecX_vecX_rule, |
| 708 | /* 323 */ _Binary_vecX__LoadVector_memory__rule, |
| 709 | /* 324 */ _Binary_vecY_vecY_rule, |
| 710 | /* 325 */ _Binary_vecY__LoadVector_memory__rule, |
| 711 | /* 326 */ _Binary_vecZ_vecZ_rule, |
| 712 | /* 327 */ _Binary_vecZ__LoadVector_memory__rule, |
| 713 | /* 328 */ _MulAddVS2VI_vecD_vecD_rule, |
| 714 | /* 329 */ _MulAddVS2VI_vecX_vecX_rule, |
| 715 | /* 330 */ _MulAddVS2VI_vecY_vecY_rule, |
| 716 | /* 331 */ _MulAddVS2VI_vecZ_vecZ_rule, |
| 717 | /* 332 */ _Binary_memory_rRegP_rule, |
| 718 | // last internally defined operand |
| 719 | /* 333 */ storeSSI_rule, |
| 720 | /* 334 */ storeSSL_rule, |
| 721 | /* 335 */ storeSSP_rule, |
| 722 | /* 336 */ storeSSF_rule, |
| 723 | /* 337 */ storeSSD_rule, |
| 724 | /* 338 */ MoveF2VL_rule, |
| 725 | /* 339 */ MoveF2LEG_rule, |
| 726 | /* 340 */ MoveVL2F_rule, |
| 727 | /* 341 */ MoveLEG2F_rule, |
| 728 | /* 342 */ MoveD2VL_rule, |
| 729 | /* 343 */ MoveD2LEG_rule, |
| 730 | /* 344 */ MoveVL2D_rule, |
| 731 | /* 345 */ MoveLEG2D_rule, |
| 732 | /* 346 */ leaP8_rule, |
| 733 | /* 347 */ leaP32_rule, |
| 734 | /* 348 */ leaPIdxOff_rule, |
| 735 | /* 349 */ leaPIdxScale_rule, |
| 736 | /* 350 */ leaPPosIdxScale_rule, |
| 737 | /* 351 */ leaPIdxScaleOff_rule, |
| 738 | /* 352 */ leaPPosIdxOff_rule, |
| 739 | /* 353 */ leaPPosIdxScaleOff_rule, |
| 740 | /* 354 */ leaPCompressedOopOffset_rule, |
| 741 | /* 355 */ leaP8Narrow_rule, |
| 742 | /* 356 */ leaP32Narrow_rule, |
| 743 | /* 357 */ leaPIdxOffNarrow_rule, |
| 744 | /* 358 */ leaPIdxScaleNarrow_rule, |
| 745 | /* 359 */ leaPIdxScaleOffNarrow_rule, |
| 746 | /* 360 */ leaPPosIdxOffNarrow_rule, |
| 747 | /* 361 */ leaPPosIdxScaleOffNarrow_rule, |
| 748 | /* 362 */ loadConI_rule, |
| 749 | /* 363 */ loadConI0_rule, |
| 750 | /* 364 */ loadConL_rule, |
| 751 | /* 365 */ loadConL0_rule, |
| 752 | /* 366 */ loadConUL32_rule, |
| 753 | /* 367 */ loadConL32_rule, |
| 754 | /* 368 */ loadConP_rule, |
| 755 | /* 369 */ loadConP0_rule, |
| 756 | /* 370 */ loadConP31_rule, |
| 757 | /* 371 */ loadConF_rule, |
| 758 | /* 372 */ loadConN0_rule, |
| 759 | /* 373 */ loadConN_rule, |
| 760 | /* 374 */ loadConNKlass_rule, |
| 761 | /* 375 */ loadConF0_rule, |
| 762 | /* 376 */ loadConD_rule, |
| 763 | /* 377 */ loadConD0_rule, |
| 764 | /* 378 */ loadSSI_rule, |
| 765 | /* 379 */ loadSSL_rule, |
| 766 | /* 380 */ loadSSP_rule, |
| 767 | /* 381 */ loadSSF_rule, |
| 768 | /* 382 */ loadSSD_rule, |
| 769 | /* 383 */ MoveVecS2Leg_rule, |
| 770 | /* 384 */ MoveLeg2VecS_rule, |
| 771 | /* 385 */ MoveVecD2Leg_rule, |
| 772 | /* 386 */ MoveLeg2VecD_rule, |
| 773 | /* 387 */ MoveVecX2Leg_rule, |
| 774 | /* 388 */ MoveLeg2VecX_rule, |
| 775 | /* 389 */ MoveVecY2Leg_rule, |
| 776 | /* 390 */ MoveLeg2VecY_rule, |
| 777 | /* 391 */ MoveVecZ2Leg_rule, |
| 778 | /* 392 */ MoveLeg2VecZ_rule, |
| 779 | /* 393 */ vshiftcntimm_rule, |
| 780 | /* 394 */ membar_volatile_rule, |
| 781 | /* 395 */ castX2P_rule, |
| 782 | /* 396 */ castP2X_rule, |
| 783 | /* 397 */ checkCastPP_rule, |
| 784 | /* 398 */ castPP_rule, |
| 785 | /* 399 */ castII_rule, |
| 786 | /* 400 */ storePConditional_rule, |
| 787 | /* 401 */ storeIConditional_rule, |
| 788 | /* 402 */ storeLConditional_rule, |
| 789 | /* 403 */ cmpF_cc_reg_rule, |
| 790 | /* 404 */ cmpF_cc_reg_CF_rule, |
| 791 | /* 405 */ cmpF_cc_mem_rule, |
| 792 | /* 406 */ cmpF_cc_memCF_rule, |
| 793 | /* 407 */ cmpF_cc_imm_rule, |
| 794 | /* 408 */ cmpF_cc_immCF_rule, |
| 795 | /* 409 */ cmpD_cc_reg_rule, |
| 796 | /* 410 */ cmpD_cc_reg_CF_rule, |
| 797 | /* 411 */ cmpD_cc_mem_rule, |
| 798 | /* 412 */ cmpD_cc_memCF_rule, |
| 799 | /* 413 */ cmpD_cc_imm_rule, |
| 800 | /* 414 */ cmpD_cc_immCF_rule, |
| 801 | /* 415 */ roundFloat_nop_rule, |
| 802 | /* 416 */ roundDouble_nop_rule, |
| 803 | /* 417 */ MoveF2I_stack_reg_rule, |
| 804 | /* 418 */ MoveI2F_stack_reg_rule, |
| 805 | /* 419 */ MoveD2L_stack_reg_rule, |
| 806 | /* 420 */ MoveL2D_stack_reg_partial_rule, |
| 807 | /* 421 */ MoveL2D_stack_reg_rule, |
| 808 | /* 422 */ MoveF2I_reg_reg_rule, |
| 809 | /* 423 */ MoveD2L_reg_reg_rule, |
| 810 | /* 424 */ MoveI2F_reg_reg_rule, |
| 811 | /* 425 */ MoveL2D_reg_reg_rule, |
| 812 | /* 426 */ overflowAddI_rReg_rule, |
| 813 | /* 427 */ overflowAddI_rReg_imm_rule, |
| 814 | /* 428 */ overflowAddL_rReg_rule, |
| 815 | /* 429 */ overflowAddL_rReg_imm_rule, |
| 816 | /* 430 */ overflowSubI_rReg_rule, |
| 817 | /* 431 */ overflowSubI_rReg_imm_rule, |
| 818 | /* 432 */ overflowSubL_rReg_rule, |
| 819 | /* 433 */ overflowSubL_rReg_imm_rule, |
| 820 | /* 434 */ overflowNegI_rReg_rule, |
| 821 | /* 435 */ overflowNegL_rReg_rule, |
| 822 | /* 436 */ overflowMulI_rReg_rule, |
| 823 | /* 437 */ overflowMulI_rReg_imm_rule, |
| 824 | /* 438 */ overflowMulL_rReg_rule, |
| 825 | /* 439 */ overflowMulL_rReg_imm_rule, |
| 826 | /* 440 */ compI_rReg_rule, |
| 827 | /* 441 */ compI_rReg_imm_rule, |
| 828 | /* 442 */ compI_rReg_mem_rule, |
| 829 | /* 443 */ testI_reg_rule, |
| 830 | /* 444 */ testI_reg_imm_rule, |
| 831 | /* 445 */ testI_reg_mem_rule, |
| 832 | /* 446 */ testI_reg_mem_0_rule, |
| 833 | /* 447 */ compU_rReg_rule, |
| 834 | /* 448 */ compU_rReg_imm_rule, |
| 835 | /* 449 */ compU_rReg_mem_rule, |
| 836 | /* 450 */ testU_reg_rule, |
| 837 | /* 451 */ compP_rReg_rule, |
| 838 | /* 452 */ compP_rReg_mem_rule, |
| 839 | /* 453 */ compP_mem_rReg_rule, |
| 840 | /* 454 */ testP_reg_rule, |
| 841 | /* 455 */ testP_mem_rule, |
| 842 | /* 456 */ testP_mem_reg0_rule, |
| 843 | /* 457 */ compN_rReg_rule, |
| 844 | /* 458 */ compN_rReg_mem_rule, |
| 845 | /* 459 */ compN_rReg_imm_rule, |
| 846 | /* 460 */ compN_mem_imm_rule, |
| 847 | /* 461 */ compN_rReg_imm_klass_rule, |
| 848 | /* 462 */ compN_mem_imm_klass_rule, |
| 849 | /* 463 */ testN_reg_rule, |
| 850 | /* 464 */ testN_mem_rule, |
| 851 | /* 465 */ testN_mem_reg0_rule, |
| 852 | /* 466 */ compL_rReg_rule, |
| 853 | /* 467 */ compL_rReg_imm_rule, |
| 854 | /* 468 */ compL_rReg_mem_rule, |
| 855 | /* 469 */ testL_reg_rule, |
| 856 | /* 470 */ testL_reg_imm_rule, |
| 857 | /* 471 */ testL_reg_mem_rule, |
| 858 | /* 472 */ testL_reg_mem_0_rule, |
| 859 | /* 473 */ testL_reg_mem2_rule, |
| 860 | /* 474 */ testL_reg_mem2_0_rule, |
| 861 | /* 475 */ compUL_rReg_rule, |
| 862 | /* 476 */ compUL_rReg_imm_rule, |
| 863 | /* 477 */ compUL_rReg_mem_rule, |
| 864 | /* 478 */ testUL_reg_rule, |
| 865 | /* 479 */ compB_mem_imm_rule, |
| 866 | /* 480 */ testUB_mem_imm_rule, |
| 867 | /* 481 */ testB_mem_imm_rule, |
| 868 | /* 482 */ partialSubtypeCheck_vs_Zero_rule, |
| 869 | /* 483 */ cmpFastLockRTM_rule, |
| 870 | /* 484 */ cmpFastLock_rule, |
| 871 | /* 485 */ cmpFastUnlock_rule, |
| 872 | /* 486 */ safePoint_poll_rule, |
| 873 | /* 487 */ tlsLoadP_rule, |
| 874 | /* 488 */ absF_reg_rule, |
| 875 | /* 489 */ absF_reg_reg_rule, |
| 876 | /* 490 */ absD_reg_rule, |
| 877 | /* 491 */ absD_reg_reg_rule, |
| 878 | /* 492 */ negF_reg_rule, |
| 879 | /* 493 */ negF_reg_reg_rule, |
| 880 | /* 494 */ negD_reg_rule, |
| 881 | /* 495 */ negD_reg_reg_rule, |
| 882 | /* 496 */ vsqrt2D_reg_rule, |
| 883 | /* 497 */ vsqrt2D_mem_rule, |
| 884 | /* 498 */ vsqrt4D_reg_rule, |
| 885 | /* 499 */ vsqrt4D_mem_rule, |
| 886 | /* 500 */ vsqrt8D_reg_rule, |
| 887 | /* 501 */ vsqrt8D_mem_rule, |
| 888 | /* 502 */ vsqrt2F_reg_rule, |
| 889 | /* 503 */ vsqrt2F_mem_rule, |
| 890 | /* 504 */ vsqrt4F_reg_rule, |
| 891 | /* 505 */ vsqrt4F_mem_rule, |
| 892 | /* 506 */ vsqrt8F_reg_rule, |
| 893 | /* 507 */ vsqrt8F_mem_rule, |
| 894 | /* 508 */ vsqrt16F_reg_rule, |
| 895 | /* 509 */ vsqrt16F_mem_rule, |
| 896 | /* 510 */ vshiftcnt_rule, |
| 897 | /* 511 */ vshiftcnt_0_rule, |
| 898 | /* 512 */ vabs4B_reg_rule, |
| 899 | /* 513 */ vabs8B_reg_rule, |
| 900 | /* 514 */ vabs16B_reg_rule, |
| 901 | /* 515 */ vabs32B_reg_rule, |
| 902 | /* 516 */ vabs64B_reg_rule, |
| 903 | /* 517 */ vabs2S_reg_rule, |
| 904 | /* 518 */ vabs4S_reg_rule, |
| 905 | /* 519 */ vabs8S_reg_rule, |
| 906 | /* 520 */ vabs16S_reg_rule, |
| 907 | /* 521 */ vabs32S_reg_rule, |
| 908 | /* 522 */ vabs2I_reg_rule, |
| 909 | /* 523 */ vabs4I_reg_rule, |
| 910 | /* 524 */ vabs8I_reg_rule, |
| 911 | /* 525 */ vabs16I_reg_rule, |
| 912 | /* 526 */ vabs2L_reg_rule, |
| 913 | /* 527 */ vabs4L_reg_rule, |
| 914 | /* 528 */ vabs8L_reg_rule, |
| 915 | /* 529 */ vpopcount2I_rule, |
| 916 | /* 530 */ vpopcount4I_rule, |
| 917 | /* 531 */ vpopcount8I_rule, |
| 918 | /* 532 */ vpopcount16I_rule, |
| 919 | /* 533 */ loadB_rule, |
| 920 | /* 534 */ loadB2L_rule, |
| 921 | /* 535 */ loadUB_rule, |
| 922 | /* 536 */ loadUB2L_rule, |
| 923 | /* 537 */ loadUB2L_immI_rule, |
| 924 | /* 538 */ loadS_rule, |
| 925 | /* 539 */ loadS2B_rule, |
| 926 | /* 540 */ loadS2L_rule, |
| 927 | /* 541 */ loadUS_rule, |
| 928 | /* 542 */ loadUS2B_rule, |
| 929 | /* 543 */ loadUS2L_rule, |
| 930 | /* 544 */ loadUS2L_immI_255_rule, |
| 931 | /* 545 */ loadUS2L_immI_rule, |
| 932 | /* 546 */ loadI_rule, |
| 933 | /* 547 */ loadI2B_rule, |
| 934 | /* 548 */ loadI2UB_rule, |
| 935 | /* 549 */ loadI2S_rule, |
| 936 | /* 550 */ loadI2US_rule, |
| 937 | /* 551 */ loadI2L_rule, |
| 938 | /* 552 */ loadI2L_immI_255_rule, |
| 939 | /* 553 */ loadI2L_immI_65535_rule, |
| 940 | /* 554 */ loadI2L_immU31_rule, |
| 941 | /* 555 */ loadUI2L_rule, |
| 942 | /* 556 */ loadL_rule, |
| 943 | /* 557 */ loadRange_rule, |
| 944 | /* 558 */ loadP_rule, |
| 945 | /* 559 */ loadN_rule, |
| 946 | /* 560 */ loadKlass_rule, |
| 947 | /* 561 */ loadNKlass_rule, |
| 948 | /* 562 */ loadF_rule, |
| 949 | /* 563 */ loadD_partial_rule, |
| 950 | /* 564 */ loadD_rule, |
| 951 | /* 565 */ maxF_reg_rule, |
| 952 | /* 566 */ maxF_reduction_reg_rule, |
| 953 | /* 567 */ maxD_reg_rule, |
| 954 | /* 568 */ maxD_reduction_reg_rule, |
| 955 | /* 569 */ minF_reg_rule, |
| 956 | /* 570 */ minF_reduction_reg_rule, |
| 957 | /* 571 */ minD_reg_rule, |
| 958 | /* 572 */ minD_reduction_reg_rule, |
| 959 | /* 573 */ prefetchAlloc_rule, |
| 960 | /* 574 */ prefetchAllocNTA_rule, |
| 961 | /* 575 */ prefetchAllocT0_rule, |
| 962 | /* 576 */ prefetchAllocT2_rule, |
| 963 | /* 577 */ storeB_rule, |
| 964 | /* 578 */ storeC_rule, |
| 965 | /* 579 */ storeI_rule, |
| 966 | /* 580 */ storeL_rule, |
| 967 | /* 581 */ storeP_rule, |
| 968 | /* 582 */ storeImmP0_rule, |
| 969 | /* 583 */ storeImmP_rule, |
| 970 | /* 584 */ storeN_rule, |
| 971 | /* 585 */ storeNKlass_rule, |
| 972 | /* 586 */ storeImmN0_rule, |
| 973 | /* 587 */ storeImmN_rule, |
| 974 | /* 588 */ storeImmNKlass_rule, |
| 975 | /* 589 */ storeImmI0_rule, |
| 976 | /* 590 */ storeImmI_rule, |
| 977 | /* 591 */ storeImmL0_rule, |
| 978 | /* 592 */ storeImmL_rule, |
| 979 | /* 593 */ storeImmC0_rule, |
| 980 | /* 594 */ storeImmI16_rule, |
| 981 | /* 595 */ storeImmB0_rule, |
| 982 | /* 596 */ storeImmB_rule, |
| 983 | /* 597 */ storeImmCM0_reg_rule, |
| 984 | /* 598 */ storeImmCM0_rule, |
| 985 | /* 599 */ storeF_rule, |
| 986 | /* 600 */ storeF0_rule, |
| 987 | /* 601 */ storeF_imm_rule, |
| 988 | /* 602 */ storeD_rule, |
| 989 | /* 603 */ storeD0_imm_rule, |
| 990 | /* 604 */ storeD0_rule, |
| 991 | /* 605 */ bytes_reverse_int_rule, |
| 992 | /* 606 */ bytes_reverse_long_rule, |
| 993 | /* 607 */ bytes_reverse_unsigned_short_rule, |
| 994 | /* 608 */ bytes_reverse_short_rule, |
| 995 | /* 609 */ countLeadingZerosI_rule, |
| 996 | /* 610 */ countLeadingZerosI_bsr_rule, |
| 997 | /* 611 */ countLeadingZerosL_rule, |
| 998 | /* 612 */ countLeadingZerosL_bsr_rule, |
| 999 | /* 613 */ countTrailingZerosI_rule, |
| 1000 | /* 614 */ countTrailingZerosI_bsf_rule, |
| 1001 | /* 615 */ countTrailingZerosL_rule, |
| 1002 | /* 616 */ countTrailingZerosL_bsf_rule, |
| 1003 | /* 617 */ popCountI_rule, |
| 1004 | /* 618 */ popCountI_mem_rule, |
| 1005 | /* 619 */ popCountL_rule, |
| 1006 | /* 620 */ popCountL_mem_rule, |
| 1007 | /* 621 */ membar_acquire_rule, |
| 1008 | /* 622 */ membar_acquire_0_rule, |
| 1009 | /* 623 */ membar_acquire_lock_rule, |
| 1010 | /* 624 */ membar_release_rule, |
| 1011 | /* 625 */ membar_release_0_rule, |
| 1012 | /* 626 */ membar_release_lock_rule, |
| 1013 | /* 627 */ unnecessary_membar_volatile_rule, |
| 1014 | /* 628 */ membar_storestore_rule, |
| 1015 | /* 629 */ convP2I_rule, |
| 1016 | /* 630 */ convN2I_rule, |
| 1017 | /* 631 */ encodeHeapOop_rule, |
| 1018 | /* 632 */ encodeHeapOop_not_null_rule, |
| 1019 | /* 633 */ decodeHeapOop_rule, |
| 1020 | /* 634 */ decodeHeapOop_not_null_rule, |
| 1021 | /* 635 */ encodeKlass_not_null_rule, |
| 1022 | /* 636 */ decodeKlass_not_null_rule, |
| 1023 | /* 637 */ jumpXtnd_offset_rule, |
| 1024 | /* 638 */ jumpXtnd_addr_rule, |
| 1025 | /* 639 */ jumpXtnd_rule, |
| 1026 | /* 640 */ cmovI_reg_rule, |
| 1027 | /* 641 */ cmovI_regU_rule, |
| 1028 | /* 642 */ cmovI_regUCF_rule, |
| 1029 | /* 643 */ cmovI_mem_rule, |
| 1030 | /* 644 */ cmovI_memU_rule, |
| 1031 | /* 645 */ cmovI_memUCF_rule, |
| 1032 | /* 646 */ cmovN_reg_rule, |
| 1033 | /* 647 */ cmovN_regU_rule, |
| 1034 | /* 648 */ cmovN_regUCF_rule, |
| 1035 | /* 649 */ cmovP_reg_rule, |
| 1036 | /* 650 */ cmovP_regU_rule, |
| 1037 | /* 651 */ cmovP_regUCF_rule, |
| 1038 | /* 652 */ cmovL_reg_rule, |
| 1039 | /* 653 */ cmovL_mem_rule, |
| 1040 | /* 654 */ cmovL_regU_rule, |
| 1041 | /* 655 */ cmovL_regUCF_rule, |
| 1042 | /* 656 */ cmovL_memU_rule, |
| 1043 | /* 657 */ cmovL_memUCF_rule, |
| 1044 | /* 658 */ cmovF_reg_rule, |
| 1045 | /* 659 */ cmovF_regU_rule, |
| 1046 | /* 660 */ cmovF_regUCF_rule, |
| 1047 | /* 661 */ cmovD_reg_rule, |
| 1048 | /* 662 */ cmovD_regU_rule, |
| 1049 | /* 663 */ cmovD_regUCF_rule, |
| 1050 | /* 664 */ addI_rReg_rule, |
| 1051 | /* 665 */ addI_rReg_imm_rule, |
| 1052 | /* 666 */ addI_rReg_mem_rule, |
| 1053 | /* 667 */ addI_rReg_mem_0_rule, |
| 1054 | /* 668 */ addI_mem_rReg_rule, |
| 1055 | /* 669 */ addI_mem_rReg_0_rule, |
| 1056 | /* 670 */ addI_mem_imm_rule, |
| 1057 | /* 671 */ incI_rReg_rule, |
| 1058 | /* 672 */ incI_mem_rule, |
| 1059 | /* 673 */ decI_rReg_rule, |
| 1060 | /* 674 */ decI_mem_rule, |
| 1061 | /* 675 */ leaI_rReg_immI_rule, |
| 1062 | /* 676 */ addL_rReg_rule, |
| 1063 | /* 677 */ addL_rReg_imm_rule, |
| 1064 | /* 678 */ addL_rReg_mem_rule, |
| 1065 | /* 679 */ addL_rReg_mem_0_rule, |
| 1066 | /* 680 */ addL_mem_rReg_rule, |
| 1067 | /* 681 */ addL_mem_rReg_0_rule, |
| 1068 | /* 682 */ addL_mem_imm_rule, |
| 1069 | /* 683 */ incL_rReg_rule, |
| 1070 | /* 684 */ incL_mem_rule, |
| 1071 | /* 685 */ decL_rReg_rule, |
| 1072 | /* 686 */ decL_mem_rule, |
| 1073 | /* 687 */ leaL_rReg_immL_rule, |
| 1074 | /* 688 */ addP_rReg_rule, |
| 1075 | /* 689 */ addP_rReg_imm_rule, |
| 1076 | /* 690 */ leaP_rReg_imm_rule, |
| 1077 | /* 691 */ loadPLocked_rule, |
| 1078 | /* 692 */ compareAndSwapP_rule, |
| 1079 | /* 693 */ compareAndSwapP_0_rule, |
| 1080 | /* 694 */ compareAndSwapL_rule, |
| 1081 | /* 695 */ compareAndSwapL_0_rule, |
| 1082 | /* 696 */ compareAndSwapI_rule, |
| 1083 | /* 697 */ compareAndSwapI_0_rule, |
| 1084 | /* 698 */ compareAndSwapB_rule, |
| 1085 | /* 699 */ compareAndSwapB_0_rule, |
| 1086 | /* 700 */ compareAndSwapS_rule, |
| 1087 | /* 701 */ compareAndSwapS_0_rule, |
| 1088 | /* 702 */ compareAndSwapN_rule, |
| 1089 | /* 703 */ compareAndSwapN_0_rule, |
| 1090 | /* 704 */ compareAndExchangeB_rule, |
| 1091 | /* 705 */ compareAndExchangeS_rule, |
| 1092 | /* 706 */ compareAndExchangeI_rule, |
| 1093 | /* 707 */ compareAndExchangeL_rule, |
| 1094 | /* 708 */ compareAndExchangeN_rule, |
| 1095 | /* 709 */ compareAndExchangeP_rule, |
| 1096 | /* 710 */ xaddB_no_res_rule, |
| 1097 | /* 711 */ xaddB_rule, |
| 1098 | /* 712 */ xaddS_no_res_rule, |
| 1099 | /* 713 */ xaddS_rule, |
| 1100 | /* 714 */ xaddI_no_res_rule, |
| 1101 | /* 715 */ xaddI_rule, |
| 1102 | /* 716 */ xaddL_no_res_rule, |
| 1103 | /* 717 */ xaddL_rule, |
| 1104 | /* 718 */ xchgB_rule, |
| 1105 | /* 719 */ xchgS_rule, |
| 1106 | /* 720 */ xchgI_rule, |
| 1107 | /* 721 */ xchgL_rule, |
| 1108 | /* 722 */ xchgP_rule, |
| 1109 | /* 723 */ xchgN_rule, |
| 1110 | /* 724 */ absI_rReg_rule, |
| 1111 | /* 725 */ absL_rReg_rule, |
| 1112 | /* 726 */ subI_rReg_rule, |
| 1113 | /* 727 */ subI_rReg_imm_rule, |
| 1114 | /* 728 */ subI_rReg_mem_rule, |
| 1115 | /* 729 */ subI_mem_rReg_rule, |
| 1116 | /* 730 */ subI_mem_imm_rule, |
| 1117 | /* 731 */ subL_rReg_rule, |
| 1118 | /* 732 */ subL_rReg_imm_rule, |
| 1119 | /* 733 */ subL_rReg_mem_rule, |
| 1120 | /* 734 */ subL_mem_rReg_rule, |
| 1121 | /* 735 */ subL_mem_imm_rule, |
| 1122 | /* 736 */ subP_rReg_rule, |
| 1123 | /* 737 */ negI_rReg_rule, |
| 1124 | /* 738 */ negI_mem_rule, |
| 1125 | /* 739 */ negL_rReg_rule, |
| 1126 | /* 740 */ negL_mem_rule, |
| 1127 | /* 741 */ mulI_rReg_rule, |
| 1128 | /* 742 */ mulI_rReg_imm_rule, |
| 1129 | /* 743 */ mulI_mem_rule, |
| 1130 | /* 744 */ mulI_mem_0_rule, |
| 1131 | /* 745 */ mulI_mem_imm_rule, |
| 1132 | /* 746 */ mulAddS2I_rReg_rule, |
| 1133 | /* 747 */ mulL_rReg_rule, |
| 1134 | /* 748 */ mulL_rReg_imm_rule, |
| 1135 | /* 749 */ mulL_mem_rule, |
| 1136 | /* 750 */ mulL_mem_0_rule, |
| 1137 | /* 751 */ mulL_mem_imm_rule, |
| 1138 | /* 752 */ mulHiL_rReg_rule, |
| 1139 | /* 753 */ divI_rReg_rule, |
| 1140 | /* 754 */ divL_rReg_rule, |
| 1141 | /* 755 */ divModI_rReg_divmod_rule, |
| 1142 | /* 756 */ divModL_rReg_divmod_rule, |
| 1143 | /* 757 */ loadConL_0x6666666666666667_rule, |
| 1144 | /* 758 */ mul_hi_rule, |
| 1145 | /* 759 */ sarL_rReg_63_rule, |
| 1146 | /* 760 */ sarL_rReg_2_rule, |
| 1147 | /* 761 */ divL_10_rule, |
| 1148 | /* 762 */ modI_rReg_rule, |
| 1149 | /* 763 */ modL_rReg_rule, |
| 1150 | /* 764 */ salI_rReg_1_rule, |
| 1151 | /* 765 */ salI_mem_1_rule, |
| 1152 | /* 766 */ salI_rReg_imm_rule, |
| 1153 | /* 767 */ salI_mem_imm_rule, |
| 1154 | /* 768 */ salI_rReg_CL_rule, |
| 1155 | /* 769 */ salI_mem_CL_rule, |
| 1156 | /* 770 */ sarI_rReg_1_rule, |
| 1157 | /* 771 */ sarI_mem_1_rule, |
| 1158 | /* 772 */ sarI_rReg_imm_rule, |
| 1159 | /* 773 */ sarI_mem_imm_rule, |
| 1160 | /* 774 */ sarI_rReg_CL_rule, |
| 1161 | /* 775 */ sarI_mem_CL_rule, |
| 1162 | /* 776 */ shrI_rReg_1_rule, |
| 1163 | /* 777 */ shrI_mem_1_rule, |
| 1164 | /* 778 */ shrI_rReg_imm_rule, |
| 1165 | /* 779 */ shrI_mem_imm_rule, |
| 1166 | /* 780 */ shrI_rReg_CL_rule, |
| 1167 | /* 781 */ shrI_mem_CL_rule, |
| 1168 | /* 782 */ salL_rReg_1_rule, |
| 1169 | /* 783 */ salL_mem_1_rule, |
| 1170 | /* 784 */ salL_rReg_imm_rule, |
| 1171 | /* 785 */ salL_mem_imm_rule, |
| 1172 | /* 786 */ salL_rReg_CL_rule, |
| 1173 | /* 787 */ salL_mem_CL_rule, |
| 1174 | /* 788 */ sarL_rReg_1_rule, |
| 1175 | /* 789 */ sarL_mem_1_rule, |
| 1176 | /* 790 */ sarL_rReg_imm_rule, |
| 1177 | /* 791 */ sarL_mem_imm_rule, |
| 1178 | /* 792 */ sarL_rReg_CL_rule, |
| 1179 | /* 793 */ sarL_mem_CL_rule, |
| 1180 | /* 794 */ shrL_rReg_1_rule, |
| 1181 | /* 795 */ shrL_mem_1_rule, |
| 1182 | /* 796 */ shrL_rReg_imm_rule, |
| 1183 | /* 797 */ shrL_mem_imm_rule, |
| 1184 | /* 798 */ shrL_rReg_CL_rule, |
| 1185 | /* 799 */ shrL_mem_CL_rule, |
| 1186 | /* 800 */ i2b_rule, |
| 1187 | /* 801 */ i2s_rule, |
| 1188 | /* 802 */ rolI_rReg_imm1_rule, |
| 1189 | /* 803 */ rolI_rReg_imm8_rule, |
| 1190 | /* 804 */ rolI_rReg_CL_rule, |
| 1191 | /* 805 */ rolI_rReg_i1_rule, |
| 1192 | /* 806 */ rolI_rReg_i1_0_rule, |
| 1193 | /* 807 */ rolI_rReg_i8_rule, |
| 1194 | /* 808 */ rolI_rReg_i8_0_rule, |
| 1195 | /* 809 */ rolI_rReg_Var_C0_rule, |
| 1196 | /* 810 */ rolI_rReg_Var_C0_0_rule, |
| 1197 | /* 811 */ rolI_rReg_Var_C32_rule, |
| 1198 | /* 812 */ rolI_rReg_Var_C32_0_rule, |
| 1199 | /* 813 */ rorI_rReg_imm1_rule, |
| 1200 | /* 814 */ rorI_rReg_imm8_rule, |
| 1201 | /* 815 */ rorI_rReg_CL_rule, |
| 1202 | /* 816 */ rorI_rReg_i1_rule, |
| 1203 | /* 817 */ rorI_rReg_i1_0_rule, |
| 1204 | /* 818 */ rorI_rReg_i8_rule, |
| 1205 | /* 819 */ rorI_rReg_i8_0_rule, |
| 1206 | /* 820 */ rorI_rReg_Var_C0_rule, |
| 1207 | /* 821 */ rorI_rReg_Var_C0_0_rule, |
| 1208 | /* 822 */ rorI_rReg_Var_C32_rule, |
| 1209 | /* 823 */ rorI_rReg_Var_C32_0_rule, |
| 1210 | /* 824 */ rolL_rReg_imm1_rule, |
| 1211 | /* 825 */ rolL_rReg_imm8_rule, |
| 1212 | /* 826 */ rolL_rReg_CL_rule, |
| 1213 | /* 827 */ rolL_rReg_i1_rule, |
| 1214 | /* 828 */ rolL_rReg_i1_0_rule, |
| 1215 | /* 829 */ rolL_rReg_i8_rule, |
| 1216 | /* 830 */ rolL_rReg_i8_0_rule, |
| 1217 | /* 831 */ rolL_rReg_Var_C0_rule, |
| 1218 | /* 832 */ rolL_rReg_Var_C0_0_rule, |
| 1219 | /* 833 */ rolL_rReg_Var_C64_rule, |
| 1220 | /* 834 */ rolL_rReg_Var_C64_0_rule, |
| 1221 | /* 835 */ rorL_rReg_imm1_rule, |
| 1222 | /* 836 */ rorL_rReg_imm8_rule, |
| 1223 | /* 837 */ rorL_rReg_CL_rule, |
| 1224 | /* 838 */ rorL_rReg_i1_rule, |
| 1225 | /* 839 */ rorL_rReg_i1_0_rule, |
| 1226 | /* 840 */ rorL_rReg_i8_rule, |
| 1227 | /* 841 */ rorL_rReg_i8_0_rule, |
| 1228 | /* 842 */ rorL_rReg_Var_C0_rule, |
| 1229 | /* 843 */ rorL_rReg_Var_C0_0_rule, |
| 1230 | /* 844 */ rorL_rReg_Var_C64_rule, |
| 1231 | /* 845 */ rorL_rReg_Var_C64_0_rule, |
| 1232 | /* 846 */ andI_rReg_rule, |
| 1233 | /* 847 */ andI_rReg_imm255_rule, |
| 1234 | /* 848 */ andI2L_rReg_imm255_rule, |
| 1235 | /* 849 */ andI_rReg_imm65535_rule, |
| 1236 | /* 850 */ andI2L_rReg_imm65535_rule, |
| 1237 | /* 851 */ andI_rReg_imm_rule, |
| 1238 | /* 852 */ andI_rReg_mem_rule, |
| 1239 | /* 853 */ andI_rReg_mem_0_rule, |
| 1240 | /* 854 */ andB_mem_rReg_rule, |
| 1241 | /* 855 */ andB_mem_rReg_0_rule, |
| 1242 | /* 856 */ andI_mem_rReg_rule, |
| 1243 | /* 857 */ andI_mem_rReg_0_rule, |
| 1244 | /* 858 */ andI_mem_imm_rule, |
| 1245 | /* 859 */ andnI_rReg_rReg_mem_rule, |
| 1246 | /* 860 */ andnI_rReg_rReg_mem_0_rule, |
| 1247 | /* 861 */ andnI_rReg_rReg_rReg_rule, |
| 1248 | /* 862 */ andnI_rReg_rReg_rReg_0_rule, |
| 1249 | /* 863 */ blsiI_rReg_rReg_rule, |
| 1250 | /* 864 */ blsiI_rReg_rReg_0_rule, |
| 1251 | /* 865 */ blsiI_rReg_mem_rule, |
| 1252 | /* 866 */ blsiI_rReg_mem_0_rule, |
| 1253 | /* 867 */ blsmskI_rReg_mem_rule, |
| 1254 | /* 868 */ blsmskI_rReg_mem_0_rule, |
| 1255 | /* 869 */ blsmskI_rReg_rReg_rule, |
| 1256 | /* 870 */ blsmskI_rReg_rReg_0_rule, |
| 1257 | /* 871 */ blsrI_rReg_rReg_rule, |
| 1258 | /* 872 */ blsrI_rReg_rReg_0_rule, |
| 1259 | /* 873 */ blsrI_rReg_mem_rule, |
| 1260 | /* 874 */ blsrI_rReg_mem_0_rule, |
| 1261 | /* 875 */ orI_rReg_rule, |
| 1262 | /* 876 */ orI_rReg_imm_rule, |
| 1263 | /* 877 */ orI_rReg_mem_rule, |
| 1264 | /* 878 */ orI_rReg_mem_0_rule, |
| 1265 | /* 879 */ orB_mem_rReg_rule, |
| 1266 | /* 880 */ orB_mem_rReg_0_rule, |
| 1267 | /* 881 */ orI_mem_rReg_rule, |
| 1268 | /* 882 */ orI_mem_rReg_0_rule, |
| 1269 | /* 883 */ orI_mem_imm_rule, |
| 1270 | /* 884 */ xorI_rReg_rule, |
| 1271 | /* 885 */ xorI_rReg_im1_rule, |
| 1272 | /* 886 */ xorI_rReg_imm_rule, |
| 1273 | /* 887 */ xorI_rReg_mem_rule, |
| 1274 | /* 888 */ xorI_rReg_mem_0_rule, |
| 1275 | /* 889 */ xorB_mem_rReg_rule, |
| 1276 | /* 890 */ xorB_mem_rReg_0_rule, |
| 1277 | /* 891 */ xorI_mem_rReg_rule, |
| 1278 | /* 892 */ xorI_mem_rReg_0_rule, |
| 1279 | /* 893 */ xorI_mem_imm_rule, |
| 1280 | /* 894 */ andL_rReg_rule, |
| 1281 | /* 895 */ andL_rReg_imm255_rule, |
| 1282 | /* 896 */ andL_rReg_imm65535_rule, |
| 1283 | /* 897 */ andL_rReg_imm_rule, |
| 1284 | /* 898 */ andL_rReg_mem_rule, |
| 1285 | /* 899 */ andL_rReg_mem_0_rule, |
| 1286 | /* 900 */ andL_mem_rReg_rule, |
| 1287 | /* 901 */ andL_mem_rReg_0_rule, |
| 1288 | /* 902 */ andL_mem_imm_rule, |
| 1289 | /* 903 */ andnL_rReg_rReg_mem_rule, |
| 1290 | /* 904 */ andnL_rReg_rReg_mem_0_rule, |
| 1291 | /* 905 */ andnL_rReg_rReg_rReg_rule, |
| 1292 | /* 906 */ andnL_rReg_rReg_rReg_0_rule, |
| 1293 | /* 907 */ blsiL_rReg_rReg_rule, |
| 1294 | /* 908 */ blsiL_rReg_rReg_0_rule, |
| 1295 | /* 909 */ blsiL_rReg_mem_rule, |
| 1296 | /* 910 */ blsiL_rReg_mem_0_rule, |
| 1297 | /* 911 */ blsmskL_rReg_mem_rule, |
| 1298 | /* 912 */ blsmskL_rReg_mem_0_rule, |
| 1299 | /* 913 */ blsmskL_rReg_rReg_rule, |
| 1300 | /* 914 */ blsmskL_rReg_rReg_0_rule, |
| 1301 | /* 915 */ blsrL_rReg_rReg_rule, |
| 1302 | /* 916 */ blsrL_rReg_rReg_0_rule, |
| 1303 | /* 917 */ blsrL_rReg_mem_rule, |
| 1304 | /* 918 */ blsrL_rReg_mem_0_rule, |
| 1305 | /* 919 */ orL_rReg_rule, |
| 1306 | /* 920 */ orL_rReg_castP2X_rule, |
| 1307 | /* 921 */ orL_rReg_castP2X_0_rule, |
| 1308 | /* 922 */ orL_rReg_imm_rule, |
| 1309 | /* 923 */ orL_rReg_mem_rule, |
| 1310 | /* 924 */ orL_rReg_mem_0_rule, |
| 1311 | /* 925 */ orL_mem_rReg_rule, |
| 1312 | /* 926 */ orL_mem_rReg_0_rule, |
| 1313 | /* 927 */ orL_mem_imm_rule, |
| 1314 | /* 928 */ xorL_rReg_rule, |
| 1315 | /* 929 */ xorL_rReg_im1_rule, |
| 1316 | /* 930 */ xorL_rReg_imm_rule, |
| 1317 | /* 931 */ xorL_rReg_mem_rule, |
| 1318 | /* 932 */ xorL_rReg_mem_0_rule, |
| 1319 | /* 933 */ xorL_mem_rReg_rule, |
| 1320 | /* 934 */ xorL_mem_rReg_0_rule, |
| 1321 | /* 935 */ xorL_mem_imm_rule, |
| 1322 | /* 936 */ convI2B_rule, |
| 1323 | /* 937 */ convP2B_rule, |
| 1324 | /* 938 */ cmpLTMask_rule, |
| 1325 | /* 939 */ cmpLTMask0_rule, |
| 1326 | /* 940 */ cadd_cmpLTMask_rule, |
| 1327 | /* 941 */ cadd_cmpLTMask_1_rule, |
| 1328 | /* 942 */ cadd_cmpLTMask_0_rule, |
| 1329 | /* 943 */ cadd_cmpLTMask_2_rule, |
| 1330 | /* 944 */ and_cmpLTMask_rule, |
| 1331 | /* 945 */ and_cmpLTMask_0_rule, |
| 1332 | /* 946 */ cmpF_reg_rule, |
| 1333 | /* 947 */ cmpF_mem_rule, |
| 1334 | /* 948 */ cmpF_imm_rule, |
| 1335 | /* 949 */ cmpD_reg_rule, |
| 1336 | /* 950 */ cmpD_mem_rule, |
| 1337 | /* 951 */ cmpD_imm_rule, |
| 1338 | /* 952 */ convF2D_reg_reg_rule, |
| 1339 | /* 953 */ convF2D_reg_mem_rule, |
| 1340 | /* 954 */ convD2F_reg_reg_rule, |
| 1341 | /* 955 */ convD2F_reg_mem_rule, |
| 1342 | /* 956 */ convF2I_reg_reg_rule, |
| 1343 | /* 957 */ convF2L_reg_reg_rule, |
| 1344 | /* 958 */ convD2I_reg_reg_rule, |
| 1345 | /* 959 */ convD2L_reg_reg_rule, |
| 1346 | /* 960 */ convI2F_reg_reg_rule, |
| 1347 | /* 961 */ convI2F_reg_mem_rule, |
| 1348 | /* 962 */ convI2D_reg_reg_rule, |
| 1349 | /* 963 */ convI2D_reg_mem_rule, |
| 1350 | /* 964 */ convXI2F_reg_rule, |
| 1351 | /* 965 */ convXI2D_reg_rule, |
| 1352 | /* 966 */ convL2F_reg_reg_rule, |
| 1353 | /* 967 */ convL2F_reg_mem_rule, |
| 1354 | /* 968 */ convL2D_reg_reg_rule, |
| 1355 | /* 969 */ convL2D_reg_mem_rule, |
| 1356 | /* 970 */ convI2L_reg_reg_rule, |
| 1357 | /* 971 */ convI2L_reg_reg_zex_rule, |
| 1358 | /* 972 */ convI2L_reg_mem_zex_rule, |
| 1359 | /* 973 */ zerox_long_reg_reg_rule, |
| 1360 | /* 974 */ convL2I_reg_reg_rule, |
| 1361 | /* 975 */ MoveF2I_reg_stack_rule, |
| 1362 | /* 976 */ MoveI2F_reg_stack_rule, |
| 1363 | /* 977 */ MoveD2L_reg_stack_rule, |
| 1364 | /* 978 */ MoveL2D_reg_stack_rule, |
| 1365 | /* 979 */ rep_stos_rule, |
| 1366 | /* 980 */ rep_stos_large_rule, |
| 1367 | /* 981 */ string_compareL_rule, |
| 1368 | /* 982 */ string_compareU_rule, |
| 1369 | /* 983 */ string_compareLU_rule, |
| 1370 | /* 984 */ string_compareUL_rule, |
| 1371 | /* 985 */ string_indexof_conL_rule, |
| 1372 | /* 986 */ string_indexof_conU_rule, |
| 1373 | /* 987 */ string_indexof_conUL_rule, |
| 1374 | /* 988 */ string_indexofL_rule, |
| 1375 | /* 989 */ string_indexofU_rule, |
| 1376 | /* 990 */ string_indexofUL_rule, |
| 1377 | /* 991 */ string_indexofU_char_rule, |
| 1378 | /* 992 */ string_equals_rule, |
| 1379 | /* 993 */ array_equalsB_rule, |
| 1380 | /* 994 */ array_equalsC_rule, |
| 1381 | /* 995 */ has_negatives_rule, |
| 1382 | /* 996 */ string_compress_rule, |
| 1383 | /* 997 */ string_inflate_rule, |
| 1384 | /* 998 */ encode_iso_array_rule, |
| 1385 | /* 999 */ cmpL3_reg_reg_rule, |
| 1386 | /* 1000 */ cmovI_reg_g_rule, |
| 1387 | /* 1001 */ minI_rReg_rule, |
| 1388 | /* 1002 */ cmovI_reg_l_rule, |
| 1389 | /* 1003 */ maxI_rReg_rule, |
| 1390 | /* 1004 */ jmpDir_rule, |
| 1391 | /* 1005 */ jmpCon_rule, |
| 1392 | /* 1006 */ jmpLoopEnd_rule, |
| 1393 | /* 1007 */ jmpLoopEndU_rule, |
| 1394 | /* 1008 */ jmpLoopEndUCF_rule, |
| 1395 | /* 1009 */ jmpLoopEnd_and_restoreMask_rule, |
| 1396 | /* 1010 */ jmpLoopEndU_and_restoreMask_rule, |
| 1397 | /* 1011 */ jmpLoopEndUCF_and_restoreMask_rule, |
| 1398 | /* 1012 */ jmpConU_rule, |
| 1399 | /* 1013 */ jmpConUCF_rule, |
| 1400 | /* 1014 */ jmpConUCF2_rule, |
| 1401 | /* 1015 */ partialSubtypeCheck_rule, |
| 1402 | /* 1016 */ jmpDir_short_rule, |
| 1403 | /* 1017 */ jmpCon_short_rule, |
| 1404 | /* 1018 */ jmpLoopEnd_short_rule, |
| 1405 | /* 1019 */ jmpLoopEndU_short_rule, |
| 1406 | /* 1020 */ jmpLoopEndUCF_short_rule, |
| 1407 | /* 1021 */ jmpConU_short_rule, |
| 1408 | /* 1022 */ jmpConUCF_short_rule, |
| 1409 | /* 1023 */ jmpConUCF2_short_rule, |
| 1410 | /* 1024 */ safePoint_poll_far_rule, |
| 1411 | /* 1025 */ safePoint_poll_tls_rule, |
| 1412 | /* 1026 */ CallStaticJavaDirect_rule, |
| 1413 | /* 1027 */ CallDynamicJavaDirect_rule, |
| 1414 | /* 1028 */ CallRuntimeDirect_rule, |
| 1415 | /* 1029 */ CallLeafDirect_rule, |
| 1416 | /* 1030 */ CallLeafNoFPDirect_rule, |
| 1417 | /* 1031 */ Ret_rule, |
| 1418 | /* 1032 */ TailCalljmpInd_rule, |
| 1419 | /* 1033 */ tailjmpInd_rule, |
| 1420 | /* 1034 */ CreateException_rule, |
| 1421 | /* 1035 */ RethrowException_rule, |
| 1422 | /* 1036 */ ShouldNotReachHere_rule, |
| 1423 | /* 1037 */ setMask_rule, |
| 1424 | /* 1038 */ addF_reg_rule, |
| 1425 | /* 1039 */ addF_mem_rule, |
| 1426 | /* 1040 */ addF_mem_0_rule, |
| 1427 | /* 1041 */ addF_imm_rule, |
| 1428 | /* 1042 */ addF_reg_reg_rule, |
| 1429 | /* 1043 */ addF_reg_mem_rule, |
| 1430 | /* 1044 */ addF_reg_mem_0_rule, |
| 1431 | /* 1045 */ addF_reg_imm_rule, |
| 1432 | /* 1046 */ addD_reg_rule, |
| 1433 | /* 1047 */ addD_mem_rule, |
| 1434 | /* 1048 */ addD_mem_0_rule, |
| 1435 | /* 1049 */ addD_imm_rule, |
| 1436 | /* 1050 */ addD_reg_reg_rule, |
| 1437 | /* 1051 */ addD_reg_mem_rule, |
| 1438 | /* 1052 */ addD_reg_mem_0_rule, |
| 1439 | /* 1053 */ addD_reg_imm_rule, |
| 1440 | /* 1054 */ subF_reg_rule, |
| 1441 | /* 1055 */ subF_mem_rule, |
| 1442 | /* 1056 */ subF_imm_rule, |
| 1443 | /* 1057 */ subF_reg_reg_rule, |
| 1444 | /* 1058 */ subF_reg_mem_rule, |
| 1445 | /* 1059 */ subF_reg_imm_rule, |
| 1446 | /* 1060 */ subD_reg_rule, |
| 1447 | /* 1061 */ subD_mem_rule, |
| 1448 | /* 1062 */ subD_imm_rule, |
| 1449 | /* 1063 */ subD_reg_reg_rule, |
| 1450 | /* 1064 */ subD_reg_mem_rule, |
| 1451 | /* 1065 */ subD_reg_imm_rule, |
| 1452 | /* 1066 */ mulF_reg_rule, |
| 1453 | /* 1067 */ mulF_mem_rule, |
| 1454 | /* 1068 */ mulF_mem_0_rule, |
| 1455 | /* 1069 */ mulF_imm_rule, |
| 1456 | /* 1070 */ mulF_reg_reg_rule, |
| 1457 | /* 1071 */ mulF_reg_mem_rule, |
| 1458 | /* 1072 */ mulF_reg_mem_0_rule, |
| 1459 | /* 1073 */ mulF_reg_imm_rule, |
| 1460 | /* 1074 */ mulD_reg_rule, |
| 1461 | /* 1075 */ mulD_mem_rule, |
| 1462 | /* 1076 */ mulD_mem_0_rule, |
| 1463 | /* 1077 */ mulD_imm_rule, |
| 1464 | /* 1078 */ mulD_reg_reg_rule, |
| 1465 | /* 1079 */ mulD_reg_mem_rule, |
| 1466 | /* 1080 */ mulD_reg_mem_0_rule, |
| 1467 | /* 1081 */ mulD_reg_imm_rule, |
| 1468 | /* 1082 */ divF_reg_rule, |
| 1469 | /* 1083 */ divF_mem_rule, |
| 1470 | /* 1084 */ divF_imm_rule, |
| 1471 | /* 1085 */ divF_reg_reg_rule, |
| 1472 | /* 1086 */ divF_reg_mem_rule, |
| 1473 | /* 1087 */ divF_reg_imm_rule, |
| 1474 | /* 1088 */ divD_reg_rule, |
| 1475 | /* 1089 */ divD_mem_rule, |
| 1476 | /* 1090 */ divD_imm_rule, |
| 1477 | /* 1091 */ divD_reg_reg_rule, |
| 1478 | /* 1092 */ divD_reg_mem_rule, |
| 1479 | /* 1093 */ divD_reg_imm_rule, |
| 1480 | /* 1094 */ sqrtF_reg_rule, |
| 1481 | /* 1095 */ sqrtF_mem_rule, |
| 1482 | /* 1096 */ sqrtF_imm_rule, |
| 1483 | /* 1097 */ sqrtD_reg_rule, |
| 1484 | /* 1098 */ sqrtD_mem_rule, |
| 1485 | /* 1099 */ sqrtD_imm_rule, |
| 1486 | /* 1100 */ onspinwait_rule, |
| 1487 | /* 1101 */ fmaD_reg_rule, |
| 1488 | /* 1102 */ fmaF_reg_rule, |
| 1489 | /* 1103 */ loadV4_rule, |
| 1490 | /* 1104 */ loadV8_rule, |
| 1491 | /* 1105 */ loadV16_rule, |
| 1492 | /* 1106 */ loadV32_rule, |
| 1493 | /* 1107 */ loadV64_dword_rule, |
| 1494 | /* 1108 */ loadV64_qword_rule, |
| 1495 | /* 1109 */ storeV4_rule, |
| 1496 | /* 1110 */ storeV8_rule, |
| 1497 | /* 1111 */ storeV16_rule, |
| 1498 | /* 1112 */ storeV32_rule, |
| 1499 | /* 1113 */ storeV64_dword_rule, |
| 1500 | /* 1114 */ storeV64_qword_rule, |
| 1501 | /* 1115 */ Repl16B_rule, |
| 1502 | /* 1116 */ Repl32B_rule, |
| 1503 | /* 1117 */ Repl64B_rule, |
| 1504 | /* 1118 */ Repl16B_imm_rule, |
| 1505 | /* 1119 */ Repl32B_imm_rule, |
| 1506 | /* 1120 */ Repl64B_imm_rule, |
| 1507 | /* 1121 */ Repl4S_rule, |
| 1508 | /* 1122 */ Repl4S_mem_rule, |
| 1509 | /* 1123 */ Repl8S_rule, |
| 1510 | /* 1124 */ Repl8S_mem_rule, |
| 1511 | /* 1125 */ Repl8S_imm_rule, |
| 1512 | /* 1126 */ Repl16S_rule, |
| 1513 | /* 1127 */ Repl16S_mem_rule, |
| 1514 | /* 1128 */ Repl16S_imm_rule, |
| 1515 | /* 1129 */ Repl32S_rule, |
| 1516 | /* 1130 */ Repl32S_mem_rule, |
| 1517 | /* 1131 */ Repl32S_imm_rule, |
| 1518 | /* 1132 */ Repl4I_rule, |
| 1519 | /* 1133 */ Repl4I_mem_rule, |
| 1520 | /* 1134 */ Repl8I_rule, |
| 1521 | /* 1135 */ Repl8I_mem_rule, |
| 1522 | /* 1136 */ Repl16I_rule, |
| 1523 | /* 1137 */ Repl16I_mem_rule, |
| 1524 | /* 1138 */ Repl4I_imm_rule, |
| 1525 | /* 1139 */ Repl8I_imm_rule, |
| 1526 | /* 1140 */ Repl16I_imm_rule, |
| 1527 | /* 1141 */ Repl2L_mem_rule, |
| 1528 | /* 1142 */ Repl4L_rule, |
| 1529 | /* 1143 */ Repl8L_rule, |
| 1530 | /* 1144 */ Repl4L_imm_rule, |
| 1531 | /* 1145 */ Repl8L_imm_rule, |
| 1532 | /* 1146 */ Repl4L_mem_rule, |
| 1533 | /* 1147 */ Repl8L_mem_rule, |
| 1534 | /* 1148 */ Repl2F_mem_rule, |
| 1535 | /* 1149 */ Repl4F_mem_rule, |
| 1536 | /* 1150 */ Repl8F_rule, |
| 1537 | /* 1151 */ Repl8F_mem_rule, |
| 1538 | /* 1152 */ Repl16F_rule, |
| 1539 | /* 1153 */ Repl16F_mem_rule, |
| 1540 | /* 1154 */ Repl2F_zero_rule, |
| 1541 | /* 1155 */ Repl4F_zero_rule, |
| 1542 | /* 1156 */ Repl8F_zero_rule, |
| 1543 | /* 1157 */ Repl2D_mem_rule, |
| 1544 | /* 1158 */ Repl4D_rule, |
| 1545 | /* 1159 */ Repl4D_mem_rule, |
| 1546 | /* 1160 */ Repl8D_rule, |
| 1547 | /* 1161 */ Repl8D_mem_rule, |
| 1548 | /* 1162 */ Repl2D_zero_rule, |
| 1549 | /* 1163 */ Repl4D_zero_rule, |
| 1550 | /* 1164 */ Repl4B_rule, |
| 1551 | /* 1165 */ Repl8B_rule, |
| 1552 | /* 1166 */ Repl4B_imm_rule, |
| 1553 | /* 1167 */ Repl8B_imm_rule, |
| 1554 | /* 1168 */ Repl4B_zero_rule, |
| 1555 | /* 1169 */ Repl8B_zero_rule, |
| 1556 | /* 1170 */ Repl16B_zero_rule, |
| 1557 | /* 1171 */ Repl32B_zero_rule, |
| 1558 | /* 1172 */ Repl2S_rule, |
| 1559 | /* 1173 */ Repl2S_imm_rule, |
| 1560 | /* 1174 */ Repl4S_imm_rule, |
| 1561 | /* 1175 */ Repl2S_zero_rule, |
| 1562 | /* 1176 */ Repl4S_zero_rule, |
| 1563 | /* 1177 */ Repl8S_zero_rule, |
| 1564 | /* 1178 */ Repl16S_zero_rule, |
| 1565 | /* 1179 */ Repl2I_rule, |
| 1566 | /* 1180 */ Repl2I_mem_rule, |
| 1567 | /* 1181 */ Repl2I_imm_rule, |
| 1568 | /* 1182 */ Repl2I_zero_rule, |
| 1569 | /* 1183 */ Repl4I_zero_rule, |
| 1570 | /* 1184 */ Repl8I_zero_rule, |
| 1571 | /* 1185 */ Repl2L_rule, |
| 1572 | /* 1186 */ Repl2L_imm_rule, |
| 1573 | /* 1187 */ Repl2L_zero_rule, |
| 1574 | /* 1188 */ Repl4L_zero_rule, |
| 1575 | /* 1189 */ Repl2F_rule, |
| 1576 | /* 1190 */ Repl4F_rule, |
| 1577 | /* 1191 */ Repl2D_rule, |
| 1578 | /* 1192 */ Repl4B_mem_evex_rule, |
| 1579 | /* 1193 */ Repl8B_mem_evex_rule, |
| 1580 | /* 1194 */ Repl16B_evex_rule, |
| 1581 | /* 1195 */ Repl16B_mem_evex_rule, |
| 1582 | /* 1196 */ Repl32B_evex_rule, |
| 1583 | /* 1197 */ Repl32B_mem_evex_rule, |
| 1584 | /* 1198 */ Repl64B_evex_rule, |
| 1585 | /* 1199 */ Repl64B_mem_evex_rule, |
| 1586 | /* 1200 */ Repl16B_imm_evex_rule, |
| 1587 | /* 1201 */ Repl32B_imm_evex_rule, |
| 1588 | /* 1202 */ Repl64B_imm_evex_rule, |
| 1589 | /* 1203 */ Repl64B_zero_evex_rule, |
| 1590 | /* 1204 */ Repl4S_evex_rule, |
| 1591 | /* 1205 */ Repl4S_mem_evex_rule, |
| 1592 | /* 1206 */ Repl8S_evex_rule, |
| 1593 | /* 1207 */ Repl8S_mem_evex_rule, |
| 1594 | /* 1208 */ Repl16S_evex_rule, |
| 1595 | /* 1209 */ Repl16S_mem_evex_rule, |
| 1596 | /* 1210 */ Repl32S_evex_rule, |
| 1597 | /* 1211 */ Repl32S_mem_evex_rule, |
| 1598 | /* 1212 */ Repl8S_imm_evex_rule, |
| 1599 | /* 1213 */ Repl16S_imm_evex_rule, |
| 1600 | /* 1214 */ Repl32S_imm_evex_rule, |
| 1601 | /* 1215 */ Repl32S_zero_evex_rule, |
| 1602 | /* 1216 */ Repl4I_evex_rule, |
| 1603 | /* 1217 */ Repl4I_mem_evex_rule, |
| 1604 | /* 1218 */ Repl8I_evex_rule, |
| 1605 | /* 1219 */ Repl8I_mem_evex_rule, |
| 1606 | /* 1220 */ Repl16I_evex_rule, |
| 1607 | /* 1221 */ Repl16I_mem_evex_rule, |
| 1608 | /* 1222 */ Repl4I_imm_evex_rule, |
| 1609 | /* 1223 */ Repl8I_imm_evex_rule, |
| 1610 | /* 1224 */ Repl16I_imm_evex_rule, |
| 1611 | /* 1225 */ Repl16I_zero_evex_rule, |
| 1612 | /* 1226 */ Repl4L_evex_rule, |
| 1613 | /* 1227 */ Repl8L_evex_rule, |
| 1614 | /* 1228 */ Repl4L_imm_evex_rule, |
| 1615 | /* 1229 */ Repl8L_imm_evex_rule, |
| 1616 | /* 1230 */ Repl2L_mem_evex_rule, |
| 1617 | /* 1231 */ Repl4L_mem_evex_rule, |
| 1618 | /* 1232 */ Repl8L_mem_evex_rule, |
| 1619 | /* 1233 */ Repl8L_zero_evex_rule, |
| 1620 | /* 1234 */ Repl8F_evex_rule, |
| 1621 | /* 1235 */ Repl8F_mem_evex_rule, |
| 1622 | /* 1236 */ Repl16F_evex_rule, |
| 1623 | /* 1237 */ Repl16F_mem_evex_rule, |
| 1624 | /* 1238 */ Repl2F_zero_evex_rule, |
| 1625 | /* 1239 */ Repl4F_zero_evex_rule, |
| 1626 | /* 1240 */ Repl8F_zero_evex_rule, |
| 1627 | /* 1241 */ Repl16F_zero_evex_rule, |
| 1628 | /* 1242 */ Repl4D_evex_rule, |
| 1629 | /* 1243 */ Repl4D_mem_evex_rule, |
| 1630 | /* 1244 */ Repl8D_evex_rule, |
| 1631 | /* 1245 */ Repl8D_mem_evex_rule, |
| 1632 | /* 1246 */ Repl2D_zero_evex_rule, |
| 1633 | /* 1247 */ Repl4D_zero_evex_rule, |
| 1634 | /* 1248 */ Repl8D_zero_evex_rule, |
| 1635 | /* 1249 */ rsadd2I_reduction_reg_rule, |
| 1636 | /* 1250 */ rvadd2I_reduction_reg_rule, |
| 1637 | /* 1251 */ rvadd2I_reduction_reg_evex_rule, |
| 1638 | /* 1252 */ rsadd4I_reduction_reg_rule, |
| 1639 | /* 1253 */ rvadd4I_reduction_reg_rule, |
| 1640 | /* 1254 */ rvadd4I_reduction_reg_evex_rule, |
| 1641 | /* 1255 */ rvadd8I_reduction_reg_rule, |
| 1642 | /* 1256 */ rvadd8I_reduction_reg_evex_rule, |
| 1643 | /* 1257 */ rvadd16I_reduction_reg_evex_rule, |
| 1644 | /* 1258 */ rvadd2L_reduction_reg_rule, |
| 1645 | /* 1259 */ rvadd4L_reduction_reg_rule, |
| 1646 | /* 1260 */ rvadd8L_reduction_reg_rule, |
| 1647 | /* 1261 */ rsadd2F_reduction_reg_rule, |
| 1648 | /* 1262 */ rvadd2F_reduction_reg_rule, |
| 1649 | /* 1263 */ rsadd4F_reduction_reg_rule, |
| 1650 | /* 1264 */ rvadd4F_reduction_reg_rule, |
| 1651 | /* 1265 */ radd8F_reduction_reg_rule, |
| 1652 | /* 1266 */ radd16F_reduction_reg_rule, |
| 1653 | /* 1267 */ rsadd2D_reduction_reg_rule, |
| 1654 | /* 1268 */ rvadd2D_reduction_reg_rule, |
| 1655 | /* 1269 */ rvadd4D_reduction_reg_rule, |
| 1656 | /* 1270 */ rvadd8D_reduction_reg_rule, |
| 1657 | /* 1271 */ rsmul2I_reduction_reg_rule, |
| 1658 | /* 1272 */ rvmul2I_reduction_reg_rule, |
| 1659 | /* 1273 */ rsmul4I_reduction_reg_rule, |
| 1660 | /* 1274 */ rvmul4I_reduction_reg_rule, |
| 1661 | /* 1275 */ rvmul8I_reduction_reg_rule, |
| 1662 | /* 1276 */ rvmul16I_reduction_reg_rule, |
| 1663 | /* 1277 */ rvmul2L_reduction_reg_rule, |
| 1664 | /* 1278 */ rvmul4L_reduction_reg_rule, |
| 1665 | /* 1279 */ rvmul8L_reduction_reg_rule, |
| 1666 | /* 1280 */ rsmul2F_reduction_rule, |
| 1667 | /* 1281 */ rvmul2F_reduction_reg_rule, |
| 1668 | /* 1282 */ rsmul4F_reduction_reg_rule, |
| 1669 | /* 1283 */ rvmul4F_reduction_reg_rule, |
| 1670 | /* 1284 */ rvmul8F_reduction_reg_rule, |
| 1671 | /* 1285 */ rvmul16F_reduction_reg_rule, |
| 1672 | /* 1286 */ rsmul2D_reduction_reg_rule, |
| 1673 | /* 1287 */ rvmul2D_reduction_reg_rule, |
| 1674 | /* 1288 */ rvmul4D_reduction_reg_rule, |
| 1675 | /* 1289 */ rvmul8D_reduction_reg_rule, |
| 1676 | /* 1290 */ vadd4B_rule, |
| 1677 | /* 1291 */ vadd4B_reg_rule, |
| 1678 | /* 1292 */ vadd4B_mem_rule, |
| 1679 | /* 1293 */ vadd4B_mem_0_rule, |
| 1680 | /* 1294 */ vadd8B_rule, |
| 1681 | /* 1295 */ vadd8B_reg_rule, |
| 1682 | /* 1296 */ vadd8B_mem_rule, |
| 1683 | /* 1297 */ vadd8B_mem_0_rule, |
| 1684 | /* 1298 */ vadd16B_rule, |
| 1685 | /* 1299 */ vadd16B_reg_rule, |
| 1686 | /* 1300 */ vadd16B_mem_rule, |
| 1687 | /* 1301 */ vadd16B_mem_0_rule, |
| 1688 | /* 1302 */ vadd32B_reg_rule, |
| 1689 | /* 1303 */ vadd32B_mem_rule, |
| 1690 | /* 1304 */ vadd32B_mem_0_rule, |
| 1691 | /* 1305 */ vadd64B_reg_rule, |
| 1692 | /* 1306 */ vadd64B_mem_rule, |
| 1693 | /* 1307 */ vadd64B_mem_0_rule, |
| 1694 | /* 1308 */ vadd2S_rule, |
| 1695 | /* 1309 */ vadd2S_reg_rule, |
| 1696 | /* 1310 */ vadd2S_mem_rule, |
| 1697 | /* 1311 */ vadd2S_mem_0_rule, |
| 1698 | /* 1312 */ vadd4S_rule, |
| 1699 | /* 1313 */ vadd4S_reg_rule, |
| 1700 | /* 1314 */ vadd4S_mem_rule, |
| 1701 | /* 1315 */ vadd4S_mem_0_rule, |
| 1702 | /* 1316 */ vadd8S_rule, |
| 1703 | /* 1317 */ vadd8S_reg_rule, |
| 1704 | /* 1318 */ vadd8S_mem_rule, |
| 1705 | /* 1319 */ vadd8S_mem_0_rule, |
| 1706 | /* 1320 */ vadd16S_reg_rule, |
| 1707 | /* 1321 */ vadd16S_mem_rule, |
| 1708 | /* 1322 */ vadd16S_mem_0_rule, |
| 1709 | /* 1323 */ vadd32S_reg_rule, |
| 1710 | /* 1324 */ vadd32S_mem_rule, |
| 1711 | /* 1325 */ vadd32S_mem_0_rule, |
| 1712 | /* 1326 */ vadd2I_rule, |
| 1713 | /* 1327 */ vadd2I_reg_rule, |
| 1714 | /* 1328 */ vadd2I_mem_rule, |
| 1715 | /* 1329 */ vadd2I_mem_0_rule, |
| 1716 | /* 1330 */ vadd4I_rule, |
| 1717 | /* 1331 */ vadd4I_reg_rule, |
| 1718 | /* 1332 */ vadd4I_mem_rule, |
| 1719 | /* 1333 */ vadd4I_mem_0_rule, |
| 1720 | /* 1334 */ vadd8I_reg_rule, |
| 1721 | /* 1335 */ vadd8I_mem_rule, |
| 1722 | /* 1336 */ vadd8I_mem_0_rule, |
| 1723 | /* 1337 */ vadd16I_reg_rule, |
| 1724 | /* 1338 */ vadd16I_mem_rule, |
| 1725 | /* 1339 */ vadd16I_mem_0_rule, |
| 1726 | /* 1340 */ vadd2L_rule, |
| 1727 | /* 1341 */ vadd2L_reg_rule, |
| 1728 | /* 1342 */ vadd2L_mem_rule, |
| 1729 | /* 1343 */ vadd2L_mem_0_rule, |
| 1730 | /* 1344 */ vadd4L_reg_rule, |
| 1731 | /* 1345 */ vadd4L_mem_rule, |
| 1732 | /* 1346 */ vadd4L_mem_0_rule, |
| 1733 | /* 1347 */ vadd8L_reg_rule, |
| 1734 | /* 1348 */ vadd8L_mem_rule, |
| 1735 | /* 1349 */ vadd8L_mem_0_rule, |
| 1736 | /* 1350 */ vadd2F_rule, |
| 1737 | /* 1351 */ vadd2F_reg_rule, |
| 1738 | /* 1352 */ vadd2F_mem_rule, |
| 1739 | /* 1353 */ vadd2F_mem_0_rule, |
| 1740 | /* 1354 */ vadd4F_rule, |
| 1741 | /* 1355 */ vadd4F_reg_rule, |
| 1742 | /* 1356 */ vadd4F_mem_rule, |
| 1743 | /* 1357 */ vadd4F_mem_0_rule, |
| 1744 | /* 1358 */ vadd8F_reg_rule, |
| 1745 | /* 1359 */ vadd8F_mem_rule, |
| 1746 | /* 1360 */ vadd8F_mem_0_rule, |
| 1747 | /* 1361 */ vadd16F_reg_rule, |
| 1748 | /* 1362 */ vadd16F_mem_rule, |
| 1749 | /* 1363 */ vadd16F_mem_0_rule, |
| 1750 | /* 1364 */ vadd2D_rule, |
| 1751 | /* 1365 */ vadd2D_reg_rule, |
| 1752 | /* 1366 */ vadd2D_mem_rule, |
| 1753 | /* 1367 */ vadd2D_mem_0_rule, |
| 1754 | /* 1368 */ vadd4D_reg_rule, |
| 1755 | /* 1369 */ vadd4D_mem_rule, |
| 1756 | /* 1370 */ vadd4D_mem_0_rule, |
| 1757 | /* 1371 */ vadd8D_reg_rule, |
| 1758 | /* 1372 */ vadd8D_mem_rule, |
| 1759 | /* 1373 */ vadd8D_mem_0_rule, |
| 1760 | /* 1374 */ vsub4B_rule, |
| 1761 | /* 1375 */ vsub4B_reg_rule, |
| 1762 | /* 1376 */ vsub4B_mem_rule, |
| 1763 | /* 1377 */ vsub8B_rule, |
| 1764 | /* 1378 */ vsub8B_reg_rule, |
| 1765 | /* 1379 */ vsub8B_mem_rule, |
| 1766 | /* 1380 */ vsub16B_rule, |
| 1767 | /* 1381 */ vsub16B_reg_rule, |
| 1768 | /* 1382 */ vsub16B_mem_rule, |
| 1769 | /* 1383 */ vsub32B_reg_rule, |
| 1770 | /* 1384 */ vsub32B_mem_rule, |
| 1771 | /* 1385 */ vsub64B_reg_rule, |
| 1772 | /* 1386 */ vsub64B_mem_rule, |
| 1773 | /* 1387 */ vsub2S_rule, |
| 1774 | /* 1388 */ vsub2S_reg_rule, |
| 1775 | /* 1389 */ vsub2S_mem_rule, |
| 1776 | /* 1390 */ vsub4S_rule, |
| 1777 | /* 1391 */ vsub4S_reg_rule, |
| 1778 | /* 1392 */ vsub4S_mem_rule, |
| 1779 | /* 1393 */ vsub8S_rule, |
| 1780 | /* 1394 */ vsub8S_reg_rule, |
| 1781 | /* 1395 */ vsub8S_mem_rule, |
| 1782 | /* 1396 */ vsub16S_reg_rule, |
| 1783 | /* 1397 */ vsub16S_mem_rule, |
| 1784 | /* 1398 */ vsub32S_reg_rule, |
| 1785 | /* 1399 */ vsub32S_mem_rule, |
| 1786 | /* 1400 */ vsub2I_rule, |
| 1787 | /* 1401 */ vsub2I_reg_rule, |
| 1788 | /* 1402 */ vsub2I_mem_rule, |
| 1789 | /* 1403 */ vsub4I_rule, |
| 1790 | /* 1404 */ vsub4I_reg_rule, |
| 1791 | /* 1405 */ vsub4I_mem_rule, |
| 1792 | /* 1406 */ vsub8I_reg_rule, |
| 1793 | /* 1407 */ vsub8I_mem_rule, |
| 1794 | /* 1408 */ vsub16I_reg_rule, |
| 1795 | /* 1409 */ vsub16I_mem_rule, |
| 1796 | /* 1410 */ vsub2L_rule, |
| 1797 | /* 1411 */ vsub2L_reg_rule, |
| 1798 | /* 1412 */ vsub2L_mem_rule, |
| 1799 | /* 1413 */ vsub4L_reg_rule, |
| 1800 | /* 1414 */ vsub4L_mem_rule, |
| 1801 | /* 1415 */ vsub8L_reg_rule, |
| 1802 | /* 1416 */ vsub8L_mem_rule, |
| 1803 | /* 1417 */ vsub2F_rule, |
| 1804 | /* 1418 */ vsub2F_reg_rule, |
| 1805 | /* 1419 */ vsub2F_mem_rule, |
| 1806 | /* 1420 */ vsub4F_rule, |
| 1807 | /* 1421 */ vsub4F_reg_rule, |
| 1808 | /* 1422 */ vsub4F_mem_rule, |
| 1809 | /* 1423 */ vsub8F_reg_rule, |
| 1810 | /* 1424 */ vsub8F_mem_rule, |
| 1811 | /* 1425 */ vsub16F_reg_rule, |
| 1812 | /* 1426 */ vsub16F_mem_rule, |
| 1813 | /* 1427 */ vsub2D_rule, |
| 1814 | /* 1428 */ vsub2D_reg_rule, |
| 1815 | /* 1429 */ vsub2D_mem_rule, |
| 1816 | /* 1430 */ vsub4D_reg_rule, |
| 1817 | /* 1431 */ vsub4D_mem_rule, |
| 1818 | /* 1432 */ vsub8D_reg_rule, |
| 1819 | /* 1433 */ vsub8D_mem_rule, |
| 1820 | /* 1434 */ mul4B_reg_rule, |
| 1821 | /* 1435 */ mul8B_reg_rule, |
| 1822 | /* 1436 */ mul16B_reg_rule, |
| 1823 | /* 1437 */ vmul16B_reg_avx_rule, |
| 1824 | /* 1438 */ vmul32B_reg_avx_rule, |
| 1825 | /* 1439 */ vmul64B_reg_avx_rule, |
| 1826 | /* 1440 */ vmul2S_rule, |
| 1827 | /* 1441 */ vmul2S_reg_rule, |
| 1828 | /* 1442 */ vmul2S_mem_rule, |
| 1829 | /* 1443 */ vmul2S_mem_0_rule, |
| 1830 | /* 1444 */ vmul4S_rule, |
| 1831 | /* 1445 */ vmul4S_reg_rule, |
| 1832 | /* 1446 */ vmul4S_mem_rule, |
| 1833 | /* 1447 */ vmul4S_mem_0_rule, |
| 1834 | /* 1448 */ vmul8S_rule, |
| 1835 | /* 1449 */ vmul8S_reg_rule, |
| 1836 | /* 1450 */ vmul8S_mem_rule, |
| 1837 | /* 1451 */ vmul8S_mem_0_rule, |
| 1838 | /* 1452 */ vmul16S_reg_rule, |
| 1839 | /* 1453 */ vmul16S_mem_rule, |
| 1840 | /* 1454 */ vmul16S_mem_0_rule, |
| 1841 | /* 1455 */ vmul32S_reg_rule, |
| 1842 | /* 1456 */ vmul32S_mem_rule, |
| 1843 | /* 1457 */ vmul32S_mem_0_rule, |
| 1844 | /* 1458 */ vmul2I_rule, |
| 1845 | /* 1459 */ vmul2I_reg_rule, |
| 1846 | /* 1460 */ vmul2I_mem_rule, |
| 1847 | /* 1461 */ vmul2I_mem_0_rule, |
| 1848 | /* 1462 */ vmul4I_rule, |
| 1849 | /* 1463 */ vmul4I_reg_rule, |
| 1850 | /* 1464 */ vmul4I_mem_rule, |
| 1851 | /* 1465 */ vmul4I_mem_0_rule, |
| 1852 | /* 1466 */ vmul2L_reg_rule, |
| 1853 | /* 1467 */ vmul2L_mem_rule, |
| 1854 | /* 1468 */ vmul2L_mem_0_rule, |
| 1855 | /* 1469 */ vmul4L_reg_rule, |
| 1856 | /* 1470 */ vmul4L_mem_rule, |
| 1857 | /* 1471 */ vmul4L_mem_0_rule, |
| 1858 | /* 1472 */ vmul8L_reg_rule, |
| 1859 | /* 1473 */ vmul8L_mem_rule, |
| 1860 | /* 1474 */ vmul8L_mem_0_rule, |
| 1861 | /* 1475 */ vmul8I_reg_rule, |
| 1862 | /* 1476 */ vmul8I_mem_rule, |
| 1863 | /* 1477 */ vmul8I_mem_0_rule, |
| 1864 | /* 1478 */ vmul16I_reg_rule, |
| 1865 | /* 1479 */ vmul16I_mem_rule, |
| 1866 | /* 1480 */ vmul16I_mem_0_rule, |
| 1867 | /* 1481 */ vmul2F_rule, |
| 1868 | /* 1482 */ vmul2F_reg_rule, |
| 1869 | /* 1483 */ vmul2F_mem_rule, |
| 1870 | /* 1484 */ vmul2F_mem_0_rule, |
| 1871 | /* 1485 */ vmul4F_rule, |
| 1872 | /* 1486 */ vmul4F_reg_rule, |
| 1873 | /* 1487 */ vmul4F_mem_rule, |
| 1874 | /* 1488 */ vmul4F_mem_0_rule, |
| 1875 | /* 1489 */ vmul8F_reg_rule, |
| 1876 | /* 1490 */ vmul8F_mem_rule, |
| 1877 | /* 1491 */ vmul8F_mem_0_rule, |
| 1878 | /* 1492 */ vmul16F_reg_rule, |
| 1879 | /* 1493 */ vmul16F_mem_rule, |
| 1880 | /* 1494 */ vmul16F_mem_0_rule, |
| 1881 | /* 1495 */ vmul2D_rule, |
| 1882 | /* 1496 */ vmul2D_reg_rule, |
| 1883 | /* 1497 */ vmul2D_mem_rule, |
| 1884 | /* 1498 */ vmul2D_mem_0_rule, |
| 1885 | /* 1499 */ vmul4D_reg_rule, |
| 1886 | /* 1500 */ vmul4D_mem_rule, |
| 1887 | /* 1501 */ vmul4D_mem_0_rule, |
| 1888 | /* 1502 */ vmul8D_reg_rule, |
| 1889 | /* 1503 */ vmul8D_mem_rule, |
| 1890 | /* 1504 */ vmul8D_mem_0_rule, |
| 1891 | /* 1505 */ vcmov8F_reg_rule, |
| 1892 | /* 1506 */ vcmov4D_reg_rule, |
| 1893 | /* 1507 */ vdiv2F_rule, |
| 1894 | /* 1508 */ vdiv2F_reg_rule, |
| 1895 | /* 1509 */ vdiv2F_mem_rule, |
| 1896 | /* 1510 */ vdiv4F_rule, |
| 1897 | /* 1511 */ vdiv4F_reg_rule, |
| 1898 | /* 1512 */ vdiv4F_mem_rule, |
| 1899 | /* 1513 */ vdiv8F_reg_rule, |
| 1900 | /* 1514 */ vdiv8F_mem_rule, |
| 1901 | /* 1515 */ vdiv16F_reg_rule, |
| 1902 | /* 1516 */ vdiv16F_mem_rule, |
| 1903 | /* 1517 */ vdiv2D_rule, |
| 1904 | /* 1518 */ vdiv2D_reg_rule, |
| 1905 | /* 1519 */ vdiv2D_mem_rule, |
| 1906 | /* 1520 */ vdiv4D_reg_rule, |
| 1907 | /* 1521 */ vdiv4D_mem_rule, |
| 1908 | /* 1522 */ vdiv8D_reg_rule, |
| 1909 | /* 1523 */ vdiv8D_mem_rule, |
| 1910 | /* 1524 */ vshift4B_rule, |
| 1911 | /* 1525 */ vshift4B_0_rule, |
| 1912 | /* 1526 */ vshift4B_1_rule, |
| 1913 | /* 1527 */ vshift8B_rule, |
| 1914 | /* 1528 */ vshift8B_0_rule, |
| 1915 | /* 1529 */ vshift8B_1_rule, |
| 1916 | /* 1530 */ vshift16B_rule, |
| 1917 | /* 1531 */ vshift16B_0_rule, |
| 1918 | /* 1532 */ vshift16B_1_rule, |
| 1919 | /* 1533 */ vshift16B_avx_rule, |
| 1920 | /* 1534 */ vshift16B_avx_0_rule, |
| 1921 | /* 1535 */ vshift16B_avx_1_rule, |
| 1922 | /* 1536 */ vshift32B_avx_rule, |
| 1923 | /* 1537 */ vshift32B_avx_0_rule, |
| 1924 | /* 1538 */ vshift32B_avx_1_rule, |
| 1925 | /* 1539 */ vshift64B_avx_rule, |
| 1926 | /* 1540 */ vshift64B_avx_0_rule, |
| 1927 | /* 1541 */ vshift64B_avx_1_rule, |
| 1928 | /* 1542 */ vshist2S_rule, |
| 1929 | /* 1543 */ vshist2S_0_rule, |
| 1930 | /* 1544 */ vshist2S_1_rule, |
| 1931 | /* 1545 */ vshift4S_rule, |
| 1932 | /* 1546 */ vshift4S_0_rule, |
| 1933 | /* 1547 */ vshift4S_1_rule, |
| 1934 | /* 1548 */ vshift8S_rule, |
| 1935 | /* 1549 */ vshift8S_0_rule, |
| 1936 | /* 1550 */ vshift8S_1_rule, |
| 1937 | /* 1551 */ vshift16S_rule, |
| 1938 | /* 1552 */ vshift16S_0_rule, |
| 1939 | /* 1553 */ vshift16S_1_rule, |
| 1940 | /* 1554 */ vshift32S_rule, |
| 1941 | /* 1555 */ vshift32S_0_rule, |
| 1942 | /* 1556 */ vshift32S_1_rule, |
| 1943 | /* 1557 */ vshift2I_rule, |
| 1944 | /* 1558 */ vshift2I_0_rule, |
| 1945 | /* 1559 */ vshift2I_1_rule, |
| 1946 | /* 1560 */ vshift4I_rule, |
| 1947 | /* 1561 */ vshift4I_0_rule, |
| 1948 | /* 1562 */ vshift4I_1_rule, |
| 1949 | /* 1563 */ vshift8I_rule, |
| 1950 | /* 1564 */ vshift8I_0_rule, |
| 1951 | /* 1565 */ vshift8I_1_rule, |
| 1952 | /* 1566 */ vshift16I_rule, |
| 1953 | /* 1567 */ vshift16I_0_rule, |
| 1954 | /* 1568 */ vshift16I_1_rule, |
| 1955 | /* 1569 */ vshift2L_rule, |
| 1956 | /* 1570 */ vshift2L_0_rule, |
| 1957 | /* 1571 */ vshift4L_rule, |
| 1958 | /* 1572 */ vshift4L_0_rule, |
| 1959 | /* 1573 */ vshift8L_rule, |
| 1960 | /* 1574 */ vshift8L_0_rule, |
| 1961 | /* 1575 */ vshift8L_1_rule, |
| 1962 | /* 1576 */ vsra2L_reg_rule, |
| 1963 | /* 1577 */ vsra2L_reg_evex_rule, |
| 1964 | /* 1578 */ vsra4L_reg_rule, |
| 1965 | /* 1579 */ vsra4L_reg_evex_rule, |
| 1966 | /* 1580 */ vand4B_rule, |
| 1967 | /* 1581 */ vand4B_reg_rule, |
| 1968 | /* 1582 */ vand4B_mem_rule, |
| 1969 | /* 1583 */ vand4B_mem_0_rule, |
| 1970 | /* 1584 */ vand8B_rule, |
| 1971 | /* 1585 */ vand8B_reg_rule, |
| 1972 | /* 1586 */ vand8B_mem_rule, |
| 1973 | /* 1587 */ vand8B_mem_0_rule, |
| 1974 | /* 1588 */ vand16B_rule, |
| 1975 | /* 1589 */ vand16B_reg_rule, |
| 1976 | /* 1590 */ vand16B_mem_rule, |
| 1977 | /* 1591 */ vand16B_mem_0_rule, |
| 1978 | /* 1592 */ vand32B_reg_rule, |
| 1979 | /* 1593 */ vand32B_mem_rule, |
| 1980 | /* 1594 */ vand32B_mem_0_rule, |
| 1981 | /* 1595 */ vand64B_reg_rule, |
| 1982 | /* 1596 */ vand64B_mem_rule, |
| 1983 | /* 1597 */ vand64B_mem_0_rule, |
| 1984 | /* 1598 */ vor4B_rule, |
| 1985 | /* 1599 */ vor4B_reg_rule, |
| 1986 | /* 1600 */ vor4B_mem_rule, |
| 1987 | /* 1601 */ vor4B_mem_0_rule, |
| 1988 | /* 1602 */ vor8B_rule, |
| 1989 | /* 1603 */ vor8B_reg_rule, |
| 1990 | /* 1604 */ vor8B_mem_rule, |
| 1991 | /* 1605 */ vor8B_mem_0_rule, |
| 1992 | /* 1606 */ vor16B_rule, |
| 1993 | /* 1607 */ vor16B_reg_rule, |
| 1994 | /* 1608 */ vor16B_mem_rule, |
| 1995 | /* 1609 */ vor16B_mem_0_rule, |
| 1996 | /* 1610 */ vor32B_reg_rule, |
| 1997 | /* 1611 */ vor32B_mem_rule, |
| 1998 | /* 1612 */ vor32B_mem_0_rule, |
| 1999 | /* 1613 */ vor64B_reg_rule, |
| 2000 | /* 1614 */ vor64B_mem_rule, |
| 2001 | /* 1615 */ vor64B_mem_0_rule, |
| 2002 | /* 1616 */ vxor4B_rule, |
| 2003 | /* 1617 */ vxor4B_reg_rule, |
| 2004 | /* 1618 */ vxor4B_mem_rule, |
| 2005 | /* 1619 */ vxor4B_mem_0_rule, |
| 2006 | /* 1620 */ vxor8B_rule, |
| 2007 | /* 1621 */ vxor8B_reg_rule, |
| 2008 | /* 1622 */ vxor8B_mem_rule, |
| 2009 | /* 1623 */ vxor8B_mem_0_rule, |
| 2010 | /* 1624 */ vxor16B_rule, |
| 2011 | /* 1625 */ vxor16B_reg_rule, |
| 2012 | /* 1626 */ vxor16B_mem_rule, |
| 2013 | /* 1627 */ vxor16B_mem_0_rule, |
| 2014 | /* 1628 */ vxor32B_reg_rule, |
| 2015 | /* 1629 */ vxor32B_mem_rule, |
| 2016 | /* 1630 */ vxor32B_mem_0_rule, |
| 2017 | /* 1631 */ vxor64B_reg_rule, |
| 2018 | /* 1632 */ vxor64B_mem_rule, |
| 2019 | /* 1633 */ vxor64B_mem_0_rule, |
| 2020 | /* 1634 */ vabsneg2D_rule, |
| 2021 | /* 1635 */ vabsneg2D_0_rule, |
| 2022 | /* 1636 */ vabsneg4D_rule, |
| 2023 | /* 1637 */ vabsneg4D_0_rule, |
| 2024 | /* 1638 */ vabsneg8D_rule, |
| 2025 | /* 1639 */ vabsneg8D_0_rule, |
| 2026 | /* 1640 */ vabsneg2F_rule, |
| 2027 | /* 1641 */ vabsneg2F_0_rule, |
| 2028 | /* 1642 */ vabsneg4F_rule, |
| 2029 | /* 1643 */ vabsneg4F_0_rule, |
| 2030 | /* 1644 */ vabsneg8F_rule, |
| 2031 | /* 1645 */ vabsneg8F_0_rule, |
| 2032 | /* 1646 */ vabsneg16F_rule, |
| 2033 | /* 1647 */ vabsneg16F_0_rule, |
| 2034 | /* 1648 */ vfma2D_reg_rule, |
| 2035 | /* 1649 */ vfma2D_mem_rule, |
| 2036 | /* 1650 */ vfma4D_reg_rule, |
| 2037 | /* 1651 */ vfma4D_mem_rule, |
| 2038 | /* 1652 */ vfma8D_reg_rule, |
| 2039 | /* 1653 */ vfma8D_mem_rule, |
| 2040 | /* 1654 */ vfma4F_reg_rule, |
| 2041 | /* 1655 */ vfma4F_mem_rule, |
| 2042 | /* 1656 */ vfma8F_reg_rule, |
| 2043 | /* 1657 */ vfma8F_mem_rule, |
| 2044 | /* 1658 */ vfma16F_reg_rule, |
| 2045 | /* 1659 */ vfma16F_mem_rule, |
| 2046 | /* 1660 */ smuladd4S2I_reg_rule, |
| 2047 | /* 1661 */ vmuladd4S2I_reg_rule, |
| 2048 | /* 1662 */ smuladd8S4I_reg_rule, |
| 2049 | /* 1663 */ vmuladd8S4I_reg_rule, |
| 2050 | /* 1664 */ vmuladd16S8I_reg_rule, |
| 2051 | /* 1665 */ vmuladd32S16I_reg_rule, |
| 2052 | /* 1666 */ vmuladdadd4S2I_reg_rule, |
| 2053 | /* 1667 */ vmuladdadd4S2I_reg_0_rule, |
| 2054 | /* 1668 */ vmuladdadd8S4I_reg_rule, |
| 2055 | /* 1669 */ vmuladdadd8S4I_reg_0_rule, |
| 2056 | /* 1670 */ vmuladdadd16S8I_reg_rule, |
| 2057 | /* 1671 */ vmuladdadd16S8I_reg_0_rule, |
| 2058 | /* 1672 */ vmuladdadd32S16I_reg_rule, |
| 2059 | /* 1673 */ vmuladdadd32S16I_reg_0_rule, |
| 2060 | /* 1674 */ compareAndSwapP_shenandoah_rule, |
| 2061 | /* 1675 */ compareAndSwapP_shenandoah_0_rule, |
| 2062 | /* 1676 */ compareAndSwapN_shenandoah_rule, |
| 2063 | /* 1677 */ compareAndSwapN_shenandoah_0_rule, |
| 2064 | /* 1678 */ compareAndExchangeN_shenandoah_rule, |
| 2065 | /* 1679 */ compareAndExchangeP_shenandoah_rule, |
| 2066 | /* 1680 */ zLoadBarrierSlowRegXmmAndYmm_rule, |
| 2067 | /* 1681 */ zLoadBarrierSlowRegZmm_rule, |
| 2068 | /* 1682 */ zLoadBarrierWeakSlowRegXmmAndYmm_rule, |
| 2069 | /* 1683 */ zLoadBarrierWeakSlowRegZmm_rule, |
| 2070 | /* 1684 */ z_compareAndExchangeP_rule, |
| 2071 | /* 1685 */ z_compareAndSwapP_rule, |
| 2072 | /* 1686 */ z_compareAndSwapP_0_rule, |
| 2073 | /* 1687 */ z_xchgP_rule, |
| 2074 | // last instruction |
| 2075 | _BEGIN_INST_CHAIN_RULE = 333, |
| 2076 | _END_INST_CHAIN_RULE = 394, |
| 2077 | _BEGIN_REMATERIALIZE = 338, |
| 2078 | _END_REMATERIALIZE = 533, |
| 2079 | _last_Mach_Node = 1688 |
| 2080 | }; |
| 2081 | |
| 2082 | // Enumerate machine registers starting after reserved regs. |
| 2083 | // in the order of occurrence in the alloc_class(es). |
| 2084 | enum MachRegisterEncodes { |
| 2085 | R10_enc = 10, |
| 2086 | R10_H_enc = 10, |
| 2087 | R11_enc = 11, |
| 2088 | R11_H_enc = 11, |
| 2089 | R8_enc = 8, |
| 2090 | R8_H_enc = 8, |
| 2091 | R9_enc = 9, |
| 2092 | R9_H_enc = 9, |
| 2093 | R12_enc = 12, |
| 2094 | R12_H_enc = 12, |
| 2095 | RCX_enc = 1, |
| 2096 | RCX_H_enc = 1, |
| 2097 | RBX_enc = 3, |
| 2098 | RBX_H_enc = 3, |
| 2099 | RDI_enc = 7, |
| 2100 | RDI_H_enc = 7, |
| 2101 | RDX_enc = 2, |
| 2102 | RDX_H_enc = 2, |
| 2103 | RSI_enc = 6, |
| 2104 | RSI_H_enc = 6, |
| 2105 | RAX_enc = 0, |
| 2106 | RAX_H_enc = 0, |
| 2107 | RBP_enc = 5, |
| 2108 | RBP_H_enc = 5, |
| 2109 | R13_enc = 13, |
| 2110 | R13_H_enc = 13, |
| 2111 | R14_enc = 14, |
| 2112 | R14_H_enc = 14, |
| 2113 | R15_enc = 15, |
| 2114 | R15_H_enc = 15, |
| 2115 | RSP_enc = 4, |
| 2116 | RSP_H_enc = 4, |
| 2117 | XMM0_enc = 0, |
| 2118 | XMM0b_enc = 0, |
| 2119 | XMM0c_enc = 0, |
| 2120 | XMM0d_enc = 0, |
| 2121 | XMM0e_enc = 0, |
| 2122 | XMM0f_enc = 0, |
| 2123 | XMM0g_enc = 0, |
| 2124 | XMM0h_enc = 0, |
| 2125 | XMM0i_enc = 0, |
| 2126 | XMM0j_enc = 0, |
| 2127 | XMM0k_enc = 0, |
| 2128 | XMM0l_enc = 0, |
| 2129 | XMM0m_enc = 0, |
| 2130 | XMM0n_enc = 0, |
| 2131 | XMM0o_enc = 0, |
| 2132 | XMM0p_enc = 0, |
| 2133 | XMM1_enc = 1, |
| 2134 | XMM1b_enc = 1, |
| 2135 | XMM1c_enc = 1, |
| 2136 | XMM1d_enc = 1, |
| 2137 | XMM1e_enc = 1, |
| 2138 | XMM1f_enc = 1, |
| 2139 | XMM1g_enc = 1, |
| 2140 | XMM1h_enc = 1, |
| 2141 | XMM1i_enc = 1, |
| 2142 | XMM1j_enc = 1, |
| 2143 | XMM1k_enc = 1, |
| 2144 | XMM1l_enc = 1, |
| 2145 | XMM1m_enc = 1, |
| 2146 | XMM1n_enc = 1, |
| 2147 | XMM1o_enc = 1, |
| 2148 | XMM1p_enc = 1, |
| 2149 | XMM2_enc = 2, |
| 2150 | XMM2b_enc = 2, |
| 2151 | XMM2c_enc = 2, |
| 2152 | XMM2d_enc = 2, |
| 2153 | XMM2e_enc = 2, |
| 2154 | XMM2f_enc = 2, |
| 2155 | XMM2g_enc = 2, |
| 2156 | XMM2h_enc = 2, |
| 2157 | XMM2i_enc = 2, |
| 2158 | XMM2j_enc = 2, |
| 2159 | XMM2k_enc = 2, |
| 2160 | XMM2l_enc = 2, |
| 2161 | XMM2m_enc = 2, |
| 2162 | XMM2n_enc = 2, |
| 2163 | XMM2o_enc = 2, |
| 2164 | XMM2p_enc = 2, |
| 2165 | XMM3_enc = 3, |
| 2166 | XMM3b_enc = 3, |
| 2167 | XMM3c_enc = 3, |
| 2168 | XMM3d_enc = 3, |
| 2169 | XMM3e_enc = 3, |
| 2170 | XMM3f_enc = 3, |
| 2171 | XMM3g_enc = 3, |
| 2172 | XMM3h_enc = 3, |
| 2173 | XMM3i_enc = 3, |
| 2174 | XMM3j_enc = 3, |
| 2175 | XMM3k_enc = 3, |
| 2176 | XMM3l_enc = 3, |
| 2177 | XMM3m_enc = 3, |
| 2178 | XMM3n_enc = 3, |
| 2179 | XMM3o_enc = 3, |
| 2180 | XMM3p_enc = 3, |
| 2181 | XMM4_enc = 4, |
| 2182 | XMM4b_enc = 4, |
| 2183 | XMM4c_enc = 4, |
| 2184 | XMM4d_enc = 4, |
| 2185 | XMM4e_enc = 4, |
| 2186 | XMM4f_enc = 4, |
| 2187 | XMM4g_enc = 4, |
| 2188 | XMM4h_enc = 4, |
| 2189 | XMM4i_enc = 4, |
| 2190 | XMM4j_enc = 4, |
| 2191 | XMM4k_enc = 4, |
| 2192 | XMM4l_enc = 4, |
| 2193 | XMM4m_enc = 4, |
| 2194 | XMM4n_enc = 4, |
| 2195 | XMM4o_enc = 4, |
| 2196 | XMM4p_enc = 4, |
| 2197 | XMM5_enc = 5, |
| 2198 | XMM5b_enc = 5, |
| 2199 | XMM5c_enc = 5, |
| 2200 | XMM5d_enc = 5, |
| 2201 | XMM5e_enc = 5, |
| 2202 | XMM5f_enc = 5, |
| 2203 | XMM5g_enc = 5, |
| 2204 | XMM5h_enc = 5, |
| 2205 | XMM5i_enc = 5, |
| 2206 | XMM5j_enc = 5, |
| 2207 | XMM5k_enc = 5, |
| 2208 | XMM5l_enc = 5, |
| 2209 | XMM5m_enc = 5, |
| 2210 | XMM5n_enc = 5, |
| 2211 | XMM5o_enc = 5, |
| 2212 | XMM5p_enc = 5, |
| 2213 | XMM6_enc = 6, |
| 2214 | XMM6b_enc = 6, |
| 2215 | XMM6c_enc = 6, |
| 2216 | XMM6d_enc = 6, |
| 2217 | XMM6e_enc = 6, |
| 2218 | XMM6f_enc = 6, |
| 2219 | XMM6g_enc = 6, |
| 2220 | XMM6h_enc = 6, |
| 2221 | XMM6i_enc = 6, |
| 2222 | XMM6j_enc = 6, |
| 2223 | XMM6k_enc = 6, |
| 2224 | XMM6l_enc = 6, |
| 2225 | XMM6m_enc = 6, |
| 2226 | XMM6n_enc = 6, |
| 2227 | XMM6o_enc = 6, |
| 2228 | XMM6p_enc = 6, |
| 2229 | XMM7_enc = 7, |
| 2230 | XMM7b_enc = 7, |
| 2231 | XMM7c_enc = 7, |
| 2232 | XMM7d_enc = 7, |
| 2233 | XMM7e_enc = 7, |
| 2234 | XMM7f_enc = 7, |
| 2235 | XMM7g_enc = 7, |
| 2236 | XMM7h_enc = 7, |
| 2237 | XMM7i_enc = 7, |
| 2238 | XMM7j_enc = 7, |
| 2239 | XMM7k_enc = 7, |
| 2240 | XMM7l_enc = 7, |
| 2241 | XMM7m_enc = 7, |
| 2242 | XMM7n_enc = 7, |
| 2243 | XMM7o_enc = 7, |
| 2244 | XMM7p_enc = 7, |
| 2245 | XMM8_enc = 8, |
| 2246 | XMM8b_enc = 8, |
| 2247 | XMM8c_enc = 8, |
| 2248 | XMM8d_enc = 8, |
| 2249 | XMM8e_enc = 8, |
| 2250 | XMM8f_enc = 8, |
| 2251 | XMM8g_enc = 8, |
| 2252 | XMM8h_enc = 8, |
| 2253 | XMM8i_enc = 8, |
| 2254 | XMM8j_enc = 8, |
| 2255 | XMM8k_enc = 8, |
| 2256 | XMM8l_enc = 8, |
| 2257 | XMM8m_enc = 8, |
| 2258 | XMM8n_enc = 8, |
| 2259 | XMM8o_enc = 8, |
| 2260 | XMM8p_enc = 8, |
| 2261 | XMM9_enc = 9, |
| 2262 | XMM9b_enc = 9, |
| 2263 | XMM9c_enc = 9, |
| 2264 | XMM9d_enc = 9, |
| 2265 | XMM9e_enc = 9, |
| 2266 | XMM9f_enc = 9, |
| 2267 | XMM9g_enc = 9, |
| 2268 | XMM9h_enc = 9, |
| 2269 | XMM9i_enc = 9, |
| 2270 | XMM9j_enc = 9, |
| 2271 | XMM9k_enc = 9, |
| 2272 | XMM9l_enc = 9, |
| 2273 | XMM9m_enc = 9, |
| 2274 | XMM9n_enc = 9, |
| 2275 | XMM9o_enc = 9, |
| 2276 | XMM9p_enc = 9, |
| 2277 | XMM10_enc = 10, |
| 2278 | XMM10b_enc = 10, |
| 2279 | XMM10c_enc = 10, |
| 2280 | XMM10d_enc = 10, |
| 2281 | XMM10e_enc = 10, |
| 2282 | XMM10f_enc = 10, |
| 2283 | XMM10g_enc = 10, |
| 2284 | XMM10h_enc = 10, |
| 2285 | XMM10i_enc = 10, |
| 2286 | XMM10j_enc = 10, |
| 2287 | XMM10k_enc = 10, |
| 2288 | XMM10l_enc = 10, |
| 2289 | XMM10m_enc = 10, |
| 2290 | XMM10n_enc = 10, |
| 2291 | XMM10o_enc = 10, |
| 2292 | XMM10p_enc = 10, |
| 2293 | XMM11_enc = 11, |
| 2294 | XMM11b_enc = 11, |
| 2295 | XMM11c_enc = 11, |
| 2296 | XMM11d_enc = 11, |
| 2297 | XMM11e_enc = 11, |
| 2298 | XMM11f_enc = 11, |
| 2299 | XMM11g_enc = 11, |
| 2300 | XMM11h_enc = 11, |
| 2301 | XMM11i_enc = 11, |
| 2302 | XMM11j_enc = 11, |
| 2303 | XMM11k_enc = 11, |
| 2304 | XMM11l_enc = 11, |
| 2305 | XMM11m_enc = 11, |
| 2306 | XMM11n_enc = 11, |
| 2307 | XMM11o_enc = 11, |
| 2308 | XMM11p_enc = 11, |
| 2309 | XMM12_enc = 12, |
| 2310 | XMM12b_enc = 12, |
| 2311 | XMM12c_enc = 12, |
| 2312 | XMM12d_enc = 12, |
| 2313 | XMM12e_enc = 12, |
| 2314 | XMM12f_enc = 12, |
| 2315 | XMM12g_enc = 12, |
| 2316 | XMM12h_enc = 12, |
| 2317 | XMM12i_enc = 12, |
| 2318 | XMM12j_enc = 12, |
| 2319 | XMM12k_enc = 12, |
| 2320 | XMM12l_enc = 12, |
| 2321 | XMM12m_enc = 12, |
| 2322 | XMM12n_enc = 12, |
| 2323 | XMM12o_enc = 12, |
| 2324 | XMM12p_enc = 12, |
| 2325 | XMM13_enc = 13, |
| 2326 | XMM13b_enc = 13, |
| 2327 | XMM13c_enc = 13, |
| 2328 | XMM13d_enc = 13, |
| 2329 | XMM13e_enc = 13, |
| 2330 | XMM13f_enc = 13, |
| 2331 | XMM13g_enc = 13, |
| 2332 | XMM13h_enc = 13, |
| 2333 | XMM13i_enc = 13, |
| 2334 | XMM13j_enc = 13, |
| 2335 | XMM13k_enc = 13, |
| 2336 | XMM13l_enc = 13, |
| 2337 | XMM13m_enc = 13, |
| 2338 | XMM13n_enc = 13, |
| 2339 | XMM13o_enc = 13, |
| 2340 | XMM13p_enc = 13, |
| 2341 | XMM14_enc = 14, |
| 2342 | XMM14b_enc = 14, |
| 2343 | XMM14c_enc = 14, |
| 2344 | XMM14d_enc = 14, |
| 2345 | XMM14e_enc = 14, |
| 2346 | XMM14f_enc = 14, |
| 2347 | XMM14g_enc = 14, |
| 2348 | XMM14h_enc = 14, |
| 2349 | XMM14i_enc = 14, |
| 2350 | XMM14j_enc = 14, |
| 2351 | XMM14k_enc = 14, |
| 2352 | XMM14l_enc = 14, |
| 2353 | XMM14m_enc = 14, |
| 2354 | XMM14n_enc = 14, |
| 2355 | XMM14o_enc = 14, |
| 2356 | XMM14p_enc = 14, |
| 2357 | XMM15_enc = 15, |
| 2358 | XMM15b_enc = 15, |
| 2359 | XMM15c_enc = 15, |
| 2360 | XMM15d_enc = 15, |
| 2361 | XMM15e_enc = 15, |
| 2362 | XMM15f_enc = 15, |
| 2363 | XMM15g_enc = 15, |
| 2364 | XMM15h_enc = 15, |
| 2365 | XMM15i_enc = 15, |
| 2366 | XMM15j_enc = 15, |
| 2367 | XMM15k_enc = 15, |
| 2368 | XMM15l_enc = 15, |
| 2369 | XMM15m_enc = 15, |
| 2370 | XMM15n_enc = 15, |
| 2371 | XMM15o_enc = 15, |
| 2372 | XMM15p_enc = 15, |
| 2373 | XMM16_enc = 16, |
| 2374 | XMM16b_enc = 16, |
| 2375 | XMM16c_enc = 16, |
| 2376 | XMM16d_enc = 16, |
| 2377 | XMM16e_enc = 16, |
| 2378 | XMM16f_enc = 16, |
| 2379 | XMM16g_enc = 16, |
| 2380 | XMM16h_enc = 16, |
| 2381 | XMM16i_enc = 16, |
| 2382 | XMM16j_enc = 16, |
| 2383 | XMM16k_enc = 16, |
| 2384 | XMM16l_enc = 16, |
| 2385 | XMM16m_enc = 16, |
| 2386 | XMM16n_enc = 16, |
| 2387 | XMM16o_enc = 16, |
| 2388 | XMM16p_enc = 16, |
| 2389 | XMM17_enc = 17, |
| 2390 | XMM17b_enc = 17, |
| 2391 | XMM17c_enc = 17, |
| 2392 | XMM17d_enc = 17, |
| 2393 | XMM17e_enc = 17, |
| 2394 | XMM17f_enc = 17, |
| 2395 | XMM17g_enc = 17, |
| 2396 | XMM17h_enc = 17, |
| 2397 | XMM17i_enc = 17, |
| 2398 | XMM17j_enc = 17, |
| 2399 | XMM17k_enc = 17, |
| 2400 | XMM17l_enc = 17, |
| 2401 | XMM17m_enc = 17, |
| 2402 | XMM17n_enc = 17, |
| 2403 | XMM17o_enc = 17, |
| 2404 | XMM17p_enc = 17, |
| 2405 | XMM18_enc = 18, |
| 2406 | XMM18b_enc = 18, |
| 2407 | XMM18c_enc = 18, |
| 2408 | XMM18d_enc = 18, |
| 2409 | XMM18e_enc = 18, |
| 2410 | XMM18f_enc = 18, |
| 2411 | XMM18g_enc = 18, |
| 2412 | XMM18h_enc = 18, |
| 2413 | XMM18i_enc = 18, |
| 2414 | XMM18j_enc = 18, |
| 2415 | XMM18k_enc = 18, |
| 2416 | XMM18l_enc = 18, |
| 2417 | XMM18m_enc = 18, |
| 2418 | XMM18n_enc = 18, |
| 2419 | XMM18o_enc = 18, |
| 2420 | XMM18p_enc = 18, |
| 2421 | XMM19_enc = 19, |
| 2422 | XMM19b_enc = 19, |
| 2423 | XMM19c_enc = 19, |
| 2424 | XMM19d_enc = 19, |
| 2425 | XMM19e_enc = 19, |
| 2426 | XMM19f_enc = 19, |
| 2427 | XMM19g_enc = 19, |
| 2428 | XMM19h_enc = 19, |
| 2429 | XMM19i_enc = 19, |
| 2430 | XMM19j_enc = 19, |
| 2431 | XMM19k_enc = 19, |
| 2432 | XMM19l_enc = 19, |
| 2433 | XMM19m_enc = 19, |
| 2434 | XMM19n_enc = 19, |
| 2435 | XMM19o_enc = 19, |
| 2436 | XMM19p_enc = 19, |
| 2437 | XMM20_enc = 20, |
| 2438 | XMM20b_enc = 20, |
| 2439 | XMM20c_enc = 20, |
| 2440 | XMM20d_enc = 20, |
| 2441 | XMM20e_enc = 20, |
| 2442 | XMM20f_enc = 20, |
| 2443 | XMM20g_enc = 20, |
| 2444 | XMM20h_enc = 20, |
| 2445 | XMM20i_enc = 20, |
| 2446 | XMM20j_enc = 20, |
| 2447 | XMM20k_enc = 20, |
| 2448 | XMM20l_enc = 20, |
| 2449 | XMM20m_enc = 20, |
| 2450 | XMM20n_enc = 20, |
| 2451 | XMM20o_enc = 20, |
| 2452 | XMM20p_enc = 20, |
| 2453 | XMM21_enc = 21, |
| 2454 | XMM21b_enc = 21, |
| 2455 | XMM21c_enc = 21, |
| 2456 | XMM21d_enc = 21, |
| 2457 | XMM21e_enc = 21, |
| 2458 | XMM21f_enc = 21, |
| 2459 | XMM21g_enc = 21, |
| 2460 | XMM21h_enc = 21, |
| 2461 | XMM21i_enc = 21, |
| 2462 | XMM21j_enc = 21, |
| 2463 | XMM21k_enc = 21, |
| 2464 | XMM21l_enc = 21, |
| 2465 | XMM21m_enc = 21, |
| 2466 | XMM21n_enc = 21, |
| 2467 | XMM21o_enc = 21, |
| 2468 | XMM21p_enc = 21, |
| 2469 | XMM22_enc = 22, |
| 2470 | XMM22b_enc = 22, |
| 2471 | XMM22c_enc = 22, |
| 2472 | XMM22d_enc = 22, |
| 2473 | XMM22e_enc = 22, |
| 2474 | XMM22f_enc = 22, |
| 2475 | XMM22g_enc = 22, |
| 2476 | XMM22h_enc = 22, |
| 2477 | XMM22i_enc = 22, |
| 2478 | XMM22j_enc = 22, |
| 2479 | XMM22k_enc = 22, |
| 2480 | XMM22l_enc = 22, |
| 2481 | XMM22m_enc = 22, |
| 2482 | XMM22n_enc = 22, |
| 2483 | XMM22o_enc = 22, |
| 2484 | XMM22p_enc = 22, |
| 2485 | XMM23_enc = 23, |
| 2486 | XMM23b_enc = 23, |
| 2487 | XMM23c_enc = 23, |
| 2488 | XMM23d_enc = 23, |
| 2489 | XMM23e_enc = 23, |
| 2490 | XMM23f_enc = 23, |
| 2491 | XMM23g_enc = 23, |
| 2492 | XMM23h_enc = 23, |
| 2493 | XMM23i_enc = 23, |
| 2494 | XMM23j_enc = 23, |
| 2495 | XMM23k_enc = 23, |
| 2496 | XMM23l_enc = 23, |
| 2497 | XMM23m_enc = 23, |
| 2498 | XMM23n_enc = 23, |
| 2499 | XMM23o_enc = 23, |
| 2500 | XMM23p_enc = 23, |
| 2501 | XMM24_enc = 24, |
| 2502 | XMM24b_enc = 24, |
| 2503 | XMM24c_enc = 24, |
| 2504 | XMM24d_enc = 24, |
| 2505 | XMM24e_enc = 24, |
| 2506 | XMM24f_enc = 24, |
| 2507 | XMM24g_enc = 24, |
| 2508 | XMM24h_enc = 24, |
| 2509 | XMM24i_enc = 24, |
| 2510 | XMM24j_enc = 24, |
| 2511 | XMM24k_enc = 24, |
| 2512 | XMM24l_enc = 24, |
| 2513 | XMM24m_enc = 24, |
| 2514 | XMM24n_enc = 24, |
| 2515 | XMM24o_enc = 24, |
| 2516 | XMM24p_enc = 24, |
| 2517 | XMM25_enc = 25, |
| 2518 | XMM25b_enc = 25, |
| 2519 | XMM25c_enc = 25, |
| 2520 | XMM25d_enc = 25, |
| 2521 | XMM25e_enc = 25, |
| 2522 | XMM25f_enc = 25, |
| 2523 | XMM25g_enc = 25, |
| 2524 | XMM25h_enc = 25, |
| 2525 | XMM25i_enc = 25, |
| 2526 | XMM25j_enc = 25, |
| 2527 | XMM25k_enc = 25, |
| 2528 | XMM25l_enc = 25, |
| 2529 | XMM25m_enc = 25, |
| 2530 | XMM25n_enc = 25, |
| 2531 | XMM25o_enc = 25, |
| 2532 | XMM25p_enc = 25, |
| 2533 | XMM26_enc = 26, |
| 2534 | XMM26b_enc = 26, |
| 2535 | XMM26c_enc = 26, |
| 2536 | XMM26d_enc = 26, |
| 2537 | XMM26e_enc = 26, |
| 2538 | XMM26f_enc = 26, |
| 2539 | XMM26g_enc = 26, |
| 2540 | XMM26h_enc = 26, |
| 2541 | XMM26i_enc = 26, |
| 2542 | XMM26j_enc = 26, |
| 2543 | XMM26k_enc = 26, |
| 2544 | XMM26l_enc = 26, |
| 2545 | XMM26m_enc = 26, |
| 2546 | XMM26n_enc = 26, |
| 2547 | XMM26o_enc = 26, |
| 2548 | XMM26p_enc = 26, |
| 2549 | XMM27_enc = 27, |
| 2550 | XMM27b_enc = 27, |
| 2551 | XMM27c_enc = 27, |
| 2552 | XMM27d_enc = 27, |
| 2553 | XMM27e_enc = 27, |
| 2554 | XMM27f_enc = 27, |
| 2555 | XMM27g_enc = 27, |
| 2556 | XMM27h_enc = 27, |
| 2557 | XMM27i_enc = 27, |
| 2558 | XMM27j_enc = 27, |
| 2559 | XMM27k_enc = 27, |
| 2560 | XMM27l_enc = 27, |
| 2561 | XMM27m_enc = 27, |
| 2562 | XMM27n_enc = 27, |
| 2563 | XMM27o_enc = 27, |
| 2564 | XMM27p_enc = 27, |
| 2565 | XMM28_enc = 28, |
| 2566 | XMM28b_enc = 28, |
| 2567 | XMM28c_enc = 28, |
| 2568 | XMM28d_enc = 28, |
| 2569 | XMM28e_enc = 28, |
| 2570 | XMM28f_enc = 28, |
| 2571 | XMM28g_enc = 28, |
| 2572 | XMM28h_enc = 28, |
| 2573 | XMM28i_enc = 28, |
| 2574 | XMM28j_enc = 28, |
| 2575 | XMM28k_enc = 28, |
| 2576 | XMM28l_enc = 28, |
| 2577 | XMM28m_enc = 28, |
| 2578 | XMM28n_enc = 28, |
| 2579 | XMM28o_enc = 28, |
| 2580 | XMM28p_enc = 28, |
| 2581 | XMM29_enc = 29, |
| 2582 | XMM29b_enc = 29, |
| 2583 | XMM29c_enc = 29, |
| 2584 | XMM29d_enc = 29, |
| 2585 | XMM29e_enc = 29, |
| 2586 | XMM29f_enc = 29, |
| 2587 | XMM29g_enc = 29, |
| 2588 | XMM29h_enc = 29, |
| 2589 | XMM29i_enc = 29, |
| 2590 | XMM29j_enc = 29, |
| 2591 | XMM29k_enc = 29, |
| 2592 | XMM29l_enc = 29, |
| 2593 | XMM29m_enc = 29, |
| 2594 | XMM29n_enc = 29, |
| 2595 | XMM29o_enc = 29, |
| 2596 | XMM29p_enc = 29, |
| 2597 | XMM30_enc = 30, |
| 2598 | XMM30b_enc = 30, |
| 2599 | XMM30c_enc = 30, |
| 2600 | XMM30d_enc = 30, |
| 2601 | XMM30e_enc = 30, |
| 2602 | XMM30f_enc = 30, |
| 2603 | XMM30g_enc = 30, |
| 2604 | XMM30h_enc = 30, |
| 2605 | XMM30i_enc = 30, |
| 2606 | XMM30j_enc = 30, |
| 2607 | XMM30k_enc = 30, |
| 2608 | XMM30l_enc = 30, |
| 2609 | XMM30m_enc = 30, |
| 2610 | XMM30n_enc = 30, |
| 2611 | XMM30o_enc = 30, |
| 2612 | XMM30p_enc = 30, |
| 2613 | XMM31_enc = 31, |
| 2614 | XMM31b_enc = 31, |
| 2615 | XMM31c_enc = 31, |
| 2616 | XMM31d_enc = 31, |
| 2617 | XMM31e_enc = 31, |
| 2618 | XMM31f_enc = 31, |
| 2619 | XMM31g_enc = 31, |
| 2620 | XMM31h_enc = 31, |
| 2621 | XMM31i_enc = 31, |
| 2622 | XMM31j_enc = 31, |
| 2623 | XMM31k_enc = 31, |
| 2624 | XMM31l_enc = 31, |
| 2625 | XMM31m_enc = 31, |
| 2626 | XMM31n_enc = 31, |
| 2627 | XMM31o_enc = 31, |
| 2628 | XMM31p_enc = 31, |
| 2629 | RFLAGS_enc = 16 |
| 2630 | }; |
| 2631 | |
| 2632 | // Pipeline Stages |
| 2633 | enum machPipelineStages { |
| 2634 | stage_undefined = 0, |
| 2635 | stage_S0 = 1, |
| 2636 | stage_S1 = 2, |
| 2637 | stage_S2 = 3, |
| 2638 | stage_S3 = 4, |
| 2639 | stage_S4 = 5, |
| 2640 | stage_S5 = 6, |
| 2641 | stage_count = 6 |
| 2642 | }; |
| 2643 | |
| 2644 | // Pipeline Resources |
| 2645 | enum machPipelineResources { |
| 2646 | resource_D0 = 0, |
| 2647 | resource_D1 = 1, |
| 2648 | resource_D2 = 2, |
| 2649 | resource_MS0 = 3, |
| 2650 | resource_MS1 = 4, |
| 2651 | resource_MS2 = 5, |
| 2652 | resource_BR = 6, |
| 2653 | resource_FPU = 7, |
| 2654 | resource_ALU0 = 8, |
| 2655 | resource_ALU1 = 9, |
| 2656 | resource_ALU2 = 10, |
| 2657 | |
| 2658 | res_mask_D0 = 0x00000001, |
| 2659 | res_mask_D1 = 0x00000002, |
| 2660 | res_mask_D2 = 0x00000004, |
| 2661 | res_mask_DECODE = 0x00000007, |
| 2662 | res_mask_MS0 = 0x00000008, |
| 2663 | res_mask_MS1 = 0x00000010, |
| 2664 | res_mask_MS2 = 0x00000020, |
| 2665 | res_mask_MEM = 0x00000038, |
| 2666 | res_mask_BR = 0x00000040, |
| 2667 | res_mask_FPU = 0x00000080, |
| 2668 | res_mask_ALU0 = 0x00000100, |
| 2669 | res_mask_ALU1 = 0x00000200, |
| 2670 | res_mask_ALU2 = 0x00000400, |
| 2671 | res_mask_ALU = 0x00000700, |
| 2672 | |
| 2673 | resource_count = 11 |
| 2674 | }; |
| 2675 | |
| 2676 | // MACROS to inline and constant fold State::valid(index)... |
| 2677 | // when given a constant 'index' in dfa_<arch>.cpp |
| 2678 | // uint word = index >> 5; // Shift out bit position |
| 2679 | // uint bitpos = index & 0x0001F; // Mask off word bits |
| 2680 | #define STATE__VALID(index) (_valid[((uint)index) >> 5] & (0x1 << (((uint)index) & 0x0001F))) |
| 2681 | |
| 2682 | #define STATE__NOT_YET_VALID(index) ( (_valid[((uint)index) >> 5] & (0x1 << (((uint)index) & 0x0001F))) == 0 ) |
| 2683 | |
| 2684 | #define STATE__VALID_CHILD(state,index) ( state && (state->_valid[((uint)index) >> 5] & (0x1 << (((uint)index) & 0x0001F))) ) |
| 2685 | |
| 2686 | #define STATE__SET_VALID(index) (_valid[((uint)index) >> 5] |= (0x1 << (((uint)index) & 0x0001F))) |
| 2687 | |
| 2688 | //---------------------------State------------------------------------------- |
| 2689 | // State contains an integral cost vector, indexed by machine operand opcodes, |
| 2690 | // a rule vector consisting of machine operand/instruction opcodes, and also |
| 2691 | // indexed by machine operand opcodes, pointers to the children in the label |
| 2692 | // tree generated by the Label routines in ideal nodes (currently limited to |
| 2693 | // two for convenience, but this could change). |
| 2694 | class State : public ResourceObj { |
| 2695 | public: |
| 2696 | int _id; // State identifier |
| 2697 | Node *_leaf; // Ideal (non-machine-node) leaf of match tree |
| 2698 | State *_kids[2]; // Children of state node in label tree |
| 2699 | unsigned int _cost[_LAST_MACH_OPER]; // Cost vector, indexed by operand opcodes |
| 2700 | unsigned int _rule[_LAST_MACH_OPER]; // Rule vector, indexed by operand opcodes |
| 2701 | unsigned int _valid[(_LAST_MACH_OPER/32)+1]; // Bit Map of valid Cost/Rule entries |
| 2702 | |
| 2703 | State(void); // Constructor |
| 2704 | DEBUG_ONLY( ~State(void); ) // Destructor |
| 2705 | |
| 2706 | // Methods created by ADLC and invoked by Reduce |
| 2707 | MachOper *MachOperGenerator(int opcode); |
| 2708 | MachNode *MachNodeGenerator(int opcode); |
| 2709 | |
| 2710 | // Assign a state to a node, definition of method produced by ADLC |
| 2711 | bool DFA( int opcode, const Node *ideal ); |
| 2712 | |
| 2713 | // Access function for _valid bit vector |
| 2714 | bool valid(uint index) { |
| 2715 | return( STATE__VALID(index) != 0 ); |
| 2716 | } |
| 2717 | |
| 2718 | // Set function for _valid bit vector |
| 2719 | void set_valid(uint index) { |
| 2720 | STATE__SET_VALID(index); |
| 2721 | } |
| 2722 | |
| 2723 | #ifndef PRODUCT |
| 2724 | void dump(); // Debugging prints |
| 2725 | void dump(int depth); |
| 2726 | #endif |
| 2727 | void _sub_Op_RegN(const Node *n); |
| 2728 | void _sub_Op_RegI(const Node *n); |
| 2729 | void _sub_Op_RegP(const Node *n); |
| 2730 | void _sub_Op_RegF(const Node *n); |
| 2731 | void _sub_Op_RegD(const Node *n); |
| 2732 | void _sub_Op_RegL(const Node *n); |
| 2733 | void _sub_Op_RegFlags(const Node *n); |
| 2734 | void _sub_Op_VecS(const Node *n); |
| 2735 | void _sub_Op_VecD(const Node *n); |
| 2736 | void _sub_Op_VecX(const Node *n); |
| 2737 | void _sub_Op_VecY(const Node *n); |
| 2738 | void _sub_Op_VecZ(const Node *n); |
| 2739 | void _sub_Op_AbsD(const Node *n); |
| 2740 | void _sub_Op_AbsF(const Node *n); |
| 2741 | void _sub_Op_AbsI(const Node *n); |
| 2742 | void _sub_Op_AbsL(const Node *n); |
| 2743 | void _sub_Op_AddD(const Node *n); |
| 2744 | void _sub_Op_AddF(const Node *n); |
| 2745 | void _sub_Op_AddI(const Node *n); |
| 2746 | void _sub_Op_AddL(const Node *n); |
| 2747 | void _sub_Op_AddP(const Node *n); |
| 2748 | void _sub_Op_AndI(const Node *n); |
| 2749 | void _sub_Op_AndL(const Node *n); |
| 2750 | void _sub_Op_AryEq(const Node *n); |
| 2751 | void _sub_Op_Binary(const Node *n); |
| 2752 | void _sub_Op_Bool(const Node *n); |
| 2753 | void _sub_Op_ReverseBytesI(const Node *n); |
| 2754 | void _sub_Op_ReverseBytesL(const Node *n); |
| 2755 | void _sub_Op_ReverseBytesUS(const Node *n); |
| 2756 | void _sub_Op_ReverseBytesS(const Node *n); |
| 2757 | void _sub_Op_CallDynamicJava(const Node *n); |
| 2758 | void _sub_Op_CallLeaf(const Node *n); |
| 2759 | void _sub_Op_CallLeafNoFP(const Node *n); |
| 2760 | void _sub_Op_CallRuntime(const Node *n); |
| 2761 | void _sub_Op_CallStaticJava(const Node *n); |
| 2762 | void _sub_Op_CastII(const Node *n); |
| 2763 | void _sub_Op_CastX2P(const Node *n); |
| 2764 | void _sub_Op_CastP2X(const Node *n); |
| 2765 | void _sub_Op_CastPP(const Node *n); |
| 2766 | void _sub_Op_CheckCastPP(const Node *n); |
| 2767 | void _sub_Op_ClearArray(const Node *n); |
| 2768 | void _sub_Op_CMoveD(const Node *n); |
| 2769 | void _sub_Op_CMoveVD(const Node *n); |
| 2770 | void _sub_Op_CMoveF(const Node *n); |
| 2771 | void _sub_Op_CMoveVF(const Node *n); |
| 2772 | void _sub_Op_CMoveI(const Node *n); |
| 2773 | void _sub_Op_CMoveL(const Node *n); |
| 2774 | void _sub_Op_CMoveP(const Node *n); |
| 2775 | void _sub_Op_CMoveN(const Node *n); |
| 2776 | void _sub_Op_CmpN(const Node *n); |
| 2777 | void _sub_Op_CmpD(const Node *n); |
| 2778 | void _sub_Op_CmpD3(const Node *n); |
| 2779 | void _sub_Op_CmpF(const Node *n); |
| 2780 | void _sub_Op_CmpF3(const Node *n); |
| 2781 | void _sub_Op_CmpI(const Node *n); |
| 2782 | void _sub_Op_CmpL(const Node *n); |
| 2783 | void _sub_Op_CmpL3(const Node *n); |
| 2784 | void _sub_Op_CmpLTMask(const Node *n); |
| 2785 | void _sub_Op_CmpP(const Node *n); |
| 2786 | void _sub_Op_CmpU(const Node *n); |
| 2787 | void _sub_Op_CmpUL(const Node *n); |
| 2788 | void _sub_Op_CompareAndSwapB(const Node *n); |
| 2789 | void _sub_Op_CompareAndSwapS(const Node *n); |
| 2790 | void _sub_Op_CompareAndSwapI(const Node *n); |
| 2791 | void _sub_Op_CompareAndSwapL(const Node *n); |
| 2792 | void _sub_Op_CompareAndSwapP(const Node *n); |
| 2793 | void _sub_Op_CompareAndSwapN(const Node *n); |
| 2794 | void _sub_Op_WeakCompareAndSwapB(const Node *n); |
| 2795 | void _sub_Op_WeakCompareAndSwapS(const Node *n); |
| 2796 | void _sub_Op_WeakCompareAndSwapI(const Node *n); |
| 2797 | void _sub_Op_WeakCompareAndSwapL(const Node *n); |
| 2798 | void _sub_Op_WeakCompareAndSwapP(const Node *n); |
| 2799 | void _sub_Op_WeakCompareAndSwapN(const Node *n); |
| 2800 | void _sub_Op_CompareAndExchangeB(const Node *n); |
| 2801 | void _sub_Op_CompareAndExchangeS(const Node *n); |
| 2802 | void _sub_Op_CompareAndExchangeI(const Node *n); |
| 2803 | void _sub_Op_CompareAndExchangeL(const Node *n); |
| 2804 | void _sub_Op_CompareAndExchangeP(const Node *n); |
| 2805 | void _sub_Op_CompareAndExchangeN(const Node *n); |
| 2806 | void _sub_Op_GetAndAddB(const Node *n); |
| 2807 | void _sub_Op_GetAndAddS(const Node *n); |
| 2808 | void _sub_Op_GetAndAddI(const Node *n); |
| 2809 | void _sub_Op_GetAndAddL(const Node *n); |
| 2810 | void _sub_Op_GetAndSetB(const Node *n); |
| 2811 | void _sub_Op_GetAndSetS(const Node *n); |
| 2812 | void _sub_Op_GetAndSetI(const Node *n); |
| 2813 | void _sub_Op_GetAndSetL(const Node *n); |
| 2814 | void _sub_Op_GetAndSetP(const Node *n); |
| 2815 | void _sub_Op_GetAndSetN(const Node *n); |
| 2816 | void _sub_Op_ConN(const Node *n); |
| 2817 | void _sub_Op_ConNKlass(const Node *n); |
| 2818 | void _sub_Op_ConD(const Node *n); |
| 2819 | void _sub_Op_ConF(const Node *n); |
| 2820 | void _sub_Op_ConI(const Node *n); |
| 2821 | void _sub_Op_ConL(const Node *n); |
| 2822 | void _sub_Op_ConP(const Node *n); |
| 2823 | void _sub_Op_Conv2B(const Node *n); |
| 2824 | void _sub_Op_ConvD2F(const Node *n); |
| 2825 | void _sub_Op_ConvD2I(const Node *n); |
| 2826 | void _sub_Op_ConvD2L(const Node *n); |
| 2827 | void _sub_Op_ConvF2D(const Node *n); |
| 2828 | void _sub_Op_ConvF2I(const Node *n); |
| 2829 | void _sub_Op_ConvF2L(const Node *n); |
| 2830 | void _sub_Op_ConvI2D(const Node *n); |
| 2831 | void _sub_Op_ConvI2F(const Node *n); |
| 2832 | void _sub_Op_ConvI2L(const Node *n); |
| 2833 | void _sub_Op_ConvL2D(const Node *n); |
| 2834 | void _sub_Op_ConvL2F(const Node *n); |
| 2835 | void _sub_Op_ConvL2I(const Node *n); |
| 2836 | void _sub_Op_CountedLoopEnd(const Node *n); |
| 2837 | void _sub_Op_CountLeadingZerosI(const Node *n); |
| 2838 | void _sub_Op_CountLeadingZerosL(const Node *n); |
| 2839 | void _sub_Op_CountTrailingZerosI(const Node *n); |
| 2840 | void _sub_Op_CountTrailingZerosL(const Node *n); |
| 2841 | void _sub_Op_CreateEx(const Node *n); |
| 2842 | void _sub_Op_DecodeN(const Node *n); |
| 2843 | void _sub_Op_DecodeNKlass(const Node *n); |
| 2844 | void _sub_Op_DivD(const Node *n); |
| 2845 | void _sub_Op_DivF(const Node *n); |
| 2846 | void _sub_Op_DivI(const Node *n); |
| 2847 | void _sub_Op_DivL(const Node *n); |
| 2848 | void _sub_Op_DivModI(const Node *n); |
| 2849 | void _sub_Op_DivModL(const Node *n); |
| 2850 | void _sub_Op_EncodeISOArray(const Node *n); |
| 2851 | void _sub_Op_EncodeP(const Node *n); |
| 2852 | void _sub_Op_EncodePKlass(const Node *n); |
| 2853 | void _sub_Op_FastLock(const Node *n); |
| 2854 | void _sub_Op_FastUnlock(const Node *n); |
| 2855 | void _sub_Op_FmaD(const Node *n); |
| 2856 | void _sub_Op_FmaF(const Node *n); |
| 2857 | void _sub_Op_Goto(const Node *n); |
| 2858 | void _sub_Op_Halt(const Node *n); |
| 2859 | void _sub_Op_HasNegatives(const Node *n); |
| 2860 | void _sub_Op_If(const Node *n); |
| 2861 | void _sub_Op_Jump(const Node *n); |
| 2862 | void _sub_Op_LShiftI(const Node *n); |
| 2863 | void _sub_Op_LShiftL(const Node *n); |
| 2864 | void _sub_Op_LoadB(const Node *n); |
| 2865 | void _sub_Op_LoadUB(const Node *n); |
| 2866 | void _sub_Op_LoadUS(const Node *n); |
| 2867 | void _sub_Op_LoadD(const Node *n); |
| 2868 | void _sub_Op_LoadF(const Node *n); |
| 2869 | void _sub_Op_LoadI(const Node *n); |
| 2870 | void _sub_Op_LoadKlass(const Node *n); |
| 2871 | void _sub_Op_LoadNKlass(const Node *n); |
| 2872 | void _sub_Op_LoadL(const Node *n); |
| 2873 | void _sub_Op_LoadPLocked(const Node *n); |
| 2874 | void _sub_Op_LoadP(const Node *n); |
| 2875 | void _sub_Op_LoadN(const Node *n); |
| 2876 | void _sub_Op_LoadRange(const Node *n); |
| 2877 | void _sub_Op_LoadS(const Node *n); |
| 2878 | void _sub_Op_LoadBarrierSlowReg(const Node *n); |
| 2879 | void _sub_Op_ZCompareAndSwapP(const Node *n); |
| 2880 | void _sub_Op_ZWeakCompareAndSwapP(const Node *n); |
| 2881 | void _sub_Op_ZCompareAndExchangeP(const Node *n); |
| 2882 | void _sub_Op_ZGetAndSetP(const Node *n); |
| 2883 | void _sub_Op_MulAddS2I(const Node *n); |
| 2884 | void _sub_Op_MaxD(const Node *n); |
| 2885 | void _sub_Op_MaxF(const Node *n); |
| 2886 | void _sub_Op_MaxI(const Node *n); |
| 2887 | void _sub_Op_MemBarAcquire(const Node *n); |
| 2888 | void _sub_Op_LoadFence(const Node *n); |
| 2889 | void _sub_Op_SetVectMaskI(const Node *n); |
| 2890 | void _sub_Op_MemBarAcquireLock(const Node *n); |
| 2891 | void _sub_Op_MemBarRelease(const Node *n); |
| 2892 | void _sub_Op_StoreFence(const Node *n); |
| 2893 | void _sub_Op_MemBarReleaseLock(const Node *n); |
| 2894 | void _sub_Op_MemBarVolatile(const Node *n); |
| 2895 | void _sub_Op_MemBarStoreStore(const Node *n); |
| 2896 | void _sub_Op_MinD(const Node *n); |
| 2897 | void _sub_Op_MinF(const Node *n); |
| 2898 | void _sub_Op_MinI(const Node *n); |
| 2899 | void _sub_Op_ModI(const Node *n); |
| 2900 | void _sub_Op_ModL(const Node *n); |
| 2901 | void _sub_Op_MoveI2F(const Node *n); |
| 2902 | void _sub_Op_MoveF2I(const Node *n); |
| 2903 | void _sub_Op_MoveL2D(const Node *n); |
| 2904 | void _sub_Op_MoveD2L(const Node *n); |
| 2905 | void _sub_Op_MulD(const Node *n); |
| 2906 | void _sub_Op_MulF(const Node *n); |
| 2907 | void _sub_Op_MulHiL(const Node *n); |
| 2908 | void _sub_Op_MulI(const Node *n); |
| 2909 | void _sub_Op_MulL(const Node *n); |
| 2910 | void _sub_Op_NegD(const Node *n); |
| 2911 | void _sub_Op_NegF(const Node *n); |
| 2912 | void _sub_Op_OnSpinWait(const Node *n); |
| 2913 | void _sub_Op_OrI(const Node *n); |
| 2914 | void _sub_Op_OrL(const Node *n); |
| 2915 | void _sub_Op_OverflowAddI(const Node *n); |
| 2916 | void _sub_Op_OverflowSubI(const Node *n); |
| 2917 | void _sub_Op_OverflowMulI(const Node *n); |
| 2918 | void _sub_Op_OverflowAddL(const Node *n); |
| 2919 | void _sub_Op_OverflowSubL(const Node *n); |
| 2920 | void _sub_Op_OverflowMulL(const Node *n); |
| 2921 | void _sub_Op_PartialSubtypeCheck(const Node *n); |
| 2922 | void _sub_Op_PopCountI(const Node *n); |
| 2923 | void _sub_Op_PopCountL(const Node *n); |
| 2924 | void _sub_Op_PopCountVI(const Node *n); |
| 2925 | void _sub_Op_PrefetchAllocation(const Node *n); |
| 2926 | void _sub_Op_RShiftI(const Node *n); |
| 2927 | void _sub_Op_RShiftL(const Node *n); |
| 2928 | void _sub_Op_Rethrow(const Node *n); |
| 2929 | void _sub_Op_Return(const Node *n); |
| 2930 | void _sub_Op_RoundDouble(const Node *n); |
| 2931 | void _sub_Op_RoundFloat(const Node *n); |
| 2932 | void _sub_Op_SafePoint(const Node *n); |
| 2933 | void _sub_Op_ShenandoahCompareAndExchangeP(const Node *n); |
| 2934 | void _sub_Op_ShenandoahCompareAndExchangeN(const Node *n); |
| 2935 | void _sub_Op_ShenandoahCompareAndSwapN(const Node *n); |
| 2936 | void _sub_Op_ShenandoahCompareAndSwapP(const Node *n); |
| 2937 | void _sub_Op_ShenandoahWeakCompareAndSwapN(const Node *n); |
| 2938 | void _sub_Op_ShenandoahWeakCompareAndSwapP(const Node *n); |
| 2939 | void _sub_Op_SqrtD(const Node *n); |
| 2940 | void _sub_Op_SqrtF(const Node *n); |
| 2941 | void _sub_Op_StoreB(const Node *n); |
| 2942 | void _sub_Op_StoreC(const Node *n); |
| 2943 | void _sub_Op_StoreCM(const Node *n); |
| 2944 | void _sub_Op_StorePConditional(const Node *n); |
| 2945 | void _sub_Op_StoreIConditional(const Node *n); |
| 2946 | void _sub_Op_StoreLConditional(const Node *n); |
| 2947 | void _sub_Op_StoreD(const Node *n); |
| 2948 | void _sub_Op_StoreF(const Node *n); |
| 2949 | void _sub_Op_StoreI(const Node *n); |
| 2950 | void _sub_Op_StoreL(const Node *n); |
| 2951 | void _sub_Op_StoreP(const Node *n); |
| 2952 | void _sub_Op_StoreN(const Node *n); |
| 2953 | void _sub_Op_StoreNKlass(const Node *n); |
| 2954 | void _sub_Op_StrComp(const Node *n); |
| 2955 | void _sub_Op_StrCompressedCopy(const Node *n); |
| 2956 | void _sub_Op_StrEquals(const Node *n); |
| 2957 | void _sub_Op_StrIndexOf(const Node *n); |
| 2958 | void _sub_Op_StrIndexOfChar(const Node *n); |
| 2959 | void _sub_Op_StrInflatedCopy(const Node *n); |
| 2960 | void _sub_Op_SubD(const Node *n); |
| 2961 | void _sub_Op_SubF(const Node *n); |
| 2962 | void _sub_Op_SubI(const Node *n); |
| 2963 | void _sub_Op_SubL(const Node *n); |
| 2964 | void _sub_Op_TailCall(const Node *n); |
| 2965 | void _sub_Op_TailJump(const Node *n); |
| 2966 | void _sub_Op_ThreadLocal(const Node *n); |
| 2967 | void _sub_Op_URShiftI(const Node *n); |
| 2968 | void _sub_Op_URShiftL(const Node *n); |
| 2969 | void _sub_Op_XorI(const Node *n); |
| 2970 | void _sub_Op_XorL(const Node *n); |
| 2971 | void _sub_Op_AddVB(const Node *n); |
| 2972 | void _sub_Op_AddVS(const Node *n); |
| 2973 | void _sub_Op_AddVI(const Node *n); |
| 2974 | void _sub_Op_AddReductionVI(const Node *n); |
| 2975 | void _sub_Op_AddVL(const Node *n); |
| 2976 | void _sub_Op_AddReductionVL(const Node *n); |
| 2977 | void _sub_Op_AddVF(const Node *n); |
| 2978 | void _sub_Op_AddReductionVF(const Node *n); |
| 2979 | void _sub_Op_AddVD(const Node *n); |
| 2980 | void _sub_Op_AddReductionVD(const Node *n); |
| 2981 | void _sub_Op_SubVB(const Node *n); |
| 2982 | void _sub_Op_SubVS(const Node *n); |
| 2983 | void _sub_Op_SubVI(const Node *n); |
| 2984 | void _sub_Op_SubVL(const Node *n); |
| 2985 | void _sub_Op_SubVF(const Node *n); |
| 2986 | void _sub_Op_SubVD(const Node *n); |
| 2987 | void _sub_Op_MulVB(const Node *n); |
| 2988 | void _sub_Op_MulVS(const Node *n); |
| 2989 | void _sub_Op_MulVI(const Node *n); |
| 2990 | void _sub_Op_MulReductionVI(const Node *n); |
| 2991 | void _sub_Op_MulVL(const Node *n); |
| 2992 | void _sub_Op_MulReductionVL(const Node *n); |
| 2993 | void _sub_Op_MulVF(const Node *n); |
| 2994 | void _sub_Op_MulReductionVF(const Node *n); |
| 2995 | void _sub_Op_MulVD(const Node *n); |
| 2996 | void _sub_Op_MulReductionVD(const Node *n); |
| 2997 | void _sub_Op_MulAddVS2VI(const Node *n); |
| 2998 | void _sub_Op_FmaVD(const Node *n); |
| 2999 | void _sub_Op_FmaVF(const Node *n); |
| 3000 | void _sub_Op_DivVF(const Node *n); |
| 3001 | void _sub_Op_DivVD(const Node *n); |
| 3002 | void _sub_Op_AbsVB(const Node *n); |
| 3003 | void _sub_Op_AbsVS(const Node *n); |
| 3004 | void _sub_Op_AbsVI(const Node *n); |
| 3005 | void _sub_Op_AbsVL(const Node *n); |
| 3006 | void _sub_Op_AbsVF(const Node *n); |
| 3007 | void _sub_Op_AbsVD(const Node *n); |
| 3008 | void _sub_Op_NegVF(const Node *n); |
| 3009 | void _sub_Op_NegVD(const Node *n); |
| 3010 | void _sub_Op_SqrtVD(const Node *n); |
| 3011 | void _sub_Op_SqrtVF(const Node *n); |
| 3012 | void _sub_Op_LShiftCntV(const Node *n); |
| 3013 | void _sub_Op_RShiftCntV(const Node *n); |
| 3014 | void _sub_Op_LShiftVB(const Node *n); |
| 3015 | void _sub_Op_LShiftVS(const Node *n); |
| 3016 | void _sub_Op_LShiftVI(const Node *n); |
| 3017 | void _sub_Op_LShiftVL(const Node *n); |
| 3018 | void _sub_Op_RShiftVB(const Node *n); |
| 3019 | void _sub_Op_RShiftVS(const Node *n); |
| 3020 | void _sub_Op_RShiftVI(const Node *n); |
| 3021 | void _sub_Op_RShiftVL(const Node *n); |
| 3022 | void _sub_Op_URShiftVB(const Node *n); |
| 3023 | void _sub_Op_URShiftVS(const Node *n); |
| 3024 | void _sub_Op_URShiftVI(const Node *n); |
| 3025 | void _sub_Op_URShiftVL(const Node *n); |
| 3026 | void _sub_Op_AndV(const Node *n); |
| 3027 | void _sub_Op_OrV(const Node *n); |
| 3028 | void _sub_Op_XorV(const Node *n); |
| 3029 | void _sub_Op_LoadVector(const Node *n); |
| 3030 | void _sub_Op_StoreVector(const Node *n); |
| 3031 | void _sub_Op_ReplicateB(const Node *n); |
| 3032 | void _sub_Op_ReplicateS(const Node *n); |
| 3033 | void _sub_Op_ReplicateI(const Node *n); |
| 3034 | void _sub_Op_ReplicateL(const Node *n); |
| 3035 | void _sub_Op_ReplicateF(const Node *n); |
| 3036 | void _sub_Op_ReplicateD(const Node *n); |
| 3037 | }; |
| 3038 | |
| 3039 | |
| 3040 | |
| 3041 | // Total number of operands defined in architecture definition |
| 3042 | #define FIRST_OPERAND_CLASS 153 |
| 3043 | #define NUM_OPERANDS 154 |
| 3044 | |
| 3045 | // Total number of instructions defined in architecture definition |
| 3046 | #define NUM_INSTRUCTIONS 1337 |
| 3047 | |
| 3048 | //----------------------------Declare classes derived from MachOper---------- |
| 3049 | |
| 3050 | class UniverseOper : public MachOper { |
| 3051 | private: |
| 3052 | virtual uint num_edges() const { return 0; } |
| 3053 | public: |
| 3054 | UniverseOper() {} |
| 3055 | virtual MachOper *clone() const; |
| 3056 | virtual uint opcode() const { return UNIVERSE; } |
| 3057 | |
| 3058 | #ifndef PRODUCT |
| 3059 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3060 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3061 | virtual const char *Name() const { return "Universe";} |
| 3062 | #endif |
| 3063 | }; |
| 3064 | |
| 3065 | class sRegIOper : public MachOper { |
| 3066 | private: |
| 3067 | virtual const RegMask *in_RegMask(int index) const; |
| 3068 | public: |
| 3069 | sRegIOper() {} |
| 3070 | virtual MachOper *clone() const; |
| 3071 | virtual uint opcode() const { return SREGI; } |
| 3072 | virtual int reg(PhaseRegAlloc *ra_, const Node *node) const { |
| 3073 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node));/* sReg */ |
| 3074 | } |
| 3075 | virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 3076 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 3077 | } |
| 3078 | |
| 3079 | #ifndef PRODUCT |
| 3080 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3081 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3082 | virtual const char *Name() const { return "sRegI";} |
| 3083 | #endif |
| 3084 | }; |
| 3085 | |
| 3086 | class sRegPOper : public MachOper { |
| 3087 | private: |
| 3088 | virtual const RegMask *in_RegMask(int index) const; |
| 3089 | public: |
| 3090 | sRegPOper() {} |
| 3091 | virtual MachOper *clone() const; |
| 3092 | virtual uint opcode() const { return SREGP; } |
| 3093 | virtual int reg(PhaseRegAlloc *ra_, const Node *node) const { |
| 3094 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node));/* sReg */ |
| 3095 | } |
| 3096 | virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 3097 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 3098 | } |
| 3099 | |
| 3100 | #ifndef PRODUCT |
| 3101 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3102 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3103 | virtual const char *Name() const { return "sRegP";} |
| 3104 | #endif |
| 3105 | }; |
| 3106 | |
| 3107 | class sRegFOper : public MachOper { |
| 3108 | private: |
| 3109 | virtual const RegMask *in_RegMask(int index) const; |
| 3110 | public: |
| 3111 | sRegFOper() {} |
| 3112 | virtual MachOper *clone() const; |
| 3113 | virtual uint opcode() const { return SREGF; } |
| 3114 | virtual int reg(PhaseRegAlloc *ra_, const Node *node) const { |
| 3115 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node));/* sReg */ |
| 3116 | } |
| 3117 | virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 3118 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 3119 | } |
| 3120 | |
| 3121 | #ifndef PRODUCT |
| 3122 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3123 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3124 | virtual const char *Name() const { return "sRegF";} |
| 3125 | #endif |
| 3126 | }; |
| 3127 | |
| 3128 | class sRegDOper : public MachOper { |
| 3129 | private: |
| 3130 | virtual const RegMask *in_RegMask(int index) const; |
| 3131 | public: |
| 3132 | sRegDOper() {} |
| 3133 | virtual MachOper *clone() const; |
| 3134 | virtual uint opcode() const { return SREGD; } |
| 3135 | virtual int reg(PhaseRegAlloc *ra_, const Node *node) const { |
| 3136 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node));/* sReg */ |
| 3137 | } |
| 3138 | virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 3139 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 3140 | } |
| 3141 | |
| 3142 | #ifndef PRODUCT |
| 3143 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3144 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3145 | virtual const char *Name() const { return "sRegD";} |
| 3146 | #endif |
| 3147 | }; |
| 3148 | |
| 3149 | class sRegLOper : public MachOper { |
| 3150 | private: |
| 3151 | virtual const RegMask *in_RegMask(int index) const; |
| 3152 | public: |
| 3153 | sRegLOper() {} |
| 3154 | virtual MachOper *clone() const; |
| 3155 | virtual uint opcode() const { return SREGL; } |
| 3156 | virtual int reg(PhaseRegAlloc *ra_, const Node *node) const { |
| 3157 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node));/* sReg */ |
| 3158 | } |
| 3159 | virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 3160 | return (int)OptoReg::reg2stack(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 3161 | } |
| 3162 | |
| 3163 | #ifndef PRODUCT |
| 3164 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3165 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3166 | virtual const char *Name() const { return "sRegL";} |
| 3167 | #endif |
| 3168 | }; |
| 3169 | |
| 3170 | class immIOper : public MachOper { |
| 3171 | private: |
| 3172 | virtual uint num_edges() const { return 0; } |
| 3173 | int32_t _c0; |
| 3174 | public: |
| 3175 | immIOper(int32_t c0) : _c0(c0) {} |
| 3176 | virtual MachOper *clone() const; |
| 3177 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3178 | virtual uint opcode() const { return IMMI; } |
| 3179 | virtual const Type *type() const { return TypeInt::INT; } |
| 3180 | |
| 3181 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3182 | |
| 3183 | #ifndef PRODUCT |
| 3184 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3185 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3186 | virtual void dump_spec(outputStream *st) const { |
| 3187 | st->print("#%d", _c0); |
| 3188 | st->print("/0x%08x", _c0); |
| 3189 | } |
| 3190 | virtual const char *Name() const { return "immI";} |
| 3191 | #endif |
| 3192 | }; |
| 3193 | |
| 3194 | class immI0Oper : public MachOper { |
| 3195 | private: |
| 3196 | virtual uint num_edges() const { return 0; } |
| 3197 | int32_t _c0; |
| 3198 | public: |
| 3199 | immI0Oper(int32_t c0) : _c0(c0) {} |
| 3200 | virtual MachOper *clone() const; |
| 3201 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3202 | virtual uint opcode() const { return IMMI0; } |
| 3203 | virtual const Type *type() const { return TypeInt::INT; } |
| 3204 | |
| 3205 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3206 | |
| 3207 | #ifndef PRODUCT |
| 3208 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3209 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3210 | virtual void dump_spec(outputStream *st) const { |
| 3211 | st->print("#%d", _c0); |
| 3212 | st->print("/0x%08x", _c0); |
| 3213 | } |
| 3214 | virtual const char *Name() const { return "immI0";} |
| 3215 | #endif |
| 3216 | }; |
| 3217 | |
| 3218 | class immI1Oper : public MachOper { |
| 3219 | private: |
| 3220 | virtual uint num_edges() const { return 0; } |
| 3221 | int32_t _c0; |
| 3222 | public: |
| 3223 | immI1Oper(int32_t c0) : _c0(c0) {} |
| 3224 | virtual MachOper *clone() const; |
| 3225 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3226 | virtual uint opcode() const { return IMMI1; } |
| 3227 | virtual const Type *type() const { return TypeInt::INT; } |
| 3228 | |
| 3229 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3230 | |
| 3231 | #ifndef PRODUCT |
| 3232 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3233 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3234 | virtual void dump_spec(outputStream *st) const { |
| 3235 | st->print("#%d", _c0); |
| 3236 | st->print("/0x%08x", _c0); |
| 3237 | } |
| 3238 | virtual const char *Name() const { return "immI1";} |
| 3239 | #endif |
| 3240 | }; |
| 3241 | |
| 3242 | class immI_M1Oper : public MachOper { |
| 3243 | private: |
| 3244 | virtual uint num_edges() const { return 0; } |
| 3245 | int32_t _c0; |
| 3246 | public: |
| 3247 | immI_M1Oper(int32_t c0) : _c0(c0) {} |
| 3248 | virtual MachOper *clone() const; |
| 3249 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3250 | virtual uint opcode() const { return IMMI_M1; } |
| 3251 | virtual const Type *type() const { return TypeInt::INT; } |
| 3252 | |
| 3253 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3254 | |
| 3255 | #ifndef PRODUCT |
| 3256 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3257 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3258 | virtual void dump_spec(outputStream *st) const { |
| 3259 | st->print("#%d", _c0); |
| 3260 | st->print("/0x%08x", _c0); |
| 3261 | } |
| 3262 | virtual const char *Name() const { return "immI_M1";} |
| 3263 | #endif |
| 3264 | }; |
| 3265 | |
| 3266 | class immI2Oper : public MachOper { |
| 3267 | private: |
| 3268 | virtual uint num_edges() const { return 0; } |
| 3269 | int32_t _c0; |
| 3270 | public: |
| 3271 | immI2Oper(int32_t c0) : _c0(c0) {} |
| 3272 | virtual MachOper *clone() const; |
| 3273 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3274 | virtual uint opcode() const { return IMMI2; } |
| 3275 | virtual const Type *type() const { return TypeInt::INT; } |
| 3276 | |
| 3277 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3278 | |
| 3279 | #ifndef PRODUCT |
| 3280 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3281 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3282 | virtual void dump_spec(outputStream *st) const { |
| 3283 | st->print("#%d", _c0); |
| 3284 | st->print("/0x%08x", _c0); |
| 3285 | } |
| 3286 | virtual const char *Name() const { return "immI2";} |
| 3287 | #endif |
| 3288 | }; |
| 3289 | |
| 3290 | class immI8Oper : public MachOper { |
| 3291 | private: |
| 3292 | virtual uint num_edges() const { return 0; } |
| 3293 | int32_t _c0; |
| 3294 | public: |
| 3295 | immI8Oper(int32_t c0) : _c0(c0) {} |
| 3296 | virtual MachOper *clone() const; |
| 3297 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3298 | virtual uint opcode() const { return IMMI8; } |
| 3299 | virtual const Type *type() const { return TypeInt::INT; } |
| 3300 | |
| 3301 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3302 | |
| 3303 | #ifndef PRODUCT |
| 3304 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3305 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3306 | virtual void dump_spec(outputStream *st) const { |
| 3307 | st->print("#%d", _c0); |
| 3308 | st->print("/0x%08x", _c0); |
| 3309 | } |
| 3310 | virtual const char *Name() const { return "immI8";} |
| 3311 | #endif |
| 3312 | }; |
| 3313 | |
| 3314 | class immU8Oper : public MachOper { |
| 3315 | private: |
| 3316 | virtual uint num_edges() const { return 0; } |
| 3317 | int32_t _c0; |
| 3318 | public: |
| 3319 | immU8Oper(int32_t c0) : _c0(c0) {} |
| 3320 | virtual MachOper *clone() const; |
| 3321 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3322 | virtual uint opcode() const { return IMMU8; } |
| 3323 | virtual const Type *type() const { return TypeInt::INT; } |
| 3324 | |
| 3325 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3326 | |
| 3327 | #ifndef PRODUCT |
| 3328 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3329 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3330 | virtual void dump_spec(outputStream *st) const { |
| 3331 | st->print("#%d", _c0); |
| 3332 | st->print("/0x%08x", _c0); |
| 3333 | } |
| 3334 | virtual const char *Name() const { return "immU8";} |
| 3335 | #endif |
| 3336 | }; |
| 3337 | |
| 3338 | class immI16Oper : public MachOper { |
| 3339 | private: |
| 3340 | virtual uint num_edges() const { return 0; } |
| 3341 | int32_t _c0; |
| 3342 | public: |
| 3343 | immI16Oper(int32_t c0) : _c0(c0) {} |
| 3344 | virtual MachOper *clone() const; |
| 3345 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3346 | virtual uint opcode() const { return IMMI16; } |
| 3347 | virtual const Type *type() const { return TypeInt::INT; } |
| 3348 | |
| 3349 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3350 | |
| 3351 | #ifndef PRODUCT |
| 3352 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3353 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3354 | virtual void dump_spec(outputStream *st) const { |
| 3355 | st->print("#%d", _c0); |
| 3356 | st->print("/0x%08x", _c0); |
| 3357 | } |
| 3358 | virtual const char *Name() const { return "immI16";} |
| 3359 | #endif |
| 3360 | }; |
| 3361 | |
| 3362 | class immU31Oper : public MachOper { |
| 3363 | private: |
| 3364 | virtual uint num_edges() const { return 0; } |
| 3365 | int32_t _c0; |
| 3366 | public: |
| 3367 | immU31Oper(int32_t c0) : _c0(c0) {} |
| 3368 | virtual MachOper *clone() const; |
| 3369 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3370 | virtual uint opcode() const { return IMMU31; } |
| 3371 | virtual const Type *type() const { return TypeInt::INT; } |
| 3372 | |
| 3373 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3374 | |
| 3375 | #ifndef PRODUCT |
| 3376 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3377 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3378 | virtual void dump_spec(outputStream *st) const { |
| 3379 | st->print("#%d", _c0); |
| 3380 | st->print("/0x%08x", _c0); |
| 3381 | } |
| 3382 | virtual const char *Name() const { return "immU31";} |
| 3383 | #endif |
| 3384 | }; |
| 3385 | |
| 3386 | class immI_32Oper : public MachOper { |
| 3387 | private: |
| 3388 | virtual uint num_edges() const { return 0; } |
| 3389 | int32_t _c0; |
| 3390 | public: |
| 3391 | immI_32Oper(int32_t c0) : _c0(c0) {} |
| 3392 | virtual MachOper *clone() const; |
| 3393 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3394 | virtual uint opcode() const { return IMMI_32; } |
| 3395 | virtual const Type *type() const { return TypeInt::INT; } |
| 3396 | |
| 3397 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3398 | |
| 3399 | #ifndef PRODUCT |
| 3400 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3401 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3402 | virtual void dump_spec(outputStream *st) const { |
| 3403 | st->print("#%d", _c0); |
| 3404 | st->print("/0x%08x", _c0); |
| 3405 | } |
| 3406 | virtual const char *Name() const { return "immI_32";} |
| 3407 | #endif |
| 3408 | }; |
| 3409 | |
| 3410 | class immI_64Oper : public MachOper { |
| 3411 | private: |
| 3412 | virtual uint num_edges() const { return 0; } |
| 3413 | int32_t _c0; |
| 3414 | public: |
| 3415 | immI_64Oper(int32_t c0) : _c0(c0) {} |
| 3416 | virtual MachOper *clone() const; |
| 3417 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3418 | virtual uint opcode() const { return IMMI_64; } |
| 3419 | virtual const Type *type() const { return TypeInt::INT; } |
| 3420 | |
| 3421 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3422 | |
| 3423 | #ifndef PRODUCT |
| 3424 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3425 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3426 | virtual void dump_spec(outputStream *st) const { |
| 3427 | st->print("#%d", _c0); |
| 3428 | st->print("/0x%08x", _c0); |
| 3429 | } |
| 3430 | virtual const char *Name() const { return "immI_64";} |
| 3431 | #endif |
| 3432 | }; |
| 3433 | |
| 3434 | class immPOper : public MachOper { |
| 3435 | private: |
| 3436 | virtual uint num_edges() const { return 0; } |
| 3437 | const TypePtr *_c0; |
| 3438 | public: |
| 3439 | immPOper(const TypePtr *c0) : _c0(c0) {} |
| 3440 | virtual MachOper *clone() const; |
| 3441 | virtual uint opcode() const { return IMMP; } |
| 3442 | virtual const Type *type() const { return _c0; } |
| 3443 | |
| 3444 | virtual intptr_t constant() const { return _c0->get_con(); } |
| 3445 | virtual relocInfo::relocType constant_reloc() const { return _c0->reloc(); } |
| 3446 | |
| 3447 | #ifndef PRODUCT |
| 3448 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3449 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3450 | virtual void dump_spec(outputStream *st) const { |
| 3451 | _c0->dump_on(st); |
| 3452 | } |
| 3453 | virtual const char *Name() const { return "immP";} |
| 3454 | #endif |
| 3455 | }; |
| 3456 | |
| 3457 | class immP0Oper : public MachOper { |
| 3458 | private: |
| 3459 | virtual uint num_edges() const { return 0; } |
| 3460 | const TypePtr *_c0; |
| 3461 | public: |
| 3462 | immP0Oper(const TypePtr *c0) : _c0(c0) {} |
| 3463 | virtual MachOper *clone() const; |
| 3464 | virtual uint opcode() const { return IMMP0; } |
| 3465 | virtual const Type *type() const { return _c0; } |
| 3466 | |
| 3467 | virtual intptr_t constant() const { return _c0->get_con(); } |
| 3468 | virtual relocInfo::relocType constant_reloc() const { return _c0->reloc(); } |
| 3469 | |
| 3470 | #ifndef PRODUCT |
| 3471 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3472 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3473 | virtual void dump_spec(outputStream *st) const { |
| 3474 | _c0->dump_on(st); |
| 3475 | } |
| 3476 | virtual const char *Name() const { return "immP0";} |
| 3477 | #endif |
| 3478 | }; |
| 3479 | |
| 3480 | class immNOper : public MachOper { |
| 3481 | private: |
| 3482 | virtual uint num_edges() const { return 0; } |
| 3483 | const TypeNarrowOop *_c0; |
| 3484 | public: |
| 3485 | immNOper(const TypeNarrowOop *c0) : _c0(c0) {} |
| 3486 | virtual MachOper *clone() const; |
| 3487 | virtual uint opcode() const { return IMMN; } |
| 3488 | virtual const Type *type() const { return _c0; } |
| 3489 | |
| 3490 | virtual intptr_t constant() const { return _c0->get_ptrtype()->get_con(); } |
| 3491 | virtual relocInfo::relocType constant_reloc() const { return _c0->get_ptrtype()->reloc(); } |
| 3492 | |
| 3493 | #ifndef PRODUCT |
| 3494 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3495 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3496 | virtual void dump_spec(outputStream *st) const { |
| 3497 | _c0->dump_on(st); |
| 3498 | } |
| 3499 | virtual const char *Name() const { return "immN";} |
| 3500 | #endif |
| 3501 | }; |
| 3502 | |
| 3503 | class immNKlassOper : public MachOper { |
| 3504 | private: |
| 3505 | virtual uint num_edges() const { return 0; } |
| 3506 | const TypeNarrowKlass *_c0; |
| 3507 | public: |
| 3508 | immNKlassOper(const TypeNarrowKlass *c0) : _c0(c0) {} |
| 3509 | virtual MachOper *clone() const; |
| 3510 | virtual uint opcode() const { return IMMNKLASS; } |
| 3511 | virtual const Type *type() const { return _c0; } |
| 3512 | |
| 3513 | virtual intptr_t constant() const { return _c0->get_ptrtype()->get_con(); } |
| 3514 | virtual relocInfo::relocType constant_reloc() const { return _c0->get_ptrtype()->reloc(); } |
| 3515 | |
| 3516 | #ifndef PRODUCT |
| 3517 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3518 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3519 | virtual void dump_spec(outputStream *st) const { |
| 3520 | _c0->dump_on(st); |
| 3521 | } |
| 3522 | virtual const char *Name() const { return "immNKlass";} |
| 3523 | #endif |
| 3524 | }; |
| 3525 | |
| 3526 | class immN0Oper : public MachOper { |
| 3527 | private: |
| 3528 | virtual uint num_edges() const { return 0; } |
| 3529 | const TypeNarrowOop *_c0; |
| 3530 | public: |
| 3531 | immN0Oper(const TypeNarrowOop *c0) : _c0(c0) {} |
| 3532 | virtual MachOper *clone() const; |
| 3533 | virtual uint opcode() const { return IMMN0; } |
| 3534 | virtual const Type *type() const { return _c0; } |
| 3535 | |
| 3536 | virtual intptr_t constant() const { return _c0->get_ptrtype()->get_con(); } |
| 3537 | virtual relocInfo::relocType constant_reloc() const { return _c0->get_ptrtype()->reloc(); } |
| 3538 | |
| 3539 | #ifndef PRODUCT |
| 3540 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3541 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3542 | virtual void dump_spec(outputStream *st) const { |
| 3543 | _c0->dump_on(st); |
| 3544 | } |
| 3545 | virtual const char *Name() const { return "immN0";} |
| 3546 | #endif |
| 3547 | }; |
| 3548 | |
| 3549 | class immP31Oper : public MachOper { |
| 3550 | private: |
| 3551 | virtual uint num_edges() const { return 0; } |
| 3552 | const TypePtr *_c0; |
| 3553 | public: |
| 3554 | immP31Oper(const TypePtr *c0) : _c0(c0) {} |
| 3555 | virtual MachOper *clone() const; |
| 3556 | virtual uint opcode() const { return IMMP31; } |
| 3557 | virtual const Type *type() const { return _c0; } |
| 3558 | |
| 3559 | virtual intptr_t constant() const { return _c0->get_con(); } |
| 3560 | virtual relocInfo::relocType constant_reloc() const { return _c0->reloc(); } |
| 3561 | |
| 3562 | #ifndef PRODUCT |
| 3563 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3564 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3565 | virtual void dump_spec(outputStream *st) const { |
| 3566 | _c0->dump_on(st); |
| 3567 | } |
| 3568 | virtual const char *Name() const { return "immP31";} |
| 3569 | #endif |
| 3570 | }; |
| 3571 | |
| 3572 | class immLOper : public MachOper { |
| 3573 | private: |
| 3574 | virtual uint num_edges() const { return 0; } |
| 3575 | jlong _c0; |
| 3576 | public: |
| 3577 | immLOper(jlong c0) : _c0(c0) {} |
| 3578 | virtual MachOper *clone() const; |
| 3579 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3580 | virtual uint opcode() const { return IMML; } |
| 3581 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3582 | |
| 3583 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3584 | virtual jlong constantL() const { return _c0; } |
| 3585 | |
| 3586 | #ifndef PRODUCT |
| 3587 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3588 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3589 | virtual void dump_spec(outputStream *st) const { |
| 3590 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3591 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3592 | } |
| 3593 | virtual const char *Name() const { return "immL";} |
| 3594 | #endif |
| 3595 | }; |
| 3596 | |
| 3597 | class immL8Oper : public MachOper { |
| 3598 | private: |
| 3599 | virtual uint num_edges() const { return 0; } |
| 3600 | jlong _c0; |
| 3601 | public: |
| 3602 | immL8Oper(jlong c0) : _c0(c0) {} |
| 3603 | virtual MachOper *clone() const; |
| 3604 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3605 | virtual uint opcode() const { return IMML8; } |
| 3606 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3607 | |
| 3608 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3609 | virtual jlong constantL() const { return _c0; } |
| 3610 | |
| 3611 | #ifndef PRODUCT |
| 3612 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3613 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3614 | virtual void dump_spec(outputStream *st) const { |
| 3615 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3616 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3617 | } |
| 3618 | virtual const char *Name() const { return "immL8";} |
| 3619 | #endif |
| 3620 | }; |
| 3621 | |
| 3622 | class immUL32Oper : public MachOper { |
| 3623 | private: |
| 3624 | virtual uint num_edges() const { return 0; } |
| 3625 | jlong _c0; |
| 3626 | public: |
| 3627 | immUL32Oper(jlong c0) : _c0(c0) {} |
| 3628 | virtual MachOper *clone() const; |
| 3629 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3630 | virtual uint opcode() const { return IMMUL32; } |
| 3631 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3632 | |
| 3633 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3634 | virtual jlong constantL() const { return _c0; } |
| 3635 | |
| 3636 | #ifndef PRODUCT |
| 3637 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3638 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3639 | virtual void dump_spec(outputStream *st) const { |
| 3640 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3641 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3642 | } |
| 3643 | virtual const char *Name() const { return "immUL32";} |
| 3644 | #endif |
| 3645 | }; |
| 3646 | |
| 3647 | class immL32Oper : public MachOper { |
| 3648 | private: |
| 3649 | virtual uint num_edges() const { return 0; } |
| 3650 | jlong _c0; |
| 3651 | public: |
| 3652 | immL32Oper(jlong c0) : _c0(c0) {} |
| 3653 | virtual MachOper *clone() const; |
| 3654 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3655 | virtual uint opcode() const { return IMML32; } |
| 3656 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3657 | |
| 3658 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3659 | virtual jlong constantL() const { return _c0; } |
| 3660 | |
| 3661 | #ifndef PRODUCT |
| 3662 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3663 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3664 | virtual void dump_spec(outputStream *st) const { |
| 3665 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3666 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3667 | } |
| 3668 | virtual const char *Name() const { return "immL32";} |
| 3669 | #endif |
| 3670 | }; |
| 3671 | |
| 3672 | class immL0Oper : public MachOper { |
| 3673 | private: |
| 3674 | virtual uint num_edges() const { return 0; } |
| 3675 | jlong _c0; |
| 3676 | public: |
| 3677 | immL0Oper(jlong c0) : _c0(c0) {} |
| 3678 | virtual MachOper *clone() const; |
| 3679 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3680 | virtual uint opcode() const { return IMML0; } |
| 3681 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3682 | |
| 3683 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3684 | virtual jlong constantL() const { return _c0; } |
| 3685 | |
| 3686 | #ifndef PRODUCT |
| 3687 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3688 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3689 | virtual void dump_spec(outputStream *st) const { |
| 3690 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3691 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3692 | } |
| 3693 | virtual const char *Name() const { return "immL0";} |
| 3694 | #endif |
| 3695 | }; |
| 3696 | |
| 3697 | class immL1Oper : public MachOper { |
| 3698 | private: |
| 3699 | virtual uint num_edges() const { return 0; } |
| 3700 | jlong _c0; |
| 3701 | public: |
| 3702 | immL1Oper(jlong c0) : _c0(c0) {} |
| 3703 | virtual MachOper *clone() const; |
| 3704 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3705 | virtual uint opcode() const { return IMML1; } |
| 3706 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3707 | |
| 3708 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3709 | virtual jlong constantL() const { return _c0; } |
| 3710 | |
| 3711 | #ifndef PRODUCT |
| 3712 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3713 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3714 | virtual void dump_spec(outputStream *st) const { |
| 3715 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3716 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3717 | } |
| 3718 | virtual const char *Name() const { return "immL1";} |
| 3719 | #endif |
| 3720 | }; |
| 3721 | |
| 3722 | class immL_M1Oper : public MachOper { |
| 3723 | private: |
| 3724 | virtual uint num_edges() const { return 0; } |
| 3725 | jlong _c0; |
| 3726 | public: |
| 3727 | immL_M1Oper(jlong c0) : _c0(c0) {} |
| 3728 | virtual MachOper *clone() const; |
| 3729 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3730 | virtual uint opcode() const { return IMML_M1; } |
| 3731 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3732 | |
| 3733 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3734 | virtual jlong constantL() const { return _c0; } |
| 3735 | |
| 3736 | #ifndef PRODUCT |
| 3737 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3738 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3739 | virtual void dump_spec(outputStream *st) const { |
| 3740 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3741 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3742 | } |
| 3743 | virtual const char *Name() const { return "immL_M1";} |
| 3744 | #endif |
| 3745 | }; |
| 3746 | |
| 3747 | class immL10Oper : public MachOper { |
| 3748 | private: |
| 3749 | virtual uint num_edges() const { return 0; } |
| 3750 | jlong _c0; |
| 3751 | public: |
| 3752 | immL10Oper(jlong c0) : _c0(c0) {} |
| 3753 | virtual MachOper *clone() const; |
| 3754 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3755 | virtual uint opcode() const { return IMML10; } |
| 3756 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3757 | |
| 3758 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3759 | virtual jlong constantL() const { return _c0; } |
| 3760 | |
| 3761 | #ifndef PRODUCT |
| 3762 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3763 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3764 | virtual void dump_spec(outputStream *st) const { |
| 3765 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3766 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3767 | } |
| 3768 | virtual const char *Name() const { return "immL10";} |
| 3769 | #endif |
| 3770 | }; |
| 3771 | |
| 3772 | class immL_127Oper : public MachOper { |
| 3773 | private: |
| 3774 | virtual uint num_edges() const { return 0; } |
| 3775 | jlong _c0; |
| 3776 | public: |
| 3777 | immL_127Oper(jlong c0) : _c0(c0) {} |
| 3778 | virtual MachOper *clone() const; |
| 3779 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3780 | virtual uint opcode() const { return IMML_127; } |
| 3781 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3782 | |
| 3783 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3784 | virtual jlong constantL() const { return _c0; } |
| 3785 | |
| 3786 | #ifndef PRODUCT |
| 3787 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3788 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3789 | virtual void dump_spec(outputStream *st) const { |
| 3790 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3791 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3792 | } |
| 3793 | virtual const char *Name() const { return "immL_127";} |
| 3794 | #endif |
| 3795 | }; |
| 3796 | |
| 3797 | class immL_32bitsOper : public MachOper { |
| 3798 | private: |
| 3799 | virtual uint num_edges() const { return 0; } |
| 3800 | jlong _c0; |
| 3801 | public: |
| 3802 | immL_32bitsOper(jlong c0) : _c0(c0) {} |
| 3803 | virtual MachOper *clone() const; |
| 3804 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3805 | virtual uint opcode() const { return IMML_32BITS; } |
| 3806 | virtual const Type *type() const { return TypeLong::LONG; } |
| 3807 | |
| 3808 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3809 | virtual jlong constantL() const { return _c0; } |
| 3810 | |
| 3811 | #ifndef PRODUCT |
| 3812 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3813 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3814 | virtual void dump_spec(outputStream *st) const { |
| 3815 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 3816 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 3817 | } |
| 3818 | virtual const char *Name() const { return "immL_32bits";} |
| 3819 | #endif |
| 3820 | }; |
| 3821 | |
| 3822 | class immF0Oper : public MachOper { |
| 3823 | private: |
| 3824 | virtual uint num_edges() const { return 0; } |
| 3825 | jfloat _c0; |
| 3826 | public: |
| 3827 | immF0Oper(jfloat c0) : _c0(c0) {} |
| 3828 | virtual MachOper *clone() const; |
| 3829 | virtual uint opcode() const { return IMMF0; } |
| 3830 | virtual const Type *type() const { return Type::FLOAT; } |
| 3831 | |
| 3832 | virtual intptr_t constant() const { ShouldNotReachHere(); return 0; } |
| 3833 | virtual jfloat constantF() const { return (jfloat)_c0; } |
| 3834 | |
| 3835 | #ifndef PRODUCT |
| 3836 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3837 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3838 | virtual void dump_spec(outputStream *st) const { |
| 3839 | st->print("#%f", _c0); |
| 3840 | jint _c0i = JavaValue(_c0).get_jint(); |
| 3841 | st->print("/0x%x/", _c0i); |
| 3842 | } |
| 3843 | virtual const char *Name() const { return "immF0";} |
| 3844 | #endif |
| 3845 | }; |
| 3846 | |
| 3847 | class immFOper : public MachOper { |
| 3848 | private: |
| 3849 | virtual uint num_edges() const { return 0; } |
| 3850 | jfloat _c0; |
| 3851 | public: |
| 3852 | immFOper(jfloat c0) : _c0(c0) {} |
| 3853 | virtual MachOper *clone() const; |
| 3854 | virtual uint opcode() const { return IMMF; } |
| 3855 | virtual const Type *type() const { return Type::FLOAT; } |
| 3856 | |
| 3857 | virtual intptr_t constant() const { ShouldNotReachHere(); return 0; } |
| 3858 | virtual jfloat constantF() const { return (jfloat)_c0; } |
| 3859 | |
| 3860 | #ifndef PRODUCT |
| 3861 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3862 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3863 | virtual void dump_spec(outputStream *st) const { |
| 3864 | st->print("#%f", _c0); |
| 3865 | jint _c0i = JavaValue(_c0).get_jint(); |
| 3866 | st->print("/0x%x/", _c0i); |
| 3867 | } |
| 3868 | virtual const char *Name() const { return "immF";} |
| 3869 | #endif |
| 3870 | }; |
| 3871 | |
| 3872 | class immD0Oper : public MachOper { |
| 3873 | private: |
| 3874 | virtual uint num_edges() const { return 0; } |
| 3875 | jdouble _c0; |
| 3876 | public: |
| 3877 | immD0Oper(jdouble c0) : _c0(c0) {} |
| 3878 | virtual MachOper *clone() const; |
| 3879 | virtual uint opcode() const { return IMMD0; } |
| 3880 | virtual const Type *type() const { return Type::DOUBLE; } |
| 3881 | |
| 3882 | virtual intptr_t constant() const { ShouldNotReachHere(); return 0; } |
| 3883 | virtual jdouble constantD() const { return _c0; } |
| 3884 | |
| 3885 | #ifndef PRODUCT |
| 3886 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3887 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3888 | virtual void dump_spec(outputStream *st) const { |
| 3889 | st->print("#%f", _c0); |
| 3890 | jlong _c0l = JavaValue(_c0).get_jlong(); |
| 3891 | st->print("/"PTR64_FORMAT, (uint64_t)_c0l); |
| 3892 | } |
| 3893 | virtual const char *Name() const { return "immD0";} |
| 3894 | #endif |
| 3895 | }; |
| 3896 | |
| 3897 | class immDOper : public MachOper { |
| 3898 | private: |
| 3899 | virtual uint num_edges() const { return 0; } |
| 3900 | jdouble _c0; |
| 3901 | public: |
| 3902 | immDOper(jdouble c0) : _c0(c0) {} |
| 3903 | virtual MachOper *clone() const; |
| 3904 | virtual uint opcode() const { return IMMD; } |
| 3905 | virtual const Type *type() const { return Type::DOUBLE; } |
| 3906 | |
| 3907 | virtual intptr_t constant() const { ShouldNotReachHere(); return 0; } |
| 3908 | virtual jdouble constantD() const { return _c0; } |
| 3909 | |
| 3910 | #ifndef PRODUCT |
| 3911 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3912 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3913 | virtual void dump_spec(outputStream *st) const { |
| 3914 | st->print("#%f", _c0); |
| 3915 | jlong _c0l = JavaValue(_c0).get_jlong(); |
| 3916 | st->print("/"PTR64_FORMAT, (uint64_t)_c0l); |
| 3917 | } |
| 3918 | virtual const char *Name() const { return "immD";} |
| 3919 | #endif |
| 3920 | }; |
| 3921 | |
| 3922 | class immI_16Oper : public MachOper { |
| 3923 | private: |
| 3924 | virtual uint num_edges() const { return 0; } |
| 3925 | int32_t _c0; |
| 3926 | public: |
| 3927 | immI_16Oper(int32_t c0) : _c0(c0) {} |
| 3928 | virtual MachOper *clone() const; |
| 3929 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3930 | virtual uint opcode() const { return IMMI_16; } |
| 3931 | virtual const Type *type() const { return TypeInt::INT; } |
| 3932 | |
| 3933 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3934 | |
| 3935 | #ifndef PRODUCT |
| 3936 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3937 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3938 | virtual void dump_spec(outputStream *st) const { |
| 3939 | st->print("#%d", _c0); |
| 3940 | st->print("/0x%08x", _c0); |
| 3941 | } |
| 3942 | virtual const char *Name() const { return "immI_16";} |
| 3943 | #endif |
| 3944 | }; |
| 3945 | |
| 3946 | class immI_24Oper : public MachOper { |
| 3947 | private: |
| 3948 | virtual uint num_edges() const { return 0; } |
| 3949 | int32_t _c0; |
| 3950 | public: |
| 3951 | immI_24Oper(int32_t c0) : _c0(c0) {} |
| 3952 | virtual MachOper *clone() const; |
| 3953 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3954 | virtual uint opcode() const { return IMMI_24; } |
| 3955 | virtual const Type *type() const { return TypeInt::INT; } |
| 3956 | |
| 3957 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3958 | |
| 3959 | #ifndef PRODUCT |
| 3960 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3961 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3962 | virtual void dump_spec(outputStream *st) const { |
| 3963 | st->print("#%d", _c0); |
| 3964 | st->print("/0x%08x", _c0); |
| 3965 | } |
| 3966 | virtual const char *Name() const { return "immI_24";} |
| 3967 | #endif |
| 3968 | }; |
| 3969 | |
| 3970 | class immI_255Oper : public MachOper { |
| 3971 | private: |
| 3972 | virtual uint num_edges() const { return 0; } |
| 3973 | int32_t _c0; |
| 3974 | public: |
| 3975 | immI_255Oper(int32_t c0) : _c0(c0) {} |
| 3976 | virtual MachOper *clone() const; |
| 3977 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 3978 | virtual uint opcode() const { return IMMI_255; } |
| 3979 | virtual const Type *type() const { return TypeInt::INT; } |
| 3980 | |
| 3981 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 3982 | |
| 3983 | #ifndef PRODUCT |
| 3984 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 3985 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 3986 | virtual void dump_spec(outputStream *st) const { |
| 3987 | st->print("#%d", _c0); |
| 3988 | st->print("/0x%08x", _c0); |
| 3989 | } |
| 3990 | virtual const char *Name() const { return "immI_255";} |
| 3991 | #endif |
| 3992 | }; |
| 3993 | |
| 3994 | class immI_65535Oper : public MachOper { |
| 3995 | private: |
| 3996 | virtual uint num_edges() const { return 0; } |
| 3997 | int32_t _c0; |
| 3998 | public: |
| 3999 | immI_65535Oper(int32_t c0) : _c0(c0) {} |
| 4000 | virtual MachOper *clone() const; |
| 4001 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4002 | virtual uint opcode() const { return IMMI_65535; } |
| 4003 | virtual const Type *type() const { return TypeInt::INT; } |
| 4004 | |
| 4005 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 4006 | |
| 4007 | #ifndef PRODUCT |
| 4008 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4009 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4010 | virtual void dump_spec(outputStream *st) const { |
| 4011 | st->print("#%d", _c0); |
| 4012 | st->print("/0x%08x", _c0); |
| 4013 | } |
| 4014 | virtual const char *Name() const { return "immI_65535";} |
| 4015 | #endif |
| 4016 | }; |
| 4017 | |
| 4018 | class immL_255Oper : public MachOper { |
| 4019 | private: |
| 4020 | virtual uint num_edges() const { return 0; } |
| 4021 | jlong _c0; |
| 4022 | public: |
| 4023 | immL_255Oper(jlong c0) : _c0(c0) {} |
| 4024 | virtual MachOper *clone() const; |
| 4025 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4026 | virtual uint opcode() const { return IMML_255; } |
| 4027 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4028 | |
| 4029 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 4030 | virtual jlong constantL() const { return _c0; } |
| 4031 | |
| 4032 | #ifndef PRODUCT |
| 4033 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4034 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4035 | virtual void dump_spec(outputStream *st) const { |
| 4036 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 4037 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 4038 | } |
| 4039 | virtual const char *Name() const { return "immL_255";} |
| 4040 | #endif |
| 4041 | }; |
| 4042 | |
| 4043 | class immL_65535Oper : public MachOper { |
| 4044 | private: |
| 4045 | virtual uint num_edges() const { return 0; } |
| 4046 | jlong _c0; |
| 4047 | public: |
| 4048 | immL_65535Oper(jlong c0) : _c0(c0) {} |
| 4049 | virtual MachOper *clone() const; |
| 4050 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4051 | virtual uint opcode() const { return IMML_65535; } |
| 4052 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4053 | |
| 4054 | virtual intptr_t constant() const { return (intptr_t)_c0; } |
| 4055 | virtual jlong constantL() const { return _c0; } |
| 4056 | |
| 4057 | #ifndef PRODUCT |
| 4058 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4059 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4060 | virtual void dump_spec(outputStream *st) const { |
| 4061 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 4062 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 4063 | } |
| 4064 | virtual const char *Name() const { return "immL_65535";} |
| 4065 | #endif |
| 4066 | }; |
| 4067 | |
| 4068 | class rRegIOper : public MachOper { |
| 4069 | private: |
| 4070 | virtual const RegMask *in_RegMask(int index) const; |
| 4071 | public: |
| 4072 | rRegIOper() {} |
| 4073 | virtual MachOper *clone() const; |
| 4074 | virtual uint opcode() const { return RREGI; } |
| 4075 | virtual const Type *type() const { return TypeInt::INT; } |
| 4076 | |
| 4077 | |
| 4078 | #ifndef PRODUCT |
| 4079 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4080 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4081 | virtual const char *Name() const { return "rRegI";} |
| 4082 | #endif |
| 4083 | }; |
| 4084 | |
| 4085 | class rax_RegIOper : public MachOper { |
| 4086 | private: |
| 4087 | virtual const RegMask *in_RegMask(int index) const; |
| 4088 | public: |
| 4089 | rax_RegIOper() {} |
| 4090 | virtual MachOper *clone() const; |
| 4091 | virtual uint opcode() const { return RAX_REGI; } |
| 4092 | virtual const Type *type() const { return TypeInt::INT; } |
| 4093 | |
| 4094 | |
| 4095 | #ifndef PRODUCT |
| 4096 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4097 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4098 | virtual const char *Name() const { return "rax_RegI";} |
| 4099 | #endif |
| 4100 | }; |
| 4101 | |
| 4102 | class rbx_RegIOper : public MachOper { |
| 4103 | private: |
| 4104 | virtual const RegMask *in_RegMask(int index) const; |
| 4105 | public: |
| 4106 | rbx_RegIOper() {} |
| 4107 | virtual MachOper *clone() const; |
| 4108 | virtual uint opcode() const { return RBX_REGI; } |
| 4109 | virtual const Type *type() const { return TypeInt::INT; } |
| 4110 | |
| 4111 | |
| 4112 | #ifndef PRODUCT |
| 4113 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4114 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4115 | virtual const char *Name() const { return "rbx_RegI";} |
| 4116 | #endif |
| 4117 | }; |
| 4118 | |
| 4119 | class rcx_RegIOper : public MachOper { |
| 4120 | private: |
| 4121 | virtual const RegMask *in_RegMask(int index) const; |
| 4122 | public: |
| 4123 | rcx_RegIOper() {} |
| 4124 | virtual MachOper *clone() const; |
| 4125 | virtual uint opcode() const { return RCX_REGI; } |
| 4126 | virtual const Type *type() const { return TypeInt::INT; } |
| 4127 | |
| 4128 | |
| 4129 | #ifndef PRODUCT |
| 4130 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4131 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4132 | virtual const char *Name() const { return "rcx_RegI";} |
| 4133 | #endif |
| 4134 | }; |
| 4135 | |
| 4136 | class rdx_RegIOper : public MachOper { |
| 4137 | private: |
| 4138 | virtual const RegMask *in_RegMask(int index) const; |
| 4139 | public: |
| 4140 | rdx_RegIOper() {} |
| 4141 | virtual MachOper *clone() const; |
| 4142 | virtual uint opcode() const { return RDX_REGI; } |
| 4143 | virtual const Type *type() const { return TypeInt::INT; } |
| 4144 | |
| 4145 | |
| 4146 | #ifndef PRODUCT |
| 4147 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4148 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4149 | virtual const char *Name() const { return "rdx_RegI";} |
| 4150 | #endif |
| 4151 | }; |
| 4152 | |
| 4153 | class rdi_RegIOper : public MachOper { |
| 4154 | private: |
| 4155 | virtual const RegMask *in_RegMask(int index) const; |
| 4156 | public: |
| 4157 | rdi_RegIOper() {} |
| 4158 | virtual MachOper *clone() const; |
| 4159 | virtual uint opcode() const { return RDI_REGI; } |
| 4160 | virtual const Type *type() const { return TypeInt::INT; } |
| 4161 | |
| 4162 | |
| 4163 | #ifndef PRODUCT |
| 4164 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4165 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4166 | virtual const char *Name() const { return "rdi_RegI";} |
| 4167 | #endif |
| 4168 | }; |
| 4169 | |
| 4170 | class no_rcx_RegIOper : public MachOper { |
| 4171 | private: |
| 4172 | virtual const RegMask *in_RegMask(int index) const; |
| 4173 | public: |
| 4174 | no_rcx_RegIOper() {} |
| 4175 | virtual MachOper *clone() const; |
| 4176 | virtual uint opcode() const { return NO_RCX_REGI; } |
| 4177 | virtual const Type *type() const { return TypeInt::INT; } |
| 4178 | |
| 4179 | |
| 4180 | #ifndef PRODUCT |
| 4181 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4182 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4183 | virtual const char *Name() const { return "no_rcx_RegI";} |
| 4184 | #endif |
| 4185 | }; |
| 4186 | |
| 4187 | class no_rax_rdx_RegIOper : public MachOper { |
| 4188 | private: |
| 4189 | virtual const RegMask *in_RegMask(int index) const; |
| 4190 | public: |
| 4191 | no_rax_rdx_RegIOper() {} |
| 4192 | virtual MachOper *clone() const; |
| 4193 | virtual uint opcode() const { return NO_RAX_RDX_REGI; } |
| 4194 | virtual const Type *type() const { return TypeInt::INT; } |
| 4195 | |
| 4196 | |
| 4197 | #ifndef PRODUCT |
| 4198 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4199 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4200 | virtual const char *Name() const { return "no_rax_rdx_RegI";} |
| 4201 | #endif |
| 4202 | }; |
| 4203 | |
| 4204 | class any_RegPOper : public MachOper { |
| 4205 | private: |
| 4206 | virtual const RegMask *in_RegMask(int index) const; |
| 4207 | public: |
| 4208 | any_RegPOper() {} |
| 4209 | virtual MachOper *clone() const; |
| 4210 | virtual uint opcode() const { return ANY_REGP; } |
| 4211 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4212 | |
| 4213 | |
| 4214 | #ifndef PRODUCT |
| 4215 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4216 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4217 | virtual const char *Name() const { return "any_RegP";} |
| 4218 | #endif |
| 4219 | }; |
| 4220 | |
| 4221 | class rRegPOper : public MachOper { |
| 4222 | private: |
| 4223 | virtual const RegMask *in_RegMask(int index) const; |
| 4224 | public: |
| 4225 | rRegPOper() {} |
| 4226 | virtual MachOper *clone() const; |
| 4227 | virtual uint opcode() const { return RREGP; } |
| 4228 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4229 | |
| 4230 | |
| 4231 | #ifndef PRODUCT |
| 4232 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4233 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4234 | virtual const char *Name() const { return "rRegP";} |
| 4235 | #endif |
| 4236 | }; |
| 4237 | |
| 4238 | class rRegNOper : public MachOper { |
| 4239 | private: |
| 4240 | virtual const RegMask *in_RegMask(int index) const; |
| 4241 | public: |
| 4242 | rRegNOper() {} |
| 4243 | virtual MachOper *clone() const; |
| 4244 | virtual uint opcode() const { return RREGN; } |
| 4245 | virtual const Type *type() const { return TypeNarrowOop::BOTTOM; } |
| 4246 | |
| 4247 | |
| 4248 | #ifndef PRODUCT |
| 4249 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4250 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4251 | virtual const char *Name() const { return "rRegN";} |
| 4252 | #endif |
| 4253 | }; |
| 4254 | |
| 4255 | class no_rax_RegPOper : public MachOper { |
| 4256 | private: |
| 4257 | virtual const RegMask *in_RegMask(int index) const; |
| 4258 | public: |
| 4259 | no_rax_RegPOper() {} |
| 4260 | virtual MachOper *clone() const; |
| 4261 | virtual uint opcode() const { return NO_RAX_REGP; } |
| 4262 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4263 | |
| 4264 | |
| 4265 | #ifndef PRODUCT |
| 4266 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4267 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4268 | virtual const char *Name() const { return "no_rax_RegP";} |
| 4269 | #endif |
| 4270 | }; |
| 4271 | |
| 4272 | class no_rbp_RegPOper : public MachOper { |
| 4273 | private: |
| 4274 | virtual const RegMask *in_RegMask(int index) const; |
| 4275 | public: |
| 4276 | no_rbp_RegPOper() {} |
| 4277 | virtual MachOper *clone() const; |
| 4278 | virtual uint opcode() const { return NO_RBP_REGP; } |
| 4279 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4280 | |
| 4281 | |
| 4282 | #ifndef PRODUCT |
| 4283 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4284 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4285 | virtual const char *Name() const { return "no_rbp_RegP";} |
| 4286 | #endif |
| 4287 | }; |
| 4288 | |
| 4289 | class no_rax_rbx_RegPOper : public MachOper { |
| 4290 | private: |
| 4291 | virtual const RegMask *in_RegMask(int index) const; |
| 4292 | public: |
| 4293 | no_rax_rbx_RegPOper() {} |
| 4294 | virtual MachOper *clone() const; |
| 4295 | virtual uint opcode() const { return NO_RAX_RBX_REGP; } |
| 4296 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4297 | |
| 4298 | |
| 4299 | #ifndef PRODUCT |
| 4300 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4301 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4302 | virtual const char *Name() const { return "no_rax_rbx_RegP";} |
| 4303 | #endif |
| 4304 | }; |
| 4305 | |
| 4306 | class rax_RegPOper : public MachOper { |
| 4307 | private: |
| 4308 | virtual const RegMask *in_RegMask(int index) const; |
| 4309 | public: |
| 4310 | rax_RegPOper() {} |
| 4311 | virtual MachOper *clone() const; |
| 4312 | virtual uint opcode() const { return RAX_REGP; } |
| 4313 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4314 | |
| 4315 | |
| 4316 | #ifndef PRODUCT |
| 4317 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4318 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4319 | virtual const char *Name() const { return "rax_RegP";} |
| 4320 | #endif |
| 4321 | }; |
| 4322 | |
| 4323 | class rax_RegNOper : public MachOper { |
| 4324 | private: |
| 4325 | virtual const RegMask *in_RegMask(int index) const; |
| 4326 | public: |
| 4327 | rax_RegNOper() {} |
| 4328 | virtual MachOper *clone() const; |
| 4329 | virtual uint opcode() const { return RAX_REGN; } |
| 4330 | virtual const Type *type() const { return TypeNarrowOop::BOTTOM; } |
| 4331 | |
| 4332 | |
| 4333 | #ifndef PRODUCT |
| 4334 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4335 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4336 | virtual const char *Name() const { return "rax_RegN";} |
| 4337 | #endif |
| 4338 | }; |
| 4339 | |
| 4340 | class rbx_RegPOper : public MachOper { |
| 4341 | private: |
| 4342 | virtual const RegMask *in_RegMask(int index) const; |
| 4343 | public: |
| 4344 | rbx_RegPOper() {} |
| 4345 | virtual MachOper *clone() const; |
| 4346 | virtual uint opcode() const { return RBX_REGP; } |
| 4347 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4348 | |
| 4349 | |
| 4350 | #ifndef PRODUCT |
| 4351 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4352 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4353 | virtual const char *Name() const { return "rbx_RegP";} |
| 4354 | #endif |
| 4355 | }; |
| 4356 | |
| 4357 | class rsi_RegPOper : public MachOper { |
| 4358 | private: |
| 4359 | virtual const RegMask *in_RegMask(int index) const; |
| 4360 | public: |
| 4361 | rsi_RegPOper() {} |
| 4362 | virtual MachOper *clone() const; |
| 4363 | virtual uint opcode() const { return RSI_REGP; } |
| 4364 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4365 | |
| 4366 | |
| 4367 | #ifndef PRODUCT |
| 4368 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4369 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4370 | virtual const char *Name() const { return "rsi_RegP";} |
| 4371 | #endif |
| 4372 | }; |
| 4373 | |
| 4374 | class rdi_RegPOper : public MachOper { |
| 4375 | private: |
| 4376 | virtual const RegMask *in_RegMask(int index) const; |
| 4377 | public: |
| 4378 | rdi_RegPOper() {} |
| 4379 | virtual MachOper *clone() const; |
| 4380 | virtual uint opcode() const { return RDI_REGP; } |
| 4381 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4382 | |
| 4383 | |
| 4384 | #ifndef PRODUCT |
| 4385 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4386 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4387 | virtual const char *Name() const { return "rdi_RegP";} |
| 4388 | #endif |
| 4389 | }; |
| 4390 | |
| 4391 | class r15_RegPOper : public MachOper { |
| 4392 | private: |
| 4393 | virtual const RegMask *in_RegMask(int index) const; |
| 4394 | public: |
| 4395 | r15_RegPOper() {} |
| 4396 | virtual MachOper *clone() const; |
| 4397 | virtual uint opcode() const { return R15_REGP; } |
| 4398 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4399 | |
| 4400 | |
| 4401 | #ifndef PRODUCT |
| 4402 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4403 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4404 | virtual const char *Name() const { return "r15_RegP";} |
| 4405 | #endif |
| 4406 | }; |
| 4407 | |
| 4408 | class rRegLOper : public MachOper { |
| 4409 | private: |
| 4410 | virtual const RegMask *in_RegMask(int index) const; |
| 4411 | public: |
| 4412 | rRegLOper() {} |
| 4413 | virtual MachOper *clone() const; |
| 4414 | virtual uint opcode() const { return RREGL; } |
| 4415 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4416 | |
| 4417 | |
| 4418 | #ifndef PRODUCT |
| 4419 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4420 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4421 | virtual const char *Name() const { return "rRegL";} |
| 4422 | #endif |
| 4423 | }; |
| 4424 | |
| 4425 | class no_rax_rdx_RegLOper : public MachOper { |
| 4426 | private: |
| 4427 | virtual const RegMask *in_RegMask(int index) const; |
| 4428 | public: |
| 4429 | no_rax_rdx_RegLOper() {} |
| 4430 | virtual MachOper *clone() const; |
| 4431 | virtual uint opcode() const { return NO_RAX_RDX_REGL; } |
| 4432 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4433 | |
| 4434 | |
| 4435 | #ifndef PRODUCT |
| 4436 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4437 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4438 | virtual const char *Name() const { return "no_rax_rdx_RegL";} |
| 4439 | #endif |
| 4440 | }; |
| 4441 | |
| 4442 | class no_rax_RegLOper : public MachOper { |
| 4443 | private: |
| 4444 | virtual const RegMask *in_RegMask(int index) const; |
| 4445 | public: |
| 4446 | no_rax_RegLOper() {} |
| 4447 | virtual MachOper *clone() const; |
| 4448 | virtual uint opcode() const { return NO_RAX_REGL; } |
| 4449 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4450 | |
| 4451 | |
| 4452 | #ifndef PRODUCT |
| 4453 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4454 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4455 | virtual const char *Name() const { return "no_rax_RegL";} |
| 4456 | #endif |
| 4457 | }; |
| 4458 | |
| 4459 | class no_rcx_RegLOper : public MachOper { |
| 4460 | private: |
| 4461 | virtual const RegMask *in_RegMask(int index) const; |
| 4462 | public: |
| 4463 | no_rcx_RegLOper() {} |
| 4464 | virtual MachOper *clone() const; |
| 4465 | virtual uint opcode() const { return NO_RCX_REGL; } |
| 4466 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4467 | |
| 4468 | |
| 4469 | #ifndef PRODUCT |
| 4470 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4471 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4472 | virtual const char *Name() const { return "no_rcx_RegL";} |
| 4473 | #endif |
| 4474 | }; |
| 4475 | |
| 4476 | class rax_RegLOper : public MachOper { |
| 4477 | private: |
| 4478 | virtual const RegMask *in_RegMask(int index) const; |
| 4479 | public: |
| 4480 | rax_RegLOper() {} |
| 4481 | virtual MachOper *clone() const; |
| 4482 | virtual uint opcode() const { return RAX_REGL; } |
| 4483 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4484 | |
| 4485 | |
| 4486 | #ifndef PRODUCT |
| 4487 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4488 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4489 | virtual const char *Name() const { return "rax_RegL";} |
| 4490 | #endif |
| 4491 | }; |
| 4492 | |
| 4493 | class rcx_RegLOper : public MachOper { |
| 4494 | private: |
| 4495 | virtual const RegMask *in_RegMask(int index) const; |
| 4496 | public: |
| 4497 | rcx_RegLOper() {} |
| 4498 | virtual MachOper *clone() const; |
| 4499 | virtual uint opcode() const { return RCX_REGL; } |
| 4500 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4501 | |
| 4502 | |
| 4503 | #ifndef PRODUCT |
| 4504 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4505 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4506 | virtual const char *Name() const { return "rcx_RegL";} |
| 4507 | #endif |
| 4508 | }; |
| 4509 | |
| 4510 | class rdx_RegLOper : public MachOper { |
| 4511 | private: |
| 4512 | virtual const RegMask *in_RegMask(int index) const; |
| 4513 | public: |
| 4514 | rdx_RegLOper() {} |
| 4515 | virtual MachOper *clone() const; |
| 4516 | virtual uint opcode() const { return RDX_REGL; } |
| 4517 | virtual const Type *type() const { return TypeLong::LONG; } |
| 4518 | |
| 4519 | |
| 4520 | #ifndef PRODUCT |
| 4521 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4522 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4523 | virtual const char *Name() const { return "rdx_RegL";} |
| 4524 | #endif |
| 4525 | }; |
| 4526 | |
| 4527 | class rFlagsRegOper : public MachOper { |
| 4528 | private: |
| 4529 | virtual const RegMask *in_RegMask(int index) const; |
| 4530 | public: |
| 4531 | rFlagsRegOper() {} |
| 4532 | virtual MachOper *clone() const; |
| 4533 | virtual uint opcode() const { return RFLAGSREG; } |
| 4534 | virtual const Type *type() const { return TypeInt::CC /*flags*/; } |
| 4535 | |
| 4536 | |
| 4537 | #ifndef PRODUCT |
| 4538 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4539 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4540 | virtual const char *Name() const { return "rFlagsReg";} |
| 4541 | #endif |
| 4542 | }; |
| 4543 | |
| 4544 | class rFlagsRegUOper : public MachOper { |
| 4545 | private: |
| 4546 | virtual const RegMask *in_RegMask(int index) const; |
| 4547 | public: |
| 4548 | rFlagsRegUOper() {} |
| 4549 | virtual MachOper *clone() const; |
| 4550 | virtual uint opcode() const { return RFLAGSREGU; } |
| 4551 | virtual const Type *type() const { return TypeInt::CC /*flags*/; } |
| 4552 | |
| 4553 | |
| 4554 | #ifndef PRODUCT |
| 4555 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4556 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4557 | virtual const char *Name() const { return "rFlagsRegU";} |
| 4558 | #endif |
| 4559 | }; |
| 4560 | |
| 4561 | class rFlagsRegUCFOper : public MachOper { |
| 4562 | private: |
| 4563 | virtual const RegMask *in_RegMask(int index) const; |
| 4564 | public: |
| 4565 | rFlagsRegUCFOper() {} |
| 4566 | virtual MachOper *clone() const; |
| 4567 | virtual uint opcode() const { return RFLAGSREGUCF; } |
| 4568 | virtual const Type *type() const { return TypeInt::CC /*flags*/; } |
| 4569 | |
| 4570 | |
| 4571 | #ifndef PRODUCT |
| 4572 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4573 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4574 | virtual const char *Name() const { return "rFlagsRegUCF";} |
| 4575 | #endif |
| 4576 | }; |
| 4577 | |
| 4578 | class regFOper : public MachOper { |
| 4579 | private: |
| 4580 | virtual const RegMask *in_RegMask(int index) const; |
| 4581 | public: |
| 4582 | regFOper() {} |
| 4583 | virtual MachOper *clone() const; |
| 4584 | virtual uint opcode() const { return REGF; } |
| 4585 | virtual const Type *type() const { return Type::FLOAT; } |
| 4586 | |
| 4587 | |
| 4588 | #ifndef PRODUCT |
| 4589 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4590 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4591 | virtual const char *Name() const { return "regF";} |
| 4592 | #endif |
| 4593 | }; |
| 4594 | |
| 4595 | class legRegFOper : public MachOper { |
| 4596 | private: |
| 4597 | virtual const RegMask *in_RegMask(int index) const; |
| 4598 | public: |
| 4599 | legRegFOper() {} |
| 4600 | virtual MachOper *clone() const; |
| 4601 | virtual uint opcode() const { return LEGREGF; } |
| 4602 | virtual const Type *type() const { return Type::FLOAT; } |
| 4603 | |
| 4604 | |
| 4605 | #ifndef PRODUCT |
| 4606 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4607 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4608 | virtual const char *Name() const { return "legRegF";} |
| 4609 | #endif |
| 4610 | }; |
| 4611 | |
| 4612 | class vlRegFOper : public MachOper { |
| 4613 | private: |
| 4614 | virtual const RegMask *in_RegMask(int index) const; |
| 4615 | public: |
| 4616 | vlRegFOper() {} |
| 4617 | virtual MachOper *clone() const; |
| 4618 | virtual uint opcode() const { return VLREGF; } |
| 4619 | virtual const Type *type() const { return Type::FLOAT; } |
| 4620 | |
| 4621 | |
| 4622 | #ifndef PRODUCT |
| 4623 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4624 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4625 | virtual const char *Name() const { return "vlRegF";} |
| 4626 | #endif |
| 4627 | }; |
| 4628 | |
| 4629 | class regDOper : public MachOper { |
| 4630 | private: |
| 4631 | virtual const RegMask *in_RegMask(int index) const; |
| 4632 | public: |
| 4633 | regDOper() {} |
| 4634 | virtual MachOper *clone() const; |
| 4635 | virtual uint opcode() const { return REGD; } |
| 4636 | virtual const Type *type() const { return Type::DOUBLE; } |
| 4637 | |
| 4638 | |
| 4639 | #ifndef PRODUCT |
| 4640 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4641 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4642 | virtual const char *Name() const { return "regD";} |
| 4643 | #endif |
| 4644 | }; |
| 4645 | |
| 4646 | class legRegDOper : public MachOper { |
| 4647 | private: |
| 4648 | virtual const RegMask *in_RegMask(int index) const; |
| 4649 | public: |
| 4650 | legRegDOper() {} |
| 4651 | virtual MachOper *clone() const; |
| 4652 | virtual uint opcode() const { return LEGREGD; } |
| 4653 | virtual const Type *type() const { return Type::DOUBLE; } |
| 4654 | |
| 4655 | |
| 4656 | #ifndef PRODUCT |
| 4657 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4658 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4659 | virtual const char *Name() const { return "legRegD";} |
| 4660 | #endif |
| 4661 | }; |
| 4662 | |
| 4663 | class vlRegDOper : public MachOper { |
| 4664 | private: |
| 4665 | virtual const RegMask *in_RegMask(int index) const; |
| 4666 | public: |
| 4667 | vlRegDOper() {} |
| 4668 | virtual MachOper *clone() const; |
| 4669 | virtual uint opcode() const { return VLREGD; } |
| 4670 | virtual const Type *type() const { return Type::DOUBLE; } |
| 4671 | |
| 4672 | |
| 4673 | #ifndef PRODUCT |
| 4674 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4675 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4676 | virtual const char *Name() const { return "vlRegD";} |
| 4677 | #endif |
| 4678 | }; |
| 4679 | |
| 4680 | class vecSOper : public MachOper { |
| 4681 | private: |
| 4682 | virtual const RegMask *in_RegMask(int index) const; |
| 4683 | public: |
| 4684 | vecSOper() {} |
| 4685 | virtual MachOper *clone() const; |
| 4686 | virtual uint opcode() const { return VECS; } |
| 4687 | virtual const Type *type() const { return TypeVect::VECTS; } |
| 4688 | |
| 4689 | |
| 4690 | #ifndef PRODUCT |
| 4691 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4692 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4693 | virtual const char *Name() const { return "vecS";} |
| 4694 | #endif |
| 4695 | }; |
| 4696 | |
| 4697 | class legVecSOper : public MachOper { |
| 4698 | private: |
| 4699 | virtual const RegMask *in_RegMask(int index) const; |
| 4700 | public: |
| 4701 | legVecSOper() {} |
| 4702 | virtual MachOper *clone() const; |
| 4703 | virtual uint opcode() const { return LEGVECS; } |
| 4704 | virtual const Type *type() const { return TypeVect::VECTS; } |
| 4705 | |
| 4706 | |
| 4707 | #ifndef PRODUCT |
| 4708 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4709 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4710 | virtual const char *Name() const { return "legVecS";} |
| 4711 | #endif |
| 4712 | }; |
| 4713 | |
| 4714 | class vecDOper : public MachOper { |
| 4715 | private: |
| 4716 | virtual const RegMask *in_RegMask(int index) const; |
| 4717 | public: |
| 4718 | vecDOper() {} |
| 4719 | virtual MachOper *clone() const; |
| 4720 | virtual uint opcode() const { return VECD; } |
| 4721 | virtual const Type *type() const { return TypeVect::VECTD; } |
| 4722 | |
| 4723 | |
| 4724 | #ifndef PRODUCT |
| 4725 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4726 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4727 | virtual const char *Name() const { return "vecD";} |
| 4728 | #endif |
| 4729 | }; |
| 4730 | |
| 4731 | class legVecDOper : public MachOper { |
| 4732 | private: |
| 4733 | virtual const RegMask *in_RegMask(int index) const; |
| 4734 | public: |
| 4735 | legVecDOper() {} |
| 4736 | virtual MachOper *clone() const; |
| 4737 | virtual uint opcode() const { return LEGVECD; } |
| 4738 | virtual const Type *type() const { return TypeVect::VECTD; } |
| 4739 | |
| 4740 | |
| 4741 | #ifndef PRODUCT |
| 4742 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4743 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4744 | virtual const char *Name() const { return "legVecD";} |
| 4745 | #endif |
| 4746 | }; |
| 4747 | |
| 4748 | class vecXOper : public MachOper { |
| 4749 | private: |
| 4750 | virtual const RegMask *in_RegMask(int index) const; |
| 4751 | public: |
| 4752 | vecXOper() {} |
| 4753 | virtual MachOper *clone() const; |
| 4754 | virtual uint opcode() const { return VECX; } |
| 4755 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 4756 | |
| 4757 | |
| 4758 | #ifndef PRODUCT |
| 4759 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4760 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4761 | virtual const char *Name() const { return "vecX";} |
| 4762 | #endif |
| 4763 | }; |
| 4764 | |
| 4765 | class legVecXOper : public MachOper { |
| 4766 | private: |
| 4767 | virtual const RegMask *in_RegMask(int index) const; |
| 4768 | public: |
| 4769 | legVecXOper() {} |
| 4770 | virtual MachOper *clone() const; |
| 4771 | virtual uint opcode() const { return LEGVECX; } |
| 4772 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 4773 | |
| 4774 | |
| 4775 | #ifndef PRODUCT |
| 4776 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4777 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4778 | virtual const char *Name() const { return "legVecX";} |
| 4779 | #endif |
| 4780 | }; |
| 4781 | |
| 4782 | class vecYOper : public MachOper { |
| 4783 | private: |
| 4784 | virtual const RegMask *in_RegMask(int index) const; |
| 4785 | public: |
| 4786 | vecYOper() {} |
| 4787 | virtual MachOper *clone() const; |
| 4788 | virtual uint opcode() const { return VECY; } |
| 4789 | virtual const Type *type() const { return TypeVect::VECTY; } |
| 4790 | |
| 4791 | |
| 4792 | #ifndef PRODUCT |
| 4793 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4794 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4795 | virtual const char *Name() const { return "vecY";} |
| 4796 | #endif |
| 4797 | }; |
| 4798 | |
| 4799 | class legVecYOper : public MachOper { |
| 4800 | private: |
| 4801 | virtual const RegMask *in_RegMask(int index) const; |
| 4802 | public: |
| 4803 | legVecYOper() {} |
| 4804 | virtual MachOper *clone() const; |
| 4805 | virtual uint opcode() const { return LEGVECY; } |
| 4806 | virtual const Type *type() const { return TypeVect::VECTY; } |
| 4807 | |
| 4808 | |
| 4809 | #ifndef PRODUCT |
| 4810 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4811 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4812 | virtual const char *Name() const { return "legVecY";} |
| 4813 | #endif |
| 4814 | }; |
| 4815 | |
| 4816 | class indirectOper : public MachOper { |
| 4817 | private: |
| 4818 | virtual const RegMask *in_RegMask(int index) const; |
| 4819 | public: |
| 4820 | indirectOper() {} |
| 4821 | virtual MachOper *clone() const; |
| 4822 | virtual uint opcode() const { return INDIRECT; } |
| 4823 | virtual const Type *type() const { return TypePtr::BOTTOM; } |
| 4824 | |
| 4825 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4826 | // Replacement variable: reg |
| 4827 | return (int)ra_->get_encode(node->in(idx)); |
| 4828 | } |
| 4829 | virtual int base_position() const { return 0; } |
| 4830 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4831 | return 0x4; |
| 4832 | } |
| 4833 | virtual int scale() const { |
| 4834 | return 0x0; |
| 4835 | } |
| 4836 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4837 | return 0x0; |
| 4838 | } |
| 4839 | virtual int constant_disp() const { |
| 4840 | return 0x0; |
| 4841 | } |
| 4842 | |
| 4843 | #ifndef PRODUCT |
| 4844 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4845 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4846 | virtual const char *Name() const { return "indirect";} |
| 4847 | #endif |
| 4848 | }; |
| 4849 | |
| 4850 | class indOffset8Oper : public MachOper { |
| 4851 | private: |
| 4852 | virtual const RegMask *in_RegMask(int index) const; |
| 4853 | jlong _c0; |
| 4854 | public: |
| 4855 | indOffset8Oper(jlong c0) : _c0(c0) {} |
| 4856 | virtual MachOper *clone() const; |
| 4857 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4858 | virtual uint opcode() const { return INDOFFSET8; } |
| 4859 | |
| 4860 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4861 | // Replacement variable: reg |
| 4862 | return (int)ra_->get_encode(node->in(idx)); |
| 4863 | } |
| 4864 | virtual int base_position() const { return 0; } |
| 4865 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4866 | return 0x4; |
| 4867 | } |
| 4868 | virtual int scale() const { |
| 4869 | return 0x0; |
| 4870 | } |
| 4871 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4872 | // Replacement variable: off |
| 4873 | return (int)_c0; |
| 4874 | } |
| 4875 | virtual int constant_disp() const { |
| 4876 | // Replacement variable: off |
| 4877 | return (int)_c0; |
| 4878 | } |
| 4879 | |
| 4880 | #ifndef PRODUCT |
| 4881 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4882 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4883 | virtual void dump_spec(outputStream *st) const { |
| 4884 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 4885 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 4886 | } |
| 4887 | virtual const char *Name() const { return "indOffset8";} |
| 4888 | #endif |
| 4889 | }; |
| 4890 | |
| 4891 | class indOffset32Oper : public MachOper { |
| 4892 | private: |
| 4893 | virtual const RegMask *in_RegMask(int index) const; |
| 4894 | jlong _c0; |
| 4895 | public: |
| 4896 | indOffset32Oper(jlong c0) : _c0(c0) {} |
| 4897 | virtual MachOper *clone() const; |
| 4898 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4899 | virtual uint opcode() const { return INDOFFSET32; } |
| 4900 | |
| 4901 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4902 | // Replacement variable: reg |
| 4903 | return (int)ra_->get_encode(node->in(idx)); |
| 4904 | } |
| 4905 | virtual int base_position() const { return 0; } |
| 4906 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4907 | return 0x4; |
| 4908 | } |
| 4909 | virtual int scale() const { |
| 4910 | return 0x0; |
| 4911 | } |
| 4912 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4913 | // Replacement variable: off |
| 4914 | return (int)_c0; |
| 4915 | } |
| 4916 | virtual int constant_disp() const { |
| 4917 | // Replacement variable: off |
| 4918 | return (int)_c0; |
| 4919 | } |
| 4920 | |
| 4921 | #ifndef PRODUCT |
| 4922 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4923 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4924 | virtual void dump_spec(outputStream *st) const { |
| 4925 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 4926 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 4927 | } |
| 4928 | virtual const char *Name() const { return "indOffset32";} |
| 4929 | #endif |
| 4930 | }; |
| 4931 | |
| 4932 | class indIndexOffsetOper : public MachOper { |
| 4933 | private: |
| 4934 | virtual uint num_edges() const { return 2; } |
| 4935 | virtual const RegMask *in_RegMask(int index) const; |
| 4936 | jlong _c0; |
| 4937 | public: |
| 4938 | indIndexOffsetOper(jlong c0) : _c0(c0) {} |
| 4939 | virtual MachOper *clone() const; |
| 4940 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 4941 | virtual uint opcode() const { return INDINDEXOFFSET; } |
| 4942 | |
| 4943 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4944 | // Replacement variable: reg |
| 4945 | return (int)ra_->get_encode(node->in(idx)); |
| 4946 | } |
| 4947 | virtual int base_position() const { return 0; } |
| 4948 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4949 | // Replacement variable: lreg |
| 4950 | return (int)ra_->get_encode(node->in(idx+1)); |
| 4951 | } |
| 4952 | virtual int index_position() const { return 1; } |
| 4953 | virtual int scale() const { |
| 4954 | return 0x0; |
| 4955 | } |
| 4956 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4957 | // Replacement variable: off |
| 4958 | return (int)_c0; |
| 4959 | } |
| 4960 | virtual int constant_disp() const { |
| 4961 | // Replacement variable: off |
| 4962 | return (int)_c0; |
| 4963 | } |
| 4964 | |
| 4965 | #ifndef PRODUCT |
| 4966 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 4967 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 4968 | virtual void dump_spec(outputStream *st) const { |
| 4969 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 4970 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 4971 | } |
| 4972 | virtual const char *Name() const { return "indIndexOffset";} |
| 4973 | #endif |
| 4974 | }; |
| 4975 | |
| 4976 | class indIndexOper : public MachOper { |
| 4977 | private: |
| 4978 | virtual uint num_edges() const { return 2; } |
| 4979 | virtual const RegMask *in_RegMask(int index) const; |
| 4980 | public: |
| 4981 | indIndexOper() {} |
| 4982 | virtual MachOper *clone() const; |
| 4983 | virtual uint opcode() const { return INDINDEX; } |
| 4984 | |
| 4985 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4986 | // Replacement variable: reg |
| 4987 | return (int)ra_->get_encode(node->in(idx)); |
| 4988 | } |
| 4989 | virtual int base_position() const { return 0; } |
| 4990 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4991 | // Replacement variable: lreg |
| 4992 | return (int)ra_->get_encode(node->in(idx+1)); |
| 4993 | } |
| 4994 | virtual int index_position() const { return 1; } |
| 4995 | virtual int scale() const { |
| 4996 | return 0x0; |
| 4997 | } |
| 4998 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 4999 | return 0x0; |
| 5000 | } |
| 5001 | virtual int constant_disp() const { |
| 5002 | return 0x0; |
| 5003 | } |
| 5004 | |
| 5005 | #ifndef PRODUCT |
| 5006 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5007 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5008 | virtual const char *Name() const { return "indIndex";} |
| 5009 | #endif |
| 5010 | }; |
| 5011 | |
| 5012 | class indIndexScaleOper : public MachOper { |
| 5013 | private: |
| 5014 | virtual uint num_edges() const { return 2; } |
| 5015 | virtual const RegMask *in_RegMask(int index) const; |
| 5016 | jint _c0; |
| 5017 | public: |
| 5018 | indIndexScaleOper(int32_t c0) : _c0(c0) {} |
| 5019 | virtual MachOper *clone() const; |
| 5020 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5021 | virtual uint opcode() const { return INDINDEXSCALE; } |
| 5022 | |
| 5023 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5024 | // Replacement variable: reg |
| 5025 | return (int)ra_->get_encode(node->in(idx)); |
| 5026 | } |
| 5027 | virtual int base_position() const { return 0; } |
| 5028 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5029 | // Replacement variable: lreg |
| 5030 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5031 | } |
| 5032 | virtual int index_position() const { return 1; } |
| 5033 | virtual int scale() const { |
| 5034 | // Replacement variable: scale |
| 5035 | return (int)_c0; |
| 5036 | } |
| 5037 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5038 | return 0x0; |
| 5039 | } |
| 5040 | virtual int constant_disp() const { |
| 5041 | return 0x0; |
| 5042 | } |
| 5043 | |
| 5044 | #ifndef PRODUCT |
| 5045 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5046 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5047 | virtual void dump_spec(outputStream *st) const { |
| 5048 | st->print("#%d", _c0); |
| 5049 | st->print("/0x%08x", _c0); |
| 5050 | } |
| 5051 | virtual const char *Name() const { return "indIndexScale";} |
| 5052 | #endif |
| 5053 | }; |
| 5054 | |
| 5055 | class indPosIndexScaleOper : public MachOper { |
| 5056 | private: |
| 5057 | virtual uint num_edges() const { return 2; } |
| 5058 | virtual const RegMask *in_RegMask(int index) const; |
| 5059 | jint _c0; |
| 5060 | public: |
| 5061 | indPosIndexScaleOper(int32_t c0) : _c0(c0) {} |
| 5062 | virtual MachOper *clone() const; |
| 5063 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5064 | virtual uint opcode() const { return INDPOSINDEXSCALE; } |
| 5065 | |
| 5066 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5067 | // Replacement variable: reg |
| 5068 | return (int)ra_->get_encode(node->in(idx)); |
| 5069 | } |
| 5070 | virtual int base_position() const { return 0; } |
| 5071 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5072 | // Replacement variable: idx |
| 5073 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5074 | } |
| 5075 | virtual int index_position() const { return 1; } |
| 5076 | virtual int scale() const { |
| 5077 | // Replacement variable: scale |
| 5078 | return (int)_c0; |
| 5079 | } |
| 5080 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5081 | return 0x0; |
| 5082 | } |
| 5083 | virtual int constant_disp() const { |
| 5084 | return 0x0; |
| 5085 | } |
| 5086 | |
| 5087 | #ifndef PRODUCT |
| 5088 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5089 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5090 | virtual void dump_spec(outputStream *st) const { |
| 5091 | st->print("#%d", _c0); |
| 5092 | st->print("/0x%08x", _c0); |
| 5093 | } |
| 5094 | virtual const char *Name() const { return "indPosIndexScale";} |
| 5095 | #endif |
| 5096 | }; |
| 5097 | |
| 5098 | class indIndexScaleOffsetOper : public MachOper { |
| 5099 | private: |
| 5100 | virtual uint num_edges() const { return 2; } |
| 5101 | virtual const RegMask *in_RegMask(int index) const; |
| 5102 | jint _c0; |
| 5103 | jlong _c1; |
| 5104 | public: |
| 5105 | indIndexScaleOffsetOper(int32_t c0, jlong c1) : _c0(c0), _c1(c1) {} |
| 5106 | virtual MachOper *clone() const; |
| 5107 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5108 | virtual uint opcode() const { return INDINDEXSCALEOFFSET; } |
| 5109 | |
| 5110 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5111 | // Replacement variable: reg |
| 5112 | return (int)ra_->get_encode(node->in(idx)); |
| 5113 | } |
| 5114 | virtual int base_position() const { return 0; } |
| 5115 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5116 | // Replacement variable: lreg |
| 5117 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5118 | } |
| 5119 | virtual int index_position() const { return 1; } |
| 5120 | virtual int scale() const { |
| 5121 | // Replacement variable: scale |
| 5122 | return (int)_c0; |
| 5123 | } |
| 5124 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5125 | // Replacement variable: off |
| 5126 | return (int)_c1; |
| 5127 | } |
| 5128 | virtual int constant_disp() const { |
| 5129 | // Replacement variable: off |
| 5130 | return (int)_c1; |
| 5131 | } |
| 5132 | |
| 5133 | #ifndef PRODUCT |
| 5134 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5135 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5136 | virtual void dump_spec(outputStream *st) const { |
| 5137 | st->print("#%d", _c0); |
| 5138 | st->print("/0x%08x", _c0); |
| 5139 | st->print("#"INT64_FORMAT, (int64_t)_c1); |
| 5140 | st->print("/"PTR64_FORMAT, (uint64_t)_c1); |
| 5141 | } |
| 5142 | virtual const char *Name() const { return "indIndexScaleOffset";} |
| 5143 | #endif |
| 5144 | }; |
| 5145 | |
| 5146 | class indPosIndexOffsetOper : public MachOper { |
| 5147 | private: |
| 5148 | virtual uint num_edges() const { return 2; } |
| 5149 | virtual const RegMask *in_RegMask(int index) const; |
| 5150 | jlong _c0; |
| 5151 | public: |
| 5152 | indPosIndexOffsetOper(jlong c0) : _c0(c0) {} |
| 5153 | virtual MachOper *clone() const; |
| 5154 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5155 | virtual uint opcode() const { return INDPOSINDEXOFFSET; } |
| 5156 | |
| 5157 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5158 | // Replacement variable: reg |
| 5159 | return (int)ra_->get_encode(node->in(idx)); |
| 5160 | } |
| 5161 | virtual int base_position() const { return 0; } |
| 5162 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5163 | // Replacement variable: idx |
| 5164 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5165 | } |
| 5166 | virtual int index_position() const { return 1; } |
| 5167 | virtual int scale() const { |
| 5168 | return 0x0; |
| 5169 | } |
| 5170 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5171 | // Replacement variable: off |
| 5172 | return (int)_c0; |
| 5173 | } |
| 5174 | virtual int constant_disp() const { |
| 5175 | // Replacement variable: off |
| 5176 | return (int)_c0; |
| 5177 | } |
| 5178 | |
| 5179 | #ifndef PRODUCT |
| 5180 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5181 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5182 | virtual void dump_spec(outputStream *st) const { |
| 5183 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5184 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5185 | } |
| 5186 | virtual const char *Name() const { return "indPosIndexOffset";} |
| 5187 | #endif |
| 5188 | }; |
| 5189 | |
| 5190 | class indPosIndexScaleOffsetOper : public MachOper { |
| 5191 | private: |
| 5192 | virtual uint num_edges() const { return 2; } |
| 5193 | virtual const RegMask *in_RegMask(int index) const; |
| 5194 | jint _c0; |
| 5195 | jlong _c1; |
| 5196 | public: |
| 5197 | indPosIndexScaleOffsetOper(int32_t c0, jlong c1) : _c0(c0), _c1(c1) {} |
| 5198 | virtual MachOper *clone() const; |
| 5199 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5200 | virtual uint opcode() const { return INDPOSINDEXSCALEOFFSET; } |
| 5201 | |
| 5202 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5203 | // Replacement variable: reg |
| 5204 | return (int)ra_->get_encode(node->in(idx)); |
| 5205 | } |
| 5206 | virtual int base_position() const { return 0; } |
| 5207 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5208 | // Replacement variable: idx |
| 5209 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5210 | } |
| 5211 | virtual int index_position() const { return 1; } |
| 5212 | virtual int scale() const { |
| 5213 | // Replacement variable: scale |
| 5214 | return (int)_c0; |
| 5215 | } |
| 5216 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5217 | // Replacement variable: off |
| 5218 | return (int)_c1; |
| 5219 | } |
| 5220 | virtual int constant_disp() const { |
| 5221 | // Replacement variable: off |
| 5222 | return (int)_c1; |
| 5223 | } |
| 5224 | |
| 5225 | #ifndef PRODUCT |
| 5226 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5227 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5228 | virtual void dump_spec(outputStream *st) const { |
| 5229 | st->print("#%d", _c0); |
| 5230 | st->print("/0x%08x", _c0); |
| 5231 | st->print("#"INT64_FORMAT, (int64_t)_c1); |
| 5232 | st->print("/"PTR64_FORMAT, (uint64_t)_c1); |
| 5233 | } |
| 5234 | virtual const char *Name() const { return "indPosIndexScaleOffset";} |
| 5235 | #endif |
| 5236 | }; |
| 5237 | |
| 5238 | class indCompressedOopOffsetOper : public MachOper { |
| 5239 | private: |
| 5240 | virtual const RegMask *in_RegMask(int index) const; |
| 5241 | jlong _c0; |
| 5242 | public: |
| 5243 | indCompressedOopOffsetOper(jlong c0) : _c0(c0) {} |
| 5244 | virtual MachOper *clone() const; |
| 5245 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5246 | virtual uint opcode() const { return INDCOMPRESSEDOOPOFFSET; } |
| 5247 | |
| 5248 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5249 | return 0xc; |
| 5250 | } |
| 5251 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5252 | // Replacement variable: reg |
| 5253 | return (int)ra_->get_encode(node->in(idx)); |
| 5254 | } |
| 5255 | virtual int index_position() const { return 0; } |
| 5256 | virtual int scale() const { |
| 5257 | return 0x3; |
| 5258 | } |
| 5259 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5260 | // Replacement variable: off |
| 5261 | return (int)_c0; |
| 5262 | } |
| 5263 | virtual int constant_disp() const { |
| 5264 | // Replacement variable: off |
| 5265 | return (int)_c0; |
| 5266 | } |
| 5267 | |
| 5268 | #ifndef PRODUCT |
| 5269 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5270 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5271 | virtual void dump_spec(outputStream *st) const { |
| 5272 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5273 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5274 | } |
| 5275 | virtual const char *Name() const { return "indCompressedOopOffset";} |
| 5276 | #endif |
| 5277 | }; |
| 5278 | |
| 5279 | class indirectNarrowOper : public MachOper { |
| 5280 | private: |
| 5281 | virtual const RegMask *in_RegMask(int index) const; |
| 5282 | public: |
| 5283 | indirectNarrowOper() {} |
| 5284 | virtual MachOper *clone() const; |
| 5285 | virtual uint opcode() const { return INDIRECTNARROW; } |
| 5286 | |
| 5287 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5288 | // Replacement variable: reg |
| 5289 | return (int)ra_->get_encode(node->in(idx)); |
| 5290 | } |
| 5291 | virtual int base_position() const { return 0; } |
| 5292 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5293 | return 0x4; |
| 5294 | } |
| 5295 | virtual int scale() const { |
| 5296 | return 0x0; |
| 5297 | } |
| 5298 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5299 | return 0x0; |
| 5300 | } |
| 5301 | virtual int constant_disp() const { |
| 5302 | return 0x0; |
| 5303 | } |
| 5304 | |
| 5305 | #ifndef PRODUCT |
| 5306 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5307 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5308 | virtual const char *Name() const { return "indirectNarrow";} |
| 5309 | #endif |
| 5310 | }; |
| 5311 | |
| 5312 | class indOffset8NarrowOper : public MachOper { |
| 5313 | private: |
| 5314 | virtual const RegMask *in_RegMask(int index) const; |
| 5315 | jlong _c0; |
| 5316 | public: |
| 5317 | indOffset8NarrowOper(jlong c0) : _c0(c0) {} |
| 5318 | virtual MachOper *clone() const; |
| 5319 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5320 | virtual uint opcode() const { return INDOFFSET8NARROW; } |
| 5321 | |
| 5322 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5323 | // Replacement variable: reg |
| 5324 | return (int)ra_->get_encode(node->in(idx)); |
| 5325 | } |
| 5326 | virtual int base_position() const { return 0; } |
| 5327 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5328 | return 0x4; |
| 5329 | } |
| 5330 | virtual int scale() const { |
| 5331 | return 0x0; |
| 5332 | } |
| 5333 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5334 | // Replacement variable: off |
| 5335 | return (int)_c0; |
| 5336 | } |
| 5337 | virtual int constant_disp() const { |
| 5338 | // Replacement variable: off |
| 5339 | return (int)_c0; |
| 5340 | } |
| 5341 | |
| 5342 | #ifndef PRODUCT |
| 5343 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5344 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5345 | virtual void dump_spec(outputStream *st) const { |
| 5346 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5347 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5348 | } |
| 5349 | virtual const char *Name() const { return "indOffset8Narrow";} |
| 5350 | #endif |
| 5351 | }; |
| 5352 | |
| 5353 | class indOffset32NarrowOper : public MachOper { |
| 5354 | private: |
| 5355 | virtual const RegMask *in_RegMask(int index) const; |
| 5356 | jlong _c0; |
| 5357 | public: |
| 5358 | indOffset32NarrowOper(jlong c0) : _c0(c0) {} |
| 5359 | virtual MachOper *clone() const; |
| 5360 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5361 | virtual uint opcode() const { return INDOFFSET32NARROW; } |
| 5362 | |
| 5363 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5364 | // Replacement variable: reg |
| 5365 | return (int)ra_->get_encode(node->in(idx)); |
| 5366 | } |
| 5367 | virtual int base_position() const { return 0; } |
| 5368 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5369 | return 0x4; |
| 5370 | } |
| 5371 | virtual int scale() const { |
| 5372 | return 0x0; |
| 5373 | } |
| 5374 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5375 | // Replacement variable: off |
| 5376 | return (int)_c0; |
| 5377 | } |
| 5378 | virtual int constant_disp() const { |
| 5379 | // Replacement variable: off |
| 5380 | return (int)_c0; |
| 5381 | } |
| 5382 | |
| 5383 | #ifndef PRODUCT |
| 5384 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5385 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5386 | virtual void dump_spec(outputStream *st) const { |
| 5387 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5388 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5389 | } |
| 5390 | virtual const char *Name() const { return "indOffset32Narrow";} |
| 5391 | #endif |
| 5392 | }; |
| 5393 | |
| 5394 | class indIndexOffsetNarrowOper : public MachOper { |
| 5395 | private: |
| 5396 | virtual uint num_edges() const { return 2; } |
| 5397 | virtual const RegMask *in_RegMask(int index) const; |
| 5398 | jlong _c0; |
| 5399 | public: |
| 5400 | indIndexOffsetNarrowOper(jlong c0) : _c0(c0) {} |
| 5401 | virtual MachOper *clone() const; |
| 5402 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5403 | virtual uint opcode() const { return INDINDEXOFFSETNARROW; } |
| 5404 | |
| 5405 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5406 | // Replacement variable: reg |
| 5407 | return (int)ra_->get_encode(node->in(idx)); |
| 5408 | } |
| 5409 | virtual int base_position() const { return 0; } |
| 5410 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5411 | // Replacement variable: lreg |
| 5412 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5413 | } |
| 5414 | virtual int index_position() const { return 1; } |
| 5415 | virtual int scale() const { |
| 5416 | return 0x0; |
| 5417 | } |
| 5418 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5419 | // Replacement variable: off |
| 5420 | return (int)_c0; |
| 5421 | } |
| 5422 | virtual int constant_disp() const { |
| 5423 | // Replacement variable: off |
| 5424 | return (int)_c0; |
| 5425 | } |
| 5426 | |
| 5427 | #ifndef PRODUCT |
| 5428 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5429 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5430 | virtual void dump_spec(outputStream *st) const { |
| 5431 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5432 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5433 | } |
| 5434 | virtual const char *Name() const { return "indIndexOffsetNarrow";} |
| 5435 | #endif |
| 5436 | }; |
| 5437 | |
| 5438 | class indIndexNarrowOper : public MachOper { |
| 5439 | private: |
| 5440 | virtual uint num_edges() const { return 2; } |
| 5441 | virtual const RegMask *in_RegMask(int index) const; |
| 5442 | public: |
| 5443 | indIndexNarrowOper() {} |
| 5444 | virtual MachOper *clone() const; |
| 5445 | virtual uint opcode() const { return INDINDEXNARROW; } |
| 5446 | |
| 5447 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5448 | // Replacement variable: reg |
| 5449 | return (int)ra_->get_encode(node->in(idx)); |
| 5450 | } |
| 5451 | virtual int base_position() const { return 0; } |
| 5452 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5453 | // Replacement variable: lreg |
| 5454 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5455 | } |
| 5456 | virtual int index_position() const { return 1; } |
| 5457 | virtual int scale() const { |
| 5458 | return 0x0; |
| 5459 | } |
| 5460 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5461 | return 0x0; |
| 5462 | } |
| 5463 | virtual int constant_disp() const { |
| 5464 | return 0x0; |
| 5465 | } |
| 5466 | |
| 5467 | #ifndef PRODUCT |
| 5468 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5469 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5470 | virtual const char *Name() const { return "indIndexNarrow";} |
| 5471 | #endif |
| 5472 | }; |
| 5473 | |
| 5474 | class indIndexScaleNarrowOper : public MachOper { |
| 5475 | private: |
| 5476 | virtual uint num_edges() const { return 2; } |
| 5477 | virtual const RegMask *in_RegMask(int index) const; |
| 5478 | jint _c0; |
| 5479 | public: |
| 5480 | indIndexScaleNarrowOper(int32_t c0) : _c0(c0) {} |
| 5481 | virtual MachOper *clone() const; |
| 5482 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5483 | virtual uint opcode() const { return INDINDEXSCALENARROW; } |
| 5484 | |
| 5485 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5486 | // Replacement variable: reg |
| 5487 | return (int)ra_->get_encode(node->in(idx)); |
| 5488 | } |
| 5489 | virtual int base_position() const { return 0; } |
| 5490 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5491 | // Replacement variable: lreg |
| 5492 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5493 | } |
| 5494 | virtual int index_position() const { return 1; } |
| 5495 | virtual int scale() const { |
| 5496 | // Replacement variable: scale |
| 5497 | return (int)_c0; |
| 5498 | } |
| 5499 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5500 | return 0x0; |
| 5501 | } |
| 5502 | virtual int constant_disp() const { |
| 5503 | return 0x0; |
| 5504 | } |
| 5505 | |
| 5506 | #ifndef PRODUCT |
| 5507 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5508 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5509 | virtual void dump_spec(outputStream *st) const { |
| 5510 | st->print("#%d", _c0); |
| 5511 | st->print("/0x%08x", _c0); |
| 5512 | } |
| 5513 | virtual const char *Name() const { return "indIndexScaleNarrow";} |
| 5514 | #endif |
| 5515 | }; |
| 5516 | |
| 5517 | class indIndexScaleOffsetNarrowOper : public MachOper { |
| 5518 | private: |
| 5519 | virtual uint num_edges() const { return 2; } |
| 5520 | virtual const RegMask *in_RegMask(int index) const; |
| 5521 | jint _c0; |
| 5522 | jlong _c1; |
| 5523 | public: |
| 5524 | indIndexScaleOffsetNarrowOper(int32_t c0, jlong c1) : _c0(c0), _c1(c1) {} |
| 5525 | virtual MachOper *clone() const; |
| 5526 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5527 | virtual uint opcode() const { return INDINDEXSCALEOFFSETNARROW; } |
| 5528 | |
| 5529 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5530 | // Replacement variable: reg |
| 5531 | return (int)ra_->get_encode(node->in(idx)); |
| 5532 | } |
| 5533 | virtual int base_position() const { return 0; } |
| 5534 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5535 | // Replacement variable: lreg |
| 5536 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5537 | } |
| 5538 | virtual int index_position() const { return 1; } |
| 5539 | virtual int scale() const { |
| 5540 | // Replacement variable: scale |
| 5541 | return (int)_c0; |
| 5542 | } |
| 5543 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5544 | // Replacement variable: off |
| 5545 | return (int)_c1; |
| 5546 | } |
| 5547 | virtual int constant_disp() const { |
| 5548 | // Replacement variable: off |
| 5549 | return (int)_c1; |
| 5550 | } |
| 5551 | |
| 5552 | #ifndef PRODUCT |
| 5553 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5554 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5555 | virtual void dump_spec(outputStream *st) const { |
| 5556 | st->print("#%d", _c0); |
| 5557 | st->print("/0x%08x", _c0); |
| 5558 | st->print("#"INT64_FORMAT, (int64_t)_c1); |
| 5559 | st->print("/"PTR64_FORMAT, (uint64_t)_c1); |
| 5560 | } |
| 5561 | virtual const char *Name() const { return "indIndexScaleOffsetNarrow";} |
| 5562 | #endif |
| 5563 | }; |
| 5564 | |
| 5565 | class indPosIndexOffsetNarrowOper : public MachOper { |
| 5566 | private: |
| 5567 | virtual uint num_edges() const { return 2; } |
| 5568 | virtual const RegMask *in_RegMask(int index) const; |
| 5569 | jlong _c0; |
| 5570 | public: |
| 5571 | indPosIndexOffsetNarrowOper(jlong c0) : _c0(c0) {} |
| 5572 | virtual MachOper *clone() const; |
| 5573 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5574 | virtual uint opcode() const { return INDPOSINDEXOFFSETNARROW; } |
| 5575 | |
| 5576 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5577 | // Replacement variable: reg |
| 5578 | return (int)ra_->get_encode(node->in(idx)); |
| 5579 | } |
| 5580 | virtual int base_position() const { return 0; } |
| 5581 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5582 | // Replacement variable: idx |
| 5583 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5584 | } |
| 5585 | virtual int index_position() const { return 1; } |
| 5586 | virtual int scale() const { |
| 5587 | return 0x0; |
| 5588 | } |
| 5589 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5590 | // Replacement variable: off |
| 5591 | return (int)_c0; |
| 5592 | } |
| 5593 | virtual int constant_disp() const { |
| 5594 | // Replacement variable: off |
| 5595 | return (int)_c0; |
| 5596 | } |
| 5597 | |
| 5598 | #ifndef PRODUCT |
| 5599 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5600 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5601 | virtual void dump_spec(outputStream *st) const { |
| 5602 | st->print("#"INT64_FORMAT, (int64_t)_c0); |
| 5603 | st->print("/"PTR64_FORMAT, (uint64_t)_c0); |
| 5604 | } |
| 5605 | virtual const char *Name() const { return "indPosIndexOffsetNarrow";} |
| 5606 | #endif |
| 5607 | }; |
| 5608 | |
| 5609 | class indPosIndexScaleOffsetNarrowOper : public MachOper { |
| 5610 | private: |
| 5611 | virtual uint num_edges() const { return 2; } |
| 5612 | virtual const RegMask *in_RegMask(int index) const; |
| 5613 | jint _c0; |
| 5614 | jlong _c1; |
| 5615 | public: |
| 5616 | indPosIndexScaleOffsetNarrowOper(int32_t c0, jlong c1) : _c0(c0), _c1(c1) {} |
| 5617 | virtual MachOper *clone() const; |
| 5618 | virtual void set_con( jint c0 ) { _c0 = c0; } |
| 5619 | virtual uint opcode() const { return INDPOSINDEXSCALEOFFSETNARROW; } |
| 5620 | |
| 5621 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5622 | // Replacement variable: reg |
| 5623 | return (int)ra_->get_encode(node->in(idx)); |
| 5624 | } |
| 5625 | virtual int base_position() const { return 0; } |
| 5626 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5627 | // Replacement variable: idx |
| 5628 | return (int)ra_->get_encode(node->in(idx+1)); |
| 5629 | } |
| 5630 | virtual int index_position() const { return 1; } |
| 5631 | virtual int scale() const { |
| 5632 | // Replacement variable: scale |
| 5633 | return (int)_c0; |
| 5634 | } |
| 5635 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5636 | // Replacement variable: off |
| 5637 | return (int)_c1; |
| 5638 | } |
| 5639 | virtual int constant_disp() const { |
| 5640 | // Replacement variable: off |
| 5641 | return (int)_c1; |
| 5642 | } |
| 5643 | |
| 5644 | #ifndef PRODUCT |
| 5645 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5646 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5647 | virtual void dump_spec(outputStream *st) const { |
| 5648 | st->print("#%d", _c0); |
| 5649 | st->print("/0x%08x", _c0); |
| 5650 | st->print("#"INT64_FORMAT, (int64_t)_c1); |
| 5651 | st->print("/"PTR64_FORMAT, (uint64_t)_c1); |
| 5652 | } |
| 5653 | virtual const char *Name() const { return "indPosIndexScaleOffsetNarrow";} |
| 5654 | #endif |
| 5655 | }; |
| 5656 | |
| 5657 | class stackSlotPOper : public MachOper { |
| 5658 | private: |
| 5659 | virtual const RegMask *in_RegMask(int index) const; |
| 5660 | public: |
| 5661 | stackSlotPOper() {} |
| 5662 | virtual MachOper *clone() const; |
| 5663 | virtual uint opcode() const { return STACKSLOTP; } |
| 5664 | virtual const Type *type() const { return TypePtr::BOTTOM; } // stackSlotX |
| 5665 | |
| 5666 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5667 | return 0x4; |
| 5668 | } |
| 5669 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5670 | return 0x4; |
| 5671 | } |
| 5672 | virtual int scale() const { |
| 5673 | return 0x0; |
| 5674 | } |
| 5675 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5676 | // Replacement variable: reg |
| 5677 | if( idx != 0 ) { |
| 5678 | // Access stack offset (register number) for input operand |
| 5679 | return ra_->reg2offset(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 5680 | } |
| 5681 | // Access stack offset (register number) from myself |
| 5682 | return ra_->reg2offset(ra_->get_reg_first(node));/* sReg */ |
| 5683 | } |
| 5684 | virtual int constant_disp() const { return Type::OffsetBot; } |
| 5685 | #ifndef PRODUCT |
| 5686 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5687 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5688 | virtual const char *Name() const { return "stackSlotP";} |
| 5689 | #endif |
| 5690 | }; |
| 5691 | |
| 5692 | class stackSlotIOper : public MachOper { |
| 5693 | private: |
| 5694 | virtual const RegMask *in_RegMask(int index) const; |
| 5695 | public: |
| 5696 | stackSlotIOper() {} |
| 5697 | virtual MachOper *clone() const; |
| 5698 | virtual uint opcode() const { return STACKSLOTI; } |
| 5699 | virtual const Type *type() const { return TypeInt::INT; } // stackSlotX |
| 5700 | |
| 5701 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5702 | return 0x4; |
| 5703 | } |
| 5704 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5705 | return 0x4; |
| 5706 | } |
| 5707 | virtual int scale() const { |
| 5708 | return 0x0; |
| 5709 | } |
| 5710 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5711 | // Replacement variable: reg |
| 5712 | if( idx != 0 ) { |
| 5713 | // Access stack offset (register number) for input operand |
| 5714 | return ra_->reg2offset(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 5715 | } |
| 5716 | // Access stack offset (register number) from myself |
| 5717 | return ra_->reg2offset(ra_->get_reg_first(node));/* sReg */ |
| 5718 | } |
| 5719 | virtual int constant_disp() const { return Type::OffsetBot; } |
| 5720 | #ifndef PRODUCT |
| 5721 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5722 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5723 | virtual const char *Name() const { return "stackSlotI";} |
| 5724 | #endif |
| 5725 | }; |
| 5726 | |
| 5727 | class stackSlotFOper : public MachOper { |
| 5728 | private: |
| 5729 | virtual const RegMask *in_RegMask(int index) const; |
| 5730 | public: |
| 5731 | stackSlotFOper() {} |
| 5732 | virtual MachOper *clone() const; |
| 5733 | virtual uint opcode() const { return STACKSLOTF; } |
| 5734 | virtual const Type *type() const { return Type::FLOAT; } // stackSlotX |
| 5735 | |
| 5736 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5737 | return 0x4; |
| 5738 | } |
| 5739 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5740 | return 0x4; |
| 5741 | } |
| 5742 | virtual int scale() const { |
| 5743 | return 0x0; |
| 5744 | } |
| 5745 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5746 | // Replacement variable: reg |
| 5747 | if( idx != 0 ) { |
| 5748 | // Access stack offset (register number) for input operand |
| 5749 | return ra_->reg2offset(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 5750 | } |
| 5751 | // Access stack offset (register number) from myself |
| 5752 | return ra_->reg2offset(ra_->get_reg_first(node));/* sReg */ |
| 5753 | } |
| 5754 | virtual int constant_disp() const { return Type::OffsetBot; } |
| 5755 | #ifndef PRODUCT |
| 5756 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5757 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5758 | virtual const char *Name() const { return "stackSlotF";} |
| 5759 | #endif |
| 5760 | }; |
| 5761 | |
| 5762 | class stackSlotDOper : public MachOper { |
| 5763 | private: |
| 5764 | virtual const RegMask *in_RegMask(int index) const; |
| 5765 | public: |
| 5766 | stackSlotDOper() {} |
| 5767 | virtual MachOper *clone() const; |
| 5768 | virtual uint opcode() const { return STACKSLOTD; } |
| 5769 | virtual const Type *type() const { return Type::DOUBLE; } // stackSlotX |
| 5770 | |
| 5771 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5772 | return 0x4; |
| 5773 | } |
| 5774 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5775 | return 0x4; |
| 5776 | } |
| 5777 | virtual int scale() const { |
| 5778 | return 0x0; |
| 5779 | } |
| 5780 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5781 | // Replacement variable: reg |
| 5782 | if( idx != 0 ) { |
| 5783 | // Access stack offset (register number) for input operand |
| 5784 | return ra_->reg2offset(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 5785 | } |
| 5786 | // Access stack offset (register number) from myself |
| 5787 | return ra_->reg2offset(ra_->get_reg_first(node));/* sReg */ |
| 5788 | } |
| 5789 | virtual int constant_disp() const { return Type::OffsetBot; } |
| 5790 | #ifndef PRODUCT |
| 5791 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5792 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5793 | virtual const char *Name() const { return "stackSlotD";} |
| 5794 | #endif |
| 5795 | }; |
| 5796 | |
| 5797 | class stackSlotLOper : public MachOper { |
| 5798 | private: |
| 5799 | virtual const RegMask *in_RegMask(int index) const; |
| 5800 | public: |
| 5801 | stackSlotLOper() {} |
| 5802 | virtual MachOper *clone() const; |
| 5803 | virtual uint opcode() const { return STACKSLOTL; } |
| 5804 | virtual const Type *type() const { return TypeLong::LONG; } // stackSlotX |
| 5805 | |
| 5806 | virtual int base(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5807 | return 0x4; |
| 5808 | } |
| 5809 | virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5810 | return 0x4; |
| 5811 | } |
| 5812 | virtual int scale() const { |
| 5813 | return 0x0; |
| 5814 | } |
| 5815 | virtual int disp(PhaseRegAlloc *ra_, const Node *node, int idx) const { |
| 5816 | // Replacement variable: reg |
| 5817 | if( idx != 0 ) { |
| 5818 | // Access stack offset (register number) for input operand |
| 5819 | return ra_->reg2offset(ra_->get_reg_first(node->in(idx)));/* sReg */ |
| 5820 | } |
| 5821 | // Access stack offset (register number) from myself |
| 5822 | return ra_->reg2offset(ra_->get_reg_first(node));/* sReg */ |
| 5823 | } |
| 5824 | virtual int constant_disp() const { return Type::OffsetBot; } |
| 5825 | #ifndef PRODUCT |
| 5826 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5827 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5828 | virtual const char *Name() const { return "stackSlotL";} |
| 5829 | #endif |
| 5830 | }; |
| 5831 | |
| 5832 | class cmpOpOper : public MachOper { |
| 5833 | private: |
| 5834 | virtual uint num_edges() const { return 0; } |
| 5835 | private: |
| 5836 | BoolTest::mask _c0; |
| 5837 | public: |
| 5838 | virtual int ccode() const { |
| 5839 | switch (_c0) { |
| 5840 | case BoolTest::eq : return equal(); |
| 5841 | case BoolTest::gt : return greater(); |
| 5842 | case BoolTest::lt : return less(); |
| 5843 | case BoolTest::ne : return not_equal(); |
| 5844 | case BoolTest::le : return less_equal(); |
| 5845 | case BoolTest::ge : return greater_equal(); |
| 5846 | case BoolTest::overflow : return overflow(); |
| 5847 | case BoolTest::no_overflow: return no_overflow(); |
| 5848 | default : ShouldNotReachHere(); return 0; |
| 5849 | } |
| 5850 | }; |
| 5851 | virtual void negate() { |
| 5852 | _c0 = (BoolTest::mask)((int)_c0^0x4); |
| 5853 | }; |
| 5854 | public: |
| 5855 | cmpOpOper(BoolTest::mask c0) : _c0(c0) {} |
| 5856 | virtual MachOper *clone() const; |
| 5857 | virtual uint opcode() const { return CMPOP; } |
| 5858 | virtual const Type *type() const { ShouldNotCallThis(); return Type::BOTTOM; } |
| 5859 | |
| 5860 | virtual int equal() const { |
| 5861 | return 0x4; |
| 5862 | } |
| 5863 | virtual int not_equal() const { |
| 5864 | return 0x5; |
| 5865 | } |
| 5866 | virtual int less() const { |
| 5867 | return 0xC; |
| 5868 | } |
| 5869 | virtual int greater_equal() const { |
| 5870 | return 0xD; |
| 5871 | } |
| 5872 | virtual int less_equal() const { |
| 5873 | return 0xE; |
| 5874 | } |
| 5875 | virtual int greater() const { |
| 5876 | return 0xF; |
| 5877 | } |
| 5878 | virtual int overflow() const { |
| 5879 | return 0x0; |
| 5880 | } |
| 5881 | virtual int no_overflow() const { |
| 5882 | return 0x1; |
| 5883 | } |
| 5884 | |
| 5885 | #ifndef PRODUCT |
| 5886 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5887 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5888 | virtual void dump_spec(outputStream *st) const { |
| 5889 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 5890 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 5891 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 5892 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 5893 | else if( _c0 == BoolTest::lt ) st->print_raw("l"); |
| 5894 | else if( _c0 == BoolTest::gt ) st->print_raw("g"); |
| 5895 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 5896 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 5897 | } |
| 5898 | virtual const char *Name() const { return "cmpOp";} |
| 5899 | #endif |
| 5900 | }; |
| 5901 | |
| 5902 | class cmpOpUOper : public MachOper { |
| 5903 | private: |
| 5904 | virtual uint num_edges() const { return 0; } |
| 5905 | private: |
| 5906 | BoolTest::mask _c0; |
| 5907 | public: |
| 5908 | virtual int ccode() const { |
| 5909 | switch (_c0) { |
| 5910 | case BoolTest::eq : return equal(); |
| 5911 | case BoolTest::gt : return greater(); |
| 5912 | case BoolTest::lt : return less(); |
| 5913 | case BoolTest::ne : return not_equal(); |
| 5914 | case BoolTest::le : return less_equal(); |
| 5915 | case BoolTest::ge : return greater_equal(); |
| 5916 | case BoolTest::overflow : return overflow(); |
| 5917 | case BoolTest::no_overflow: return no_overflow(); |
| 5918 | default : ShouldNotReachHere(); return 0; |
| 5919 | } |
| 5920 | }; |
| 5921 | virtual void negate() { |
| 5922 | _c0 = (BoolTest::mask)((int)_c0^0x4); |
| 5923 | }; |
| 5924 | public: |
| 5925 | cmpOpUOper(BoolTest::mask c0) : _c0(c0) {} |
| 5926 | virtual MachOper *clone() const; |
| 5927 | virtual uint opcode() const { return CMPOPU; } |
| 5928 | virtual const Type *type() const { ShouldNotCallThis(); return Type::BOTTOM; } |
| 5929 | |
| 5930 | virtual int equal() const { |
| 5931 | return 0x4; |
| 5932 | } |
| 5933 | virtual int not_equal() const { |
| 5934 | return 0x5; |
| 5935 | } |
| 5936 | virtual int less() const { |
| 5937 | return 0x2; |
| 5938 | } |
| 5939 | virtual int greater_equal() const { |
| 5940 | return 0x3; |
| 5941 | } |
| 5942 | virtual int less_equal() const { |
| 5943 | return 0x6; |
| 5944 | } |
| 5945 | virtual int greater() const { |
| 5946 | return 0x7; |
| 5947 | } |
| 5948 | virtual int overflow() const { |
| 5949 | return 0x0; |
| 5950 | } |
| 5951 | virtual int no_overflow() const { |
| 5952 | return 0x1; |
| 5953 | } |
| 5954 | |
| 5955 | #ifndef PRODUCT |
| 5956 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 5957 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 5958 | virtual void dump_spec(outputStream *st) const { |
| 5959 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 5960 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 5961 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 5962 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 5963 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 5964 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 5965 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 5966 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 5967 | } |
| 5968 | virtual const char *Name() const { return "cmpOpU";} |
| 5969 | #endif |
| 5970 | }; |
| 5971 | |
| 5972 | class cmpOpUCFOper : public MachOper { |
| 5973 | private: |
| 5974 | virtual uint num_edges() const { return 0; } |
| 5975 | private: |
| 5976 | BoolTest::mask _c0; |
| 5977 | public: |
| 5978 | virtual int ccode() const { |
| 5979 | switch (_c0) { |
| 5980 | case BoolTest::eq : return equal(); |
| 5981 | case BoolTest::gt : return greater(); |
| 5982 | case BoolTest::lt : return less(); |
| 5983 | case BoolTest::ne : return not_equal(); |
| 5984 | case BoolTest::le : return less_equal(); |
| 5985 | case BoolTest::ge : return greater_equal(); |
| 5986 | case BoolTest::overflow : return overflow(); |
| 5987 | case BoolTest::no_overflow: return no_overflow(); |
| 5988 | default : ShouldNotReachHere(); return 0; |
| 5989 | } |
| 5990 | }; |
| 5991 | virtual void negate() { |
| 5992 | _c0 = (BoolTest::mask)((int)_c0^0x4); |
| 5993 | }; |
| 5994 | public: |
| 5995 | cmpOpUCFOper(BoolTest::mask c0) : _c0(c0) {} |
| 5996 | virtual MachOper *clone() const; |
| 5997 | virtual uint opcode() const { return CMPOPUCF; } |
| 5998 | virtual const Type *type() const { ShouldNotCallThis(); return Type::BOTTOM; } |
| 5999 | |
| 6000 | virtual int equal() const { |
| 6001 | return 0x4; |
| 6002 | } |
| 6003 | virtual int not_equal() const { |
| 6004 | return 0x5; |
| 6005 | } |
| 6006 | virtual int less() const { |
| 6007 | return 0x2; |
| 6008 | } |
| 6009 | virtual int greater_equal() const { |
| 6010 | return 0x3; |
| 6011 | } |
| 6012 | virtual int less_equal() const { |
| 6013 | return 0x6; |
| 6014 | } |
| 6015 | virtual int greater() const { |
| 6016 | return 0x7; |
| 6017 | } |
| 6018 | virtual int overflow() const { |
| 6019 | return 0x0; |
| 6020 | } |
| 6021 | virtual int no_overflow() const { |
| 6022 | return 0x1; |
| 6023 | } |
| 6024 | |
| 6025 | #ifndef PRODUCT |
| 6026 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6027 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6028 | virtual void dump_spec(outputStream *st) const { |
| 6029 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 6030 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 6031 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 6032 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 6033 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 6034 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 6035 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 6036 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 6037 | } |
| 6038 | virtual const char *Name() const { return "cmpOpUCF";} |
| 6039 | #endif |
| 6040 | }; |
| 6041 | |
| 6042 | class cmpOpUCF2Oper : public MachOper { |
| 6043 | private: |
| 6044 | virtual uint num_edges() const { return 0; } |
| 6045 | private: |
| 6046 | BoolTest::mask _c0; |
| 6047 | public: |
| 6048 | virtual int ccode() const { |
| 6049 | switch (_c0) { |
| 6050 | case BoolTest::eq : return equal(); |
| 6051 | case BoolTest::gt : return greater(); |
| 6052 | case BoolTest::lt : return less(); |
| 6053 | case BoolTest::ne : return not_equal(); |
| 6054 | case BoolTest::le : return less_equal(); |
| 6055 | case BoolTest::ge : return greater_equal(); |
| 6056 | case BoolTest::overflow : return overflow(); |
| 6057 | case BoolTest::no_overflow: return no_overflow(); |
| 6058 | default : ShouldNotReachHere(); return 0; |
| 6059 | } |
| 6060 | }; |
| 6061 | virtual void negate() { |
| 6062 | _c0 = (BoolTest::mask)((int)_c0^0x4); |
| 6063 | }; |
| 6064 | public: |
| 6065 | cmpOpUCF2Oper(BoolTest::mask c0) : _c0(c0) {} |
| 6066 | virtual MachOper *clone() const; |
| 6067 | virtual uint opcode() const { return CMPOPUCF2; } |
| 6068 | virtual const Type *type() const { ShouldNotCallThis(); return Type::BOTTOM; } |
| 6069 | |
| 6070 | virtual int equal() const { |
| 6071 | return 0x4; |
| 6072 | } |
| 6073 | virtual int not_equal() const { |
| 6074 | return 0x5; |
| 6075 | } |
| 6076 | virtual int less() const { |
| 6077 | return 0x2; |
| 6078 | } |
| 6079 | virtual int greater_equal() const { |
| 6080 | return 0x3; |
| 6081 | } |
| 6082 | virtual int less_equal() const { |
| 6083 | return 0x6; |
| 6084 | } |
| 6085 | virtual int greater() const { |
| 6086 | return 0x7; |
| 6087 | } |
| 6088 | virtual int overflow() const { |
| 6089 | return 0x0; |
| 6090 | } |
| 6091 | virtual int no_overflow() const { |
| 6092 | return 0x1; |
| 6093 | } |
| 6094 | |
| 6095 | #ifndef PRODUCT |
| 6096 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6097 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6098 | virtual void dump_spec(outputStream *st) const { |
| 6099 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 6100 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 6101 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 6102 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 6103 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 6104 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 6105 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 6106 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 6107 | } |
| 6108 | virtual const char *Name() const { return "cmpOpUCF2";} |
| 6109 | #endif |
| 6110 | }; |
| 6111 | |
| 6112 | class rxmm0Oper : public MachOper { |
| 6113 | private: |
| 6114 | virtual const RegMask *in_RegMask(int index) const; |
| 6115 | public: |
| 6116 | rxmm0Oper() {} |
| 6117 | virtual MachOper *clone() const; |
| 6118 | virtual uint opcode() const { return RXMM0; } |
| 6119 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6120 | |
| 6121 | |
| 6122 | #ifndef PRODUCT |
| 6123 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6124 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6125 | virtual const char *Name() const { return "rxmm0";} |
| 6126 | #endif |
| 6127 | }; |
| 6128 | |
| 6129 | class rxmm1Oper : public MachOper { |
| 6130 | private: |
| 6131 | virtual const RegMask *in_RegMask(int index) const; |
| 6132 | public: |
| 6133 | rxmm1Oper() {} |
| 6134 | virtual MachOper *clone() const; |
| 6135 | virtual uint opcode() const { return RXMM1; } |
| 6136 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6137 | |
| 6138 | |
| 6139 | #ifndef PRODUCT |
| 6140 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6141 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6142 | virtual const char *Name() const { return "rxmm1";} |
| 6143 | #endif |
| 6144 | }; |
| 6145 | |
| 6146 | class rxmm2Oper : public MachOper { |
| 6147 | private: |
| 6148 | virtual const RegMask *in_RegMask(int index) const; |
| 6149 | public: |
| 6150 | rxmm2Oper() {} |
| 6151 | virtual MachOper *clone() const; |
| 6152 | virtual uint opcode() const { return RXMM2; } |
| 6153 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6154 | |
| 6155 | |
| 6156 | #ifndef PRODUCT |
| 6157 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6158 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6159 | virtual const char *Name() const { return "rxmm2";} |
| 6160 | #endif |
| 6161 | }; |
| 6162 | |
| 6163 | class rxmm3Oper : public MachOper { |
| 6164 | private: |
| 6165 | virtual const RegMask *in_RegMask(int index) const; |
| 6166 | public: |
| 6167 | rxmm3Oper() {} |
| 6168 | virtual MachOper *clone() const; |
| 6169 | virtual uint opcode() const { return RXMM3; } |
| 6170 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6171 | |
| 6172 | |
| 6173 | #ifndef PRODUCT |
| 6174 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6175 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6176 | virtual const char *Name() const { return "rxmm3";} |
| 6177 | #endif |
| 6178 | }; |
| 6179 | |
| 6180 | class rxmm4Oper : public MachOper { |
| 6181 | private: |
| 6182 | virtual const RegMask *in_RegMask(int index) const; |
| 6183 | public: |
| 6184 | rxmm4Oper() {} |
| 6185 | virtual MachOper *clone() const; |
| 6186 | virtual uint opcode() const { return RXMM4; } |
| 6187 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6188 | |
| 6189 | |
| 6190 | #ifndef PRODUCT |
| 6191 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6192 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6193 | virtual const char *Name() const { return "rxmm4";} |
| 6194 | #endif |
| 6195 | }; |
| 6196 | |
| 6197 | class rxmm5Oper : public MachOper { |
| 6198 | private: |
| 6199 | virtual const RegMask *in_RegMask(int index) const; |
| 6200 | public: |
| 6201 | rxmm5Oper() {} |
| 6202 | virtual MachOper *clone() const; |
| 6203 | virtual uint opcode() const { return RXMM5; } |
| 6204 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6205 | |
| 6206 | |
| 6207 | #ifndef PRODUCT |
| 6208 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6209 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6210 | virtual const char *Name() const { return "rxmm5";} |
| 6211 | #endif |
| 6212 | }; |
| 6213 | |
| 6214 | class rxmm6Oper : public MachOper { |
| 6215 | private: |
| 6216 | virtual const RegMask *in_RegMask(int index) const; |
| 6217 | public: |
| 6218 | rxmm6Oper() {} |
| 6219 | virtual MachOper *clone() const; |
| 6220 | virtual uint opcode() const { return RXMM6; } |
| 6221 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6222 | |
| 6223 | |
| 6224 | #ifndef PRODUCT |
| 6225 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6226 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6227 | virtual const char *Name() const { return "rxmm6";} |
| 6228 | #endif |
| 6229 | }; |
| 6230 | |
| 6231 | class rxmm7Oper : public MachOper { |
| 6232 | private: |
| 6233 | virtual const RegMask *in_RegMask(int index) const; |
| 6234 | public: |
| 6235 | rxmm7Oper() {} |
| 6236 | virtual MachOper *clone() const; |
| 6237 | virtual uint opcode() const { return RXMM7; } |
| 6238 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6239 | |
| 6240 | |
| 6241 | #ifndef PRODUCT |
| 6242 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6243 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6244 | virtual const char *Name() const { return "rxmm7";} |
| 6245 | #endif |
| 6246 | }; |
| 6247 | |
| 6248 | class rxmm8Oper : public MachOper { |
| 6249 | private: |
| 6250 | virtual const RegMask *in_RegMask(int index) const; |
| 6251 | public: |
| 6252 | rxmm8Oper() {} |
| 6253 | virtual MachOper *clone() const; |
| 6254 | virtual uint opcode() const { return RXMM8; } |
| 6255 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6256 | |
| 6257 | |
| 6258 | #ifndef PRODUCT |
| 6259 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6260 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6261 | virtual const char *Name() const { return "rxmm8";} |
| 6262 | #endif |
| 6263 | }; |
| 6264 | |
| 6265 | class rxmm9Oper : public MachOper { |
| 6266 | private: |
| 6267 | virtual const RegMask *in_RegMask(int index) const; |
| 6268 | public: |
| 6269 | rxmm9Oper() {} |
| 6270 | virtual MachOper *clone() const; |
| 6271 | virtual uint opcode() const { return RXMM9; } |
| 6272 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6273 | |
| 6274 | |
| 6275 | #ifndef PRODUCT |
| 6276 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6277 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6278 | virtual const char *Name() const { return "rxmm9";} |
| 6279 | #endif |
| 6280 | }; |
| 6281 | |
| 6282 | class rxmm10Oper : public MachOper { |
| 6283 | private: |
| 6284 | virtual const RegMask *in_RegMask(int index) const; |
| 6285 | public: |
| 6286 | rxmm10Oper() {} |
| 6287 | virtual MachOper *clone() const; |
| 6288 | virtual uint opcode() const { return RXMM10; } |
| 6289 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6290 | |
| 6291 | |
| 6292 | #ifndef PRODUCT |
| 6293 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6294 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6295 | virtual const char *Name() const { return "rxmm10";} |
| 6296 | #endif |
| 6297 | }; |
| 6298 | |
| 6299 | class rxmm11Oper : public MachOper { |
| 6300 | private: |
| 6301 | virtual const RegMask *in_RegMask(int index) const; |
| 6302 | public: |
| 6303 | rxmm11Oper() {} |
| 6304 | virtual MachOper *clone() const; |
| 6305 | virtual uint opcode() const { return RXMM11; } |
| 6306 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6307 | |
| 6308 | |
| 6309 | #ifndef PRODUCT |
| 6310 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6311 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6312 | virtual const char *Name() const { return "rxmm11";} |
| 6313 | #endif |
| 6314 | }; |
| 6315 | |
| 6316 | class rxmm12Oper : public MachOper { |
| 6317 | private: |
| 6318 | virtual const RegMask *in_RegMask(int index) const; |
| 6319 | public: |
| 6320 | rxmm12Oper() {} |
| 6321 | virtual MachOper *clone() const; |
| 6322 | virtual uint opcode() const { return RXMM12; } |
| 6323 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6324 | |
| 6325 | |
| 6326 | #ifndef PRODUCT |
| 6327 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6328 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6329 | virtual const char *Name() const { return "rxmm12";} |
| 6330 | #endif |
| 6331 | }; |
| 6332 | |
| 6333 | class rxmm13Oper : public MachOper { |
| 6334 | private: |
| 6335 | virtual const RegMask *in_RegMask(int index) const; |
| 6336 | public: |
| 6337 | rxmm13Oper() {} |
| 6338 | virtual MachOper *clone() const; |
| 6339 | virtual uint opcode() const { return RXMM13; } |
| 6340 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6341 | |
| 6342 | |
| 6343 | #ifndef PRODUCT |
| 6344 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6345 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6346 | virtual const char *Name() const { return "rxmm13";} |
| 6347 | #endif |
| 6348 | }; |
| 6349 | |
| 6350 | class rxmm14Oper : public MachOper { |
| 6351 | private: |
| 6352 | virtual const RegMask *in_RegMask(int index) const; |
| 6353 | public: |
| 6354 | rxmm14Oper() {} |
| 6355 | virtual MachOper *clone() const; |
| 6356 | virtual uint opcode() const { return RXMM14; } |
| 6357 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6358 | |
| 6359 | |
| 6360 | #ifndef PRODUCT |
| 6361 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6362 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6363 | virtual const char *Name() const { return "rxmm14";} |
| 6364 | #endif |
| 6365 | }; |
| 6366 | |
| 6367 | class rxmm15Oper : public MachOper { |
| 6368 | private: |
| 6369 | virtual const RegMask *in_RegMask(int index) const; |
| 6370 | public: |
| 6371 | rxmm15Oper() {} |
| 6372 | virtual MachOper *clone() const; |
| 6373 | virtual uint opcode() const { return RXMM15; } |
| 6374 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6375 | |
| 6376 | |
| 6377 | #ifndef PRODUCT |
| 6378 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6379 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6380 | virtual const char *Name() const { return "rxmm15";} |
| 6381 | #endif |
| 6382 | }; |
| 6383 | |
| 6384 | class rxmm16Oper : public MachOper { |
| 6385 | private: |
| 6386 | virtual const RegMask *in_RegMask(int index) const; |
| 6387 | public: |
| 6388 | rxmm16Oper() {} |
| 6389 | virtual MachOper *clone() const; |
| 6390 | virtual uint opcode() const { return RXMM16; } |
| 6391 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6392 | |
| 6393 | |
| 6394 | #ifndef PRODUCT |
| 6395 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6396 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6397 | virtual const char *Name() const { return "rxmm16";} |
| 6398 | #endif |
| 6399 | }; |
| 6400 | |
| 6401 | class rxmm17Oper : public MachOper { |
| 6402 | private: |
| 6403 | virtual const RegMask *in_RegMask(int index) const; |
| 6404 | public: |
| 6405 | rxmm17Oper() {} |
| 6406 | virtual MachOper *clone() const; |
| 6407 | virtual uint opcode() const { return RXMM17; } |
| 6408 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6409 | |
| 6410 | |
| 6411 | #ifndef PRODUCT |
| 6412 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6413 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6414 | virtual const char *Name() const { return "rxmm17";} |
| 6415 | #endif |
| 6416 | }; |
| 6417 | |
| 6418 | class rxmm18Oper : public MachOper { |
| 6419 | private: |
| 6420 | virtual const RegMask *in_RegMask(int index) const; |
| 6421 | public: |
| 6422 | rxmm18Oper() {} |
| 6423 | virtual MachOper *clone() const; |
| 6424 | virtual uint opcode() const { return RXMM18; } |
| 6425 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6426 | |
| 6427 | |
| 6428 | #ifndef PRODUCT |
| 6429 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6430 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6431 | virtual const char *Name() const { return "rxmm18";} |
| 6432 | #endif |
| 6433 | }; |
| 6434 | |
| 6435 | class rxmm19Oper : public MachOper { |
| 6436 | private: |
| 6437 | virtual const RegMask *in_RegMask(int index) const; |
| 6438 | public: |
| 6439 | rxmm19Oper() {} |
| 6440 | virtual MachOper *clone() const; |
| 6441 | virtual uint opcode() const { return RXMM19; } |
| 6442 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6443 | |
| 6444 | |
| 6445 | #ifndef PRODUCT |
| 6446 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6447 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6448 | virtual const char *Name() const { return "rxmm19";} |
| 6449 | #endif |
| 6450 | }; |
| 6451 | |
| 6452 | class rxmm20Oper : public MachOper { |
| 6453 | private: |
| 6454 | virtual const RegMask *in_RegMask(int index) const; |
| 6455 | public: |
| 6456 | rxmm20Oper() {} |
| 6457 | virtual MachOper *clone() const; |
| 6458 | virtual uint opcode() const { return RXMM20; } |
| 6459 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6460 | |
| 6461 | |
| 6462 | #ifndef PRODUCT |
| 6463 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6464 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6465 | virtual const char *Name() const { return "rxmm20";} |
| 6466 | #endif |
| 6467 | }; |
| 6468 | |
| 6469 | class rxmm21Oper : public MachOper { |
| 6470 | private: |
| 6471 | virtual const RegMask *in_RegMask(int index) const; |
| 6472 | public: |
| 6473 | rxmm21Oper() {} |
| 6474 | virtual MachOper *clone() const; |
| 6475 | virtual uint opcode() const { return RXMM21; } |
| 6476 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6477 | |
| 6478 | |
| 6479 | #ifndef PRODUCT |
| 6480 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6481 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6482 | virtual const char *Name() const { return "rxmm21";} |
| 6483 | #endif |
| 6484 | }; |
| 6485 | |
| 6486 | class rxmm22Oper : public MachOper { |
| 6487 | private: |
| 6488 | virtual const RegMask *in_RegMask(int index) const; |
| 6489 | public: |
| 6490 | rxmm22Oper() {} |
| 6491 | virtual MachOper *clone() const; |
| 6492 | virtual uint opcode() const { return RXMM22; } |
| 6493 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6494 | |
| 6495 | |
| 6496 | #ifndef PRODUCT |
| 6497 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6498 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6499 | virtual const char *Name() const { return "rxmm22";} |
| 6500 | #endif |
| 6501 | }; |
| 6502 | |
| 6503 | class rxmm23Oper : public MachOper { |
| 6504 | private: |
| 6505 | virtual const RegMask *in_RegMask(int index) const; |
| 6506 | public: |
| 6507 | rxmm23Oper() {} |
| 6508 | virtual MachOper *clone() const; |
| 6509 | virtual uint opcode() const { return RXMM23; } |
| 6510 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6511 | |
| 6512 | |
| 6513 | #ifndef PRODUCT |
| 6514 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6515 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6516 | virtual const char *Name() const { return "rxmm23";} |
| 6517 | #endif |
| 6518 | }; |
| 6519 | |
| 6520 | class rxmm24Oper : public MachOper { |
| 6521 | private: |
| 6522 | virtual const RegMask *in_RegMask(int index) const; |
| 6523 | public: |
| 6524 | rxmm24Oper() {} |
| 6525 | virtual MachOper *clone() const; |
| 6526 | virtual uint opcode() const { return RXMM24; } |
| 6527 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6528 | |
| 6529 | |
| 6530 | #ifndef PRODUCT |
| 6531 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6532 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6533 | virtual const char *Name() const { return "rxmm24";} |
| 6534 | #endif |
| 6535 | }; |
| 6536 | |
| 6537 | class rxmm25Oper : public MachOper { |
| 6538 | private: |
| 6539 | virtual const RegMask *in_RegMask(int index) const; |
| 6540 | public: |
| 6541 | rxmm25Oper() {} |
| 6542 | virtual MachOper *clone() const; |
| 6543 | virtual uint opcode() const { return RXMM25; } |
| 6544 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6545 | |
| 6546 | |
| 6547 | #ifndef PRODUCT |
| 6548 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6549 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6550 | virtual const char *Name() const { return "rxmm25";} |
| 6551 | #endif |
| 6552 | }; |
| 6553 | |
| 6554 | class rxmm26Oper : public MachOper { |
| 6555 | private: |
| 6556 | virtual const RegMask *in_RegMask(int index) const; |
| 6557 | public: |
| 6558 | rxmm26Oper() {} |
| 6559 | virtual MachOper *clone() const; |
| 6560 | virtual uint opcode() const { return RXMM26; } |
| 6561 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6562 | |
| 6563 | |
| 6564 | #ifndef PRODUCT |
| 6565 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6566 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6567 | virtual const char *Name() const { return "rxmm26";} |
| 6568 | #endif |
| 6569 | }; |
| 6570 | |
| 6571 | class rxmm27Oper : public MachOper { |
| 6572 | private: |
| 6573 | virtual const RegMask *in_RegMask(int index) const; |
| 6574 | public: |
| 6575 | rxmm27Oper() {} |
| 6576 | virtual MachOper *clone() const; |
| 6577 | virtual uint opcode() const { return RXMM27; } |
| 6578 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6579 | |
| 6580 | |
| 6581 | #ifndef PRODUCT |
| 6582 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6583 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6584 | virtual const char *Name() const { return "rxmm27";} |
| 6585 | #endif |
| 6586 | }; |
| 6587 | |
| 6588 | class rxmm28Oper : public MachOper { |
| 6589 | private: |
| 6590 | virtual const RegMask *in_RegMask(int index) const; |
| 6591 | public: |
| 6592 | rxmm28Oper() {} |
| 6593 | virtual MachOper *clone() const; |
| 6594 | virtual uint opcode() const { return RXMM28; } |
| 6595 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6596 | |
| 6597 | |
| 6598 | #ifndef PRODUCT |
| 6599 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6600 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6601 | virtual const char *Name() const { return "rxmm28";} |
| 6602 | #endif |
| 6603 | }; |
| 6604 | |
| 6605 | class rxmm29Oper : public MachOper { |
| 6606 | private: |
| 6607 | virtual const RegMask *in_RegMask(int index) const; |
| 6608 | public: |
| 6609 | rxmm29Oper() {} |
| 6610 | virtual MachOper *clone() const; |
| 6611 | virtual uint opcode() const { return RXMM29; } |
| 6612 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6613 | |
| 6614 | |
| 6615 | #ifndef PRODUCT |
| 6616 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6617 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6618 | virtual const char *Name() const { return "rxmm29";} |
| 6619 | #endif |
| 6620 | }; |
| 6621 | |
| 6622 | class rxmm30Oper : public MachOper { |
| 6623 | private: |
| 6624 | virtual const RegMask *in_RegMask(int index) const; |
| 6625 | public: |
| 6626 | rxmm30Oper() {} |
| 6627 | virtual MachOper *clone() const; |
| 6628 | virtual uint opcode() const { return RXMM30; } |
| 6629 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6630 | |
| 6631 | |
| 6632 | #ifndef PRODUCT |
| 6633 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6634 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6635 | virtual const char *Name() const { return "rxmm30";} |
| 6636 | #endif |
| 6637 | }; |
| 6638 | |
| 6639 | class rxmm31Oper : public MachOper { |
| 6640 | private: |
| 6641 | virtual const RegMask *in_RegMask(int index) const; |
| 6642 | public: |
| 6643 | rxmm31Oper() {} |
| 6644 | virtual MachOper *clone() const; |
| 6645 | virtual uint opcode() const { return RXMM31; } |
| 6646 | virtual const Type *type() const { return TypeVect::VECTX; } |
| 6647 | |
| 6648 | |
| 6649 | #ifndef PRODUCT |
| 6650 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6651 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6652 | virtual const char *Name() const { return "rxmm31";} |
| 6653 | #endif |
| 6654 | }; |
| 6655 | |
| 6656 | class vecZOper : public MachOper { |
| 6657 | private: |
| 6658 | virtual const RegMask *in_RegMask(int index) const; |
| 6659 | public: |
| 6660 | vecZOper() {} |
| 6661 | virtual MachOper *clone() const; |
| 6662 | virtual uint opcode() const { return VECZ; } |
| 6663 | virtual const Type *type() const { return TypeVect::VECTZ; } |
| 6664 | |
| 6665 | |
| 6666 | #ifndef PRODUCT |
| 6667 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6668 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6669 | virtual const char *Name() const { return "vecZ";} |
| 6670 | #endif |
| 6671 | }; |
| 6672 | |
| 6673 | class legVecZOper : public MachOper { |
| 6674 | private: |
| 6675 | virtual const RegMask *in_RegMask(int index) const; |
| 6676 | public: |
| 6677 | legVecZOper() {} |
| 6678 | virtual MachOper *clone() const; |
| 6679 | virtual uint opcode() const { return LEGVECZ; } |
| 6680 | virtual const Type *type() const { return TypeVect::VECTZ; } |
| 6681 | |
| 6682 | |
| 6683 | #ifndef PRODUCT |
| 6684 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6685 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6686 | virtual const char *Name() const { return "legVecZ";} |
| 6687 | #endif |
| 6688 | }; |
| 6689 | |
| 6690 | class cmpOp_vcmppdOper : public MachOper { |
| 6691 | private: |
| 6692 | virtual uint num_edges() const { return 0; } |
| 6693 | private: |
| 6694 | BoolTest::mask _c0; |
| 6695 | public: |
| 6696 | virtual int ccode() const { |
| 6697 | switch (_c0) { |
| 6698 | case BoolTest::eq : return equal(); |
| 6699 | case BoolTest::gt : return greater(); |
| 6700 | case BoolTest::lt : return less(); |
| 6701 | case BoolTest::ne : return not_equal(); |
| 6702 | case BoolTest::le : return less_equal(); |
| 6703 | case BoolTest::ge : return greater_equal(); |
| 6704 | case BoolTest::overflow : return overflow(); |
| 6705 | case BoolTest::no_overflow: return no_overflow(); |
| 6706 | default : ShouldNotReachHere(); return 0; |
| 6707 | } |
| 6708 | }; |
| 6709 | virtual void negate() { |
| 6710 | _c0 = (BoolTest::mask)((int)_c0^0x4); |
| 6711 | }; |
| 6712 | public: |
| 6713 | cmpOp_vcmppdOper(BoolTest::mask c0) : _c0(c0) {} |
| 6714 | virtual MachOper *clone() const; |
| 6715 | virtual uint opcode() const { return CMPOP_VCMPPD; } |
| 6716 | virtual const Type *type() const { ShouldNotCallThis(); return Type::BOTTOM; } |
| 6717 | |
| 6718 | virtual int equal() const { |
| 6719 | return 0x0; |
| 6720 | } |
| 6721 | virtual int not_equal() const { |
| 6722 | return 0xC; |
| 6723 | } |
| 6724 | virtual int less() const { |
| 6725 | return 0x1; |
| 6726 | } |
| 6727 | virtual int greater_equal() const { |
| 6728 | return 0xD; |
| 6729 | } |
| 6730 | virtual int less_equal() const { |
| 6731 | return 0x2; |
| 6732 | } |
| 6733 | virtual int greater() const { |
| 6734 | return 0xE; |
| 6735 | } |
| 6736 | virtual int overflow() const { |
| 6737 | return 0x20; |
| 6738 | } |
| 6739 | virtual int no_overflow() const { |
| 6740 | return 0x21; |
| 6741 | } |
| 6742 | |
| 6743 | #ifndef PRODUCT |
| 6744 | virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; |
| 6745 | virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const; |
| 6746 | virtual void dump_spec(outputStream *st) const { |
| 6747 | if( _c0 == BoolTest::eq ) st->print_raw("eq"); |
| 6748 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 6749 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 6750 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 6751 | else if( _c0 == BoolTest::lt ) st->print_raw("lt"); |
| 6752 | else if( _c0 == BoolTest::gt ) st->print_raw("gt"); |
| 6753 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 6754 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 6755 | } |
| 6756 | virtual const char *Name() const { return "cmpOp_vcmppd";} |
| 6757 | #endif |
| 6758 | }; |
| 6759 | |
| 6760 | //----------------------------Declare classes for Pipelines----------------- |
| 6761 | |
| 6762 | // Pipeline_Use_Cycle_Mask Class |
| 6763 | class Pipeline_Use_Cycle_Mask { |
| 6764 | protected: |
| 6765 | uint _mask; |
| 6766 | |
| 6767 | public: |
| 6768 | Pipeline_Use_Cycle_Mask() : _mask(0) {} |
| 6769 | |
| 6770 | Pipeline_Use_Cycle_Mask(uint mask) : _mask(mask) {} |
| 6771 | |
| 6772 | Pipeline_Use_Cycle_Mask& operator=(const Pipeline_Use_Cycle_Mask &in) { |
| 6773 | _mask = in._mask; |
| 6774 | return *this; |
| 6775 | } |
| 6776 | |
| 6777 | bool overlaps(const Pipeline_Use_Cycle_Mask &in2) const { |
| 6778 | return ((_mask & in2._mask) != 0); |
| 6779 | } |
| 6780 | |
| 6781 | Pipeline_Use_Cycle_Mask& operator<<=(int n) { |
| 6782 | _mask <<= n; |
| 6783 | return *this; |
| 6784 | } |
| 6785 | |
| 6786 | void Or(const Pipeline_Use_Cycle_Mask &in2) { |
| 6787 | _mask |= in2._mask; |
| 6788 | } |
| 6789 | |
| 6790 | friend Pipeline_Use_Cycle_Mask operator&(const Pipeline_Use_Cycle_Mask &, const Pipeline_Use_Cycle_Mask &); |
| 6791 | friend Pipeline_Use_Cycle_Mask operator|(const Pipeline_Use_Cycle_Mask &, const Pipeline_Use_Cycle_Mask &); |
| 6792 | |
| 6793 | friend class Pipeline_Use; |
| 6794 | |
| 6795 | friend class Pipeline_Use_Element; |
| 6796 | |
| 6797 | }; |
| 6798 | |
| 6799 | // Pipeline_Use_Element Class |
| 6800 | class Pipeline_Use_Element { |
| 6801 | protected: |
| 6802 | // Mask of used functional units |
| 6803 | uint _used; |
| 6804 | |
| 6805 | // Lower and upper bound of functional unit number range |
| 6806 | uint _lb, _ub; |
| 6807 | |
| 6808 | // Indicates multiple functionals units available |
| 6809 | bool _multiple; |
| 6810 | |
| 6811 | // Mask of specific used cycles |
| 6812 | Pipeline_Use_Cycle_Mask _mask; |
| 6813 | |
| 6814 | public: |
| 6815 | Pipeline_Use_Element() {} |
| 6816 | |
| 6817 | Pipeline_Use_Element(uint used, uint lb, uint ub, bool multiple, Pipeline_Use_Cycle_Mask mask) |
| 6818 | : _used(used), _lb(lb), _ub(ub), _multiple(multiple), _mask(mask) {} |
| 6819 | |
| 6820 | uint used() const { return _used; } |
| 6821 | |
| 6822 | uint lowerBound() const { return _lb; } |
| 6823 | |
| 6824 | uint upperBound() const { return _ub; } |
| 6825 | |
| 6826 | bool multiple() const { return _multiple; } |
| 6827 | |
| 6828 | Pipeline_Use_Cycle_Mask mask() const { return _mask; } |
| 6829 | |
| 6830 | bool overlaps(const Pipeline_Use_Element &in2) const { |
| 6831 | return ((_used & in2._used) != 0 && _mask.overlaps(in2._mask)); |
| 6832 | } |
| 6833 | |
| 6834 | void step(uint cycles) { |
| 6835 | _used = 0; |
| 6836 | _mask <<= cycles; |
| 6837 | } |
| 6838 | |
| 6839 | friend class Pipeline_Use; |
| 6840 | }; |
| 6841 | |
| 6842 | // Pipeline_Use Class |
| 6843 | class Pipeline_Use { |
| 6844 | protected: |
| 6845 | // These resources can be used |
| 6846 | uint _resources_used; |
| 6847 | |
| 6848 | // These resources are used; excludes multiple choice functional units |
| 6849 | uint _resources_used_exclusively; |
| 6850 | |
| 6851 | // Number of elements |
| 6852 | uint _count; |
| 6853 | |
| 6854 | // This is the array of Pipeline_Use_Elements |
| 6855 | Pipeline_Use_Element * _elements; |
| 6856 | |
| 6857 | public: |
| 6858 | Pipeline_Use(uint resources_used, uint resources_used_exclusively, uint count, Pipeline_Use_Element *elements) |
| 6859 | : _resources_used(resources_used) |
| 6860 | , _resources_used_exclusively(resources_used_exclusively) |
| 6861 | , _count(count) |
| 6862 | , _elements(elements) |
| 6863 | {} |
| 6864 | |
| 6865 | uint resourcesUsed() const { return _resources_used; } |
| 6866 | |
| 6867 | uint resourcesUsedExclusively() const { return _resources_used_exclusively; } |
| 6868 | |
| 6869 | uint count() const { return _count; } |
| 6870 | |
| 6871 | Pipeline_Use_Element * element(uint i) const { return &_elements[i]; } |
| 6872 | |
| 6873 | uint full_latency(uint delay, const Pipeline_Use &pred) const; |
| 6874 | |
| 6875 | void add_usage(const Pipeline_Use &pred); |
| 6876 | |
| 6877 | void reset() { |
| 6878 | _resources_used = _resources_used_exclusively = 0; |
| 6879 | }; |
| 6880 | |
| 6881 | void step(uint cycles) { |
| 6882 | reset(); |
| 6883 | for (uint i = 0; i < 11; i++) |
| 6884 | (&_elements[i])->step(cycles); |
| 6885 | }; |
| 6886 | |
| 6887 | static const Pipeline_Use elaborated_use; |
| 6888 | static const Pipeline_Use_Element elaborated_elements[11]; |
| 6889 | |
| 6890 | friend class Pipeline; |
| 6891 | }; |
| 6892 | |
| 6893 | // Pipeline Class |
| 6894 | class Pipeline { |
| 6895 | public: |
| 6896 | static bool enabled() { return true; } |
| 6897 | |
| 6898 | enum { |
| 6899 | _variable_size_instructions = 1, |
| 6900 | _fixed_size_instructions = 0, |
| 6901 | _branch_has_delay_slot = 0, |
| 6902 | _max_instrs_per_bundle = 3, |
| 6903 | _max_bundles_per_cycle = 1, |
| 6904 | _max_instrs_per_cycle = 3 |
| 6905 | }; |
| 6906 | |
| 6907 | static bool instr_has_unit_size() { return true; } |
| 6908 | |
| 6909 | // Bundling is not supported |
| 6910 | |
| 6911 | // Size of an instruction |
| 6912 | static uint instr_unit_size() { return 1; }; |
| 6913 | |
| 6914 | // Bundles do not exist - unsupported |
| 6915 | static uint bundle_unit_size() { assert( false, "Bundles are not supported"); return 0; }; |
| 6916 | |
| 6917 | static bool requires_bundling() { return false; } |
| 6918 | |
| 6919 | private: |
| 6920 | Pipeline(); // Not a legal constructor |
| 6921 | |
| 6922 | const unsigned char _read_stage_count; |
| 6923 | const unsigned char _write_stage; |
| 6924 | const unsigned char _fixed_latency; |
| 6925 | const unsigned char _instruction_count; |
| 6926 | const bool _has_fixed_latency; |
| 6927 | const bool _has_branch_delay; |
| 6928 | const bool _has_multiple_bundles; |
| 6929 | const bool _force_serialization; |
| 6930 | const bool _may_have_no_code; |
| 6931 | const enum machPipelineStages * const _read_stages; |
| 6932 | const enum machPipelineStages * const _resource_stage; |
| 6933 | const uint * const _resource_cycles; |
| 6934 | const Pipeline_Use _resource_use; |
| 6935 | |
| 6936 | public: |
| 6937 | Pipeline(uint write_stage, |
| 6938 | uint count, |
| 6939 | bool has_fixed_latency, |
| 6940 | uint fixed_latency, |
| 6941 | uint instruction_count, |
| 6942 | bool has_branch_delay, |
| 6943 | bool has_multiple_bundles, |
| 6944 | bool force_serialization, |
| 6945 | bool may_have_no_code, |
| 6946 | enum machPipelineStages * const dst, |
| 6947 | enum machPipelineStages * const stage, |
| 6948 | uint * const cycles, |
| 6949 | Pipeline_Use resource_use) |
| 6950 | : _read_stage_count(count) |
| 6951 | , _write_stage(write_stage) |
| 6952 | , _fixed_latency(fixed_latency) |
| 6953 | , _instruction_count(instruction_count) |
| 6954 | , _has_fixed_latency(has_fixed_latency) |
| 6955 | , _has_branch_delay(has_branch_delay) |
| 6956 | , _has_multiple_bundles(has_multiple_bundles) |
| 6957 | , _force_serialization(force_serialization) |
| 6958 | , _may_have_no_code(may_have_no_code) |
| 6959 | , _read_stages(dst) |
| 6960 | , _resource_stage(stage) |
| 6961 | , _resource_cycles(cycles) |
| 6962 | , _resource_use(resource_use) |
| 6963 | {}; |
| 6964 | |
| 6965 | uint writeStage() const { |
| 6966 | return (_write_stage); |
| 6967 | } |
| 6968 | |
| 6969 | enum machPipelineStages readStage(int ndx) const { |
| 6970 | return (ndx < _read_stage_count ? _read_stages[ndx] : stage_undefined); } |
| 6971 | |
| 6972 | uint resourcesUsed() const { |
| 6973 | return _resource_use.resourcesUsed(); |
| 6974 | } |
| 6975 | |
| 6976 | uint resourcesUsedExclusively() const { |
| 6977 | return _resource_use.resourcesUsedExclusively(); |
| 6978 | } |
| 6979 | |
| 6980 | bool hasFixedLatency() const { |
| 6981 | return (_has_fixed_latency); |
| 6982 | } |
| 6983 | |
| 6984 | uint fixedLatency() const { |
| 6985 | return (_fixed_latency); |
| 6986 | } |
| 6987 | |
| 6988 | uint functional_unit_latency(uint start, const Pipeline *pred) const; |
| 6989 | |
| 6990 | uint operand_latency(uint opnd, const Pipeline *pred) const; |
| 6991 | |
| 6992 | const Pipeline_Use& resourceUse() const { |
| 6993 | return (_resource_use); } |
| 6994 | |
| 6995 | const Pipeline_Use_Element * resourceUseElement(uint i) const { |
| 6996 | return (&_resource_use._elements[i]); } |
| 6997 | |
| 6998 | uint resourceUseCount() const { |
| 6999 | return (_resource_use._count); } |
| 7000 | |
| 7001 | uint instructionCount() const { |
| 7002 | return (_instruction_count); } |
| 7003 | |
| 7004 | bool hasBranchDelay() const { |
| 7005 | return (_has_branch_delay); } |
| 7006 | |
| 7007 | bool hasMultipleBundles() const { |
| 7008 | return (_has_multiple_bundles); } |
| 7009 | |
| 7010 | bool forceSerialization() const { |
| 7011 | return (_force_serialization); } |
| 7012 | |
| 7013 | bool mayHaveNoCode() const { |
| 7014 | return (_may_have_no_code); } |
| 7015 | |
| 7016 | //const Pipeline_Use_Cycle_Mask& resourceUseMask(int resource) const { |
| 7017 | // return (_resource_use_masks[resource]); } |
| 7018 | |
| 7019 | |
| 7020 | #ifndef PRODUCT |
| 7021 | static const char * stageName(uint i); |
| 7022 | #endif |
| 7023 | }; |
| 7024 | |
| 7025 | // Bundle class |
| 7026 | class Bundle { |
| 7027 | protected: |
| 7028 | enum { |
| 7029 | _unused_delay = 0x0, |
| 7030 | _use_nop_delay = 0x1, |
| 7031 | _use_unconditional_delay = 0x2, |
| 7032 | _use_conditional_delay = 0x3, |
| 7033 | _used_in_conditional_delay = 0x4, |
| 7034 | _used_in_unconditional_delay = 0x5, |
| 7035 | _used_in_all_conditional_delays = 0x6, |
| 7036 | |
| 7037 | _use_delay = 0x3, |
| 7038 | _used_in_delay = 0x4 |
| 7039 | }; |
| 7040 | |
| 7041 | uint _flags : 3, |
| 7042 | _starts_bundle : 1, |
| 7043 | _instr_count : 2, |
| 7044 | _resources_used : 11; |
| 7045 | public: |
| 7046 | Bundle() : _flags(_unused_delay), _starts_bundle(0), _instr_count(0), _resources_used(0) {} |
| 7047 | |
| 7048 | void set_instr_count(uint i) { _instr_count = i; } |
| 7049 | void set_resources_used(uint i) { _resources_used = i; } |
| 7050 | void clear_usage() { _flags = _unused_delay; } |
| 7051 | void set_starts_bundle() { _starts_bundle = true; } |
| 7052 | uint flags() const { return (_flags); } |
| 7053 | uint instr_count() const { return (_instr_count); } |
| 7054 | uint resources_used() const { return (_resources_used); } |
| 7055 | bool starts_bundle() const { return (_starts_bundle != 0); } |
| 7056 | void set_use_nop_delay() { _flags = _use_nop_delay; } |
| 7057 | void set_use_unconditional_delay() { _flags = _use_unconditional_delay; } |
| 7058 | void set_use_conditional_delay() { _flags = _use_conditional_delay; } |
| 7059 | void set_used_in_unconditional_delay() { _flags = _used_in_unconditional_delay; } |
| 7060 | void set_used_in_conditional_delay() { _flags = _used_in_conditional_delay; } |
| 7061 | void set_used_in_all_conditional_delays() { _flags = _used_in_all_conditional_delays; } |
| 7062 | bool use_nop_delay() { return (_flags == _use_nop_delay); } |
| 7063 | bool use_unconditional_delay() { return (_flags == _use_unconditional_delay); } |
| 7064 | bool use_conditional_delay() { return (_flags == _use_conditional_delay); } |
| 7065 | bool used_in_unconditional_delay() { return (_flags == _used_in_unconditional_delay); } |
| 7066 | bool used_in_conditional_delay() { return (_flags == _used_in_conditional_delay); } |
| 7067 | bool used_in_all_conditional_delays() { return (_flags == _used_in_all_conditional_delays); } |
| 7068 | bool use_delay() { return ((_flags & _use_delay) != 0); } |
| 7069 | bool used_in_delay() { return ((_flags & _used_in_delay) != 0); } |
| 7070 | |
| 7071 | enum { |
| 7072 | _nop_count = 1 |
| 7073 | }; |
| 7074 | |
| 7075 | static void initialize_nops(MachNode *nop_list[1]); |
| 7076 | |
| 7077 | #ifndef PRODUCT |
| 7078 | void dump(outputStream *st = tty) const; |
| 7079 | #endif |
| 7080 | }; |
| 7081 | |
| 7082 | |
| 7083 | //----------------------------Declare classes derived from MachNode---------- |
| 7084 | |
| 7085 | class loadBNode : public MachNode { |
| 7086 | private: |
| 7087 | MachOper *_opnd_array[2]; |
| 7088 | public: |
| 7089 | MachOper *opnd_array(uint operand_index) const { |
| 7090 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7091 | return _opnd_array[operand_index]; |
| 7092 | } |
| 7093 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7094 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7095 | _opnd_array[operand_index] = operand; |
| 7096 | } |
| 7097 | private: |
| 7098 | virtual const RegMask &out_RegMask() const; |
| 7099 | virtual uint rule() const { return loadB_rule; } |
| 7100 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7101 | virtual int ideal_Opcode() const { return Op_LoadB; } |
| 7102 | virtual int reloc() const; |
| 7103 | virtual uint oper_input_base() const { return 2; } |
| 7104 | public: |
| 7105 | loadBNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7106 | virtual uint size_of() const { return sizeof(loadBNode); } |
| 7107 | static const Pipeline *pipeline_class(); |
| 7108 | virtual const Pipeline *pipeline() const; |
| 7109 | virtual const MachOper *memory_operand() const; |
| 7110 | #ifndef PRODUCT |
| 7111 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7112 | virtual const char *Name() const { return "loadB";} |
| 7113 | #endif |
| 7114 | }; |
| 7115 | |
| 7116 | class loadB2LNode : public MachNode { |
| 7117 | private: |
| 7118 | MachOper *_opnd_array[2]; |
| 7119 | public: |
| 7120 | MachOper *opnd_array(uint operand_index) const { |
| 7121 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7122 | return _opnd_array[operand_index]; |
| 7123 | } |
| 7124 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7125 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7126 | _opnd_array[operand_index] = operand; |
| 7127 | } |
| 7128 | private: |
| 7129 | virtual const RegMask &out_RegMask() const; |
| 7130 | virtual uint rule() const { return loadB2L_rule; } |
| 7131 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7132 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7133 | virtual int reloc() const; |
| 7134 | virtual uint oper_input_base() const { return 2; } |
| 7135 | public: |
| 7136 | loadB2LNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7137 | virtual uint size_of() const { return sizeof(loadB2LNode); } |
| 7138 | static const Pipeline *pipeline_class(); |
| 7139 | virtual const Pipeline *pipeline() const; |
| 7140 | virtual const MachOper *memory_operand() const; |
| 7141 | #ifndef PRODUCT |
| 7142 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7143 | virtual const char *Name() const { return "loadB2L";} |
| 7144 | #endif |
| 7145 | }; |
| 7146 | |
| 7147 | class loadUBNode : public MachNode { |
| 7148 | private: |
| 7149 | MachOper *_opnd_array[2]; |
| 7150 | public: |
| 7151 | MachOper *opnd_array(uint operand_index) const { |
| 7152 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7153 | return _opnd_array[operand_index]; |
| 7154 | } |
| 7155 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7156 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7157 | _opnd_array[operand_index] = operand; |
| 7158 | } |
| 7159 | private: |
| 7160 | virtual const RegMask &out_RegMask() const; |
| 7161 | virtual uint rule() const { return loadUB_rule; } |
| 7162 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7163 | virtual int ideal_Opcode() const { return Op_LoadUB; } |
| 7164 | virtual int reloc() const; |
| 7165 | virtual uint oper_input_base() const { return 2; } |
| 7166 | public: |
| 7167 | loadUBNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7168 | virtual uint size_of() const { return sizeof(loadUBNode); } |
| 7169 | static const Pipeline *pipeline_class(); |
| 7170 | virtual const Pipeline *pipeline() const; |
| 7171 | virtual const MachOper *memory_operand() const; |
| 7172 | #ifndef PRODUCT |
| 7173 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7174 | virtual const char *Name() const { return "loadUB";} |
| 7175 | #endif |
| 7176 | }; |
| 7177 | |
| 7178 | class loadUB2LNode : public MachNode { |
| 7179 | private: |
| 7180 | MachOper *_opnd_array[2]; |
| 7181 | public: |
| 7182 | MachOper *opnd_array(uint operand_index) const { |
| 7183 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7184 | return _opnd_array[operand_index]; |
| 7185 | } |
| 7186 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7187 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7188 | _opnd_array[operand_index] = operand; |
| 7189 | } |
| 7190 | private: |
| 7191 | virtual const RegMask &out_RegMask() const; |
| 7192 | virtual uint rule() const { return loadUB2L_rule; } |
| 7193 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7194 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7195 | virtual int reloc() const; |
| 7196 | virtual uint oper_input_base() const { return 2; } |
| 7197 | public: |
| 7198 | loadUB2LNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7199 | virtual uint size_of() const { return sizeof(loadUB2LNode); } |
| 7200 | static const Pipeline *pipeline_class(); |
| 7201 | virtual const Pipeline *pipeline() const; |
| 7202 | virtual const MachOper *memory_operand() const; |
| 7203 | #ifndef PRODUCT |
| 7204 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7205 | virtual const char *Name() const { return "loadUB2L";} |
| 7206 | #endif |
| 7207 | }; |
| 7208 | |
| 7209 | class loadUB2L_immINode : public MachNode { |
| 7210 | private: |
| 7211 | MachOper *_opnd_array[3]; |
| 7212 | public: |
| 7213 | MachOper *opnd_array(uint operand_index) const { |
| 7214 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7215 | return _opnd_array[operand_index]; |
| 7216 | } |
| 7217 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7218 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7219 | _opnd_array[operand_index] = operand; |
| 7220 | } |
| 7221 | private: |
| 7222 | virtual const RegMask &out_RegMask() const; |
| 7223 | virtual uint rule() const { return loadUB2L_immI_rule; } |
| 7224 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7225 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7226 | virtual int reloc() const; |
| 7227 | virtual uint oper_input_base() const { return 2; } |
| 7228 | public: |
| 7229 | loadUB2L_immINode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7230 | virtual uint size_of() const { return sizeof(loadUB2L_immINode); } |
| 7231 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7232 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 7233 | static const Pipeline *pipeline_class(); |
| 7234 | virtual const Pipeline *pipeline() const; |
| 7235 | virtual const MachOper *memory_operand() const; |
| 7236 | #ifndef PRODUCT |
| 7237 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7238 | virtual const char *Name() const { return "loadUB2L_immI";} |
| 7239 | #endif |
| 7240 | }; |
| 7241 | |
| 7242 | class loadSNode : public MachNode { |
| 7243 | private: |
| 7244 | MachOper *_opnd_array[2]; |
| 7245 | public: |
| 7246 | MachOper *opnd_array(uint operand_index) const { |
| 7247 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7248 | return _opnd_array[operand_index]; |
| 7249 | } |
| 7250 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7251 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7252 | _opnd_array[operand_index] = operand; |
| 7253 | } |
| 7254 | private: |
| 7255 | virtual const RegMask &out_RegMask() const; |
| 7256 | virtual uint rule() const { return loadS_rule; } |
| 7257 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7258 | virtual int ideal_Opcode() const { return Op_LoadS; } |
| 7259 | virtual int reloc() const; |
| 7260 | virtual uint oper_input_base() const { return 2; } |
| 7261 | public: |
| 7262 | loadSNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7263 | virtual uint size_of() const { return sizeof(loadSNode); } |
| 7264 | static const Pipeline *pipeline_class(); |
| 7265 | virtual const Pipeline *pipeline() const; |
| 7266 | virtual const MachOper *memory_operand() const; |
| 7267 | #ifndef PRODUCT |
| 7268 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7269 | virtual const char *Name() const { return "loadS";} |
| 7270 | #endif |
| 7271 | }; |
| 7272 | |
| 7273 | class loadS2BNode : public MachNode { |
| 7274 | private: |
| 7275 | MachOper *_opnd_array[4]; |
| 7276 | public: |
| 7277 | MachOper *opnd_array(uint operand_index) const { |
| 7278 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7279 | return _opnd_array[operand_index]; |
| 7280 | } |
| 7281 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7282 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7283 | _opnd_array[operand_index] = operand; |
| 7284 | } |
| 7285 | private: |
| 7286 | virtual const RegMask &out_RegMask() const; |
| 7287 | virtual uint rule() const { return loadS2B_rule; } |
| 7288 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7289 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 7290 | virtual int reloc() const; |
| 7291 | virtual uint oper_input_base() const { return 2; } |
| 7292 | public: |
| 7293 | loadS2BNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7294 | virtual uint size_of() const { return sizeof(loadS2BNode); } |
| 7295 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7296 | static const Pipeline *pipeline_class(); |
| 7297 | virtual const Pipeline *pipeline() const; |
| 7298 | virtual const MachOper *memory_operand() const; |
| 7299 | #ifndef PRODUCT |
| 7300 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7301 | virtual const char *Name() const { return "loadS2B";} |
| 7302 | #endif |
| 7303 | }; |
| 7304 | |
| 7305 | class loadS2LNode : public MachNode { |
| 7306 | private: |
| 7307 | MachOper *_opnd_array[2]; |
| 7308 | public: |
| 7309 | MachOper *opnd_array(uint operand_index) const { |
| 7310 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7311 | return _opnd_array[operand_index]; |
| 7312 | } |
| 7313 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7314 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7315 | _opnd_array[operand_index] = operand; |
| 7316 | } |
| 7317 | private: |
| 7318 | virtual const RegMask &out_RegMask() const; |
| 7319 | virtual uint rule() const { return loadS2L_rule; } |
| 7320 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7321 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7322 | virtual int reloc() const; |
| 7323 | virtual uint oper_input_base() const { return 2; } |
| 7324 | public: |
| 7325 | loadS2LNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7326 | virtual uint size_of() const { return sizeof(loadS2LNode); } |
| 7327 | static const Pipeline *pipeline_class(); |
| 7328 | virtual const Pipeline *pipeline() const; |
| 7329 | virtual const MachOper *memory_operand() const; |
| 7330 | #ifndef PRODUCT |
| 7331 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7332 | virtual const char *Name() const { return "loadS2L";} |
| 7333 | #endif |
| 7334 | }; |
| 7335 | |
| 7336 | class loadUSNode : public MachNode { |
| 7337 | private: |
| 7338 | MachOper *_opnd_array[2]; |
| 7339 | public: |
| 7340 | MachOper *opnd_array(uint operand_index) const { |
| 7341 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7342 | return _opnd_array[operand_index]; |
| 7343 | } |
| 7344 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7345 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7346 | _opnd_array[operand_index] = operand; |
| 7347 | } |
| 7348 | private: |
| 7349 | virtual const RegMask &out_RegMask() const; |
| 7350 | virtual uint rule() const { return loadUS_rule; } |
| 7351 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7352 | virtual int ideal_Opcode() const { return Op_LoadUS; } |
| 7353 | virtual int reloc() const; |
| 7354 | virtual uint oper_input_base() const { return 2; } |
| 7355 | public: |
| 7356 | loadUSNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7357 | virtual uint size_of() const { return sizeof(loadUSNode); } |
| 7358 | static const Pipeline *pipeline_class(); |
| 7359 | virtual const Pipeline *pipeline() const; |
| 7360 | virtual const MachOper *memory_operand() const; |
| 7361 | #ifndef PRODUCT |
| 7362 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7363 | virtual const char *Name() const { return "loadUS";} |
| 7364 | #endif |
| 7365 | }; |
| 7366 | |
| 7367 | class loadUS2BNode : public MachNode { |
| 7368 | private: |
| 7369 | MachOper *_opnd_array[4]; |
| 7370 | public: |
| 7371 | MachOper *opnd_array(uint operand_index) const { |
| 7372 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7373 | return _opnd_array[operand_index]; |
| 7374 | } |
| 7375 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7377 | _opnd_array[operand_index] = operand; |
| 7378 | } |
| 7379 | private: |
| 7380 | virtual const RegMask &out_RegMask() const; |
| 7381 | virtual uint rule() const { return loadUS2B_rule; } |
| 7382 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7383 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 7384 | virtual int reloc() const; |
| 7385 | virtual uint oper_input_base() const { return 2; } |
| 7386 | public: |
| 7387 | loadUS2BNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7388 | virtual uint size_of() const { return sizeof(loadUS2BNode); } |
| 7389 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7390 | static const Pipeline *pipeline_class(); |
| 7391 | virtual const Pipeline *pipeline() const; |
| 7392 | virtual const MachOper *memory_operand() const; |
| 7393 | #ifndef PRODUCT |
| 7394 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7395 | virtual const char *Name() const { return "loadUS2B";} |
| 7396 | #endif |
| 7397 | }; |
| 7398 | |
| 7399 | class loadUS2LNode : public MachNode { |
| 7400 | private: |
| 7401 | MachOper *_opnd_array[2]; |
| 7402 | public: |
| 7403 | MachOper *opnd_array(uint operand_index) const { |
| 7404 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7405 | return _opnd_array[operand_index]; |
| 7406 | } |
| 7407 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7408 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7409 | _opnd_array[operand_index] = operand; |
| 7410 | } |
| 7411 | private: |
| 7412 | virtual const RegMask &out_RegMask() const; |
| 7413 | virtual uint rule() const { return loadUS2L_rule; } |
| 7414 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7415 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7416 | virtual int reloc() const; |
| 7417 | virtual uint oper_input_base() const { return 2; } |
| 7418 | public: |
| 7419 | loadUS2LNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7420 | virtual uint size_of() const { return sizeof(loadUS2LNode); } |
| 7421 | static const Pipeline *pipeline_class(); |
| 7422 | virtual const Pipeline *pipeline() const; |
| 7423 | virtual const MachOper *memory_operand() const; |
| 7424 | #ifndef PRODUCT |
| 7425 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7426 | virtual const char *Name() const { return "loadUS2L";} |
| 7427 | #endif |
| 7428 | }; |
| 7429 | |
| 7430 | class loadUS2L_immI_255Node : public MachNode { |
| 7431 | private: |
| 7432 | MachOper *_opnd_array[3]; |
| 7433 | public: |
| 7434 | MachOper *opnd_array(uint operand_index) const { |
| 7435 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7436 | return _opnd_array[operand_index]; |
| 7437 | } |
| 7438 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7439 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7440 | _opnd_array[operand_index] = operand; |
| 7441 | } |
| 7442 | private: |
| 7443 | virtual const RegMask &out_RegMask() const; |
| 7444 | virtual uint rule() const { return loadUS2L_immI_255_rule; } |
| 7445 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7446 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7447 | virtual int reloc() const; |
| 7448 | virtual uint oper_input_base() const { return 2; } |
| 7449 | public: |
| 7450 | loadUS2L_immI_255Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7451 | virtual uint size_of() const { return sizeof(loadUS2L_immI_255Node); } |
| 7452 | static const Pipeline *pipeline_class(); |
| 7453 | virtual const Pipeline *pipeline() const; |
| 7454 | virtual const MachOper *memory_operand() const; |
| 7455 | #ifndef PRODUCT |
| 7456 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7457 | virtual const char *Name() const { return "loadUS2L_immI_255";} |
| 7458 | #endif |
| 7459 | }; |
| 7460 | |
| 7461 | class loadUS2L_immINode : public MachNode { |
| 7462 | private: |
| 7463 | MachOper *_opnd_array[3]; |
| 7464 | public: |
| 7465 | MachOper *opnd_array(uint operand_index) const { |
| 7466 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7467 | return _opnd_array[operand_index]; |
| 7468 | } |
| 7469 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7470 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7471 | _opnd_array[operand_index] = operand; |
| 7472 | } |
| 7473 | private: |
| 7474 | virtual const RegMask &out_RegMask() const; |
| 7475 | virtual uint rule() const { return loadUS2L_immI_rule; } |
| 7476 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7477 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7478 | virtual int reloc() const; |
| 7479 | virtual uint oper_input_base() const { return 2; } |
| 7480 | public: |
| 7481 | loadUS2L_immINode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7482 | virtual uint size_of() const { return sizeof(loadUS2L_immINode); } |
| 7483 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7484 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 7485 | static const Pipeline *pipeline_class(); |
| 7486 | virtual const Pipeline *pipeline() const; |
| 7487 | virtual const MachOper *memory_operand() const; |
| 7488 | #ifndef PRODUCT |
| 7489 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7490 | virtual const char *Name() const { return "loadUS2L_immI";} |
| 7491 | #endif |
| 7492 | }; |
| 7493 | |
| 7494 | class loadINode : public MachNode { |
| 7495 | private: |
| 7496 | MachOper *_opnd_array[2]; |
| 7497 | public: |
| 7498 | MachOper *opnd_array(uint operand_index) const { |
| 7499 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7500 | return _opnd_array[operand_index]; |
| 7501 | } |
| 7502 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7503 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7504 | _opnd_array[operand_index] = operand; |
| 7505 | } |
| 7506 | private: |
| 7507 | virtual const RegMask &out_RegMask() const; |
| 7508 | virtual uint rule() const { return loadI_rule; } |
| 7509 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7510 | virtual int ideal_Opcode() const { return Op_LoadI; } |
| 7511 | virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted); |
| 7512 | virtual int reloc() const; |
| 7513 | virtual uint oper_input_base() const { return 2; } |
| 7514 | public: |
| 7515 | loadINode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7516 | virtual uint size_of() const { return sizeof(loadINode); } |
| 7517 | static const Pipeline *pipeline_class(); |
| 7518 | virtual const Pipeline *pipeline() const; |
| 7519 | virtual const MachOper *memory_operand() const; |
| 7520 | #ifndef PRODUCT |
| 7521 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7522 | virtual const char *Name() const { return "loadI";} |
| 7523 | #endif |
| 7524 | }; |
| 7525 | |
| 7526 | class loadI2BNode : public MachNode { |
| 7527 | private: |
| 7528 | MachOper *_opnd_array[4]; |
| 7529 | public: |
| 7530 | MachOper *opnd_array(uint operand_index) const { |
| 7531 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7532 | return _opnd_array[operand_index]; |
| 7533 | } |
| 7534 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7535 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7536 | _opnd_array[operand_index] = operand; |
| 7537 | } |
| 7538 | private: |
| 7539 | virtual const RegMask &out_RegMask() const; |
| 7540 | virtual uint rule() const { return loadI2B_rule; } |
| 7541 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7542 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 7543 | virtual int reloc() const; |
| 7544 | virtual uint oper_input_base() const { return 2; } |
| 7545 | public: |
| 7546 | loadI2BNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7547 | virtual uint size_of() const { return sizeof(loadI2BNode); } |
| 7548 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7549 | static const Pipeline *pipeline_class(); |
| 7550 | virtual const Pipeline *pipeline() const; |
| 7551 | virtual const MachOper *memory_operand() const; |
| 7552 | #ifndef PRODUCT |
| 7553 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7554 | virtual const char *Name() const { return "loadI2B";} |
| 7555 | #endif |
| 7556 | }; |
| 7557 | |
| 7558 | class loadI2UBNode : public MachNode { |
| 7559 | private: |
| 7560 | MachOper *_opnd_array[3]; |
| 7561 | public: |
| 7562 | MachOper *opnd_array(uint operand_index) const { |
| 7563 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7564 | return _opnd_array[operand_index]; |
| 7565 | } |
| 7566 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7567 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7568 | _opnd_array[operand_index] = operand; |
| 7569 | } |
| 7570 | private: |
| 7571 | virtual const RegMask &out_RegMask() const; |
| 7572 | virtual uint rule() const { return loadI2UB_rule; } |
| 7573 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7574 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 7575 | virtual int reloc() const; |
| 7576 | virtual uint oper_input_base() const { return 2; } |
| 7577 | public: |
| 7578 | loadI2UBNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7579 | virtual uint size_of() const { return sizeof(loadI2UBNode); } |
| 7580 | static const Pipeline *pipeline_class(); |
| 7581 | virtual const Pipeline *pipeline() const; |
| 7582 | virtual const MachOper *memory_operand() const; |
| 7583 | #ifndef PRODUCT |
| 7584 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7585 | virtual const char *Name() const { return "loadI2UB";} |
| 7586 | #endif |
| 7587 | }; |
| 7588 | |
| 7589 | class loadI2SNode : public MachNode { |
| 7590 | private: |
| 7591 | MachOper *_opnd_array[4]; |
| 7592 | public: |
| 7593 | MachOper *opnd_array(uint operand_index) const { |
| 7594 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7595 | return _opnd_array[operand_index]; |
| 7596 | } |
| 7597 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7598 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7599 | _opnd_array[operand_index] = operand; |
| 7600 | } |
| 7601 | private: |
| 7602 | virtual const RegMask &out_RegMask() const; |
| 7603 | virtual uint rule() const { return loadI2S_rule; } |
| 7604 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7605 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 7606 | virtual int reloc() const; |
| 7607 | virtual uint oper_input_base() const { return 2; } |
| 7608 | public: |
| 7609 | loadI2SNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7610 | virtual uint size_of() const { return sizeof(loadI2SNode); } |
| 7611 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7612 | static const Pipeline *pipeline_class(); |
| 7613 | virtual const Pipeline *pipeline() const; |
| 7614 | virtual const MachOper *memory_operand() const; |
| 7615 | #ifndef PRODUCT |
| 7616 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7617 | virtual const char *Name() const { return "loadI2S";} |
| 7618 | #endif |
| 7619 | }; |
| 7620 | |
| 7621 | class loadI2USNode : public MachNode { |
| 7622 | private: |
| 7623 | MachOper *_opnd_array[3]; |
| 7624 | public: |
| 7625 | MachOper *opnd_array(uint operand_index) const { |
| 7626 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7627 | return _opnd_array[operand_index]; |
| 7628 | } |
| 7629 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7630 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7631 | _opnd_array[operand_index] = operand; |
| 7632 | } |
| 7633 | private: |
| 7634 | virtual const RegMask &out_RegMask() const; |
| 7635 | virtual uint rule() const { return loadI2US_rule; } |
| 7636 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7637 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 7638 | virtual int reloc() const; |
| 7639 | virtual uint oper_input_base() const { return 2; } |
| 7640 | public: |
| 7641 | loadI2USNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7642 | virtual uint size_of() const { return sizeof(loadI2USNode); } |
| 7643 | static const Pipeline *pipeline_class(); |
| 7644 | virtual const Pipeline *pipeline() const; |
| 7645 | virtual const MachOper *memory_operand() const; |
| 7646 | #ifndef PRODUCT |
| 7647 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7648 | virtual const char *Name() const { return "loadI2US";} |
| 7649 | #endif |
| 7650 | }; |
| 7651 | |
| 7652 | class loadI2LNode : public MachNode { |
| 7653 | private: |
| 7654 | MachOper *_opnd_array[2]; |
| 7655 | public: |
| 7656 | MachOper *opnd_array(uint operand_index) const { |
| 7657 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7658 | return _opnd_array[operand_index]; |
| 7659 | } |
| 7660 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7661 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7662 | _opnd_array[operand_index] = operand; |
| 7663 | } |
| 7664 | private: |
| 7665 | virtual const RegMask &out_RegMask() const; |
| 7666 | virtual uint rule() const { return loadI2L_rule; } |
| 7667 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7668 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7669 | virtual int reloc() const; |
| 7670 | virtual uint oper_input_base() const { return 2; } |
| 7671 | public: |
| 7672 | loadI2LNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7673 | virtual uint size_of() const { return sizeof(loadI2LNode); } |
| 7674 | static const Pipeline *pipeline_class(); |
| 7675 | virtual const Pipeline *pipeline() const; |
| 7676 | virtual const MachOper *memory_operand() const; |
| 7677 | #ifndef PRODUCT |
| 7678 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7679 | virtual const char *Name() const { return "loadI2L";} |
| 7680 | #endif |
| 7681 | }; |
| 7682 | |
| 7683 | class loadI2L_immI_255Node : public MachNode { |
| 7684 | private: |
| 7685 | MachOper *_opnd_array[3]; |
| 7686 | public: |
| 7687 | MachOper *opnd_array(uint operand_index) const { |
| 7688 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7689 | return _opnd_array[operand_index]; |
| 7690 | } |
| 7691 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7692 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7693 | _opnd_array[operand_index] = operand; |
| 7694 | } |
| 7695 | private: |
| 7696 | virtual const RegMask &out_RegMask() const; |
| 7697 | virtual uint rule() const { return loadI2L_immI_255_rule; } |
| 7698 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7699 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7700 | virtual int reloc() const; |
| 7701 | virtual uint oper_input_base() const { return 2; } |
| 7702 | public: |
| 7703 | loadI2L_immI_255Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7704 | virtual uint size_of() const { return sizeof(loadI2L_immI_255Node); } |
| 7705 | static const Pipeline *pipeline_class(); |
| 7706 | virtual const Pipeline *pipeline() const; |
| 7707 | virtual const MachOper *memory_operand() const; |
| 7708 | #ifndef PRODUCT |
| 7709 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7710 | virtual const char *Name() const { return "loadI2L_immI_255";} |
| 7711 | #endif |
| 7712 | }; |
| 7713 | |
| 7714 | class loadI2L_immI_65535Node : public MachNode { |
| 7715 | private: |
| 7716 | MachOper *_opnd_array[3]; |
| 7717 | public: |
| 7718 | MachOper *opnd_array(uint operand_index) const { |
| 7719 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7720 | return _opnd_array[operand_index]; |
| 7721 | } |
| 7722 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7723 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7724 | _opnd_array[operand_index] = operand; |
| 7725 | } |
| 7726 | private: |
| 7727 | virtual const RegMask &out_RegMask() const; |
| 7728 | virtual uint rule() const { return loadI2L_immI_65535_rule; } |
| 7729 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7730 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7731 | virtual int reloc() const; |
| 7732 | virtual uint oper_input_base() const { return 2; } |
| 7733 | public: |
| 7734 | loadI2L_immI_65535Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7735 | virtual uint size_of() const { return sizeof(loadI2L_immI_65535Node); } |
| 7736 | static const Pipeline *pipeline_class(); |
| 7737 | virtual const Pipeline *pipeline() const; |
| 7738 | virtual const MachOper *memory_operand() const; |
| 7739 | #ifndef PRODUCT |
| 7740 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7741 | virtual const char *Name() const { return "loadI2L_immI_65535";} |
| 7742 | #endif |
| 7743 | }; |
| 7744 | |
| 7745 | class loadI2L_immU31Node : public MachNode { |
| 7746 | private: |
| 7747 | MachOper *_opnd_array[3]; |
| 7748 | public: |
| 7749 | MachOper *opnd_array(uint operand_index) const { |
| 7750 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7751 | return _opnd_array[operand_index]; |
| 7752 | } |
| 7753 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7754 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7755 | _opnd_array[operand_index] = operand; |
| 7756 | } |
| 7757 | private: |
| 7758 | virtual const RegMask &out_RegMask() const; |
| 7759 | virtual uint rule() const { return loadI2L_immU31_rule; } |
| 7760 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7761 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 7762 | virtual int reloc() const; |
| 7763 | virtual uint oper_input_base() const { return 2; } |
| 7764 | public: |
| 7765 | loadI2L_immU31Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7766 | virtual uint size_of() const { return sizeof(loadI2L_immU31Node); } |
| 7767 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 7768 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 7769 | static const Pipeline *pipeline_class(); |
| 7770 | virtual const Pipeline *pipeline() const; |
| 7771 | virtual const MachOper *memory_operand() const; |
| 7772 | #ifndef PRODUCT |
| 7773 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7774 | virtual const char *Name() const { return "loadI2L_immU31";} |
| 7775 | #endif |
| 7776 | }; |
| 7777 | |
| 7778 | class loadUI2LNode : public MachNode { |
| 7779 | private: |
| 7780 | MachOper *_opnd_array[3]; |
| 7781 | public: |
| 7782 | MachOper *opnd_array(uint operand_index) const { |
| 7783 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7784 | return _opnd_array[operand_index]; |
| 7785 | } |
| 7786 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7787 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7788 | _opnd_array[operand_index] = operand; |
| 7789 | } |
| 7790 | private: |
| 7791 | virtual const RegMask &out_RegMask() const; |
| 7792 | virtual uint rule() const { return loadUI2L_rule; } |
| 7793 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7794 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 7795 | virtual int reloc() const; |
| 7796 | virtual uint oper_input_base() const { return 2; } |
| 7797 | public: |
| 7798 | loadUI2LNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 7799 | virtual uint size_of() const { return sizeof(loadUI2LNode); } |
| 7800 | static const Pipeline *pipeline_class(); |
| 7801 | virtual const Pipeline *pipeline() const; |
| 7802 | virtual const MachOper *memory_operand() const; |
| 7803 | #ifndef PRODUCT |
| 7804 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7805 | virtual const char *Name() const { return "loadUI2L";} |
| 7806 | #endif |
| 7807 | }; |
| 7808 | |
| 7809 | class loadLNode : public MachNode { |
| 7810 | private: |
| 7811 | MachOper *_opnd_array[2]; |
| 7812 | public: |
| 7813 | MachOper *opnd_array(uint operand_index) const { |
| 7814 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7815 | return _opnd_array[operand_index]; |
| 7816 | } |
| 7817 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7818 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7819 | _opnd_array[operand_index] = operand; |
| 7820 | } |
| 7821 | private: |
| 7822 | virtual const RegMask &out_RegMask() const; |
| 7823 | virtual uint rule() const { return loadL_rule; } |
| 7824 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7825 | virtual int ideal_Opcode() const { return Op_LoadL; } |
| 7826 | virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted); |
| 7827 | virtual int reloc() const; |
| 7828 | virtual uint oper_input_base() const { return 2; } |
| 7829 | public: |
| 7830 | loadLNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7831 | virtual uint size_of() const { return sizeof(loadLNode); } |
| 7832 | static const Pipeline *pipeline_class(); |
| 7833 | virtual const Pipeline *pipeline() const; |
| 7834 | virtual const MachOper *memory_operand() const; |
| 7835 | #ifndef PRODUCT |
| 7836 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7837 | virtual const char *Name() const { return "loadL";} |
| 7838 | #endif |
| 7839 | }; |
| 7840 | |
| 7841 | class loadRangeNode : public MachNode { |
| 7842 | private: |
| 7843 | MachOper *_opnd_array[2]; |
| 7844 | public: |
| 7845 | MachOper *opnd_array(uint operand_index) const { |
| 7846 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7847 | return _opnd_array[operand_index]; |
| 7848 | } |
| 7849 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7850 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7851 | _opnd_array[operand_index] = operand; |
| 7852 | } |
| 7853 | private: |
| 7854 | virtual const RegMask &out_RegMask() const; |
| 7855 | virtual uint rule() const { return loadRange_rule; } |
| 7856 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7857 | virtual int ideal_Opcode() const { return Op_LoadRange; } |
| 7858 | virtual int reloc() const; |
| 7859 | virtual uint oper_input_base() const { return 2; } |
| 7860 | public: |
| 7861 | loadRangeNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 7862 | virtual uint size_of() const { return sizeof(loadRangeNode); } |
| 7863 | static const Pipeline *pipeline_class(); |
| 7864 | virtual const Pipeline *pipeline() const; |
| 7865 | virtual const MachOper *memory_operand() const; |
| 7866 | #ifndef PRODUCT |
| 7867 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7868 | virtual const char *Name() const { return "loadRange";} |
| 7869 | #endif |
| 7870 | }; |
| 7871 | |
| 7872 | class loadPNode : public MachTypeNode { |
| 7873 | private: |
| 7874 | MachOper *_opnd_array[2]; |
| 7875 | public: |
| 7876 | MachOper *opnd_array(uint operand_index) const { |
| 7877 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7878 | return _opnd_array[operand_index]; |
| 7879 | } |
| 7880 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7881 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7882 | _opnd_array[operand_index] = operand; |
| 7883 | } |
| 7884 | private: |
| 7885 | virtual const RegMask &out_RegMask() const; |
| 7886 | virtual uint rule() const { return loadP_rule; } |
| 7887 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7888 | virtual int ideal_Opcode() const { return Op_LoadP; } |
| 7889 | virtual int reloc() const; |
| 7890 | virtual uint oper_input_base() const { return 2; } |
| 7891 | public: |
| 7892 | loadPNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7893 | virtual uint size_of() const { return sizeof(loadPNode); } |
| 7894 | static const Pipeline *pipeline_class(); |
| 7895 | virtual const Pipeline *pipeline() const; |
| 7896 | virtual const MachOper *memory_operand() const; |
| 7897 | #ifndef PRODUCT |
| 7898 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7899 | virtual const char *Name() const { return "loadP";} |
| 7900 | #endif |
| 7901 | }; |
| 7902 | |
| 7903 | class loadNNode : public MachTypeNode { |
| 7904 | private: |
| 7905 | MachOper *_opnd_array[2]; |
| 7906 | public: |
| 7907 | MachOper *opnd_array(uint operand_index) const { |
| 7908 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7909 | return _opnd_array[operand_index]; |
| 7910 | } |
| 7911 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7912 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7913 | _opnd_array[operand_index] = operand; |
| 7914 | } |
| 7915 | private: |
| 7916 | virtual const RegMask &out_RegMask() const; |
| 7917 | virtual uint rule() const { return loadN_rule; } |
| 7918 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7919 | virtual int ideal_Opcode() const { return Op_LoadN; } |
| 7920 | virtual int reloc() const; |
| 7921 | virtual uint oper_input_base() const { return 2; } |
| 7922 | public: |
| 7923 | loadNNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 7924 | virtual uint size_of() const { return sizeof(loadNNode); } |
| 7925 | static const Pipeline *pipeline_class(); |
| 7926 | virtual const Pipeline *pipeline() const; |
| 7927 | virtual const MachOper *memory_operand() const; |
| 7928 | #ifndef PRODUCT |
| 7929 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7930 | virtual const char *Name() const { return "loadN";} |
| 7931 | #endif |
| 7932 | }; |
| 7933 | |
| 7934 | class loadKlassNode : public MachTypeNode { |
| 7935 | private: |
| 7936 | MachOper *_opnd_array[2]; |
| 7937 | public: |
| 7938 | MachOper *opnd_array(uint operand_index) const { |
| 7939 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7940 | return _opnd_array[operand_index]; |
| 7941 | } |
| 7942 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7943 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7944 | _opnd_array[operand_index] = operand; |
| 7945 | } |
| 7946 | private: |
| 7947 | virtual const RegMask &out_RegMask() const; |
| 7948 | virtual uint rule() const { return loadKlass_rule; } |
| 7949 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7950 | virtual int ideal_Opcode() const { return Op_LoadKlass; } |
| 7951 | virtual int reloc() const; |
| 7952 | virtual uint oper_input_base() const { return 2; } |
| 7953 | public: |
| 7954 | loadKlassNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 7955 | virtual uint size_of() const { return sizeof(loadKlassNode); } |
| 7956 | static const Pipeline *pipeline_class(); |
| 7957 | virtual const Pipeline *pipeline() const; |
| 7958 | virtual const MachOper *memory_operand() const; |
| 7959 | #ifndef PRODUCT |
| 7960 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7961 | virtual const char *Name() const { return "loadKlass";} |
| 7962 | #endif |
| 7963 | }; |
| 7964 | |
| 7965 | class loadNKlassNode : public MachTypeNode { |
| 7966 | private: |
| 7967 | MachOper *_opnd_array[2]; |
| 7968 | public: |
| 7969 | MachOper *opnd_array(uint operand_index) const { |
| 7970 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7971 | return _opnd_array[operand_index]; |
| 7972 | } |
| 7973 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 7974 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 7975 | _opnd_array[operand_index] = operand; |
| 7976 | } |
| 7977 | private: |
| 7978 | virtual const RegMask &out_RegMask() const; |
| 7979 | virtual uint rule() const { return loadNKlass_rule; } |
| 7980 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 7981 | virtual int ideal_Opcode() const { return Op_LoadNKlass; } |
| 7982 | virtual int reloc() const; |
| 7983 | virtual uint oper_input_base() const { return 2; } |
| 7984 | public: |
| 7985 | loadNKlassNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 7986 | virtual uint size_of() const { return sizeof(loadNKlassNode); } |
| 7987 | static const Pipeline *pipeline_class(); |
| 7988 | virtual const Pipeline *pipeline() const; |
| 7989 | virtual const MachOper *memory_operand() const; |
| 7990 | #ifndef PRODUCT |
| 7991 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 7992 | virtual const char *Name() const { return "loadNKlass";} |
| 7993 | #endif |
| 7994 | }; |
| 7995 | |
| 7996 | class loadFNode : public MachNode { |
| 7997 | private: |
| 7998 | MachOper *_opnd_array[2]; |
| 7999 | public: |
| 8000 | MachOper *opnd_array(uint operand_index) const { |
| 8001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8002 | return _opnd_array[operand_index]; |
| 8003 | } |
| 8004 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8006 | _opnd_array[operand_index] = operand; |
| 8007 | } |
| 8008 | private: |
| 8009 | virtual const RegMask &out_RegMask() const; |
| 8010 | virtual uint rule() const { return loadF_rule; } |
| 8011 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8012 | virtual int ideal_Opcode() const { return Op_LoadF; } |
| 8013 | virtual int reloc() const; |
| 8014 | virtual uint oper_input_base() const { return 2; } |
| 8015 | public: |
| 8016 | loadFNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 8017 | virtual uint size_of() const { return sizeof(loadFNode); } |
| 8018 | static const Pipeline *pipeline_class(); |
| 8019 | virtual const Pipeline *pipeline() const; |
| 8020 | virtual const MachOper *memory_operand() const; |
| 8021 | #ifndef PRODUCT |
| 8022 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8023 | virtual const char *Name() const { return "loadF";} |
| 8024 | #endif |
| 8025 | }; |
| 8026 | |
| 8027 | class MoveF2VLNode : public MachNode { |
| 8028 | private: |
| 8029 | MachOper *_opnd_array[2]; |
| 8030 | public: |
| 8031 | MachOper *opnd_array(uint operand_index) const { |
| 8032 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8033 | return _opnd_array[operand_index]; |
| 8034 | } |
| 8035 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8037 | _opnd_array[operand_index] = operand; |
| 8038 | } |
| 8039 | private: |
| 8040 | virtual const RegMask &out_RegMask() const; |
| 8041 | virtual uint rule() const { return MoveF2VL_rule; } |
| 8042 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8043 | virtual int ideal_Opcode() const { return Op_RegF; } |
| 8044 | public: |
| 8045 | MoveF2VLNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 8046 | virtual uint size_of() const { return sizeof(MoveF2VLNode); } |
| 8047 | // Rematerialize MoveF2VL |
| 8048 | static const Pipeline *pipeline_class(); |
| 8049 | virtual const Pipeline *pipeline() const; |
| 8050 | #ifndef PRODUCT |
| 8051 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8052 | virtual const char *Name() const { return "MoveF2VL";} |
| 8053 | #endif |
| 8054 | }; |
| 8055 | |
| 8056 | class MoveF2LEGNode : public MachNode { |
| 8057 | private: |
| 8058 | MachOper *_opnd_array[2]; |
| 8059 | public: |
| 8060 | MachOper *opnd_array(uint operand_index) const { |
| 8061 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8062 | return _opnd_array[operand_index]; |
| 8063 | } |
| 8064 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8065 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8066 | _opnd_array[operand_index] = operand; |
| 8067 | } |
| 8068 | private: |
| 8069 | virtual const RegMask &out_RegMask() const; |
| 8070 | virtual uint rule() const { return MoveF2LEG_rule; } |
| 8071 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8072 | virtual int ideal_Opcode() const { return Op_RegF; } |
| 8073 | public: |
| 8074 | MoveF2LEGNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 8075 | virtual uint size_of() const { return sizeof(MoveF2LEGNode); } |
| 8076 | // Rematerialize MoveF2LEG |
| 8077 | static const Pipeline *pipeline_class(); |
| 8078 | virtual const Pipeline *pipeline() const; |
| 8079 | #ifndef PRODUCT |
| 8080 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8081 | virtual const char *Name() const { return "MoveF2LEG";} |
| 8082 | #endif |
| 8083 | }; |
| 8084 | |
| 8085 | class MoveVL2FNode : public MachNode { |
| 8086 | private: |
| 8087 | MachOper *_opnd_array[2]; |
| 8088 | public: |
| 8089 | MachOper *opnd_array(uint operand_index) const { |
| 8090 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8091 | return _opnd_array[operand_index]; |
| 8092 | } |
| 8093 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8094 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8095 | _opnd_array[operand_index] = operand; |
| 8096 | } |
| 8097 | private: |
| 8098 | const RegMask *_cisc_RegMask; |
| 8099 | virtual const RegMask &out_RegMask() const; |
| 8100 | virtual uint rule() const { return MoveVL2F_rule; } |
| 8101 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8102 | virtual int ideal_Opcode() const { return Op_RegF; } |
| 8103 | virtual int cisc_operand() const { return 1; } |
| 8104 | virtual MachNode *cisc_version(int offset); |
| 8105 | virtual void use_cisc_RegMask(); |
| 8106 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 8107 | public: |
| 8108 | MoveVL2FNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 8109 | virtual uint size_of() const { return sizeof(MoveVL2FNode); } |
| 8110 | // Rematerialize MoveVL2F |
| 8111 | static const Pipeline *pipeline_class(); |
| 8112 | virtual const Pipeline *pipeline() const; |
| 8113 | #ifndef PRODUCT |
| 8114 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8115 | virtual const char *Name() const { return "MoveVL2F";} |
| 8116 | #endif |
| 8117 | }; |
| 8118 | |
| 8119 | class MoveLEG2FNode : public MachNode { |
| 8120 | private: |
| 8121 | MachOper *_opnd_array[2]; |
| 8122 | public: |
| 8123 | MachOper *opnd_array(uint operand_index) const { |
| 8124 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8125 | return _opnd_array[operand_index]; |
| 8126 | } |
| 8127 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8128 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8129 | _opnd_array[operand_index] = operand; |
| 8130 | } |
| 8131 | private: |
| 8132 | const RegMask *_cisc_RegMask; |
| 8133 | virtual const RegMask &out_RegMask() const; |
| 8134 | virtual uint rule() const { return MoveLEG2F_rule; } |
| 8135 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8136 | virtual int ideal_Opcode() const { return Op_RegF; } |
| 8137 | virtual int cisc_operand() const { return 1; } |
| 8138 | virtual MachNode *cisc_version(int offset); |
| 8139 | virtual void use_cisc_RegMask(); |
| 8140 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 8141 | public: |
| 8142 | MoveLEG2FNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 8143 | virtual uint size_of() const { return sizeof(MoveLEG2FNode); } |
| 8144 | // Rematerialize MoveLEG2F |
| 8145 | static const Pipeline *pipeline_class(); |
| 8146 | virtual const Pipeline *pipeline() const; |
| 8147 | #ifndef PRODUCT |
| 8148 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8149 | virtual const char *Name() const { return "MoveLEG2F";} |
| 8150 | #endif |
| 8151 | }; |
| 8152 | |
| 8153 | class loadD_partialNode : public MachNode { |
| 8154 | private: |
| 8155 | MachOper *_opnd_array[2]; |
| 8156 | public: |
| 8157 | MachOper *opnd_array(uint operand_index) const { |
| 8158 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8159 | return _opnd_array[operand_index]; |
| 8160 | } |
| 8161 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8162 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8163 | _opnd_array[operand_index] = operand; |
| 8164 | } |
| 8165 | private: |
| 8166 | virtual const RegMask &out_RegMask() const; |
| 8167 | virtual uint rule() const { return loadD_partial_rule; } |
| 8168 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8169 | virtual int ideal_Opcode() const { return Op_LoadD; } |
| 8170 | virtual int reloc() const; |
| 8171 | virtual uint oper_input_base() const { return 2; } |
| 8172 | public: |
| 8173 | loadD_partialNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8174 | virtual uint size_of() const { return sizeof(loadD_partialNode); } |
| 8175 | static const Pipeline *pipeline_class(); |
| 8176 | virtual const Pipeline *pipeline() const; |
| 8177 | virtual const MachOper *memory_operand() const; |
| 8178 | #ifndef PRODUCT |
| 8179 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8180 | virtual const char *Name() const { return "loadD_partial";} |
| 8181 | #endif |
| 8182 | }; |
| 8183 | |
| 8184 | class loadDNode : public MachNode { |
| 8185 | private: |
| 8186 | MachOper *_opnd_array[2]; |
| 8187 | public: |
| 8188 | MachOper *opnd_array(uint operand_index) const { |
| 8189 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8190 | return _opnd_array[operand_index]; |
| 8191 | } |
| 8192 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8193 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8194 | _opnd_array[operand_index] = operand; |
| 8195 | } |
| 8196 | private: |
| 8197 | virtual const RegMask &out_RegMask() const; |
| 8198 | virtual uint rule() const { return loadD_rule; } |
| 8199 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8200 | virtual int ideal_Opcode() const { return Op_LoadD; } |
| 8201 | virtual int reloc() const; |
| 8202 | virtual uint oper_input_base() const { return 2; } |
| 8203 | public: |
| 8204 | loadDNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8205 | virtual uint size_of() const { return sizeof(loadDNode); } |
| 8206 | static const Pipeline *pipeline_class(); |
| 8207 | virtual const Pipeline *pipeline() const; |
| 8208 | virtual const MachOper *memory_operand() const; |
| 8209 | #ifndef PRODUCT |
| 8210 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8211 | virtual const char *Name() const { return "loadD";} |
| 8212 | #endif |
| 8213 | }; |
| 8214 | |
| 8215 | class MoveD2VLNode : public MachNode { |
| 8216 | private: |
| 8217 | MachOper *_opnd_array[2]; |
| 8218 | public: |
| 8219 | MachOper *opnd_array(uint operand_index) const { |
| 8220 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8221 | return _opnd_array[operand_index]; |
| 8222 | } |
| 8223 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8224 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8225 | _opnd_array[operand_index] = operand; |
| 8226 | } |
| 8227 | private: |
| 8228 | virtual const RegMask &out_RegMask() const; |
| 8229 | virtual uint rule() const { return MoveD2VL_rule; } |
| 8230 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8231 | virtual int ideal_Opcode() const { return Op_RegD; } |
| 8232 | public: |
| 8233 | MoveD2VLNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 8234 | virtual uint size_of() const { return sizeof(MoveD2VLNode); } |
| 8235 | // Rematerialize MoveD2VL |
| 8236 | static const Pipeline *pipeline_class(); |
| 8237 | virtual const Pipeline *pipeline() const; |
| 8238 | #ifndef PRODUCT |
| 8239 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8240 | virtual const char *Name() const { return "MoveD2VL";} |
| 8241 | #endif |
| 8242 | }; |
| 8243 | |
| 8244 | class MoveD2LEGNode : public MachNode { |
| 8245 | private: |
| 8246 | MachOper *_opnd_array[2]; |
| 8247 | public: |
| 8248 | MachOper *opnd_array(uint operand_index) const { |
| 8249 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8250 | return _opnd_array[operand_index]; |
| 8251 | } |
| 8252 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8253 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8254 | _opnd_array[operand_index] = operand; |
| 8255 | } |
| 8256 | private: |
| 8257 | virtual const RegMask &out_RegMask() const; |
| 8258 | virtual uint rule() const { return MoveD2LEG_rule; } |
| 8259 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8260 | virtual int ideal_Opcode() const { return Op_RegD; } |
| 8261 | public: |
| 8262 | MoveD2LEGNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 8263 | virtual uint size_of() const { return sizeof(MoveD2LEGNode); } |
| 8264 | // Rematerialize MoveD2LEG |
| 8265 | static const Pipeline *pipeline_class(); |
| 8266 | virtual const Pipeline *pipeline() const; |
| 8267 | #ifndef PRODUCT |
| 8268 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8269 | virtual const char *Name() const { return "MoveD2LEG";} |
| 8270 | #endif |
| 8271 | }; |
| 8272 | |
| 8273 | class MoveVL2DNode : public MachNode { |
| 8274 | private: |
| 8275 | MachOper *_opnd_array[2]; |
| 8276 | public: |
| 8277 | MachOper *opnd_array(uint operand_index) const { |
| 8278 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8279 | return _opnd_array[operand_index]; |
| 8280 | } |
| 8281 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8282 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8283 | _opnd_array[operand_index] = operand; |
| 8284 | } |
| 8285 | private: |
| 8286 | const RegMask *_cisc_RegMask; |
| 8287 | virtual const RegMask &out_RegMask() const; |
| 8288 | virtual uint rule() const { return MoveVL2D_rule; } |
| 8289 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8290 | virtual int ideal_Opcode() const { return Op_RegD; } |
| 8291 | virtual int cisc_operand() const { return 1; } |
| 8292 | virtual MachNode *cisc_version(int offset); |
| 8293 | virtual void use_cisc_RegMask(); |
| 8294 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 8295 | public: |
| 8296 | MoveVL2DNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 8297 | virtual uint size_of() const { return sizeof(MoveVL2DNode); } |
| 8298 | // Rematerialize MoveVL2D |
| 8299 | static const Pipeline *pipeline_class(); |
| 8300 | virtual const Pipeline *pipeline() const; |
| 8301 | #ifndef PRODUCT |
| 8302 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8303 | virtual const char *Name() const { return "MoveVL2D";} |
| 8304 | #endif |
| 8305 | }; |
| 8306 | |
| 8307 | class MoveLEG2DNode : public MachNode { |
| 8308 | private: |
| 8309 | MachOper *_opnd_array[2]; |
| 8310 | public: |
| 8311 | MachOper *opnd_array(uint operand_index) const { |
| 8312 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8313 | return _opnd_array[operand_index]; |
| 8314 | } |
| 8315 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8316 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8317 | _opnd_array[operand_index] = operand; |
| 8318 | } |
| 8319 | private: |
| 8320 | const RegMask *_cisc_RegMask; |
| 8321 | virtual const RegMask &out_RegMask() const; |
| 8322 | virtual uint rule() const { return MoveLEG2D_rule; } |
| 8323 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8324 | virtual int ideal_Opcode() const { return Op_RegD; } |
| 8325 | virtual int cisc_operand() const { return 1; } |
| 8326 | virtual MachNode *cisc_version(int offset); |
| 8327 | virtual void use_cisc_RegMask(); |
| 8328 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 8329 | public: |
| 8330 | MoveLEG2DNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 8331 | virtual uint size_of() const { return sizeof(MoveLEG2DNode); } |
| 8332 | // Rematerialize MoveLEG2D |
| 8333 | static const Pipeline *pipeline_class(); |
| 8334 | virtual const Pipeline *pipeline() const; |
| 8335 | #ifndef PRODUCT |
| 8336 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8337 | virtual const char *Name() const { return "MoveLEG2D";} |
| 8338 | #endif |
| 8339 | }; |
| 8340 | |
| 8341 | class maxF_regNode : public MachNode { |
| 8342 | private: |
| 8343 | MachOper *_opnd_array[6]; |
| 8344 | public: |
| 8345 | MachOper *opnd_array(uint operand_index) const { |
| 8346 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8347 | return _opnd_array[operand_index]; |
| 8348 | } |
| 8349 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8350 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8351 | _opnd_array[operand_index] = operand; |
| 8352 | } |
| 8353 | private: |
| 8354 | virtual const RegMask &out_RegMask() const; |
| 8355 | virtual uint rule() const { return maxF_reg_rule; } |
| 8356 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8357 | virtual int ideal_Opcode() const { return Op_MaxF; } |
| 8358 | public: |
| 8359 | maxF_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 8360 | virtual uint size_of() const { return sizeof(maxF_regNode); } |
| 8361 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8362 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8363 | static const Pipeline *pipeline_class(); |
| 8364 | virtual const Pipeline *pipeline() const; |
| 8365 | #ifndef PRODUCT |
| 8366 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8367 | virtual const char *Name() const { return "maxF_reg";} |
| 8368 | #endif |
| 8369 | }; |
| 8370 | |
| 8371 | class maxF_reduction_regNode : public MachNode { |
| 8372 | private: |
| 8373 | MachOper *_opnd_array[5]; |
| 8374 | public: |
| 8375 | MachOper *opnd_array(uint operand_index) const { |
| 8376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8377 | return _opnd_array[operand_index]; |
| 8378 | } |
| 8379 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8380 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8381 | _opnd_array[operand_index] = operand; |
| 8382 | } |
| 8383 | private: |
| 8384 | virtual const RegMask &out_RegMask() const; |
| 8385 | virtual uint rule() const { return maxF_reduction_reg_rule; } |
| 8386 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8387 | virtual int ideal_Opcode() const { return Op_MaxF; } |
| 8388 | public: |
| 8389 | maxF_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 8390 | virtual uint size_of() const { return sizeof(maxF_reduction_regNode); } |
| 8391 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8392 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8393 | static const Pipeline *pipeline_class(); |
| 8394 | virtual const Pipeline *pipeline() const; |
| 8395 | #ifndef PRODUCT |
| 8396 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8397 | virtual const char *Name() const { return "maxF_reduction_reg";} |
| 8398 | #endif |
| 8399 | }; |
| 8400 | |
| 8401 | class maxD_regNode : public MachNode { |
| 8402 | private: |
| 8403 | MachOper *_opnd_array[6]; |
| 8404 | public: |
| 8405 | MachOper *opnd_array(uint operand_index) const { |
| 8406 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8407 | return _opnd_array[operand_index]; |
| 8408 | } |
| 8409 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8410 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8411 | _opnd_array[operand_index] = operand; |
| 8412 | } |
| 8413 | private: |
| 8414 | virtual const RegMask &out_RegMask() const; |
| 8415 | virtual uint rule() const { return maxD_reg_rule; } |
| 8416 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8417 | virtual int ideal_Opcode() const { return Op_MaxD; } |
| 8418 | public: |
| 8419 | maxD_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 8420 | virtual uint size_of() const { return sizeof(maxD_regNode); } |
| 8421 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8422 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8423 | static const Pipeline *pipeline_class(); |
| 8424 | virtual const Pipeline *pipeline() const; |
| 8425 | #ifndef PRODUCT |
| 8426 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8427 | virtual const char *Name() const { return "maxD_reg";} |
| 8428 | #endif |
| 8429 | }; |
| 8430 | |
| 8431 | class maxD_reduction_regNode : public MachNode { |
| 8432 | private: |
| 8433 | MachOper *_opnd_array[5]; |
| 8434 | public: |
| 8435 | MachOper *opnd_array(uint operand_index) const { |
| 8436 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8437 | return _opnd_array[operand_index]; |
| 8438 | } |
| 8439 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8441 | _opnd_array[operand_index] = operand; |
| 8442 | } |
| 8443 | private: |
| 8444 | virtual const RegMask &out_RegMask() const; |
| 8445 | virtual uint rule() const { return maxD_reduction_reg_rule; } |
| 8446 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8447 | virtual int ideal_Opcode() const { return Op_MaxD; } |
| 8448 | public: |
| 8449 | maxD_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 8450 | virtual uint size_of() const { return sizeof(maxD_reduction_regNode); } |
| 8451 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8452 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8453 | static const Pipeline *pipeline_class(); |
| 8454 | virtual const Pipeline *pipeline() const; |
| 8455 | #ifndef PRODUCT |
| 8456 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8457 | virtual const char *Name() const { return "maxD_reduction_reg";} |
| 8458 | #endif |
| 8459 | }; |
| 8460 | |
| 8461 | class minF_regNode : public MachNode { |
| 8462 | private: |
| 8463 | MachOper *_opnd_array[6]; |
| 8464 | public: |
| 8465 | MachOper *opnd_array(uint operand_index) const { |
| 8466 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8467 | return _opnd_array[operand_index]; |
| 8468 | } |
| 8469 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8470 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8471 | _opnd_array[operand_index] = operand; |
| 8472 | } |
| 8473 | private: |
| 8474 | virtual const RegMask &out_RegMask() const; |
| 8475 | virtual uint rule() const { return minF_reg_rule; } |
| 8476 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8477 | virtual int ideal_Opcode() const { return Op_MinF; } |
| 8478 | public: |
| 8479 | minF_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 8480 | virtual uint size_of() const { return sizeof(minF_regNode); } |
| 8481 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8482 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8483 | static const Pipeline *pipeline_class(); |
| 8484 | virtual const Pipeline *pipeline() const; |
| 8485 | #ifndef PRODUCT |
| 8486 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8487 | virtual const char *Name() const { return "minF_reg";} |
| 8488 | #endif |
| 8489 | }; |
| 8490 | |
| 8491 | class minF_reduction_regNode : public MachNode { |
| 8492 | private: |
| 8493 | MachOper *_opnd_array[5]; |
| 8494 | public: |
| 8495 | MachOper *opnd_array(uint operand_index) const { |
| 8496 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8497 | return _opnd_array[operand_index]; |
| 8498 | } |
| 8499 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8500 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8501 | _opnd_array[operand_index] = operand; |
| 8502 | } |
| 8503 | private: |
| 8504 | virtual const RegMask &out_RegMask() const; |
| 8505 | virtual uint rule() const { return minF_reduction_reg_rule; } |
| 8506 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8507 | virtual int ideal_Opcode() const { return Op_MinF; } |
| 8508 | public: |
| 8509 | minF_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 8510 | virtual uint size_of() const { return sizeof(minF_reduction_regNode); } |
| 8511 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8512 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8513 | static const Pipeline *pipeline_class(); |
| 8514 | virtual const Pipeline *pipeline() const; |
| 8515 | #ifndef PRODUCT |
| 8516 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8517 | virtual const char *Name() const { return "minF_reduction_reg";} |
| 8518 | #endif |
| 8519 | }; |
| 8520 | |
| 8521 | class minD_regNode : public MachNode { |
| 8522 | private: |
| 8523 | MachOper *_opnd_array[6]; |
| 8524 | public: |
| 8525 | MachOper *opnd_array(uint operand_index) const { |
| 8526 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8527 | return _opnd_array[operand_index]; |
| 8528 | } |
| 8529 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8530 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8531 | _opnd_array[operand_index] = operand; |
| 8532 | } |
| 8533 | private: |
| 8534 | virtual const RegMask &out_RegMask() const; |
| 8535 | virtual uint rule() const { return minD_reg_rule; } |
| 8536 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8537 | virtual int ideal_Opcode() const { return Op_MinD; } |
| 8538 | public: |
| 8539 | minD_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 8540 | virtual uint size_of() const { return sizeof(minD_regNode); } |
| 8541 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8542 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8543 | static const Pipeline *pipeline_class(); |
| 8544 | virtual const Pipeline *pipeline() const; |
| 8545 | #ifndef PRODUCT |
| 8546 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8547 | virtual const char *Name() const { return "minD_reg";} |
| 8548 | #endif |
| 8549 | }; |
| 8550 | |
| 8551 | class minD_reduction_regNode : public MachNode { |
| 8552 | private: |
| 8553 | MachOper *_opnd_array[5]; |
| 8554 | public: |
| 8555 | MachOper *opnd_array(uint operand_index) const { |
| 8556 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8557 | return _opnd_array[operand_index]; |
| 8558 | } |
| 8559 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8560 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8561 | _opnd_array[operand_index] = operand; |
| 8562 | } |
| 8563 | private: |
| 8564 | virtual const RegMask &out_RegMask() const; |
| 8565 | virtual uint rule() const { return minD_reduction_reg_rule; } |
| 8566 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8567 | virtual int ideal_Opcode() const { return Op_MinD; } |
| 8568 | public: |
| 8569 | minD_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 8570 | virtual uint size_of() const { return sizeof(minD_reduction_regNode); } |
| 8571 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 8572 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 8573 | static const Pipeline *pipeline_class(); |
| 8574 | virtual const Pipeline *pipeline() const; |
| 8575 | #ifndef PRODUCT |
| 8576 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8577 | virtual const char *Name() const { return "minD_reduction_reg";} |
| 8578 | #endif |
| 8579 | }; |
| 8580 | |
| 8581 | class leaP8Node : public MachTypeNode { |
| 8582 | private: |
| 8583 | MachOper *_opnd_array[2]; |
| 8584 | public: |
| 8585 | MachOper *opnd_array(uint operand_index) const { |
| 8586 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8587 | return _opnd_array[operand_index]; |
| 8588 | } |
| 8589 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8590 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8591 | _opnd_array[operand_index] = operand; |
| 8592 | } |
| 8593 | private: |
| 8594 | virtual const RegMask &out_RegMask() const; |
| 8595 | virtual uint rule() const { return leaP8_rule; } |
| 8596 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8597 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8598 | virtual uint oper_input_base() const { return 2; } |
| 8599 | public: |
| 8600 | leaP8Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8601 | virtual uint size_of() const { return sizeof(leaP8Node); } |
| 8602 | // Rematerialize leaP8 |
| 8603 | static const Pipeline *pipeline_class(); |
| 8604 | virtual const Pipeline *pipeline() const; |
| 8605 | #ifndef PRODUCT |
| 8606 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8607 | virtual const char *Name() const { return "leaP8";} |
| 8608 | #endif |
| 8609 | }; |
| 8610 | |
| 8611 | class leaP32Node : public MachTypeNode { |
| 8612 | private: |
| 8613 | MachOper *_opnd_array[2]; |
| 8614 | public: |
| 8615 | MachOper *opnd_array(uint operand_index) const { |
| 8616 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8617 | return _opnd_array[operand_index]; |
| 8618 | } |
| 8619 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8620 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8621 | _opnd_array[operand_index] = operand; |
| 8622 | } |
| 8623 | private: |
| 8624 | virtual const RegMask &out_RegMask() const; |
| 8625 | virtual uint rule() const { return leaP32_rule; } |
| 8626 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8627 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8628 | virtual uint oper_input_base() const { return 2; } |
| 8629 | public: |
| 8630 | leaP32Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8631 | virtual uint size_of() const { return sizeof(leaP32Node); } |
| 8632 | // Rematerialize leaP32 |
| 8633 | static const Pipeline *pipeline_class(); |
| 8634 | virtual const Pipeline *pipeline() const; |
| 8635 | #ifndef PRODUCT |
| 8636 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8637 | virtual const char *Name() const { return "leaP32";} |
| 8638 | #endif |
| 8639 | }; |
| 8640 | |
| 8641 | class leaPIdxOffNode : public MachTypeNode { |
| 8642 | private: |
| 8643 | MachOper *_opnd_array[2]; |
| 8644 | public: |
| 8645 | MachOper *opnd_array(uint operand_index) const { |
| 8646 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8647 | return _opnd_array[operand_index]; |
| 8648 | } |
| 8649 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8650 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8651 | _opnd_array[operand_index] = operand; |
| 8652 | } |
| 8653 | private: |
| 8654 | virtual const RegMask &out_RegMask() const; |
| 8655 | virtual uint rule() const { return leaPIdxOff_rule; } |
| 8656 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8657 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8658 | virtual uint oper_input_base() const { return 2; } |
| 8659 | public: |
| 8660 | leaPIdxOffNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8661 | virtual uint size_of() const { return sizeof(leaPIdxOffNode); } |
| 8662 | // Rematerialize leaPIdxOff |
| 8663 | static const Pipeline *pipeline_class(); |
| 8664 | virtual const Pipeline *pipeline() const; |
| 8665 | #ifndef PRODUCT |
| 8666 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8667 | virtual const char *Name() const { return "leaPIdxOff";} |
| 8668 | #endif |
| 8669 | }; |
| 8670 | |
| 8671 | class leaPIdxScaleNode : public MachTypeNode { |
| 8672 | private: |
| 8673 | MachOper *_opnd_array[2]; |
| 8674 | public: |
| 8675 | MachOper *opnd_array(uint operand_index) const { |
| 8676 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8677 | return _opnd_array[operand_index]; |
| 8678 | } |
| 8679 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8680 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8681 | _opnd_array[operand_index] = operand; |
| 8682 | } |
| 8683 | private: |
| 8684 | virtual const RegMask &out_RegMask() const; |
| 8685 | virtual uint rule() const { return leaPIdxScale_rule; } |
| 8686 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8687 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8688 | virtual uint oper_input_base() const { return 2; } |
| 8689 | public: |
| 8690 | leaPIdxScaleNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8691 | virtual uint size_of() const { return sizeof(leaPIdxScaleNode); } |
| 8692 | // Rematerialize leaPIdxScale |
| 8693 | static const Pipeline *pipeline_class(); |
| 8694 | virtual const Pipeline *pipeline() const; |
| 8695 | #ifndef PRODUCT |
| 8696 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8697 | virtual const char *Name() const { return "leaPIdxScale";} |
| 8698 | #endif |
| 8699 | }; |
| 8700 | |
| 8701 | class leaPPosIdxScaleNode : public MachTypeNode { |
| 8702 | private: |
| 8703 | MachOper *_opnd_array[2]; |
| 8704 | public: |
| 8705 | MachOper *opnd_array(uint operand_index) const { |
| 8706 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8707 | return _opnd_array[operand_index]; |
| 8708 | } |
| 8709 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8710 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8711 | _opnd_array[operand_index] = operand; |
| 8712 | } |
| 8713 | private: |
| 8714 | virtual const RegMask &out_RegMask() const; |
| 8715 | virtual uint rule() const { return leaPPosIdxScale_rule; } |
| 8716 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8717 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8718 | virtual uint oper_input_base() const { return 2; } |
| 8719 | public: |
| 8720 | leaPPosIdxScaleNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8721 | virtual uint size_of() const { return sizeof(leaPPosIdxScaleNode); } |
| 8722 | // Rematerialize leaPPosIdxScale |
| 8723 | static const Pipeline *pipeline_class(); |
| 8724 | virtual const Pipeline *pipeline() const; |
| 8725 | #ifndef PRODUCT |
| 8726 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8727 | virtual const char *Name() const { return "leaPPosIdxScale";} |
| 8728 | #endif |
| 8729 | }; |
| 8730 | |
| 8731 | class leaPIdxScaleOffNode : public MachTypeNode { |
| 8732 | private: |
| 8733 | MachOper *_opnd_array[2]; |
| 8734 | public: |
| 8735 | MachOper *opnd_array(uint operand_index) const { |
| 8736 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8737 | return _opnd_array[operand_index]; |
| 8738 | } |
| 8739 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8740 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8741 | _opnd_array[operand_index] = operand; |
| 8742 | } |
| 8743 | private: |
| 8744 | virtual const RegMask &out_RegMask() const; |
| 8745 | virtual uint rule() const { return leaPIdxScaleOff_rule; } |
| 8746 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8747 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8748 | virtual uint oper_input_base() const { return 2; } |
| 8749 | public: |
| 8750 | leaPIdxScaleOffNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8751 | virtual uint size_of() const { return sizeof(leaPIdxScaleOffNode); } |
| 8752 | // Rematerialize leaPIdxScaleOff |
| 8753 | static const Pipeline *pipeline_class(); |
| 8754 | virtual const Pipeline *pipeline() const; |
| 8755 | #ifndef PRODUCT |
| 8756 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8757 | virtual const char *Name() const { return "leaPIdxScaleOff";} |
| 8758 | #endif |
| 8759 | }; |
| 8760 | |
| 8761 | class leaPPosIdxOffNode : public MachTypeNode { |
| 8762 | private: |
| 8763 | MachOper *_opnd_array[2]; |
| 8764 | public: |
| 8765 | MachOper *opnd_array(uint operand_index) const { |
| 8766 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8767 | return _opnd_array[operand_index]; |
| 8768 | } |
| 8769 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8770 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8771 | _opnd_array[operand_index] = operand; |
| 8772 | } |
| 8773 | private: |
| 8774 | virtual const RegMask &out_RegMask() const; |
| 8775 | virtual uint rule() const { return leaPPosIdxOff_rule; } |
| 8776 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8777 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8778 | virtual uint oper_input_base() const { return 2; } |
| 8779 | public: |
| 8780 | leaPPosIdxOffNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8781 | virtual uint size_of() const { return sizeof(leaPPosIdxOffNode); } |
| 8782 | // Rematerialize leaPPosIdxOff |
| 8783 | static const Pipeline *pipeline_class(); |
| 8784 | virtual const Pipeline *pipeline() const; |
| 8785 | #ifndef PRODUCT |
| 8786 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8787 | virtual const char *Name() const { return "leaPPosIdxOff";} |
| 8788 | #endif |
| 8789 | }; |
| 8790 | |
| 8791 | class leaPPosIdxScaleOffNode : public MachTypeNode { |
| 8792 | private: |
| 8793 | MachOper *_opnd_array[2]; |
| 8794 | public: |
| 8795 | MachOper *opnd_array(uint operand_index) const { |
| 8796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8797 | return _opnd_array[operand_index]; |
| 8798 | } |
| 8799 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8800 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8801 | _opnd_array[operand_index] = operand; |
| 8802 | } |
| 8803 | private: |
| 8804 | virtual const RegMask &out_RegMask() const; |
| 8805 | virtual uint rule() const { return leaPPosIdxScaleOff_rule; } |
| 8806 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8807 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8808 | virtual uint oper_input_base() const { return 2; } |
| 8809 | public: |
| 8810 | leaPPosIdxScaleOffNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8811 | virtual uint size_of() const { return sizeof(leaPPosIdxScaleOffNode); } |
| 8812 | // Rematerialize leaPPosIdxScaleOff |
| 8813 | static const Pipeline *pipeline_class(); |
| 8814 | virtual const Pipeline *pipeline() const; |
| 8815 | #ifndef PRODUCT |
| 8816 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8817 | virtual const char *Name() const { return "leaPPosIdxScaleOff";} |
| 8818 | #endif |
| 8819 | }; |
| 8820 | |
| 8821 | class leaPCompressedOopOffsetNode : public MachTypeNode { |
| 8822 | private: |
| 8823 | MachOper *_opnd_array[2]; |
| 8824 | public: |
| 8825 | MachOper *opnd_array(uint operand_index) const { |
| 8826 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8827 | return _opnd_array[operand_index]; |
| 8828 | } |
| 8829 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8831 | _opnd_array[operand_index] = operand; |
| 8832 | } |
| 8833 | private: |
| 8834 | virtual const RegMask &out_RegMask() const; |
| 8835 | virtual uint rule() const { return leaPCompressedOopOffset_rule; } |
| 8836 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8837 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8838 | virtual uint oper_input_base() const { return 2; } |
| 8839 | public: |
| 8840 | leaPCompressedOopOffsetNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8841 | virtual uint size_of() const { return sizeof(leaPCompressedOopOffsetNode); } |
| 8842 | // Rematerialize leaPCompressedOopOffset |
| 8843 | static const Pipeline *pipeline_class(); |
| 8844 | virtual const Pipeline *pipeline() const; |
| 8845 | #ifndef PRODUCT |
| 8846 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8847 | virtual const char *Name() const { return "leaPCompressedOopOffset";} |
| 8848 | #endif |
| 8849 | }; |
| 8850 | |
| 8851 | class leaP8NarrowNode : public MachTypeNode { |
| 8852 | private: |
| 8853 | MachOper *_opnd_array[2]; |
| 8854 | public: |
| 8855 | MachOper *opnd_array(uint operand_index) const { |
| 8856 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8857 | return _opnd_array[operand_index]; |
| 8858 | } |
| 8859 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8860 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8861 | _opnd_array[operand_index] = operand; |
| 8862 | } |
| 8863 | private: |
| 8864 | virtual const RegMask &out_RegMask() const; |
| 8865 | virtual uint rule() const { return leaP8Narrow_rule; } |
| 8866 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8867 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8868 | virtual uint oper_input_base() const { return 2; } |
| 8869 | public: |
| 8870 | leaP8NarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8871 | virtual uint size_of() const { return sizeof(leaP8NarrowNode); } |
| 8872 | // Rematerialize leaP8Narrow |
| 8873 | static const Pipeline *pipeline_class(); |
| 8874 | virtual const Pipeline *pipeline() const; |
| 8875 | #ifndef PRODUCT |
| 8876 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8877 | virtual const char *Name() const { return "leaP8Narrow";} |
| 8878 | #endif |
| 8879 | }; |
| 8880 | |
| 8881 | class leaP32NarrowNode : public MachTypeNode { |
| 8882 | private: |
| 8883 | MachOper *_opnd_array[2]; |
| 8884 | public: |
| 8885 | MachOper *opnd_array(uint operand_index) const { |
| 8886 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8887 | return _opnd_array[operand_index]; |
| 8888 | } |
| 8889 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8890 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8891 | _opnd_array[operand_index] = operand; |
| 8892 | } |
| 8893 | private: |
| 8894 | virtual const RegMask &out_RegMask() const; |
| 8895 | virtual uint rule() const { return leaP32Narrow_rule; } |
| 8896 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8897 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8898 | virtual uint oper_input_base() const { return 2; } |
| 8899 | public: |
| 8900 | leaP32NarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8901 | virtual uint size_of() const { return sizeof(leaP32NarrowNode); } |
| 8902 | // Rematerialize leaP32Narrow |
| 8903 | static const Pipeline *pipeline_class(); |
| 8904 | virtual const Pipeline *pipeline() const; |
| 8905 | #ifndef PRODUCT |
| 8906 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8907 | virtual const char *Name() const { return "leaP32Narrow";} |
| 8908 | #endif |
| 8909 | }; |
| 8910 | |
| 8911 | class leaPIdxOffNarrowNode : public MachTypeNode { |
| 8912 | private: |
| 8913 | MachOper *_opnd_array[2]; |
| 8914 | public: |
| 8915 | MachOper *opnd_array(uint operand_index) const { |
| 8916 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8917 | return _opnd_array[operand_index]; |
| 8918 | } |
| 8919 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8920 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8921 | _opnd_array[operand_index] = operand; |
| 8922 | } |
| 8923 | private: |
| 8924 | virtual const RegMask &out_RegMask() const; |
| 8925 | virtual uint rule() const { return leaPIdxOffNarrow_rule; } |
| 8926 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8927 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8928 | virtual uint oper_input_base() const { return 2; } |
| 8929 | public: |
| 8930 | leaPIdxOffNarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8931 | virtual uint size_of() const { return sizeof(leaPIdxOffNarrowNode); } |
| 8932 | // Rematerialize leaPIdxOffNarrow |
| 8933 | static const Pipeline *pipeline_class(); |
| 8934 | virtual const Pipeline *pipeline() const; |
| 8935 | #ifndef PRODUCT |
| 8936 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8937 | virtual const char *Name() const { return "leaPIdxOffNarrow";} |
| 8938 | #endif |
| 8939 | }; |
| 8940 | |
| 8941 | class leaPIdxScaleNarrowNode : public MachTypeNode { |
| 8942 | private: |
| 8943 | MachOper *_opnd_array[2]; |
| 8944 | public: |
| 8945 | MachOper *opnd_array(uint operand_index) const { |
| 8946 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8947 | return _opnd_array[operand_index]; |
| 8948 | } |
| 8949 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8950 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8951 | _opnd_array[operand_index] = operand; |
| 8952 | } |
| 8953 | private: |
| 8954 | virtual const RegMask &out_RegMask() const; |
| 8955 | virtual uint rule() const { return leaPIdxScaleNarrow_rule; } |
| 8956 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8957 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8958 | virtual uint oper_input_base() const { return 2; } |
| 8959 | public: |
| 8960 | leaPIdxScaleNarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8961 | virtual uint size_of() const { return sizeof(leaPIdxScaleNarrowNode); } |
| 8962 | // Rematerialize leaPIdxScaleNarrow |
| 8963 | static const Pipeline *pipeline_class(); |
| 8964 | virtual const Pipeline *pipeline() const; |
| 8965 | #ifndef PRODUCT |
| 8966 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8967 | virtual const char *Name() const { return "leaPIdxScaleNarrow";} |
| 8968 | #endif |
| 8969 | }; |
| 8970 | |
| 8971 | class leaPIdxScaleOffNarrowNode : public MachTypeNode { |
| 8972 | private: |
| 8973 | MachOper *_opnd_array[2]; |
| 8974 | public: |
| 8975 | MachOper *opnd_array(uint operand_index) const { |
| 8976 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8977 | return _opnd_array[operand_index]; |
| 8978 | } |
| 8979 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 8980 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 8981 | _opnd_array[operand_index] = operand; |
| 8982 | } |
| 8983 | private: |
| 8984 | virtual const RegMask &out_RegMask() const; |
| 8985 | virtual uint rule() const { return leaPIdxScaleOffNarrow_rule; } |
| 8986 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 8987 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 8988 | virtual uint oper_input_base() const { return 2; } |
| 8989 | public: |
| 8990 | leaPIdxScaleOffNarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 8991 | virtual uint size_of() const { return sizeof(leaPIdxScaleOffNarrowNode); } |
| 8992 | // Rematerialize leaPIdxScaleOffNarrow |
| 8993 | static const Pipeline *pipeline_class(); |
| 8994 | virtual const Pipeline *pipeline() const; |
| 8995 | #ifndef PRODUCT |
| 8996 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 8997 | virtual const char *Name() const { return "leaPIdxScaleOffNarrow";} |
| 8998 | #endif |
| 8999 | }; |
| 9000 | |
| 9001 | class leaPPosIdxOffNarrowNode : public MachTypeNode { |
| 9002 | private: |
| 9003 | MachOper *_opnd_array[2]; |
| 9004 | public: |
| 9005 | MachOper *opnd_array(uint operand_index) const { |
| 9006 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9007 | return _opnd_array[operand_index]; |
| 9008 | } |
| 9009 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9010 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9011 | _opnd_array[operand_index] = operand; |
| 9012 | } |
| 9013 | private: |
| 9014 | virtual const RegMask &out_RegMask() const; |
| 9015 | virtual uint rule() const { return leaPPosIdxOffNarrow_rule; } |
| 9016 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9017 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 9018 | virtual uint oper_input_base() const { return 2; } |
| 9019 | public: |
| 9020 | leaPPosIdxOffNarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9021 | virtual uint size_of() const { return sizeof(leaPPosIdxOffNarrowNode); } |
| 9022 | // Rematerialize leaPPosIdxOffNarrow |
| 9023 | static const Pipeline *pipeline_class(); |
| 9024 | virtual const Pipeline *pipeline() const; |
| 9025 | #ifndef PRODUCT |
| 9026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9027 | virtual const char *Name() const { return "leaPPosIdxOffNarrow";} |
| 9028 | #endif |
| 9029 | }; |
| 9030 | |
| 9031 | class leaPPosIdxScaleOffNarrowNode : public MachTypeNode { |
| 9032 | private: |
| 9033 | MachOper *_opnd_array[2]; |
| 9034 | public: |
| 9035 | MachOper *opnd_array(uint operand_index) const { |
| 9036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9037 | return _opnd_array[operand_index]; |
| 9038 | } |
| 9039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9041 | _opnd_array[operand_index] = operand; |
| 9042 | } |
| 9043 | private: |
| 9044 | virtual const RegMask &out_RegMask() const; |
| 9045 | virtual uint rule() const { return leaPPosIdxScaleOffNarrow_rule; } |
| 9046 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9047 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 9048 | virtual uint oper_input_base() const { return 2; } |
| 9049 | public: |
| 9050 | leaPPosIdxScaleOffNarrowNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9051 | virtual uint size_of() const { return sizeof(leaPPosIdxScaleOffNarrowNode); } |
| 9052 | // Rematerialize leaPPosIdxScaleOffNarrow |
| 9053 | static const Pipeline *pipeline_class(); |
| 9054 | virtual const Pipeline *pipeline() const; |
| 9055 | #ifndef PRODUCT |
| 9056 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9057 | virtual const char *Name() const { return "leaPPosIdxScaleOffNarrow";} |
| 9058 | #endif |
| 9059 | }; |
| 9060 | |
| 9061 | class loadConINode : public MachNode { |
| 9062 | private: |
| 9063 | MachOper *_opnd_array[2]; |
| 9064 | public: |
| 9065 | MachOper *opnd_array(uint operand_index) const { |
| 9066 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9067 | return _opnd_array[operand_index]; |
| 9068 | } |
| 9069 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9070 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9071 | _opnd_array[operand_index] = operand; |
| 9072 | } |
| 9073 | private: |
| 9074 | virtual const RegMask &out_RegMask() const; |
| 9075 | virtual uint rule() const { return loadConI_rule; } |
| 9076 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9077 | virtual int ideal_Opcode() const { return Op_ConI; } |
| 9078 | public: |
| 9079 | loadConINode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9080 | virtual uint size_of() const { return sizeof(loadConINode); } |
| 9081 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9082 | // Rematerialize loadConI |
| 9083 | static const Pipeline *pipeline_class(); |
| 9084 | virtual const Pipeline *pipeline() const; |
| 9085 | virtual const class Type *bottom_type() const { |
| 9086 | return TypeInt::make(opnd_array(1)->constant()); |
| 9087 | }; |
| 9088 | #ifndef PRODUCT |
| 9089 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9090 | virtual const char *Name() const { return "loadConI";} |
| 9091 | #endif |
| 9092 | }; |
| 9093 | |
| 9094 | class loadConI0Node : public MachNode { |
| 9095 | private: |
| 9096 | MachOper *_opnd_array[2]; |
| 9097 | public: |
| 9098 | MachOper *opnd_array(uint operand_index) const { |
| 9099 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9100 | return _opnd_array[operand_index]; |
| 9101 | } |
| 9102 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9103 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9104 | _opnd_array[operand_index] = operand; |
| 9105 | } |
| 9106 | private: |
| 9107 | virtual const RegMask &out_RegMask() const; |
| 9108 | virtual uint rule() const { return loadConI0_rule; } |
| 9109 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9110 | virtual int ideal_Opcode() const { return Op_ConI; } |
| 9111 | public: |
| 9112 | loadConI0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9113 | virtual uint size_of() const { return sizeof(loadConI0Node); } |
| 9114 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9115 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9116 | // Rematerialize loadConI0 |
| 9117 | static const Pipeline *pipeline_class(); |
| 9118 | virtual const Pipeline *pipeline() const; |
| 9119 | virtual const class Type *bottom_type() const { |
| 9120 | return TypeInt::make(opnd_array(1)->constant()); |
| 9121 | }; |
| 9122 | #ifndef PRODUCT |
| 9123 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9124 | virtual const char *Name() const { return "loadConI0";} |
| 9125 | #endif |
| 9126 | }; |
| 9127 | |
| 9128 | class loadConLNode : public MachNode { |
| 9129 | private: |
| 9130 | MachOper *_opnd_array[2]; |
| 9131 | public: |
| 9132 | MachOper *opnd_array(uint operand_index) const { |
| 9133 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9134 | return _opnd_array[operand_index]; |
| 9135 | } |
| 9136 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9138 | _opnd_array[operand_index] = operand; |
| 9139 | } |
| 9140 | private: |
| 9141 | virtual const RegMask &out_RegMask() const; |
| 9142 | virtual uint rule() const { return loadConL_rule; } |
| 9143 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9144 | virtual int ideal_Opcode() const { return Op_ConL; } |
| 9145 | public: |
| 9146 | loadConLNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9147 | virtual uint size_of() const { return sizeof(loadConLNode); } |
| 9148 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9149 | // Rematerialize loadConL |
| 9150 | static const Pipeline *pipeline_class(); |
| 9151 | virtual const Pipeline *pipeline() const; |
| 9152 | virtual const class Type *bottom_type() const { |
| 9153 | return TypeLong::make(opnd_array(1)->constantL()); |
| 9154 | }; |
| 9155 | #ifndef PRODUCT |
| 9156 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9157 | virtual const char *Name() const { return "loadConL";} |
| 9158 | #endif |
| 9159 | }; |
| 9160 | |
| 9161 | class loadConL0Node : public MachNode { |
| 9162 | private: |
| 9163 | MachOper *_opnd_array[2]; |
| 9164 | public: |
| 9165 | MachOper *opnd_array(uint operand_index) const { |
| 9166 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9167 | return _opnd_array[operand_index]; |
| 9168 | } |
| 9169 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9170 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9171 | _opnd_array[operand_index] = operand; |
| 9172 | } |
| 9173 | private: |
| 9174 | virtual const RegMask &out_RegMask() const; |
| 9175 | virtual uint rule() const { return loadConL0_rule; } |
| 9176 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9177 | virtual int ideal_Opcode() const { return Op_ConL; } |
| 9178 | public: |
| 9179 | loadConL0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9180 | virtual uint size_of() const { return sizeof(loadConL0Node); } |
| 9181 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9182 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9183 | // Rematerialize loadConL0 |
| 9184 | static const Pipeline *pipeline_class(); |
| 9185 | virtual const Pipeline *pipeline() const; |
| 9186 | virtual const class Type *bottom_type() const { |
| 9187 | return TypeLong::make(opnd_array(1)->constantL()); |
| 9188 | }; |
| 9189 | #ifndef PRODUCT |
| 9190 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9191 | virtual const char *Name() const { return "loadConL0";} |
| 9192 | #endif |
| 9193 | }; |
| 9194 | |
| 9195 | class loadConUL32Node : public MachNode { |
| 9196 | private: |
| 9197 | MachOper *_opnd_array[2]; |
| 9198 | public: |
| 9199 | MachOper *opnd_array(uint operand_index) const { |
| 9200 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9201 | return _opnd_array[operand_index]; |
| 9202 | } |
| 9203 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9204 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9205 | _opnd_array[operand_index] = operand; |
| 9206 | } |
| 9207 | private: |
| 9208 | virtual const RegMask &out_RegMask() const; |
| 9209 | virtual uint rule() const { return loadConUL32_rule; } |
| 9210 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9211 | virtual int ideal_Opcode() const { return Op_ConL; } |
| 9212 | public: |
| 9213 | loadConUL32Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9214 | virtual uint size_of() const { return sizeof(loadConUL32Node); } |
| 9215 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9216 | // Rematerialize loadConUL32 |
| 9217 | static const Pipeline *pipeline_class(); |
| 9218 | virtual const Pipeline *pipeline() const; |
| 9219 | virtual const class Type *bottom_type() const { |
| 9220 | return TypeLong::make(opnd_array(1)->constantL()); |
| 9221 | }; |
| 9222 | #ifndef PRODUCT |
| 9223 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9224 | virtual const char *Name() const { return "loadConUL32";} |
| 9225 | #endif |
| 9226 | }; |
| 9227 | |
| 9228 | class loadConL32Node : public MachNode { |
| 9229 | private: |
| 9230 | MachOper *_opnd_array[2]; |
| 9231 | public: |
| 9232 | MachOper *opnd_array(uint operand_index) const { |
| 9233 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9234 | return _opnd_array[operand_index]; |
| 9235 | } |
| 9236 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9237 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9238 | _opnd_array[operand_index] = operand; |
| 9239 | } |
| 9240 | private: |
| 9241 | virtual const RegMask &out_RegMask() const; |
| 9242 | virtual uint rule() const { return loadConL32_rule; } |
| 9243 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9244 | virtual int ideal_Opcode() const { return Op_ConL; } |
| 9245 | public: |
| 9246 | loadConL32Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9247 | virtual uint size_of() const { return sizeof(loadConL32Node); } |
| 9248 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9249 | // Rematerialize loadConL32 |
| 9250 | static const Pipeline *pipeline_class(); |
| 9251 | virtual const Pipeline *pipeline() const; |
| 9252 | virtual const class Type *bottom_type() const { |
| 9253 | return TypeLong::make(opnd_array(1)->constantL()); |
| 9254 | }; |
| 9255 | #ifndef PRODUCT |
| 9256 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9257 | virtual const char *Name() const { return "loadConL32";} |
| 9258 | #endif |
| 9259 | }; |
| 9260 | |
| 9261 | class loadConPNode : public MachNode { |
| 9262 | private: |
| 9263 | MachOper *_opnd_array[2]; |
| 9264 | public: |
| 9265 | MachOper *opnd_array(uint operand_index) const { |
| 9266 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9267 | return _opnd_array[operand_index]; |
| 9268 | } |
| 9269 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9271 | _opnd_array[operand_index] = operand; |
| 9272 | } |
| 9273 | private: |
| 9274 | virtual const RegMask &out_RegMask() const; |
| 9275 | virtual uint rule() const { return loadConP_rule; } |
| 9276 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9277 | virtual int ideal_Opcode() const { return Op_ConP; } |
| 9278 | virtual int reloc() const; |
| 9279 | public: |
| 9280 | loadConPNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9281 | virtual uint size_of() const { return sizeof(loadConPNode); } |
| 9282 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9283 | // Rematerialize loadConP |
| 9284 | static const Pipeline *pipeline_class(); |
| 9285 | virtual const Pipeline *pipeline() const; |
| 9286 | virtual const class Type *bottom_type() const { |
| 9287 | return opnd_array(1)->type(); |
| 9288 | }; |
| 9289 | #ifndef PRODUCT |
| 9290 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9291 | virtual const char *Name() const { return "loadConP";} |
| 9292 | #endif |
| 9293 | }; |
| 9294 | |
| 9295 | class loadConP0Node : public MachNode { |
| 9296 | private: |
| 9297 | MachOper *_opnd_array[2]; |
| 9298 | public: |
| 9299 | MachOper *opnd_array(uint operand_index) const { |
| 9300 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9301 | return _opnd_array[operand_index]; |
| 9302 | } |
| 9303 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9304 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9305 | _opnd_array[operand_index] = operand; |
| 9306 | } |
| 9307 | private: |
| 9308 | virtual const RegMask &out_RegMask() const; |
| 9309 | virtual uint rule() const { return loadConP0_rule; } |
| 9310 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9311 | virtual int ideal_Opcode() const { return Op_ConP; } |
| 9312 | virtual int reloc() const; |
| 9313 | public: |
| 9314 | loadConP0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9315 | virtual uint size_of() const { return sizeof(loadConP0Node); } |
| 9316 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9317 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9318 | // Rematerialize loadConP0 |
| 9319 | static const Pipeline *pipeline_class(); |
| 9320 | virtual const Pipeline *pipeline() const; |
| 9321 | virtual const class Type *bottom_type() const { |
| 9322 | return opnd_array(1)->type(); |
| 9323 | }; |
| 9324 | #ifndef PRODUCT |
| 9325 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9326 | virtual const char *Name() const { return "loadConP0";} |
| 9327 | #endif |
| 9328 | }; |
| 9329 | |
| 9330 | class loadConP31Node : public MachNode { |
| 9331 | private: |
| 9332 | MachOper *_opnd_array[2]; |
| 9333 | public: |
| 9334 | MachOper *opnd_array(uint operand_index) const { |
| 9335 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9336 | return _opnd_array[operand_index]; |
| 9337 | } |
| 9338 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9339 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9340 | _opnd_array[operand_index] = operand; |
| 9341 | } |
| 9342 | private: |
| 9343 | virtual const RegMask &out_RegMask() const; |
| 9344 | virtual uint rule() const { return loadConP31_rule; } |
| 9345 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9346 | virtual int ideal_Opcode() const { return Op_ConP; } |
| 9347 | virtual int reloc() const; |
| 9348 | public: |
| 9349 | loadConP31Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9350 | virtual uint size_of() const { return sizeof(loadConP31Node); } |
| 9351 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9352 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9353 | // Rematerialize loadConP31 |
| 9354 | static const Pipeline *pipeline_class(); |
| 9355 | virtual const Pipeline *pipeline() const; |
| 9356 | virtual const class Type *bottom_type() const { |
| 9357 | return opnd_array(1)->type(); |
| 9358 | }; |
| 9359 | #ifndef PRODUCT |
| 9360 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9361 | virtual const char *Name() const { return "loadConP31";} |
| 9362 | #endif |
| 9363 | }; |
| 9364 | |
| 9365 | class loadConFNode : public MachConstantNode { |
| 9366 | private: |
| 9367 | MachOper *_opnd_array[2]; |
| 9368 | public: |
| 9369 | MachOper *opnd_array(uint operand_index) const { |
| 9370 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9371 | return _opnd_array[operand_index]; |
| 9372 | } |
| 9373 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9374 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9375 | _opnd_array[operand_index] = operand; |
| 9376 | } |
| 9377 | private: |
| 9378 | virtual const RegMask &out_RegMask() const; |
| 9379 | virtual uint rule() const { return loadConF_rule; } |
| 9380 | virtual void eval_constant(Compile* C); |
| 9381 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9382 | virtual int ideal_Opcode() const { return Op_ConF; } |
| 9383 | virtual int reloc() const; |
| 9384 | virtual uint oper_input_base() const { return 1; } |
| 9385 | public: |
| 9386 | loadConFNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9387 | virtual uint size_of() const { return sizeof(loadConFNode); } |
| 9388 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9389 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9390 | // Rematerialize loadConF |
| 9391 | static const Pipeline *pipeline_class(); |
| 9392 | virtual const Pipeline *pipeline() const; |
| 9393 | virtual const class Type *bottom_type() const { |
| 9394 | return TypeF::make(opnd_array(1)->constantF()); |
| 9395 | }; |
| 9396 | #ifndef PRODUCT |
| 9397 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9398 | virtual const char *Name() const { return "loadConF";} |
| 9399 | #endif |
| 9400 | }; |
| 9401 | |
| 9402 | class loadConN0Node : public MachNode { |
| 9403 | private: |
| 9404 | MachOper *_opnd_array[2]; |
| 9405 | public: |
| 9406 | MachOper *opnd_array(uint operand_index) const { |
| 9407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9408 | return _opnd_array[operand_index]; |
| 9409 | } |
| 9410 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9412 | _opnd_array[operand_index] = operand; |
| 9413 | } |
| 9414 | private: |
| 9415 | virtual const RegMask &out_RegMask() const; |
| 9416 | virtual uint rule() const { return loadConN0_rule; } |
| 9417 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9418 | virtual int ideal_Opcode() const { return Op_ConN; } |
| 9419 | public: |
| 9420 | loadConN0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9421 | virtual uint size_of() const { return sizeof(loadConN0Node); } |
| 9422 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9423 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9424 | // Rematerialize loadConN0 |
| 9425 | static const Pipeline *pipeline_class(); |
| 9426 | virtual const Pipeline *pipeline() const; |
| 9427 | virtual const class Type *bottom_type() const { |
| 9428 | return opnd_array(1)->type(); |
| 9429 | }; |
| 9430 | #ifndef PRODUCT |
| 9431 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9432 | virtual const char *Name() const { return "loadConN0";} |
| 9433 | #endif |
| 9434 | }; |
| 9435 | |
| 9436 | class loadConNNode : public MachNode { |
| 9437 | private: |
| 9438 | MachOper *_opnd_array[2]; |
| 9439 | public: |
| 9440 | MachOper *opnd_array(uint operand_index) const { |
| 9441 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9442 | return _opnd_array[operand_index]; |
| 9443 | } |
| 9444 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9445 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9446 | _opnd_array[operand_index] = operand; |
| 9447 | } |
| 9448 | private: |
| 9449 | virtual const RegMask &out_RegMask() const; |
| 9450 | virtual uint rule() const { return loadConN_rule; } |
| 9451 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9452 | virtual int ideal_Opcode() const { return Op_ConN; } |
| 9453 | public: |
| 9454 | loadConNNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9455 | virtual uint size_of() const { return sizeof(loadConNNode); } |
| 9456 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9457 | // Rematerialize loadConN |
| 9458 | static const Pipeline *pipeline_class(); |
| 9459 | virtual const Pipeline *pipeline() const; |
| 9460 | virtual const class Type *bottom_type() const { |
| 9461 | return opnd_array(1)->type(); |
| 9462 | }; |
| 9463 | #ifndef PRODUCT |
| 9464 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9465 | virtual const char *Name() const { return "loadConN";} |
| 9466 | #endif |
| 9467 | }; |
| 9468 | |
| 9469 | class loadConNKlassNode : public MachNode { |
| 9470 | private: |
| 9471 | MachOper *_opnd_array[2]; |
| 9472 | public: |
| 9473 | MachOper *opnd_array(uint operand_index) const { |
| 9474 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9475 | return _opnd_array[operand_index]; |
| 9476 | } |
| 9477 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9478 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9479 | _opnd_array[operand_index] = operand; |
| 9480 | } |
| 9481 | private: |
| 9482 | virtual const RegMask &out_RegMask() const; |
| 9483 | virtual uint rule() const { return loadConNKlass_rule; } |
| 9484 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9485 | virtual int ideal_Opcode() const { return Op_ConNKlass; } |
| 9486 | public: |
| 9487 | loadConNKlassNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9488 | virtual uint size_of() const { return sizeof(loadConNKlassNode); } |
| 9489 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9490 | // Rematerialize loadConNKlass |
| 9491 | static const Pipeline *pipeline_class(); |
| 9492 | virtual const Pipeline *pipeline() const; |
| 9493 | virtual const class Type *bottom_type() const { |
| 9494 | return opnd_array(1)->type(); |
| 9495 | }; |
| 9496 | #ifndef PRODUCT |
| 9497 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9498 | virtual const char *Name() const { return "loadConNKlass";} |
| 9499 | #endif |
| 9500 | }; |
| 9501 | |
| 9502 | class loadConF0Node : public MachNode { |
| 9503 | private: |
| 9504 | MachOper *_opnd_array[2]; |
| 9505 | public: |
| 9506 | MachOper *opnd_array(uint operand_index) const { |
| 9507 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9508 | return _opnd_array[operand_index]; |
| 9509 | } |
| 9510 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9511 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9512 | _opnd_array[operand_index] = operand; |
| 9513 | } |
| 9514 | private: |
| 9515 | virtual const RegMask &out_RegMask() const; |
| 9516 | virtual uint rule() const { return loadConF0_rule; } |
| 9517 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9518 | virtual int ideal_Opcode() const { return Op_ConF; } |
| 9519 | virtual int reloc() const; |
| 9520 | public: |
| 9521 | loadConF0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9522 | virtual uint size_of() const { return sizeof(loadConF0Node); } |
| 9523 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9524 | // Rematerialize loadConF0 |
| 9525 | static const Pipeline *pipeline_class(); |
| 9526 | virtual const Pipeline *pipeline() const; |
| 9527 | virtual const class Type *bottom_type() const { |
| 9528 | return TypeF::make(opnd_array(1)->constantF()); |
| 9529 | }; |
| 9530 | #ifndef PRODUCT |
| 9531 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9532 | virtual const char *Name() const { return "loadConF0";} |
| 9533 | #endif |
| 9534 | }; |
| 9535 | |
| 9536 | class loadConDNode : public MachConstantNode { |
| 9537 | private: |
| 9538 | MachOper *_opnd_array[2]; |
| 9539 | public: |
| 9540 | MachOper *opnd_array(uint operand_index) const { |
| 9541 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9542 | return _opnd_array[operand_index]; |
| 9543 | } |
| 9544 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9545 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9546 | _opnd_array[operand_index] = operand; |
| 9547 | } |
| 9548 | private: |
| 9549 | virtual const RegMask &out_RegMask() const; |
| 9550 | virtual uint rule() const { return loadConD_rule; } |
| 9551 | virtual void eval_constant(Compile* C); |
| 9552 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9553 | virtual int ideal_Opcode() const { return Op_ConD; } |
| 9554 | virtual int reloc() const; |
| 9555 | virtual uint oper_input_base() const { return 1; } |
| 9556 | public: |
| 9557 | loadConDNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9558 | virtual uint size_of() const { return sizeof(loadConDNode); } |
| 9559 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 9560 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9561 | // Rematerialize loadConD |
| 9562 | static const Pipeline *pipeline_class(); |
| 9563 | virtual const Pipeline *pipeline() const; |
| 9564 | virtual const class Type *bottom_type() const { |
| 9565 | return TypeD::make(opnd_array(1)->constantD()); |
| 9566 | }; |
| 9567 | #ifndef PRODUCT |
| 9568 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9569 | virtual const char *Name() const { return "loadConD";} |
| 9570 | #endif |
| 9571 | }; |
| 9572 | |
| 9573 | class loadConD0Node : public MachNode { |
| 9574 | private: |
| 9575 | MachOper *_opnd_array[2]; |
| 9576 | public: |
| 9577 | MachOper *opnd_array(uint operand_index) const { |
| 9578 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9579 | return _opnd_array[operand_index]; |
| 9580 | } |
| 9581 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9582 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9583 | _opnd_array[operand_index] = operand; |
| 9584 | } |
| 9585 | private: |
| 9586 | virtual const RegMask &out_RegMask() const; |
| 9587 | virtual uint rule() const { return loadConD0_rule; } |
| 9588 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9589 | virtual int ideal_Opcode() const { return Op_ConD; } |
| 9590 | virtual int reloc() const; |
| 9591 | public: |
| 9592 | loadConD0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 9593 | virtual uint size_of() const { return sizeof(loadConD0Node); } |
| 9594 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 9595 | // Rematerialize loadConD0 |
| 9596 | static const Pipeline *pipeline_class(); |
| 9597 | virtual const Pipeline *pipeline() const; |
| 9598 | virtual const class Type *bottom_type() const { |
| 9599 | return TypeD::make(opnd_array(1)->constantD()); |
| 9600 | }; |
| 9601 | #ifndef PRODUCT |
| 9602 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9603 | virtual const char *Name() const { return "loadConD0";} |
| 9604 | #endif |
| 9605 | }; |
| 9606 | |
| 9607 | class loadSSINode : public MachNode { |
| 9608 | private: |
| 9609 | MachOper *_opnd_array[2]; |
| 9610 | public: |
| 9611 | MachOper *opnd_array(uint operand_index) const { |
| 9612 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9613 | return _opnd_array[operand_index]; |
| 9614 | } |
| 9615 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9616 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9617 | _opnd_array[operand_index] = operand; |
| 9618 | } |
| 9619 | private: |
| 9620 | virtual const RegMask &out_RegMask() const; |
| 9621 | virtual uint rule() const { return loadSSI_rule; } |
| 9622 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9623 | public: |
| 9624 | loadSSINode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9625 | virtual uint size_of() const { return sizeof(loadSSINode); } |
| 9626 | // Rematerialize loadSSI |
| 9627 | static const Pipeline *pipeline_class(); |
| 9628 | virtual const Pipeline *pipeline() const; |
| 9629 | #ifndef PRODUCT |
| 9630 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9631 | virtual const char *Name() const { return "loadSSI";} |
| 9632 | #endif |
| 9633 | }; |
| 9634 | |
| 9635 | class loadSSLNode : public MachNode { |
| 9636 | private: |
| 9637 | MachOper *_opnd_array[2]; |
| 9638 | public: |
| 9639 | MachOper *opnd_array(uint operand_index) const { |
| 9640 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9641 | return _opnd_array[operand_index]; |
| 9642 | } |
| 9643 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9644 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9645 | _opnd_array[operand_index] = operand; |
| 9646 | } |
| 9647 | private: |
| 9648 | virtual const RegMask &out_RegMask() const; |
| 9649 | virtual uint rule() const { return loadSSL_rule; } |
| 9650 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9651 | public: |
| 9652 | loadSSLNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9653 | virtual uint size_of() const { return sizeof(loadSSLNode); } |
| 9654 | // Rematerialize loadSSL |
| 9655 | static const Pipeline *pipeline_class(); |
| 9656 | virtual const Pipeline *pipeline() const; |
| 9657 | #ifndef PRODUCT |
| 9658 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9659 | virtual const char *Name() const { return "loadSSL";} |
| 9660 | #endif |
| 9661 | }; |
| 9662 | |
| 9663 | class loadSSPNode : public MachNode { |
| 9664 | private: |
| 9665 | MachOper *_opnd_array[2]; |
| 9666 | public: |
| 9667 | MachOper *opnd_array(uint operand_index) const { |
| 9668 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9669 | return _opnd_array[operand_index]; |
| 9670 | } |
| 9671 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9672 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9673 | _opnd_array[operand_index] = operand; |
| 9674 | } |
| 9675 | private: |
| 9676 | virtual const RegMask &out_RegMask() const; |
| 9677 | virtual uint rule() const { return loadSSP_rule; } |
| 9678 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9679 | public: |
| 9680 | loadSSPNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9681 | virtual uint size_of() const { return sizeof(loadSSPNode); } |
| 9682 | // Rematerialize loadSSP |
| 9683 | static const Pipeline *pipeline_class(); |
| 9684 | virtual const Pipeline *pipeline() const; |
| 9685 | #ifndef PRODUCT |
| 9686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9687 | virtual const char *Name() const { return "loadSSP";} |
| 9688 | #endif |
| 9689 | }; |
| 9690 | |
| 9691 | class loadSSFNode : public MachNode { |
| 9692 | private: |
| 9693 | MachOper *_opnd_array[2]; |
| 9694 | public: |
| 9695 | MachOper *opnd_array(uint operand_index) const { |
| 9696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9697 | return _opnd_array[operand_index]; |
| 9698 | } |
| 9699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9701 | _opnd_array[operand_index] = operand; |
| 9702 | } |
| 9703 | private: |
| 9704 | virtual const RegMask &out_RegMask() const; |
| 9705 | virtual uint rule() const { return loadSSF_rule; } |
| 9706 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9707 | public: |
| 9708 | loadSSFNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9709 | virtual uint size_of() const { return sizeof(loadSSFNode); } |
| 9710 | // Rematerialize loadSSF |
| 9711 | static const Pipeline *pipeline_class(); |
| 9712 | virtual const Pipeline *pipeline() const; |
| 9713 | #ifndef PRODUCT |
| 9714 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9715 | virtual const char *Name() const { return "loadSSF";} |
| 9716 | #endif |
| 9717 | }; |
| 9718 | |
| 9719 | class loadSSDNode : public MachNode { |
| 9720 | private: |
| 9721 | MachOper *_opnd_array[2]; |
| 9722 | public: |
| 9723 | MachOper *opnd_array(uint operand_index) const { |
| 9724 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9725 | return _opnd_array[operand_index]; |
| 9726 | } |
| 9727 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9728 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9729 | _opnd_array[operand_index] = operand; |
| 9730 | } |
| 9731 | private: |
| 9732 | virtual const RegMask &out_RegMask() const; |
| 9733 | virtual uint rule() const { return loadSSD_rule; } |
| 9734 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9735 | public: |
| 9736 | loadSSDNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 9737 | virtual uint size_of() const { return sizeof(loadSSDNode); } |
| 9738 | // Rematerialize loadSSD |
| 9739 | static const Pipeline *pipeline_class(); |
| 9740 | virtual const Pipeline *pipeline() const; |
| 9741 | #ifndef PRODUCT |
| 9742 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9743 | virtual const char *Name() const { return "loadSSD";} |
| 9744 | #endif |
| 9745 | }; |
| 9746 | |
| 9747 | class prefetchAllocNode : public MachNode { |
| 9748 | private: |
| 9749 | MachOper *_opnd_array[2]; |
| 9750 | public: |
| 9751 | MachOper *opnd_array(uint operand_index) const { |
| 9752 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9753 | return _opnd_array[operand_index]; |
| 9754 | } |
| 9755 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9756 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9757 | _opnd_array[operand_index] = operand; |
| 9758 | } |
| 9759 | private: |
| 9760 | virtual const RegMask &out_RegMask() const; |
| 9761 | virtual uint rule() const { return prefetchAlloc_rule; } |
| 9762 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9763 | virtual int ideal_Opcode() const { return Op_PrefetchAllocation; } |
| 9764 | virtual int reloc() const; |
| 9765 | virtual uint oper_input_base() const { return 2; } |
| 9766 | public: |
| 9767 | prefetchAllocNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9768 | virtual uint size_of() const { return sizeof(prefetchAllocNode); } |
| 9769 | static const Pipeline *pipeline_class(); |
| 9770 | virtual const Pipeline *pipeline() const; |
| 9771 | virtual const MachOper *memory_operand() const; |
| 9772 | #ifndef PRODUCT |
| 9773 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9774 | virtual const char *Name() const { return "prefetchAlloc";} |
| 9775 | #endif |
| 9776 | }; |
| 9777 | |
| 9778 | class prefetchAllocNTANode : public MachNode { |
| 9779 | private: |
| 9780 | MachOper *_opnd_array[2]; |
| 9781 | public: |
| 9782 | MachOper *opnd_array(uint operand_index) const { |
| 9783 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9784 | return _opnd_array[operand_index]; |
| 9785 | } |
| 9786 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9787 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9788 | _opnd_array[operand_index] = operand; |
| 9789 | } |
| 9790 | private: |
| 9791 | virtual const RegMask &out_RegMask() const; |
| 9792 | virtual uint rule() const { return prefetchAllocNTA_rule; } |
| 9793 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9794 | virtual int ideal_Opcode() const { return Op_PrefetchAllocation; } |
| 9795 | virtual int reloc() const; |
| 9796 | virtual uint oper_input_base() const { return 2; } |
| 9797 | public: |
| 9798 | prefetchAllocNTANode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9799 | virtual uint size_of() const { return sizeof(prefetchAllocNTANode); } |
| 9800 | static const Pipeline *pipeline_class(); |
| 9801 | virtual const Pipeline *pipeline() const; |
| 9802 | virtual const MachOper *memory_operand() const; |
| 9803 | #ifndef PRODUCT |
| 9804 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9805 | virtual const char *Name() const { return "prefetchAllocNTA";} |
| 9806 | #endif |
| 9807 | }; |
| 9808 | |
| 9809 | class prefetchAllocT0Node : public MachNode { |
| 9810 | private: |
| 9811 | MachOper *_opnd_array[2]; |
| 9812 | public: |
| 9813 | MachOper *opnd_array(uint operand_index) const { |
| 9814 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9815 | return _opnd_array[operand_index]; |
| 9816 | } |
| 9817 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9818 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9819 | _opnd_array[operand_index] = operand; |
| 9820 | } |
| 9821 | private: |
| 9822 | virtual const RegMask &out_RegMask() const; |
| 9823 | virtual uint rule() const { return prefetchAllocT0_rule; } |
| 9824 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9825 | virtual int ideal_Opcode() const { return Op_PrefetchAllocation; } |
| 9826 | virtual int reloc() const; |
| 9827 | virtual uint oper_input_base() const { return 2; } |
| 9828 | public: |
| 9829 | prefetchAllocT0Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9830 | virtual uint size_of() const { return sizeof(prefetchAllocT0Node); } |
| 9831 | static const Pipeline *pipeline_class(); |
| 9832 | virtual const Pipeline *pipeline() const; |
| 9833 | virtual const MachOper *memory_operand() const; |
| 9834 | #ifndef PRODUCT |
| 9835 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9836 | virtual const char *Name() const { return "prefetchAllocT0";} |
| 9837 | #endif |
| 9838 | }; |
| 9839 | |
| 9840 | class prefetchAllocT2Node : public MachNode { |
| 9841 | private: |
| 9842 | MachOper *_opnd_array[2]; |
| 9843 | public: |
| 9844 | MachOper *opnd_array(uint operand_index) const { |
| 9845 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9846 | return _opnd_array[operand_index]; |
| 9847 | } |
| 9848 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9849 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9850 | _opnd_array[operand_index] = operand; |
| 9851 | } |
| 9852 | private: |
| 9853 | virtual const RegMask &out_RegMask() const; |
| 9854 | virtual uint rule() const { return prefetchAllocT2_rule; } |
| 9855 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9856 | virtual int ideal_Opcode() const { return Op_PrefetchAllocation; } |
| 9857 | virtual int reloc() const; |
| 9858 | virtual uint oper_input_base() const { return 2; } |
| 9859 | public: |
| 9860 | prefetchAllocT2Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 9861 | virtual uint size_of() const { return sizeof(prefetchAllocT2Node); } |
| 9862 | static const Pipeline *pipeline_class(); |
| 9863 | virtual const Pipeline *pipeline() const; |
| 9864 | virtual const MachOper *memory_operand() const; |
| 9865 | #ifndef PRODUCT |
| 9866 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9867 | virtual const char *Name() const { return "prefetchAllocT2";} |
| 9868 | #endif |
| 9869 | }; |
| 9870 | |
| 9871 | class storeBNode : public MachTypeNode { |
| 9872 | private: |
| 9873 | MachOper *_opnd_array[3]; |
| 9874 | public: |
| 9875 | MachOper *opnd_array(uint operand_index) const { |
| 9876 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9877 | return _opnd_array[operand_index]; |
| 9878 | } |
| 9879 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9880 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9881 | _opnd_array[operand_index] = operand; |
| 9882 | } |
| 9883 | private: |
| 9884 | virtual const RegMask &out_RegMask() const; |
| 9885 | virtual uint rule() const { return storeB_rule; } |
| 9886 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9887 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 9888 | virtual int reloc() const; |
| 9889 | virtual uint oper_input_base() const { return 2; } |
| 9890 | public: |
| 9891 | storeBNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 9892 | virtual uint size_of() const { return sizeof(storeBNode); } |
| 9893 | static const Pipeline *pipeline_class(); |
| 9894 | virtual const Pipeline *pipeline() const; |
| 9895 | virtual const MachOper *memory_operand() const; |
| 9896 | #ifndef PRODUCT |
| 9897 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9898 | virtual const char *Name() const { return "storeB";} |
| 9899 | #endif |
| 9900 | }; |
| 9901 | |
| 9902 | class storeCNode : public MachTypeNode { |
| 9903 | private: |
| 9904 | MachOper *_opnd_array[3]; |
| 9905 | public: |
| 9906 | MachOper *opnd_array(uint operand_index) const { |
| 9907 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9908 | return _opnd_array[operand_index]; |
| 9909 | } |
| 9910 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9911 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9912 | _opnd_array[operand_index] = operand; |
| 9913 | } |
| 9914 | private: |
| 9915 | virtual const RegMask &out_RegMask() const; |
| 9916 | virtual uint rule() const { return storeC_rule; } |
| 9917 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9918 | virtual int ideal_Opcode() const { return Op_StoreC; } |
| 9919 | virtual int reloc() const; |
| 9920 | virtual uint oper_input_base() const { return 2; } |
| 9921 | public: |
| 9922 | storeCNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 9923 | virtual uint size_of() const { return sizeof(storeCNode); } |
| 9924 | static const Pipeline *pipeline_class(); |
| 9925 | virtual const Pipeline *pipeline() const; |
| 9926 | virtual const MachOper *memory_operand() const; |
| 9927 | #ifndef PRODUCT |
| 9928 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9929 | virtual const char *Name() const { return "storeC";} |
| 9930 | #endif |
| 9931 | }; |
| 9932 | |
| 9933 | class storeINode : public MachTypeNode { |
| 9934 | private: |
| 9935 | MachOper *_opnd_array[3]; |
| 9936 | public: |
| 9937 | MachOper *opnd_array(uint operand_index) const { |
| 9938 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9939 | return _opnd_array[operand_index]; |
| 9940 | } |
| 9941 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9942 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9943 | _opnd_array[operand_index] = operand; |
| 9944 | } |
| 9945 | private: |
| 9946 | virtual const RegMask &out_RegMask() const; |
| 9947 | virtual uint rule() const { return storeI_rule; } |
| 9948 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9949 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 9950 | virtual int reloc() const; |
| 9951 | virtual uint oper_input_base() const { return 2; } |
| 9952 | public: |
| 9953 | storeINode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 9954 | virtual uint size_of() const { return sizeof(storeINode); } |
| 9955 | static const Pipeline *pipeline_class(); |
| 9956 | virtual const Pipeline *pipeline() const; |
| 9957 | virtual const MachOper *memory_operand() const; |
| 9958 | #ifndef PRODUCT |
| 9959 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9960 | virtual const char *Name() const { return "storeI";} |
| 9961 | #endif |
| 9962 | }; |
| 9963 | |
| 9964 | class storeLNode : public MachTypeNode { |
| 9965 | private: |
| 9966 | MachOper *_opnd_array[3]; |
| 9967 | public: |
| 9968 | MachOper *opnd_array(uint operand_index) const { |
| 9969 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9970 | return _opnd_array[operand_index]; |
| 9971 | } |
| 9972 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 9973 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 9974 | _opnd_array[operand_index] = operand; |
| 9975 | } |
| 9976 | private: |
| 9977 | virtual const RegMask &out_RegMask() const; |
| 9978 | virtual uint rule() const { return storeL_rule; } |
| 9979 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 9980 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 9981 | virtual int reloc() const; |
| 9982 | virtual uint oper_input_base() const { return 2; } |
| 9983 | public: |
| 9984 | storeLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 9985 | virtual uint size_of() const { return sizeof(storeLNode); } |
| 9986 | static const Pipeline *pipeline_class(); |
| 9987 | virtual const Pipeline *pipeline() const; |
| 9988 | virtual const MachOper *memory_operand() const; |
| 9989 | #ifndef PRODUCT |
| 9990 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 9991 | virtual const char *Name() const { return "storeL";} |
| 9992 | #endif |
| 9993 | }; |
| 9994 | |
| 9995 | class storePNode : public MachTypeNode { |
| 9996 | private: |
| 9997 | MachOper *_opnd_array[3]; |
| 9998 | public: |
| 9999 | MachOper *opnd_array(uint operand_index) const { |
| 10000 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10001 | return _opnd_array[operand_index]; |
| 10002 | } |
| 10003 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10005 | _opnd_array[operand_index] = operand; |
| 10006 | } |
| 10007 | private: |
| 10008 | virtual const RegMask &out_RegMask() const; |
| 10009 | virtual uint rule() const { return storeP_rule; } |
| 10010 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10011 | virtual int ideal_Opcode() const { return Op_StoreP; } |
| 10012 | virtual int reloc() const; |
| 10013 | virtual uint oper_input_base() const { return 2; } |
| 10014 | public: |
| 10015 | storePNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10016 | virtual uint size_of() const { return sizeof(storePNode); } |
| 10017 | static const Pipeline *pipeline_class(); |
| 10018 | virtual const Pipeline *pipeline() const; |
| 10019 | virtual const MachOper *memory_operand() const; |
| 10020 | #ifndef PRODUCT |
| 10021 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10022 | virtual const char *Name() const { return "storeP";} |
| 10023 | #endif |
| 10024 | }; |
| 10025 | |
| 10026 | class storeImmP0Node : public MachTypeNode { |
| 10027 | private: |
| 10028 | MachOper *_opnd_array[3]; |
| 10029 | public: |
| 10030 | MachOper *opnd_array(uint operand_index) const { |
| 10031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10032 | return _opnd_array[operand_index]; |
| 10033 | } |
| 10034 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10036 | _opnd_array[operand_index] = operand; |
| 10037 | } |
| 10038 | private: |
| 10039 | virtual const RegMask &out_RegMask() const; |
| 10040 | virtual uint rule() const { return storeImmP0_rule; } |
| 10041 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10042 | virtual int ideal_Opcode() const { return Op_StoreP; } |
| 10043 | virtual int reloc() const; |
| 10044 | virtual uint oper_input_base() const { return 2; } |
| 10045 | public: |
| 10046 | storeImmP0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10047 | virtual uint size_of() const { return sizeof(storeImmP0Node); } |
| 10048 | static const Pipeline *pipeline_class(); |
| 10049 | virtual const Pipeline *pipeline() const; |
| 10050 | virtual const MachOper *memory_operand() const; |
| 10051 | #ifndef PRODUCT |
| 10052 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10053 | virtual const char *Name() const { return "storeImmP0";} |
| 10054 | #endif |
| 10055 | }; |
| 10056 | |
| 10057 | class storeImmPNode : public MachTypeNode { |
| 10058 | private: |
| 10059 | MachOper *_opnd_array[3]; |
| 10060 | public: |
| 10061 | MachOper *opnd_array(uint operand_index) const { |
| 10062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10063 | return _opnd_array[operand_index]; |
| 10064 | } |
| 10065 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10066 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10067 | _opnd_array[operand_index] = operand; |
| 10068 | } |
| 10069 | private: |
| 10070 | virtual const RegMask &out_RegMask() const; |
| 10071 | virtual uint rule() const { return storeImmP_rule; } |
| 10072 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10073 | virtual int ideal_Opcode() const { return Op_StoreP; } |
| 10074 | virtual int reloc() const; |
| 10075 | virtual uint oper_input_base() const { return 2; } |
| 10076 | public: |
| 10077 | storeImmPNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10078 | virtual uint size_of() const { return sizeof(storeImmPNode); } |
| 10079 | static const Pipeline *pipeline_class(); |
| 10080 | virtual const Pipeline *pipeline() const; |
| 10081 | virtual const MachOper *memory_operand() const; |
| 10082 | #ifndef PRODUCT |
| 10083 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10084 | virtual const char *Name() const { return "storeImmP";} |
| 10085 | #endif |
| 10086 | }; |
| 10087 | |
| 10088 | class storeNNode : public MachTypeNode { |
| 10089 | private: |
| 10090 | MachOper *_opnd_array[3]; |
| 10091 | public: |
| 10092 | MachOper *opnd_array(uint operand_index) const { |
| 10093 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10094 | return _opnd_array[operand_index]; |
| 10095 | } |
| 10096 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10097 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10098 | _opnd_array[operand_index] = operand; |
| 10099 | } |
| 10100 | private: |
| 10101 | virtual const RegMask &out_RegMask() const; |
| 10102 | virtual uint rule() const { return storeN_rule; } |
| 10103 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10104 | virtual int ideal_Opcode() const { return Op_StoreN; } |
| 10105 | virtual int reloc() const; |
| 10106 | virtual uint oper_input_base() const { return 2; } |
| 10107 | public: |
| 10108 | storeNNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10109 | virtual uint size_of() const { return sizeof(storeNNode); } |
| 10110 | static const Pipeline *pipeline_class(); |
| 10111 | virtual const Pipeline *pipeline() const; |
| 10112 | virtual const MachOper *memory_operand() const; |
| 10113 | #ifndef PRODUCT |
| 10114 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10115 | virtual const char *Name() const { return "storeN";} |
| 10116 | #endif |
| 10117 | }; |
| 10118 | |
| 10119 | class storeNKlassNode : public MachTypeNode { |
| 10120 | private: |
| 10121 | MachOper *_opnd_array[3]; |
| 10122 | public: |
| 10123 | MachOper *opnd_array(uint operand_index) const { |
| 10124 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10125 | return _opnd_array[operand_index]; |
| 10126 | } |
| 10127 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10128 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10129 | _opnd_array[operand_index] = operand; |
| 10130 | } |
| 10131 | private: |
| 10132 | virtual const RegMask &out_RegMask() const; |
| 10133 | virtual uint rule() const { return storeNKlass_rule; } |
| 10134 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10135 | virtual int ideal_Opcode() const { return Op_StoreNKlass; } |
| 10136 | virtual int reloc() const; |
| 10137 | virtual uint oper_input_base() const { return 2; } |
| 10138 | public: |
| 10139 | storeNKlassNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10140 | virtual uint size_of() const { return sizeof(storeNKlassNode); } |
| 10141 | static const Pipeline *pipeline_class(); |
| 10142 | virtual const Pipeline *pipeline() const; |
| 10143 | virtual const MachOper *memory_operand() const; |
| 10144 | #ifndef PRODUCT |
| 10145 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10146 | virtual const char *Name() const { return "storeNKlass";} |
| 10147 | #endif |
| 10148 | }; |
| 10149 | |
| 10150 | class storeImmN0Node : public MachTypeNode { |
| 10151 | private: |
| 10152 | MachOper *_opnd_array[3]; |
| 10153 | public: |
| 10154 | MachOper *opnd_array(uint operand_index) const { |
| 10155 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10156 | return _opnd_array[operand_index]; |
| 10157 | } |
| 10158 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10159 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10160 | _opnd_array[operand_index] = operand; |
| 10161 | } |
| 10162 | private: |
| 10163 | virtual const RegMask &out_RegMask() const; |
| 10164 | virtual uint rule() const { return storeImmN0_rule; } |
| 10165 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10166 | virtual int ideal_Opcode() const { return Op_StoreN; } |
| 10167 | virtual int reloc() const; |
| 10168 | virtual uint oper_input_base() const { return 2; } |
| 10169 | public: |
| 10170 | storeImmN0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10171 | virtual uint size_of() const { return sizeof(storeImmN0Node); } |
| 10172 | static const Pipeline *pipeline_class(); |
| 10173 | virtual const Pipeline *pipeline() const; |
| 10174 | virtual const MachOper *memory_operand() const; |
| 10175 | #ifndef PRODUCT |
| 10176 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10177 | virtual const char *Name() const { return "storeImmN0";} |
| 10178 | #endif |
| 10179 | }; |
| 10180 | |
| 10181 | class storeImmNNode : public MachTypeNode { |
| 10182 | private: |
| 10183 | MachOper *_opnd_array[3]; |
| 10184 | public: |
| 10185 | MachOper *opnd_array(uint operand_index) const { |
| 10186 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10187 | return _opnd_array[operand_index]; |
| 10188 | } |
| 10189 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10190 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10191 | _opnd_array[operand_index] = operand; |
| 10192 | } |
| 10193 | private: |
| 10194 | virtual const RegMask &out_RegMask() const; |
| 10195 | virtual uint rule() const { return storeImmN_rule; } |
| 10196 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10197 | virtual int ideal_Opcode() const { return Op_StoreN; } |
| 10198 | virtual int reloc() const; |
| 10199 | virtual uint oper_input_base() const { return 2; } |
| 10200 | public: |
| 10201 | storeImmNNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10202 | virtual uint size_of() const { return sizeof(storeImmNNode); } |
| 10203 | static const Pipeline *pipeline_class(); |
| 10204 | virtual const Pipeline *pipeline() const; |
| 10205 | virtual const MachOper *memory_operand() const; |
| 10206 | #ifndef PRODUCT |
| 10207 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10208 | virtual const char *Name() const { return "storeImmN";} |
| 10209 | #endif |
| 10210 | }; |
| 10211 | |
| 10212 | class storeImmNKlassNode : public MachTypeNode { |
| 10213 | private: |
| 10214 | MachOper *_opnd_array[3]; |
| 10215 | public: |
| 10216 | MachOper *opnd_array(uint operand_index) const { |
| 10217 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10218 | return _opnd_array[operand_index]; |
| 10219 | } |
| 10220 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10221 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10222 | _opnd_array[operand_index] = operand; |
| 10223 | } |
| 10224 | private: |
| 10225 | virtual const RegMask &out_RegMask() const; |
| 10226 | virtual uint rule() const { return storeImmNKlass_rule; } |
| 10227 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10228 | virtual int ideal_Opcode() const { return Op_StoreNKlass; } |
| 10229 | virtual int reloc() const; |
| 10230 | virtual uint oper_input_base() const { return 2; } |
| 10231 | public: |
| 10232 | storeImmNKlassNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10233 | virtual uint size_of() const { return sizeof(storeImmNKlassNode); } |
| 10234 | static const Pipeline *pipeline_class(); |
| 10235 | virtual const Pipeline *pipeline() const; |
| 10236 | virtual const MachOper *memory_operand() const; |
| 10237 | #ifndef PRODUCT |
| 10238 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10239 | virtual const char *Name() const { return "storeImmNKlass";} |
| 10240 | #endif |
| 10241 | }; |
| 10242 | |
| 10243 | class storeImmI0Node : public MachTypeNode { |
| 10244 | private: |
| 10245 | MachOper *_opnd_array[3]; |
| 10246 | public: |
| 10247 | MachOper *opnd_array(uint operand_index) const { |
| 10248 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10249 | return _opnd_array[operand_index]; |
| 10250 | } |
| 10251 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10252 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10253 | _opnd_array[operand_index] = operand; |
| 10254 | } |
| 10255 | private: |
| 10256 | virtual const RegMask &out_RegMask() const; |
| 10257 | virtual uint rule() const { return storeImmI0_rule; } |
| 10258 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10259 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 10260 | virtual int reloc() const; |
| 10261 | virtual uint oper_input_base() const { return 2; } |
| 10262 | public: |
| 10263 | storeImmI0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10264 | virtual uint size_of() const { return sizeof(storeImmI0Node); } |
| 10265 | static const Pipeline *pipeline_class(); |
| 10266 | virtual const Pipeline *pipeline() const; |
| 10267 | virtual const MachOper *memory_operand() const; |
| 10268 | #ifndef PRODUCT |
| 10269 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10270 | virtual const char *Name() const { return "storeImmI0";} |
| 10271 | #endif |
| 10272 | }; |
| 10273 | |
| 10274 | class storeImmINode : public MachTypeNode { |
| 10275 | private: |
| 10276 | MachOper *_opnd_array[3]; |
| 10277 | public: |
| 10278 | MachOper *opnd_array(uint operand_index) const { |
| 10279 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10280 | return _opnd_array[operand_index]; |
| 10281 | } |
| 10282 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10283 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10284 | _opnd_array[operand_index] = operand; |
| 10285 | } |
| 10286 | private: |
| 10287 | virtual const RegMask &out_RegMask() const; |
| 10288 | virtual uint rule() const { return storeImmI_rule; } |
| 10289 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10290 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 10291 | virtual int reloc() const; |
| 10292 | virtual uint oper_input_base() const { return 2; } |
| 10293 | public: |
| 10294 | storeImmINode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10295 | virtual uint size_of() const { return sizeof(storeImmINode); } |
| 10296 | static const Pipeline *pipeline_class(); |
| 10297 | virtual const Pipeline *pipeline() const; |
| 10298 | virtual const MachOper *memory_operand() const; |
| 10299 | #ifndef PRODUCT |
| 10300 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10301 | virtual const char *Name() const { return "storeImmI";} |
| 10302 | #endif |
| 10303 | }; |
| 10304 | |
| 10305 | class storeImmL0Node : public MachTypeNode { |
| 10306 | private: |
| 10307 | MachOper *_opnd_array[3]; |
| 10308 | public: |
| 10309 | MachOper *opnd_array(uint operand_index) const { |
| 10310 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10311 | return _opnd_array[operand_index]; |
| 10312 | } |
| 10313 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10314 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10315 | _opnd_array[operand_index] = operand; |
| 10316 | } |
| 10317 | private: |
| 10318 | virtual const RegMask &out_RegMask() const; |
| 10319 | virtual uint rule() const { return storeImmL0_rule; } |
| 10320 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10321 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 10322 | virtual int reloc() const; |
| 10323 | virtual uint oper_input_base() const { return 2; } |
| 10324 | public: |
| 10325 | storeImmL0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10326 | virtual uint size_of() const { return sizeof(storeImmL0Node); } |
| 10327 | static const Pipeline *pipeline_class(); |
| 10328 | virtual const Pipeline *pipeline() const; |
| 10329 | virtual const MachOper *memory_operand() const; |
| 10330 | #ifndef PRODUCT |
| 10331 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10332 | virtual const char *Name() const { return "storeImmL0";} |
| 10333 | #endif |
| 10334 | }; |
| 10335 | |
| 10336 | class storeImmLNode : public MachTypeNode { |
| 10337 | private: |
| 10338 | MachOper *_opnd_array[3]; |
| 10339 | public: |
| 10340 | MachOper *opnd_array(uint operand_index) const { |
| 10341 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10342 | return _opnd_array[operand_index]; |
| 10343 | } |
| 10344 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10345 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10346 | _opnd_array[operand_index] = operand; |
| 10347 | } |
| 10348 | private: |
| 10349 | virtual const RegMask &out_RegMask() const; |
| 10350 | virtual uint rule() const { return storeImmL_rule; } |
| 10351 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10352 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 10353 | virtual int reloc() const; |
| 10354 | virtual uint oper_input_base() const { return 2; } |
| 10355 | public: |
| 10356 | storeImmLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10357 | virtual uint size_of() const { return sizeof(storeImmLNode); } |
| 10358 | static const Pipeline *pipeline_class(); |
| 10359 | virtual const Pipeline *pipeline() const; |
| 10360 | virtual const MachOper *memory_operand() const; |
| 10361 | #ifndef PRODUCT |
| 10362 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10363 | virtual const char *Name() const { return "storeImmL";} |
| 10364 | #endif |
| 10365 | }; |
| 10366 | |
| 10367 | class storeImmC0Node : public MachTypeNode { |
| 10368 | private: |
| 10369 | MachOper *_opnd_array[3]; |
| 10370 | public: |
| 10371 | MachOper *opnd_array(uint operand_index) const { |
| 10372 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10373 | return _opnd_array[operand_index]; |
| 10374 | } |
| 10375 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10377 | _opnd_array[operand_index] = operand; |
| 10378 | } |
| 10379 | private: |
| 10380 | virtual const RegMask &out_RegMask() const; |
| 10381 | virtual uint rule() const { return storeImmC0_rule; } |
| 10382 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10383 | virtual int ideal_Opcode() const { return Op_StoreC; } |
| 10384 | virtual int reloc() const; |
| 10385 | virtual uint oper_input_base() const { return 2; } |
| 10386 | public: |
| 10387 | storeImmC0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10388 | virtual uint size_of() const { return sizeof(storeImmC0Node); } |
| 10389 | static const Pipeline *pipeline_class(); |
| 10390 | virtual const Pipeline *pipeline() const; |
| 10391 | virtual const MachOper *memory_operand() const; |
| 10392 | #ifndef PRODUCT |
| 10393 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10394 | virtual const char *Name() const { return "storeImmC0";} |
| 10395 | #endif |
| 10396 | }; |
| 10397 | |
| 10398 | class storeImmI16Node : public MachTypeNode { |
| 10399 | private: |
| 10400 | MachOper *_opnd_array[3]; |
| 10401 | public: |
| 10402 | MachOper *opnd_array(uint operand_index) const { |
| 10403 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10404 | return _opnd_array[operand_index]; |
| 10405 | } |
| 10406 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10408 | _opnd_array[operand_index] = operand; |
| 10409 | } |
| 10410 | private: |
| 10411 | virtual const RegMask &out_RegMask() const; |
| 10412 | virtual uint rule() const { return storeImmI16_rule; } |
| 10413 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10414 | virtual int ideal_Opcode() const { return Op_StoreC; } |
| 10415 | virtual int reloc() const; |
| 10416 | virtual uint oper_input_base() const { return 2; } |
| 10417 | public: |
| 10418 | storeImmI16Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10419 | virtual uint size_of() const { return sizeof(storeImmI16Node); } |
| 10420 | static const Pipeline *pipeline_class(); |
| 10421 | virtual const Pipeline *pipeline() const; |
| 10422 | virtual const MachOper *memory_operand() const; |
| 10423 | #ifndef PRODUCT |
| 10424 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10425 | virtual const char *Name() const { return "storeImmI16";} |
| 10426 | #endif |
| 10427 | }; |
| 10428 | |
| 10429 | class storeImmB0Node : public MachTypeNode { |
| 10430 | private: |
| 10431 | MachOper *_opnd_array[3]; |
| 10432 | public: |
| 10433 | MachOper *opnd_array(uint operand_index) const { |
| 10434 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10435 | return _opnd_array[operand_index]; |
| 10436 | } |
| 10437 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10438 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10439 | _opnd_array[operand_index] = operand; |
| 10440 | } |
| 10441 | private: |
| 10442 | virtual const RegMask &out_RegMask() const; |
| 10443 | virtual uint rule() const { return storeImmB0_rule; } |
| 10444 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10445 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 10446 | virtual int reloc() const; |
| 10447 | virtual uint oper_input_base() const { return 2; } |
| 10448 | public: |
| 10449 | storeImmB0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10450 | virtual uint size_of() const { return sizeof(storeImmB0Node); } |
| 10451 | static const Pipeline *pipeline_class(); |
| 10452 | virtual const Pipeline *pipeline() const; |
| 10453 | virtual const MachOper *memory_operand() const; |
| 10454 | #ifndef PRODUCT |
| 10455 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10456 | virtual const char *Name() const { return "storeImmB0";} |
| 10457 | #endif |
| 10458 | }; |
| 10459 | |
| 10460 | class storeImmBNode : public MachTypeNode { |
| 10461 | private: |
| 10462 | MachOper *_opnd_array[3]; |
| 10463 | public: |
| 10464 | MachOper *opnd_array(uint operand_index) const { |
| 10465 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10466 | return _opnd_array[operand_index]; |
| 10467 | } |
| 10468 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10469 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10470 | _opnd_array[operand_index] = operand; |
| 10471 | } |
| 10472 | private: |
| 10473 | virtual const RegMask &out_RegMask() const; |
| 10474 | virtual uint rule() const { return storeImmB_rule; } |
| 10475 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10476 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 10477 | virtual int reloc() const; |
| 10478 | virtual uint oper_input_base() const { return 2; } |
| 10479 | public: |
| 10480 | storeImmBNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10481 | virtual uint size_of() const { return sizeof(storeImmBNode); } |
| 10482 | static const Pipeline *pipeline_class(); |
| 10483 | virtual const Pipeline *pipeline() const; |
| 10484 | virtual const MachOper *memory_operand() const; |
| 10485 | #ifndef PRODUCT |
| 10486 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10487 | virtual const char *Name() const { return "storeImmB";} |
| 10488 | #endif |
| 10489 | }; |
| 10490 | |
| 10491 | class storeImmCM0_regNode : public MachTypeNode { |
| 10492 | private: |
| 10493 | MachOper *_opnd_array[3]; |
| 10494 | public: |
| 10495 | MachOper *opnd_array(uint operand_index) const { |
| 10496 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10497 | return _opnd_array[operand_index]; |
| 10498 | } |
| 10499 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10500 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10501 | _opnd_array[operand_index] = operand; |
| 10502 | } |
| 10503 | private: |
| 10504 | virtual const RegMask &out_RegMask() const; |
| 10505 | virtual uint rule() const { return storeImmCM0_reg_rule; } |
| 10506 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10507 | virtual int ideal_Opcode() const { return Op_StoreCM; } |
| 10508 | virtual int reloc() const; |
| 10509 | virtual uint oper_input_base() const { return 2; } |
| 10510 | public: |
| 10511 | storeImmCM0_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10512 | virtual uint size_of() const { return sizeof(storeImmCM0_regNode); } |
| 10513 | static const Pipeline *pipeline_class(); |
| 10514 | virtual const Pipeline *pipeline() const; |
| 10515 | virtual const MachOper *memory_operand() const; |
| 10516 | #ifndef PRODUCT |
| 10517 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10518 | virtual const char *Name() const { return "storeImmCM0_reg";} |
| 10519 | #endif |
| 10520 | }; |
| 10521 | |
| 10522 | class storeImmCM0Node : public MachTypeNode { |
| 10523 | private: |
| 10524 | MachOper *_opnd_array[3]; |
| 10525 | public: |
| 10526 | MachOper *opnd_array(uint operand_index) const { |
| 10527 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10528 | return _opnd_array[operand_index]; |
| 10529 | } |
| 10530 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10531 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10532 | _opnd_array[operand_index] = operand; |
| 10533 | } |
| 10534 | private: |
| 10535 | virtual const RegMask &out_RegMask() const; |
| 10536 | virtual uint rule() const { return storeImmCM0_rule; } |
| 10537 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10538 | virtual int ideal_Opcode() const { return Op_StoreCM; } |
| 10539 | virtual int reloc() const; |
| 10540 | virtual uint oper_input_base() const { return 2; } |
| 10541 | public: |
| 10542 | storeImmCM0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10543 | virtual uint size_of() const { return sizeof(storeImmCM0Node); } |
| 10544 | static const Pipeline *pipeline_class(); |
| 10545 | virtual const Pipeline *pipeline() const; |
| 10546 | virtual const MachOper *memory_operand() const; |
| 10547 | #ifndef PRODUCT |
| 10548 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10549 | virtual const char *Name() const { return "storeImmCM0";} |
| 10550 | #endif |
| 10551 | }; |
| 10552 | |
| 10553 | class storeFNode : public MachTypeNode { |
| 10554 | private: |
| 10555 | MachOper *_opnd_array[3]; |
| 10556 | public: |
| 10557 | MachOper *opnd_array(uint operand_index) const { |
| 10558 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10559 | return _opnd_array[operand_index]; |
| 10560 | } |
| 10561 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10562 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10563 | _opnd_array[operand_index] = operand; |
| 10564 | } |
| 10565 | private: |
| 10566 | virtual const RegMask &out_RegMask() const; |
| 10567 | virtual uint rule() const { return storeF_rule; } |
| 10568 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10569 | virtual int ideal_Opcode() const { return Op_StoreF; } |
| 10570 | virtual int reloc() const; |
| 10571 | virtual uint oper_input_base() const { return 2; } |
| 10572 | public: |
| 10573 | storeFNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10574 | virtual uint size_of() const { return sizeof(storeFNode); } |
| 10575 | static const Pipeline *pipeline_class(); |
| 10576 | virtual const Pipeline *pipeline() const; |
| 10577 | virtual const MachOper *memory_operand() const; |
| 10578 | #ifndef PRODUCT |
| 10579 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10580 | virtual const char *Name() const { return "storeF";} |
| 10581 | #endif |
| 10582 | }; |
| 10583 | |
| 10584 | class storeF0Node : public MachTypeNode { |
| 10585 | private: |
| 10586 | MachOper *_opnd_array[3]; |
| 10587 | public: |
| 10588 | MachOper *opnd_array(uint operand_index) const { |
| 10589 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10590 | return _opnd_array[operand_index]; |
| 10591 | } |
| 10592 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10593 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10594 | _opnd_array[operand_index] = operand; |
| 10595 | } |
| 10596 | private: |
| 10597 | virtual const RegMask &out_RegMask() const; |
| 10598 | virtual uint rule() const { return storeF0_rule; } |
| 10599 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10600 | virtual int ideal_Opcode() const { return Op_StoreF; } |
| 10601 | virtual int reloc() const; |
| 10602 | virtual uint oper_input_base() const { return 2; } |
| 10603 | public: |
| 10604 | storeF0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10605 | virtual uint size_of() const { return sizeof(storeF0Node); } |
| 10606 | static const Pipeline *pipeline_class(); |
| 10607 | virtual const Pipeline *pipeline() const; |
| 10608 | virtual const MachOper *memory_operand() const; |
| 10609 | #ifndef PRODUCT |
| 10610 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10611 | virtual const char *Name() const { return "storeF0";} |
| 10612 | #endif |
| 10613 | }; |
| 10614 | |
| 10615 | class storeF_immNode : public MachTypeNode { |
| 10616 | private: |
| 10617 | MachOper *_opnd_array[3]; |
| 10618 | public: |
| 10619 | MachOper *opnd_array(uint operand_index) const { |
| 10620 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10621 | return _opnd_array[operand_index]; |
| 10622 | } |
| 10623 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10624 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10625 | _opnd_array[operand_index] = operand; |
| 10626 | } |
| 10627 | private: |
| 10628 | virtual const RegMask &out_RegMask() const; |
| 10629 | virtual uint rule() const { return storeF_imm_rule; } |
| 10630 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10631 | virtual int ideal_Opcode() const { return Op_StoreF; } |
| 10632 | virtual int reloc() const; |
| 10633 | virtual uint oper_input_base() const { return 2; } |
| 10634 | public: |
| 10635 | storeF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10636 | virtual uint size_of() const { return sizeof(storeF_immNode); } |
| 10637 | static const Pipeline *pipeline_class(); |
| 10638 | virtual const Pipeline *pipeline() const; |
| 10639 | virtual const MachOper *memory_operand() const; |
| 10640 | #ifndef PRODUCT |
| 10641 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10642 | virtual const char *Name() const { return "storeF_imm";} |
| 10643 | #endif |
| 10644 | }; |
| 10645 | |
| 10646 | class storeDNode : public MachTypeNode { |
| 10647 | private: |
| 10648 | MachOper *_opnd_array[3]; |
| 10649 | public: |
| 10650 | MachOper *opnd_array(uint operand_index) const { |
| 10651 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10652 | return _opnd_array[operand_index]; |
| 10653 | } |
| 10654 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10655 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10656 | _opnd_array[operand_index] = operand; |
| 10657 | } |
| 10658 | private: |
| 10659 | virtual const RegMask &out_RegMask() const; |
| 10660 | virtual uint rule() const { return storeD_rule; } |
| 10661 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10662 | virtual int ideal_Opcode() const { return Op_StoreD; } |
| 10663 | virtual int reloc() const; |
| 10664 | virtual uint oper_input_base() const { return 2; } |
| 10665 | public: |
| 10666 | storeDNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10667 | virtual uint size_of() const { return sizeof(storeDNode); } |
| 10668 | static const Pipeline *pipeline_class(); |
| 10669 | virtual const Pipeline *pipeline() const; |
| 10670 | virtual const MachOper *memory_operand() const; |
| 10671 | #ifndef PRODUCT |
| 10672 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10673 | virtual const char *Name() const { return "storeD";} |
| 10674 | #endif |
| 10675 | }; |
| 10676 | |
| 10677 | class storeD0_immNode : public MachTypeNode { |
| 10678 | private: |
| 10679 | MachOper *_opnd_array[3]; |
| 10680 | public: |
| 10681 | MachOper *opnd_array(uint operand_index) const { |
| 10682 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10683 | return _opnd_array[operand_index]; |
| 10684 | } |
| 10685 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10686 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10687 | _opnd_array[operand_index] = operand; |
| 10688 | } |
| 10689 | private: |
| 10690 | virtual const RegMask &out_RegMask() const; |
| 10691 | virtual uint rule() const { return storeD0_imm_rule; } |
| 10692 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10693 | virtual int ideal_Opcode() const { return Op_StoreD; } |
| 10694 | virtual int reloc() const; |
| 10695 | virtual uint oper_input_base() const { return 2; } |
| 10696 | public: |
| 10697 | storeD0_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10698 | virtual uint size_of() const { return sizeof(storeD0_immNode); } |
| 10699 | static const Pipeline *pipeline_class(); |
| 10700 | virtual const Pipeline *pipeline() const; |
| 10701 | virtual const MachOper *memory_operand() const; |
| 10702 | #ifndef PRODUCT |
| 10703 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10704 | virtual const char *Name() const { return "storeD0_imm";} |
| 10705 | #endif |
| 10706 | }; |
| 10707 | |
| 10708 | class storeD0Node : public MachTypeNode { |
| 10709 | private: |
| 10710 | MachOper *_opnd_array[3]; |
| 10711 | public: |
| 10712 | MachOper *opnd_array(uint operand_index) const { |
| 10713 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10714 | return _opnd_array[operand_index]; |
| 10715 | } |
| 10716 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10717 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10718 | _opnd_array[operand_index] = operand; |
| 10719 | } |
| 10720 | private: |
| 10721 | virtual const RegMask &out_RegMask() const; |
| 10722 | virtual uint rule() const { return storeD0_rule; } |
| 10723 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10724 | virtual int ideal_Opcode() const { return Op_StoreD; } |
| 10725 | virtual int reloc() const; |
| 10726 | virtual uint oper_input_base() const { return 2; } |
| 10727 | public: |
| 10728 | storeD0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 10729 | virtual uint size_of() const { return sizeof(storeD0Node); } |
| 10730 | static const Pipeline *pipeline_class(); |
| 10731 | virtual const Pipeline *pipeline() const; |
| 10732 | virtual const MachOper *memory_operand() const; |
| 10733 | #ifndef PRODUCT |
| 10734 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10735 | virtual const char *Name() const { return "storeD0";} |
| 10736 | #endif |
| 10737 | }; |
| 10738 | |
| 10739 | class storeSSINode : public MachNode { |
| 10740 | private: |
| 10741 | MachOper *_opnd_array[2]; |
| 10742 | public: |
| 10743 | MachOper *opnd_array(uint operand_index) const { |
| 10744 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10745 | return _opnd_array[operand_index]; |
| 10746 | } |
| 10747 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10748 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10749 | _opnd_array[operand_index] = operand; |
| 10750 | } |
| 10751 | private: |
| 10752 | virtual const RegMask &out_RegMask() const; |
| 10753 | virtual uint rule() const { return storeSSI_rule; } |
| 10754 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10755 | virtual int ideal_Opcode() const { return Op_RegI; } |
| 10756 | public: |
| 10757 | storeSSINode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Copy); } |
| 10758 | virtual uint size_of() const { return sizeof(storeSSINode); } |
| 10759 | static const Pipeline *pipeline_class(); |
| 10760 | virtual const Pipeline *pipeline() const; |
| 10761 | #ifndef PRODUCT |
| 10762 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10763 | virtual const char *Name() const { return "storeSSI";} |
| 10764 | #endif |
| 10765 | }; |
| 10766 | |
| 10767 | class storeSSLNode : public MachNode { |
| 10768 | private: |
| 10769 | MachOper *_opnd_array[2]; |
| 10770 | public: |
| 10771 | MachOper *opnd_array(uint operand_index) const { |
| 10772 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10773 | return _opnd_array[operand_index]; |
| 10774 | } |
| 10775 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10776 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10777 | _opnd_array[operand_index] = operand; |
| 10778 | } |
| 10779 | private: |
| 10780 | virtual const RegMask &out_RegMask() const; |
| 10781 | virtual uint rule() const { return storeSSL_rule; } |
| 10782 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10783 | virtual int ideal_Opcode() const { return Op_RegL; } |
| 10784 | public: |
| 10785 | storeSSLNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Copy); } |
| 10786 | virtual uint size_of() const { return sizeof(storeSSLNode); } |
| 10787 | static const Pipeline *pipeline_class(); |
| 10788 | virtual const Pipeline *pipeline() const; |
| 10789 | #ifndef PRODUCT |
| 10790 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10791 | virtual const char *Name() const { return "storeSSL";} |
| 10792 | #endif |
| 10793 | }; |
| 10794 | |
| 10795 | class storeSSPNode : public MachNode { |
| 10796 | private: |
| 10797 | MachOper *_opnd_array[2]; |
| 10798 | public: |
| 10799 | MachOper *opnd_array(uint operand_index) const { |
| 10800 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10801 | return _opnd_array[operand_index]; |
| 10802 | } |
| 10803 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10804 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10805 | _opnd_array[operand_index] = operand; |
| 10806 | } |
| 10807 | private: |
| 10808 | virtual const RegMask &out_RegMask() const; |
| 10809 | virtual uint rule() const { return storeSSP_rule; } |
| 10810 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10811 | virtual int ideal_Opcode() const { return Op_RegP; } |
| 10812 | public: |
| 10813 | storeSSPNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Copy); } |
| 10814 | virtual uint size_of() const { return sizeof(storeSSPNode); } |
| 10815 | static const Pipeline *pipeline_class(); |
| 10816 | virtual const Pipeline *pipeline() const; |
| 10817 | const Type *bottom_type() const { return in(1)->bottom_type(); } // Copy? |
| 10818 | #ifndef PRODUCT |
| 10819 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10820 | virtual const char *Name() const { return "storeSSP";} |
| 10821 | #endif |
| 10822 | }; |
| 10823 | |
| 10824 | class storeSSFNode : public MachNode { |
| 10825 | private: |
| 10826 | MachOper *_opnd_array[2]; |
| 10827 | public: |
| 10828 | MachOper *opnd_array(uint operand_index) const { |
| 10829 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10830 | return _opnd_array[operand_index]; |
| 10831 | } |
| 10832 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10833 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10834 | _opnd_array[operand_index] = operand; |
| 10835 | } |
| 10836 | private: |
| 10837 | virtual const RegMask &out_RegMask() const; |
| 10838 | virtual uint rule() const { return storeSSF_rule; } |
| 10839 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10840 | virtual int ideal_Opcode() const { return Op_RegF; } |
| 10841 | public: |
| 10842 | storeSSFNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Copy); } |
| 10843 | virtual uint size_of() const { return sizeof(storeSSFNode); } |
| 10844 | static const Pipeline *pipeline_class(); |
| 10845 | virtual const Pipeline *pipeline() const; |
| 10846 | #ifndef PRODUCT |
| 10847 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10848 | virtual const char *Name() const { return "storeSSF";} |
| 10849 | #endif |
| 10850 | }; |
| 10851 | |
| 10852 | class storeSSDNode : public MachNode { |
| 10853 | private: |
| 10854 | MachOper *_opnd_array[2]; |
| 10855 | public: |
| 10856 | MachOper *opnd_array(uint operand_index) const { |
| 10857 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10858 | return _opnd_array[operand_index]; |
| 10859 | } |
| 10860 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10862 | _opnd_array[operand_index] = operand; |
| 10863 | } |
| 10864 | private: |
| 10865 | virtual const RegMask &out_RegMask() const; |
| 10866 | virtual uint rule() const { return storeSSD_rule; } |
| 10867 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10868 | virtual int ideal_Opcode() const { return Op_RegD; } |
| 10869 | public: |
| 10870 | storeSSDNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_Copy); } |
| 10871 | virtual uint size_of() const { return sizeof(storeSSDNode); } |
| 10872 | static const Pipeline *pipeline_class(); |
| 10873 | virtual const Pipeline *pipeline() const; |
| 10874 | #ifndef PRODUCT |
| 10875 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10876 | virtual const char *Name() const { return "storeSSD";} |
| 10877 | #endif |
| 10878 | }; |
| 10879 | |
| 10880 | class bytes_reverse_intNode : public MachNode { |
| 10881 | private: |
| 10882 | MachOper *_opnd_array[2]; |
| 10883 | public: |
| 10884 | MachOper *opnd_array(uint operand_index) const { |
| 10885 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10886 | return _opnd_array[operand_index]; |
| 10887 | } |
| 10888 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10889 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10890 | _opnd_array[operand_index] = operand; |
| 10891 | } |
| 10892 | private: |
| 10893 | virtual const RegMask &out_RegMask() const; |
| 10894 | virtual uint rule() const { return bytes_reverse_int_rule; } |
| 10895 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10896 | virtual int ideal_Opcode() const { return Op_ReverseBytesI; } |
| 10897 | virtual uint two_adr() const { return oper_input_base(); } |
| 10898 | public: |
| 10899 | bytes_reverse_intNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 10900 | virtual uint size_of() const { return sizeof(bytes_reverse_intNode); } |
| 10901 | static const Pipeline *pipeline_class(); |
| 10902 | virtual const Pipeline *pipeline() const; |
| 10903 | #ifndef PRODUCT |
| 10904 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10905 | virtual const char *Name() const { return "bytes_reverse_int";} |
| 10906 | #endif |
| 10907 | }; |
| 10908 | |
| 10909 | class bytes_reverse_longNode : public MachNode { |
| 10910 | private: |
| 10911 | MachOper *_opnd_array[2]; |
| 10912 | public: |
| 10913 | MachOper *opnd_array(uint operand_index) const { |
| 10914 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10915 | return _opnd_array[operand_index]; |
| 10916 | } |
| 10917 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10918 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10919 | _opnd_array[operand_index] = operand; |
| 10920 | } |
| 10921 | private: |
| 10922 | virtual const RegMask &out_RegMask() const; |
| 10923 | virtual uint rule() const { return bytes_reverse_long_rule; } |
| 10924 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10925 | virtual int ideal_Opcode() const { return Op_ReverseBytesL; } |
| 10926 | virtual uint two_adr() const { return oper_input_base(); } |
| 10927 | public: |
| 10928 | bytes_reverse_longNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 10929 | virtual uint size_of() const { return sizeof(bytes_reverse_longNode); } |
| 10930 | static const Pipeline *pipeline_class(); |
| 10931 | virtual const Pipeline *pipeline() const; |
| 10932 | #ifndef PRODUCT |
| 10933 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10934 | virtual const char *Name() const { return "bytes_reverse_long";} |
| 10935 | #endif |
| 10936 | }; |
| 10937 | |
| 10938 | class bytes_reverse_unsigned_shortNode : public MachNode { |
| 10939 | private: |
| 10940 | MachOper *_opnd_array[2]; |
| 10941 | public: |
| 10942 | MachOper *opnd_array(uint operand_index) const { |
| 10943 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10944 | return _opnd_array[operand_index]; |
| 10945 | } |
| 10946 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10947 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10948 | _opnd_array[operand_index] = operand; |
| 10949 | } |
| 10950 | private: |
| 10951 | virtual const RegMask &out_RegMask() const; |
| 10952 | virtual uint rule() const { return bytes_reverse_unsigned_short_rule; } |
| 10953 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10954 | virtual int ideal_Opcode() const { return Op_ReverseBytesUS; } |
| 10955 | virtual uint two_adr() const { return oper_input_base(); } |
| 10956 | public: |
| 10957 | bytes_reverse_unsigned_shortNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 10958 | virtual uint size_of() const { return sizeof(bytes_reverse_unsigned_shortNode); } |
| 10959 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 10960 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 10961 | static const Pipeline *pipeline_class(); |
| 10962 | virtual const Pipeline *pipeline() const; |
| 10963 | #ifndef PRODUCT |
| 10964 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10965 | virtual const char *Name() const { return "bytes_reverse_unsigned_short";} |
| 10966 | #endif |
| 10967 | }; |
| 10968 | |
| 10969 | class bytes_reverse_shortNode : public MachNode { |
| 10970 | private: |
| 10971 | MachOper *_opnd_array[2]; |
| 10972 | public: |
| 10973 | MachOper *opnd_array(uint operand_index) const { |
| 10974 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10975 | return _opnd_array[operand_index]; |
| 10976 | } |
| 10977 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 10978 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 10979 | _opnd_array[operand_index] = operand; |
| 10980 | } |
| 10981 | private: |
| 10982 | virtual const RegMask &out_RegMask() const; |
| 10983 | virtual uint rule() const { return bytes_reverse_short_rule; } |
| 10984 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 10985 | virtual int ideal_Opcode() const { return Op_ReverseBytesS; } |
| 10986 | virtual uint two_adr() const { return oper_input_base(); } |
| 10987 | public: |
| 10988 | bytes_reverse_shortNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 10989 | virtual uint size_of() const { return sizeof(bytes_reverse_shortNode); } |
| 10990 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 10991 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 10992 | static const Pipeline *pipeline_class(); |
| 10993 | virtual const Pipeline *pipeline() const; |
| 10994 | #ifndef PRODUCT |
| 10995 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 10996 | virtual const char *Name() const { return "bytes_reverse_short";} |
| 10997 | #endif |
| 10998 | }; |
| 10999 | |
| 11000 | class countLeadingZerosINode : public MachNode { |
| 11001 | private: |
| 11002 | MachOper *_opnd_array[2]; |
| 11003 | public: |
| 11004 | MachOper *opnd_array(uint operand_index) const { |
| 11005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11006 | return _opnd_array[operand_index]; |
| 11007 | } |
| 11008 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11009 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11010 | _opnd_array[operand_index] = operand; |
| 11011 | } |
| 11012 | private: |
| 11013 | virtual const RegMask &out_RegMask() const; |
| 11014 | virtual uint rule() const { return countLeadingZerosI_rule; } |
| 11015 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11016 | virtual int ideal_Opcode() const { return Op_CountLeadingZerosI; } |
| 11017 | public: |
| 11018 | countLeadingZerosINode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11019 | virtual uint size_of() const { return sizeof(countLeadingZerosINode); } |
| 11020 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11021 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11022 | static const Pipeline *pipeline_class(); |
| 11023 | virtual const Pipeline *pipeline() const; |
| 11024 | #ifndef PRODUCT |
| 11025 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11026 | virtual const char *Name() const { return "countLeadingZerosI";} |
| 11027 | #endif |
| 11028 | }; |
| 11029 | |
| 11030 | class countLeadingZerosI_bsrNode : public MachNode { |
| 11031 | private: |
| 11032 | MachOper *_opnd_array[2]; |
| 11033 | public: |
| 11034 | MachOper *opnd_array(uint operand_index) const { |
| 11035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11036 | return _opnd_array[operand_index]; |
| 11037 | } |
| 11038 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11039 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11040 | _opnd_array[operand_index] = operand; |
| 11041 | } |
| 11042 | private: |
| 11043 | virtual const RegMask &out_RegMask() const; |
| 11044 | virtual uint rule() const { return countLeadingZerosI_bsr_rule; } |
| 11045 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11046 | virtual int ideal_Opcode() const { return Op_CountLeadingZerosI; } |
| 11047 | public: |
| 11048 | countLeadingZerosI_bsrNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11049 | virtual uint size_of() const { return sizeof(countLeadingZerosI_bsrNode); } |
| 11050 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11051 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11052 | static const Pipeline *pipeline_class(); |
| 11053 | virtual const Pipeline *pipeline() const; |
| 11054 | #ifndef PRODUCT |
| 11055 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11056 | virtual const char *Name() const { return "countLeadingZerosI_bsr";} |
| 11057 | #endif |
| 11058 | }; |
| 11059 | |
| 11060 | class countLeadingZerosLNode : public MachNode { |
| 11061 | private: |
| 11062 | MachOper *_opnd_array[2]; |
| 11063 | public: |
| 11064 | MachOper *opnd_array(uint operand_index) const { |
| 11065 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11066 | return _opnd_array[operand_index]; |
| 11067 | } |
| 11068 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11069 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11070 | _opnd_array[operand_index] = operand; |
| 11071 | } |
| 11072 | private: |
| 11073 | virtual const RegMask &out_RegMask() const; |
| 11074 | virtual uint rule() const { return countLeadingZerosL_rule; } |
| 11075 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11076 | virtual int ideal_Opcode() const { return Op_CountLeadingZerosL; } |
| 11077 | public: |
| 11078 | countLeadingZerosLNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11079 | virtual uint size_of() const { return sizeof(countLeadingZerosLNode); } |
| 11080 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11081 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11082 | static const Pipeline *pipeline_class(); |
| 11083 | virtual const Pipeline *pipeline() const; |
| 11084 | #ifndef PRODUCT |
| 11085 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11086 | virtual const char *Name() const { return "countLeadingZerosL";} |
| 11087 | #endif |
| 11088 | }; |
| 11089 | |
| 11090 | class countLeadingZerosL_bsrNode : public MachNode { |
| 11091 | private: |
| 11092 | MachOper *_opnd_array[2]; |
| 11093 | public: |
| 11094 | MachOper *opnd_array(uint operand_index) const { |
| 11095 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11096 | return _opnd_array[operand_index]; |
| 11097 | } |
| 11098 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11099 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11100 | _opnd_array[operand_index] = operand; |
| 11101 | } |
| 11102 | private: |
| 11103 | virtual const RegMask &out_RegMask() const; |
| 11104 | virtual uint rule() const { return countLeadingZerosL_bsr_rule; } |
| 11105 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11106 | virtual int ideal_Opcode() const { return Op_CountLeadingZerosL; } |
| 11107 | public: |
| 11108 | countLeadingZerosL_bsrNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11109 | virtual uint size_of() const { return sizeof(countLeadingZerosL_bsrNode); } |
| 11110 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11111 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11112 | static const Pipeline *pipeline_class(); |
| 11113 | virtual const Pipeline *pipeline() const; |
| 11114 | #ifndef PRODUCT |
| 11115 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11116 | virtual const char *Name() const { return "countLeadingZerosL_bsr";} |
| 11117 | #endif |
| 11118 | }; |
| 11119 | |
| 11120 | class countTrailingZerosINode : public MachNode { |
| 11121 | private: |
| 11122 | MachOper *_opnd_array[2]; |
| 11123 | public: |
| 11124 | MachOper *opnd_array(uint operand_index) const { |
| 11125 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11126 | return _opnd_array[operand_index]; |
| 11127 | } |
| 11128 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11129 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11130 | _opnd_array[operand_index] = operand; |
| 11131 | } |
| 11132 | private: |
| 11133 | virtual const RegMask &out_RegMask() const; |
| 11134 | virtual uint rule() const { return countTrailingZerosI_rule; } |
| 11135 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11136 | virtual int ideal_Opcode() const { return Op_CountTrailingZerosI; } |
| 11137 | public: |
| 11138 | countTrailingZerosINode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11139 | virtual uint size_of() const { return sizeof(countTrailingZerosINode); } |
| 11140 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11141 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11142 | static const Pipeline *pipeline_class(); |
| 11143 | virtual const Pipeline *pipeline() const; |
| 11144 | #ifndef PRODUCT |
| 11145 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11146 | virtual const char *Name() const { return "countTrailingZerosI";} |
| 11147 | #endif |
| 11148 | }; |
| 11149 | |
| 11150 | class countTrailingZerosI_bsfNode : public MachNode { |
| 11151 | private: |
| 11152 | MachOper *_opnd_array[2]; |
| 11153 | public: |
| 11154 | MachOper *opnd_array(uint operand_index) const { |
| 11155 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11156 | return _opnd_array[operand_index]; |
| 11157 | } |
| 11158 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11159 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11160 | _opnd_array[operand_index] = operand; |
| 11161 | } |
| 11162 | private: |
| 11163 | virtual const RegMask &out_RegMask() const; |
| 11164 | virtual uint rule() const { return countTrailingZerosI_bsf_rule; } |
| 11165 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11166 | virtual int ideal_Opcode() const { return Op_CountTrailingZerosI; } |
| 11167 | public: |
| 11168 | countTrailingZerosI_bsfNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11169 | virtual uint size_of() const { return sizeof(countTrailingZerosI_bsfNode); } |
| 11170 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11171 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11172 | static const Pipeline *pipeline_class(); |
| 11173 | virtual const Pipeline *pipeline() const; |
| 11174 | #ifndef PRODUCT |
| 11175 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11176 | virtual const char *Name() const { return "countTrailingZerosI_bsf";} |
| 11177 | #endif |
| 11178 | }; |
| 11179 | |
| 11180 | class countTrailingZerosLNode : public MachNode { |
| 11181 | private: |
| 11182 | MachOper *_opnd_array[2]; |
| 11183 | public: |
| 11184 | MachOper *opnd_array(uint operand_index) const { |
| 11185 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11186 | return _opnd_array[operand_index]; |
| 11187 | } |
| 11188 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11189 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11190 | _opnd_array[operand_index] = operand; |
| 11191 | } |
| 11192 | private: |
| 11193 | virtual const RegMask &out_RegMask() const; |
| 11194 | virtual uint rule() const { return countTrailingZerosL_rule; } |
| 11195 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11196 | virtual int ideal_Opcode() const { return Op_CountTrailingZerosL; } |
| 11197 | public: |
| 11198 | countTrailingZerosLNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11199 | virtual uint size_of() const { return sizeof(countTrailingZerosLNode); } |
| 11200 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11201 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11202 | static const Pipeline *pipeline_class(); |
| 11203 | virtual const Pipeline *pipeline() const; |
| 11204 | #ifndef PRODUCT |
| 11205 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11206 | virtual const char *Name() const { return "countTrailingZerosL";} |
| 11207 | #endif |
| 11208 | }; |
| 11209 | |
| 11210 | class countTrailingZerosL_bsfNode : public MachNode { |
| 11211 | private: |
| 11212 | MachOper *_opnd_array[2]; |
| 11213 | public: |
| 11214 | MachOper *opnd_array(uint operand_index) const { |
| 11215 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11216 | return _opnd_array[operand_index]; |
| 11217 | } |
| 11218 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11219 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11220 | _opnd_array[operand_index] = operand; |
| 11221 | } |
| 11222 | private: |
| 11223 | virtual const RegMask &out_RegMask() const; |
| 11224 | virtual uint rule() const { return countTrailingZerosL_bsf_rule; } |
| 11225 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11226 | virtual int ideal_Opcode() const { return Op_CountTrailingZerosL; } |
| 11227 | public: |
| 11228 | countTrailingZerosL_bsfNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11229 | virtual uint size_of() const { return sizeof(countTrailingZerosL_bsfNode); } |
| 11230 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11231 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11232 | static const Pipeline *pipeline_class(); |
| 11233 | virtual const Pipeline *pipeline() const; |
| 11234 | #ifndef PRODUCT |
| 11235 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11236 | virtual const char *Name() const { return "countTrailingZerosL_bsf";} |
| 11237 | #endif |
| 11238 | }; |
| 11239 | |
| 11240 | class popCountINode : public MachNode { |
| 11241 | private: |
| 11242 | MachOper *_opnd_array[2]; |
| 11243 | public: |
| 11244 | MachOper *opnd_array(uint operand_index) const { |
| 11245 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11246 | return _opnd_array[operand_index]; |
| 11247 | } |
| 11248 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11249 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11250 | _opnd_array[operand_index] = operand; |
| 11251 | } |
| 11252 | private: |
| 11253 | const RegMask *_cisc_RegMask; |
| 11254 | virtual const RegMask &out_RegMask() const; |
| 11255 | virtual uint rule() const { return popCountI_rule; } |
| 11256 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11257 | virtual int ideal_Opcode() const { return Op_PopCountI; } |
| 11258 | virtual int cisc_operand() const { return 1; } |
| 11259 | virtual MachNode *cisc_version(int offset); |
| 11260 | virtual void use_cisc_RegMask(); |
| 11261 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 11262 | public: |
| 11263 | popCountINode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 11264 | virtual uint size_of() const { return sizeof(popCountINode); } |
| 11265 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11266 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11267 | static const Pipeline *pipeline_class(); |
| 11268 | virtual const Pipeline *pipeline() const; |
| 11269 | #ifndef PRODUCT |
| 11270 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11271 | virtual const char *Name() const { return "popCountI";} |
| 11272 | #endif |
| 11273 | }; |
| 11274 | |
| 11275 | class popCountI_memNode : public MachNode { |
| 11276 | private: |
| 11277 | MachOper *_opnd_array[2]; |
| 11278 | public: |
| 11279 | MachOper *opnd_array(uint operand_index) const { |
| 11280 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11281 | return _opnd_array[operand_index]; |
| 11282 | } |
| 11283 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11284 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11285 | _opnd_array[operand_index] = operand; |
| 11286 | } |
| 11287 | private: |
| 11288 | virtual const RegMask &out_RegMask() const; |
| 11289 | virtual uint rule() const { return popCountI_mem_rule; } |
| 11290 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11291 | virtual int ideal_Opcode() const { return Op_PopCountI; } |
| 11292 | virtual int reloc() const; |
| 11293 | virtual uint oper_input_base() const { return 2; } |
| 11294 | public: |
| 11295 | popCountI_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 11296 | virtual uint size_of() const { return sizeof(popCountI_memNode); } |
| 11297 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11298 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11299 | static const Pipeline *pipeline_class(); |
| 11300 | virtual const Pipeline *pipeline() const; |
| 11301 | virtual const MachOper *memory_operand() const; |
| 11302 | #ifndef PRODUCT |
| 11303 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11304 | virtual const char *Name() const { return "popCountI_mem";} |
| 11305 | #endif |
| 11306 | }; |
| 11307 | |
| 11308 | class popCountLNode : public MachNode { |
| 11309 | private: |
| 11310 | MachOper *_opnd_array[2]; |
| 11311 | public: |
| 11312 | MachOper *opnd_array(uint operand_index) const { |
| 11313 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11314 | return _opnd_array[operand_index]; |
| 11315 | } |
| 11316 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11317 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11318 | _opnd_array[operand_index] = operand; |
| 11319 | } |
| 11320 | private: |
| 11321 | const RegMask *_cisc_RegMask; |
| 11322 | virtual const RegMask &out_RegMask() const; |
| 11323 | virtual uint rule() const { return popCountL_rule; } |
| 11324 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11325 | virtual int ideal_Opcode() const { return Op_PopCountL; } |
| 11326 | virtual int cisc_operand() const { return 1; } |
| 11327 | virtual MachNode *cisc_version(int offset); |
| 11328 | virtual void use_cisc_RegMask(); |
| 11329 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 11330 | public: |
| 11331 | popCountLNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 11332 | virtual uint size_of() const { return sizeof(popCountLNode); } |
| 11333 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11334 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11335 | static const Pipeline *pipeline_class(); |
| 11336 | virtual const Pipeline *pipeline() const; |
| 11337 | #ifndef PRODUCT |
| 11338 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11339 | virtual const char *Name() const { return "popCountL";} |
| 11340 | #endif |
| 11341 | }; |
| 11342 | |
| 11343 | class popCountL_memNode : public MachNode { |
| 11344 | private: |
| 11345 | MachOper *_opnd_array[2]; |
| 11346 | public: |
| 11347 | MachOper *opnd_array(uint operand_index) const { |
| 11348 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11349 | return _opnd_array[operand_index]; |
| 11350 | } |
| 11351 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11352 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11353 | _opnd_array[operand_index] = operand; |
| 11354 | } |
| 11355 | private: |
| 11356 | virtual const RegMask &out_RegMask() const; |
| 11357 | virtual uint rule() const { return popCountL_mem_rule; } |
| 11358 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11359 | virtual int ideal_Opcode() const { return Op_PopCountL; } |
| 11360 | virtual int reloc() const; |
| 11361 | virtual uint oper_input_base() const { return 2; } |
| 11362 | public: |
| 11363 | popCountL_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 11364 | virtual uint size_of() const { return sizeof(popCountL_memNode); } |
| 11365 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11366 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11367 | static const Pipeline *pipeline_class(); |
| 11368 | virtual const Pipeline *pipeline() const; |
| 11369 | virtual const MachOper *memory_operand() const; |
| 11370 | #ifndef PRODUCT |
| 11371 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11372 | virtual const char *Name() const { return "popCountL_mem";} |
| 11373 | #endif |
| 11374 | }; |
| 11375 | |
| 11376 | class membar_acquireNode : public MachMemBarNode { |
| 11377 | private: |
| 11378 | MachOper *_opnd_array[1]; |
| 11379 | public: |
| 11380 | MachOper *opnd_array(uint operand_index) const { |
| 11381 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11382 | return _opnd_array[operand_index]; |
| 11383 | } |
| 11384 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11385 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11386 | _opnd_array[operand_index] = operand; |
| 11387 | } |
| 11388 | private: |
| 11389 | virtual const RegMask &out_RegMask() const; |
| 11390 | virtual uint rule() const { return membar_acquire_rule; } |
| 11391 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11392 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11393 | virtual int ideal_Opcode() const { return Op_MemBarAcquire; } |
| 11394 | virtual uint oper_input_base() const { return 1; } |
| 11395 | public: |
| 11396 | membar_acquireNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11397 | virtual uint size_of() const { return sizeof(membar_acquireNode); } |
| 11398 | static const Pipeline *pipeline_class(); |
| 11399 | virtual const Pipeline *pipeline() const; |
| 11400 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11401 | #ifndef PRODUCT |
| 11402 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11403 | virtual const char *Name() const { return "membar_acquire";} |
| 11404 | #endif |
| 11405 | }; |
| 11406 | |
| 11407 | class membar_acquire_0Node : public MachMemBarNode { |
| 11408 | private: |
| 11409 | MachOper *_opnd_array[1]; |
| 11410 | public: |
| 11411 | MachOper *opnd_array(uint operand_index) const { |
| 11412 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11413 | return _opnd_array[operand_index]; |
| 11414 | } |
| 11415 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11417 | _opnd_array[operand_index] = operand; |
| 11418 | } |
| 11419 | private: |
| 11420 | virtual const RegMask &out_RegMask() const; |
| 11421 | virtual uint rule() const { return membar_acquire_0_rule; } |
| 11422 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11423 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11424 | virtual int ideal_Opcode() const { return Op_LoadFence; } |
| 11425 | virtual uint oper_input_base() const { return 1; } |
| 11426 | public: |
| 11427 | membar_acquire_0Node() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11428 | virtual uint size_of() const { return sizeof(membar_acquire_0Node); } |
| 11429 | static const Pipeline *pipeline_class(); |
| 11430 | virtual const Pipeline *pipeline() const; |
| 11431 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11432 | #ifndef PRODUCT |
| 11433 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11434 | virtual const char *Name() const { return "membar_acquire_0";} |
| 11435 | #endif |
| 11436 | }; |
| 11437 | |
| 11438 | class membar_acquire_lockNode : public MachMemBarNode { |
| 11439 | private: |
| 11440 | MachOper *_opnd_array[1]; |
| 11441 | public: |
| 11442 | MachOper *opnd_array(uint operand_index) const { |
| 11443 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11444 | return _opnd_array[operand_index]; |
| 11445 | } |
| 11446 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11447 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11448 | _opnd_array[operand_index] = operand; |
| 11449 | } |
| 11450 | private: |
| 11451 | virtual const RegMask &out_RegMask() const; |
| 11452 | virtual uint rule() const { return membar_acquire_lock_rule; } |
| 11453 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11454 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11455 | virtual int ideal_Opcode() const { return Op_MemBarAcquireLock; } |
| 11456 | virtual uint oper_input_base() const { return 1; } |
| 11457 | public: |
| 11458 | membar_acquire_lockNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11459 | virtual uint size_of() const { return sizeof(membar_acquire_lockNode); } |
| 11460 | static const Pipeline *pipeline_class(); |
| 11461 | virtual const Pipeline *pipeline() const; |
| 11462 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11463 | #ifndef PRODUCT |
| 11464 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11465 | virtual const char *Name() const { return "membar_acquire_lock";} |
| 11466 | #endif |
| 11467 | }; |
| 11468 | |
| 11469 | class membar_releaseNode : public MachMemBarNode { |
| 11470 | private: |
| 11471 | MachOper *_opnd_array[1]; |
| 11472 | public: |
| 11473 | MachOper *opnd_array(uint operand_index) const { |
| 11474 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11475 | return _opnd_array[operand_index]; |
| 11476 | } |
| 11477 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11478 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11479 | _opnd_array[operand_index] = operand; |
| 11480 | } |
| 11481 | private: |
| 11482 | virtual const RegMask &out_RegMask() const; |
| 11483 | virtual uint rule() const { return membar_release_rule; } |
| 11484 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11485 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11486 | virtual int ideal_Opcode() const { return Op_MemBarRelease; } |
| 11487 | virtual uint oper_input_base() const { return 1; } |
| 11488 | public: |
| 11489 | membar_releaseNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11490 | virtual uint size_of() const { return sizeof(membar_releaseNode); } |
| 11491 | static const Pipeline *pipeline_class(); |
| 11492 | virtual const Pipeline *pipeline() const; |
| 11493 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11494 | #ifndef PRODUCT |
| 11495 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11496 | virtual const char *Name() const { return "membar_release";} |
| 11497 | #endif |
| 11498 | }; |
| 11499 | |
| 11500 | class membar_release_0Node : public MachMemBarNode { |
| 11501 | private: |
| 11502 | MachOper *_opnd_array[1]; |
| 11503 | public: |
| 11504 | MachOper *opnd_array(uint operand_index) const { |
| 11505 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11506 | return _opnd_array[operand_index]; |
| 11507 | } |
| 11508 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11509 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11510 | _opnd_array[operand_index] = operand; |
| 11511 | } |
| 11512 | private: |
| 11513 | virtual const RegMask &out_RegMask() const; |
| 11514 | virtual uint rule() const { return membar_release_0_rule; } |
| 11515 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11516 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11517 | virtual int ideal_Opcode() const { return Op_StoreFence; } |
| 11518 | virtual uint oper_input_base() const { return 1; } |
| 11519 | public: |
| 11520 | membar_release_0Node() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11521 | virtual uint size_of() const { return sizeof(membar_release_0Node); } |
| 11522 | static const Pipeline *pipeline_class(); |
| 11523 | virtual const Pipeline *pipeline() const; |
| 11524 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11525 | #ifndef PRODUCT |
| 11526 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11527 | virtual const char *Name() const { return "membar_release_0";} |
| 11528 | #endif |
| 11529 | }; |
| 11530 | |
| 11531 | class membar_release_lockNode : public MachMemBarNode { |
| 11532 | private: |
| 11533 | MachOper *_opnd_array[1]; |
| 11534 | public: |
| 11535 | MachOper *opnd_array(uint operand_index) const { |
| 11536 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11537 | return _opnd_array[operand_index]; |
| 11538 | } |
| 11539 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11540 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11541 | _opnd_array[operand_index] = operand; |
| 11542 | } |
| 11543 | private: |
| 11544 | virtual const RegMask &out_RegMask() const; |
| 11545 | virtual uint rule() const { return membar_release_lock_rule; } |
| 11546 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11547 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11548 | virtual int ideal_Opcode() const { return Op_MemBarReleaseLock; } |
| 11549 | virtual uint oper_input_base() const { return 1; } |
| 11550 | public: |
| 11551 | membar_release_lockNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11552 | virtual uint size_of() const { return sizeof(membar_release_lockNode); } |
| 11553 | static const Pipeline *pipeline_class(); |
| 11554 | virtual const Pipeline *pipeline() const; |
| 11555 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11556 | #ifndef PRODUCT |
| 11557 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11558 | virtual const char *Name() const { return "membar_release_lock";} |
| 11559 | #endif |
| 11560 | }; |
| 11561 | |
| 11562 | class membar_volatileNode : public MachMemBarNode { |
| 11563 | private: |
| 11564 | MachOper *_opnd_array[2]; |
| 11565 | public: |
| 11566 | MachOper *opnd_array(uint operand_index) const { |
| 11567 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11568 | return _opnd_array[operand_index]; |
| 11569 | } |
| 11570 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11571 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11572 | _opnd_array[operand_index] = operand; |
| 11573 | } |
| 11574 | private: |
| 11575 | virtual const RegMask &out_RegMask() const; |
| 11576 | virtual uint rule() const { return membar_volatile_rule; } |
| 11577 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11578 | virtual int ideal_Opcode() const { return Op_MemBarVolatile; } |
| 11579 | virtual uint oper_input_base() const { return 1; } |
| 11580 | public: |
| 11581 | membar_volatileNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11582 | virtual uint size_of() const { return sizeof(membar_volatileNode); } |
| 11583 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11584 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11585 | // Rematerialize membar_volatile |
| 11586 | static const Pipeline *pipeline_class(); |
| 11587 | virtual const Pipeline *pipeline() const; |
| 11588 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11589 | #ifndef PRODUCT |
| 11590 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11591 | virtual const char *Name() const { return "membar_volatile";} |
| 11592 | #endif |
| 11593 | }; |
| 11594 | |
| 11595 | class unnecessary_membar_volatileNode : public MachMemBarNode { |
| 11596 | private: |
| 11597 | MachOper *_opnd_array[1]; |
| 11598 | public: |
| 11599 | MachOper *opnd_array(uint operand_index) const { |
| 11600 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11601 | return _opnd_array[operand_index]; |
| 11602 | } |
| 11603 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11604 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11605 | _opnd_array[operand_index] = operand; |
| 11606 | } |
| 11607 | private: |
| 11608 | virtual const RegMask &out_RegMask() const; |
| 11609 | virtual uint rule() const { return unnecessary_membar_volatile_rule; } |
| 11610 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11611 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11612 | virtual int ideal_Opcode() const { return Op_MemBarVolatile; } |
| 11613 | virtual uint oper_input_base() const { return 1; } |
| 11614 | public: |
| 11615 | unnecessary_membar_volatileNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11616 | virtual uint size_of() const { return sizeof(unnecessary_membar_volatileNode); } |
| 11617 | static const Pipeline *pipeline_class(); |
| 11618 | virtual const Pipeline *pipeline() const; |
| 11619 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11620 | #ifndef PRODUCT |
| 11621 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11622 | virtual const char *Name() const { return "unnecessary_membar_volatile";} |
| 11623 | #endif |
| 11624 | }; |
| 11625 | |
| 11626 | class membar_storestoreNode : public MachMemBarNode { |
| 11627 | private: |
| 11628 | MachOper *_opnd_array[1]; |
| 11629 | public: |
| 11630 | MachOper *opnd_array(uint operand_index) const { |
| 11631 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11632 | return _opnd_array[operand_index]; |
| 11633 | } |
| 11634 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11635 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11636 | _opnd_array[operand_index] = operand; |
| 11637 | } |
| 11638 | private: |
| 11639 | virtual const RegMask &out_RegMask() const; |
| 11640 | virtual uint rule() const { return membar_storestore_rule; } |
| 11641 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11642 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 11643 | virtual int ideal_Opcode() const { return Op_MemBarStoreStore; } |
| 11644 | virtual uint oper_input_base() const { return 1; } |
| 11645 | public: |
| 11646 | membar_storestoreNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 11647 | virtual uint size_of() const { return sizeof(membar_storestoreNode); } |
| 11648 | static const Pipeline *pipeline_class(); |
| 11649 | virtual const Pipeline *pipeline() const; |
| 11650 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 11651 | #ifndef PRODUCT |
| 11652 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11653 | virtual const char *Name() const { return "membar_storestore";} |
| 11654 | #endif |
| 11655 | }; |
| 11656 | |
| 11657 | class castX2PNode : public MachTypeNode { |
| 11658 | private: |
| 11659 | MachOper *_opnd_array[2]; |
| 11660 | public: |
| 11661 | MachOper *opnd_array(uint operand_index) const { |
| 11662 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11663 | return _opnd_array[operand_index]; |
| 11664 | } |
| 11665 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11666 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11667 | _opnd_array[operand_index] = operand; |
| 11668 | } |
| 11669 | private: |
| 11670 | virtual const RegMask &out_RegMask() const; |
| 11671 | virtual uint rule() const { return castX2P_rule; } |
| 11672 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11673 | virtual int ideal_Opcode() const { return Op_CastX2P; } |
| 11674 | virtual uint oper_input_base() const { return 1; } |
| 11675 | public: |
| 11676 | castX2PNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11677 | virtual uint size_of() const { return sizeof(castX2PNode); } |
| 11678 | // Rematerialize castX2P |
| 11679 | static const Pipeline *pipeline_class(); |
| 11680 | virtual const Pipeline *pipeline() const; |
| 11681 | #ifndef PRODUCT |
| 11682 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11683 | virtual const char *Name() const { return "castX2P";} |
| 11684 | #endif |
| 11685 | }; |
| 11686 | |
| 11687 | class castP2XNode : public MachNode { |
| 11688 | private: |
| 11689 | MachOper *_opnd_array[2]; |
| 11690 | public: |
| 11691 | MachOper *opnd_array(uint operand_index) const { |
| 11692 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11693 | return _opnd_array[operand_index]; |
| 11694 | } |
| 11695 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11697 | _opnd_array[operand_index] = operand; |
| 11698 | } |
| 11699 | private: |
| 11700 | virtual const RegMask &out_RegMask() const; |
| 11701 | virtual uint rule() const { return castP2X_rule; } |
| 11702 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11703 | virtual int ideal_Opcode() const { return Op_CastP2X; } |
| 11704 | public: |
| 11705 | castP2XNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11706 | virtual uint size_of() const { return sizeof(castP2XNode); } |
| 11707 | // Rematerialize castP2X |
| 11708 | static const Pipeline *pipeline_class(); |
| 11709 | virtual const Pipeline *pipeline() const; |
| 11710 | #ifndef PRODUCT |
| 11711 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11712 | virtual const char *Name() const { return "castP2X";} |
| 11713 | #endif |
| 11714 | }; |
| 11715 | |
| 11716 | class convP2INode : public MachNode { |
| 11717 | private: |
| 11718 | MachOper *_opnd_array[2]; |
| 11719 | public: |
| 11720 | MachOper *opnd_array(uint operand_index) const { |
| 11721 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11722 | return _opnd_array[operand_index]; |
| 11723 | } |
| 11724 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11725 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11726 | _opnd_array[operand_index] = operand; |
| 11727 | } |
| 11728 | private: |
| 11729 | virtual const RegMask &out_RegMask() const; |
| 11730 | virtual uint rule() const { return convP2I_rule; } |
| 11731 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11732 | virtual int ideal_Opcode() const { return Op_ConvL2I; } |
| 11733 | public: |
| 11734 | convP2INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11735 | virtual uint size_of() const { return sizeof(convP2INode); } |
| 11736 | static const Pipeline *pipeline_class(); |
| 11737 | virtual const Pipeline *pipeline() const; |
| 11738 | #ifndef PRODUCT |
| 11739 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11740 | virtual const char *Name() const { return "convP2I";} |
| 11741 | #endif |
| 11742 | }; |
| 11743 | |
| 11744 | class convN2INode : public MachNode { |
| 11745 | private: |
| 11746 | MachOper *_opnd_array[2]; |
| 11747 | public: |
| 11748 | MachOper *opnd_array(uint operand_index) const { |
| 11749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11750 | return _opnd_array[operand_index]; |
| 11751 | } |
| 11752 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11753 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11754 | _opnd_array[operand_index] = operand; |
| 11755 | } |
| 11756 | private: |
| 11757 | virtual const RegMask &out_RegMask() const; |
| 11758 | virtual uint rule() const { return convN2I_rule; } |
| 11759 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11760 | virtual int ideal_Opcode() const { return Op_ConvL2I; } |
| 11761 | public: |
| 11762 | convN2INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11763 | virtual uint size_of() const { return sizeof(convN2INode); } |
| 11764 | static const Pipeline *pipeline_class(); |
| 11765 | virtual const Pipeline *pipeline() const; |
| 11766 | #ifndef PRODUCT |
| 11767 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11768 | virtual const char *Name() const { return "convN2I";} |
| 11769 | #endif |
| 11770 | }; |
| 11771 | |
| 11772 | class encodeHeapOopNode : public MachTypeNode { |
| 11773 | private: |
| 11774 | MachOper *_opnd_array[2]; |
| 11775 | public: |
| 11776 | MachOper *opnd_array(uint operand_index) const { |
| 11777 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11778 | return _opnd_array[operand_index]; |
| 11779 | } |
| 11780 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11781 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11782 | _opnd_array[operand_index] = operand; |
| 11783 | } |
| 11784 | private: |
| 11785 | virtual const RegMask &out_RegMask() const; |
| 11786 | virtual uint rule() const { return encodeHeapOop_rule; } |
| 11787 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11788 | virtual int ideal_Opcode() const { return Op_EncodeP; } |
| 11789 | virtual uint oper_input_base() const { return 1; } |
| 11790 | public: |
| 11791 | encodeHeapOopNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11792 | virtual uint size_of() const { return sizeof(encodeHeapOopNode); } |
| 11793 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11794 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11795 | static const Pipeline *pipeline_class(); |
| 11796 | virtual const Pipeline *pipeline() const; |
| 11797 | #ifndef PRODUCT |
| 11798 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11799 | virtual const char *Name() const { return "encodeHeapOop";} |
| 11800 | #endif |
| 11801 | }; |
| 11802 | |
| 11803 | class encodeHeapOop_not_nullNode : public MachTypeNode { |
| 11804 | private: |
| 11805 | MachOper *_opnd_array[2]; |
| 11806 | public: |
| 11807 | MachOper *opnd_array(uint operand_index) const { |
| 11808 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11809 | return _opnd_array[operand_index]; |
| 11810 | } |
| 11811 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11813 | _opnd_array[operand_index] = operand; |
| 11814 | } |
| 11815 | private: |
| 11816 | virtual const RegMask &out_RegMask() const; |
| 11817 | virtual uint rule() const { return encodeHeapOop_not_null_rule; } |
| 11818 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11819 | virtual int ideal_Opcode() const { return Op_EncodeP; } |
| 11820 | virtual uint oper_input_base() const { return 1; } |
| 11821 | public: |
| 11822 | encodeHeapOop_not_nullNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11823 | virtual uint size_of() const { return sizeof(encodeHeapOop_not_nullNode); } |
| 11824 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11825 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11826 | static const Pipeline *pipeline_class(); |
| 11827 | virtual const Pipeline *pipeline() const; |
| 11828 | #ifndef PRODUCT |
| 11829 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11830 | virtual const char *Name() const { return "encodeHeapOop_not_null";} |
| 11831 | #endif |
| 11832 | }; |
| 11833 | |
| 11834 | class decodeHeapOopNode : public MachTypeNode { |
| 11835 | private: |
| 11836 | MachOper *_opnd_array[2]; |
| 11837 | public: |
| 11838 | MachOper *opnd_array(uint operand_index) const { |
| 11839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11840 | return _opnd_array[operand_index]; |
| 11841 | } |
| 11842 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11843 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11844 | _opnd_array[operand_index] = operand; |
| 11845 | } |
| 11846 | private: |
| 11847 | virtual const RegMask &out_RegMask() const; |
| 11848 | virtual uint rule() const { return decodeHeapOop_rule; } |
| 11849 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11850 | virtual int ideal_Opcode() const { return Op_DecodeN; } |
| 11851 | virtual uint oper_input_base() const { return 1; } |
| 11852 | public: |
| 11853 | decodeHeapOopNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11854 | virtual uint size_of() const { return sizeof(decodeHeapOopNode); } |
| 11855 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11856 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11857 | static const Pipeline *pipeline_class(); |
| 11858 | virtual const Pipeline *pipeline() const; |
| 11859 | #ifndef PRODUCT |
| 11860 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11861 | virtual const char *Name() const { return "decodeHeapOop";} |
| 11862 | #endif |
| 11863 | }; |
| 11864 | |
| 11865 | class decodeHeapOop_not_nullNode : public MachTypeNode { |
| 11866 | private: |
| 11867 | MachOper *_opnd_array[2]; |
| 11868 | public: |
| 11869 | MachOper *opnd_array(uint operand_index) const { |
| 11870 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11871 | return _opnd_array[operand_index]; |
| 11872 | } |
| 11873 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11874 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11875 | _opnd_array[operand_index] = operand; |
| 11876 | } |
| 11877 | private: |
| 11878 | virtual const RegMask &out_RegMask() const; |
| 11879 | virtual uint rule() const { return decodeHeapOop_not_null_rule; } |
| 11880 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11881 | virtual int ideal_Opcode() const { return Op_DecodeN; } |
| 11882 | virtual uint oper_input_base() const { return 1; } |
| 11883 | public: |
| 11884 | decodeHeapOop_not_nullNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11885 | virtual uint size_of() const { return sizeof(decodeHeapOop_not_nullNode); } |
| 11886 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11887 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11888 | static const Pipeline *pipeline_class(); |
| 11889 | virtual const Pipeline *pipeline() const; |
| 11890 | #ifndef PRODUCT |
| 11891 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11892 | virtual const char *Name() const { return "decodeHeapOop_not_null";} |
| 11893 | #endif |
| 11894 | }; |
| 11895 | |
| 11896 | class encodeKlass_not_nullNode : public MachTypeNode { |
| 11897 | private: |
| 11898 | MachOper *_opnd_array[2]; |
| 11899 | public: |
| 11900 | MachOper *opnd_array(uint operand_index) const { |
| 11901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11902 | return _opnd_array[operand_index]; |
| 11903 | } |
| 11904 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11905 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11906 | _opnd_array[operand_index] = operand; |
| 11907 | } |
| 11908 | private: |
| 11909 | virtual const RegMask &out_RegMask() const; |
| 11910 | virtual uint rule() const { return encodeKlass_not_null_rule; } |
| 11911 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11912 | virtual int ideal_Opcode() const { return Op_EncodePKlass; } |
| 11913 | virtual uint oper_input_base() const { return 1; } |
| 11914 | public: |
| 11915 | encodeKlass_not_nullNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11916 | virtual uint size_of() const { return sizeof(encodeKlass_not_nullNode); } |
| 11917 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11918 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11919 | static const Pipeline *pipeline_class(); |
| 11920 | virtual const Pipeline *pipeline() const; |
| 11921 | #ifndef PRODUCT |
| 11922 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11923 | virtual const char *Name() const { return "encodeKlass_not_null";} |
| 11924 | #endif |
| 11925 | }; |
| 11926 | |
| 11927 | class decodeKlass_not_nullNode : public MachTypeNode { |
| 11928 | private: |
| 11929 | MachOper *_opnd_array[2]; |
| 11930 | public: |
| 11931 | MachOper *opnd_array(uint operand_index) const { |
| 11932 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11933 | return _opnd_array[operand_index]; |
| 11934 | } |
| 11935 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11936 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11937 | _opnd_array[operand_index] = operand; |
| 11938 | } |
| 11939 | private: |
| 11940 | virtual const RegMask &out_RegMask() const; |
| 11941 | virtual uint rule() const { return decodeKlass_not_null_rule; } |
| 11942 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11943 | virtual int ideal_Opcode() const { return Op_DecodeNKlass; } |
| 11944 | virtual uint oper_input_base() const { return 1; } |
| 11945 | public: |
| 11946 | decodeKlass_not_nullNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 11947 | virtual uint size_of() const { return sizeof(decodeKlass_not_nullNode); } |
| 11948 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11949 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11950 | static const Pipeline *pipeline_class(); |
| 11951 | virtual const Pipeline *pipeline() const; |
| 11952 | #ifndef PRODUCT |
| 11953 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11954 | virtual const char *Name() const { return "decodeKlass_not_null";} |
| 11955 | #endif |
| 11956 | }; |
| 11957 | |
| 11958 | class jumpXtnd_offsetNode : public MachJumpNode { |
| 11959 | private: |
| 11960 | MachOper *_opnd_array[4]; |
| 11961 | GrowableArray<Label*> _index2label; |
| 11962 | public: |
| 11963 | MachOper *opnd_array(uint operand_index) const { |
| 11964 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11965 | return _opnd_array[operand_index]; |
| 11966 | } |
| 11967 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 11968 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 11969 | _opnd_array[operand_index] = operand; |
| 11970 | } |
| 11971 | private: |
| 11972 | virtual void add_case_label(int index_num, Label* blockLabel) { |
| 11973 | _index2label.at_put_grow(index_num, blockLabel); |
| 11974 | } |
| 11975 | virtual const RegMask &out_RegMask() const; |
| 11976 | virtual uint rule() const { return jumpXtnd_offset_rule; } |
| 11977 | virtual void eval_constant(Compile* C); |
| 11978 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 11979 | virtual int ideal_Opcode() const { return Op_Jump; } |
| 11980 | virtual uint oper_input_base() const { return 1; } |
| 11981 | public: |
| 11982 | jumpXtnd_offsetNode() : _index2label(MinJumpTableSize*2) { _num_opnds = 4; _opnds = _opnd_array; } |
| 11983 | virtual uint size_of() const { return sizeof(jumpXtnd_offsetNode); } |
| 11984 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 11985 | virtual bool pinned() const { return true; } |
| 11986 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 11987 | static const Pipeline *pipeline_class(); |
| 11988 | virtual const Pipeline *pipeline() const; |
| 11989 | #ifndef PRODUCT |
| 11990 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 11991 | virtual const char *Name() const { return "jumpXtnd_offset";} |
| 11992 | #endif |
| 11993 | }; |
| 11994 | |
| 11995 | class jumpXtnd_addrNode : public MachJumpNode { |
| 11996 | private: |
| 11997 | MachOper *_opnd_array[5]; |
| 11998 | GrowableArray<Label*> _index2label; |
| 11999 | public: |
| 12000 | MachOper *opnd_array(uint operand_index) const { |
| 12001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12002 | return _opnd_array[operand_index]; |
| 12003 | } |
| 12004 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12006 | _opnd_array[operand_index] = operand; |
| 12007 | } |
| 12008 | private: |
| 12009 | virtual void add_case_label(int index_num, Label* blockLabel) { |
| 12010 | _index2label.at_put_grow(index_num, blockLabel); |
| 12011 | } |
| 12012 | virtual const RegMask &out_RegMask() const; |
| 12013 | virtual uint rule() const { return jumpXtnd_addr_rule; } |
| 12014 | virtual void eval_constant(Compile* C); |
| 12015 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12016 | virtual int ideal_Opcode() const { return Op_Jump; } |
| 12017 | virtual uint oper_input_base() const { return 1; } |
| 12018 | public: |
| 12019 | jumpXtnd_addrNode() : _index2label(MinJumpTableSize*2) { _num_opnds = 5; _opnds = _opnd_array; } |
| 12020 | virtual uint size_of() const { return sizeof(jumpXtnd_addrNode); } |
| 12021 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12022 | virtual bool pinned() const { return true; } |
| 12023 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12024 | static const Pipeline *pipeline_class(); |
| 12025 | virtual const Pipeline *pipeline() const; |
| 12026 | #ifndef PRODUCT |
| 12027 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12028 | virtual const char *Name() const { return "jumpXtnd_addr";} |
| 12029 | #endif |
| 12030 | }; |
| 12031 | |
| 12032 | class jumpXtndNode : public MachJumpNode { |
| 12033 | private: |
| 12034 | MachOper *_opnd_array[3]; |
| 12035 | GrowableArray<Label*> _index2label; |
| 12036 | public: |
| 12037 | MachOper *opnd_array(uint operand_index) const { |
| 12038 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12039 | return _opnd_array[operand_index]; |
| 12040 | } |
| 12041 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12042 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12043 | _opnd_array[operand_index] = operand; |
| 12044 | } |
| 12045 | private: |
| 12046 | virtual void add_case_label(int index_num, Label* blockLabel) { |
| 12047 | _index2label.at_put_grow(index_num, blockLabel); |
| 12048 | } |
| 12049 | virtual const RegMask &out_RegMask() const; |
| 12050 | virtual uint rule() const { return jumpXtnd_rule; } |
| 12051 | virtual void eval_constant(Compile* C); |
| 12052 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12053 | virtual int ideal_Opcode() const { return Op_Jump; } |
| 12054 | virtual uint oper_input_base() const { return 1; } |
| 12055 | public: |
| 12056 | jumpXtndNode() : _index2label(MinJumpTableSize*2) { _num_opnds = 3; _opnds = _opnd_array; } |
| 12057 | virtual uint size_of() const { return sizeof(jumpXtndNode); } |
| 12058 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12059 | virtual bool pinned() const { return true; } |
| 12060 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12061 | static const Pipeline *pipeline_class(); |
| 12062 | virtual const Pipeline *pipeline() const; |
| 12063 | #ifndef PRODUCT |
| 12064 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12065 | virtual const char *Name() const { return "jumpXtnd";} |
| 12066 | #endif |
| 12067 | }; |
| 12068 | |
| 12069 | class cmovI_regNode : public MachNode { |
| 12070 | private: |
| 12071 | MachOper *_opnd_array[5]; |
| 12072 | public: |
| 12073 | MachOper *opnd_array(uint operand_index) const { |
| 12074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12075 | return _opnd_array[operand_index]; |
| 12076 | } |
| 12077 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12078 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12079 | _opnd_array[operand_index] = operand; |
| 12080 | } |
| 12081 | private: |
| 12082 | const RegMask *_cisc_RegMask; |
| 12083 | virtual const RegMask &out_RegMask() const; |
| 12084 | virtual uint rule() const { return cmovI_reg_rule; } |
| 12085 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12086 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12087 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12088 | virtual int cisc_operand() const { return 4; } |
| 12089 | virtual MachNode *cisc_version(int offset); |
| 12090 | virtual void use_cisc_RegMask(); |
| 12091 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12092 | public: |
| 12093 | cmovI_regNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12094 | virtual uint size_of() const { return sizeof(cmovI_regNode); } |
| 12095 | static const Pipeline *pipeline_class(); |
| 12096 | virtual const Pipeline *pipeline() const; |
| 12097 | #ifndef PRODUCT |
| 12098 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12099 | virtual const char *Name() const { return "cmovI_reg";} |
| 12100 | #endif |
| 12101 | }; |
| 12102 | |
| 12103 | class cmovI_regUNode : public MachNode { |
| 12104 | private: |
| 12105 | MachOper *_opnd_array[5]; |
| 12106 | public: |
| 12107 | MachOper *opnd_array(uint operand_index) const { |
| 12108 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12109 | return _opnd_array[operand_index]; |
| 12110 | } |
| 12111 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12112 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12113 | _opnd_array[operand_index] = operand; |
| 12114 | } |
| 12115 | private: |
| 12116 | const RegMask *_cisc_RegMask; |
| 12117 | virtual const RegMask &out_RegMask() const; |
| 12118 | virtual uint rule() const { return cmovI_regU_rule; } |
| 12119 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12120 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12121 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12122 | virtual int cisc_operand() const { return 4; } |
| 12123 | virtual MachNode *cisc_version(int offset); |
| 12124 | virtual void use_cisc_RegMask(); |
| 12125 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12126 | public: |
| 12127 | cmovI_regUNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12128 | virtual uint size_of() const { return sizeof(cmovI_regUNode); } |
| 12129 | static const Pipeline *pipeline_class(); |
| 12130 | virtual const Pipeline *pipeline() const; |
| 12131 | #ifndef PRODUCT |
| 12132 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12133 | virtual const char *Name() const { return "cmovI_regU";} |
| 12134 | #endif |
| 12135 | }; |
| 12136 | |
| 12137 | class cmovI_regUCFNode : public MachNode { |
| 12138 | private: |
| 12139 | MachOper *_opnd_array[5]; |
| 12140 | public: |
| 12141 | MachOper *opnd_array(uint operand_index) const { |
| 12142 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12143 | return _opnd_array[operand_index]; |
| 12144 | } |
| 12145 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12146 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12147 | _opnd_array[operand_index] = operand; |
| 12148 | } |
| 12149 | private: |
| 12150 | const RegMask *_cisc_RegMask; |
| 12151 | virtual const RegMask &out_RegMask() const; |
| 12152 | virtual uint rule() const { return cmovI_regUCF_rule; } |
| 12153 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12154 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12155 | virtual int cisc_operand() const { return 4; } |
| 12156 | virtual MachNode *cisc_version(int offset); |
| 12157 | virtual void use_cisc_RegMask(); |
| 12158 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12159 | public: |
| 12160 | cmovI_regUCFNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12161 | virtual uint size_of() const { return sizeof(cmovI_regUCFNode); } |
| 12162 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12163 | #ifndef PRODUCT |
| 12164 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12165 | virtual const char *Name() const { return "cmovI_regUCF";} |
| 12166 | #endif |
| 12167 | }; |
| 12168 | |
| 12169 | class cmovI_memNode : public MachNode { |
| 12170 | private: |
| 12171 | MachOper *_opnd_array[5]; |
| 12172 | public: |
| 12173 | MachOper *opnd_array(uint operand_index) const { |
| 12174 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12175 | return _opnd_array[operand_index]; |
| 12176 | } |
| 12177 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12178 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12179 | _opnd_array[operand_index] = operand; |
| 12180 | } |
| 12181 | private: |
| 12182 | virtual const RegMask &out_RegMask() const; |
| 12183 | virtual uint rule() const { return cmovI_mem_rule; } |
| 12184 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12185 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12186 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12187 | virtual int reloc() const; |
| 12188 | virtual uint oper_input_base() const { return 2; } |
| 12189 | public: |
| 12190 | cmovI_memNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12191 | virtual uint size_of() const { return sizeof(cmovI_memNode); } |
| 12192 | static const Pipeline *pipeline_class(); |
| 12193 | virtual const Pipeline *pipeline() const; |
| 12194 | virtual const MachOper *memory_operand() const; |
| 12195 | #ifndef PRODUCT |
| 12196 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12197 | virtual const char *Name() const { return "cmovI_mem";} |
| 12198 | #endif |
| 12199 | }; |
| 12200 | |
| 12201 | class cmovI_memUNode : public MachNode { |
| 12202 | private: |
| 12203 | MachOper *_opnd_array[5]; |
| 12204 | public: |
| 12205 | MachOper *opnd_array(uint operand_index) const { |
| 12206 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12207 | return _opnd_array[operand_index]; |
| 12208 | } |
| 12209 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12210 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12211 | _opnd_array[operand_index] = operand; |
| 12212 | } |
| 12213 | private: |
| 12214 | virtual const RegMask &out_RegMask() const; |
| 12215 | virtual uint rule() const { return cmovI_memU_rule; } |
| 12216 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12217 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12218 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12219 | virtual int reloc() const; |
| 12220 | virtual uint oper_input_base() const { return 2; } |
| 12221 | public: |
| 12222 | cmovI_memUNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12223 | virtual uint size_of() const { return sizeof(cmovI_memUNode); } |
| 12224 | static const Pipeline *pipeline_class(); |
| 12225 | virtual const Pipeline *pipeline() const; |
| 12226 | virtual const MachOper *memory_operand() const; |
| 12227 | #ifndef PRODUCT |
| 12228 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12229 | virtual const char *Name() const { return "cmovI_memU";} |
| 12230 | #endif |
| 12231 | }; |
| 12232 | |
| 12233 | class cmovI_memUCFNode : public MachNode { |
| 12234 | private: |
| 12235 | MachOper *_opnd_array[5]; |
| 12236 | public: |
| 12237 | MachOper *opnd_array(uint operand_index) const { |
| 12238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12239 | return _opnd_array[operand_index]; |
| 12240 | } |
| 12241 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12242 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12243 | _opnd_array[operand_index] = operand; |
| 12244 | } |
| 12245 | private: |
| 12246 | virtual const RegMask &out_RegMask() const; |
| 12247 | virtual uint rule() const { return cmovI_memUCF_rule; } |
| 12248 | virtual int ideal_Opcode() const { return Op_CMoveI; } |
| 12249 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12250 | virtual int reloc() const; |
| 12251 | virtual uint oper_input_base() const { return 2; } |
| 12252 | public: |
| 12253 | cmovI_memUCFNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12254 | virtual uint size_of() const { return sizeof(cmovI_memUCFNode); } |
| 12255 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12256 | virtual const MachOper *memory_operand() const; |
| 12257 | #ifndef PRODUCT |
| 12258 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12259 | virtual const char *Name() const { return "cmovI_memUCF";} |
| 12260 | #endif |
| 12261 | }; |
| 12262 | |
| 12263 | class cmovN_regNode : public MachNode { |
| 12264 | private: |
| 12265 | MachOper *_opnd_array[5]; |
| 12266 | public: |
| 12267 | MachOper *opnd_array(uint operand_index) const { |
| 12268 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12269 | return _opnd_array[operand_index]; |
| 12270 | } |
| 12271 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12273 | _opnd_array[operand_index] = operand; |
| 12274 | } |
| 12275 | private: |
| 12276 | virtual const RegMask &out_RegMask() const; |
| 12277 | virtual uint rule() const { return cmovN_reg_rule; } |
| 12278 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12279 | virtual int ideal_Opcode() const { return Op_CMoveN; } |
| 12280 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12281 | public: |
| 12282 | cmovN_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12283 | virtual uint size_of() const { return sizeof(cmovN_regNode); } |
| 12284 | static const Pipeline *pipeline_class(); |
| 12285 | virtual const Pipeline *pipeline() const; |
| 12286 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveN |
| 12287 | #ifndef PRODUCT |
| 12288 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12289 | virtual const char *Name() const { return "cmovN_reg";} |
| 12290 | #endif |
| 12291 | }; |
| 12292 | |
| 12293 | class cmovN_regUNode : public MachNode { |
| 12294 | private: |
| 12295 | MachOper *_opnd_array[5]; |
| 12296 | public: |
| 12297 | MachOper *opnd_array(uint operand_index) const { |
| 12298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12299 | return _opnd_array[operand_index]; |
| 12300 | } |
| 12301 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12302 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12303 | _opnd_array[operand_index] = operand; |
| 12304 | } |
| 12305 | private: |
| 12306 | virtual const RegMask &out_RegMask() const; |
| 12307 | virtual uint rule() const { return cmovN_regU_rule; } |
| 12308 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12309 | virtual int ideal_Opcode() const { return Op_CMoveN; } |
| 12310 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12311 | public: |
| 12312 | cmovN_regUNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12313 | virtual uint size_of() const { return sizeof(cmovN_regUNode); } |
| 12314 | static const Pipeline *pipeline_class(); |
| 12315 | virtual const Pipeline *pipeline() const; |
| 12316 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveN |
| 12317 | #ifndef PRODUCT |
| 12318 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12319 | virtual const char *Name() const { return "cmovN_regU";} |
| 12320 | #endif |
| 12321 | }; |
| 12322 | |
| 12323 | class cmovN_regUCFNode : public MachNode { |
| 12324 | private: |
| 12325 | MachOper *_opnd_array[5]; |
| 12326 | public: |
| 12327 | MachOper *opnd_array(uint operand_index) const { |
| 12328 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12329 | return _opnd_array[operand_index]; |
| 12330 | } |
| 12331 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12332 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12333 | _opnd_array[operand_index] = operand; |
| 12334 | } |
| 12335 | private: |
| 12336 | virtual const RegMask &out_RegMask() const; |
| 12337 | virtual uint rule() const { return cmovN_regUCF_rule; } |
| 12338 | virtual int ideal_Opcode() const { return Op_CMoveN; } |
| 12339 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12340 | public: |
| 12341 | cmovN_regUCFNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12342 | virtual uint size_of() const { return sizeof(cmovN_regUCFNode); } |
| 12343 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12344 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveN |
| 12345 | #ifndef PRODUCT |
| 12346 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12347 | virtual const char *Name() const { return "cmovN_regUCF";} |
| 12348 | #endif |
| 12349 | }; |
| 12350 | |
| 12351 | class cmovP_regNode : public MachNode { |
| 12352 | private: |
| 12353 | MachOper *_opnd_array[5]; |
| 12354 | public: |
| 12355 | MachOper *opnd_array(uint operand_index) const { |
| 12356 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12357 | return _opnd_array[operand_index]; |
| 12358 | } |
| 12359 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12361 | _opnd_array[operand_index] = operand; |
| 12362 | } |
| 12363 | private: |
| 12364 | virtual const RegMask &out_RegMask() const; |
| 12365 | virtual uint rule() const { return cmovP_reg_rule; } |
| 12366 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12367 | virtual int ideal_Opcode() const { return Op_CMoveP; } |
| 12368 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12369 | public: |
| 12370 | cmovP_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12371 | virtual uint size_of() const { return sizeof(cmovP_regNode); } |
| 12372 | static const Pipeline *pipeline_class(); |
| 12373 | virtual const Pipeline *pipeline() const; |
| 12374 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveP |
| 12375 | #ifndef PRODUCT |
| 12376 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12377 | virtual const char *Name() const { return "cmovP_reg";} |
| 12378 | #endif |
| 12379 | }; |
| 12380 | |
| 12381 | class cmovP_regUNode : public MachNode { |
| 12382 | private: |
| 12383 | MachOper *_opnd_array[5]; |
| 12384 | public: |
| 12385 | MachOper *opnd_array(uint operand_index) const { |
| 12386 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12387 | return _opnd_array[operand_index]; |
| 12388 | } |
| 12389 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12390 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12391 | _opnd_array[operand_index] = operand; |
| 12392 | } |
| 12393 | private: |
| 12394 | virtual const RegMask &out_RegMask() const; |
| 12395 | virtual uint rule() const { return cmovP_regU_rule; } |
| 12396 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12397 | virtual int ideal_Opcode() const { return Op_CMoveP; } |
| 12398 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12399 | public: |
| 12400 | cmovP_regUNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12401 | virtual uint size_of() const { return sizeof(cmovP_regUNode); } |
| 12402 | static const Pipeline *pipeline_class(); |
| 12403 | virtual const Pipeline *pipeline() const; |
| 12404 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveP |
| 12405 | #ifndef PRODUCT |
| 12406 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12407 | virtual const char *Name() const { return "cmovP_regU";} |
| 12408 | #endif |
| 12409 | }; |
| 12410 | |
| 12411 | class cmovP_regUCFNode : public MachNode { |
| 12412 | private: |
| 12413 | MachOper *_opnd_array[5]; |
| 12414 | public: |
| 12415 | MachOper *opnd_array(uint operand_index) const { |
| 12416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12417 | return _opnd_array[operand_index]; |
| 12418 | } |
| 12419 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12420 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12421 | _opnd_array[operand_index] = operand; |
| 12422 | } |
| 12423 | private: |
| 12424 | virtual const RegMask &out_RegMask() const; |
| 12425 | virtual uint rule() const { return cmovP_regUCF_rule; } |
| 12426 | virtual int ideal_Opcode() const { return Op_CMoveP; } |
| 12427 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12428 | public: |
| 12429 | cmovP_regUCFNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12430 | virtual uint size_of() const { return sizeof(cmovP_regUCFNode); } |
| 12431 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12432 | const Type *bottom_type() const { const Type *t = in(oper_input_base()+1)->bottom_type(); return (req() <= oper_input_base()+2) ? t : t->meet(in(oper_input_base()+2)->bottom_type()); } // CMoveP |
| 12433 | #ifndef PRODUCT |
| 12434 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12435 | virtual const char *Name() const { return "cmovP_regUCF";} |
| 12436 | #endif |
| 12437 | }; |
| 12438 | |
| 12439 | class cmovL_regNode : public MachNode { |
| 12440 | private: |
| 12441 | MachOper *_opnd_array[5]; |
| 12442 | public: |
| 12443 | MachOper *opnd_array(uint operand_index) const { |
| 12444 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12445 | return _opnd_array[operand_index]; |
| 12446 | } |
| 12447 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12448 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12449 | _opnd_array[operand_index] = operand; |
| 12450 | } |
| 12451 | private: |
| 12452 | const RegMask *_cisc_RegMask; |
| 12453 | virtual const RegMask &out_RegMask() const; |
| 12454 | virtual uint rule() const { return cmovL_reg_rule; } |
| 12455 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12456 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12457 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12458 | virtual int cisc_operand() const { return 4; } |
| 12459 | virtual MachNode *cisc_version(int offset); |
| 12460 | virtual void use_cisc_RegMask(); |
| 12461 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12462 | public: |
| 12463 | cmovL_regNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12464 | virtual uint size_of() const { return sizeof(cmovL_regNode); } |
| 12465 | static const Pipeline *pipeline_class(); |
| 12466 | virtual const Pipeline *pipeline() const; |
| 12467 | #ifndef PRODUCT |
| 12468 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12469 | virtual const char *Name() const { return "cmovL_reg";} |
| 12470 | #endif |
| 12471 | }; |
| 12472 | |
| 12473 | class cmovL_memNode : public MachNode { |
| 12474 | private: |
| 12475 | MachOper *_opnd_array[5]; |
| 12476 | public: |
| 12477 | MachOper *opnd_array(uint operand_index) const { |
| 12478 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12479 | return _opnd_array[operand_index]; |
| 12480 | } |
| 12481 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12482 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12483 | _opnd_array[operand_index] = operand; |
| 12484 | } |
| 12485 | private: |
| 12486 | virtual const RegMask &out_RegMask() const; |
| 12487 | virtual uint rule() const { return cmovL_mem_rule; } |
| 12488 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12489 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12490 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12491 | virtual int reloc() const; |
| 12492 | virtual uint oper_input_base() const { return 2; } |
| 12493 | public: |
| 12494 | cmovL_memNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12495 | virtual uint size_of() const { return sizeof(cmovL_memNode); } |
| 12496 | static const Pipeline *pipeline_class(); |
| 12497 | virtual const Pipeline *pipeline() const; |
| 12498 | virtual const MachOper *memory_operand() const; |
| 12499 | #ifndef PRODUCT |
| 12500 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12501 | virtual const char *Name() const { return "cmovL_mem";} |
| 12502 | #endif |
| 12503 | }; |
| 12504 | |
| 12505 | class cmovL_regUNode : public MachNode { |
| 12506 | private: |
| 12507 | MachOper *_opnd_array[5]; |
| 12508 | public: |
| 12509 | MachOper *opnd_array(uint operand_index) const { |
| 12510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12511 | return _opnd_array[operand_index]; |
| 12512 | } |
| 12513 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12514 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12515 | _opnd_array[operand_index] = operand; |
| 12516 | } |
| 12517 | private: |
| 12518 | const RegMask *_cisc_RegMask; |
| 12519 | virtual const RegMask &out_RegMask() const; |
| 12520 | virtual uint rule() const { return cmovL_regU_rule; } |
| 12521 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12522 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12523 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12524 | virtual int cisc_operand() const { return 4; } |
| 12525 | virtual MachNode *cisc_version(int offset); |
| 12526 | virtual void use_cisc_RegMask(); |
| 12527 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12528 | public: |
| 12529 | cmovL_regUNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12530 | virtual uint size_of() const { return sizeof(cmovL_regUNode); } |
| 12531 | static const Pipeline *pipeline_class(); |
| 12532 | virtual const Pipeline *pipeline() const; |
| 12533 | #ifndef PRODUCT |
| 12534 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12535 | virtual const char *Name() const { return "cmovL_regU";} |
| 12536 | #endif |
| 12537 | }; |
| 12538 | |
| 12539 | class cmovL_regUCFNode : public MachNode { |
| 12540 | private: |
| 12541 | MachOper *_opnd_array[5]; |
| 12542 | public: |
| 12543 | MachOper *opnd_array(uint operand_index) const { |
| 12544 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12545 | return _opnd_array[operand_index]; |
| 12546 | } |
| 12547 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12548 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12549 | _opnd_array[operand_index] = operand; |
| 12550 | } |
| 12551 | private: |
| 12552 | const RegMask *_cisc_RegMask; |
| 12553 | virtual const RegMask &out_RegMask() const; |
| 12554 | virtual uint rule() const { return cmovL_regUCF_rule; } |
| 12555 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12556 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12557 | virtual int cisc_operand() const { return 4; } |
| 12558 | virtual MachNode *cisc_version(int offset); |
| 12559 | virtual void use_cisc_RegMask(); |
| 12560 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12561 | public: |
| 12562 | cmovL_regUCFNode() { _cisc_RegMask = NULL; _num_opnds = 5; _opnds = _opnd_array; } |
| 12563 | virtual uint size_of() const { return sizeof(cmovL_regUCFNode); } |
| 12564 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12565 | #ifndef PRODUCT |
| 12566 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12567 | virtual const char *Name() const { return "cmovL_regUCF";} |
| 12568 | #endif |
| 12569 | }; |
| 12570 | |
| 12571 | class cmovL_memUNode : public MachNode { |
| 12572 | private: |
| 12573 | MachOper *_opnd_array[5]; |
| 12574 | public: |
| 12575 | MachOper *opnd_array(uint operand_index) const { |
| 12576 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12577 | return _opnd_array[operand_index]; |
| 12578 | } |
| 12579 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12580 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12581 | _opnd_array[operand_index] = operand; |
| 12582 | } |
| 12583 | private: |
| 12584 | virtual const RegMask &out_RegMask() const; |
| 12585 | virtual uint rule() const { return cmovL_memU_rule; } |
| 12586 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12587 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12588 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12589 | virtual int reloc() const; |
| 12590 | virtual uint oper_input_base() const { return 2; } |
| 12591 | public: |
| 12592 | cmovL_memUNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12593 | virtual uint size_of() const { return sizeof(cmovL_memUNode); } |
| 12594 | static const Pipeline *pipeline_class(); |
| 12595 | virtual const Pipeline *pipeline() const; |
| 12596 | virtual const MachOper *memory_operand() const; |
| 12597 | #ifndef PRODUCT |
| 12598 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12599 | virtual const char *Name() const { return "cmovL_memU";} |
| 12600 | #endif |
| 12601 | }; |
| 12602 | |
| 12603 | class cmovL_memUCFNode : public MachNode { |
| 12604 | private: |
| 12605 | MachOper *_opnd_array[5]; |
| 12606 | public: |
| 12607 | MachOper *opnd_array(uint operand_index) const { |
| 12608 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12609 | return _opnd_array[operand_index]; |
| 12610 | } |
| 12611 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12612 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12613 | _opnd_array[operand_index] = operand; |
| 12614 | } |
| 12615 | private: |
| 12616 | virtual const RegMask &out_RegMask() const; |
| 12617 | virtual uint rule() const { return cmovL_memUCF_rule; } |
| 12618 | virtual int ideal_Opcode() const { return Op_CMoveL; } |
| 12619 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12620 | virtual int reloc() const; |
| 12621 | virtual uint oper_input_base() const { return 2; } |
| 12622 | public: |
| 12623 | cmovL_memUCFNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12624 | virtual uint size_of() const { return sizeof(cmovL_memUCFNode); } |
| 12625 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12626 | virtual const MachOper *memory_operand() const; |
| 12627 | #ifndef PRODUCT |
| 12628 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12629 | virtual const char *Name() const { return "cmovL_memUCF";} |
| 12630 | #endif |
| 12631 | }; |
| 12632 | |
| 12633 | class cmovF_regNode : public MachNode { |
| 12634 | private: |
| 12635 | MachOper *_opnd_array[5]; |
| 12636 | public: |
| 12637 | MachOper *opnd_array(uint operand_index) const { |
| 12638 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12639 | return _opnd_array[operand_index]; |
| 12640 | } |
| 12641 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12642 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12643 | _opnd_array[operand_index] = operand; |
| 12644 | } |
| 12645 | private: |
| 12646 | virtual const RegMask &out_RegMask() const; |
| 12647 | virtual uint rule() const { return cmovF_reg_rule; } |
| 12648 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12649 | virtual int ideal_Opcode() const { return Op_CMoveF; } |
| 12650 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12651 | public: |
| 12652 | cmovF_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12653 | virtual uint size_of() const { return sizeof(cmovF_regNode); } |
| 12654 | static const Pipeline *pipeline_class(); |
| 12655 | virtual const Pipeline *pipeline() const; |
| 12656 | #ifndef PRODUCT |
| 12657 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12658 | virtual const char *Name() const { return "cmovF_reg";} |
| 12659 | #endif |
| 12660 | }; |
| 12661 | |
| 12662 | class cmovF_regUNode : public MachNode { |
| 12663 | private: |
| 12664 | MachOper *_opnd_array[5]; |
| 12665 | public: |
| 12666 | MachOper *opnd_array(uint operand_index) const { |
| 12667 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12668 | return _opnd_array[operand_index]; |
| 12669 | } |
| 12670 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12671 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12672 | _opnd_array[operand_index] = operand; |
| 12673 | } |
| 12674 | private: |
| 12675 | virtual const RegMask &out_RegMask() const; |
| 12676 | virtual uint rule() const { return cmovF_regU_rule; } |
| 12677 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12678 | virtual int ideal_Opcode() const { return Op_CMoveF; } |
| 12679 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12680 | public: |
| 12681 | cmovF_regUNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12682 | virtual uint size_of() const { return sizeof(cmovF_regUNode); } |
| 12683 | static const Pipeline *pipeline_class(); |
| 12684 | virtual const Pipeline *pipeline() const; |
| 12685 | #ifndef PRODUCT |
| 12686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12687 | virtual const char *Name() const { return "cmovF_regU";} |
| 12688 | #endif |
| 12689 | }; |
| 12690 | |
| 12691 | class cmovF_regUCFNode : public MachNode { |
| 12692 | private: |
| 12693 | MachOper *_opnd_array[5]; |
| 12694 | public: |
| 12695 | MachOper *opnd_array(uint operand_index) const { |
| 12696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12697 | return _opnd_array[operand_index]; |
| 12698 | } |
| 12699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12701 | _opnd_array[operand_index] = operand; |
| 12702 | } |
| 12703 | private: |
| 12704 | virtual const RegMask &out_RegMask() const; |
| 12705 | virtual uint rule() const { return cmovF_regUCF_rule; } |
| 12706 | virtual int ideal_Opcode() const { return Op_CMoveF; } |
| 12707 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12708 | public: |
| 12709 | cmovF_regUCFNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12710 | virtual uint size_of() const { return sizeof(cmovF_regUCFNode); } |
| 12711 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12712 | #ifndef PRODUCT |
| 12713 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12714 | virtual const char *Name() const { return "cmovF_regUCF";} |
| 12715 | #endif |
| 12716 | }; |
| 12717 | |
| 12718 | class cmovD_regNode : public MachNode { |
| 12719 | private: |
| 12720 | MachOper *_opnd_array[5]; |
| 12721 | public: |
| 12722 | MachOper *opnd_array(uint operand_index) const { |
| 12723 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12724 | return _opnd_array[operand_index]; |
| 12725 | } |
| 12726 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12727 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12728 | _opnd_array[operand_index] = operand; |
| 12729 | } |
| 12730 | private: |
| 12731 | virtual const RegMask &out_RegMask() const; |
| 12732 | virtual uint rule() const { return cmovD_reg_rule; } |
| 12733 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12734 | virtual int ideal_Opcode() const { return Op_CMoveD; } |
| 12735 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12736 | public: |
| 12737 | cmovD_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12738 | virtual uint size_of() const { return sizeof(cmovD_regNode); } |
| 12739 | static const Pipeline *pipeline_class(); |
| 12740 | virtual const Pipeline *pipeline() const; |
| 12741 | #ifndef PRODUCT |
| 12742 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12743 | virtual const char *Name() const { return "cmovD_reg";} |
| 12744 | #endif |
| 12745 | }; |
| 12746 | |
| 12747 | class cmovD_regUNode : public MachNode { |
| 12748 | private: |
| 12749 | MachOper *_opnd_array[5]; |
| 12750 | public: |
| 12751 | MachOper *opnd_array(uint operand_index) const { |
| 12752 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12753 | return _opnd_array[operand_index]; |
| 12754 | } |
| 12755 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12756 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12757 | _opnd_array[operand_index] = operand; |
| 12758 | } |
| 12759 | private: |
| 12760 | virtual const RegMask &out_RegMask() const; |
| 12761 | virtual uint rule() const { return cmovD_regU_rule; } |
| 12762 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12763 | virtual int ideal_Opcode() const { return Op_CMoveD; } |
| 12764 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12765 | public: |
| 12766 | cmovD_regUNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12767 | virtual uint size_of() const { return sizeof(cmovD_regUNode); } |
| 12768 | static const Pipeline *pipeline_class(); |
| 12769 | virtual const Pipeline *pipeline() const; |
| 12770 | #ifndef PRODUCT |
| 12771 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12772 | virtual const char *Name() const { return "cmovD_regU";} |
| 12773 | #endif |
| 12774 | }; |
| 12775 | |
| 12776 | class cmovD_regUCFNode : public MachNode { |
| 12777 | private: |
| 12778 | MachOper *_opnd_array[5]; |
| 12779 | public: |
| 12780 | MachOper *opnd_array(uint operand_index) const { |
| 12781 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12782 | return _opnd_array[operand_index]; |
| 12783 | } |
| 12784 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12785 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12786 | _opnd_array[operand_index] = operand; |
| 12787 | } |
| 12788 | private: |
| 12789 | virtual const RegMask &out_RegMask() const; |
| 12790 | virtual uint rule() const { return cmovD_regUCF_rule; } |
| 12791 | virtual int ideal_Opcode() const { return Op_CMoveD; } |
| 12792 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 12793 | public: |
| 12794 | cmovD_regUCFNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 12795 | virtual uint size_of() const { return sizeof(cmovD_regUCFNode); } |
| 12796 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12797 | #ifndef PRODUCT |
| 12798 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12799 | virtual const char *Name() const { return "cmovD_regUCF";} |
| 12800 | #endif |
| 12801 | }; |
| 12802 | |
| 12803 | class addI_rRegNode : public MachNode { |
| 12804 | private: |
| 12805 | MachOper *_opnd_array[3]; |
| 12806 | public: |
| 12807 | MachOper *opnd_array(uint operand_index) const { |
| 12808 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12809 | return _opnd_array[operand_index]; |
| 12810 | } |
| 12811 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12813 | _opnd_array[operand_index] = operand; |
| 12814 | } |
| 12815 | private: |
| 12816 | const RegMask *_cisc_RegMask; |
| 12817 | virtual const RegMask &out_RegMask() const; |
| 12818 | virtual uint rule() const { return addI_rReg_rule; } |
| 12819 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12820 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 12821 | virtual uint two_adr() const { return oper_input_base(); } |
| 12822 | virtual int cisc_operand() const { return 2; } |
| 12823 | virtual MachNode *cisc_version(int offset); |
| 12824 | virtual void use_cisc_RegMask(); |
| 12825 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 12826 | public: |
| 12827 | addI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 12828 | virtual uint size_of() const { return sizeof(addI_rRegNode); } |
| 12829 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12830 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12831 | static const Pipeline *pipeline_class(); |
| 12832 | virtual const Pipeline *pipeline() const; |
| 12833 | #ifndef PRODUCT |
| 12834 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12835 | virtual const char *Name() const { return "addI_rReg";} |
| 12836 | #endif |
| 12837 | }; |
| 12838 | |
| 12839 | class addI_rReg_immNode : public MachNode { |
| 12840 | private: |
| 12841 | MachOper *_opnd_array[3]; |
| 12842 | public: |
| 12843 | MachOper *opnd_array(uint operand_index) const { |
| 12844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12845 | return _opnd_array[operand_index]; |
| 12846 | } |
| 12847 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12848 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12849 | _opnd_array[operand_index] = operand; |
| 12850 | } |
| 12851 | private: |
| 12852 | virtual const RegMask &out_RegMask() const; |
| 12853 | virtual uint rule() const { return addI_rReg_imm_rule; } |
| 12854 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12855 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 12856 | virtual uint two_adr() const { return oper_input_base(); } |
| 12857 | public: |
| 12858 | addI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 12859 | virtual uint size_of() const { return sizeof(addI_rReg_immNode); } |
| 12860 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12861 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12862 | static const Pipeline *pipeline_class(); |
| 12863 | virtual const Pipeline *pipeline() const; |
| 12864 | #ifndef PRODUCT |
| 12865 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12866 | virtual const char *Name() const { return "addI_rReg_imm";} |
| 12867 | #endif |
| 12868 | }; |
| 12869 | |
| 12870 | class addI_rReg_memNode : public MachNode { |
| 12871 | private: |
| 12872 | MachOper *_opnd_array[3]; |
| 12873 | public: |
| 12874 | MachOper *opnd_array(uint operand_index) const { |
| 12875 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12876 | return _opnd_array[operand_index]; |
| 12877 | } |
| 12878 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12879 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12880 | _opnd_array[operand_index] = operand; |
| 12881 | } |
| 12882 | private: |
| 12883 | virtual const RegMask &out_RegMask() const; |
| 12884 | virtual uint rule() const { return addI_rReg_mem_rule; } |
| 12885 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12886 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 12887 | virtual uint two_adr() const { return oper_input_base(); } |
| 12888 | virtual int reloc() const; |
| 12889 | virtual uint oper_input_base() const { return 2; } |
| 12890 | public: |
| 12891 | addI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 12892 | virtual uint size_of() const { return sizeof(addI_rReg_memNode); } |
| 12893 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12894 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12895 | static const Pipeline *pipeline_class(); |
| 12896 | virtual const Pipeline *pipeline() const; |
| 12897 | virtual const MachOper *memory_operand() const; |
| 12898 | #ifndef PRODUCT |
| 12899 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12900 | virtual const char *Name() const { return "addI_rReg_mem";} |
| 12901 | #endif |
| 12902 | }; |
| 12903 | |
| 12904 | class addI_rReg_mem_0Node : public MachNode { |
| 12905 | private: |
| 12906 | MachOper *_opnd_array[3]; |
| 12907 | public: |
| 12908 | MachOper *opnd_array(uint operand_index) const { |
| 12909 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12910 | return _opnd_array[operand_index]; |
| 12911 | } |
| 12912 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12913 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12914 | _opnd_array[operand_index] = operand; |
| 12915 | } |
| 12916 | private: |
| 12917 | virtual const RegMask &out_RegMask() const; |
| 12918 | virtual uint rule() const { return addI_rReg_mem_0_rule; } |
| 12919 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12920 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 12921 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 12922 | virtual int reloc() const; |
| 12923 | virtual uint oper_input_base() const { return 2; } |
| 12924 | public: |
| 12925 | addI_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 12926 | virtual uint size_of() const { return sizeof(addI_rReg_mem_0Node); } |
| 12927 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12928 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12929 | static const Pipeline *pipeline_class(); |
| 12930 | virtual const Pipeline *pipeline() const; |
| 12931 | virtual const MachOper *memory_operand() const; |
| 12932 | #ifndef PRODUCT |
| 12933 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12934 | virtual const char *Name() const { return "addI_rReg_mem_0";} |
| 12935 | #endif |
| 12936 | }; |
| 12937 | |
| 12938 | class addI_mem_rRegNode : public MachTypeNode { |
| 12939 | private: |
| 12940 | MachOper *_opnd_array[4]; |
| 12941 | public: |
| 12942 | MachOper *opnd_array(uint operand_index) const { |
| 12943 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12944 | return _opnd_array[operand_index]; |
| 12945 | } |
| 12946 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12947 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12948 | _opnd_array[operand_index] = operand; |
| 12949 | } |
| 12950 | private: |
| 12951 | virtual const RegMask &out_RegMask() const; |
| 12952 | virtual uint rule() const { return addI_mem_rReg_rule; } |
| 12953 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12954 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 12955 | virtual int reloc() const; |
| 12956 | virtual uint oper_input_base() const { return 2; } |
| 12957 | public: |
| 12958 | addI_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 12959 | virtual uint size_of() const { return sizeof(addI_mem_rRegNode); } |
| 12960 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12961 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12962 | static const Pipeline *pipeline_class(); |
| 12963 | virtual const Pipeline *pipeline() const; |
| 12964 | virtual const MachOper *memory_operand() const; |
| 12965 | #ifndef PRODUCT |
| 12966 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 12967 | virtual const char *Name() const { return "addI_mem_rReg";} |
| 12968 | #endif |
| 12969 | }; |
| 12970 | |
| 12971 | class addI_mem_rReg_0Node : public MachTypeNode { |
| 12972 | private: |
| 12973 | MachOper *_opnd_array[4]; |
| 12974 | public: |
| 12975 | MachOper *opnd_array(uint operand_index) const { |
| 12976 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12977 | return _opnd_array[operand_index]; |
| 12978 | } |
| 12979 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 12980 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 12981 | _opnd_array[operand_index] = operand; |
| 12982 | } |
| 12983 | private: |
| 12984 | virtual const RegMask &out_RegMask() const; |
| 12985 | virtual uint rule() const { return addI_mem_rReg_0_rule; } |
| 12986 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 12987 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 12988 | virtual int reloc() const; |
| 12989 | virtual uint oper_input_base() const { return 2; } |
| 12990 | public: |
| 12991 | addI_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 12992 | virtual uint size_of() const { return sizeof(addI_mem_rReg_0Node); } |
| 12993 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 12994 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 12995 | static const Pipeline *pipeline_class(); |
| 12996 | virtual const Pipeline *pipeline() const; |
| 12997 | virtual const MachOper *memory_operand() const; |
| 12998 | #ifndef PRODUCT |
| 12999 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13000 | virtual const char *Name() const { return "addI_mem_rReg_0";} |
| 13001 | #endif |
| 13002 | }; |
| 13003 | |
| 13004 | class addI_mem_immNode : public MachTypeNode { |
| 13005 | private: |
| 13006 | MachOper *_opnd_array[4]; |
| 13007 | public: |
| 13008 | MachOper *opnd_array(uint operand_index) const { |
| 13009 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13010 | return _opnd_array[operand_index]; |
| 13011 | } |
| 13012 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13013 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13014 | _opnd_array[operand_index] = operand; |
| 13015 | } |
| 13016 | private: |
| 13017 | virtual const RegMask &out_RegMask() const; |
| 13018 | virtual uint rule() const { return addI_mem_imm_rule; } |
| 13019 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13020 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 13021 | virtual int reloc() const; |
| 13022 | virtual uint oper_input_base() const { return 2; } |
| 13023 | public: |
| 13024 | addI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13025 | virtual uint size_of() const { return sizeof(addI_mem_immNode); } |
| 13026 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13027 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13028 | static const Pipeline *pipeline_class(); |
| 13029 | virtual const Pipeline *pipeline() const; |
| 13030 | virtual const MachOper *memory_operand() const; |
| 13031 | #ifndef PRODUCT |
| 13032 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13033 | virtual const char *Name() const { return "addI_mem_imm";} |
| 13034 | #endif |
| 13035 | }; |
| 13036 | |
| 13037 | class incI_rRegNode : public MachNode { |
| 13038 | private: |
| 13039 | MachOper *_opnd_array[3]; |
| 13040 | public: |
| 13041 | MachOper *opnd_array(uint operand_index) const { |
| 13042 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13043 | return _opnd_array[operand_index]; |
| 13044 | } |
| 13045 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13046 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13047 | _opnd_array[operand_index] = operand; |
| 13048 | } |
| 13049 | private: |
| 13050 | virtual const RegMask &out_RegMask() const; |
| 13051 | virtual uint rule() const { return incI_rReg_rule; } |
| 13052 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13053 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 13054 | virtual uint two_adr() const { return oper_input_base(); } |
| 13055 | public: |
| 13056 | incI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13057 | virtual uint size_of() const { return sizeof(incI_rRegNode); } |
| 13058 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13059 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13060 | static const Pipeline *pipeline_class(); |
| 13061 | virtual const Pipeline *pipeline() const; |
| 13062 | #ifndef PRODUCT |
| 13063 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13064 | virtual const char *Name() const { return "incI_rReg";} |
| 13065 | #endif |
| 13066 | }; |
| 13067 | |
| 13068 | class incI_memNode : public MachTypeNode { |
| 13069 | private: |
| 13070 | MachOper *_opnd_array[4]; |
| 13071 | public: |
| 13072 | MachOper *opnd_array(uint operand_index) const { |
| 13073 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13074 | return _opnd_array[operand_index]; |
| 13075 | } |
| 13076 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13077 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13078 | _opnd_array[operand_index] = operand; |
| 13079 | } |
| 13080 | private: |
| 13081 | virtual const RegMask &out_RegMask() const; |
| 13082 | virtual uint rule() const { return incI_mem_rule; } |
| 13083 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13084 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 13085 | virtual int reloc() const; |
| 13086 | virtual uint oper_input_base() const { return 2; } |
| 13087 | public: |
| 13088 | incI_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13089 | virtual uint size_of() const { return sizeof(incI_memNode); } |
| 13090 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13091 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13092 | static const Pipeline *pipeline_class(); |
| 13093 | virtual const Pipeline *pipeline() const; |
| 13094 | virtual const MachOper *memory_operand() const; |
| 13095 | #ifndef PRODUCT |
| 13096 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13097 | virtual const char *Name() const { return "incI_mem";} |
| 13098 | #endif |
| 13099 | }; |
| 13100 | |
| 13101 | class decI_rRegNode : public MachNode { |
| 13102 | private: |
| 13103 | MachOper *_opnd_array[3]; |
| 13104 | public: |
| 13105 | MachOper *opnd_array(uint operand_index) const { |
| 13106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13107 | return _opnd_array[operand_index]; |
| 13108 | } |
| 13109 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13110 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13111 | _opnd_array[operand_index] = operand; |
| 13112 | } |
| 13113 | private: |
| 13114 | virtual const RegMask &out_RegMask() const; |
| 13115 | virtual uint rule() const { return decI_rReg_rule; } |
| 13116 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13117 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 13118 | virtual uint two_adr() const { return oper_input_base(); } |
| 13119 | public: |
| 13120 | decI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13121 | virtual uint size_of() const { return sizeof(decI_rRegNode); } |
| 13122 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13123 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13124 | static const Pipeline *pipeline_class(); |
| 13125 | virtual const Pipeline *pipeline() const; |
| 13126 | #ifndef PRODUCT |
| 13127 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13128 | virtual const char *Name() const { return "decI_rReg";} |
| 13129 | #endif |
| 13130 | }; |
| 13131 | |
| 13132 | class decI_memNode : public MachTypeNode { |
| 13133 | private: |
| 13134 | MachOper *_opnd_array[4]; |
| 13135 | public: |
| 13136 | MachOper *opnd_array(uint operand_index) const { |
| 13137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13138 | return _opnd_array[operand_index]; |
| 13139 | } |
| 13140 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13141 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13142 | _opnd_array[operand_index] = operand; |
| 13143 | } |
| 13144 | private: |
| 13145 | virtual const RegMask &out_RegMask() const; |
| 13146 | virtual uint rule() const { return decI_mem_rule; } |
| 13147 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13148 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 13149 | virtual int reloc() const; |
| 13150 | virtual uint oper_input_base() const { return 2; } |
| 13151 | public: |
| 13152 | decI_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13153 | virtual uint size_of() const { return sizeof(decI_memNode); } |
| 13154 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13155 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13156 | static const Pipeline *pipeline_class(); |
| 13157 | virtual const Pipeline *pipeline() const; |
| 13158 | virtual const MachOper *memory_operand() const; |
| 13159 | #ifndef PRODUCT |
| 13160 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13161 | virtual const char *Name() const { return "decI_mem";} |
| 13162 | #endif |
| 13163 | }; |
| 13164 | |
| 13165 | class leaI_rReg_immINode : public MachNode { |
| 13166 | private: |
| 13167 | MachOper *_opnd_array[3]; |
| 13168 | public: |
| 13169 | MachOper *opnd_array(uint operand_index) const { |
| 13170 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13171 | return _opnd_array[operand_index]; |
| 13172 | } |
| 13173 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13174 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13175 | _opnd_array[operand_index] = operand; |
| 13176 | } |
| 13177 | private: |
| 13178 | virtual const RegMask &out_RegMask() const; |
| 13179 | virtual uint rule() const { return leaI_rReg_immI_rule; } |
| 13180 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13181 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 13182 | public: |
| 13183 | leaI_rReg_immINode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13184 | virtual uint size_of() const { return sizeof(leaI_rReg_immINode); } |
| 13185 | static const Pipeline *pipeline_class(); |
| 13186 | virtual const Pipeline *pipeline() const; |
| 13187 | #ifndef PRODUCT |
| 13188 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13189 | virtual const char *Name() const { return "leaI_rReg_immI";} |
| 13190 | #endif |
| 13191 | }; |
| 13192 | |
| 13193 | class addL_rRegNode : public MachNode { |
| 13194 | private: |
| 13195 | MachOper *_opnd_array[3]; |
| 13196 | public: |
| 13197 | MachOper *opnd_array(uint operand_index) const { |
| 13198 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13199 | return _opnd_array[operand_index]; |
| 13200 | } |
| 13201 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13202 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13203 | _opnd_array[operand_index] = operand; |
| 13204 | } |
| 13205 | private: |
| 13206 | const RegMask *_cisc_RegMask; |
| 13207 | virtual const RegMask &out_RegMask() const; |
| 13208 | virtual uint rule() const { return addL_rReg_rule; } |
| 13209 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13210 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13211 | virtual uint two_adr() const { return oper_input_base(); } |
| 13212 | virtual int cisc_operand() const { return 2; } |
| 13213 | virtual MachNode *cisc_version(int offset); |
| 13214 | virtual void use_cisc_RegMask(); |
| 13215 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 13216 | public: |
| 13217 | addL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 13218 | virtual uint size_of() const { return sizeof(addL_rRegNode); } |
| 13219 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13220 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13221 | static const Pipeline *pipeline_class(); |
| 13222 | virtual const Pipeline *pipeline() const; |
| 13223 | #ifndef PRODUCT |
| 13224 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13225 | virtual const char *Name() const { return "addL_rReg";} |
| 13226 | #endif |
| 13227 | }; |
| 13228 | |
| 13229 | class addL_rReg_immNode : public MachNode { |
| 13230 | private: |
| 13231 | MachOper *_opnd_array[3]; |
| 13232 | public: |
| 13233 | MachOper *opnd_array(uint operand_index) const { |
| 13234 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13235 | return _opnd_array[operand_index]; |
| 13236 | } |
| 13237 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13239 | _opnd_array[operand_index] = operand; |
| 13240 | } |
| 13241 | private: |
| 13242 | virtual const RegMask &out_RegMask() const; |
| 13243 | virtual uint rule() const { return addL_rReg_imm_rule; } |
| 13244 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13245 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13246 | virtual uint two_adr() const { return oper_input_base(); } |
| 13247 | public: |
| 13248 | addL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13249 | virtual uint size_of() const { return sizeof(addL_rReg_immNode); } |
| 13250 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13251 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13252 | static const Pipeline *pipeline_class(); |
| 13253 | virtual const Pipeline *pipeline() const; |
| 13254 | #ifndef PRODUCT |
| 13255 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13256 | virtual const char *Name() const { return "addL_rReg_imm";} |
| 13257 | #endif |
| 13258 | }; |
| 13259 | |
| 13260 | class addL_rReg_memNode : public MachNode { |
| 13261 | private: |
| 13262 | MachOper *_opnd_array[3]; |
| 13263 | public: |
| 13264 | MachOper *opnd_array(uint operand_index) const { |
| 13265 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13266 | return _opnd_array[operand_index]; |
| 13267 | } |
| 13268 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13269 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13270 | _opnd_array[operand_index] = operand; |
| 13271 | } |
| 13272 | private: |
| 13273 | virtual const RegMask &out_RegMask() const; |
| 13274 | virtual uint rule() const { return addL_rReg_mem_rule; } |
| 13275 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13276 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13277 | virtual uint two_adr() const { return oper_input_base(); } |
| 13278 | virtual int reloc() const; |
| 13279 | virtual uint oper_input_base() const { return 2; } |
| 13280 | public: |
| 13281 | addL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 13282 | virtual uint size_of() const { return sizeof(addL_rReg_memNode); } |
| 13283 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13284 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13285 | static const Pipeline *pipeline_class(); |
| 13286 | virtual const Pipeline *pipeline() const; |
| 13287 | virtual const MachOper *memory_operand() const; |
| 13288 | #ifndef PRODUCT |
| 13289 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13290 | virtual const char *Name() const { return "addL_rReg_mem";} |
| 13291 | #endif |
| 13292 | }; |
| 13293 | |
| 13294 | class addL_rReg_mem_0Node : public MachNode { |
| 13295 | private: |
| 13296 | MachOper *_opnd_array[3]; |
| 13297 | public: |
| 13298 | MachOper *opnd_array(uint operand_index) const { |
| 13299 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13300 | return _opnd_array[operand_index]; |
| 13301 | } |
| 13302 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13303 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13304 | _opnd_array[operand_index] = operand; |
| 13305 | } |
| 13306 | private: |
| 13307 | virtual const RegMask &out_RegMask() const; |
| 13308 | virtual uint rule() const { return addL_rReg_mem_0_rule; } |
| 13309 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13310 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13311 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 13312 | virtual int reloc() const; |
| 13313 | virtual uint oper_input_base() const { return 2; } |
| 13314 | public: |
| 13315 | addL_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13316 | virtual uint size_of() const { return sizeof(addL_rReg_mem_0Node); } |
| 13317 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13318 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13319 | static const Pipeline *pipeline_class(); |
| 13320 | virtual const Pipeline *pipeline() const; |
| 13321 | virtual const MachOper *memory_operand() const; |
| 13322 | #ifndef PRODUCT |
| 13323 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13324 | virtual const char *Name() const { return "addL_rReg_mem_0";} |
| 13325 | #endif |
| 13326 | }; |
| 13327 | |
| 13328 | class addL_mem_rRegNode : public MachTypeNode { |
| 13329 | private: |
| 13330 | MachOper *_opnd_array[4]; |
| 13331 | public: |
| 13332 | MachOper *opnd_array(uint operand_index) const { |
| 13333 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13334 | return _opnd_array[operand_index]; |
| 13335 | } |
| 13336 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13337 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13338 | _opnd_array[operand_index] = operand; |
| 13339 | } |
| 13340 | private: |
| 13341 | virtual const RegMask &out_RegMask() const; |
| 13342 | virtual uint rule() const { return addL_mem_rReg_rule; } |
| 13343 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13344 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 13345 | virtual int reloc() const; |
| 13346 | virtual uint oper_input_base() const { return 2; } |
| 13347 | public: |
| 13348 | addL_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13349 | virtual uint size_of() const { return sizeof(addL_mem_rRegNode); } |
| 13350 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13351 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13352 | static const Pipeline *pipeline_class(); |
| 13353 | virtual const Pipeline *pipeline() const; |
| 13354 | virtual const MachOper *memory_operand() const; |
| 13355 | #ifndef PRODUCT |
| 13356 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13357 | virtual const char *Name() const { return "addL_mem_rReg";} |
| 13358 | #endif |
| 13359 | }; |
| 13360 | |
| 13361 | class addL_mem_rReg_0Node : public MachTypeNode { |
| 13362 | private: |
| 13363 | MachOper *_opnd_array[4]; |
| 13364 | public: |
| 13365 | MachOper *opnd_array(uint operand_index) const { |
| 13366 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13367 | return _opnd_array[operand_index]; |
| 13368 | } |
| 13369 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13370 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13371 | _opnd_array[operand_index] = operand; |
| 13372 | } |
| 13373 | private: |
| 13374 | virtual const RegMask &out_RegMask() const; |
| 13375 | virtual uint rule() const { return addL_mem_rReg_0_rule; } |
| 13376 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13377 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 13378 | virtual int reloc() const; |
| 13379 | virtual uint oper_input_base() const { return 2; } |
| 13380 | public: |
| 13381 | addL_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13382 | virtual uint size_of() const { return sizeof(addL_mem_rReg_0Node); } |
| 13383 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13384 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13385 | static const Pipeline *pipeline_class(); |
| 13386 | virtual const Pipeline *pipeline() const; |
| 13387 | virtual const MachOper *memory_operand() const; |
| 13388 | #ifndef PRODUCT |
| 13389 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13390 | virtual const char *Name() const { return "addL_mem_rReg_0";} |
| 13391 | #endif |
| 13392 | }; |
| 13393 | |
| 13394 | class addL_mem_immNode : public MachTypeNode { |
| 13395 | private: |
| 13396 | MachOper *_opnd_array[4]; |
| 13397 | public: |
| 13398 | MachOper *opnd_array(uint operand_index) const { |
| 13399 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13400 | return _opnd_array[operand_index]; |
| 13401 | } |
| 13402 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13403 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13404 | _opnd_array[operand_index] = operand; |
| 13405 | } |
| 13406 | private: |
| 13407 | virtual const RegMask &out_RegMask() const; |
| 13408 | virtual uint rule() const { return addL_mem_imm_rule; } |
| 13409 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13410 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 13411 | virtual int reloc() const; |
| 13412 | virtual uint oper_input_base() const { return 2; } |
| 13413 | public: |
| 13414 | addL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13415 | virtual uint size_of() const { return sizeof(addL_mem_immNode); } |
| 13416 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13417 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13418 | static const Pipeline *pipeline_class(); |
| 13419 | virtual const Pipeline *pipeline() const; |
| 13420 | virtual const MachOper *memory_operand() const; |
| 13421 | #ifndef PRODUCT |
| 13422 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13423 | virtual const char *Name() const { return "addL_mem_imm";} |
| 13424 | #endif |
| 13425 | }; |
| 13426 | |
| 13427 | class incL_rRegNode : public MachNode { |
| 13428 | private: |
| 13429 | MachOper *_opnd_array[3]; |
| 13430 | public: |
| 13431 | MachOper *opnd_array(uint operand_index) const { |
| 13432 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13433 | return _opnd_array[operand_index]; |
| 13434 | } |
| 13435 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13436 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13437 | _opnd_array[operand_index] = operand; |
| 13438 | } |
| 13439 | private: |
| 13440 | virtual const RegMask &out_RegMask() const; |
| 13441 | virtual uint rule() const { return incL_rReg_rule; } |
| 13442 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13443 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13444 | virtual uint two_adr() const { return oper_input_base(); } |
| 13445 | public: |
| 13446 | incL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13447 | virtual uint size_of() const { return sizeof(incL_rRegNode); } |
| 13448 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13449 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13450 | static const Pipeline *pipeline_class(); |
| 13451 | virtual const Pipeline *pipeline() const; |
| 13452 | #ifndef PRODUCT |
| 13453 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13454 | virtual const char *Name() const { return "incL_rReg";} |
| 13455 | #endif |
| 13456 | }; |
| 13457 | |
| 13458 | class incL_memNode : public MachTypeNode { |
| 13459 | private: |
| 13460 | MachOper *_opnd_array[4]; |
| 13461 | public: |
| 13462 | MachOper *opnd_array(uint operand_index) const { |
| 13463 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13464 | return _opnd_array[operand_index]; |
| 13465 | } |
| 13466 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13467 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13468 | _opnd_array[operand_index] = operand; |
| 13469 | } |
| 13470 | private: |
| 13471 | virtual const RegMask &out_RegMask() const; |
| 13472 | virtual uint rule() const { return incL_mem_rule; } |
| 13473 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13474 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 13475 | virtual int reloc() const; |
| 13476 | virtual uint oper_input_base() const { return 2; } |
| 13477 | public: |
| 13478 | incL_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13479 | virtual uint size_of() const { return sizeof(incL_memNode); } |
| 13480 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13481 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13482 | static const Pipeline *pipeline_class(); |
| 13483 | virtual const Pipeline *pipeline() const; |
| 13484 | virtual const MachOper *memory_operand() const; |
| 13485 | #ifndef PRODUCT |
| 13486 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13487 | virtual const char *Name() const { return "incL_mem";} |
| 13488 | #endif |
| 13489 | }; |
| 13490 | |
| 13491 | class decL_rRegNode : public MachNode { |
| 13492 | private: |
| 13493 | MachOper *_opnd_array[3]; |
| 13494 | public: |
| 13495 | MachOper *opnd_array(uint operand_index) const { |
| 13496 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13497 | return _opnd_array[operand_index]; |
| 13498 | } |
| 13499 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13500 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13501 | _opnd_array[operand_index] = operand; |
| 13502 | } |
| 13503 | private: |
| 13504 | virtual const RegMask &out_RegMask() const; |
| 13505 | virtual uint rule() const { return decL_rReg_rule; } |
| 13506 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13507 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13508 | virtual uint two_adr() const { return oper_input_base(); } |
| 13509 | public: |
| 13510 | decL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13511 | virtual uint size_of() const { return sizeof(decL_rRegNode); } |
| 13512 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13513 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13514 | static const Pipeline *pipeline_class(); |
| 13515 | virtual const Pipeline *pipeline() const; |
| 13516 | #ifndef PRODUCT |
| 13517 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13518 | virtual const char *Name() const { return "decL_rReg";} |
| 13519 | #endif |
| 13520 | }; |
| 13521 | |
| 13522 | class decL_memNode : public MachTypeNode { |
| 13523 | private: |
| 13524 | MachOper *_opnd_array[4]; |
| 13525 | public: |
| 13526 | MachOper *opnd_array(uint operand_index) const { |
| 13527 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13528 | return _opnd_array[operand_index]; |
| 13529 | } |
| 13530 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13531 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13532 | _opnd_array[operand_index] = operand; |
| 13533 | } |
| 13534 | private: |
| 13535 | virtual const RegMask &out_RegMask() const; |
| 13536 | virtual uint rule() const { return decL_mem_rule; } |
| 13537 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13538 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 13539 | virtual int reloc() const; |
| 13540 | virtual uint oper_input_base() const { return 2; } |
| 13541 | public: |
| 13542 | decL_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 13543 | virtual uint size_of() const { return sizeof(decL_memNode); } |
| 13544 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13545 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13546 | static const Pipeline *pipeline_class(); |
| 13547 | virtual const Pipeline *pipeline() const; |
| 13548 | virtual const MachOper *memory_operand() const; |
| 13549 | #ifndef PRODUCT |
| 13550 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13551 | virtual const char *Name() const { return "decL_mem";} |
| 13552 | #endif |
| 13553 | }; |
| 13554 | |
| 13555 | class leaL_rReg_immLNode : public MachNode { |
| 13556 | private: |
| 13557 | MachOper *_opnd_array[3]; |
| 13558 | public: |
| 13559 | MachOper *opnd_array(uint operand_index) const { |
| 13560 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13561 | return _opnd_array[operand_index]; |
| 13562 | } |
| 13563 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13564 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13565 | _opnd_array[operand_index] = operand; |
| 13566 | } |
| 13567 | private: |
| 13568 | virtual const RegMask &out_RegMask() const; |
| 13569 | virtual uint rule() const { return leaL_rReg_immL_rule; } |
| 13570 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13571 | virtual int ideal_Opcode() const { return Op_AddL; } |
| 13572 | public: |
| 13573 | leaL_rReg_immLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13574 | virtual uint size_of() const { return sizeof(leaL_rReg_immLNode); } |
| 13575 | static const Pipeline *pipeline_class(); |
| 13576 | virtual const Pipeline *pipeline() const; |
| 13577 | #ifndef PRODUCT |
| 13578 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13579 | virtual const char *Name() const { return "leaL_rReg_immL";} |
| 13580 | #endif |
| 13581 | }; |
| 13582 | |
| 13583 | class addP_rRegNode : public MachTypeNode { |
| 13584 | private: |
| 13585 | MachOper *_opnd_array[3]; |
| 13586 | public: |
| 13587 | MachOper *opnd_array(uint operand_index) const { |
| 13588 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13589 | return _opnd_array[operand_index]; |
| 13590 | } |
| 13591 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13592 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13593 | _opnd_array[operand_index] = operand; |
| 13594 | } |
| 13595 | private: |
| 13596 | virtual const RegMask &out_RegMask() const; |
| 13597 | virtual uint rule() const { return addP_rReg_rule; } |
| 13598 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13599 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 13600 | virtual uint two_adr() const { return oper_input_base(); } |
| 13601 | virtual uint oper_input_base() const { return 2; } |
| 13602 | public: |
| 13603 | addP_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13604 | virtual uint size_of() const { return sizeof(addP_rRegNode); } |
| 13605 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13606 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13607 | static const Pipeline *pipeline_class(); |
| 13608 | virtual const Pipeline *pipeline() const; |
| 13609 | #ifndef PRODUCT |
| 13610 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13611 | virtual const char *Name() const { return "addP_rReg";} |
| 13612 | #endif |
| 13613 | }; |
| 13614 | |
| 13615 | class addP_rReg_immNode : public MachTypeNode { |
| 13616 | private: |
| 13617 | MachOper *_opnd_array[3]; |
| 13618 | public: |
| 13619 | MachOper *opnd_array(uint operand_index) const { |
| 13620 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13621 | return _opnd_array[operand_index]; |
| 13622 | } |
| 13623 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13624 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13625 | _opnd_array[operand_index] = operand; |
| 13626 | } |
| 13627 | private: |
| 13628 | virtual const RegMask &out_RegMask() const; |
| 13629 | virtual uint rule() const { return addP_rReg_imm_rule; } |
| 13630 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13631 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 13632 | virtual uint two_adr() const { return oper_input_base(); } |
| 13633 | virtual uint oper_input_base() const { return 2; } |
| 13634 | public: |
| 13635 | addP_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13636 | virtual uint size_of() const { return sizeof(addP_rReg_immNode); } |
| 13637 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13638 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13639 | static const Pipeline *pipeline_class(); |
| 13640 | virtual const Pipeline *pipeline() const; |
| 13641 | #ifndef PRODUCT |
| 13642 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13643 | virtual const char *Name() const { return "addP_rReg_imm";} |
| 13644 | #endif |
| 13645 | }; |
| 13646 | |
| 13647 | class leaP_rReg_immNode : public MachTypeNode { |
| 13648 | private: |
| 13649 | MachOper *_opnd_array[3]; |
| 13650 | public: |
| 13651 | MachOper *opnd_array(uint operand_index) const { |
| 13652 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13653 | return _opnd_array[operand_index]; |
| 13654 | } |
| 13655 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13656 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13657 | _opnd_array[operand_index] = operand; |
| 13658 | } |
| 13659 | private: |
| 13660 | virtual const RegMask &out_RegMask() const; |
| 13661 | virtual uint rule() const { return leaP_rReg_imm_rule; } |
| 13662 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13663 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 13664 | virtual uint oper_input_base() const { return 2; } |
| 13665 | public: |
| 13666 | leaP_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 13667 | virtual uint size_of() const { return sizeof(leaP_rReg_immNode); } |
| 13668 | static const Pipeline *pipeline_class(); |
| 13669 | virtual const Pipeline *pipeline() const; |
| 13670 | #ifndef PRODUCT |
| 13671 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13672 | virtual const char *Name() const { return "leaP_rReg_imm";} |
| 13673 | #endif |
| 13674 | }; |
| 13675 | |
| 13676 | class checkCastPPNode : public MachTypeNode { |
| 13677 | private: |
| 13678 | MachOper *_opnd_array[2]; |
| 13679 | public: |
| 13680 | MachOper *opnd_array(uint operand_index) const { |
| 13681 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13682 | return _opnd_array[operand_index]; |
| 13683 | } |
| 13684 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13685 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13686 | _opnd_array[operand_index] = operand; |
| 13687 | } |
| 13688 | private: |
| 13689 | virtual const RegMask &out_RegMask() const; |
| 13690 | virtual uint rule() const { return checkCastPP_rule; } |
| 13691 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13692 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 13693 | virtual int ideal_Opcode() const { return Op_CheckCastPP; } |
| 13694 | virtual uint two_adr() const { return oper_input_base(); } |
| 13695 | virtual uint oper_input_base() const { return 1; } |
| 13696 | public: |
| 13697 | checkCastPPNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 13698 | virtual uint size_of() const { return sizeof(checkCastPPNode); } |
| 13699 | // Rematerialize checkCastPP |
| 13700 | static const Pipeline *pipeline_class(); |
| 13701 | virtual const Pipeline *pipeline() const; |
| 13702 | #ifndef PRODUCT |
| 13703 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13704 | virtual const char *Name() const { return "checkCastPP";} |
| 13705 | #endif |
| 13706 | }; |
| 13707 | |
| 13708 | class castPPNode : public MachTypeNode { |
| 13709 | private: |
| 13710 | MachOper *_opnd_array[2]; |
| 13711 | public: |
| 13712 | MachOper *opnd_array(uint operand_index) const { |
| 13713 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13714 | return _opnd_array[operand_index]; |
| 13715 | } |
| 13716 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13717 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13718 | _opnd_array[operand_index] = operand; |
| 13719 | } |
| 13720 | private: |
| 13721 | virtual const RegMask &out_RegMask() const; |
| 13722 | virtual uint rule() const { return castPP_rule; } |
| 13723 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13724 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 13725 | virtual int ideal_Opcode() const { return Op_CastPP; } |
| 13726 | virtual uint two_adr() const { return oper_input_base(); } |
| 13727 | virtual uint oper_input_base() const { return 1; } |
| 13728 | public: |
| 13729 | castPPNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 13730 | virtual uint size_of() const { return sizeof(castPPNode); } |
| 13731 | // Rematerialize castPP |
| 13732 | static const Pipeline *pipeline_class(); |
| 13733 | virtual const Pipeline *pipeline() const; |
| 13734 | #ifndef PRODUCT |
| 13735 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13736 | virtual const char *Name() const { return "castPP";} |
| 13737 | #endif |
| 13738 | }; |
| 13739 | |
| 13740 | class castIINode : public MachNode { |
| 13741 | private: |
| 13742 | MachOper *_opnd_array[2]; |
| 13743 | public: |
| 13744 | MachOper *opnd_array(uint operand_index) const { |
| 13745 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13746 | return _opnd_array[operand_index]; |
| 13747 | } |
| 13748 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13750 | _opnd_array[operand_index] = operand; |
| 13751 | } |
| 13752 | private: |
| 13753 | virtual const RegMask &out_RegMask() const; |
| 13754 | virtual uint rule() const { return castII_rule; } |
| 13755 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13756 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 13757 | virtual int ideal_Opcode() const { return Op_CastII; } |
| 13758 | virtual uint two_adr() const { return oper_input_base(); } |
| 13759 | public: |
| 13760 | castIINode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 13761 | virtual uint size_of() const { return sizeof(castIINode); } |
| 13762 | // Rematerialize castII |
| 13763 | static const Pipeline *pipeline_class(); |
| 13764 | virtual const Pipeline *pipeline() const; |
| 13765 | #ifndef PRODUCT |
| 13766 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13767 | virtual const char *Name() const { return "castII";} |
| 13768 | #endif |
| 13769 | }; |
| 13770 | |
| 13771 | class loadPLockedNode : public MachTypeNode { |
| 13772 | private: |
| 13773 | MachOper *_opnd_array[2]; |
| 13774 | public: |
| 13775 | MachOper *opnd_array(uint operand_index) const { |
| 13776 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13777 | return _opnd_array[operand_index]; |
| 13778 | } |
| 13779 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13780 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13781 | _opnd_array[operand_index] = operand; |
| 13782 | } |
| 13783 | private: |
| 13784 | virtual const RegMask &out_RegMask() const; |
| 13785 | virtual uint rule() const { return loadPLocked_rule; } |
| 13786 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13787 | virtual int ideal_Opcode() const { return Op_LoadPLocked; } |
| 13788 | virtual int reloc() const; |
| 13789 | virtual uint oper_input_base() const { return 2; } |
| 13790 | public: |
| 13791 | loadPLockedNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13792 | virtual uint size_of() const { return sizeof(loadPLockedNode); } |
| 13793 | static const Pipeline *pipeline_class(); |
| 13794 | virtual const Pipeline *pipeline() const; |
| 13795 | virtual const MachOper *memory_operand() const; |
| 13796 | #ifndef PRODUCT |
| 13797 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13798 | virtual const char *Name() const { return "loadPLocked";} |
| 13799 | #endif |
| 13800 | }; |
| 13801 | |
| 13802 | class storePConditionalNode : public MachNode { |
| 13803 | private: |
| 13804 | MachOper *_opnd_array[4]; |
| 13805 | public: |
| 13806 | MachOper *opnd_array(uint operand_index) const { |
| 13807 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13808 | return _opnd_array[operand_index]; |
| 13809 | } |
| 13810 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13811 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13812 | _opnd_array[operand_index] = operand; |
| 13813 | } |
| 13814 | private: |
| 13815 | virtual const RegMask &out_RegMask() const; |
| 13816 | virtual uint rule() const { return storePConditional_rule; } |
| 13817 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13818 | virtual int ideal_Opcode() const { return Op_StorePConditional; } |
| 13819 | virtual int reloc() const; |
| 13820 | virtual uint oper_input_base() const { return 2; } |
| 13821 | public: |
| 13822 | storePConditionalNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13823 | virtual uint size_of() const { return sizeof(storePConditionalNode); } |
| 13824 | // Rematerialize storePConditional |
| 13825 | static const Pipeline *pipeline_class(); |
| 13826 | virtual const Pipeline *pipeline() const; |
| 13827 | virtual const MachOper *memory_operand() const; |
| 13828 | #ifndef PRODUCT |
| 13829 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13830 | virtual const char *Name() const { return "storePConditional";} |
| 13831 | #endif |
| 13832 | }; |
| 13833 | |
| 13834 | class storeIConditionalNode : public MachNode { |
| 13835 | private: |
| 13836 | MachOper *_opnd_array[4]; |
| 13837 | public: |
| 13838 | MachOper *opnd_array(uint operand_index) const { |
| 13839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13840 | return _opnd_array[operand_index]; |
| 13841 | } |
| 13842 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13843 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13844 | _opnd_array[operand_index] = operand; |
| 13845 | } |
| 13846 | private: |
| 13847 | virtual const RegMask &out_RegMask() const; |
| 13848 | virtual uint rule() const { return storeIConditional_rule; } |
| 13849 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13850 | virtual int ideal_Opcode() const { return Op_StoreIConditional; } |
| 13851 | virtual int reloc() const; |
| 13852 | virtual uint oper_input_base() const { return 2; } |
| 13853 | public: |
| 13854 | storeIConditionalNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13855 | virtual uint size_of() const { return sizeof(storeIConditionalNode); } |
| 13856 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13857 | // Rematerialize storeIConditional |
| 13858 | static const Pipeline *pipeline_class(); |
| 13859 | virtual const Pipeline *pipeline() const; |
| 13860 | virtual const MachOper *memory_operand() const; |
| 13861 | #ifndef PRODUCT |
| 13862 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13863 | virtual const char *Name() const { return "storeIConditional";} |
| 13864 | #endif |
| 13865 | }; |
| 13866 | |
| 13867 | class storeLConditionalNode : public MachNode { |
| 13868 | private: |
| 13869 | MachOper *_opnd_array[4]; |
| 13870 | public: |
| 13871 | MachOper *opnd_array(uint operand_index) const { |
| 13872 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13873 | return _opnd_array[operand_index]; |
| 13874 | } |
| 13875 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13876 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13877 | _opnd_array[operand_index] = operand; |
| 13878 | } |
| 13879 | private: |
| 13880 | virtual const RegMask &out_RegMask() const; |
| 13881 | virtual uint rule() const { return storeLConditional_rule; } |
| 13882 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13883 | virtual int ideal_Opcode() const { return Op_StoreLConditional; } |
| 13884 | virtual int reloc() const; |
| 13885 | virtual uint oper_input_base() const { return 2; } |
| 13886 | public: |
| 13887 | storeLConditionalNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13888 | virtual uint size_of() const { return sizeof(storeLConditionalNode); } |
| 13889 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13890 | // Rematerialize storeLConditional |
| 13891 | static const Pipeline *pipeline_class(); |
| 13892 | virtual const Pipeline *pipeline() const; |
| 13893 | virtual const MachOper *memory_operand() const; |
| 13894 | #ifndef PRODUCT |
| 13895 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13896 | virtual const char *Name() const { return "storeLConditional";} |
| 13897 | #endif |
| 13898 | }; |
| 13899 | |
| 13900 | class compareAndSwapPNode : public MachNode { |
| 13901 | private: |
| 13902 | MachOper *_opnd_array[4]; |
| 13903 | public: |
| 13904 | MachOper *opnd_array(uint operand_index) const { |
| 13905 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13906 | return _opnd_array[operand_index]; |
| 13907 | } |
| 13908 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13909 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13910 | _opnd_array[operand_index] = operand; |
| 13911 | } |
| 13912 | private: |
| 13913 | virtual const RegMask &out_RegMask() const; |
| 13914 | virtual uint rule() const { return compareAndSwapP_rule; } |
| 13915 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13916 | virtual int ideal_Opcode() const { return Op_CompareAndSwapP; } |
| 13917 | virtual int reloc() const; |
| 13918 | virtual uint oper_input_base() const { return 2; } |
| 13919 | public: |
| 13920 | compareAndSwapPNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13921 | virtual uint size_of() const { return sizeof(compareAndSwapPNode); } |
| 13922 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13923 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13924 | static const Pipeline *pipeline_class(); |
| 13925 | virtual const Pipeline *pipeline() const; |
| 13926 | virtual const MachOper *memory_operand() const; |
| 13927 | #ifndef PRODUCT |
| 13928 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13929 | virtual const char *Name() const { return "compareAndSwapP";} |
| 13930 | #endif |
| 13931 | }; |
| 13932 | |
| 13933 | class compareAndSwapP_0Node : public MachNode { |
| 13934 | private: |
| 13935 | MachOper *_opnd_array[4]; |
| 13936 | public: |
| 13937 | MachOper *opnd_array(uint operand_index) const { |
| 13938 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13939 | return _opnd_array[operand_index]; |
| 13940 | } |
| 13941 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13942 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13943 | _opnd_array[operand_index] = operand; |
| 13944 | } |
| 13945 | private: |
| 13946 | virtual const RegMask &out_RegMask() const; |
| 13947 | virtual uint rule() const { return compareAndSwapP_0_rule; } |
| 13948 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13949 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapP; } |
| 13950 | virtual int reloc() const; |
| 13951 | virtual uint oper_input_base() const { return 2; } |
| 13952 | public: |
| 13953 | compareAndSwapP_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13954 | virtual uint size_of() const { return sizeof(compareAndSwapP_0Node); } |
| 13955 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13956 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13957 | static const Pipeline *pipeline_class(); |
| 13958 | virtual const Pipeline *pipeline() const; |
| 13959 | virtual const MachOper *memory_operand() const; |
| 13960 | #ifndef PRODUCT |
| 13961 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13962 | virtual const char *Name() const { return "compareAndSwapP_0";} |
| 13963 | #endif |
| 13964 | }; |
| 13965 | |
| 13966 | class compareAndSwapLNode : public MachNode { |
| 13967 | private: |
| 13968 | MachOper *_opnd_array[4]; |
| 13969 | public: |
| 13970 | MachOper *opnd_array(uint operand_index) const { |
| 13971 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13972 | return _opnd_array[operand_index]; |
| 13973 | } |
| 13974 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 13975 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 13976 | _opnd_array[operand_index] = operand; |
| 13977 | } |
| 13978 | private: |
| 13979 | virtual const RegMask &out_RegMask() const; |
| 13980 | virtual uint rule() const { return compareAndSwapL_rule; } |
| 13981 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 13982 | virtual int ideal_Opcode() const { return Op_CompareAndSwapL; } |
| 13983 | virtual int reloc() const; |
| 13984 | virtual uint oper_input_base() const { return 2; } |
| 13985 | public: |
| 13986 | compareAndSwapLNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 13987 | virtual uint size_of() const { return sizeof(compareAndSwapLNode); } |
| 13988 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 13989 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 13990 | static const Pipeline *pipeline_class(); |
| 13991 | virtual const Pipeline *pipeline() const; |
| 13992 | virtual const MachOper *memory_operand() const; |
| 13993 | #ifndef PRODUCT |
| 13994 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 13995 | virtual const char *Name() const { return "compareAndSwapL";} |
| 13996 | #endif |
| 13997 | }; |
| 13998 | |
| 13999 | class compareAndSwapL_0Node : public MachNode { |
| 14000 | private: |
| 14001 | MachOper *_opnd_array[4]; |
| 14002 | public: |
| 14003 | MachOper *opnd_array(uint operand_index) const { |
| 14004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14005 | return _opnd_array[operand_index]; |
| 14006 | } |
| 14007 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14008 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14009 | _opnd_array[operand_index] = operand; |
| 14010 | } |
| 14011 | private: |
| 14012 | virtual const RegMask &out_RegMask() const; |
| 14013 | virtual uint rule() const { return compareAndSwapL_0_rule; } |
| 14014 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14015 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapL; } |
| 14016 | virtual int reloc() const; |
| 14017 | virtual uint oper_input_base() const { return 2; } |
| 14018 | public: |
| 14019 | compareAndSwapL_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14020 | virtual uint size_of() const { return sizeof(compareAndSwapL_0Node); } |
| 14021 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14022 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14023 | static const Pipeline *pipeline_class(); |
| 14024 | virtual const Pipeline *pipeline() const; |
| 14025 | virtual const MachOper *memory_operand() const; |
| 14026 | #ifndef PRODUCT |
| 14027 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14028 | virtual const char *Name() const { return "compareAndSwapL_0";} |
| 14029 | #endif |
| 14030 | }; |
| 14031 | |
| 14032 | class compareAndSwapINode : public MachNode { |
| 14033 | private: |
| 14034 | MachOper *_opnd_array[4]; |
| 14035 | public: |
| 14036 | MachOper *opnd_array(uint operand_index) const { |
| 14037 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14038 | return _opnd_array[operand_index]; |
| 14039 | } |
| 14040 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14041 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14042 | _opnd_array[operand_index] = operand; |
| 14043 | } |
| 14044 | private: |
| 14045 | virtual const RegMask &out_RegMask() const; |
| 14046 | virtual uint rule() const { return compareAndSwapI_rule; } |
| 14047 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14048 | virtual int ideal_Opcode() const { return Op_CompareAndSwapI; } |
| 14049 | virtual int reloc() const; |
| 14050 | virtual uint oper_input_base() const { return 2; } |
| 14051 | public: |
| 14052 | compareAndSwapINode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14053 | virtual uint size_of() const { return sizeof(compareAndSwapINode); } |
| 14054 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14055 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14056 | static const Pipeline *pipeline_class(); |
| 14057 | virtual const Pipeline *pipeline() const; |
| 14058 | virtual const MachOper *memory_operand() const; |
| 14059 | #ifndef PRODUCT |
| 14060 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14061 | virtual const char *Name() const { return "compareAndSwapI";} |
| 14062 | #endif |
| 14063 | }; |
| 14064 | |
| 14065 | class compareAndSwapI_0Node : public MachNode { |
| 14066 | private: |
| 14067 | MachOper *_opnd_array[4]; |
| 14068 | public: |
| 14069 | MachOper *opnd_array(uint operand_index) const { |
| 14070 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14071 | return _opnd_array[operand_index]; |
| 14072 | } |
| 14073 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14075 | _opnd_array[operand_index] = operand; |
| 14076 | } |
| 14077 | private: |
| 14078 | virtual const RegMask &out_RegMask() const; |
| 14079 | virtual uint rule() const { return compareAndSwapI_0_rule; } |
| 14080 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14081 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapI; } |
| 14082 | virtual int reloc() const; |
| 14083 | virtual uint oper_input_base() const { return 2; } |
| 14084 | public: |
| 14085 | compareAndSwapI_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14086 | virtual uint size_of() const { return sizeof(compareAndSwapI_0Node); } |
| 14087 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14088 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14089 | static const Pipeline *pipeline_class(); |
| 14090 | virtual const Pipeline *pipeline() const; |
| 14091 | virtual const MachOper *memory_operand() const; |
| 14092 | #ifndef PRODUCT |
| 14093 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14094 | virtual const char *Name() const { return "compareAndSwapI_0";} |
| 14095 | #endif |
| 14096 | }; |
| 14097 | |
| 14098 | class compareAndSwapBNode : public MachNode { |
| 14099 | private: |
| 14100 | MachOper *_opnd_array[4]; |
| 14101 | public: |
| 14102 | MachOper *opnd_array(uint operand_index) const { |
| 14103 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14104 | return _opnd_array[operand_index]; |
| 14105 | } |
| 14106 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14107 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14108 | _opnd_array[operand_index] = operand; |
| 14109 | } |
| 14110 | private: |
| 14111 | virtual const RegMask &out_RegMask() const; |
| 14112 | virtual uint rule() const { return compareAndSwapB_rule; } |
| 14113 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14114 | virtual int ideal_Opcode() const { return Op_CompareAndSwapB; } |
| 14115 | virtual int reloc() const; |
| 14116 | virtual uint oper_input_base() const { return 2; } |
| 14117 | public: |
| 14118 | compareAndSwapBNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14119 | virtual uint size_of() const { return sizeof(compareAndSwapBNode); } |
| 14120 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14121 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14122 | static const Pipeline *pipeline_class(); |
| 14123 | virtual const Pipeline *pipeline() const; |
| 14124 | virtual const MachOper *memory_operand() const; |
| 14125 | #ifndef PRODUCT |
| 14126 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14127 | virtual const char *Name() const { return "compareAndSwapB";} |
| 14128 | #endif |
| 14129 | }; |
| 14130 | |
| 14131 | class compareAndSwapB_0Node : public MachNode { |
| 14132 | private: |
| 14133 | MachOper *_opnd_array[4]; |
| 14134 | public: |
| 14135 | MachOper *opnd_array(uint operand_index) const { |
| 14136 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14137 | return _opnd_array[operand_index]; |
| 14138 | } |
| 14139 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14140 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14141 | _opnd_array[operand_index] = operand; |
| 14142 | } |
| 14143 | private: |
| 14144 | virtual const RegMask &out_RegMask() const; |
| 14145 | virtual uint rule() const { return compareAndSwapB_0_rule; } |
| 14146 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14147 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapB; } |
| 14148 | virtual int reloc() const; |
| 14149 | virtual uint oper_input_base() const { return 2; } |
| 14150 | public: |
| 14151 | compareAndSwapB_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14152 | virtual uint size_of() const { return sizeof(compareAndSwapB_0Node); } |
| 14153 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14154 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14155 | static const Pipeline *pipeline_class(); |
| 14156 | virtual const Pipeline *pipeline() const; |
| 14157 | virtual const MachOper *memory_operand() const; |
| 14158 | #ifndef PRODUCT |
| 14159 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14160 | virtual const char *Name() const { return "compareAndSwapB_0";} |
| 14161 | #endif |
| 14162 | }; |
| 14163 | |
| 14164 | class compareAndSwapSNode : public MachNode { |
| 14165 | private: |
| 14166 | MachOper *_opnd_array[4]; |
| 14167 | public: |
| 14168 | MachOper *opnd_array(uint operand_index) const { |
| 14169 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14170 | return _opnd_array[operand_index]; |
| 14171 | } |
| 14172 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14173 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14174 | _opnd_array[operand_index] = operand; |
| 14175 | } |
| 14176 | private: |
| 14177 | virtual const RegMask &out_RegMask() const; |
| 14178 | virtual uint rule() const { return compareAndSwapS_rule; } |
| 14179 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14180 | virtual int ideal_Opcode() const { return Op_CompareAndSwapS; } |
| 14181 | virtual int reloc() const; |
| 14182 | virtual uint oper_input_base() const { return 2; } |
| 14183 | public: |
| 14184 | compareAndSwapSNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14185 | virtual uint size_of() const { return sizeof(compareAndSwapSNode); } |
| 14186 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14187 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14188 | static const Pipeline *pipeline_class(); |
| 14189 | virtual const Pipeline *pipeline() const; |
| 14190 | virtual const MachOper *memory_operand() const; |
| 14191 | #ifndef PRODUCT |
| 14192 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14193 | virtual const char *Name() const { return "compareAndSwapS";} |
| 14194 | #endif |
| 14195 | }; |
| 14196 | |
| 14197 | class compareAndSwapS_0Node : public MachNode { |
| 14198 | private: |
| 14199 | MachOper *_opnd_array[4]; |
| 14200 | public: |
| 14201 | MachOper *opnd_array(uint operand_index) const { |
| 14202 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14203 | return _opnd_array[operand_index]; |
| 14204 | } |
| 14205 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14206 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14207 | _opnd_array[operand_index] = operand; |
| 14208 | } |
| 14209 | private: |
| 14210 | virtual const RegMask &out_RegMask() const; |
| 14211 | virtual uint rule() const { return compareAndSwapS_0_rule; } |
| 14212 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14213 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapS; } |
| 14214 | virtual int reloc() const; |
| 14215 | virtual uint oper_input_base() const { return 2; } |
| 14216 | public: |
| 14217 | compareAndSwapS_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14218 | virtual uint size_of() const { return sizeof(compareAndSwapS_0Node); } |
| 14219 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14220 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14221 | static const Pipeline *pipeline_class(); |
| 14222 | virtual const Pipeline *pipeline() const; |
| 14223 | virtual const MachOper *memory_operand() const; |
| 14224 | #ifndef PRODUCT |
| 14225 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14226 | virtual const char *Name() const { return "compareAndSwapS_0";} |
| 14227 | #endif |
| 14228 | }; |
| 14229 | |
| 14230 | class compareAndSwapNNode : public MachNode { |
| 14231 | private: |
| 14232 | MachOper *_opnd_array[4]; |
| 14233 | public: |
| 14234 | MachOper *opnd_array(uint operand_index) const { |
| 14235 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14236 | return _opnd_array[operand_index]; |
| 14237 | } |
| 14238 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14239 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14240 | _opnd_array[operand_index] = operand; |
| 14241 | } |
| 14242 | private: |
| 14243 | virtual const RegMask &out_RegMask() const; |
| 14244 | virtual uint rule() const { return compareAndSwapN_rule; } |
| 14245 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14246 | virtual int ideal_Opcode() const { return Op_CompareAndSwapN; } |
| 14247 | virtual int reloc() const; |
| 14248 | virtual uint oper_input_base() const { return 2; } |
| 14249 | public: |
| 14250 | compareAndSwapNNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14251 | virtual uint size_of() const { return sizeof(compareAndSwapNNode); } |
| 14252 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14253 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14254 | static const Pipeline *pipeline_class(); |
| 14255 | virtual const Pipeline *pipeline() const; |
| 14256 | virtual const MachOper *memory_operand() const; |
| 14257 | #ifndef PRODUCT |
| 14258 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14259 | virtual const char *Name() const { return "compareAndSwapN";} |
| 14260 | #endif |
| 14261 | }; |
| 14262 | |
| 14263 | class compareAndSwapN_0Node : public MachNode { |
| 14264 | private: |
| 14265 | MachOper *_opnd_array[4]; |
| 14266 | public: |
| 14267 | MachOper *opnd_array(uint operand_index) const { |
| 14268 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14269 | return _opnd_array[operand_index]; |
| 14270 | } |
| 14271 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14273 | _opnd_array[operand_index] = operand; |
| 14274 | } |
| 14275 | private: |
| 14276 | virtual const RegMask &out_RegMask() const; |
| 14277 | virtual uint rule() const { return compareAndSwapN_0_rule; } |
| 14278 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14279 | virtual int ideal_Opcode() const { return Op_WeakCompareAndSwapN; } |
| 14280 | virtual int reloc() const; |
| 14281 | virtual uint oper_input_base() const { return 2; } |
| 14282 | public: |
| 14283 | compareAndSwapN_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14284 | virtual uint size_of() const { return sizeof(compareAndSwapN_0Node); } |
| 14285 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14286 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14287 | static const Pipeline *pipeline_class(); |
| 14288 | virtual const Pipeline *pipeline() const; |
| 14289 | virtual const MachOper *memory_operand() const; |
| 14290 | #ifndef PRODUCT |
| 14291 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14292 | virtual const char *Name() const { return "compareAndSwapN_0";} |
| 14293 | #endif |
| 14294 | }; |
| 14295 | |
| 14296 | class compareAndExchangeBNode : public MachNode { |
| 14297 | private: |
| 14298 | MachOper *_opnd_array[4]; |
| 14299 | public: |
| 14300 | MachOper *opnd_array(uint operand_index) const { |
| 14301 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14302 | return _opnd_array[operand_index]; |
| 14303 | } |
| 14304 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14305 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14306 | _opnd_array[operand_index] = operand; |
| 14307 | } |
| 14308 | private: |
| 14309 | virtual const RegMask &out_RegMask() const; |
| 14310 | virtual uint rule() const { return compareAndExchangeB_rule; } |
| 14311 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14312 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeB; } |
| 14313 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14314 | virtual int reloc() const; |
| 14315 | virtual uint oper_input_base() const { return 2; } |
| 14316 | public: |
| 14317 | compareAndExchangeBNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14318 | virtual uint size_of() const { return sizeof(compareAndExchangeBNode); } |
| 14319 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14320 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14321 | static const Pipeline *pipeline_class(); |
| 14322 | virtual const Pipeline *pipeline() const; |
| 14323 | virtual const MachOper *memory_operand() const; |
| 14324 | #ifndef PRODUCT |
| 14325 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14326 | virtual const char *Name() const { return "compareAndExchangeB";} |
| 14327 | #endif |
| 14328 | }; |
| 14329 | |
| 14330 | class compareAndExchangeSNode : public MachNode { |
| 14331 | private: |
| 14332 | MachOper *_opnd_array[4]; |
| 14333 | public: |
| 14334 | MachOper *opnd_array(uint operand_index) const { |
| 14335 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14336 | return _opnd_array[operand_index]; |
| 14337 | } |
| 14338 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14339 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14340 | _opnd_array[operand_index] = operand; |
| 14341 | } |
| 14342 | private: |
| 14343 | virtual const RegMask &out_RegMask() const; |
| 14344 | virtual uint rule() const { return compareAndExchangeS_rule; } |
| 14345 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14346 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeS; } |
| 14347 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14348 | virtual int reloc() const; |
| 14349 | virtual uint oper_input_base() const { return 2; } |
| 14350 | public: |
| 14351 | compareAndExchangeSNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14352 | virtual uint size_of() const { return sizeof(compareAndExchangeSNode); } |
| 14353 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14354 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14355 | static const Pipeline *pipeline_class(); |
| 14356 | virtual const Pipeline *pipeline() const; |
| 14357 | virtual const MachOper *memory_operand() const; |
| 14358 | #ifndef PRODUCT |
| 14359 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14360 | virtual const char *Name() const { return "compareAndExchangeS";} |
| 14361 | #endif |
| 14362 | }; |
| 14363 | |
| 14364 | class compareAndExchangeINode : public MachNode { |
| 14365 | private: |
| 14366 | MachOper *_opnd_array[4]; |
| 14367 | public: |
| 14368 | MachOper *opnd_array(uint operand_index) const { |
| 14369 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14370 | return _opnd_array[operand_index]; |
| 14371 | } |
| 14372 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14373 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14374 | _opnd_array[operand_index] = operand; |
| 14375 | } |
| 14376 | private: |
| 14377 | virtual const RegMask &out_RegMask() const; |
| 14378 | virtual uint rule() const { return compareAndExchangeI_rule; } |
| 14379 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14380 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeI; } |
| 14381 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14382 | virtual int reloc() const; |
| 14383 | virtual uint oper_input_base() const { return 2; } |
| 14384 | public: |
| 14385 | compareAndExchangeINode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14386 | virtual uint size_of() const { return sizeof(compareAndExchangeINode); } |
| 14387 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14388 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14389 | static const Pipeline *pipeline_class(); |
| 14390 | virtual const Pipeline *pipeline() const; |
| 14391 | virtual const MachOper *memory_operand() const; |
| 14392 | #ifndef PRODUCT |
| 14393 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14394 | virtual const char *Name() const { return "compareAndExchangeI";} |
| 14395 | #endif |
| 14396 | }; |
| 14397 | |
| 14398 | class compareAndExchangeLNode : public MachNode { |
| 14399 | private: |
| 14400 | MachOper *_opnd_array[4]; |
| 14401 | public: |
| 14402 | MachOper *opnd_array(uint operand_index) const { |
| 14403 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14404 | return _opnd_array[operand_index]; |
| 14405 | } |
| 14406 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14408 | _opnd_array[operand_index] = operand; |
| 14409 | } |
| 14410 | private: |
| 14411 | virtual const RegMask &out_RegMask() const; |
| 14412 | virtual uint rule() const { return compareAndExchangeL_rule; } |
| 14413 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14414 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeL; } |
| 14415 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14416 | virtual int reloc() const; |
| 14417 | virtual uint oper_input_base() const { return 2; } |
| 14418 | public: |
| 14419 | compareAndExchangeLNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14420 | virtual uint size_of() const { return sizeof(compareAndExchangeLNode); } |
| 14421 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14422 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14423 | static const Pipeline *pipeline_class(); |
| 14424 | virtual const Pipeline *pipeline() const; |
| 14425 | virtual const MachOper *memory_operand() const; |
| 14426 | #ifndef PRODUCT |
| 14427 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14428 | virtual const char *Name() const { return "compareAndExchangeL";} |
| 14429 | #endif |
| 14430 | }; |
| 14431 | |
| 14432 | class compareAndExchangeNNode : public MachTypeNode { |
| 14433 | private: |
| 14434 | MachOper *_opnd_array[4]; |
| 14435 | public: |
| 14436 | MachOper *opnd_array(uint operand_index) const { |
| 14437 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14438 | return _opnd_array[operand_index]; |
| 14439 | } |
| 14440 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14441 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14442 | _opnd_array[operand_index] = operand; |
| 14443 | } |
| 14444 | private: |
| 14445 | virtual const RegMask &out_RegMask() const; |
| 14446 | virtual uint rule() const { return compareAndExchangeN_rule; } |
| 14447 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14448 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeN; } |
| 14449 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14450 | virtual int reloc() const; |
| 14451 | virtual uint oper_input_base() const { return 2; } |
| 14452 | public: |
| 14453 | compareAndExchangeNNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14454 | virtual uint size_of() const { return sizeof(compareAndExchangeNNode); } |
| 14455 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14456 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14457 | static const Pipeline *pipeline_class(); |
| 14458 | virtual const Pipeline *pipeline() const; |
| 14459 | virtual const MachOper *memory_operand() const; |
| 14460 | #ifndef PRODUCT |
| 14461 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14462 | virtual const char *Name() const { return "compareAndExchangeN";} |
| 14463 | #endif |
| 14464 | }; |
| 14465 | |
| 14466 | class compareAndExchangePNode : public MachTypeNode { |
| 14467 | private: |
| 14468 | MachOper *_opnd_array[4]; |
| 14469 | public: |
| 14470 | MachOper *opnd_array(uint operand_index) const { |
| 14471 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14472 | return _opnd_array[operand_index]; |
| 14473 | } |
| 14474 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14475 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14476 | _opnd_array[operand_index] = operand; |
| 14477 | } |
| 14478 | private: |
| 14479 | virtual const RegMask &out_RegMask() const; |
| 14480 | virtual uint rule() const { return compareAndExchangeP_rule; } |
| 14481 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14482 | virtual int ideal_Opcode() const { return Op_CompareAndExchangeP; } |
| 14483 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14484 | virtual int reloc() const; |
| 14485 | virtual uint oper_input_base() const { return 2; } |
| 14486 | public: |
| 14487 | compareAndExchangePNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14488 | virtual uint size_of() const { return sizeof(compareAndExchangePNode); } |
| 14489 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14490 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14491 | static const Pipeline *pipeline_class(); |
| 14492 | virtual const Pipeline *pipeline() const; |
| 14493 | virtual const MachOper *memory_operand() const; |
| 14494 | #ifndef PRODUCT |
| 14495 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14496 | virtual const char *Name() const { return "compareAndExchangeP";} |
| 14497 | #endif |
| 14498 | }; |
| 14499 | |
| 14500 | class xaddB_no_resNode : public MachNode { |
| 14501 | private: |
| 14502 | MachOper *_opnd_array[3]; |
| 14503 | public: |
| 14504 | MachOper *opnd_array(uint operand_index) const { |
| 14505 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14506 | return _opnd_array[operand_index]; |
| 14507 | } |
| 14508 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14509 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14510 | _opnd_array[operand_index] = operand; |
| 14511 | } |
| 14512 | private: |
| 14513 | virtual const RegMask &out_RegMask() const; |
| 14514 | virtual uint rule() const { return xaddB_no_res_rule; } |
| 14515 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14516 | virtual int ideal_Opcode() const { return Op_GetAndAddB; } |
| 14517 | virtual int reloc() const; |
| 14518 | virtual uint oper_input_base() const { return 2; } |
| 14519 | public: |
| 14520 | xaddB_no_resNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14521 | virtual uint size_of() const { return sizeof(xaddB_no_resNode); } |
| 14522 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14523 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14524 | static const Pipeline *pipeline_class(); |
| 14525 | virtual const Pipeline *pipeline() const; |
| 14526 | virtual const MachOper *memory_operand() const; |
| 14527 | #ifndef PRODUCT |
| 14528 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14529 | virtual const char *Name() const { return "xaddB_no_res";} |
| 14530 | #endif |
| 14531 | }; |
| 14532 | |
| 14533 | class xaddBNode : public MachNode { |
| 14534 | private: |
| 14535 | MachOper *_opnd_array[3]; |
| 14536 | public: |
| 14537 | MachOper *opnd_array(uint operand_index) const { |
| 14538 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14539 | return _opnd_array[operand_index]; |
| 14540 | } |
| 14541 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14542 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14543 | _opnd_array[operand_index] = operand; |
| 14544 | } |
| 14545 | private: |
| 14546 | virtual const RegMask &out_RegMask() const; |
| 14547 | virtual uint rule() const { return xaddB_rule; } |
| 14548 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14549 | virtual int ideal_Opcode() const { return Op_GetAndAddB; } |
| 14550 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14551 | virtual int reloc() const; |
| 14552 | virtual uint oper_input_base() const { return 2; } |
| 14553 | public: |
| 14554 | xaddBNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14555 | virtual uint size_of() const { return sizeof(xaddBNode); } |
| 14556 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14557 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14558 | static const Pipeline *pipeline_class(); |
| 14559 | virtual const Pipeline *pipeline() const; |
| 14560 | virtual const MachOper *memory_operand() const; |
| 14561 | #ifndef PRODUCT |
| 14562 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14563 | virtual const char *Name() const { return "xaddB";} |
| 14564 | #endif |
| 14565 | }; |
| 14566 | |
| 14567 | class xaddS_no_resNode : public MachNode { |
| 14568 | private: |
| 14569 | MachOper *_opnd_array[3]; |
| 14570 | public: |
| 14571 | MachOper *opnd_array(uint operand_index) const { |
| 14572 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14573 | return _opnd_array[operand_index]; |
| 14574 | } |
| 14575 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14576 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14577 | _opnd_array[operand_index] = operand; |
| 14578 | } |
| 14579 | private: |
| 14580 | virtual const RegMask &out_RegMask() const; |
| 14581 | virtual uint rule() const { return xaddS_no_res_rule; } |
| 14582 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14583 | virtual int ideal_Opcode() const { return Op_GetAndAddS; } |
| 14584 | virtual int reloc() const; |
| 14585 | virtual uint oper_input_base() const { return 2; } |
| 14586 | public: |
| 14587 | xaddS_no_resNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14588 | virtual uint size_of() const { return sizeof(xaddS_no_resNode); } |
| 14589 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14590 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14591 | static const Pipeline *pipeline_class(); |
| 14592 | virtual const Pipeline *pipeline() const; |
| 14593 | virtual const MachOper *memory_operand() const; |
| 14594 | #ifndef PRODUCT |
| 14595 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14596 | virtual const char *Name() const { return "xaddS_no_res";} |
| 14597 | #endif |
| 14598 | }; |
| 14599 | |
| 14600 | class xaddSNode : public MachNode { |
| 14601 | private: |
| 14602 | MachOper *_opnd_array[3]; |
| 14603 | public: |
| 14604 | MachOper *opnd_array(uint operand_index) const { |
| 14605 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14606 | return _opnd_array[operand_index]; |
| 14607 | } |
| 14608 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14609 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14610 | _opnd_array[operand_index] = operand; |
| 14611 | } |
| 14612 | private: |
| 14613 | virtual const RegMask &out_RegMask() const; |
| 14614 | virtual uint rule() const { return xaddS_rule; } |
| 14615 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14616 | virtual int ideal_Opcode() const { return Op_GetAndAddS; } |
| 14617 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14618 | virtual int reloc() const; |
| 14619 | virtual uint oper_input_base() const { return 2; } |
| 14620 | public: |
| 14621 | xaddSNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14622 | virtual uint size_of() const { return sizeof(xaddSNode); } |
| 14623 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14624 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14625 | static const Pipeline *pipeline_class(); |
| 14626 | virtual const Pipeline *pipeline() const; |
| 14627 | virtual const MachOper *memory_operand() const; |
| 14628 | #ifndef PRODUCT |
| 14629 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14630 | virtual const char *Name() const { return "xaddS";} |
| 14631 | #endif |
| 14632 | }; |
| 14633 | |
| 14634 | class xaddI_no_resNode : public MachNode { |
| 14635 | private: |
| 14636 | MachOper *_opnd_array[3]; |
| 14637 | public: |
| 14638 | MachOper *opnd_array(uint operand_index) const { |
| 14639 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14640 | return _opnd_array[operand_index]; |
| 14641 | } |
| 14642 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14643 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14644 | _opnd_array[operand_index] = operand; |
| 14645 | } |
| 14646 | private: |
| 14647 | virtual const RegMask &out_RegMask() const; |
| 14648 | virtual uint rule() const { return xaddI_no_res_rule; } |
| 14649 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14650 | virtual int ideal_Opcode() const { return Op_GetAndAddI; } |
| 14651 | virtual int reloc() const; |
| 14652 | virtual uint oper_input_base() const { return 2; } |
| 14653 | public: |
| 14654 | xaddI_no_resNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14655 | virtual uint size_of() const { return sizeof(xaddI_no_resNode); } |
| 14656 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14657 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14658 | static const Pipeline *pipeline_class(); |
| 14659 | virtual const Pipeline *pipeline() const; |
| 14660 | virtual const MachOper *memory_operand() const; |
| 14661 | #ifndef PRODUCT |
| 14662 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14663 | virtual const char *Name() const { return "xaddI_no_res";} |
| 14664 | #endif |
| 14665 | }; |
| 14666 | |
| 14667 | class xaddINode : public MachNode { |
| 14668 | private: |
| 14669 | MachOper *_opnd_array[3]; |
| 14670 | public: |
| 14671 | MachOper *opnd_array(uint operand_index) const { |
| 14672 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14673 | return _opnd_array[operand_index]; |
| 14674 | } |
| 14675 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14676 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14677 | _opnd_array[operand_index] = operand; |
| 14678 | } |
| 14679 | private: |
| 14680 | virtual const RegMask &out_RegMask() const; |
| 14681 | virtual uint rule() const { return xaddI_rule; } |
| 14682 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14683 | virtual int ideal_Opcode() const { return Op_GetAndAddI; } |
| 14684 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14685 | virtual int reloc() const; |
| 14686 | virtual uint oper_input_base() const { return 2; } |
| 14687 | public: |
| 14688 | xaddINode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14689 | virtual uint size_of() const { return sizeof(xaddINode); } |
| 14690 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14691 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14692 | static const Pipeline *pipeline_class(); |
| 14693 | virtual const Pipeline *pipeline() const; |
| 14694 | virtual const MachOper *memory_operand() const; |
| 14695 | #ifndef PRODUCT |
| 14696 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14697 | virtual const char *Name() const { return "xaddI";} |
| 14698 | #endif |
| 14699 | }; |
| 14700 | |
| 14701 | class xaddL_no_resNode : public MachNode { |
| 14702 | private: |
| 14703 | MachOper *_opnd_array[3]; |
| 14704 | public: |
| 14705 | MachOper *opnd_array(uint operand_index) const { |
| 14706 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14707 | return _opnd_array[operand_index]; |
| 14708 | } |
| 14709 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14710 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14711 | _opnd_array[operand_index] = operand; |
| 14712 | } |
| 14713 | private: |
| 14714 | virtual const RegMask &out_RegMask() const; |
| 14715 | virtual uint rule() const { return xaddL_no_res_rule; } |
| 14716 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14717 | virtual int ideal_Opcode() const { return Op_GetAndAddL; } |
| 14718 | virtual int reloc() const; |
| 14719 | virtual uint oper_input_base() const { return 2; } |
| 14720 | public: |
| 14721 | xaddL_no_resNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14722 | virtual uint size_of() const { return sizeof(xaddL_no_resNode); } |
| 14723 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14724 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14725 | static const Pipeline *pipeline_class(); |
| 14726 | virtual const Pipeline *pipeline() const; |
| 14727 | virtual const MachOper *memory_operand() const; |
| 14728 | #ifndef PRODUCT |
| 14729 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14730 | virtual const char *Name() const { return "xaddL_no_res";} |
| 14731 | #endif |
| 14732 | }; |
| 14733 | |
| 14734 | class xaddLNode : public MachNode { |
| 14735 | private: |
| 14736 | MachOper *_opnd_array[3]; |
| 14737 | public: |
| 14738 | MachOper *opnd_array(uint operand_index) const { |
| 14739 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14740 | return _opnd_array[operand_index]; |
| 14741 | } |
| 14742 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14743 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14744 | _opnd_array[operand_index] = operand; |
| 14745 | } |
| 14746 | private: |
| 14747 | virtual const RegMask &out_RegMask() const; |
| 14748 | virtual uint rule() const { return xaddL_rule; } |
| 14749 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14750 | virtual int ideal_Opcode() const { return Op_GetAndAddL; } |
| 14751 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14752 | virtual int reloc() const; |
| 14753 | virtual uint oper_input_base() const { return 2; } |
| 14754 | public: |
| 14755 | xaddLNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14756 | virtual uint size_of() const { return sizeof(xaddLNode); } |
| 14757 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14758 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14759 | static const Pipeline *pipeline_class(); |
| 14760 | virtual const Pipeline *pipeline() const; |
| 14761 | virtual const MachOper *memory_operand() const; |
| 14762 | #ifndef PRODUCT |
| 14763 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14764 | virtual const char *Name() const { return "xaddL";} |
| 14765 | #endif |
| 14766 | }; |
| 14767 | |
| 14768 | class xchgBNode : public MachNode { |
| 14769 | private: |
| 14770 | MachOper *_opnd_array[3]; |
| 14771 | public: |
| 14772 | MachOper *opnd_array(uint operand_index) const { |
| 14773 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14774 | return _opnd_array[operand_index]; |
| 14775 | } |
| 14776 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14777 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14778 | _opnd_array[operand_index] = operand; |
| 14779 | } |
| 14780 | private: |
| 14781 | virtual const RegMask &out_RegMask() const; |
| 14782 | virtual uint rule() const { return xchgB_rule; } |
| 14783 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14784 | virtual int ideal_Opcode() const { return Op_GetAndSetB; } |
| 14785 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14786 | virtual int reloc() const; |
| 14787 | virtual uint oper_input_base() const { return 2; } |
| 14788 | public: |
| 14789 | xchgBNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14790 | virtual uint size_of() const { return sizeof(xchgBNode); } |
| 14791 | static const Pipeline *pipeline_class(); |
| 14792 | virtual const Pipeline *pipeline() const; |
| 14793 | virtual const MachOper *memory_operand() const; |
| 14794 | #ifndef PRODUCT |
| 14795 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14796 | virtual const char *Name() const { return "xchgB";} |
| 14797 | #endif |
| 14798 | }; |
| 14799 | |
| 14800 | class xchgSNode : public MachNode { |
| 14801 | private: |
| 14802 | MachOper *_opnd_array[3]; |
| 14803 | public: |
| 14804 | MachOper *opnd_array(uint operand_index) const { |
| 14805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14806 | return _opnd_array[operand_index]; |
| 14807 | } |
| 14808 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14810 | _opnd_array[operand_index] = operand; |
| 14811 | } |
| 14812 | private: |
| 14813 | virtual const RegMask &out_RegMask() const; |
| 14814 | virtual uint rule() const { return xchgS_rule; } |
| 14815 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14816 | virtual int ideal_Opcode() const { return Op_GetAndSetS; } |
| 14817 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14818 | virtual int reloc() const; |
| 14819 | virtual uint oper_input_base() const { return 2; } |
| 14820 | public: |
| 14821 | xchgSNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14822 | virtual uint size_of() const { return sizeof(xchgSNode); } |
| 14823 | static const Pipeline *pipeline_class(); |
| 14824 | virtual const Pipeline *pipeline() const; |
| 14825 | virtual const MachOper *memory_operand() const; |
| 14826 | #ifndef PRODUCT |
| 14827 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14828 | virtual const char *Name() const { return "xchgS";} |
| 14829 | #endif |
| 14830 | }; |
| 14831 | |
| 14832 | class xchgINode : public MachNode { |
| 14833 | private: |
| 14834 | MachOper *_opnd_array[3]; |
| 14835 | public: |
| 14836 | MachOper *opnd_array(uint operand_index) const { |
| 14837 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14838 | return _opnd_array[operand_index]; |
| 14839 | } |
| 14840 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14841 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14842 | _opnd_array[operand_index] = operand; |
| 14843 | } |
| 14844 | private: |
| 14845 | virtual const RegMask &out_RegMask() const; |
| 14846 | virtual uint rule() const { return xchgI_rule; } |
| 14847 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14848 | virtual int ideal_Opcode() const { return Op_GetAndSetI; } |
| 14849 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14850 | virtual int reloc() const; |
| 14851 | virtual uint oper_input_base() const { return 2; } |
| 14852 | public: |
| 14853 | xchgINode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14854 | virtual uint size_of() const { return sizeof(xchgINode); } |
| 14855 | static const Pipeline *pipeline_class(); |
| 14856 | virtual const Pipeline *pipeline() const; |
| 14857 | virtual const MachOper *memory_operand() const; |
| 14858 | #ifndef PRODUCT |
| 14859 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14860 | virtual const char *Name() const { return "xchgI";} |
| 14861 | #endif |
| 14862 | }; |
| 14863 | |
| 14864 | class xchgLNode : public MachNode { |
| 14865 | private: |
| 14866 | MachOper *_opnd_array[3]; |
| 14867 | public: |
| 14868 | MachOper *opnd_array(uint operand_index) const { |
| 14869 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14870 | return _opnd_array[operand_index]; |
| 14871 | } |
| 14872 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14873 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14874 | _opnd_array[operand_index] = operand; |
| 14875 | } |
| 14876 | private: |
| 14877 | virtual const RegMask &out_RegMask() const; |
| 14878 | virtual uint rule() const { return xchgL_rule; } |
| 14879 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14880 | virtual int ideal_Opcode() const { return Op_GetAndSetL; } |
| 14881 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14882 | virtual int reloc() const; |
| 14883 | virtual uint oper_input_base() const { return 2; } |
| 14884 | public: |
| 14885 | xchgLNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14886 | virtual uint size_of() const { return sizeof(xchgLNode); } |
| 14887 | static const Pipeline *pipeline_class(); |
| 14888 | virtual const Pipeline *pipeline() const; |
| 14889 | virtual const MachOper *memory_operand() const; |
| 14890 | #ifndef PRODUCT |
| 14891 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14892 | virtual const char *Name() const { return "xchgL";} |
| 14893 | #endif |
| 14894 | }; |
| 14895 | |
| 14896 | class xchgPNode : public MachTypeNode { |
| 14897 | private: |
| 14898 | MachOper *_opnd_array[3]; |
| 14899 | public: |
| 14900 | MachOper *opnd_array(uint operand_index) const { |
| 14901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14902 | return _opnd_array[operand_index]; |
| 14903 | } |
| 14904 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14905 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14906 | _opnd_array[operand_index] = operand; |
| 14907 | } |
| 14908 | private: |
| 14909 | virtual const RegMask &out_RegMask() const; |
| 14910 | virtual uint rule() const { return xchgP_rule; } |
| 14911 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14912 | virtual int ideal_Opcode() const { return Op_GetAndSetP; } |
| 14913 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14914 | virtual int reloc() const; |
| 14915 | virtual uint oper_input_base() const { return 2; } |
| 14916 | public: |
| 14917 | xchgPNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14918 | virtual uint size_of() const { return sizeof(xchgPNode); } |
| 14919 | static const Pipeline *pipeline_class(); |
| 14920 | virtual const Pipeline *pipeline() const; |
| 14921 | virtual const MachOper *memory_operand() const; |
| 14922 | #ifndef PRODUCT |
| 14923 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14924 | virtual const char *Name() const { return "xchgP";} |
| 14925 | #endif |
| 14926 | }; |
| 14927 | |
| 14928 | class xchgNNode : public MachTypeNode { |
| 14929 | private: |
| 14930 | MachOper *_opnd_array[3]; |
| 14931 | public: |
| 14932 | MachOper *opnd_array(uint operand_index) const { |
| 14933 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14934 | return _opnd_array[operand_index]; |
| 14935 | } |
| 14936 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14937 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14938 | _opnd_array[operand_index] = operand; |
| 14939 | } |
| 14940 | private: |
| 14941 | virtual const RegMask &out_RegMask() const; |
| 14942 | virtual uint rule() const { return xchgN_rule; } |
| 14943 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14944 | virtual int ideal_Opcode() const { return Op_GetAndSetN; } |
| 14945 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14946 | virtual int reloc() const; |
| 14947 | virtual uint oper_input_base() const { return 2; } |
| 14948 | public: |
| 14949 | xchgNNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 14950 | virtual uint size_of() const { return sizeof(xchgNNode); } |
| 14951 | static const Pipeline *pipeline_class(); |
| 14952 | virtual const Pipeline *pipeline() const; |
| 14953 | virtual const MachOper *memory_operand() const; |
| 14954 | #ifndef PRODUCT |
| 14955 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14956 | virtual const char *Name() const { return "xchgN";} |
| 14957 | #endif |
| 14958 | }; |
| 14959 | |
| 14960 | class absI_rRegNode : public MachNode { |
| 14961 | private: |
| 14962 | MachOper *_opnd_array[4]; |
| 14963 | public: |
| 14964 | MachOper *opnd_array(uint operand_index) const { |
| 14965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14966 | return _opnd_array[operand_index]; |
| 14967 | } |
| 14968 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 14969 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14970 | _opnd_array[operand_index] = operand; |
| 14971 | } |
| 14972 | private: |
| 14973 | virtual const RegMask &out_RegMask() const; |
| 14974 | virtual uint rule() const { return absI_rReg_rule; } |
| 14975 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 14976 | virtual int ideal_Opcode() const { return Op_AbsI; } |
| 14977 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 14978 | public: |
| 14979 | absI_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 14980 | virtual uint size_of() const { return sizeof(absI_rRegNode); } |
| 14981 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 14982 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 14983 | static const Pipeline *pipeline_class(); |
| 14984 | virtual const Pipeline *pipeline() const; |
| 14985 | #ifndef PRODUCT |
| 14986 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 14987 | virtual const char *Name() const { return "absI_rReg";} |
| 14988 | #endif |
| 14989 | }; |
| 14990 | |
| 14991 | class absL_rRegNode : public MachNode { |
| 14992 | private: |
| 14993 | MachOper *_opnd_array[4]; |
| 14994 | public: |
| 14995 | MachOper *opnd_array(uint operand_index) const { |
| 14996 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 14997 | return _opnd_array[operand_index]; |
| 14998 | } |
| 14999 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15000 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15001 | _opnd_array[operand_index] = operand; |
| 15002 | } |
| 15003 | private: |
| 15004 | virtual const RegMask &out_RegMask() const; |
| 15005 | virtual uint rule() const { return absL_rReg_rule; } |
| 15006 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15007 | virtual int ideal_Opcode() const { return Op_AbsL; } |
| 15008 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 15009 | public: |
| 15010 | absL_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15011 | virtual uint size_of() const { return sizeof(absL_rRegNode); } |
| 15012 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15013 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15014 | static const Pipeline *pipeline_class(); |
| 15015 | virtual const Pipeline *pipeline() const; |
| 15016 | #ifndef PRODUCT |
| 15017 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15018 | virtual const char *Name() const { return "absL_rReg";} |
| 15019 | #endif |
| 15020 | }; |
| 15021 | |
| 15022 | class subI_rRegNode : public MachNode { |
| 15023 | private: |
| 15024 | MachOper *_opnd_array[3]; |
| 15025 | public: |
| 15026 | MachOper *opnd_array(uint operand_index) const { |
| 15027 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15028 | return _opnd_array[operand_index]; |
| 15029 | } |
| 15030 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15032 | _opnd_array[operand_index] = operand; |
| 15033 | } |
| 15034 | private: |
| 15035 | const RegMask *_cisc_RegMask; |
| 15036 | virtual const RegMask &out_RegMask() const; |
| 15037 | virtual uint rule() const { return subI_rReg_rule; } |
| 15038 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15039 | virtual int ideal_Opcode() const { return Op_SubI; } |
| 15040 | virtual uint two_adr() const { return oper_input_base(); } |
| 15041 | virtual int cisc_operand() const { return 2; } |
| 15042 | virtual MachNode *cisc_version(int offset); |
| 15043 | virtual void use_cisc_RegMask(); |
| 15044 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15045 | public: |
| 15046 | subI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15047 | virtual uint size_of() const { return sizeof(subI_rRegNode); } |
| 15048 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15049 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15050 | static const Pipeline *pipeline_class(); |
| 15051 | virtual const Pipeline *pipeline() const; |
| 15052 | #ifndef PRODUCT |
| 15053 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15054 | virtual const char *Name() const { return "subI_rReg";} |
| 15055 | #endif |
| 15056 | }; |
| 15057 | |
| 15058 | class subI_rReg_immNode : public MachNode { |
| 15059 | private: |
| 15060 | MachOper *_opnd_array[3]; |
| 15061 | public: |
| 15062 | MachOper *opnd_array(uint operand_index) const { |
| 15063 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15064 | return _opnd_array[operand_index]; |
| 15065 | } |
| 15066 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15067 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15068 | _opnd_array[operand_index] = operand; |
| 15069 | } |
| 15070 | private: |
| 15071 | virtual const RegMask &out_RegMask() const; |
| 15072 | virtual uint rule() const { return subI_rReg_imm_rule; } |
| 15073 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15074 | virtual int ideal_Opcode() const { return Op_SubI; } |
| 15075 | virtual uint two_adr() const { return oper_input_base(); } |
| 15076 | public: |
| 15077 | subI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15078 | virtual uint size_of() const { return sizeof(subI_rReg_immNode); } |
| 15079 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15080 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15081 | static const Pipeline *pipeline_class(); |
| 15082 | virtual const Pipeline *pipeline() const; |
| 15083 | #ifndef PRODUCT |
| 15084 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15085 | virtual const char *Name() const { return "subI_rReg_imm";} |
| 15086 | #endif |
| 15087 | }; |
| 15088 | |
| 15089 | class subI_rReg_memNode : public MachNode { |
| 15090 | private: |
| 15091 | MachOper *_opnd_array[3]; |
| 15092 | public: |
| 15093 | MachOper *opnd_array(uint operand_index) const { |
| 15094 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15095 | return _opnd_array[operand_index]; |
| 15096 | } |
| 15097 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15098 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15099 | _opnd_array[operand_index] = operand; |
| 15100 | } |
| 15101 | private: |
| 15102 | virtual const RegMask &out_RegMask() const; |
| 15103 | virtual uint rule() const { return subI_rReg_mem_rule; } |
| 15104 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15105 | virtual int ideal_Opcode() const { return Op_SubI; } |
| 15106 | virtual uint two_adr() const { return oper_input_base(); } |
| 15107 | virtual int reloc() const; |
| 15108 | virtual uint oper_input_base() const { return 2; } |
| 15109 | public: |
| 15110 | subI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15111 | virtual uint size_of() const { return sizeof(subI_rReg_memNode); } |
| 15112 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15113 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15114 | static const Pipeline *pipeline_class(); |
| 15115 | virtual const Pipeline *pipeline() const; |
| 15116 | virtual const MachOper *memory_operand() const; |
| 15117 | #ifndef PRODUCT |
| 15118 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15119 | virtual const char *Name() const { return "subI_rReg_mem";} |
| 15120 | #endif |
| 15121 | }; |
| 15122 | |
| 15123 | class subI_mem_rRegNode : public MachTypeNode { |
| 15124 | private: |
| 15125 | MachOper *_opnd_array[4]; |
| 15126 | public: |
| 15127 | MachOper *opnd_array(uint operand_index) const { |
| 15128 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15129 | return _opnd_array[operand_index]; |
| 15130 | } |
| 15131 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15132 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15133 | _opnd_array[operand_index] = operand; |
| 15134 | } |
| 15135 | private: |
| 15136 | virtual const RegMask &out_RegMask() const; |
| 15137 | virtual uint rule() const { return subI_mem_rReg_rule; } |
| 15138 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15139 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 15140 | virtual int reloc() const; |
| 15141 | virtual uint oper_input_base() const { return 2; } |
| 15142 | public: |
| 15143 | subI_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15144 | virtual uint size_of() const { return sizeof(subI_mem_rRegNode); } |
| 15145 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15146 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15147 | static const Pipeline *pipeline_class(); |
| 15148 | virtual const Pipeline *pipeline() const; |
| 15149 | virtual const MachOper *memory_operand() const; |
| 15150 | #ifndef PRODUCT |
| 15151 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15152 | virtual const char *Name() const { return "subI_mem_rReg";} |
| 15153 | #endif |
| 15154 | }; |
| 15155 | |
| 15156 | class subI_mem_immNode : public MachTypeNode { |
| 15157 | private: |
| 15158 | MachOper *_opnd_array[4]; |
| 15159 | public: |
| 15160 | MachOper *opnd_array(uint operand_index) const { |
| 15161 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15162 | return _opnd_array[operand_index]; |
| 15163 | } |
| 15164 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15165 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15166 | _opnd_array[operand_index] = operand; |
| 15167 | } |
| 15168 | private: |
| 15169 | virtual const RegMask &out_RegMask() const; |
| 15170 | virtual uint rule() const { return subI_mem_imm_rule; } |
| 15171 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15172 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 15173 | virtual int reloc() const; |
| 15174 | virtual uint oper_input_base() const { return 2; } |
| 15175 | public: |
| 15176 | subI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15177 | virtual uint size_of() const { return sizeof(subI_mem_immNode); } |
| 15178 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15179 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15180 | static const Pipeline *pipeline_class(); |
| 15181 | virtual const Pipeline *pipeline() const; |
| 15182 | virtual const MachOper *memory_operand() const; |
| 15183 | #ifndef PRODUCT |
| 15184 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15185 | virtual const char *Name() const { return "subI_mem_imm";} |
| 15186 | #endif |
| 15187 | }; |
| 15188 | |
| 15189 | class subL_rRegNode : public MachNode { |
| 15190 | private: |
| 15191 | MachOper *_opnd_array[3]; |
| 15192 | public: |
| 15193 | MachOper *opnd_array(uint operand_index) const { |
| 15194 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15195 | return _opnd_array[operand_index]; |
| 15196 | } |
| 15197 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15198 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15199 | _opnd_array[operand_index] = operand; |
| 15200 | } |
| 15201 | private: |
| 15202 | const RegMask *_cisc_RegMask; |
| 15203 | virtual const RegMask &out_RegMask() const; |
| 15204 | virtual uint rule() const { return subL_rReg_rule; } |
| 15205 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15206 | virtual int ideal_Opcode() const { return Op_SubL; } |
| 15207 | virtual uint two_adr() const { return oper_input_base(); } |
| 15208 | virtual int cisc_operand() const { return 2; } |
| 15209 | virtual MachNode *cisc_version(int offset); |
| 15210 | virtual void use_cisc_RegMask(); |
| 15211 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15212 | public: |
| 15213 | subL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15214 | virtual uint size_of() const { return sizeof(subL_rRegNode); } |
| 15215 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15216 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15217 | static const Pipeline *pipeline_class(); |
| 15218 | virtual const Pipeline *pipeline() const; |
| 15219 | #ifndef PRODUCT |
| 15220 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15221 | virtual const char *Name() const { return "subL_rReg";} |
| 15222 | #endif |
| 15223 | }; |
| 15224 | |
| 15225 | class subL_rReg_immNode : public MachNode { |
| 15226 | private: |
| 15227 | MachOper *_opnd_array[3]; |
| 15228 | public: |
| 15229 | MachOper *opnd_array(uint operand_index) const { |
| 15230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15231 | return _opnd_array[operand_index]; |
| 15232 | } |
| 15233 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15234 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15235 | _opnd_array[operand_index] = operand; |
| 15236 | } |
| 15237 | private: |
| 15238 | virtual const RegMask &out_RegMask() const; |
| 15239 | virtual uint rule() const { return subL_rReg_imm_rule; } |
| 15240 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15241 | virtual int ideal_Opcode() const { return Op_SubL; } |
| 15242 | virtual uint two_adr() const { return oper_input_base(); } |
| 15243 | public: |
| 15244 | subL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15245 | virtual uint size_of() const { return sizeof(subL_rReg_immNode); } |
| 15246 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15247 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15248 | static const Pipeline *pipeline_class(); |
| 15249 | virtual const Pipeline *pipeline() const; |
| 15250 | #ifndef PRODUCT |
| 15251 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15252 | virtual const char *Name() const { return "subL_rReg_imm";} |
| 15253 | #endif |
| 15254 | }; |
| 15255 | |
| 15256 | class subL_rReg_memNode : public MachNode { |
| 15257 | private: |
| 15258 | MachOper *_opnd_array[3]; |
| 15259 | public: |
| 15260 | MachOper *opnd_array(uint operand_index) const { |
| 15261 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15262 | return _opnd_array[operand_index]; |
| 15263 | } |
| 15264 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15265 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15266 | _opnd_array[operand_index] = operand; |
| 15267 | } |
| 15268 | private: |
| 15269 | virtual const RegMask &out_RegMask() const; |
| 15270 | virtual uint rule() const { return subL_rReg_mem_rule; } |
| 15271 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15272 | virtual int ideal_Opcode() const { return Op_SubL; } |
| 15273 | virtual uint two_adr() const { return oper_input_base(); } |
| 15274 | virtual int reloc() const; |
| 15275 | virtual uint oper_input_base() const { return 2; } |
| 15276 | public: |
| 15277 | subL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15278 | virtual uint size_of() const { return sizeof(subL_rReg_memNode); } |
| 15279 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15280 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15281 | static const Pipeline *pipeline_class(); |
| 15282 | virtual const Pipeline *pipeline() const; |
| 15283 | virtual const MachOper *memory_operand() const; |
| 15284 | #ifndef PRODUCT |
| 15285 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15286 | virtual const char *Name() const { return "subL_rReg_mem";} |
| 15287 | #endif |
| 15288 | }; |
| 15289 | |
| 15290 | class subL_mem_rRegNode : public MachTypeNode { |
| 15291 | private: |
| 15292 | MachOper *_opnd_array[4]; |
| 15293 | public: |
| 15294 | MachOper *opnd_array(uint operand_index) const { |
| 15295 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15296 | return _opnd_array[operand_index]; |
| 15297 | } |
| 15298 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15299 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15300 | _opnd_array[operand_index] = operand; |
| 15301 | } |
| 15302 | private: |
| 15303 | virtual const RegMask &out_RegMask() const; |
| 15304 | virtual uint rule() const { return subL_mem_rReg_rule; } |
| 15305 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15306 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 15307 | virtual int reloc() const; |
| 15308 | virtual uint oper_input_base() const { return 2; } |
| 15309 | public: |
| 15310 | subL_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15311 | virtual uint size_of() const { return sizeof(subL_mem_rRegNode); } |
| 15312 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15313 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15314 | static const Pipeline *pipeline_class(); |
| 15315 | virtual const Pipeline *pipeline() const; |
| 15316 | virtual const MachOper *memory_operand() const; |
| 15317 | #ifndef PRODUCT |
| 15318 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15319 | virtual const char *Name() const { return "subL_mem_rReg";} |
| 15320 | #endif |
| 15321 | }; |
| 15322 | |
| 15323 | class subL_mem_immNode : public MachTypeNode { |
| 15324 | private: |
| 15325 | MachOper *_opnd_array[4]; |
| 15326 | public: |
| 15327 | MachOper *opnd_array(uint operand_index) const { |
| 15328 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15329 | return _opnd_array[operand_index]; |
| 15330 | } |
| 15331 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15332 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15333 | _opnd_array[operand_index] = operand; |
| 15334 | } |
| 15335 | private: |
| 15336 | virtual const RegMask &out_RegMask() const; |
| 15337 | virtual uint rule() const { return subL_mem_imm_rule; } |
| 15338 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15339 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 15340 | virtual int reloc() const; |
| 15341 | virtual uint oper_input_base() const { return 2; } |
| 15342 | public: |
| 15343 | subL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15344 | virtual uint size_of() const { return sizeof(subL_mem_immNode); } |
| 15345 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15346 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15347 | static const Pipeline *pipeline_class(); |
| 15348 | virtual const Pipeline *pipeline() const; |
| 15349 | virtual const MachOper *memory_operand() const; |
| 15350 | #ifndef PRODUCT |
| 15351 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15352 | virtual const char *Name() const { return "subL_mem_imm";} |
| 15353 | #endif |
| 15354 | }; |
| 15355 | |
| 15356 | class subP_rRegNode : public MachTypeNode { |
| 15357 | private: |
| 15358 | MachOper *_opnd_array[4]; |
| 15359 | public: |
| 15360 | MachOper *opnd_array(uint operand_index) const { |
| 15361 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15362 | return _opnd_array[operand_index]; |
| 15363 | } |
| 15364 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15365 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15366 | _opnd_array[operand_index] = operand; |
| 15367 | } |
| 15368 | private: |
| 15369 | virtual const RegMask &out_RegMask() const; |
| 15370 | virtual uint rule() const { return subP_rReg_rule; } |
| 15371 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15372 | virtual int ideal_Opcode() const { return Op_AddP; } |
| 15373 | virtual uint two_adr() const { return oper_input_base(); } |
| 15374 | virtual uint oper_input_base() const { return 2; } |
| 15375 | public: |
| 15376 | subP_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15377 | virtual uint size_of() const { return sizeof(subP_rRegNode); } |
| 15378 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15379 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15380 | static const Pipeline *pipeline_class(); |
| 15381 | virtual const Pipeline *pipeline() const; |
| 15382 | #ifndef PRODUCT |
| 15383 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15384 | virtual const char *Name() const { return "subP_rReg";} |
| 15385 | #endif |
| 15386 | }; |
| 15387 | |
| 15388 | class negI_rRegNode : public MachNode { |
| 15389 | private: |
| 15390 | MachOper *_opnd_array[3]; |
| 15391 | public: |
| 15392 | MachOper *opnd_array(uint operand_index) const { |
| 15393 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15394 | return _opnd_array[operand_index]; |
| 15395 | } |
| 15396 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15397 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15398 | _opnd_array[operand_index] = operand; |
| 15399 | } |
| 15400 | private: |
| 15401 | virtual const RegMask &out_RegMask() const; |
| 15402 | virtual uint rule() const { return negI_rReg_rule; } |
| 15403 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15404 | virtual int ideal_Opcode() const { return Op_SubI; } |
| 15405 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 15406 | public: |
| 15407 | negI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15408 | virtual uint size_of() const { return sizeof(negI_rRegNode); } |
| 15409 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15410 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15411 | static const Pipeline *pipeline_class(); |
| 15412 | virtual const Pipeline *pipeline() const; |
| 15413 | #ifndef PRODUCT |
| 15414 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15415 | virtual const char *Name() const { return "negI_rReg";} |
| 15416 | #endif |
| 15417 | }; |
| 15418 | |
| 15419 | class negI_memNode : public MachTypeNode { |
| 15420 | private: |
| 15421 | MachOper *_opnd_array[4]; |
| 15422 | public: |
| 15423 | MachOper *opnd_array(uint operand_index) const { |
| 15424 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15425 | return _opnd_array[operand_index]; |
| 15426 | } |
| 15427 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15428 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15429 | _opnd_array[operand_index] = operand; |
| 15430 | } |
| 15431 | private: |
| 15432 | virtual const RegMask &out_RegMask() const; |
| 15433 | virtual uint rule() const { return negI_mem_rule; } |
| 15434 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15435 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 15436 | virtual int reloc() const; |
| 15437 | virtual uint oper_input_base() const { return 2; } |
| 15438 | public: |
| 15439 | negI_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15440 | virtual uint size_of() const { return sizeof(negI_memNode); } |
| 15441 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15442 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15443 | static const Pipeline *pipeline_class(); |
| 15444 | virtual const Pipeline *pipeline() const; |
| 15445 | virtual const MachOper *memory_operand() const; |
| 15446 | #ifndef PRODUCT |
| 15447 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15448 | virtual const char *Name() const { return "negI_mem";} |
| 15449 | #endif |
| 15450 | }; |
| 15451 | |
| 15452 | class negL_rRegNode : public MachNode { |
| 15453 | private: |
| 15454 | MachOper *_opnd_array[3]; |
| 15455 | public: |
| 15456 | MachOper *opnd_array(uint operand_index) const { |
| 15457 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15458 | return _opnd_array[operand_index]; |
| 15459 | } |
| 15460 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15461 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15462 | _opnd_array[operand_index] = operand; |
| 15463 | } |
| 15464 | private: |
| 15465 | virtual const RegMask &out_RegMask() const; |
| 15466 | virtual uint rule() const { return negL_rReg_rule; } |
| 15467 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15468 | virtual int ideal_Opcode() const { return Op_SubL; } |
| 15469 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 15470 | public: |
| 15471 | negL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15472 | virtual uint size_of() const { return sizeof(negL_rRegNode); } |
| 15473 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15474 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15475 | static const Pipeline *pipeline_class(); |
| 15476 | virtual const Pipeline *pipeline() const; |
| 15477 | #ifndef PRODUCT |
| 15478 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15479 | virtual const char *Name() const { return "negL_rReg";} |
| 15480 | #endif |
| 15481 | }; |
| 15482 | |
| 15483 | class negL_memNode : public MachTypeNode { |
| 15484 | private: |
| 15485 | MachOper *_opnd_array[4]; |
| 15486 | public: |
| 15487 | MachOper *opnd_array(uint operand_index) const { |
| 15488 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15489 | return _opnd_array[operand_index]; |
| 15490 | } |
| 15491 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15492 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15493 | _opnd_array[operand_index] = operand; |
| 15494 | } |
| 15495 | private: |
| 15496 | virtual const RegMask &out_RegMask() const; |
| 15497 | virtual uint rule() const { return negL_mem_rule; } |
| 15498 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15499 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 15500 | virtual int reloc() const; |
| 15501 | virtual uint oper_input_base() const { return 2; } |
| 15502 | public: |
| 15503 | negL_memNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 15504 | virtual uint size_of() const { return sizeof(negL_memNode); } |
| 15505 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15506 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15507 | static const Pipeline *pipeline_class(); |
| 15508 | virtual const Pipeline *pipeline() const; |
| 15509 | virtual const MachOper *memory_operand() const; |
| 15510 | #ifndef PRODUCT |
| 15511 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15512 | virtual const char *Name() const { return "negL_mem";} |
| 15513 | #endif |
| 15514 | }; |
| 15515 | |
| 15516 | class mulI_rRegNode : public MachNode { |
| 15517 | private: |
| 15518 | MachOper *_opnd_array[3]; |
| 15519 | public: |
| 15520 | MachOper *opnd_array(uint operand_index) const { |
| 15521 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15522 | return _opnd_array[operand_index]; |
| 15523 | } |
| 15524 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15525 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15526 | _opnd_array[operand_index] = operand; |
| 15527 | } |
| 15528 | private: |
| 15529 | const RegMask *_cisc_RegMask; |
| 15530 | virtual const RegMask &out_RegMask() const; |
| 15531 | virtual uint rule() const { return mulI_rReg_rule; } |
| 15532 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15533 | virtual int ideal_Opcode() const { return Op_MulI; } |
| 15534 | virtual uint two_adr() const { return oper_input_base(); } |
| 15535 | virtual int cisc_operand() const { return 2; } |
| 15536 | virtual MachNode *cisc_version(int offset); |
| 15537 | virtual void use_cisc_RegMask(); |
| 15538 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15539 | public: |
| 15540 | mulI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15541 | virtual uint size_of() const { return sizeof(mulI_rRegNode); } |
| 15542 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15543 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15544 | static const Pipeline *pipeline_class(); |
| 15545 | virtual const Pipeline *pipeline() const; |
| 15546 | #ifndef PRODUCT |
| 15547 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15548 | virtual const char *Name() const { return "mulI_rReg";} |
| 15549 | #endif |
| 15550 | }; |
| 15551 | |
| 15552 | class mulI_rReg_immNode : public MachNode { |
| 15553 | private: |
| 15554 | MachOper *_opnd_array[3]; |
| 15555 | public: |
| 15556 | MachOper *opnd_array(uint operand_index) const { |
| 15557 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15558 | return _opnd_array[operand_index]; |
| 15559 | } |
| 15560 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15561 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15562 | _opnd_array[operand_index] = operand; |
| 15563 | } |
| 15564 | private: |
| 15565 | const RegMask *_cisc_RegMask; |
| 15566 | virtual const RegMask &out_RegMask() const; |
| 15567 | virtual uint rule() const { return mulI_rReg_imm_rule; } |
| 15568 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15569 | virtual int ideal_Opcode() const { return Op_MulI; } |
| 15570 | virtual int cisc_operand() const { return 1; } |
| 15571 | virtual MachNode *cisc_version(int offset); |
| 15572 | virtual void use_cisc_RegMask(); |
| 15573 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15574 | public: |
| 15575 | mulI_rReg_immNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15576 | virtual uint size_of() const { return sizeof(mulI_rReg_immNode); } |
| 15577 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15578 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15579 | static const Pipeline *pipeline_class(); |
| 15580 | virtual const Pipeline *pipeline() const; |
| 15581 | #ifndef PRODUCT |
| 15582 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15583 | virtual const char *Name() const { return "mulI_rReg_imm";} |
| 15584 | #endif |
| 15585 | }; |
| 15586 | |
| 15587 | class mulI_memNode : public MachNode { |
| 15588 | private: |
| 15589 | MachOper *_opnd_array[3]; |
| 15590 | public: |
| 15591 | MachOper *opnd_array(uint operand_index) const { |
| 15592 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15593 | return _opnd_array[operand_index]; |
| 15594 | } |
| 15595 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15596 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15597 | _opnd_array[operand_index] = operand; |
| 15598 | } |
| 15599 | private: |
| 15600 | virtual const RegMask &out_RegMask() const; |
| 15601 | virtual uint rule() const { return mulI_mem_rule; } |
| 15602 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15603 | virtual int ideal_Opcode() const { return Op_MulI; } |
| 15604 | virtual uint two_adr() const { return oper_input_base(); } |
| 15605 | virtual int reloc() const; |
| 15606 | virtual uint oper_input_base() const { return 2; } |
| 15607 | public: |
| 15608 | mulI_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15609 | virtual uint size_of() const { return sizeof(mulI_memNode); } |
| 15610 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15611 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15612 | static const Pipeline *pipeline_class(); |
| 15613 | virtual const Pipeline *pipeline() const; |
| 15614 | virtual const MachOper *memory_operand() const; |
| 15615 | #ifndef PRODUCT |
| 15616 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15617 | virtual const char *Name() const { return "mulI_mem";} |
| 15618 | #endif |
| 15619 | }; |
| 15620 | |
| 15621 | class mulI_mem_0Node : public MachNode { |
| 15622 | private: |
| 15623 | MachOper *_opnd_array[3]; |
| 15624 | public: |
| 15625 | MachOper *opnd_array(uint operand_index) const { |
| 15626 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15627 | return _opnd_array[operand_index]; |
| 15628 | } |
| 15629 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15630 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15631 | _opnd_array[operand_index] = operand; |
| 15632 | } |
| 15633 | private: |
| 15634 | virtual const RegMask &out_RegMask() const; |
| 15635 | virtual uint rule() const { return mulI_mem_0_rule; } |
| 15636 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15637 | virtual int ideal_Opcode() const { return Op_MulI; } |
| 15638 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 15639 | virtual int reloc() const; |
| 15640 | virtual uint oper_input_base() const { return 2; } |
| 15641 | public: |
| 15642 | mulI_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 15643 | virtual uint size_of() const { return sizeof(mulI_mem_0Node); } |
| 15644 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15645 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15646 | static const Pipeline *pipeline_class(); |
| 15647 | virtual const Pipeline *pipeline() const; |
| 15648 | virtual const MachOper *memory_operand() const; |
| 15649 | #ifndef PRODUCT |
| 15650 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15651 | virtual const char *Name() const { return "mulI_mem_0";} |
| 15652 | #endif |
| 15653 | }; |
| 15654 | |
| 15655 | class mulI_mem_immNode : public MachNode { |
| 15656 | private: |
| 15657 | MachOper *_opnd_array[3]; |
| 15658 | public: |
| 15659 | MachOper *opnd_array(uint operand_index) const { |
| 15660 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15661 | return _opnd_array[operand_index]; |
| 15662 | } |
| 15663 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15664 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15665 | _opnd_array[operand_index] = operand; |
| 15666 | } |
| 15667 | private: |
| 15668 | virtual const RegMask &out_RegMask() const; |
| 15669 | virtual uint rule() const { return mulI_mem_imm_rule; } |
| 15670 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15671 | virtual int ideal_Opcode() const { return Op_MulI; } |
| 15672 | virtual int reloc() const; |
| 15673 | virtual uint oper_input_base() const { return 2; } |
| 15674 | public: |
| 15675 | mulI_mem_immNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15676 | virtual uint size_of() const { return sizeof(mulI_mem_immNode); } |
| 15677 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15678 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15679 | static const Pipeline *pipeline_class(); |
| 15680 | virtual const Pipeline *pipeline() const; |
| 15681 | virtual const MachOper *memory_operand() const; |
| 15682 | #ifndef PRODUCT |
| 15683 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15684 | virtual const char *Name() const { return "mulI_mem_imm";} |
| 15685 | #endif |
| 15686 | }; |
| 15687 | |
| 15688 | class mulAddS2I_rRegNode : public MachNode { |
| 15689 | private: |
| 15690 | MachOper *_opnd_array[5]; |
| 15691 | public: |
| 15692 | MachOper *opnd_array(uint operand_index) const { |
| 15693 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15694 | return _opnd_array[operand_index]; |
| 15695 | } |
| 15696 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15697 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15698 | _opnd_array[operand_index] = operand; |
| 15699 | } |
| 15700 | private: |
| 15701 | virtual const RegMask &out_RegMask() const; |
| 15702 | virtual uint rule() const { return mulAddS2I_rReg_rule; } |
| 15703 | virtual int ideal_Opcode() const { return Op_MulAddS2I; } |
| 15704 | virtual uint two_adr() const { return oper_input_base(); } |
| 15705 | public: |
| 15706 | mulAddS2I_rRegNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 15707 | virtual uint size_of() const { return sizeof(mulAddS2I_rRegNode); } |
| 15708 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15709 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15710 | #ifndef PRODUCT |
| 15711 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15712 | virtual const char *Name() const { return "mulAddS2I_rReg";} |
| 15713 | #endif |
| 15714 | }; |
| 15715 | |
| 15716 | class mulL_rRegNode : public MachNode { |
| 15717 | private: |
| 15718 | MachOper *_opnd_array[3]; |
| 15719 | public: |
| 15720 | MachOper *opnd_array(uint operand_index) const { |
| 15721 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15722 | return _opnd_array[operand_index]; |
| 15723 | } |
| 15724 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15725 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15726 | _opnd_array[operand_index] = operand; |
| 15727 | } |
| 15728 | private: |
| 15729 | const RegMask *_cisc_RegMask; |
| 15730 | virtual const RegMask &out_RegMask() const; |
| 15731 | virtual uint rule() const { return mulL_rReg_rule; } |
| 15732 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15733 | virtual int ideal_Opcode() const { return Op_MulL; } |
| 15734 | virtual uint two_adr() const { return oper_input_base(); } |
| 15735 | virtual int cisc_operand() const { return 2; } |
| 15736 | virtual MachNode *cisc_version(int offset); |
| 15737 | virtual void use_cisc_RegMask(); |
| 15738 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15739 | public: |
| 15740 | mulL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15741 | virtual uint size_of() const { return sizeof(mulL_rRegNode); } |
| 15742 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15743 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15744 | static const Pipeline *pipeline_class(); |
| 15745 | virtual const Pipeline *pipeline() const; |
| 15746 | #ifndef PRODUCT |
| 15747 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15748 | virtual const char *Name() const { return "mulL_rReg";} |
| 15749 | #endif |
| 15750 | }; |
| 15751 | |
| 15752 | class mulL_rReg_immNode : public MachNode { |
| 15753 | private: |
| 15754 | MachOper *_opnd_array[3]; |
| 15755 | public: |
| 15756 | MachOper *opnd_array(uint operand_index) const { |
| 15757 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15758 | return _opnd_array[operand_index]; |
| 15759 | } |
| 15760 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15761 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15762 | _opnd_array[operand_index] = operand; |
| 15763 | } |
| 15764 | private: |
| 15765 | const RegMask *_cisc_RegMask; |
| 15766 | virtual const RegMask &out_RegMask() const; |
| 15767 | virtual uint rule() const { return mulL_rReg_imm_rule; } |
| 15768 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15769 | virtual int ideal_Opcode() const { return Op_MulL; } |
| 15770 | virtual int cisc_operand() const { return 1; } |
| 15771 | virtual MachNode *cisc_version(int offset); |
| 15772 | virtual void use_cisc_RegMask(); |
| 15773 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 15774 | public: |
| 15775 | mulL_rReg_immNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 15776 | virtual uint size_of() const { return sizeof(mulL_rReg_immNode); } |
| 15777 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15778 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15779 | static const Pipeline *pipeline_class(); |
| 15780 | virtual const Pipeline *pipeline() const; |
| 15781 | #ifndef PRODUCT |
| 15782 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15783 | virtual const char *Name() const { return "mulL_rReg_imm";} |
| 15784 | #endif |
| 15785 | }; |
| 15786 | |
| 15787 | class mulL_memNode : public MachNode { |
| 15788 | private: |
| 15789 | MachOper *_opnd_array[3]; |
| 15790 | public: |
| 15791 | MachOper *opnd_array(uint operand_index) const { |
| 15792 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15793 | return _opnd_array[operand_index]; |
| 15794 | } |
| 15795 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15797 | _opnd_array[operand_index] = operand; |
| 15798 | } |
| 15799 | private: |
| 15800 | virtual const RegMask &out_RegMask() const; |
| 15801 | virtual uint rule() const { return mulL_mem_rule; } |
| 15802 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15803 | virtual int ideal_Opcode() const { return Op_MulL; } |
| 15804 | virtual uint two_adr() const { return oper_input_base(); } |
| 15805 | virtual int reloc() const; |
| 15806 | virtual uint oper_input_base() const { return 2; } |
| 15807 | public: |
| 15808 | mulL_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15809 | virtual uint size_of() const { return sizeof(mulL_memNode); } |
| 15810 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15811 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15812 | static const Pipeline *pipeline_class(); |
| 15813 | virtual const Pipeline *pipeline() const; |
| 15814 | virtual const MachOper *memory_operand() const; |
| 15815 | #ifndef PRODUCT |
| 15816 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15817 | virtual const char *Name() const { return "mulL_mem";} |
| 15818 | #endif |
| 15819 | }; |
| 15820 | |
| 15821 | class mulL_mem_0Node : public MachNode { |
| 15822 | private: |
| 15823 | MachOper *_opnd_array[3]; |
| 15824 | public: |
| 15825 | MachOper *opnd_array(uint operand_index) const { |
| 15826 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15827 | return _opnd_array[operand_index]; |
| 15828 | } |
| 15829 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15831 | _opnd_array[operand_index] = operand; |
| 15832 | } |
| 15833 | private: |
| 15834 | virtual const RegMask &out_RegMask() const; |
| 15835 | virtual uint rule() const { return mulL_mem_0_rule; } |
| 15836 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15837 | virtual int ideal_Opcode() const { return Op_MulL; } |
| 15838 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 15839 | virtual int reloc() const; |
| 15840 | virtual uint oper_input_base() const { return 2; } |
| 15841 | public: |
| 15842 | mulL_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 15843 | virtual uint size_of() const { return sizeof(mulL_mem_0Node); } |
| 15844 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15845 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15846 | static const Pipeline *pipeline_class(); |
| 15847 | virtual const Pipeline *pipeline() const; |
| 15848 | virtual const MachOper *memory_operand() const; |
| 15849 | #ifndef PRODUCT |
| 15850 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15851 | virtual const char *Name() const { return "mulL_mem_0";} |
| 15852 | #endif |
| 15853 | }; |
| 15854 | |
| 15855 | class mulL_mem_immNode : public MachNode { |
| 15856 | private: |
| 15857 | MachOper *_opnd_array[3]; |
| 15858 | public: |
| 15859 | MachOper *opnd_array(uint operand_index) const { |
| 15860 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15861 | return _opnd_array[operand_index]; |
| 15862 | } |
| 15863 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15864 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15865 | _opnd_array[operand_index] = operand; |
| 15866 | } |
| 15867 | private: |
| 15868 | virtual const RegMask &out_RegMask() const; |
| 15869 | virtual uint rule() const { return mulL_mem_imm_rule; } |
| 15870 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15871 | virtual int ideal_Opcode() const { return Op_MulL; } |
| 15872 | virtual int reloc() const; |
| 15873 | virtual uint oper_input_base() const { return 2; } |
| 15874 | public: |
| 15875 | mulL_mem_immNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 15876 | virtual uint size_of() const { return sizeof(mulL_mem_immNode); } |
| 15877 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15878 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15879 | static const Pipeline *pipeline_class(); |
| 15880 | virtual const Pipeline *pipeline() const; |
| 15881 | virtual const MachOper *memory_operand() const; |
| 15882 | #ifndef PRODUCT |
| 15883 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15884 | virtual const char *Name() const { return "mulL_mem_imm";} |
| 15885 | #endif |
| 15886 | }; |
| 15887 | |
| 15888 | class mulHiL_rRegNode : public MachNode { |
| 15889 | private: |
| 15890 | MachOper *_opnd_array[3]; |
| 15891 | public: |
| 15892 | MachOper *opnd_array(uint operand_index) const { |
| 15893 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15894 | return _opnd_array[operand_index]; |
| 15895 | } |
| 15896 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15897 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15898 | _opnd_array[operand_index] = operand; |
| 15899 | } |
| 15900 | private: |
| 15901 | virtual const RegMask &out_RegMask() const; |
| 15902 | virtual uint rule() const { return mulHiL_rReg_rule; } |
| 15903 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15904 | virtual int ideal_Opcode() const { return Op_MulHiL; } |
| 15905 | public: |
| 15906 | mulHiL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15907 | virtual uint size_of() const { return sizeof(mulHiL_rRegNode); } |
| 15908 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15909 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15910 | static const Pipeline *pipeline_class(); |
| 15911 | virtual const Pipeline *pipeline() const; |
| 15912 | #ifndef PRODUCT |
| 15913 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15914 | virtual const char *Name() const { return "mulHiL_rReg";} |
| 15915 | #endif |
| 15916 | }; |
| 15917 | |
| 15918 | class divI_rRegNode : public MachNode { |
| 15919 | private: |
| 15920 | MachOper *_opnd_array[3]; |
| 15921 | public: |
| 15922 | MachOper *opnd_array(uint operand_index) const { |
| 15923 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15924 | return _opnd_array[operand_index]; |
| 15925 | } |
| 15926 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15927 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15928 | _opnd_array[operand_index] = operand; |
| 15929 | } |
| 15930 | private: |
| 15931 | virtual const RegMask &out_RegMask() const; |
| 15932 | virtual uint rule() const { return divI_rReg_rule; } |
| 15933 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15934 | virtual int ideal_Opcode() const { return Op_DivI; } |
| 15935 | virtual uint two_adr() const { return oper_input_base(); } |
| 15936 | public: |
| 15937 | divI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15938 | virtual uint size_of() const { return sizeof(divI_rRegNode); } |
| 15939 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15940 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15941 | static const Pipeline *pipeline_class(); |
| 15942 | virtual const Pipeline *pipeline() const; |
| 15943 | #ifndef PRODUCT |
| 15944 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15945 | virtual const char *Name() const { return "divI_rReg";} |
| 15946 | #endif |
| 15947 | }; |
| 15948 | |
| 15949 | class divL_rRegNode : public MachNode { |
| 15950 | private: |
| 15951 | MachOper *_opnd_array[3]; |
| 15952 | public: |
| 15953 | MachOper *opnd_array(uint operand_index) const { |
| 15954 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15955 | return _opnd_array[operand_index]; |
| 15956 | } |
| 15957 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15958 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15959 | _opnd_array[operand_index] = operand; |
| 15960 | } |
| 15961 | private: |
| 15962 | virtual const RegMask &out_RegMask() const; |
| 15963 | virtual uint rule() const { return divL_rReg_rule; } |
| 15964 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15965 | virtual int ideal_Opcode() const { return Op_DivL; } |
| 15966 | virtual uint two_adr() const { return oper_input_base(); } |
| 15967 | public: |
| 15968 | divL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15969 | virtual uint size_of() const { return sizeof(divL_rRegNode); } |
| 15970 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 15971 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 15972 | static const Pipeline *pipeline_class(); |
| 15973 | virtual const Pipeline *pipeline() const; |
| 15974 | #ifndef PRODUCT |
| 15975 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 15976 | virtual const char *Name() const { return "divL_rReg";} |
| 15977 | #endif |
| 15978 | }; |
| 15979 | |
| 15980 | class divModI_rReg_divmodNode : public MachNode { |
| 15981 | private: |
| 15982 | MachOper *_opnd_array[3]; |
| 15983 | public: |
| 15984 | MachOper *opnd_array(uint operand_index) const { |
| 15985 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15986 | return _opnd_array[operand_index]; |
| 15987 | } |
| 15988 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 15989 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 15990 | _opnd_array[operand_index] = operand; |
| 15991 | } |
| 15992 | private: |
| 15993 | virtual const RegMask &out_RegMask() const; |
| 15994 | virtual uint rule() const { return divModI_rReg_divmod_rule; } |
| 15995 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 15996 | virtual int ideal_Opcode() const { return Op_DivModI; } |
| 15997 | public: |
| 15998 | divModI_rReg_divmodNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 15999 | virtual uint size_of() const { return sizeof(divModI_rReg_divmodNode); } |
| 16000 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16001 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16002 | static const Pipeline *pipeline_class(); |
| 16003 | virtual const Pipeline *pipeline() const; |
| 16004 | #ifndef PRODUCT |
| 16005 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16006 | virtual const char *Name() const { return "divModI_rReg_divmod";} |
| 16007 | #endif |
| 16008 | }; |
| 16009 | |
| 16010 | class divModL_rReg_divmodNode : public MachNode { |
| 16011 | private: |
| 16012 | MachOper *_opnd_array[3]; |
| 16013 | public: |
| 16014 | MachOper *opnd_array(uint operand_index) const { |
| 16015 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16016 | return _opnd_array[operand_index]; |
| 16017 | } |
| 16018 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16019 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16020 | _opnd_array[operand_index] = operand; |
| 16021 | } |
| 16022 | private: |
| 16023 | virtual const RegMask &out_RegMask() const; |
| 16024 | virtual uint rule() const { return divModL_rReg_divmod_rule; } |
| 16025 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16026 | virtual int ideal_Opcode() const { return Op_DivModL; } |
| 16027 | public: |
| 16028 | divModL_rReg_divmodNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16029 | virtual uint size_of() const { return sizeof(divModL_rReg_divmodNode); } |
| 16030 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16031 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16032 | static const Pipeline *pipeline_class(); |
| 16033 | virtual const Pipeline *pipeline() const; |
| 16034 | #ifndef PRODUCT |
| 16035 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16036 | virtual const char *Name() const { return "divModL_rReg_divmod";} |
| 16037 | #endif |
| 16038 | }; |
| 16039 | |
| 16040 | class loadConL_0x6666666666666667Node : public MachNode { |
| 16041 | private: |
| 16042 | MachOper *_opnd_array[1]; |
| 16043 | public: |
| 16044 | MachOper *opnd_array(uint operand_index) const { |
| 16045 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16046 | return _opnd_array[operand_index]; |
| 16047 | } |
| 16048 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16049 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16050 | _opnd_array[operand_index] = operand; |
| 16051 | } |
| 16052 | private: |
| 16053 | virtual const RegMask &out_RegMask() const; |
| 16054 | virtual uint rule() const { return loadConL_0x6666666666666667_rule; } |
| 16055 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16056 | public: |
| 16057 | loadConL_0x6666666666666667Node() { _num_opnds = 1; _opnds = _opnd_array; } |
| 16058 | virtual uint size_of() const { return sizeof(loadConL_0x6666666666666667Node); } |
| 16059 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16060 | static const Pipeline *pipeline_class(); |
| 16061 | virtual const Pipeline *pipeline() const; |
| 16062 | #ifndef PRODUCT |
| 16063 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16064 | virtual const char *Name() const { return "loadConL_0x6666666666666667";} |
| 16065 | #endif |
| 16066 | }; |
| 16067 | |
| 16068 | class mul_hiNode : public MachNode { |
| 16069 | private: |
| 16070 | MachOper *_opnd_array[3]; |
| 16071 | public: |
| 16072 | MachOper *opnd_array(uint operand_index) const { |
| 16073 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16074 | return _opnd_array[operand_index]; |
| 16075 | } |
| 16076 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16077 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16078 | _opnd_array[operand_index] = operand; |
| 16079 | } |
| 16080 | private: |
| 16081 | virtual const RegMask &out_RegMask() const; |
| 16082 | virtual uint rule() const { return mul_hi_rule; } |
| 16083 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16084 | public: |
| 16085 | mul_hiNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16086 | virtual uint size_of() const { return sizeof(mul_hiNode); } |
| 16087 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16088 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16089 | static const Pipeline *pipeline_class(); |
| 16090 | virtual const Pipeline *pipeline() const; |
| 16091 | #ifndef PRODUCT |
| 16092 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16093 | virtual const char *Name() const { return "mul_hi";} |
| 16094 | #endif |
| 16095 | }; |
| 16096 | |
| 16097 | class sarL_rReg_63Node : public MachNode { |
| 16098 | private: |
| 16099 | MachOper *_opnd_array[2]; |
| 16100 | public: |
| 16101 | MachOper *opnd_array(uint operand_index) const { |
| 16102 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16103 | return _opnd_array[operand_index]; |
| 16104 | } |
| 16105 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16107 | _opnd_array[operand_index] = operand; |
| 16108 | } |
| 16109 | private: |
| 16110 | virtual const RegMask &out_RegMask() const; |
| 16111 | virtual uint rule() const { return sarL_rReg_63_rule; } |
| 16112 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16113 | virtual uint two_adr() const { return oper_input_base(); } |
| 16114 | public: |
| 16115 | sarL_rReg_63Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 16116 | virtual uint size_of() const { return sizeof(sarL_rReg_63Node); } |
| 16117 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16118 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16119 | static const Pipeline *pipeline_class(); |
| 16120 | virtual const Pipeline *pipeline() const; |
| 16121 | #ifndef PRODUCT |
| 16122 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16123 | virtual const char *Name() const { return "sarL_rReg_63";} |
| 16124 | #endif |
| 16125 | }; |
| 16126 | |
| 16127 | class sarL_rReg_2Node : public MachNode { |
| 16128 | private: |
| 16129 | MachOper *_opnd_array[2]; |
| 16130 | public: |
| 16131 | MachOper *opnd_array(uint operand_index) const { |
| 16132 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16133 | return _opnd_array[operand_index]; |
| 16134 | } |
| 16135 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16136 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16137 | _opnd_array[operand_index] = operand; |
| 16138 | } |
| 16139 | private: |
| 16140 | virtual const RegMask &out_RegMask() const; |
| 16141 | virtual uint rule() const { return sarL_rReg_2_rule; } |
| 16142 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16143 | virtual uint two_adr() const { return oper_input_base(); } |
| 16144 | public: |
| 16145 | sarL_rReg_2Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 16146 | virtual uint size_of() const { return sizeof(sarL_rReg_2Node); } |
| 16147 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16148 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16149 | static const Pipeline *pipeline_class(); |
| 16150 | virtual const Pipeline *pipeline() const; |
| 16151 | #ifndef PRODUCT |
| 16152 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16153 | virtual const char *Name() const { return "sarL_rReg_2";} |
| 16154 | #endif |
| 16155 | }; |
| 16156 | |
| 16157 | class divL_10Node : public MachNode { |
| 16158 | private: |
| 16159 | MachOper *_opnd_array[3]; |
| 16160 | public: |
| 16161 | MachOper *opnd_array(uint operand_index) const { |
| 16162 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16163 | return _opnd_array[operand_index]; |
| 16164 | } |
| 16165 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16166 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16167 | _opnd_array[operand_index] = operand; |
| 16168 | } |
| 16169 | private: |
| 16170 | virtual const RegMask &out_RegMask() const; |
| 16171 | virtual uint rule() const { return divL_10_rule; } |
| 16172 | virtual int ideal_Opcode() const { return Op_DivL; } |
| 16173 | public: |
| 16174 | divL_10Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16175 | virtual uint size_of() const { return sizeof(divL_10Node); } |
| 16176 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16177 | #ifndef PRODUCT |
| 16178 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16179 | virtual const char *Name() const { return "divL_10";} |
| 16180 | #endif |
| 16181 | }; |
| 16182 | |
| 16183 | class modI_rRegNode : public MachNode { |
| 16184 | private: |
| 16185 | MachOper *_opnd_array[3]; |
| 16186 | public: |
| 16187 | MachOper *opnd_array(uint operand_index) const { |
| 16188 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16189 | return _opnd_array[operand_index]; |
| 16190 | } |
| 16191 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16192 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16193 | _opnd_array[operand_index] = operand; |
| 16194 | } |
| 16195 | private: |
| 16196 | virtual const RegMask &out_RegMask() const; |
| 16197 | virtual uint rule() const { return modI_rReg_rule; } |
| 16198 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16199 | virtual int ideal_Opcode() const { return Op_ModI; } |
| 16200 | public: |
| 16201 | modI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16202 | virtual uint size_of() const { return sizeof(modI_rRegNode); } |
| 16203 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16204 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16205 | static const Pipeline *pipeline_class(); |
| 16206 | virtual const Pipeline *pipeline() const; |
| 16207 | #ifndef PRODUCT |
| 16208 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16209 | virtual const char *Name() const { return "modI_rReg";} |
| 16210 | #endif |
| 16211 | }; |
| 16212 | |
| 16213 | class modL_rRegNode : public MachNode { |
| 16214 | private: |
| 16215 | MachOper *_opnd_array[3]; |
| 16216 | public: |
| 16217 | MachOper *opnd_array(uint operand_index) const { |
| 16218 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16219 | return _opnd_array[operand_index]; |
| 16220 | } |
| 16221 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16222 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16223 | _opnd_array[operand_index] = operand; |
| 16224 | } |
| 16225 | private: |
| 16226 | virtual const RegMask &out_RegMask() const; |
| 16227 | virtual uint rule() const { return modL_rReg_rule; } |
| 16228 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16229 | virtual int ideal_Opcode() const { return Op_ModL; } |
| 16230 | public: |
| 16231 | modL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16232 | virtual uint size_of() const { return sizeof(modL_rRegNode); } |
| 16233 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16234 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16235 | static const Pipeline *pipeline_class(); |
| 16236 | virtual const Pipeline *pipeline() const; |
| 16237 | #ifndef PRODUCT |
| 16238 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16239 | virtual const char *Name() const { return "modL_rReg";} |
| 16240 | #endif |
| 16241 | }; |
| 16242 | |
| 16243 | class salI_rReg_1Node : public MachNode { |
| 16244 | private: |
| 16245 | MachOper *_opnd_array[3]; |
| 16246 | public: |
| 16247 | MachOper *opnd_array(uint operand_index) const { |
| 16248 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16249 | return _opnd_array[operand_index]; |
| 16250 | } |
| 16251 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16252 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16253 | _opnd_array[operand_index] = operand; |
| 16254 | } |
| 16255 | private: |
| 16256 | virtual const RegMask &out_RegMask() const; |
| 16257 | virtual uint rule() const { return salI_rReg_1_rule; } |
| 16258 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16259 | virtual int ideal_Opcode() const { return Op_LShiftI; } |
| 16260 | virtual uint two_adr() const { return oper_input_base(); } |
| 16261 | public: |
| 16262 | salI_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16263 | virtual uint size_of() const { return sizeof(salI_rReg_1Node); } |
| 16264 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16265 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16266 | static const Pipeline *pipeline_class(); |
| 16267 | virtual const Pipeline *pipeline() const; |
| 16268 | #ifndef PRODUCT |
| 16269 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16270 | virtual const char *Name() const { return "salI_rReg_1";} |
| 16271 | #endif |
| 16272 | }; |
| 16273 | |
| 16274 | class salI_mem_1Node : public MachTypeNode { |
| 16275 | private: |
| 16276 | MachOper *_opnd_array[4]; |
| 16277 | public: |
| 16278 | MachOper *opnd_array(uint operand_index) const { |
| 16279 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16280 | return _opnd_array[operand_index]; |
| 16281 | } |
| 16282 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16283 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16284 | _opnd_array[operand_index] = operand; |
| 16285 | } |
| 16286 | private: |
| 16287 | virtual const RegMask &out_RegMask() const; |
| 16288 | virtual uint rule() const { return salI_mem_1_rule; } |
| 16289 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16290 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16291 | virtual int reloc() const; |
| 16292 | virtual uint oper_input_base() const { return 2; } |
| 16293 | public: |
| 16294 | salI_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16295 | virtual uint size_of() const { return sizeof(salI_mem_1Node); } |
| 16296 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16297 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16298 | static const Pipeline *pipeline_class(); |
| 16299 | virtual const Pipeline *pipeline() const; |
| 16300 | virtual const MachOper *memory_operand() const; |
| 16301 | #ifndef PRODUCT |
| 16302 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16303 | virtual const char *Name() const { return "salI_mem_1";} |
| 16304 | #endif |
| 16305 | }; |
| 16306 | |
| 16307 | class salI_rReg_immNode : public MachNode { |
| 16308 | private: |
| 16309 | MachOper *_opnd_array[3]; |
| 16310 | public: |
| 16311 | MachOper *opnd_array(uint operand_index) const { |
| 16312 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16313 | return _opnd_array[operand_index]; |
| 16314 | } |
| 16315 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16316 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16317 | _opnd_array[operand_index] = operand; |
| 16318 | } |
| 16319 | private: |
| 16320 | virtual const RegMask &out_RegMask() const; |
| 16321 | virtual uint rule() const { return salI_rReg_imm_rule; } |
| 16322 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16323 | virtual int ideal_Opcode() const { return Op_LShiftI; } |
| 16324 | virtual uint two_adr() const { return oper_input_base(); } |
| 16325 | public: |
| 16326 | salI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16327 | virtual uint size_of() const { return sizeof(salI_rReg_immNode); } |
| 16328 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16329 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16330 | static const Pipeline *pipeline_class(); |
| 16331 | virtual const Pipeline *pipeline() const; |
| 16332 | #ifndef PRODUCT |
| 16333 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16334 | virtual const char *Name() const { return "salI_rReg_imm";} |
| 16335 | #endif |
| 16336 | }; |
| 16337 | |
| 16338 | class salI_mem_immNode : public MachTypeNode { |
| 16339 | private: |
| 16340 | MachOper *_opnd_array[4]; |
| 16341 | public: |
| 16342 | MachOper *opnd_array(uint operand_index) const { |
| 16343 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16344 | return _opnd_array[operand_index]; |
| 16345 | } |
| 16346 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16347 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16348 | _opnd_array[operand_index] = operand; |
| 16349 | } |
| 16350 | private: |
| 16351 | virtual const RegMask &out_RegMask() const; |
| 16352 | virtual uint rule() const { return salI_mem_imm_rule; } |
| 16353 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16354 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16355 | virtual int reloc() const; |
| 16356 | virtual uint oper_input_base() const { return 2; } |
| 16357 | public: |
| 16358 | salI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16359 | virtual uint size_of() const { return sizeof(salI_mem_immNode); } |
| 16360 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16361 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16362 | static const Pipeline *pipeline_class(); |
| 16363 | virtual const Pipeline *pipeline() const; |
| 16364 | virtual const MachOper *memory_operand() const; |
| 16365 | #ifndef PRODUCT |
| 16366 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16367 | virtual const char *Name() const { return "salI_mem_imm";} |
| 16368 | #endif |
| 16369 | }; |
| 16370 | |
| 16371 | class salI_rReg_CLNode : public MachNode { |
| 16372 | private: |
| 16373 | MachOper *_opnd_array[3]; |
| 16374 | public: |
| 16375 | MachOper *opnd_array(uint operand_index) const { |
| 16376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16377 | return _opnd_array[operand_index]; |
| 16378 | } |
| 16379 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16380 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16381 | _opnd_array[operand_index] = operand; |
| 16382 | } |
| 16383 | private: |
| 16384 | virtual const RegMask &out_RegMask() const; |
| 16385 | virtual uint rule() const { return salI_rReg_CL_rule; } |
| 16386 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16387 | virtual int ideal_Opcode() const { return Op_LShiftI; } |
| 16388 | virtual uint two_adr() const { return oper_input_base(); } |
| 16389 | public: |
| 16390 | salI_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16391 | virtual uint size_of() const { return sizeof(salI_rReg_CLNode); } |
| 16392 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16393 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16394 | static const Pipeline *pipeline_class(); |
| 16395 | virtual const Pipeline *pipeline() const; |
| 16396 | #ifndef PRODUCT |
| 16397 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16398 | virtual const char *Name() const { return "salI_rReg_CL";} |
| 16399 | #endif |
| 16400 | }; |
| 16401 | |
| 16402 | class salI_mem_CLNode : public MachTypeNode { |
| 16403 | private: |
| 16404 | MachOper *_opnd_array[4]; |
| 16405 | public: |
| 16406 | MachOper *opnd_array(uint operand_index) const { |
| 16407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16408 | return _opnd_array[operand_index]; |
| 16409 | } |
| 16410 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16412 | _opnd_array[operand_index] = operand; |
| 16413 | } |
| 16414 | private: |
| 16415 | virtual const RegMask &out_RegMask() const; |
| 16416 | virtual uint rule() const { return salI_mem_CL_rule; } |
| 16417 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16418 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16419 | virtual int reloc() const; |
| 16420 | virtual uint oper_input_base() const { return 2; } |
| 16421 | public: |
| 16422 | salI_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16423 | virtual uint size_of() const { return sizeof(salI_mem_CLNode); } |
| 16424 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16425 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16426 | static const Pipeline *pipeline_class(); |
| 16427 | virtual const Pipeline *pipeline() const; |
| 16428 | virtual const MachOper *memory_operand() const; |
| 16429 | #ifndef PRODUCT |
| 16430 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16431 | virtual const char *Name() const { return "salI_mem_CL";} |
| 16432 | #endif |
| 16433 | }; |
| 16434 | |
| 16435 | class sarI_rReg_1Node : public MachNode { |
| 16436 | private: |
| 16437 | MachOper *_opnd_array[3]; |
| 16438 | public: |
| 16439 | MachOper *opnd_array(uint operand_index) const { |
| 16440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16441 | return _opnd_array[operand_index]; |
| 16442 | } |
| 16443 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16444 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16445 | _opnd_array[operand_index] = operand; |
| 16446 | } |
| 16447 | private: |
| 16448 | virtual const RegMask &out_RegMask() const; |
| 16449 | virtual uint rule() const { return sarI_rReg_1_rule; } |
| 16450 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16451 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 16452 | virtual uint two_adr() const { return oper_input_base(); } |
| 16453 | public: |
| 16454 | sarI_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16455 | virtual uint size_of() const { return sizeof(sarI_rReg_1Node); } |
| 16456 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16457 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16458 | static const Pipeline *pipeline_class(); |
| 16459 | virtual const Pipeline *pipeline() const; |
| 16460 | #ifndef PRODUCT |
| 16461 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16462 | virtual const char *Name() const { return "sarI_rReg_1";} |
| 16463 | #endif |
| 16464 | }; |
| 16465 | |
| 16466 | class sarI_mem_1Node : public MachTypeNode { |
| 16467 | private: |
| 16468 | MachOper *_opnd_array[4]; |
| 16469 | public: |
| 16470 | MachOper *opnd_array(uint operand_index) const { |
| 16471 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16472 | return _opnd_array[operand_index]; |
| 16473 | } |
| 16474 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16475 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16476 | _opnd_array[operand_index] = operand; |
| 16477 | } |
| 16478 | private: |
| 16479 | virtual const RegMask &out_RegMask() const; |
| 16480 | virtual uint rule() const { return sarI_mem_1_rule; } |
| 16481 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16482 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16483 | virtual int reloc() const; |
| 16484 | virtual uint oper_input_base() const { return 2; } |
| 16485 | public: |
| 16486 | sarI_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16487 | virtual uint size_of() const { return sizeof(sarI_mem_1Node); } |
| 16488 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16489 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16490 | static const Pipeline *pipeline_class(); |
| 16491 | virtual const Pipeline *pipeline() const; |
| 16492 | virtual const MachOper *memory_operand() const; |
| 16493 | #ifndef PRODUCT |
| 16494 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16495 | virtual const char *Name() const { return "sarI_mem_1";} |
| 16496 | #endif |
| 16497 | }; |
| 16498 | |
| 16499 | class sarI_rReg_immNode : public MachNode { |
| 16500 | private: |
| 16501 | MachOper *_opnd_array[3]; |
| 16502 | public: |
| 16503 | MachOper *opnd_array(uint operand_index) const { |
| 16504 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16505 | return _opnd_array[operand_index]; |
| 16506 | } |
| 16507 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16508 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16509 | _opnd_array[operand_index] = operand; |
| 16510 | } |
| 16511 | private: |
| 16512 | virtual const RegMask &out_RegMask() const; |
| 16513 | virtual uint rule() const { return sarI_rReg_imm_rule; } |
| 16514 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16515 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 16516 | virtual uint two_adr() const { return oper_input_base(); } |
| 16517 | public: |
| 16518 | sarI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16519 | virtual uint size_of() const { return sizeof(sarI_rReg_immNode); } |
| 16520 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16521 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16522 | static const Pipeline *pipeline_class(); |
| 16523 | virtual const Pipeline *pipeline() const; |
| 16524 | #ifndef PRODUCT |
| 16525 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16526 | virtual const char *Name() const { return "sarI_rReg_imm";} |
| 16527 | #endif |
| 16528 | }; |
| 16529 | |
| 16530 | class sarI_mem_immNode : public MachTypeNode { |
| 16531 | private: |
| 16532 | MachOper *_opnd_array[4]; |
| 16533 | public: |
| 16534 | MachOper *opnd_array(uint operand_index) const { |
| 16535 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16536 | return _opnd_array[operand_index]; |
| 16537 | } |
| 16538 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16539 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16540 | _opnd_array[operand_index] = operand; |
| 16541 | } |
| 16542 | private: |
| 16543 | virtual const RegMask &out_RegMask() const; |
| 16544 | virtual uint rule() const { return sarI_mem_imm_rule; } |
| 16545 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16546 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16547 | virtual int reloc() const; |
| 16548 | virtual uint oper_input_base() const { return 2; } |
| 16549 | public: |
| 16550 | sarI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16551 | virtual uint size_of() const { return sizeof(sarI_mem_immNode); } |
| 16552 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16553 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16554 | static const Pipeline *pipeline_class(); |
| 16555 | virtual const Pipeline *pipeline() const; |
| 16556 | virtual const MachOper *memory_operand() const; |
| 16557 | #ifndef PRODUCT |
| 16558 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16559 | virtual const char *Name() const { return "sarI_mem_imm";} |
| 16560 | #endif |
| 16561 | }; |
| 16562 | |
| 16563 | class sarI_rReg_CLNode : public MachNode { |
| 16564 | private: |
| 16565 | MachOper *_opnd_array[3]; |
| 16566 | public: |
| 16567 | MachOper *opnd_array(uint operand_index) const { |
| 16568 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16569 | return _opnd_array[operand_index]; |
| 16570 | } |
| 16571 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16572 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16573 | _opnd_array[operand_index] = operand; |
| 16574 | } |
| 16575 | private: |
| 16576 | virtual const RegMask &out_RegMask() const; |
| 16577 | virtual uint rule() const { return sarI_rReg_CL_rule; } |
| 16578 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16579 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 16580 | virtual uint two_adr() const { return oper_input_base(); } |
| 16581 | public: |
| 16582 | sarI_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16583 | virtual uint size_of() const { return sizeof(sarI_rReg_CLNode); } |
| 16584 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16585 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16586 | static const Pipeline *pipeline_class(); |
| 16587 | virtual const Pipeline *pipeline() const; |
| 16588 | #ifndef PRODUCT |
| 16589 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16590 | virtual const char *Name() const { return "sarI_rReg_CL";} |
| 16591 | #endif |
| 16592 | }; |
| 16593 | |
| 16594 | class sarI_mem_CLNode : public MachTypeNode { |
| 16595 | private: |
| 16596 | MachOper *_opnd_array[4]; |
| 16597 | public: |
| 16598 | MachOper *opnd_array(uint operand_index) const { |
| 16599 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16600 | return _opnd_array[operand_index]; |
| 16601 | } |
| 16602 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16603 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16604 | _opnd_array[operand_index] = operand; |
| 16605 | } |
| 16606 | private: |
| 16607 | virtual const RegMask &out_RegMask() const; |
| 16608 | virtual uint rule() const { return sarI_mem_CL_rule; } |
| 16609 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16610 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16611 | virtual int reloc() const; |
| 16612 | virtual uint oper_input_base() const { return 2; } |
| 16613 | public: |
| 16614 | sarI_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16615 | virtual uint size_of() const { return sizeof(sarI_mem_CLNode); } |
| 16616 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16617 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16618 | static const Pipeline *pipeline_class(); |
| 16619 | virtual const Pipeline *pipeline() const; |
| 16620 | virtual const MachOper *memory_operand() const; |
| 16621 | #ifndef PRODUCT |
| 16622 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16623 | virtual const char *Name() const { return "sarI_mem_CL";} |
| 16624 | #endif |
| 16625 | }; |
| 16626 | |
| 16627 | class shrI_rReg_1Node : public MachNode { |
| 16628 | private: |
| 16629 | MachOper *_opnd_array[3]; |
| 16630 | public: |
| 16631 | MachOper *opnd_array(uint operand_index) const { |
| 16632 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16633 | return _opnd_array[operand_index]; |
| 16634 | } |
| 16635 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16636 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16637 | _opnd_array[operand_index] = operand; |
| 16638 | } |
| 16639 | private: |
| 16640 | virtual const RegMask &out_RegMask() const; |
| 16641 | virtual uint rule() const { return shrI_rReg_1_rule; } |
| 16642 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16643 | virtual int ideal_Opcode() const { return Op_URShiftI; } |
| 16644 | virtual uint two_adr() const { return oper_input_base(); } |
| 16645 | public: |
| 16646 | shrI_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16647 | virtual uint size_of() const { return sizeof(shrI_rReg_1Node); } |
| 16648 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16649 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16650 | static const Pipeline *pipeline_class(); |
| 16651 | virtual const Pipeline *pipeline() const; |
| 16652 | #ifndef PRODUCT |
| 16653 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16654 | virtual const char *Name() const { return "shrI_rReg_1";} |
| 16655 | #endif |
| 16656 | }; |
| 16657 | |
| 16658 | class shrI_mem_1Node : public MachTypeNode { |
| 16659 | private: |
| 16660 | MachOper *_opnd_array[4]; |
| 16661 | public: |
| 16662 | MachOper *opnd_array(uint operand_index) const { |
| 16663 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16664 | return _opnd_array[operand_index]; |
| 16665 | } |
| 16666 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16667 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16668 | _opnd_array[operand_index] = operand; |
| 16669 | } |
| 16670 | private: |
| 16671 | virtual const RegMask &out_RegMask() const; |
| 16672 | virtual uint rule() const { return shrI_mem_1_rule; } |
| 16673 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16674 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16675 | virtual int reloc() const; |
| 16676 | virtual uint oper_input_base() const { return 2; } |
| 16677 | public: |
| 16678 | shrI_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16679 | virtual uint size_of() const { return sizeof(shrI_mem_1Node); } |
| 16680 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16681 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16682 | static const Pipeline *pipeline_class(); |
| 16683 | virtual const Pipeline *pipeline() const; |
| 16684 | virtual const MachOper *memory_operand() const; |
| 16685 | #ifndef PRODUCT |
| 16686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16687 | virtual const char *Name() const { return "shrI_mem_1";} |
| 16688 | #endif |
| 16689 | }; |
| 16690 | |
| 16691 | class shrI_rReg_immNode : public MachNode { |
| 16692 | private: |
| 16693 | MachOper *_opnd_array[3]; |
| 16694 | public: |
| 16695 | MachOper *opnd_array(uint operand_index) const { |
| 16696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16697 | return _opnd_array[operand_index]; |
| 16698 | } |
| 16699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16701 | _opnd_array[operand_index] = operand; |
| 16702 | } |
| 16703 | private: |
| 16704 | virtual const RegMask &out_RegMask() const; |
| 16705 | virtual uint rule() const { return shrI_rReg_imm_rule; } |
| 16706 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16707 | virtual int ideal_Opcode() const { return Op_URShiftI; } |
| 16708 | virtual uint two_adr() const { return oper_input_base(); } |
| 16709 | public: |
| 16710 | shrI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16711 | virtual uint size_of() const { return sizeof(shrI_rReg_immNode); } |
| 16712 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16713 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16714 | static const Pipeline *pipeline_class(); |
| 16715 | virtual const Pipeline *pipeline() const; |
| 16716 | #ifndef PRODUCT |
| 16717 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16718 | virtual const char *Name() const { return "shrI_rReg_imm";} |
| 16719 | #endif |
| 16720 | }; |
| 16721 | |
| 16722 | class shrI_mem_immNode : public MachTypeNode { |
| 16723 | private: |
| 16724 | MachOper *_opnd_array[4]; |
| 16725 | public: |
| 16726 | MachOper *opnd_array(uint operand_index) const { |
| 16727 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16728 | return _opnd_array[operand_index]; |
| 16729 | } |
| 16730 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16731 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16732 | _opnd_array[operand_index] = operand; |
| 16733 | } |
| 16734 | private: |
| 16735 | virtual const RegMask &out_RegMask() const; |
| 16736 | virtual uint rule() const { return shrI_mem_imm_rule; } |
| 16737 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16738 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16739 | virtual int reloc() const; |
| 16740 | virtual uint oper_input_base() const { return 2; } |
| 16741 | public: |
| 16742 | shrI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16743 | virtual uint size_of() const { return sizeof(shrI_mem_immNode); } |
| 16744 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16745 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16746 | static const Pipeline *pipeline_class(); |
| 16747 | virtual const Pipeline *pipeline() const; |
| 16748 | virtual const MachOper *memory_operand() const; |
| 16749 | #ifndef PRODUCT |
| 16750 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16751 | virtual const char *Name() const { return "shrI_mem_imm";} |
| 16752 | #endif |
| 16753 | }; |
| 16754 | |
| 16755 | class shrI_rReg_CLNode : public MachNode { |
| 16756 | private: |
| 16757 | MachOper *_opnd_array[3]; |
| 16758 | public: |
| 16759 | MachOper *opnd_array(uint operand_index) const { |
| 16760 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16761 | return _opnd_array[operand_index]; |
| 16762 | } |
| 16763 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16765 | _opnd_array[operand_index] = operand; |
| 16766 | } |
| 16767 | private: |
| 16768 | virtual const RegMask &out_RegMask() const; |
| 16769 | virtual uint rule() const { return shrI_rReg_CL_rule; } |
| 16770 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16771 | virtual int ideal_Opcode() const { return Op_URShiftI; } |
| 16772 | virtual uint two_adr() const { return oper_input_base(); } |
| 16773 | public: |
| 16774 | shrI_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16775 | virtual uint size_of() const { return sizeof(shrI_rReg_CLNode); } |
| 16776 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16777 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16778 | static const Pipeline *pipeline_class(); |
| 16779 | virtual const Pipeline *pipeline() const; |
| 16780 | #ifndef PRODUCT |
| 16781 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16782 | virtual const char *Name() const { return "shrI_rReg_CL";} |
| 16783 | #endif |
| 16784 | }; |
| 16785 | |
| 16786 | class shrI_mem_CLNode : public MachTypeNode { |
| 16787 | private: |
| 16788 | MachOper *_opnd_array[4]; |
| 16789 | public: |
| 16790 | MachOper *opnd_array(uint operand_index) const { |
| 16791 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16792 | return _opnd_array[operand_index]; |
| 16793 | } |
| 16794 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16795 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16796 | _opnd_array[operand_index] = operand; |
| 16797 | } |
| 16798 | private: |
| 16799 | virtual const RegMask &out_RegMask() const; |
| 16800 | virtual uint rule() const { return shrI_mem_CL_rule; } |
| 16801 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16802 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 16803 | virtual int reloc() const; |
| 16804 | virtual uint oper_input_base() const { return 2; } |
| 16805 | public: |
| 16806 | shrI_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16807 | virtual uint size_of() const { return sizeof(shrI_mem_CLNode); } |
| 16808 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16809 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16810 | static const Pipeline *pipeline_class(); |
| 16811 | virtual const Pipeline *pipeline() const; |
| 16812 | virtual const MachOper *memory_operand() const; |
| 16813 | #ifndef PRODUCT |
| 16814 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16815 | virtual const char *Name() const { return "shrI_mem_CL";} |
| 16816 | #endif |
| 16817 | }; |
| 16818 | |
| 16819 | class salL_rReg_1Node : public MachNode { |
| 16820 | private: |
| 16821 | MachOper *_opnd_array[3]; |
| 16822 | public: |
| 16823 | MachOper *opnd_array(uint operand_index) const { |
| 16824 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16825 | return _opnd_array[operand_index]; |
| 16826 | } |
| 16827 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16828 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16829 | _opnd_array[operand_index] = operand; |
| 16830 | } |
| 16831 | private: |
| 16832 | virtual const RegMask &out_RegMask() const; |
| 16833 | virtual uint rule() const { return salL_rReg_1_rule; } |
| 16834 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16835 | virtual int ideal_Opcode() const { return Op_LShiftL; } |
| 16836 | virtual uint two_adr() const { return oper_input_base(); } |
| 16837 | public: |
| 16838 | salL_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16839 | virtual uint size_of() const { return sizeof(salL_rReg_1Node); } |
| 16840 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16841 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16842 | static const Pipeline *pipeline_class(); |
| 16843 | virtual const Pipeline *pipeline() const; |
| 16844 | #ifndef PRODUCT |
| 16845 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16846 | virtual const char *Name() const { return "salL_rReg_1";} |
| 16847 | #endif |
| 16848 | }; |
| 16849 | |
| 16850 | class salL_mem_1Node : public MachTypeNode { |
| 16851 | private: |
| 16852 | MachOper *_opnd_array[4]; |
| 16853 | public: |
| 16854 | MachOper *opnd_array(uint operand_index) const { |
| 16855 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16856 | return _opnd_array[operand_index]; |
| 16857 | } |
| 16858 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16859 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16860 | _opnd_array[operand_index] = operand; |
| 16861 | } |
| 16862 | private: |
| 16863 | virtual const RegMask &out_RegMask() const; |
| 16864 | virtual uint rule() const { return salL_mem_1_rule; } |
| 16865 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16866 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 16867 | virtual int reloc() const; |
| 16868 | virtual uint oper_input_base() const { return 2; } |
| 16869 | public: |
| 16870 | salL_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16871 | virtual uint size_of() const { return sizeof(salL_mem_1Node); } |
| 16872 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16873 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16874 | static const Pipeline *pipeline_class(); |
| 16875 | virtual const Pipeline *pipeline() const; |
| 16876 | virtual const MachOper *memory_operand() const; |
| 16877 | #ifndef PRODUCT |
| 16878 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16879 | virtual const char *Name() const { return "salL_mem_1";} |
| 16880 | #endif |
| 16881 | }; |
| 16882 | |
| 16883 | class salL_rReg_immNode : public MachNode { |
| 16884 | private: |
| 16885 | MachOper *_opnd_array[3]; |
| 16886 | public: |
| 16887 | MachOper *opnd_array(uint operand_index) const { |
| 16888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16889 | return _opnd_array[operand_index]; |
| 16890 | } |
| 16891 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16893 | _opnd_array[operand_index] = operand; |
| 16894 | } |
| 16895 | private: |
| 16896 | virtual const RegMask &out_RegMask() const; |
| 16897 | virtual uint rule() const { return salL_rReg_imm_rule; } |
| 16898 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16899 | virtual int ideal_Opcode() const { return Op_LShiftL; } |
| 16900 | virtual uint two_adr() const { return oper_input_base(); } |
| 16901 | public: |
| 16902 | salL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16903 | virtual uint size_of() const { return sizeof(salL_rReg_immNode); } |
| 16904 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16905 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16906 | static const Pipeline *pipeline_class(); |
| 16907 | virtual const Pipeline *pipeline() const; |
| 16908 | #ifndef PRODUCT |
| 16909 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16910 | virtual const char *Name() const { return "salL_rReg_imm";} |
| 16911 | #endif |
| 16912 | }; |
| 16913 | |
| 16914 | class salL_mem_immNode : public MachTypeNode { |
| 16915 | private: |
| 16916 | MachOper *_opnd_array[4]; |
| 16917 | public: |
| 16918 | MachOper *opnd_array(uint operand_index) const { |
| 16919 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16920 | return _opnd_array[operand_index]; |
| 16921 | } |
| 16922 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16923 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16924 | _opnd_array[operand_index] = operand; |
| 16925 | } |
| 16926 | private: |
| 16927 | virtual const RegMask &out_RegMask() const; |
| 16928 | virtual uint rule() const { return salL_mem_imm_rule; } |
| 16929 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16930 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 16931 | virtual int reloc() const; |
| 16932 | virtual uint oper_input_base() const { return 2; } |
| 16933 | public: |
| 16934 | salL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16935 | virtual uint size_of() const { return sizeof(salL_mem_immNode); } |
| 16936 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16937 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16938 | static const Pipeline *pipeline_class(); |
| 16939 | virtual const Pipeline *pipeline() const; |
| 16940 | virtual const MachOper *memory_operand() const; |
| 16941 | #ifndef PRODUCT |
| 16942 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16943 | virtual const char *Name() const { return "salL_mem_imm";} |
| 16944 | #endif |
| 16945 | }; |
| 16946 | |
| 16947 | class salL_rReg_CLNode : public MachNode { |
| 16948 | private: |
| 16949 | MachOper *_opnd_array[3]; |
| 16950 | public: |
| 16951 | MachOper *opnd_array(uint operand_index) const { |
| 16952 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16953 | return _opnd_array[operand_index]; |
| 16954 | } |
| 16955 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16957 | _opnd_array[operand_index] = operand; |
| 16958 | } |
| 16959 | private: |
| 16960 | virtual const RegMask &out_RegMask() const; |
| 16961 | virtual uint rule() const { return salL_rReg_CL_rule; } |
| 16962 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16963 | virtual int ideal_Opcode() const { return Op_LShiftL; } |
| 16964 | virtual uint two_adr() const { return oper_input_base(); } |
| 16965 | public: |
| 16966 | salL_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 16967 | virtual uint size_of() const { return sizeof(salL_rReg_CLNode); } |
| 16968 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 16969 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 16970 | static const Pipeline *pipeline_class(); |
| 16971 | virtual const Pipeline *pipeline() const; |
| 16972 | #ifndef PRODUCT |
| 16973 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 16974 | virtual const char *Name() const { return "salL_rReg_CL";} |
| 16975 | #endif |
| 16976 | }; |
| 16977 | |
| 16978 | class salL_mem_CLNode : public MachTypeNode { |
| 16979 | private: |
| 16980 | MachOper *_opnd_array[4]; |
| 16981 | public: |
| 16982 | MachOper *opnd_array(uint operand_index) const { |
| 16983 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16984 | return _opnd_array[operand_index]; |
| 16985 | } |
| 16986 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 16987 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 16988 | _opnd_array[operand_index] = operand; |
| 16989 | } |
| 16990 | private: |
| 16991 | virtual const RegMask &out_RegMask() const; |
| 16992 | virtual uint rule() const { return salL_mem_CL_rule; } |
| 16993 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 16994 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 16995 | virtual int reloc() const; |
| 16996 | virtual uint oper_input_base() const { return 2; } |
| 16997 | public: |
| 16998 | salL_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 16999 | virtual uint size_of() const { return sizeof(salL_mem_CLNode); } |
| 17000 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17001 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17002 | static const Pipeline *pipeline_class(); |
| 17003 | virtual const Pipeline *pipeline() const; |
| 17004 | virtual const MachOper *memory_operand() const; |
| 17005 | #ifndef PRODUCT |
| 17006 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17007 | virtual const char *Name() const { return "salL_mem_CL";} |
| 17008 | #endif |
| 17009 | }; |
| 17010 | |
| 17011 | class sarL_rReg_1Node : public MachNode { |
| 17012 | private: |
| 17013 | MachOper *_opnd_array[3]; |
| 17014 | public: |
| 17015 | MachOper *opnd_array(uint operand_index) const { |
| 17016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17017 | return _opnd_array[operand_index]; |
| 17018 | } |
| 17019 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17020 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17021 | _opnd_array[operand_index] = operand; |
| 17022 | } |
| 17023 | private: |
| 17024 | virtual const RegMask &out_RegMask() const; |
| 17025 | virtual uint rule() const { return sarL_rReg_1_rule; } |
| 17026 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17027 | virtual int ideal_Opcode() const { return Op_RShiftL; } |
| 17028 | virtual uint two_adr() const { return oper_input_base(); } |
| 17029 | public: |
| 17030 | sarL_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17031 | virtual uint size_of() const { return sizeof(sarL_rReg_1Node); } |
| 17032 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17033 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17034 | static const Pipeline *pipeline_class(); |
| 17035 | virtual const Pipeline *pipeline() const; |
| 17036 | #ifndef PRODUCT |
| 17037 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17038 | virtual const char *Name() const { return "sarL_rReg_1";} |
| 17039 | #endif |
| 17040 | }; |
| 17041 | |
| 17042 | class sarL_mem_1Node : public MachTypeNode { |
| 17043 | private: |
| 17044 | MachOper *_opnd_array[4]; |
| 17045 | public: |
| 17046 | MachOper *opnd_array(uint operand_index) const { |
| 17047 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17048 | return _opnd_array[operand_index]; |
| 17049 | } |
| 17050 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17051 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17052 | _opnd_array[operand_index] = operand; |
| 17053 | } |
| 17054 | private: |
| 17055 | virtual const RegMask &out_RegMask() const; |
| 17056 | virtual uint rule() const { return sarL_mem_1_rule; } |
| 17057 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17058 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17059 | virtual int reloc() const; |
| 17060 | virtual uint oper_input_base() const { return 2; } |
| 17061 | public: |
| 17062 | sarL_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17063 | virtual uint size_of() const { return sizeof(sarL_mem_1Node); } |
| 17064 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17065 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17066 | static const Pipeline *pipeline_class(); |
| 17067 | virtual const Pipeline *pipeline() const; |
| 17068 | virtual const MachOper *memory_operand() const; |
| 17069 | #ifndef PRODUCT |
| 17070 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17071 | virtual const char *Name() const { return "sarL_mem_1";} |
| 17072 | #endif |
| 17073 | }; |
| 17074 | |
| 17075 | class sarL_rReg_immNode : public MachNode { |
| 17076 | private: |
| 17077 | MachOper *_opnd_array[3]; |
| 17078 | public: |
| 17079 | MachOper *opnd_array(uint operand_index) const { |
| 17080 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17081 | return _opnd_array[operand_index]; |
| 17082 | } |
| 17083 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17084 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17085 | _opnd_array[operand_index] = operand; |
| 17086 | } |
| 17087 | private: |
| 17088 | virtual const RegMask &out_RegMask() const; |
| 17089 | virtual uint rule() const { return sarL_rReg_imm_rule; } |
| 17090 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17091 | virtual int ideal_Opcode() const { return Op_RShiftL; } |
| 17092 | virtual uint two_adr() const { return oper_input_base(); } |
| 17093 | public: |
| 17094 | sarL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17095 | virtual uint size_of() const { return sizeof(sarL_rReg_immNode); } |
| 17096 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17097 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17098 | static const Pipeline *pipeline_class(); |
| 17099 | virtual const Pipeline *pipeline() const; |
| 17100 | #ifndef PRODUCT |
| 17101 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17102 | virtual const char *Name() const { return "sarL_rReg_imm";} |
| 17103 | #endif |
| 17104 | }; |
| 17105 | |
| 17106 | class sarL_mem_immNode : public MachTypeNode { |
| 17107 | private: |
| 17108 | MachOper *_opnd_array[4]; |
| 17109 | public: |
| 17110 | MachOper *opnd_array(uint operand_index) const { |
| 17111 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17112 | return _opnd_array[operand_index]; |
| 17113 | } |
| 17114 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17115 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17116 | _opnd_array[operand_index] = operand; |
| 17117 | } |
| 17118 | private: |
| 17119 | virtual const RegMask &out_RegMask() const; |
| 17120 | virtual uint rule() const { return sarL_mem_imm_rule; } |
| 17121 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17122 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17123 | virtual int reloc() const; |
| 17124 | virtual uint oper_input_base() const { return 2; } |
| 17125 | public: |
| 17126 | sarL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17127 | virtual uint size_of() const { return sizeof(sarL_mem_immNode); } |
| 17128 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17129 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17130 | static const Pipeline *pipeline_class(); |
| 17131 | virtual const Pipeline *pipeline() const; |
| 17132 | virtual const MachOper *memory_operand() const; |
| 17133 | #ifndef PRODUCT |
| 17134 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17135 | virtual const char *Name() const { return "sarL_mem_imm";} |
| 17136 | #endif |
| 17137 | }; |
| 17138 | |
| 17139 | class sarL_rReg_CLNode : public MachNode { |
| 17140 | private: |
| 17141 | MachOper *_opnd_array[3]; |
| 17142 | public: |
| 17143 | MachOper *opnd_array(uint operand_index) const { |
| 17144 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17145 | return _opnd_array[operand_index]; |
| 17146 | } |
| 17147 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17148 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17149 | _opnd_array[operand_index] = operand; |
| 17150 | } |
| 17151 | private: |
| 17152 | virtual const RegMask &out_RegMask() const; |
| 17153 | virtual uint rule() const { return sarL_rReg_CL_rule; } |
| 17154 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17155 | virtual int ideal_Opcode() const { return Op_RShiftL; } |
| 17156 | virtual uint two_adr() const { return oper_input_base(); } |
| 17157 | public: |
| 17158 | sarL_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17159 | virtual uint size_of() const { return sizeof(sarL_rReg_CLNode); } |
| 17160 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17161 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17162 | static const Pipeline *pipeline_class(); |
| 17163 | virtual const Pipeline *pipeline() const; |
| 17164 | #ifndef PRODUCT |
| 17165 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17166 | virtual const char *Name() const { return "sarL_rReg_CL";} |
| 17167 | #endif |
| 17168 | }; |
| 17169 | |
| 17170 | class sarL_mem_CLNode : public MachTypeNode { |
| 17171 | private: |
| 17172 | MachOper *_opnd_array[4]; |
| 17173 | public: |
| 17174 | MachOper *opnd_array(uint operand_index) const { |
| 17175 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17176 | return _opnd_array[operand_index]; |
| 17177 | } |
| 17178 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17179 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17180 | _opnd_array[operand_index] = operand; |
| 17181 | } |
| 17182 | private: |
| 17183 | virtual const RegMask &out_RegMask() const; |
| 17184 | virtual uint rule() const { return sarL_mem_CL_rule; } |
| 17185 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17186 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17187 | virtual int reloc() const; |
| 17188 | virtual uint oper_input_base() const { return 2; } |
| 17189 | public: |
| 17190 | sarL_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17191 | virtual uint size_of() const { return sizeof(sarL_mem_CLNode); } |
| 17192 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17193 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17194 | static const Pipeline *pipeline_class(); |
| 17195 | virtual const Pipeline *pipeline() const; |
| 17196 | virtual const MachOper *memory_operand() const; |
| 17197 | #ifndef PRODUCT |
| 17198 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17199 | virtual const char *Name() const { return "sarL_mem_CL";} |
| 17200 | #endif |
| 17201 | }; |
| 17202 | |
| 17203 | class shrL_rReg_1Node : public MachNode { |
| 17204 | private: |
| 17205 | MachOper *_opnd_array[3]; |
| 17206 | public: |
| 17207 | MachOper *opnd_array(uint operand_index) const { |
| 17208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17209 | return _opnd_array[operand_index]; |
| 17210 | } |
| 17211 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17212 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17213 | _opnd_array[operand_index] = operand; |
| 17214 | } |
| 17215 | private: |
| 17216 | virtual const RegMask &out_RegMask() const; |
| 17217 | virtual uint rule() const { return shrL_rReg_1_rule; } |
| 17218 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17219 | virtual int ideal_Opcode() const { return Op_URShiftL; } |
| 17220 | virtual uint two_adr() const { return oper_input_base(); } |
| 17221 | public: |
| 17222 | shrL_rReg_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17223 | virtual uint size_of() const { return sizeof(shrL_rReg_1Node); } |
| 17224 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17225 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17226 | static const Pipeline *pipeline_class(); |
| 17227 | virtual const Pipeline *pipeline() const; |
| 17228 | #ifndef PRODUCT |
| 17229 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17230 | virtual const char *Name() const { return "shrL_rReg_1";} |
| 17231 | #endif |
| 17232 | }; |
| 17233 | |
| 17234 | class shrL_mem_1Node : public MachTypeNode { |
| 17235 | private: |
| 17236 | MachOper *_opnd_array[4]; |
| 17237 | public: |
| 17238 | MachOper *opnd_array(uint operand_index) const { |
| 17239 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17240 | return _opnd_array[operand_index]; |
| 17241 | } |
| 17242 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17243 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17244 | _opnd_array[operand_index] = operand; |
| 17245 | } |
| 17246 | private: |
| 17247 | virtual const RegMask &out_RegMask() const; |
| 17248 | virtual uint rule() const { return shrL_mem_1_rule; } |
| 17249 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17250 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17251 | virtual int reloc() const; |
| 17252 | virtual uint oper_input_base() const { return 2; } |
| 17253 | public: |
| 17254 | shrL_mem_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17255 | virtual uint size_of() const { return sizeof(shrL_mem_1Node); } |
| 17256 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17257 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17258 | static const Pipeline *pipeline_class(); |
| 17259 | virtual const Pipeline *pipeline() const; |
| 17260 | virtual const MachOper *memory_operand() const; |
| 17261 | #ifndef PRODUCT |
| 17262 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17263 | virtual const char *Name() const { return "shrL_mem_1";} |
| 17264 | #endif |
| 17265 | }; |
| 17266 | |
| 17267 | class shrL_rReg_immNode : public MachNode { |
| 17268 | private: |
| 17269 | MachOper *_opnd_array[3]; |
| 17270 | public: |
| 17271 | MachOper *opnd_array(uint operand_index) const { |
| 17272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17273 | return _opnd_array[operand_index]; |
| 17274 | } |
| 17275 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17276 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17277 | _opnd_array[operand_index] = operand; |
| 17278 | } |
| 17279 | private: |
| 17280 | virtual const RegMask &out_RegMask() const; |
| 17281 | virtual uint rule() const { return shrL_rReg_imm_rule; } |
| 17282 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17283 | virtual int ideal_Opcode() const { return Op_URShiftL; } |
| 17284 | virtual uint two_adr() const { return oper_input_base(); } |
| 17285 | public: |
| 17286 | shrL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17287 | virtual uint size_of() const { return sizeof(shrL_rReg_immNode); } |
| 17288 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17289 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17290 | static const Pipeline *pipeline_class(); |
| 17291 | virtual const Pipeline *pipeline() const; |
| 17292 | #ifndef PRODUCT |
| 17293 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17294 | virtual const char *Name() const { return "shrL_rReg_imm";} |
| 17295 | #endif |
| 17296 | }; |
| 17297 | |
| 17298 | class shrL_mem_immNode : public MachTypeNode { |
| 17299 | private: |
| 17300 | MachOper *_opnd_array[4]; |
| 17301 | public: |
| 17302 | MachOper *opnd_array(uint operand_index) const { |
| 17303 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17304 | return _opnd_array[operand_index]; |
| 17305 | } |
| 17306 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17307 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17308 | _opnd_array[operand_index] = operand; |
| 17309 | } |
| 17310 | private: |
| 17311 | virtual const RegMask &out_RegMask() const; |
| 17312 | virtual uint rule() const { return shrL_mem_imm_rule; } |
| 17313 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17314 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17315 | virtual int reloc() const; |
| 17316 | virtual uint oper_input_base() const { return 2; } |
| 17317 | public: |
| 17318 | shrL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17319 | virtual uint size_of() const { return sizeof(shrL_mem_immNode); } |
| 17320 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17321 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17322 | static const Pipeline *pipeline_class(); |
| 17323 | virtual const Pipeline *pipeline() const; |
| 17324 | virtual const MachOper *memory_operand() const; |
| 17325 | #ifndef PRODUCT |
| 17326 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17327 | virtual const char *Name() const { return "shrL_mem_imm";} |
| 17328 | #endif |
| 17329 | }; |
| 17330 | |
| 17331 | class shrL_rReg_CLNode : public MachNode { |
| 17332 | private: |
| 17333 | MachOper *_opnd_array[3]; |
| 17334 | public: |
| 17335 | MachOper *opnd_array(uint operand_index) const { |
| 17336 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17337 | return _opnd_array[operand_index]; |
| 17338 | } |
| 17339 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17340 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17341 | _opnd_array[operand_index] = operand; |
| 17342 | } |
| 17343 | private: |
| 17344 | virtual const RegMask &out_RegMask() const; |
| 17345 | virtual uint rule() const { return shrL_rReg_CL_rule; } |
| 17346 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17347 | virtual int ideal_Opcode() const { return Op_URShiftL; } |
| 17348 | virtual uint two_adr() const { return oper_input_base(); } |
| 17349 | public: |
| 17350 | shrL_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17351 | virtual uint size_of() const { return sizeof(shrL_rReg_CLNode); } |
| 17352 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17353 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17354 | static const Pipeline *pipeline_class(); |
| 17355 | virtual const Pipeline *pipeline() const; |
| 17356 | #ifndef PRODUCT |
| 17357 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17358 | virtual const char *Name() const { return "shrL_rReg_CL";} |
| 17359 | #endif |
| 17360 | }; |
| 17361 | |
| 17362 | class shrL_mem_CLNode : public MachTypeNode { |
| 17363 | private: |
| 17364 | MachOper *_opnd_array[4]; |
| 17365 | public: |
| 17366 | MachOper *opnd_array(uint operand_index) const { |
| 17367 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17368 | return _opnd_array[operand_index]; |
| 17369 | } |
| 17370 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17371 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17372 | _opnd_array[operand_index] = operand; |
| 17373 | } |
| 17374 | private: |
| 17375 | virtual const RegMask &out_RegMask() const; |
| 17376 | virtual uint rule() const { return shrL_mem_CL_rule; } |
| 17377 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17378 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 17379 | virtual int reloc() const; |
| 17380 | virtual uint oper_input_base() const { return 2; } |
| 17381 | public: |
| 17382 | shrL_mem_CLNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 17383 | virtual uint size_of() const { return sizeof(shrL_mem_CLNode); } |
| 17384 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17385 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17386 | static const Pipeline *pipeline_class(); |
| 17387 | virtual const Pipeline *pipeline() const; |
| 17388 | virtual const MachOper *memory_operand() const; |
| 17389 | #ifndef PRODUCT |
| 17390 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17391 | virtual const char *Name() const { return "shrL_mem_CL";} |
| 17392 | #endif |
| 17393 | }; |
| 17394 | |
| 17395 | class i2bNode : public MachNode { |
| 17396 | private: |
| 17397 | MachOper *_opnd_array[4]; |
| 17398 | public: |
| 17399 | MachOper *opnd_array(uint operand_index) const { |
| 17400 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17401 | return _opnd_array[operand_index]; |
| 17402 | } |
| 17403 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17404 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17405 | _opnd_array[operand_index] = operand; |
| 17406 | } |
| 17407 | private: |
| 17408 | const RegMask *_cisc_RegMask; |
| 17409 | virtual const RegMask &out_RegMask() const; |
| 17410 | virtual uint rule() const { return i2b_rule; } |
| 17411 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17412 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 17413 | virtual int cisc_operand() const { return 1; } |
| 17414 | virtual MachNode *cisc_version(int offset); |
| 17415 | virtual void use_cisc_RegMask(); |
| 17416 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 17417 | public: |
| 17418 | i2bNode() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 17419 | virtual uint size_of() const { return sizeof(i2bNode); } |
| 17420 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17421 | static const Pipeline *pipeline_class(); |
| 17422 | virtual const Pipeline *pipeline() const; |
| 17423 | #ifndef PRODUCT |
| 17424 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17425 | virtual const char *Name() const { return "i2b";} |
| 17426 | #endif |
| 17427 | }; |
| 17428 | |
| 17429 | class i2sNode : public MachNode { |
| 17430 | private: |
| 17431 | MachOper *_opnd_array[4]; |
| 17432 | public: |
| 17433 | MachOper *opnd_array(uint operand_index) const { |
| 17434 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17435 | return _opnd_array[operand_index]; |
| 17436 | } |
| 17437 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17438 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17439 | _opnd_array[operand_index] = operand; |
| 17440 | } |
| 17441 | private: |
| 17442 | const RegMask *_cisc_RegMask; |
| 17443 | virtual const RegMask &out_RegMask() const; |
| 17444 | virtual uint rule() const { return i2s_rule; } |
| 17445 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17446 | virtual int ideal_Opcode() const { return Op_RShiftI; } |
| 17447 | virtual int cisc_operand() const { return 1; } |
| 17448 | virtual MachNode *cisc_version(int offset); |
| 17449 | virtual void use_cisc_RegMask(); |
| 17450 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 17451 | public: |
| 17452 | i2sNode() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 17453 | virtual uint size_of() const { return sizeof(i2sNode); } |
| 17454 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17455 | static const Pipeline *pipeline_class(); |
| 17456 | virtual const Pipeline *pipeline() const; |
| 17457 | #ifndef PRODUCT |
| 17458 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17459 | virtual const char *Name() const { return "i2s";} |
| 17460 | #endif |
| 17461 | }; |
| 17462 | |
| 17463 | class rolI_rReg_imm1Node : public MachNode { |
| 17464 | private: |
| 17465 | MachOper *_opnd_array[2]; |
| 17466 | public: |
| 17467 | MachOper *opnd_array(uint operand_index) const { |
| 17468 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17469 | return _opnd_array[operand_index]; |
| 17470 | } |
| 17471 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17472 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17473 | _opnd_array[operand_index] = operand; |
| 17474 | } |
| 17475 | private: |
| 17476 | virtual const RegMask &out_RegMask() const; |
| 17477 | virtual uint rule() const { return rolI_rReg_imm1_rule; } |
| 17478 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17479 | virtual uint two_adr() const { return oper_input_base(); } |
| 17480 | public: |
| 17481 | rolI_rReg_imm1Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 17482 | virtual uint size_of() const { return sizeof(rolI_rReg_imm1Node); } |
| 17483 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17484 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17485 | static const Pipeline *pipeline_class(); |
| 17486 | virtual const Pipeline *pipeline() const; |
| 17487 | #ifndef PRODUCT |
| 17488 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17489 | virtual const char *Name() const { return "rolI_rReg_imm1";} |
| 17490 | #endif |
| 17491 | }; |
| 17492 | |
| 17493 | class rolI_rReg_imm8Node : public MachNode { |
| 17494 | private: |
| 17495 | MachOper *_opnd_array[3]; |
| 17496 | public: |
| 17497 | MachOper *opnd_array(uint operand_index) const { |
| 17498 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17499 | return _opnd_array[operand_index]; |
| 17500 | } |
| 17501 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17502 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17503 | _opnd_array[operand_index] = operand; |
| 17504 | } |
| 17505 | private: |
| 17506 | virtual const RegMask &out_RegMask() const; |
| 17507 | virtual uint rule() const { return rolI_rReg_imm8_rule; } |
| 17508 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17509 | virtual uint two_adr() const { return oper_input_base(); } |
| 17510 | public: |
| 17511 | rolI_rReg_imm8Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17512 | virtual uint size_of() const { return sizeof(rolI_rReg_imm8Node); } |
| 17513 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17514 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17515 | static const Pipeline *pipeline_class(); |
| 17516 | virtual const Pipeline *pipeline() const; |
| 17517 | #ifndef PRODUCT |
| 17518 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17519 | virtual const char *Name() const { return "rolI_rReg_imm8";} |
| 17520 | #endif |
| 17521 | }; |
| 17522 | |
| 17523 | class rolI_rReg_CLNode : public MachNode { |
| 17524 | private: |
| 17525 | MachOper *_opnd_array[3]; |
| 17526 | public: |
| 17527 | MachOper *opnd_array(uint operand_index) const { |
| 17528 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17529 | return _opnd_array[operand_index]; |
| 17530 | } |
| 17531 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17532 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17533 | _opnd_array[operand_index] = operand; |
| 17534 | } |
| 17535 | private: |
| 17536 | virtual const RegMask &out_RegMask() const; |
| 17537 | virtual uint rule() const { return rolI_rReg_CL_rule; } |
| 17538 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17539 | virtual uint two_adr() const { return oper_input_base(); } |
| 17540 | public: |
| 17541 | rolI_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17542 | virtual uint size_of() const { return sizeof(rolI_rReg_CLNode); } |
| 17543 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17544 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17545 | static const Pipeline *pipeline_class(); |
| 17546 | virtual const Pipeline *pipeline() const; |
| 17547 | #ifndef PRODUCT |
| 17548 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17549 | virtual const char *Name() const { return "rolI_rReg_CL";} |
| 17550 | #endif |
| 17551 | }; |
| 17552 | |
| 17553 | class rolI_rReg_i1Node : public MachNode { |
| 17554 | private: |
| 17555 | MachOper *_opnd_array[5]; |
| 17556 | public: |
| 17557 | MachOper *opnd_array(uint operand_index) const { |
| 17558 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17559 | return _opnd_array[operand_index]; |
| 17560 | } |
| 17561 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17562 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17563 | _opnd_array[operand_index] = operand; |
| 17564 | } |
| 17565 | private: |
| 17566 | virtual const RegMask &out_RegMask() const; |
| 17567 | virtual uint rule() const { return rolI_rReg_i1_rule; } |
| 17568 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17569 | virtual uint two_adr() const { return oper_input_base(); } |
| 17570 | public: |
| 17571 | rolI_rReg_i1Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17572 | virtual uint size_of() const { return sizeof(rolI_rReg_i1Node); } |
| 17573 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17574 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17575 | #ifndef PRODUCT |
| 17576 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17577 | virtual const char *Name() const { return "rolI_rReg_i1";} |
| 17578 | #endif |
| 17579 | }; |
| 17580 | |
| 17581 | class rolI_rReg_i1_0Node : public MachNode { |
| 17582 | private: |
| 17583 | MachOper *_opnd_array[5]; |
| 17584 | public: |
| 17585 | MachOper *opnd_array(uint operand_index) const { |
| 17586 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17587 | return _opnd_array[operand_index]; |
| 17588 | } |
| 17589 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17590 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17591 | _opnd_array[operand_index] = operand; |
| 17592 | } |
| 17593 | private: |
| 17594 | virtual const RegMask &out_RegMask() const; |
| 17595 | virtual uint rule() const { return rolI_rReg_i1_0_rule; } |
| 17596 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17597 | virtual uint two_adr() const { return oper_input_base(); } |
| 17598 | public: |
| 17599 | rolI_rReg_i1_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17600 | virtual uint size_of() const { return sizeof(rolI_rReg_i1_0Node); } |
| 17601 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17602 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17603 | #ifndef PRODUCT |
| 17604 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17605 | virtual const char *Name() const { return "rolI_rReg_i1_0";} |
| 17606 | #endif |
| 17607 | }; |
| 17608 | |
| 17609 | class rolI_rReg_i8Node : public MachNode { |
| 17610 | private: |
| 17611 | MachOper *_opnd_array[5]; |
| 17612 | public: |
| 17613 | MachOper *opnd_array(uint operand_index) const { |
| 17614 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17615 | return _opnd_array[operand_index]; |
| 17616 | } |
| 17617 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17619 | _opnd_array[operand_index] = operand; |
| 17620 | } |
| 17621 | private: |
| 17622 | virtual const RegMask &out_RegMask() const; |
| 17623 | virtual uint rule() const { return rolI_rReg_i8_rule; } |
| 17624 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17625 | virtual uint two_adr() const { return oper_input_base(); } |
| 17626 | public: |
| 17627 | rolI_rReg_i8Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17628 | virtual uint size_of() const { return sizeof(rolI_rReg_i8Node); } |
| 17629 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17630 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17631 | #ifndef PRODUCT |
| 17632 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17633 | virtual const char *Name() const { return "rolI_rReg_i8";} |
| 17634 | #endif |
| 17635 | }; |
| 17636 | |
| 17637 | class rolI_rReg_i8_0Node : public MachNode { |
| 17638 | private: |
| 17639 | MachOper *_opnd_array[5]; |
| 17640 | public: |
| 17641 | MachOper *opnd_array(uint operand_index) const { |
| 17642 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17643 | return _opnd_array[operand_index]; |
| 17644 | } |
| 17645 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17646 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17647 | _opnd_array[operand_index] = operand; |
| 17648 | } |
| 17649 | private: |
| 17650 | virtual const RegMask &out_RegMask() const; |
| 17651 | virtual uint rule() const { return rolI_rReg_i8_0_rule; } |
| 17652 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17653 | virtual uint two_adr() const { return oper_input_base(); } |
| 17654 | public: |
| 17655 | rolI_rReg_i8_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17656 | virtual uint size_of() const { return sizeof(rolI_rReg_i8_0Node); } |
| 17657 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17658 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17659 | #ifndef PRODUCT |
| 17660 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17661 | virtual const char *Name() const { return "rolI_rReg_i8_0";} |
| 17662 | #endif |
| 17663 | }; |
| 17664 | |
| 17665 | class rolI_rReg_Var_C0Node : public MachNode { |
| 17666 | private: |
| 17667 | MachOper *_opnd_array[6]; |
| 17668 | public: |
| 17669 | MachOper *opnd_array(uint operand_index) const { |
| 17670 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17671 | return _opnd_array[operand_index]; |
| 17672 | } |
| 17673 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17674 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17675 | _opnd_array[operand_index] = operand; |
| 17676 | } |
| 17677 | private: |
| 17678 | virtual const RegMask &out_RegMask() const; |
| 17679 | virtual uint rule() const { return rolI_rReg_Var_C0_rule; } |
| 17680 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17681 | virtual uint two_adr() const { return oper_input_base(); } |
| 17682 | public: |
| 17683 | rolI_rReg_Var_C0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 17684 | virtual uint size_of() const { return sizeof(rolI_rReg_Var_C0Node); } |
| 17685 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17686 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17687 | #ifndef PRODUCT |
| 17688 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17689 | virtual const char *Name() const { return "rolI_rReg_Var_C0";} |
| 17690 | #endif |
| 17691 | }; |
| 17692 | |
| 17693 | class rolI_rReg_Var_C0_0Node : public MachNode { |
| 17694 | private: |
| 17695 | MachOper *_opnd_array[6]; |
| 17696 | public: |
| 17697 | MachOper *opnd_array(uint operand_index) const { |
| 17698 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17699 | return _opnd_array[operand_index]; |
| 17700 | } |
| 17701 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17702 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17703 | _opnd_array[operand_index] = operand; |
| 17704 | } |
| 17705 | private: |
| 17706 | virtual const RegMask &out_RegMask() const; |
| 17707 | virtual uint rule() const { return rolI_rReg_Var_C0_0_rule; } |
| 17708 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17709 | virtual uint two_adr() const { return oper_input_base(); } |
| 17710 | public: |
| 17711 | rolI_rReg_Var_C0_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 17712 | virtual uint size_of() const { return sizeof(rolI_rReg_Var_C0_0Node); } |
| 17713 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17714 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17715 | #ifndef PRODUCT |
| 17716 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17717 | virtual const char *Name() const { return "rolI_rReg_Var_C0_0";} |
| 17718 | #endif |
| 17719 | }; |
| 17720 | |
| 17721 | class rolI_rReg_Var_C32Node : public MachNode { |
| 17722 | private: |
| 17723 | MachOper *_opnd_array[6]; |
| 17724 | public: |
| 17725 | MachOper *opnd_array(uint operand_index) const { |
| 17726 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17727 | return _opnd_array[operand_index]; |
| 17728 | } |
| 17729 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17730 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17731 | _opnd_array[operand_index] = operand; |
| 17732 | } |
| 17733 | private: |
| 17734 | virtual const RegMask &out_RegMask() const; |
| 17735 | virtual uint rule() const { return rolI_rReg_Var_C32_rule; } |
| 17736 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17737 | virtual uint two_adr() const { return oper_input_base(); } |
| 17738 | public: |
| 17739 | rolI_rReg_Var_C32Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 17740 | virtual uint size_of() const { return sizeof(rolI_rReg_Var_C32Node); } |
| 17741 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17742 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17743 | #ifndef PRODUCT |
| 17744 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17745 | virtual const char *Name() const { return "rolI_rReg_Var_C32";} |
| 17746 | #endif |
| 17747 | }; |
| 17748 | |
| 17749 | class rolI_rReg_Var_C32_0Node : public MachNode { |
| 17750 | private: |
| 17751 | MachOper *_opnd_array[6]; |
| 17752 | public: |
| 17753 | MachOper *opnd_array(uint operand_index) const { |
| 17754 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17755 | return _opnd_array[operand_index]; |
| 17756 | } |
| 17757 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17758 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17759 | _opnd_array[operand_index] = operand; |
| 17760 | } |
| 17761 | private: |
| 17762 | virtual const RegMask &out_RegMask() const; |
| 17763 | virtual uint rule() const { return rolI_rReg_Var_C32_0_rule; } |
| 17764 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17765 | virtual uint two_adr() const { return oper_input_base(); } |
| 17766 | public: |
| 17767 | rolI_rReg_Var_C32_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 17768 | virtual uint size_of() const { return sizeof(rolI_rReg_Var_C32_0Node); } |
| 17769 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17770 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17771 | #ifndef PRODUCT |
| 17772 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17773 | virtual const char *Name() const { return "rolI_rReg_Var_C32_0";} |
| 17774 | #endif |
| 17775 | }; |
| 17776 | |
| 17777 | class rorI_rReg_imm1Node : public MachNode { |
| 17778 | private: |
| 17779 | MachOper *_opnd_array[2]; |
| 17780 | public: |
| 17781 | MachOper *opnd_array(uint operand_index) const { |
| 17782 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17783 | return _opnd_array[operand_index]; |
| 17784 | } |
| 17785 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17786 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17787 | _opnd_array[operand_index] = operand; |
| 17788 | } |
| 17789 | private: |
| 17790 | virtual const RegMask &out_RegMask() const; |
| 17791 | virtual uint rule() const { return rorI_rReg_imm1_rule; } |
| 17792 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17793 | virtual uint two_adr() const { return oper_input_base(); } |
| 17794 | public: |
| 17795 | rorI_rReg_imm1Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 17796 | virtual uint size_of() const { return sizeof(rorI_rReg_imm1Node); } |
| 17797 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17798 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17799 | static const Pipeline *pipeline_class(); |
| 17800 | virtual const Pipeline *pipeline() const; |
| 17801 | #ifndef PRODUCT |
| 17802 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17803 | virtual const char *Name() const { return "rorI_rReg_imm1";} |
| 17804 | #endif |
| 17805 | }; |
| 17806 | |
| 17807 | class rorI_rReg_imm8Node : public MachNode { |
| 17808 | private: |
| 17809 | MachOper *_opnd_array[3]; |
| 17810 | public: |
| 17811 | MachOper *opnd_array(uint operand_index) const { |
| 17812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17813 | return _opnd_array[operand_index]; |
| 17814 | } |
| 17815 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17816 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17817 | _opnd_array[operand_index] = operand; |
| 17818 | } |
| 17819 | private: |
| 17820 | virtual const RegMask &out_RegMask() const; |
| 17821 | virtual uint rule() const { return rorI_rReg_imm8_rule; } |
| 17822 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17823 | virtual uint two_adr() const { return oper_input_base(); } |
| 17824 | public: |
| 17825 | rorI_rReg_imm8Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17826 | virtual uint size_of() const { return sizeof(rorI_rReg_imm8Node); } |
| 17827 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17828 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17829 | static const Pipeline *pipeline_class(); |
| 17830 | virtual const Pipeline *pipeline() const; |
| 17831 | #ifndef PRODUCT |
| 17832 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17833 | virtual const char *Name() const { return "rorI_rReg_imm8";} |
| 17834 | #endif |
| 17835 | }; |
| 17836 | |
| 17837 | class rorI_rReg_CLNode : public MachNode { |
| 17838 | private: |
| 17839 | MachOper *_opnd_array[3]; |
| 17840 | public: |
| 17841 | MachOper *opnd_array(uint operand_index) const { |
| 17842 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17843 | return _opnd_array[operand_index]; |
| 17844 | } |
| 17845 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17846 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17847 | _opnd_array[operand_index] = operand; |
| 17848 | } |
| 17849 | private: |
| 17850 | virtual const RegMask &out_RegMask() const; |
| 17851 | virtual uint rule() const { return rorI_rReg_CL_rule; } |
| 17852 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 17853 | virtual uint two_adr() const { return oper_input_base(); } |
| 17854 | public: |
| 17855 | rorI_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 17856 | virtual uint size_of() const { return sizeof(rorI_rReg_CLNode); } |
| 17857 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17858 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17859 | static const Pipeline *pipeline_class(); |
| 17860 | virtual const Pipeline *pipeline() const; |
| 17861 | #ifndef PRODUCT |
| 17862 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17863 | virtual const char *Name() const { return "rorI_rReg_CL";} |
| 17864 | #endif |
| 17865 | }; |
| 17866 | |
| 17867 | class rorI_rReg_i1Node : public MachNode { |
| 17868 | private: |
| 17869 | MachOper *_opnd_array[5]; |
| 17870 | public: |
| 17871 | MachOper *opnd_array(uint operand_index) const { |
| 17872 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17873 | return _opnd_array[operand_index]; |
| 17874 | } |
| 17875 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17876 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17877 | _opnd_array[operand_index] = operand; |
| 17878 | } |
| 17879 | private: |
| 17880 | virtual const RegMask &out_RegMask() const; |
| 17881 | virtual uint rule() const { return rorI_rReg_i1_rule; } |
| 17882 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17883 | virtual uint two_adr() const { return oper_input_base(); } |
| 17884 | public: |
| 17885 | rorI_rReg_i1Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17886 | virtual uint size_of() const { return sizeof(rorI_rReg_i1Node); } |
| 17887 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17888 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17889 | #ifndef PRODUCT |
| 17890 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17891 | virtual const char *Name() const { return "rorI_rReg_i1";} |
| 17892 | #endif |
| 17893 | }; |
| 17894 | |
| 17895 | class rorI_rReg_i1_0Node : public MachNode { |
| 17896 | private: |
| 17897 | MachOper *_opnd_array[5]; |
| 17898 | public: |
| 17899 | MachOper *opnd_array(uint operand_index) const { |
| 17900 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17901 | return _opnd_array[operand_index]; |
| 17902 | } |
| 17903 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17904 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17905 | _opnd_array[operand_index] = operand; |
| 17906 | } |
| 17907 | private: |
| 17908 | virtual const RegMask &out_RegMask() const; |
| 17909 | virtual uint rule() const { return rorI_rReg_i1_0_rule; } |
| 17910 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17911 | virtual uint two_adr() const { return oper_input_base(); } |
| 17912 | public: |
| 17913 | rorI_rReg_i1_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17914 | virtual uint size_of() const { return sizeof(rorI_rReg_i1_0Node); } |
| 17915 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17916 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17917 | #ifndef PRODUCT |
| 17918 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17919 | virtual const char *Name() const { return "rorI_rReg_i1_0";} |
| 17920 | #endif |
| 17921 | }; |
| 17922 | |
| 17923 | class rorI_rReg_i8Node : public MachNode { |
| 17924 | private: |
| 17925 | MachOper *_opnd_array[5]; |
| 17926 | public: |
| 17927 | MachOper *opnd_array(uint operand_index) const { |
| 17928 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17929 | return _opnd_array[operand_index]; |
| 17930 | } |
| 17931 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17932 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17933 | _opnd_array[operand_index] = operand; |
| 17934 | } |
| 17935 | private: |
| 17936 | virtual const RegMask &out_RegMask() const; |
| 17937 | virtual uint rule() const { return rorI_rReg_i8_rule; } |
| 17938 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17939 | virtual uint two_adr() const { return oper_input_base(); } |
| 17940 | public: |
| 17941 | rorI_rReg_i8Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17942 | virtual uint size_of() const { return sizeof(rorI_rReg_i8Node); } |
| 17943 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17944 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17945 | #ifndef PRODUCT |
| 17946 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17947 | virtual const char *Name() const { return "rorI_rReg_i8";} |
| 17948 | #endif |
| 17949 | }; |
| 17950 | |
| 17951 | class rorI_rReg_i8_0Node : public MachNode { |
| 17952 | private: |
| 17953 | MachOper *_opnd_array[5]; |
| 17954 | public: |
| 17955 | MachOper *opnd_array(uint operand_index) const { |
| 17956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17957 | return _opnd_array[operand_index]; |
| 17958 | } |
| 17959 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17960 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17961 | _opnd_array[operand_index] = operand; |
| 17962 | } |
| 17963 | private: |
| 17964 | virtual const RegMask &out_RegMask() const; |
| 17965 | virtual uint rule() const { return rorI_rReg_i8_0_rule; } |
| 17966 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17967 | virtual uint two_adr() const { return oper_input_base(); } |
| 17968 | public: |
| 17969 | rorI_rReg_i8_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 17970 | virtual uint size_of() const { return sizeof(rorI_rReg_i8_0Node); } |
| 17971 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 17972 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 17973 | #ifndef PRODUCT |
| 17974 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 17975 | virtual const char *Name() const { return "rorI_rReg_i8_0";} |
| 17976 | #endif |
| 17977 | }; |
| 17978 | |
| 17979 | class rorI_rReg_Var_C0Node : public MachNode { |
| 17980 | private: |
| 17981 | MachOper *_opnd_array[6]; |
| 17982 | public: |
| 17983 | MachOper *opnd_array(uint operand_index) const { |
| 17984 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17985 | return _opnd_array[operand_index]; |
| 17986 | } |
| 17987 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 17988 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 17989 | _opnd_array[operand_index] = operand; |
| 17990 | } |
| 17991 | private: |
| 17992 | virtual const RegMask &out_RegMask() const; |
| 17993 | virtual uint rule() const { return rorI_rReg_Var_C0_rule; } |
| 17994 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 17995 | virtual uint two_adr() const { return oper_input_base(); } |
| 17996 | public: |
| 17997 | rorI_rReg_Var_C0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 17998 | virtual uint size_of() const { return sizeof(rorI_rReg_Var_C0Node); } |
| 17999 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18000 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18001 | #ifndef PRODUCT |
| 18002 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18003 | virtual const char *Name() const { return "rorI_rReg_Var_C0";} |
| 18004 | #endif |
| 18005 | }; |
| 18006 | |
| 18007 | class rorI_rReg_Var_C0_0Node : public MachNode { |
| 18008 | private: |
| 18009 | MachOper *_opnd_array[6]; |
| 18010 | public: |
| 18011 | MachOper *opnd_array(uint operand_index) const { |
| 18012 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18013 | return _opnd_array[operand_index]; |
| 18014 | } |
| 18015 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18017 | _opnd_array[operand_index] = operand; |
| 18018 | } |
| 18019 | private: |
| 18020 | virtual const RegMask &out_RegMask() const; |
| 18021 | virtual uint rule() const { return rorI_rReg_Var_C0_0_rule; } |
| 18022 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 18023 | virtual uint two_adr() const { return oper_input_base(); } |
| 18024 | public: |
| 18025 | rorI_rReg_Var_C0_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18026 | virtual uint size_of() const { return sizeof(rorI_rReg_Var_C0_0Node); } |
| 18027 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18028 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18029 | #ifndef PRODUCT |
| 18030 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18031 | virtual const char *Name() const { return "rorI_rReg_Var_C0_0";} |
| 18032 | #endif |
| 18033 | }; |
| 18034 | |
| 18035 | class rorI_rReg_Var_C32Node : public MachNode { |
| 18036 | private: |
| 18037 | MachOper *_opnd_array[6]; |
| 18038 | public: |
| 18039 | MachOper *opnd_array(uint operand_index) const { |
| 18040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18041 | return _opnd_array[operand_index]; |
| 18042 | } |
| 18043 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18044 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18045 | _opnd_array[operand_index] = operand; |
| 18046 | } |
| 18047 | private: |
| 18048 | virtual const RegMask &out_RegMask() const; |
| 18049 | virtual uint rule() const { return rorI_rReg_Var_C32_rule; } |
| 18050 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 18051 | virtual uint two_adr() const { return oper_input_base(); } |
| 18052 | public: |
| 18053 | rorI_rReg_Var_C32Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18054 | virtual uint size_of() const { return sizeof(rorI_rReg_Var_C32Node); } |
| 18055 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18056 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18057 | #ifndef PRODUCT |
| 18058 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18059 | virtual const char *Name() const { return "rorI_rReg_Var_C32";} |
| 18060 | #endif |
| 18061 | }; |
| 18062 | |
| 18063 | class rorI_rReg_Var_C32_0Node : public MachNode { |
| 18064 | private: |
| 18065 | MachOper *_opnd_array[6]; |
| 18066 | public: |
| 18067 | MachOper *opnd_array(uint operand_index) const { |
| 18068 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18069 | return _opnd_array[operand_index]; |
| 18070 | } |
| 18071 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18072 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18073 | _opnd_array[operand_index] = operand; |
| 18074 | } |
| 18075 | private: |
| 18076 | virtual const RegMask &out_RegMask() const; |
| 18077 | virtual uint rule() const { return rorI_rReg_Var_C32_0_rule; } |
| 18078 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 18079 | virtual uint two_adr() const { return oper_input_base(); } |
| 18080 | public: |
| 18081 | rorI_rReg_Var_C32_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18082 | virtual uint size_of() const { return sizeof(rorI_rReg_Var_C32_0Node); } |
| 18083 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18084 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18085 | #ifndef PRODUCT |
| 18086 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18087 | virtual const char *Name() const { return "rorI_rReg_Var_C32_0";} |
| 18088 | #endif |
| 18089 | }; |
| 18090 | |
| 18091 | class rolL_rReg_imm1Node : public MachNode { |
| 18092 | private: |
| 18093 | MachOper *_opnd_array[2]; |
| 18094 | public: |
| 18095 | MachOper *opnd_array(uint operand_index) const { |
| 18096 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18097 | return _opnd_array[operand_index]; |
| 18098 | } |
| 18099 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18100 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18101 | _opnd_array[operand_index] = operand; |
| 18102 | } |
| 18103 | private: |
| 18104 | virtual const RegMask &out_RegMask() const; |
| 18105 | virtual uint rule() const { return rolL_rReg_imm1_rule; } |
| 18106 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18107 | virtual uint two_adr() const { return oper_input_base(); } |
| 18108 | public: |
| 18109 | rolL_rReg_imm1Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 18110 | virtual uint size_of() const { return sizeof(rolL_rReg_imm1Node); } |
| 18111 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18112 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18113 | static const Pipeline *pipeline_class(); |
| 18114 | virtual const Pipeline *pipeline() const; |
| 18115 | #ifndef PRODUCT |
| 18116 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18117 | virtual const char *Name() const { return "rolL_rReg_imm1";} |
| 18118 | #endif |
| 18119 | }; |
| 18120 | |
| 18121 | class rolL_rReg_imm8Node : public MachNode { |
| 18122 | private: |
| 18123 | MachOper *_opnd_array[3]; |
| 18124 | public: |
| 18125 | MachOper *opnd_array(uint operand_index) const { |
| 18126 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18127 | return _opnd_array[operand_index]; |
| 18128 | } |
| 18129 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18130 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18131 | _opnd_array[operand_index] = operand; |
| 18132 | } |
| 18133 | private: |
| 18134 | virtual const RegMask &out_RegMask() const; |
| 18135 | virtual uint rule() const { return rolL_rReg_imm8_rule; } |
| 18136 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18137 | virtual uint two_adr() const { return oper_input_base(); } |
| 18138 | public: |
| 18139 | rolL_rReg_imm8Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18140 | virtual uint size_of() const { return sizeof(rolL_rReg_imm8Node); } |
| 18141 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18142 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18143 | static const Pipeline *pipeline_class(); |
| 18144 | virtual const Pipeline *pipeline() const; |
| 18145 | #ifndef PRODUCT |
| 18146 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18147 | virtual const char *Name() const { return "rolL_rReg_imm8";} |
| 18148 | #endif |
| 18149 | }; |
| 18150 | |
| 18151 | class rolL_rReg_CLNode : public MachNode { |
| 18152 | private: |
| 18153 | MachOper *_opnd_array[3]; |
| 18154 | public: |
| 18155 | MachOper *opnd_array(uint operand_index) const { |
| 18156 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18157 | return _opnd_array[operand_index]; |
| 18158 | } |
| 18159 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18160 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18161 | _opnd_array[operand_index] = operand; |
| 18162 | } |
| 18163 | private: |
| 18164 | virtual const RegMask &out_RegMask() const; |
| 18165 | virtual uint rule() const { return rolL_rReg_CL_rule; } |
| 18166 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18167 | virtual uint two_adr() const { return oper_input_base(); } |
| 18168 | public: |
| 18169 | rolL_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18170 | virtual uint size_of() const { return sizeof(rolL_rReg_CLNode); } |
| 18171 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18172 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18173 | static const Pipeline *pipeline_class(); |
| 18174 | virtual const Pipeline *pipeline() const; |
| 18175 | #ifndef PRODUCT |
| 18176 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18177 | virtual const char *Name() const { return "rolL_rReg_CL";} |
| 18178 | #endif |
| 18179 | }; |
| 18180 | |
| 18181 | class rolL_rReg_i1Node : public MachNode { |
| 18182 | private: |
| 18183 | MachOper *_opnd_array[5]; |
| 18184 | public: |
| 18185 | MachOper *opnd_array(uint operand_index) const { |
| 18186 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18187 | return _opnd_array[operand_index]; |
| 18188 | } |
| 18189 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18190 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18191 | _opnd_array[operand_index] = operand; |
| 18192 | } |
| 18193 | private: |
| 18194 | virtual const RegMask &out_RegMask() const; |
| 18195 | virtual uint rule() const { return rolL_rReg_i1_rule; } |
| 18196 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18197 | virtual uint two_adr() const { return oper_input_base(); } |
| 18198 | public: |
| 18199 | rolL_rReg_i1Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18200 | virtual uint size_of() const { return sizeof(rolL_rReg_i1Node); } |
| 18201 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18202 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18203 | #ifndef PRODUCT |
| 18204 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18205 | virtual const char *Name() const { return "rolL_rReg_i1";} |
| 18206 | #endif |
| 18207 | }; |
| 18208 | |
| 18209 | class rolL_rReg_i1_0Node : public MachNode { |
| 18210 | private: |
| 18211 | MachOper *_opnd_array[5]; |
| 18212 | public: |
| 18213 | MachOper *opnd_array(uint operand_index) const { |
| 18214 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18215 | return _opnd_array[operand_index]; |
| 18216 | } |
| 18217 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18218 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18219 | _opnd_array[operand_index] = operand; |
| 18220 | } |
| 18221 | private: |
| 18222 | virtual const RegMask &out_RegMask() const; |
| 18223 | virtual uint rule() const { return rolL_rReg_i1_0_rule; } |
| 18224 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18225 | virtual uint two_adr() const { return oper_input_base(); } |
| 18226 | public: |
| 18227 | rolL_rReg_i1_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18228 | virtual uint size_of() const { return sizeof(rolL_rReg_i1_0Node); } |
| 18229 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18230 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18231 | #ifndef PRODUCT |
| 18232 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18233 | virtual const char *Name() const { return "rolL_rReg_i1_0";} |
| 18234 | #endif |
| 18235 | }; |
| 18236 | |
| 18237 | class rolL_rReg_i8Node : public MachNode { |
| 18238 | private: |
| 18239 | MachOper *_opnd_array[5]; |
| 18240 | public: |
| 18241 | MachOper *opnd_array(uint operand_index) const { |
| 18242 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18243 | return _opnd_array[operand_index]; |
| 18244 | } |
| 18245 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18246 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18247 | _opnd_array[operand_index] = operand; |
| 18248 | } |
| 18249 | private: |
| 18250 | virtual const RegMask &out_RegMask() const; |
| 18251 | virtual uint rule() const { return rolL_rReg_i8_rule; } |
| 18252 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18253 | virtual uint two_adr() const { return oper_input_base(); } |
| 18254 | public: |
| 18255 | rolL_rReg_i8Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18256 | virtual uint size_of() const { return sizeof(rolL_rReg_i8Node); } |
| 18257 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18258 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18259 | #ifndef PRODUCT |
| 18260 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18261 | virtual const char *Name() const { return "rolL_rReg_i8";} |
| 18262 | #endif |
| 18263 | }; |
| 18264 | |
| 18265 | class rolL_rReg_i8_0Node : public MachNode { |
| 18266 | private: |
| 18267 | MachOper *_opnd_array[5]; |
| 18268 | public: |
| 18269 | MachOper *opnd_array(uint operand_index) const { |
| 18270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18271 | return _opnd_array[operand_index]; |
| 18272 | } |
| 18273 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18274 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18275 | _opnd_array[operand_index] = operand; |
| 18276 | } |
| 18277 | private: |
| 18278 | virtual const RegMask &out_RegMask() const; |
| 18279 | virtual uint rule() const { return rolL_rReg_i8_0_rule; } |
| 18280 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18281 | virtual uint two_adr() const { return oper_input_base(); } |
| 18282 | public: |
| 18283 | rolL_rReg_i8_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18284 | virtual uint size_of() const { return sizeof(rolL_rReg_i8_0Node); } |
| 18285 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18286 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18287 | #ifndef PRODUCT |
| 18288 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18289 | virtual const char *Name() const { return "rolL_rReg_i8_0";} |
| 18290 | #endif |
| 18291 | }; |
| 18292 | |
| 18293 | class rolL_rReg_Var_C0Node : public MachNode { |
| 18294 | private: |
| 18295 | MachOper *_opnd_array[6]; |
| 18296 | public: |
| 18297 | MachOper *opnd_array(uint operand_index) const { |
| 18298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18299 | return _opnd_array[operand_index]; |
| 18300 | } |
| 18301 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18302 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18303 | _opnd_array[operand_index] = operand; |
| 18304 | } |
| 18305 | private: |
| 18306 | virtual const RegMask &out_RegMask() const; |
| 18307 | virtual uint rule() const { return rolL_rReg_Var_C0_rule; } |
| 18308 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18309 | virtual uint two_adr() const { return oper_input_base(); } |
| 18310 | public: |
| 18311 | rolL_rReg_Var_C0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18312 | virtual uint size_of() const { return sizeof(rolL_rReg_Var_C0Node); } |
| 18313 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18314 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18315 | #ifndef PRODUCT |
| 18316 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18317 | virtual const char *Name() const { return "rolL_rReg_Var_C0";} |
| 18318 | #endif |
| 18319 | }; |
| 18320 | |
| 18321 | class rolL_rReg_Var_C0_0Node : public MachNode { |
| 18322 | private: |
| 18323 | MachOper *_opnd_array[6]; |
| 18324 | public: |
| 18325 | MachOper *opnd_array(uint operand_index) const { |
| 18326 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18327 | return _opnd_array[operand_index]; |
| 18328 | } |
| 18329 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18331 | _opnd_array[operand_index] = operand; |
| 18332 | } |
| 18333 | private: |
| 18334 | virtual const RegMask &out_RegMask() const; |
| 18335 | virtual uint rule() const { return rolL_rReg_Var_C0_0_rule; } |
| 18336 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18337 | virtual uint two_adr() const { return oper_input_base(); } |
| 18338 | public: |
| 18339 | rolL_rReg_Var_C0_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18340 | virtual uint size_of() const { return sizeof(rolL_rReg_Var_C0_0Node); } |
| 18341 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18342 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18343 | #ifndef PRODUCT |
| 18344 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18345 | virtual const char *Name() const { return "rolL_rReg_Var_C0_0";} |
| 18346 | #endif |
| 18347 | }; |
| 18348 | |
| 18349 | class rolL_rReg_Var_C64Node : public MachNode { |
| 18350 | private: |
| 18351 | MachOper *_opnd_array[6]; |
| 18352 | public: |
| 18353 | MachOper *opnd_array(uint operand_index) const { |
| 18354 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18355 | return _opnd_array[operand_index]; |
| 18356 | } |
| 18357 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18358 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18359 | _opnd_array[operand_index] = operand; |
| 18360 | } |
| 18361 | private: |
| 18362 | virtual const RegMask &out_RegMask() const; |
| 18363 | virtual uint rule() const { return rolL_rReg_Var_C64_rule; } |
| 18364 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18365 | virtual uint two_adr() const { return oper_input_base(); } |
| 18366 | public: |
| 18367 | rolL_rReg_Var_C64Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18368 | virtual uint size_of() const { return sizeof(rolL_rReg_Var_C64Node); } |
| 18369 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18370 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18371 | #ifndef PRODUCT |
| 18372 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18373 | virtual const char *Name() const { return "rolL_rReg_Var_C64";} |
| 18374 | #endif |
| 18375 | }; |
| 18376 | |
| 18377 | class rolL_rReg_Var_C64_0Node : public MachNode { |
| 18378 | private: |
| 18379 | MachOper *_opnd_array[6]; |
| 18380 | public: |
| 18381 | MachOper *opnd_array(uint operand_index) const { |
| 18382 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18383 | return _opnd_array[operand_index]; |
| 18384 | } |
| 18385 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18386 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18387 | _opnd_array[operand_index] = operand; |
| 18388 | } |
| 18389 | private: |
| 18390 | virtual const RegMask &out_RegMask() const; |
| 18391 | virtual uint rule() const { return rolL_rReg_Var_C64_0_rule; } |
| 18392 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18393 | virtual uint two_adr() const { return oper_input_base(); } |
| 18394 | public: |
| 18395 | rolL_rReg_Var_C64_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18396 | virtual uint size_of() const { return sizeof(rolL_rReg_Var_C64_0Node); } |
| 18397 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18398 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18399 | #ifndef PRODUCT |
| 18400 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18401 | virtual const char *Name() const { return "rolL_rReg_Var_C64_0";} |
| 18402 | #endif |
| 18403 | }; |
| 18404 | |
| 18405 | class rorL_rReg_imm1Node : public MachNode { |
| 18406 | private: |
| 18407 | MachOper *_opnd_array[2]; |
| 18408 | public: |
| 18409 | MachOper *opnd_array(uint operand_index) const { |
| 18410 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18411 | return _opnd_array[operand_index]; |
| 18412 | } |
| 18413 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18414 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18415 | _opnd_array[operand_index] = operand; |
| 18416 | } |
| 18417 | private: |
| 18418 | virtual const RegMask &out_RegMask() const; |
| 18419 | virtual uint rule() const { return rorL_rReg_imm1_rule; } |
| 18420 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18421 | virtual uint two_adr() const { return oper_input_base(); } |
| 18422 | public: |
| 18423 | rorL_rReg_imm1Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 18424 | virtual uint size_of() const { return sizeof(rorL_rReg_imm1Node); } |
| 18425 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18426 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18427 | static const Pipeline *pipeline_class(); |
| 18428 | virtual const Pipeline *pipeline() const; |
| 18429 | #ifndef PRODUCT |
| 18430 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18431 | virtual const char *Name() const { return "rorL_rReg_imm1";} |
| 18432 | #endif |
| 18433 | }; |
| 18434 | |
| 18435 | class rorL_rReg_imm8Node : public MachNode { |
| 18436 | private: |
| 18437 | MachOper *_opnd_array[3]; |
| 18438 | public: |
| 18439 | MachOper *opnd_array(uint operand_index) const { |
| 18440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18441 | return _opnd_array[operand_index]; |
| 18442 | } |
| 18443 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18444 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18445 | _opnd_array[operand_index] = operand; |
| 18446 | } |
| 18447 | private: |
| 18448 | virtual const RegMask &out_RegMask() const; |
| 18449 | virtual uint rule() const { return rorL_rReg_imm8_rule; } |
| 18450 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18451 | virtual uint two_adr() const { return oper_input_base(); } |
| 18452 | public: |
| 18453 | rorL_rReg_imm8Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18454 | virtual uint size_of() const { return sizeof(rorL_rReg_imm8Node); } |
| 18455 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18456 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18457 | static const Pipeline *pipeline_class(); |
| 18458 | virtual const Pipeline *pipeline() const; |
| 18459 | #ifndef PRODUCT |
| 18460 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18461 | virtual const char *Name() const { return "rorL_rReg_imm8";} |
| 18462 | #endif |
| 18463 | }; |
| 18464 | |
| 18465 | class rorL_rReg_CLNode : public MachNode { |
| 18466 | private: |
| 18467 | MachOper *_opnd_array[3]; |
| 18468 | public: |
| 18469 | MachOper *opnd_array(uint operand_index) const { |
| 18470 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18471 | return _opnd_array[operand_index]; |
| 18472 | } |
| 18473 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18474 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18475 | _opnd_array[operand_index] = operand; |
| 18476 | } |
| 18477 | private: |
| 18478 | virtual const RegMask &out_RegMask() const; |
| 18479 | virtual uint rule() const { return rorL_rReg_CL_rule; } |
| 18480 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18481 | virtual uint two_adr() const { return oper_input_base(); } |
| 18482 | public: |
| 18483 | rorL_rReg_CLNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18484 | virtual uint size_of() const { return sizeof(rorL_rReg_CLNode); } |
| 18485 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18486 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18487 | static const Pipeline *pipeline_class(); |
| 18488 | virtual const Pipeline *pipeline() const; |
| 18489 | #ifndef PRODUCT |
| 18490 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18491 | virtual const char *Name() const { return "rorL_rReg_CL";} |
| 18492 | #endif |
| 18493 | }; |
| 18494 | |
| 18495 | class rorL_rReg_i1Node : public MachNode { |
| 18496 | private: |
| 18497 | MachOper *_opnd_array[5]; |
| 18498 | public: |
| 18499 | MachOper *opnd_array(uint operand_index) const { |
| 18500 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18501 | return _opnd_array[operand_index]; |
| 18502 | } |
| 18503 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18504 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18505 | _opnd_array[operand_index] = operand; |
| 18506 | } |
| 18507 | private: |
| 18508 | virtual const RegMask &out_RegMask() const; |
| 18509 | virtual uint rule() const { return rorL_rReg_i1_rule; } |
| 18510 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18511 | virtual uint two_adr() const { return oper_input_base(); } |
| 18512 | public: |
| 18513 | rorL_rReg_i1Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18514 | virtual uint size_of() const { return sizeof(rorL_rReg_i1Node); } |
| 18515 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18516 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18517 | #ifndef PRODUCT |
| 18518 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18519 | virtual const char *Name() const { return "rorL_rReg_i1";} |
| 18520 | #endif |
| 18521 | }; |
| 18522 | |
| 18523 | class rorL_rReg_i1_0Node : public MachNode { |
| 18524 | private: |
| 18525 | MachOper *_opnd_array[5]; |
| 18526 | public: |
| 18527 | MachOper *opnd_array(uint operand_index) const { |
| 18528 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18529 | return _opnd_array[operand_index]; |
| 18530 | } |
| 18531 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18532 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18533 | _opnd_array[operand_index] = operand; |
| 18534 | } |
| 18535 | private: |
| 18536 | virtual const RegMask &out_RegMask() const; |
| 18537 | virtual uint rule() const { return rorL_rReg_i1_0_rule; } |
| 18538 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18539 | virtual uint two_adr() const { return oper_input_base(); } |
| 18540 | public: |
| 18541 | rorL_rReg_i1_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18542 | virtual uint size_of() const { return sizeof(rorL_rReg_i1_0Node); } |
| 18543 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18544 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18545 | #ifndef PRODUCT |
| 18546 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18547 | virtual const char *Name() const { return "rorL_rReg_i1_0";} |
| 18548 | #endif |
| 18549 | }; |
| 18550 | |
| 18551 | class rorL_rReg_i8Node : public MachNode { |
| 18552 | private: |
| 18553 | MachOper *_opnd_array[5]; |
| 18554 | public: |
| 18555 | MachOper *opnd_array(uint operand_index) const { |
| 18556 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18557 | return _opnd_array[operand_index]; |
| 18558 | } |
| 18559 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18560 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18561 | _opnd_array[operand_index] = operand; |
| 18562 | } |
| 18563 | private: |
| 18564 | virtual const RegMask &out_RegMask() const; |
| 18565 | virtual uint rule() const { return rorL_rReg_i8_rule; } |
| 18566 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18567 | virtual uint two_adr() const { return oper_input_base(); } |
| 18568 | public: |
| 18569 | rorL_rReg_i8Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18570 | virtual uint size_of() const { return sizeof(rorL_rReg_i8Node); } |
| 18571 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18572 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18573 | #ifndef PRODUCT |
| 18574 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18575 | virtual const char *Name() const { return "rorL_rReg_i8";} |
| 18576 | #endif |
| 18577 | }; |
| 18578 | |
| 18579 | class rorL_rReg_i8_0Node : public MachNode { |
| 18580 | private: |
| 18581 | MachOper *_opnd_array[5]; |
| 18582 | public: |
| 18583 | MachOper *opnd_array(uint operand_index) const { |
| 18584 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18585 | return _opnd_array[operand_index]; |
| 18586 | } |
| 18587 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18588 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18589 | _opnd_array[operand_index] = operand; |
| 18590 | } |
| 18591 | private: |
| 18592 | virtual const RegMask &out_RegMask() const; |
| 18593 | virtual uint rule() const { return rorL_rReg_i8_0_rule; } |
| 18594 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18595 | virtual uint two_adr() const { return oper_input_base(); } |
| 18596 | public: |
| 18597 | rorL_rReg_i8_0Node() { _num_opnds = 5; _opnds = _opnd_array; } |
| 18598 | virtual uint size_of() const { return sizeof(rorL_rReg_i8_0Node); } |
| 18599 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18600 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18601 | #ifndef PRODUCT |
| 18602 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18603 | virtual const char *Name() const { return "rorL_rReg_i8_0";} |
| 18604 | #endif |
| 18605 | }; |
| 18606 | |
| 18607 | class rorL_rReg_Var_C0Node : public MachNode { |
| 18608 | private: |
| 18609 | MachOper *_opnd_array[6]; |
| 18610 | public: |
| 18611 | MachOper *opnd_array(uint operand_index) const { |
| 18612 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18613 | return _opnd_array[operand_index]; |
| 18614 | } |
| 18615 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18616 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18617 | _opnd_array[operand_index] = operand; |
| 18618 | } |
| 18619 | private: |
| 18620 | virtual const RegMask &out_RegMask() const; |
| 18621 | virtual uint rule() const { return rorL_rReg_Var_C0_rule; } |
| 18622 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18623 | virtual uint two_adr() const { return oper_input_base(); } |
| 18624 | public: |
| 18625 | rorL_rReg_Var_C0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18626 | virtual uint size_of() const { return sizeof(rorL_rReg_Var_C0Node); } |
| 18627 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18628 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18629 | #ifndef PRODUCT |
| 18630 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18631 | virtual const char *Name() const { return "rorL_rReg_Var_C0";} |
| 18632 | #endif |
| 18633 | }; |
| 18634 | |
| 18635 | class rorL_rReg_Var_C0_0Node : public MachNode { |
| 18636 | private: |
| 18637 | MachOper *_opnd_array[6]; |
| 18638 | public: |
| 18639 | MachOper *opnd_array(uint operand_index) const { |
| 18640 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18641 | return _opnd_array[operand_index]; |
| 18642 | } |
| 18643 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18644 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18645 | _opnd_array[operand_index] = operand; |
| 18646 | } |
| 18647 | private: |
| 18648 | virtual const RegMask &out_RegMask() const; |
| 18649 | virtual uint rule() const { return rorL_rReg_Var_C0_0_rule; } |
| 18650 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18651 | virtual uint two_adr() const { return oper_input_base(); } |
| 18652 | public: |
| 18653 | rorL_rReg_Var_C0_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18654 | virtual uint size_of() const { return sizeof(rorL_rReg_Var_C0_0Node); } |
| 18655 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18656 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18657 | #ifndef PRODUCT |
| 18658 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18659 | virtual const char *Name() const { return "rorL_rReg_Var_C0_0";} |
| 18660 | #endif |
| 18661 | }; |
| 18662 | |
| 18663 | class rorL_rReg_Var_C64Node : public MachNode { |
| 18664 | private: |
| 18665 | MachOper *_opnd_array[6]; |
| 18666 | public: |
| 18667 | MachOper *opnd_array(uint operand_index) const { |
| 18668 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18669 | return _opnd_array[operand_index]; |
| 18670 | } |
| 18671 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18672 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18673 | _opnd_array[operand_index] = operand; |
| 18674 | } |
| 18675 | private: |
| 18676 | virtual const RegMask &out_RegMask() const; |
| 18677 | virtual uint rule() const { return rorL_rReg_Var_C64_rule; } |
| 18678 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18679 | virtual uint two_adr() const { return oper_input_base(); } |
| 18680 | public: |
| 18681 | rorL_rReg_Var_C64Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18682 | virtual uint size_of() const { return sizeof(rorL_rReg_Var_C64Node); } |
| 18683 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18684 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18685 | #ifndef PRODUCT |
| 18686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18687 | virtual const char *Name() const { return "rorL_rReg_Var_C64";} |
| 18688 | #endif |
| 18689 | }; |
| 18690 | |
| 18691 | class rorL_rReg_Var_C64_0Node : public MachNode { |
| 18692 | private: |
| 18693 | MachOper *_opnd_array[6]; |
| 18694 | public: |
| 18695 | MachOper *opnd_array(uint operand_index) const { |
| 18696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18697 | return _opnd_array[operand_index]; |
| 18698 | } |
| 18699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18701 | _opnd_array[operand_index] = operand; |
| 18702 | } |
| 18703 | private: |
| 18704 | virtual const RegMask &out_RegMask() const; |
| 18705 | virtual uint rule() const { return rorL_rReg_Var_C64_0_rule; } |
| 18706 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 18707 | virtual uint two_adr() const { return oper_input_base(); } |
| 18708 | public: |
| 18709 | rorL_rReg_Var_C64_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 18710 | virtual uint size_of() const { return sizeof(rorL_rReg_Var_C64_0Node); } |
| 18711 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18712 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18713 | #ifndef PRODUCT |
| 18714 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18715 | virtual const char *Name() const { return "rorL_rReg_Var_C64_0";} |
| 18716 | #endif |
| 18717 | }; |
| 18718 | |
| 18719 | class andI_rRegNode : public MachNode { |
| 18720 | private: |
| 18721 | MachOper *_opnd_array[3]; |
| 18722 | public: |
| 18723 | MachOper *opnd_array(uint operand_index) const { |
| 18724 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18725 | return _opnd_array[operand_index]; |
| 18726 | } |
| 18727 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18728 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18729 | _opnd_array[operand_index] = operand; |
| 18730 | } |
| 18731 | private: |
| 18732 | const RegMask *_cisc_RegMask; |
| 18733 | virtual const RegMask &out_RegMask() const; |
| 18734 | virtual uint rule() const { return andI_rReg_rule; } |
| 18735 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18736 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18737 | virtual uint two_adr() const { return oper_input_base(); } |
| 18738 | virtual int cisc_operand() const { return 2; } |
| 18739 | virtual MachNode *cisc_version(int offset); |
| 18740 | virtual void use_cisc_RegMask(); |
| 18741 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 18742 | public: |
| 18743 | andI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 18744 | virtual uint size_of() const { return sizeof(andI_rRegNode); } |
| 18745 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18746 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18747 | static const Pipeline *pipeline_class(); |
| 18748 | virtual const Pipeline *pipeline() const; |
| 18749 | #ifndef PRODUCT |
| 18750 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18751 | virtual const char *Name() const { return "andI_rReg";} |
| 18752 | #endif |
| 18753 | }; |
| 18754 | |
| 18755 | class andI_rReg_imm255Node : public MachNode { |
| 18756 | private: |
| 18757 | MachOper *_opnd_array[3]; |
| 18758 | public: |
| 18759 | MachOper *opnd_array(uint operand_index) const { |
| 18760 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18761 | return _opnd_array[operand_index]; |
| 18762 | } |
| 18763 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18765 | _opnd_array[operand_index] = operand; |
| 18766 | } |
| 18767 | private: |
| 18768 | virtual const RegMask &out_RegMask() const; |
| 18769 | virtual uint rule() const { return andI_rReg_imm255_rule; } |
| 18770 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18771 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18772 | virtual uint two_adr() const { return oper_input_base(); } |
| 18773 | public: |
| 18774 | andI_rReg_imm255Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18775 | virtual uint size_of() const { return sizeof(andI_rReg_imm255Node); } |
| 18776 | static const Pipeline *pipeline_class(); |
| 18777 | virtual const Pipeline *pipeline() const; |
| 18778 | #ifndef PRODUCT |
| 18779 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18780 | virtual const char *Name() const { return "andI_rReg_imm255";} |
| 18781 | #endif |
| 18782 | }; |
| 18783 | |
| 18784 | class andI2L_rReg_imm255Node : public MachNode { |
| 18785 | private: |
| 18786 | MachOper *_opnd_array[3]; |
| 18787 | public: |
| 18788 | MachOper *opnd_array(uint operand_index) const { |
| 18789 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18790 | return _opnd_array[operand_index]; |
| 18791 | } |
| 18792 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18793 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18794 | _opnd_array[operand_index] = operand; |
| 18795 | } |
| 18796 | private: |
| 18797 | const RegMask *_cisc_RegMask; |
| 18798 | virtual const RegMask &out_RegMask() const; |
| 18799 | virtual uint rule() const { return andI2L_rReg_imm255_rule; } |
| 18800 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18801 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 18802 | virtual int cisc_operand() const { return 1; } |
| 18803 | virtual MachNode *cisc_version(int offset); |
| 18804 | virtual void use_cisc_RegMask(); |
| 18805 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 18806 | public: |
| 18807 | andI2L_rReg_imm255Node() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 18808 | virtual uint size_of() const { return sizeof(andI2L_rReg_imm255Node); } |
| 18809 | static const Pipeline *pipeline_class(); |
| 18810 | virtual const Pipeline *pipeline() const; |
| 18811 | #ifndef PRODUCT |
| 18812 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18813 | virtual const char *Name() const { return "andI2L_rReg_imm255";} |
| 18814 | #endif |
| 18815 | }; |
| 18816 | |
| 18817 | class andI_rReg_imm65535Node : public MachNode { |
| 18818 | private: |
| 18819 | MachOper *_opnd_array[3]; |
| 18820 | public: |
| 18821 | MachOper *opnd_array(uint operand_index) const { |
| 18822 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18823 | return _opnd_array[operand_index]; |
| 18824 | } |
| 18825 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18826 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18827 | _opnd_array[operand_index] = operand; |
| 18828 | } |
| 18829 | private: |
| 18830 | virtual const RegMask &out_RegMask() const; |
| 18831 | virtual uint rule() const { return andI_rReg_imm65535_rule; } |
| 18832 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18833 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18834 | virtual uint two_adr() const { return oper_input_base(); } |
| 18835 | public: |
| 18836 | andI_rReg_imm65535Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18837 | virtual uint size_of() const { return sizeof(andI_rReg_imm65535Node); } |
| 18838 | static const Pipeline *pipeline_class(); |
| 18839 | virtual const Pipeline *pipeline() const; |
| 18840 | #ifndef PRODUCT |
| 18841 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18842 | virtual const char *Name() const { return "andI_rReg_imm65535";} |
| 18843 | #endif |
| 18844 | }; |
| 18845 | |
| 18846 | class andI2L_rReg_imm65535Node : public MachNode { |
| 18847 | private: |
| 18848 | MachOper *_opnd_array[3]; |
| 18849 | public: |
| 18850 | MachOper *opnd_array(uint operand_index) const { |
| 18851 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18852 | return _opnd_array[operand_index]; |
| 18853 | } |
| 18854 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18855 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18856 | _opnd_array[operand_index] = operand; |
| 18857 | } |
| 18858 | private: |
| 18859 | const RegMask *_cisc_RegMask; |
| 18860 | virtual const RegMask &out_RegMask() const; |
| 18861 | virtual uint rule() const { return andI2L_rReg_imm65535_rule; } |
| 18862 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18863 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 18864 | virtual int cisc_operand() const { return 1; } |
| 18865 | virtual MachNode *cisc_version(int offset); |
| 18866 | virtual void use_cisc_RegMask(); |
| 18867 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 18868 | public: |
| 18869 | andI2L_rReg_imm65535Node() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 18870 | virtual uint size_of() const { return sizeof(andI2L_rReg_imm65535Node); } |
| 18871 | static const Pipeline *pipeline_class(); |
| 18872 | virtual const Pipeline *pipeline() const; |
| 18873 | #ifndef PRODUCT |
| 18874 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18875 | virtual const char *Name() const { return "andI2L_rReg_imm65535";} |
| 18876 | #endif |
| 18877 | }; |
| 18878 | |
| 18879 | class andI_rReg_immNode : public MachNode { |
| 18880 | private: |
| 18881 | MachOper *_opnd_array[3]; |
| 18882 | public: |
| 18883 | MachOper *opnd_array(uint operand_index) const { |
| 18884 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18885 | return _opnd_array[operand_index]; |
| 18886 | } |
| 18887 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18889 | _opnd_array[operand_index] = operand; |
| 18890 | } |
| 18891 | private: |
| 18892 | virtual const RegMask &out_RegMask() const; |
| 18893 | virtual uint rule() const { return andI_rReg_imm_rule; } |
| 18894 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18895 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18896 | virtual uint two_adr() const { return oper_input_base(); } |
| 18897 | public: |
| 18898 | andI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 18899 | virtual uint size_of() const { return sizeof(andI_rReg_immNode); } |
| 18900 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18901 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18902 | static const Pipeline *pipeline_class(); |
| 18903 | virtual const Pipeline *pipeline() const; |
| 18904 | #ifndef PRODUCT |
| 18905 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18906 | virtual const char *Name() const { return "andI_rReg_imm";} |
| 18907 | #endif |
| 18908 | }; |
| 18909 | |
| 18910 | class andI_rReg_memNode : public MachNode { |
| 18911 | private: |
| 18912 | MachOper *_opnd_array[3]; |
| 18913 | public: |
| 18914 | MachOper *opnd_array(uint operand_index) const { |
| 18915 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18916 | return _opnd_array[operand_index]; |
| 18917 | } |
| 18918 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18919 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18920 | _opnd_array[operand_index] = operand; |
| 18921 | } |
| 18922 | private: |
| 18923 | virtual const RegMask &out_RegMask() const; |
| 18924 | virtual uint rule() const { return andI_rReg_mem_rule; } |
| 18925 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18926 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18927 | virtual uint two_adr() const { return oper_input_base(); } |
| 18928 | virtual int reloc() const; |
| 18929 | virtual uint oper_input_base() const { return 2; } |
| 18930 | public: |
| 18931 | andI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 18932 | virtual uint size_of() const { return sizeof(andI_rReg_memNode); } |
| 18933 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18934 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18935 | static const Pipeline *pipeline_class(); |
| 18936 | virtual const Pipeline *pipeline() const; |
| 18937 | virtual const MachOper *memory_operand() const; |
| 18938 | #ifndef PRODUCT |
| 18939 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18940 | virtual const char *Name() const { return "andI_rReg_mem";} |
| 18941 | #endif |
| 18942 | }; |
| 18943 | |
| 18944 | class andI_rReg_mem_0Node : public MachNode { |
| 18945 | private: |
| 18946 | MachOper *_opnd_array[3]; |
| 18947 | public: |
| 18948 | MachOper *opnd_array(uint operand_index) const { |
| 18949 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18950 | return _opnd_array[operand_index]; |
| 18951 | } |
| 18952 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18953 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18954 | _opnd_array[operand_index] = operand; |
| 18955 | } |
| 18956 | private: |
| 18957 | virtual const RegMask &out_RegMask() const; |
| 18958 | virtual uint rule() const { return andI_rReg_mem_0_rule; } |
| 18959 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18960 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 18961 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 18962 | virtual int reloc() const; |
| 18963 | virtual uint oper_input_base() const { return 2; } |
| 18964 | public: |
| 18965 | andI_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 18966 | virtual uint size_of() const { return sizeof(andI_rReg_mem_0Node); } |
| 18967 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 18968 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 18969 | static const Pipeline *pipeline_class(); |
| 18970 | virtual const Pipeline *pipeline() const; |
| 18971 | virtual const MachOper *memory_operand() const; |
| 18972 | #ifndef PRODUCT |
| 18973 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 18974 | virtual const char *Name() const { return "andI_rReg_mem_0";} |
| 18975 | #endif |
| 18976 | }; |
| 18977 | |
| 18978 | class andB_mem_rRegNode : public MachTypeNode { |
| 18979 | private: |
| 18980 | MachOper *_opnd_array[4]; |
| 18981 | public: |
| 18982 | MachOper *opnd_array(uint operand_index) const { |
| 18983 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18984 | return _opnd_array[operand_index]; |
| 18985 | } |
| 18986 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 18987 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 18988 | _opnd_array[operand_index] = operand; |
| 18989 | } |
| 18990 | private: |
| 18991 | virtual const RegMask &out_RegMask() const; |
| 18992 | virtual uint rule() const { return andB_mem_rReg_rule; } |
| 18993 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 18994 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 18995 | virtual int reloc() const; |
| 18996 | virtual uint oper_input_base() const { return 2; } |
| 18997 | public: |
| 18998 | andB_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 18999 | virtual uint size_of() const { return sizeof(andB_mem_rRegNode); } |
| 19000 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19001 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19002 | static const Pipeline *pipeline_class(); |
| 19003 | virtual const Pipeline *pipeline() const; |
| 19004 | virtual const MachOper *memory_operand() const; |
| 19005 | #ifndef PRODUCT |
| 19006 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19007 | virtual const char *Name() const { return "andB_mem_rReg";} |
| 19008 | #endif |
| 19009 | }; |
| 19010 | |
| 19011 | class andB_mem_rReg_0Node : public MachTypeNode { |
| 19012 | private: |
| 19013 | MachOper *_opnd_array[4]; |
| 19014 | public: |
| 19015 | MachOper *opnd_array(uint operand_index) const { |
| 19016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19017 | return _opnd_array[operand_index]; |
| 19018 | } |
| 19019 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19020 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19021 | _opnd_array[operand_index] = operand; |
| 19022 | } |
| 19023 | private: |
| 19024 | virtual const RegMask &out_RegMask() const; |
| 19025 | virtual uint rule() const { return andB_mem_rReg_0_rule; } |
| 19026 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19027 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 19028 | virtual int reloc() const; |
| 19029 | virtual uint oper_input_base() const { return 2; } |
| 19030 | public: |
| 19031 | andB_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19032 | virtual uint size_of() const { return sizeof(andB_mem_rReg_0Node); } |
| 19033 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19034 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19035 | static const Pipeline *pipeline_class(); |
| 19036 | virtual const Pipeline *pipeline() const; |
| 19037 | virtual const MachOper *memory_operand() const; |
| 19038 | #ifndef PRODUCT |
| 19039 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19040 | virtual const char *Name() const { return "andB_mem_rReg_0";} |
| 19041 | #endif |
| 19042 | }; |
| 19043 | |
| 19044 | class andI_mem_rRegNode : public MachTypeNode { |
| 19045 | private: |
| 19046 | MachOper *_opnd_array[4]; |
| 19047 | public: |
| 19048 | MachOper *opnd_array(uint operand_index) const { |
| 19049 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19050 | return _opnd_array[operand_index]; |
| 19051 | } |
| 19052 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19053 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19054 | _opnd_array[operand_index] = operand; |
| 19055 | } |
| 19056 | private: |
| 19057 | virtual const RegMask &out_RegMask() const; |
| 19058 | virtual uint rule() const { return andI_mem_rReg_rule; } |
| 19059 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19060 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19061 | virtual int reloc() const; |
| 19062 | virtual uint oper_input_base() const { return 2; } |
| 19063 | public: |
| 19064 | andI_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19065 | virtual uint size_of() const { return sizeof(andI_mem_rRegNode); } |
| 19066 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19067 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19068 | static const Pipeline *pipeline_class(); |
| 19069 | virtual const Pipeline *pipeline() const; |
| 19070 | virtual const MachOper *memory_operand() const; |
| 19071 | #ifndef PRODUCT |
| 19072 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19073 | virtual const char *Name() const { return "andI_mem_rReg";} |
| 19074 | #endif |
| 19075 | }; |
| 19076 | |
| 19077 | class andI_mem_rReg_0Node : public MachTypeNode { |
| 19078 | private: |
| 19079 | MachOper *_opnd_array[4]; |
| 19080 | public: |
| 19081 | MachOper *opnd_array(uint operand_index) const { |
| 19082 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19083 | return _opnd_array[operand_index]; |
| 19084 | } |
| 19085 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19086 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19087 | _opnd_array[operand_index] = operand; |
| 19088 | } |
| 19089 | private: |
| 19090 | virtual const RegMask &out_RegMask() const; |
| 19091 | virtual uint rule() const { return andI_mem_rReg_0_rule; } |
| 19092 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19093 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19094 | virtual int reloc() const; |
| 19095 | virtual uint oper_input_base() const { return 2; } |
| 19096 | public: |
| 19097 | andI_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19098 | virtual uint size_of() const { return sizeof(andI_mem_rReg_0Node); } |
| 19099 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19100 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19101 | static const Pipeline *pipeline_class(); |
| 19102 | virtual const Pipeline *pipeline() const; |
| 19103 | virtual const MachOper *memory_operand() const; |
| 19104 | #ifndef PRODUCT |
| 19105 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19106 | virtual const char *Name() const { return "andI_mem_rReg_0";} |
| 19107 | #endif |
| 19108 | }; |
| 19109 | |
| 19110 | class andI_mem_immNode : public MachTypeNode { |
| 19111 | private: |
| 19112 | MachOper *_opnd_array[4]; |
| 19113 | public: |
| 19114 | MachOper *opnd_array(uint operand_index) const { |
| 19115 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19116 | return _opnd_array[operand_index]; |
| 19117 | } |
| 19118 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19119 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19120 | _opnd_array[operand_index] = operand; |
| 19121 | } |
| 19122 | private: |
| 19123 | virtual const RegMask &out_RegMask() const; |
| 19124 | virtual uint rule() const { return andI_mem_imm_rule; } |
| 19125 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19126 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19127 | virtual int reloc() const; |
| 19128 | virtual uint oper_input_base() const { return 2; } |
| 19129 | public: |
| 19130 | andI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19131 | virtual uint size_of() const { return sizeof(andI_mem_immNode); } |
| 19132 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19133 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19134 | static const Pipeline *pipeline_class(); |
| 19135 | virtual const Pipeline *pipeline() const; |
| 19136 | virtual const MachOper *memory_operand() const; |
| 19137 | #ifndef PRODUCT |
| 19138 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19139 | virtual const char *Name() const { return "andI_mem_imm";} |
| 19140 | #endif |
| 19141 | }; |
| 19142 | |
| 19143 | class andnI_rReg_rReg_memNode : public MachNode { |
| 19144 | private: |
| 19145 | MachOper *_opnd_array[4]; |
| 19146 | public: |
| 19147 | MachOper *opnd_array(uint operand_index) const { |
| 19148 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19149 | return _opnd_array[operand_index]; |
| 19150 | } |
| 19151 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19152 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19153 | _opnd_array[operand_index] = operand; |
| 19154 | } |
| 19155 | private: |
| 19156 | virtual const RegMask &out_RegMask() const; |
| 19157 | virtual uint rule() const { return andnI_rReg_rReg_mem_rule; } |
| 19158 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19159 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19160 | virtual int reloc() const; |
| 19161 | virtual uint oper_input_base() const { return 2; } |
| 19162 | public: |
| 19163 | andnI_rReg_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 19164 | virtual uint size_of() const { return sizeof(andnI_rReg_rReg_memNode); } |
| 19165 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19166 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19167 | static const Pipeline *pipeline_class(); |
| 19168 | virtual const Pipeline *pipeline() const; |
| 19169 | virtual const MachOper *memory_operand() const; |
| 19170 | #ifndef PRODUCT |
| 19171 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19172 | virtual const char *Name() const { return "andnI_rReg_rReg_mem";} |
| 19173 | #endif |
| 19174 | }; |
| 19175 | |
| 19176 | class andnI_rReg_rReg_mem_0Node : public MachNode { |
| 19177 | private: |
| 19178 | MachOper *_opnd_array[4]; |
| 19179 | public: |
| 19180 | MachOper *opnd_array(uint operand_index) const { |
| 19181 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19182 | return _opnd_array[operand_index]; |
| 19183 | } |
| 19184 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19185 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19186 | _opnd_array[operand_index] = operand; |
| 19187 | } |
| 19188 | private: |
| 19189 | virtual const RegMask &out_RegMask() const; |
| 19190 | virtual uint rule() const { return andnI_rReg_rReg_mem_0_rule; } |
| 19191 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19192 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19193 | virtual int reloc() const; |
| 19194 | virtual uint oper_input_base() const { return 2; } |
| 19195 | public: |
| 19196 | andnI_rReg_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 19197 | virtual uint size_of() const { return sizeof(andnI_rReg_rReg_mem_0Node); } |
| 19198 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19199 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19200 | static const Pipeline *pipeline_class(); |
| 19201 | virtual const Pipeline *pipeline() const; |
| 19202 | virtual const MachOper *memory_operand() const; |
| 19203 | #ifndef PRODUCT |
| 19204 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19205 | virtual const char *Name() const { return "andnI_rReg_rReg_mem_0";} |
| 19206 | #endif |
| 19207 | }; |
| 19208 | |
| 19209 | class andnI_rReg_rReg_rRegNode : public MachNode { |
| 19210 | private: |
| 19211 | MachOper *_opnd_array[4]; |
| 19212 | public: |
| 19213 | MachOper *opnd_array(uint operand_index) const { |
| 19214 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19215 | return _opnd_array[operand_index]; |
| 19216 | } |
| 19217 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19218 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19219 | _opnd_array[operand_index] = operand; |
| 19220 | } |
| 19221 | private: |
| 19222 | const RegMask *_cisc_RegMask; |
| 19223 | virtual const RegMask &out_RegMask() const; |
| 19224 | virtual uint rule() const { return andnI_rReg_rReg_rReg_rule; } |
| 19225 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19226 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19227 | virtual int cisc_operand() const { return 3; } |
| 19228 | virtual MachNode *cisc_version(int offset); |
| 19229 | virtual void use_cisc_RegMask(); |
| 19230 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 19231 | public: |
| 19232 | andnI_rReg_rReg_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 19233 | virtual uint size_of() const { return sizeof(andnI_rReg_rReg_rRegNode); } |
| 19234 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19235 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19236 | static const Pipeline *pipeline_class(); |
| 19237 | virtual const Pipeline *pipeline() const; |
| 19238 | #ifndef PRODUCT |
| 19239 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19240 | virtual const char *Name() const { return "andnI_rReg_rReg_rReg";} |
| 19241 | #endif |
| 19242 | }; |
| 19243 | |
| 19244 | class andnI_rReg_rReg_rReg_0Node : public MachNode { |
| 19245 | private: |
| 19246 | MachOper *_opnd_array[4]; |
| 19247 | public: |
| 19248 | MachOper *opnd_array(uint operand_index) const { |
| 19249 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19250 | return _opnd_array[operand_index]; |
| 19251 | } |
| 19252 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19253 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19254 | _opnd_array[operand_index] = operand; |
| 19255 | } |
| 19256 | private: |
| 19257 | const RegMask *_cisc_RegMask; |
| 19258 | virtual const RegMask &out_RegMask() const; |
| 19259 | virtual uint rule() const { return andnI_rReg_rReg_rReg_0_rule; } |
| 19260 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19261 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19262 | virtual int cisc_operand() const { return 1; } |
| 19263 | virtual MachNode *cisc_version(int offset); |
| 19264 | virtual void use_cisc_RegMask(); |
| 19265 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 19266 | public: |
| 19267 | andnI_rReg_rReg_rReg_0Node() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 19268 | virtual uint size_of() const { return sizeof(andnI_rReg_rReg_rReg_0Node); } |
| 19269 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19270 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19271 | static const Pipeline *pipeline_class(); |
| 19272 | virtual const Pipeline *pipeline() const; |
| 19273 | #ifndef PRODUCT |
| 19274 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19275 | virtual const char *Name() const { return "andnI_rReg_rReg_rReg_0";} |
| 19276 | #endif |
| 19277 | }; |
| 19278 | |
| 19279 | class blsiI_rReg_rRegNode : public MachNode { |
| 19280 | private: |
| 19281 | MachOper *_opnd_array[4]; |
| 19282 | public: |
| 19283 | MachOper *opnd_array(uint operand_index) const { |
| 19284 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19285 | return _opnd_array[operand_index]; |
| 19286 | } |
| 19287 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19288 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19289 | _opnd_array[operand_index] = operand; |
| 19290 | } |
| 19291 | private: |
| 19292 | virtual const RegMask &out_RegMask() const; |
| 19293 | virtual uint rule() const { return blsiI_rReg_rReg_rule; } |
| 19294 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19295 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19296 | public: |
| 19297 | blsiI_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19298 | virtual uint size_of() const { return sizeof(blsiI_rReg_rRegNode); } |
| 19299 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19300 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19301 | static const Pipeline *pipeline_class(); |
| 19302 | virtual const Pipeline *pipeline() const; |
| 19303 | #ifndef PRODUCT |
| 19304 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19305 | virtual const char *Name() const { return "blsiI_rReg_rReg";} |
| 19306 | #endif |
| 19307 | }; |
| 19308 | |
| 19309 | class blsiI_rReg_rReg_0Node : public MachNode { |
| 19310 | private: |
| 19311 | MachOper *_opnd_array[4]; |
| 19312 | public: |
| 19313 | MachOper *opnd_array(uint operand_index) const { |
| 19314 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19315 | return _opnd_array[operand_index]; |
| 19316 | } |
| 19317 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19318 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19319 | _opnd_array[operand_index] = operand; |
| 19320 | } |
| 19321 | private: |
| 19322 | virtual const RegMask &out_RegMask() const; |
| 19323 | virtual uint rule() const { return blsiI_rReg_rReg_0_rule; } |
| 19324 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19325 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19326 | public: |
| 19327 | blsiI_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19328 | virtual uint size_of() const { return sizeof(blsiI_rReg_rReg_0Node); } |
| 19329 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19330 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19331 | static const Pipeline *pipeline_class(); |
| 19332 | virtual const Pipeline *pipeline() const; |
| 19333 | #ifndef PRODUCT |
| 19334 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19335 | virtual const char *Name() const { return "blsiI_rReg_rReg_0";} |
| 19336 | #endif |
| 19337 | }; |
| 19338 | |
| 19339 | class blsiI_rReg_memNode : public MachNode { |
| 19340 | private: |
| 19341 | MachOper *_opnd_array[4]; |
| 19342 | public: |
| 19343 | MachOper *opnd_array(uint operand_index) const { |
| 19344 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19345 | return _opnd_array[operand_index]; |
| 19346 | } |
| 19347 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19348 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19349 | _opnd_array[operand_index] = operand; |
| 19350 | } |
| 19351 | private: |
| 19352 | virtual const RegMask &out_RegMask() const; |
| 19353 | virtual uint rule() const { return blsiI_rReg_mem_rule; } |
| 19354 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19355 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19356 | virtual int reloc() const; |
| 19357 | virtual uint oper_input_base() const { return 2; } |
| 19358 | public: |
| 19359 | blsiI_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19360 | virtual uint size_of() const { return sizeof(blsiI_rReg_memNode); } |
| 19361 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19362 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19363 | static const Pipeline *pipeline_class(); |
| 19364 | virtual const Pipeline *pipeline() const; |
| 19365 | virtual const MachOper *memory_operand() const; |
| 19366 | #ifndef PRODUCT |
| 19367 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19368 | virtual const char *Name() const { return "blsiI_rReg_mem";} |
| 19369 | #endif |
| 19370 | }; |
| 19371 | |
| 19372 | class blsiI_rReg_mem_0Node : public MachNode { |
| 19373 | private: |
| 19374 | MachOper *_opnd_array[4]; |
| 19375 | public: |
| 19376 | MachOper *opnd_array(uint operand_index) const { |
| 19377 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19378 | return _opnd_array[operand_index]; |
| 19379 | } |
| 19380 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19381 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19382 | _opnd_array[operand_index] = operand; |
| 19383 | } |
| 19384 | private: |
| 19385 | virtual const RegMask &out_RegMask() const; |
| 19386 | virtual uint rule() const { return blsiI_rReg_mem_0_rule; } |
| 19387 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19388 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19389 | virtual int reloc() const; |
| 19390 | virtual uint oper_input_base() const { return 2; } |
| 19391 | public: |
| 19392 | blsiI_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19393 | virtual uint size_of() const { return sizeof(blsiI_rReg_mem_0Node); } |
| 19394 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19395 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19396 | static const Pipeline *pipeline_class(); |
| 19397 | virtual const Pipeline *pipeline() const; |
| 19398 | virtual const MachOper *memory_operand() const; |
| 19399 | #ifndef PRODUCT |
| 19400 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19401 | virtual const char *Name() const { return "blsiI_rReg_mem_0";} |
| 19402 | #endif |
| 19403 | }; |
| 19404 | |
| 19405 | class blsmskI_rReg_memNode : public MachNode { |
| 19406 | private: |
| 19407 | MachOper *_opnd_array[4]; |
| 19408 | public: |
| 19409 | MachOper *opnd_array(uint operand_index) const { |
| 19410 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19411 | return _opnd_array[operand_index]; |
| 19412 | } |
| 19413 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19414 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19415 | _opnd_array[operand_index] = operand; |
| 19416 | } |
| 19417 | private: |
| 19418 | virtual const RegMask &out_RegMask() const; |
| 19419 | virtual uint rule() const { return blsmskI_rReg_mem_rule; } |
| 19420 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19421 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 19422 | virtual int reloc() const; |
| 19423 | virtual uint oper_input_base() const { return 2; } |
| 19424 | public: |
| 19425 | blsmskI_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19426 | virtual uint size_of() const { return sizeof(blsmskI_rReg_memNode); } |
| 19427 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19428 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19429 | static const Pipeline *pipeline_class(); |
| 19430 | virtual const Pipeline *pipeline() const; |
| 19431 | virtual const MachOper *memory_operand() const; |
| 19432 | #ifndef PRODUCT |
| 19433 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19434 | virtual const char *Name() const { return "blsmskI_rReg_mem";} |
| 19435 | #endif |
| 19436 | }; |
| 19437 | |
| 19438 | class blsmskI_rReg_mem_0Node : public MachNode { |
| 19439 | private: |
| 19440 | MachOper *_opnd_array[4]; |
| 19441 | public: |
| 19442 | MachOper *opnd_array(uint operand_index) const { |
| 19443 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19444 | return _opnd_array[operand_index]; |
| 19445 | } |
| 19446 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19447 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19448 | _opnd_array[operand_index] = operand; |
| 19449 | } |
| 19450 | private: |
| 19451 | virtual const RegMask &out_RegMask() const; |
| 19452 | virtual uint rule() const { return blsmskI_rReg_mem_0_rule; } |
| 19453 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19454 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 19455 | virtual int reloc() const; |
| 19456 | virtual uint oper_input_base() const { return 2; } |
| 19457 | public: |
| 19458 | blsmskI_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19459 | virtual uint size_of() const { return sizeof(blsmskI_rReg_mem_0Node); } |
| 19460 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19461 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19462 | static const Pipeline *pipeline_class(); |
| 19463 | virtual const Pipeline *pipeline() const; |
| 19464 | virtual const MachOper *memory_operand() const; |
| 19465 | #ifndef PRODUCT |
| 19466 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19467 | virtual const char *Name() const { return "blsmskI_rReg_mem_0";} |
| 19468 | #endif |
| 19469 | }; |
| 19470 | |
| 19471 | class blsmskI_rReg_rRegNode : public MachNode { |
| 19472 | private: |
| 19473 | MachOper *_opnd_array[4]; |
| 19474 | public: |
| 19475 | MachOper *opnd_array(uint operand_index) const { |
| 19476 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19477 | return _opnd_array[operand_index]; |
| 19478 | } |
| 19479 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19481 | _opnd_array[operand_index] = operand; |
| 19482 | } |
| 19483 | private: |
| 19484 | virtual const RegMask &out_RegMask() const; |
| 19485 | virtual uint rule() const { return blsmskI_rReg_rReg_rule; } |
| 19486 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19487 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 19488 | public: |
| 19489 | blsmskI_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19490 | virtual uint size_of() const { return sizeof(blsmskI_rReg_rRegNode); } |
| 19491 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19492 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19493 | static const Pipeline *pipeline_class(); |
| 19494 | virtual const Pipeline *pipeline() const; |
| 19495 | #ifndef PRODUCT |
| 19496 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19497 | virtual const char *Name() const { return "blsmskI_rReg_rReg";} |
| 19498 | #endif |
| 19499 | }; |
| 19500 | |
| 19501 | class blsmskI_rReg_rReg_0Node : public MachNode { |
| 19502 | private: |
| 19503 | MachOper *_opnd_array[4]; |
| 19504 | public: |
| 19505 | MachOper *opnd_array(uint operand_index) const { |
| 19506 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19507 | return _opnd_array[operand_index]; |
| 19508 | } |
| 19509 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19511 | _opnd_array[operand_index] = operand; |
| 19512 | } |
| 19513 | private: |
| 19514 | virtual const RegMask &out_RegMask() const; |
| 19515 | virtual uint rule() const { return blsmskI_rReg_rReg_0_rule; } |
| 19516 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19517 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 19518 | public: |
| 19519 | blsmskI_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19520 | virtual uint size_of() const { return sizeof(blsmskI_rReg_rReg_0Node); } |
| 19521 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19522 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19523 | static const Pipeline *pipeline_class(); |
| 19524 | virtual const Pipeline *pipeline() const; |
| 19525 | #ifndef PRODUCT |
| 19526 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19527 | virtual const char *Name() const { return "blsmskI_rReg_rReg_0";} |
| 19528 | #endif |
| 19529 | }; |
| 19530 | |
| 19531 | class blsrI_rReg_rRegNode : public MachNode { |
| 19532 | private: |
| 19533 | MachOper *_opnd_array[4]; |
| 19534 | public: |
| 19535 | MachOper *opnd_array(uint operand_index) const { |
| 19536 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19537 | return _opnd_array[operand_index]; |
| 19538 | } |
| 19539 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19540 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19541 | _opnd_array[operand_index] = operand; |
| 19542 | } |
| 19543 | private: |
| 19544 | virtual const RegMask &out_RegMask() const; |
| 19545 | virtual uint rule() const { return blsrI_rReg_rReg_rule; } |
| 19546 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19547 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19548 | public: |
| 19549 | blsrI_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19550 | virtual uint size_of() const { return sizeof(blsrI_rReg_rRegNode); } |
| 19551 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19552 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19553 | static const Pipeline *pipeline_class(); |
| 19554 | virtual const Pipeline *pipeline() const; |
| 19555 | #ifndef PRODUCT |
| 19556 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19557 | virtual const char *Name() const { return "blsrI_rReg_rReg";} |
| 19558 | #endif |
| 19559 | }; |
| 19560 | |
| 19561 | class blsrI_rReg_rReg_0Node : public MachNode { |
| 19562 | private: |
| 19563 | MachOper *_opnd_array[4]; |
| 19564 | public: |
| 19565 | MachOper *opnd_array(uint operand_index) const { |
| 19566 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19567 | return _opnd_array[operand_index]; |
| 19568 | } |
| 19569 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19570 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19571 | _opnd_array[operand_index] = operand; |
| 19572 | } |
| 19573 | private: |
| 19574 | virtual const RegMask &out_RegMask() const; |
| 19575 | virtual uint rule() const { return blsrI_rReg_rReg_0_rule; } |
| 19576 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19577 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19578 | public: |
| 19579 | blsrI_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19580 | virtual uint size_of() const { return sizeof(blsrI_rReg_rReg_0Node); } |
| 19581 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19582 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19583 | static const Pipeline *pipeline_class(); |
| 19584 | virtual const Pipeline *pipeline() const; |
| 19585 | #ifndef PRODUCT |
| 19586 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19587 | virtual const char *Name() const { return "blsrI_rReg_rReg_0";} |
| 19588 | #endif |
| 19589 | }; |
| 19590 | |
| 19591 | class blsrI_rReg_memNode : public MachNode { |
| 19592 | private: |
| 19593 | MachOper *_opnd_array[4]; |
| 19594 | public: |
| 19595 | MachOper *opnd_array(uint operand_index) const { |
| 19596 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19597 | return _opnd_array[operand_index]; |
| 19598 | } |
| 19599 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19600 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19601 | _opnd_array[operand_index] = operand; |
| 19602 | } |
| 19603 | private: |
| 19604 | virtual const RegMask &out_RegMask() const; |
| 19605 | virtual uint rule() const { return blsrI_rReg_mem_rule; } |
| 19606 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19607 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19608 | virtual int reloc() const; |
| 19609 | virtual uint oper_input_base() const { return 2; } |
| 19610 | public: |
| 19611 | blsrI_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19612 | virtual uint size_of() const { return sizeof(blsrI_rReg_memNode); } |
| 19613 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19614 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19615 | static const Pipeline *pipeline_class(); |
| 19616 | virtual const Pipeline *pipeline() const; |
| 19617 | virtual const MachOper *memory_operand() const; |
| 19618 | #ifndef PRODUCT |
| 19619 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19620 | virtual const char *Name() const { return "blsrI_rReg_mem";} |
| 19621 | #endif |
| 19622 | }; |
| 19623 | |
| 19624 | class blsrI_rReg_mem_0Node : public MachNode { |
| 19625 | private: |
| 19626 | MachOper *_opnd_array[4]; |
| 19627 | public: |
| 19628 | MachOper *opnd_array(uint operand_index) const { |
| 19629 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19630 | return _opnd_array[operand_index]; |
| 19631 | } |
| 19632 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19633 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19634 | _opnd_array[operand_index] = operand; |
| 19635 | } |
| 19636 | private: |
| 19637 | virtual const RegMask &out_RegMask() const; |
| 19638 | virtual uint rule() const { return blsrI_rReg_mem_0_rule; } |
| 19639 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19640 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 19641 | virtual int reloc() const; |
| 19642 | virtual uint oper_input_base() const { return 2; } |
| 19643 | public: |
| 19644 | blsrI_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19645 | virtual uint size_of() const { return sizeof(blsrI_rReg_mem_0Node); } |
| 19646 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19647 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19648 | static const Pipeline *pipeline_class(); |
| 19649 | virtual const Pipeline *pipeline() const; |
| 19650 | virtual const MachOper *memory_operand() const; |
| 19651 | #ifndef PRODUCT |
| 19652 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19653 | virtual const char *Name() const { return "blsrI_rReg_mem_0";} |
| 19654 | #endif |
| 19655 | }; |
| 19656 | |
| 19657 | class orI_rRegNode : public MachNode { |
| 19658 | private: |
| 19659 | MachOper *_opnd_array[3]; |
| 19660 | public: |
| 19661 | MachOper *opnd_array(uint operand_index) const { |
| 19662 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19663 | return _opnd_array[operand_index]; |
| 19664 | } |
| 19665 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19666 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19667 | _opnd_array[operand_index] = operand; |
| 19668 | } |
| 19669 | private: |
| 19670 | const RegMask *_cisc_RegMask; |
| 19671 | virtual const RegMask &out_RegMask() const; |
| 19672 | virtual uint rule() const { return orI_rReg_rule; } |
| 19673 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19674 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 19675 | virtual uint two_adr() const { return oper_input_base(); } |
| 19676 | virtual int cisc_operand() const { return 2; } |
| 19677 | virtual MachNode *cisc_version(int offset); |
| 19678 | virtual void use_cisc_RegMask(); |
| 19679 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 19680 | public: |
| 19681 | orI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 19682 | virtual uint size_of() const { return sizeof(orI_rRegNode); } |
| 19683 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19684 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19685 | static const Pipeline *pipeline_class(); |
| 19686 | virtual const Pipeline *pipeline() const; |
| 19687 | #ifndef PRODUCT |
| 19688 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19689 | virtual const char *Name() const { return "orI_rReg";} |
| 19690 | #endif |
| 19691 | }; |
| 19692 | |
| 19693 | class orI_rReg_immNode : public MachNode { |
| 19694 | private: |
| 19695 | MachOper *_opnd_array[3]; |
| 19696 | public: |
| 19697 | MachOper *opnd_array(uint operand_index) const { |
| 19698 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19699 | return _opnd_array[operand_index]; |
| 19700 | } |
| 19701 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19702 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19703 | _opnd_array[operand_index] = operand; |
| 19704 | } |
| 19705 | private: |
| 19706 | virtual const RegMask &out_RegMask() const; |
| 19707 | virtual uint rule() const { return orI_rReg_imm_rule; } |
| 19708 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19709 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 19710 | virtual uint two_adr() const { return oper_input_base(); } |
| 19711 | public: |
| 19712 | orI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 19713 | virtual uint size_of() const { return sizeof(orI_rReg_immNode); } |
| 19714 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19715 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19716 | static const Pipeline *pipeline_class(); |
| 19717 | virtual const Pipeline *pipeline() const; |
| 19718 | #ifndef PRODUCT |
| 19719 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19720 | virtual const char *Name() const { return "orI_rReg_imm";} |
| 19721 | #endif |
| 19722 | }; |
| 19723 | |
| 19724 | class orI_rReg_memNode : public MachNode { |
| 19725 | private: |
| 19726 | MachOper *_opnd_array[3]; |
| 19727 | public: |
| 19728 | MachOper *opnd_array(uint operand_index) const { |
| 19729 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19730 | return _opnd_array[operand_index]; |
| 19731 | } |
| 19732 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19733 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19734 | _opnd_array[operand_index] = operand; |
| 19735 | } |
| 19736 | private: |
| 19737 | virtual const RegMask &out_RegMask() const; |
| 19738 | virtual uint rule() const { return orI_rReg_mem_rule; } |
| 19739 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19740 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 19741 | virtual uint two_adr() const { return oper_input_base(); } |
| 19742 | virtual int reloc() const; |
| 19743 | virtual uint oper_input_base() const { return 2; } |
| 19744 | public: |
| 19745 | orI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 19746 | virtual uint size_of() const { return sizeof(orI_rReg_memNode); } |
| 19747 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19748 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19749 | static const Pipeline *pipeline_class(); |
| 19750 | virtual const Pipeline *pipeline() const; |
| 19751 | virtual const MachOper *memory_operand() const; |
| 19752 | #ifndef PRODUCT |
| 19753 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19754 | virtual const char *Name() const { return "orI_rReg_mem";} |
| 19755 | #endif |
| 19756 | }; |
| 19757 | |
| 19758 | class orI_rReg_mem_0Node : public MachNode { |
| 19759 | private: |
| 19760 | MachOper *_opnd_array[3]; |
| 19761 | public: |
| 19762 | MachOper *opnd_array(uint operand_index) const { |
| 19763 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19764 | return _opnd_array[operand_index]; |
| 19765 | } |
| 19766 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19767 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19768 | _opnd_array[operand_index] = operand; |
| 19769 | } |
| 19770 | private: |
| 19771 | virtual const RegMask &out_RegMask() const; |
| 19772 | virtual uint rule() const { return orI_rReg_mem_0_rule; } |
| 19773 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19774 | virtual int ideal_Opcode() const { return Op_OrI; } |
| 19775 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 19776 | virtual int reloc() const; |
| 19777 | virtual uint oper_input_base() const { return 2; } |
| 19778 | public: |
| 19779 | orI_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 19780 | virtual uint size_of() const { return sizeof(orI_rReg_mem_0Node); } |
| 19781 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19782 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19783 | static const Pipeline *pipeline_class(); |
| 19784 | virtual const Pipeline *pipeline() const; |
| 19785 | virtual const MachOper *memory_operand() const; |
| 19786 | #ifndef PRODUCT |
| 19787 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19788 | virtual const char *Name() const { return "orI_rReg_mem_0";} |
| 19789 | #endif |
| 19790 | }; |
| 19791 | |
| 19792 | class orB_mem_rRegNode : public MachTypeNode { |
| 19793 | private: |
| 19794 | MachOper *_opnd_array[4]; |
| 19795 | public: |
| 19796 | MachOper *opnd_array(uint operand_index) const { |
| 19797 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19798 | return _opnd_array[operand_index]; |
| 19799 | } |
| 19800 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19801 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19802 | _opnd_array[operand_index] = operand; |
| 19803 | } |
| 19804 | private: |
| 19805 | virtual const RegMask &out_RegMask() const; |
| 19806 | virtual uint rule() const { return orB_mem_rReg_rule; } |
| 19807 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19808 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 19809 | virtual int reloc() const; |
| 19810 | virtual uint oper_input_base() const { return 2; } |
| 19811 | public: |
| 19812 | orB_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19813 | virtual uint size_of() const { return sizeof(orB_mem_rRegNode); } |
| 19814 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19815 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19816 | static const Pipeline *pipeline_class(); |
| 19817 | virtual const Pipeline *pipeline() const; |
| 19818 | virtual const MachOper *memory_operand() const; |
| 19819 | #ifndef PRODUCT |
| 19820 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19821 | virtual const char *Name() const { return "orB_mem_rReg";} |
| 19822 | #endif |
| 19823 | }; |
| 19824 | |
| 19825 | class orB_mem_rReg_0Node : public MachTypeNode { |
| 19826 | private: |
| 19827 | MachOper *_opnd_array[4]; |
| 19828 | public: |
| 19829 | MachOper *opnd_array(uint operand_index) const { |
| 19830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19831 | return _opnd_array[operand_index]; |
| 19832 | } |
| 19833 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19834 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19835 | _opnd_array[operand_index] = operand; |
| 19836 | } |
| 19837 | private: |
| 19838 | virtual const RegMask &out_RegMask() const; |
| 19839 | virtual uint rule() const { return orB_mem_rReg_0_rule; } |
| 19840 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19841 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 19842 | virtual int reloc() const; |
| 19843 | virtual uint oper_input_base() const { return 2; } |
| 19844 | public: |
| 19845 | orB_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19846 | virtual uint size_of() const { return sizeof(orB_mem_rReg_0Node); } |
| 19847 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19848 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19849 | static const Pipeline *pipeline_class(); |
| 19850 | virtual const Pipeline *pipeline() const; |
| 19851 | virtual const MachOper *memory_operand() const; |
| 19852 | #ifndef PRODUCT |
| 19853 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19854 | virtual const char *Name() const { return "orB_mem_rReg_0";} |
| 19855 | #endif |
| 19856 | }; |
| 19857 | |
| 19858 | class orI_mem_rRegNode : public MachTypeNode { |
| 19859 | private: |
| 19860 | MachOper *_opnd_array[4]; |
| 19861 | public: |
| 19862 | MachOper *opnd_array(uint operand_index) const { |
| 19863 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19864 | return _opnd_array[operand_index]; |
| 19865 | } |
| 19866 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19867 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19868 | _opnd_array[operand_index] = operand; |
| 19869 | } |
| 19870 | private: |
| 19871 | virtual const RegMask &out_RegMask() const; |
| 19872 | virtual uint rule() const { return orI_mem_rReg_rule; } |
| 19873 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19874 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19875 | virtual int reloc() const; |
| 19876 | virtual uint oper_input_base() const { return 2; } |
| 19877 | public: |
| 19878 | orI_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19879 | virtual uint size_of() const { return sizeof(orI_mem_rRegNode); } |
| 19880 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19881 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19882 | static const Pipeline *pipeline_class(); |
| 19883 | virtual const Pipeline *pipeline() const; |
| 19884 | virtual const MachOper *memory_operand() const; |
| 19885 | #ifndef PRODUCT |
| 19886 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19887 | virtual const char *Name() const { return "orI_mem_rReg";} |
| 19888 | #endif |
| 19889 | }; |
| 19890 | |
| 19891 | class orI_mem_rReg_0Node : public MachTypeNode { |
| 19892 | private: |
| 19893 | MachOper *_opnd_array[4]; |
| 19894 | public: |
| 19895 | MachOper *opnd_array(uint operand_index) const { |
| 19896 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19897 | return _opnd_array[operand_index]; |
| 19898 | } |
| 19899 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19900 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19901 | _opnd_array[operand_index] = operand; |
| 19902 | } |
| 19903 | private: |
| 19904 | virtual const RegMask &out_RegMask() const; |
| 19905 | virtual uint rule() const { return orI_mem_rReg_0_rule; } |
| 19906 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19907 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19908 | virtual int reloc() const; |
| 19909 | virtual uint oper_input_base() const { return 2; } |
| 19910 | public: |
| 19911 | orI_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19912 | virtual uint size_of() const { return sizeof(orI_mem_rReg_0Node); } |
| 19913 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19914 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19915 | static const Pipeline *pipeline_class(); |
| 19916 | virtual const Pipeline *pipeline() const; |
| 19917 | virtual const MachOper *memory_operand() const; |
| 19918 | #ifndef PRODUCT |
| 19919 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19920 | virtual const char *Name() const { return "orI_mem_rReg_0";} |
| 19921 | #endif |
| 19922 | }; |
| 19923 | |
| 19924 | class orI_mem_immNode : public MachTypeNode { |
| 19925 | private: |
| 19926 | MachOper *_opnd_array[4]; |
| 19927 | public: |
| 19928 | MachOper *opnd_array(uint operand_index) const { |
| 19929 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19930 | return _opnd_array[operand_index]; |
| 19931 | } |
| 19932 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19933 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19934 | _opnd_array[operand_index] = operand; |
| 19935 | } |
| 19936 | private: |
| 19937 | virtual const RegMask &out_RegMask() const; |
| 19938 | virtual uint rule() const { return orI_mem_imm_rule; } |
| 19939 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19940 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 19941 | virtual int reloc() const; |
| 19942 | virtual uint oper_input_base() const { return 2; } |
| 19943 | public: |
| 19944 | orI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 19945 | virtual uint size_of() const { return sizeof(orI_mem_immNode); } |
| 19946 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19947 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19948 | static const Pipeline *pipeline_class(); |
| 19949 | virtual const Pipeline *pipeline() const; |
| 19950 | virtual const MachOper *memory_operand() const; |
| 19951 | #ifndef PRODUCT |
| 19952 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19953 | virtual const char *Name() const { return "orI_mem_imm";} |
| 19954 | #endif |
| 19955 | }; |
| 19956 | |
| 19957 | class xorI_rRegNode : public MachNode { |
| 19958 | private: |
| 19959 | MachOper *_opnd_array[3]; |
| 19960 | public: |
| 19961 | MachOper *opnd_array(uint operand_index) const { |
| 19962 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19963 | return _opnd_array[operand_index]; |
| 19964 | } |
| 19965 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 19966 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19967 | _opnd_array[operand_index] = operand; |
| 19968 | } |
| 19969 | private: |
| 19970 | const RegMask *_cisc_RegMask; |
| 19971 | virtual const RegMask &out_RegMask() const; |
| 19972 | virtual uint rule() const { return xorI_rReg_rule; } |
| 19973 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 19974 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 19975 | virtual uint two_adr() const { return oper_input_base(); } |
| 19976 | virtual int cisc_operand() const { return 2; } |
| 19977 | virtual MachNode *cisc_version(int offset); |
| 19978 | virtual void use_cisc_RegMask(); |
| 19979 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 19980 | public: |
| 19981 | xorI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 19982 | virtual uint size_of() const { return sizeof(xorI_rRegNode); } |
| 19983 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 19984 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 19985 | static const Pipeline *pipeline_class(); |
| 19986 | virtual const Pipeline *pipeline() const; |
| 19987 | #ifndef PRODUCT |
| 19988 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 19989 | virtual const char *Name() const { return "xorI_rReg";} |
| 19990 | #endif |
| 19991 | }; |
| 19992 | |
| 19993 | class xorI_rReg_im1Node : public MachNode { |
| 19994 | private: |
| 19995 | MachOper *_opnd_array[3]; |
| 19996 | public: |
| 19997 | MachOper *opnd_array(uint operand_index) const { |
| 19998 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 19999 | return _opnd_array[operand_index]; |
| 20000 | } |
| 20001 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20002 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20003 | _opnd_array[operand_index] = operand; |
| 20004 | } |
| 20005 | private: |
| 20006 | virtual const RegMask &out_RegMask() const; |
| 20007 | virtual uint rule() const { return xorI_rReg_im1_rule; } |
| 20008 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20009 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 20010 | virtual uint two_adr() const { return oper_input_base(); } |
| 20011 | public: |
| 20012 | xorI_rReg_im1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 20013 | virtual uint size_of() const { return sizeof(xorI_rReg_im1Node); } |
| 20014 | static const Pipeline *pipeline_class(); |
| 20015 | virtual const Pipeline *pipeline() const; |
| 20016 | #ifndef PRODUCT |
| 20017 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20018 | virtual const char *Name() const { return "xorI_rReg_im1";} |
| 20019 | #endif |
| 20020 | }; |
| 20021 | |
| 20022 | class xorI_rReg_immNode : public MachNode { |
| 20023 | private: |
| 20024 | MachOper *_opnd_array[3]; |
| 20025 | public: |
| 20026 | MachOper *opnd_array(uint operand_index) const { |
| 20027 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20028 | return _opnd_array[operand_index]; |
| 20029 | } |
| 20030 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20032 | _opnd_array[operand_index] = operand; |
| 20033 | } |
| 20034 | private: |
| 20035 | virtual const RegMask &out_RegMask() const; |
| 20036 | virtual uint rule() const { return xorI_rReg_imm_rule; } |
| 20037 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20038 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 20039 | virtual uint two_adr() const { return oper_input_base(); } |
| 20040 | public: |
| 20041 | xorI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 20042 | virtual uint size_of() const { return sizeof(xorI_rReg_immNode); } |
| 20043 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20044 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20045 | static const Pipeline *pipeline_class(); |
| 20046 | virtual const Pipeline *pipeline() const; |
| 20047 | #ifndef PRODUCT |
| 20048 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20049 | virtual const char *Name() const { return "xorI_rReg_imm";} |
| 20050 | #endif |
| 20051 | }; |
| 20052 | |
| 20053 | class xorI_rReg_memNode : public MachNode { |
| 20054 | private: |
| 20055 | MachOper *_opnd_array[3]; |
| 20056 | public: |
| 20057 | MachOper *opnd_array(uint operand_index) const { |
| 20058 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20059 | return _opnd_array[operand_index]; |
| 20060 | } |
| 20061 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20063 | _opnd_array[operand_index] = operand; |
| 20064 | } |
| 20065 | private: |
| 20066 | virtual const RegMask &out_RegMask() const; |
| 20067 | virtual uint rule() const { return xorI_rReg_mem_rule; } |
| 20068 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20069 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 20070 | virtual uint two_adr() const { return oper_input_base(); } |
| 20071 | virtual int reloc() const; |
| 20072 | virtual uint oper_input_base() const { return 2; } |
| 20073 | public: |
| 20074 | xorI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 20075 | virtual uint size_of() const { return sizeof(xorI_rReg_memNode); } |
| 20076 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20077 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20078 | static const Pipeline *pipeline_class(); |
| 20079 | virtual const Pipeline *pipeline() const; |
| 20080 | virtual const MachOper *memory_operand() const; |
| 20081 | #ifndef PRODUCT |
| 20082 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20083 | virtual const char *Name() const { return "xorI_rReg_mem";} |
| 20084 | #endif |
| 20085 | }; |
| 20086 | |
| 20087 | class xorI_rReg_mem_0Node : public MachNode { |
| 20088 | private: |
| 20089 | MachOper *_opnd_array[3]; |
| 20090 | public: |
| 20091 | MachOper *opnd_array(uint operand_index) const { |
| 20092 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20093 | return _opnd_array[operand_index]; |
| 20094 | } |
| 20095 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20096 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20097 | _opnd_array[operand_index] = operand; |
| 20098 | } |
| 20099 | private: |
| 20100 | virtual const RegMask &out_RegMask() const; |
| 20101 | virtual uint rule() const { return xorI_rReg_mem_0_rule; } |
| 20102 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20103 | virtual int ideal_Opcode() const { return Op_XorI; } |
| 20104 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 20105 | virtual int reloc() const; |
| 20106 | virtual uint oper_input_base() const { return 2; } |
| 20107 | public: |
| 20108 | xorI_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20109 | virtual uint size_of() const { return sizeof(xorI_rReg_mem_0Node); } |
| 20110 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20111 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20112 | static const Pipeline *pipeline_class(); |
| 20113 | virtual const Pipeline *pipeline() const; |
| 20114 | virtual const MachOper *memory_operand() const; |
| 20115 | #ifndef PRODUCT |
| 20116 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20117 | virtual const char *Name() const { return "xorI_rReg_mem_0";} |
| 20118 | #endif |
| 20119 | }; |
| 20120 | |
| 20121 | class xorB_mem_rRegNode : public MachTypeNode { |
| 20122 | private: |
| 20123 | MachOper *_opnd_array[4]; |
| 20124 | public: |
| 20125 | MachOper *opnd_array(uint operand_index) const { |
| 20126 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20127 | return _opnd_array[operand_index]; |
| 20128 | } |
| 20129 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20130 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20131 | _opnd_array[operand_index] = operand; |
| 20132 | } |
| 20133 | private: |
| 20134 | virtual const RegMask &out_RegMask() const; |
| 20135 | virtual uint rule() const { return xorB_mem_rReg_rule; } |
| 20136 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20137 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 20138 | virtual int reloc() const; |
| 20139 | virtual uint oper_input_base() const { return 2; } |
| 20140 | public: |
| 20141 | xorB_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20142 | virtual uint size_of() const { return sizeof(xorB_mem_rRegNode); } |
| 20143 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20144 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20145 | static const Pipeline *pipeline_class(); |
| 20146 | virtual const Pipeline *pipeline() const; |
| 20147 | virtual const MachOper *memory_operand() const; |
| 20148 | #ifndef PRODUCT |
| 20149 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20150 | virtual const char *Name() const { return "xorB_mem_rReg";} |
| 20151 | #endif |
| 20152 | }; |
| 20153 | |
| 20154 | class xorB_mem_rReg_0Node : public MachTypeNode { |
| 20155 | private: |
| 20156 | MachOper *_opnd_array[4]; |
| 20157 | public: |
| 20158 | MachOper *opnd_array(uint operand_index) const { |
| 20159 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20160 | return _opnd_array[operand_index]; |
| 20161 | } |
| 20162 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20163 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20164 | _opnd_array[operand_index] = operand; |
| 20165 | } |
| 20166 | private: |
| 20167 | virtual const RegMask &out_RegMask() const; |
| 20168 | virtual uint rule() const { return xorB_mem_rReg_0_rule; } |
| 20169 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20170 | virtual int ideal_Opcode() const { return Op_StoreB; } |
| 20171 | virtual int reloc() const; |
| 20172 | virtual uint oper_input_base() const { return 2; } |
| 20173 | public: |
| 20174 | xorB_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20175 | virtual uint size_of() const { return sizeof(xorB_mem_rReg_0Node); } |
| 20176 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20177 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20178 | static const Pipeline *pipeline_class(); |
| 20179 | virtual const Pipeline *pipeline() const; |
| 20180 | virtual const MachOper *memory_operand() const; |
| 20181 | #ifndef PRODUCT |
| 20182 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20183 | virtual const char *Name() const { return "xorB_mem_rReg_0";} |
| 20184 | #endif |
| 20185 | }; |
| 20186 | |
| 20187 | class xorI_mem_rRegNode : public MachTypeNode { |
| 20188 | private: |
| 20189 | MachOper *_opnd_array[4]; |
| 20190 | public: |
| 20191 | MachOper *opnd_array(uint operand_index) const { |
| 20192 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20193 | return _opnd_array[operand_index]; |
| 20194 | } |
| 20195 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20196 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20197 | _opnd_array[operand_index] = operand; |
| 20198 | } |
| 20199 | private: |
| 20200 | virtual const RegMask &out_RegMask() const; |
| 20201 | virtual uint rule() const { return xorI_mem_rReg_rule; } |
| 20202 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20203 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 20204 | virtual int reloc() const; |
| 20205 | virtual uint oper_input_base() const { return 2; } |
| 20206 | public: |
| 20207 | xorI_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20208 | virtual uint size_of() const { return sizeof(xorI_mem_rRegNode); } |
| 20209 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20210 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20211 | static const Pipeline *pipeline_class(); |
| 20212 | virtual const Pipeline *pipeline() const; |
| 20213 | virtual const MachOper *memory_operand() const; |
| 20214 | #ifndef PRODUCT |
| 20215 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20216 | virtual const char *Name() const { return "xorI_mem_rReg";} |
| 20217 | #endif |
| 20218 | }; |
| 20219 | |
| 20220 | class xorI_mem_rReg_0Node : public MachTypeNode { |
| 20221 | private: |
| 20222 | MachOper *_opnd_array[4]; |
| 20223 | public: |
| 20224 | MachOper *opnd_array(uint operand_index) const { |
| 20225 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20226 | return _opnd_array[operand_index]; |
| 20227 | } |
| 20228 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20229 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20230 | _opnd_array[operand_index] = operand; |
| 20231 | } |
| 20232 | private: |
| 20233 | virtual const RegMask &out_RegMask() const; |
| 20234 | virtual uint rule() const { return xorI_mem_rReg_0_rule; } |
| 20235 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20236 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 20237 | virtual int reloc() const; |
| 20238 | virtual uint oper_input_base() const { return 2; } |
| 20239 | public: |
| 20240 | xorI_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20241 | virtual uint size_of() const { return sizeof(xorI_mem_rReg_0Node); } |
| 20242 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20243 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20244 | static const Pipeline *pipeline_class(); |
| 20245 | virtual const Pipeline *pipeline() const; |
| 20246 | virtual const MachOper *memory_operand() const; |
| 20247 | #ifndef PRODUCT |
| 20248 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20249 | virtual const char *Name() const { return "xorI_mem_rReg_0";} |
| 20250 | #endif |
| 20251 | }; |
| 20252 | |
| 20253 | class xorI_mem_immNode : public MachTypeNode { |
| 20254 | private: |
| 20255 | MachOper *_opnd_array[4]; |
| 20256 | public: |
| 20257 | MachOper *opnd_array(uint operand_index) const { |
| 20258 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20259 | return _opnd_array[operand_index]; |
| 20260 | } |
| 20261 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20262 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20263 | _opnd_array[operand_index] = operand; |
| 20264 | } |
| 20265 | private: |
| 20266 | virtual const RegMask &out_RegMask() const; |
| 20267 | virtual uint rule() const { return xorI_mem_imm_rule; } |
| 20268 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20269 | virtual int ideal_Opcode() const { return Op_StoreI; } |
| 20270 | virtual int reloc() const; |
| 20271 | virtual uint oper_input_base() const { return 2; } |
| 20272 | public: |
| 20273 | xorI_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20274 | virtual uint size_of() const { return sizeof(xorI_mem_immNode); } |
| 20275 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20276 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20277 | static const Pipeline *pipeline_class(); |
| 20278 | virtual const Pipeline *pipeline() const; |
| 20279 | virtual const MachOper *memory_operand() const; |
| 20280 | #ifndef PRODUCT |
| 20281 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20282 | virtual const char *Name() const { return "xorI_mem_imm";} |
| 20283 | #endif |
| 20284 | }; |
| 20285 | |
| 20286 | class andL_rRegNode : public MachNode { |
| 20287 | private: |
| 20288 | MachOper *_opnd_array[3]; |
| 20289 | public: |
| 20290 | MachOper *opnd_array(uint operand_index) const { |
| 20291 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20292 | return _opnd_array[operand_index]; |
| 20293 | } |
| 20294 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20295 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20296 | _opnd_array[operand_index] = operand; |
| 20297 | } |
| 20298 | private: |
| 20299 | const RegMask *_cisc_RegMask; |
| 20300 | virtual const RegMask &out_RegMask() const; |
| 20301 | virtual uint rule() const { return andL_rReg_rule; } |
| 20302 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20303 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20304 | virtual uint two_adr() const { return oper_input_base(); } |
| 20305 | virtual int cisc_operand() const { return 2; } |
| 20306 | virtual MachNode *cisc_version(int offset); |
| 20307 | virtual void use_cisc_RegMask(); |
| 20308 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 20309 | public: |
| 20310 | andL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 20311 | virtual uint size_of() const { return sizeof(andL_rRegNode); } |
| 20312 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20313 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20314 | static const Pipeline *pipeline_class(); |
| 20315 | virtual const Pipeline *pipeline() const; |
| 20316 | #ifndef PRODUCT |
| 20317 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20318 | virtual const char *Name() const { return "andL_rReg";} |
| 20319 | #endif |
| 20320 | }; |
| 20321 | |
| 20322 | class andL_rReg_imm255Node : public MachNode { |
| 20323 | private: |
| 20324 | MachOper *_opnd_array[3]; |
| 20325 | public: |
| 20326 | MachOper *opnd_array(uint operand_index) const { |
| 20327 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20328 | return _opnd_array[operand_index]; |
| 20329 | } |
| 20330 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20331 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20332 | _opnd_array[operand_index] = operand; |
| 20333 | } |
| 20334 | private: |
| 20335 | virtual const RegMask &out_RegMask() const; |
| 20336 | virtual uint rule() const { return andL_rReg_imm255_rule; } |
| 20337 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20338 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20339 | virtual uint two_adr() const { return oper_input_base(); } |
| 20340 | public: |
| 20341 | andL_rReg_imm255Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 20342 | virtual uint size_of() const { return sizeof(andL_rReg_imm255Node); } |
| 20343 | static const Pipeline *pipeline_class(); |
| 20344 | virtual const Pipeline *pipeline() const; |
| 20345 | #ifndef PRODUCT |
| 20346 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20347 | virtual const char *Name() const { return "andL_rReg_imm255";} |
| 20348 | #endif |
| 20349 | }; |
| 20350 | |
| 20351 | class andL_rReg_imm65535Node : public MachNode { |
| 20352 | private: |
| 20353 | MachOper *_opnd_array[3]; |
| 20354 | public: |
| 20355 | MachOper *opnd_array(uint operand_index) const { |
| 20356 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20357 | return _opnd_array[operand_index]; |
| 20358 | } |
| 20359 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20361 | _opnd_array[operand_index] = operand; |
| 20362 | } |
| 20363 | private: |
| 20364 | virtual const RegMask &out_RegMask() const; |
| 20365 | virtual uint rule() const { return andL_rReg_imm65535_rule; } |
| 20366 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20367 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20368 | virtual uint two_adr() const { return oper_input_base(); } |
| 20369 | public: |
| 20370 | andL_rReg_imm65535Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 20371 | virtual uint size_of() const { return sizeof(andL_rReg_imm65535Node); } |
| 20372 | static const Pipeline *pipeline_class(); |
| 20373 | virtual const Pipeline *pipeline() const; |
| 20374 | #ifndef PRODUCT |
| 20375 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20376 | virtual const char *Name() const { return "andL_rReg_imm65535";} |
| 20377 | #endif |
| 20378 | }; |
| 20379 | |
| 20380 | class andL_rReg_immNode : public MachNode { |
| 20381 | private: |
| 20382 | MachOper *_opnd_array[3]; |
| 20383 | public: |
| 20384 | MachOper *opnd_array(uint operand_index) const { |
| 20385 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20386 | return _opnd_array[operand_index]; |
| 20387 | } |
| 20388 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20389 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20390 | _opnd_array[operand_index] = operand; |
| 20391 | } |
| 20392 | private: |
| 20393 | virtual const RegMask &out_RegMask() const; |
| 20394 | virtual uint rule() const { return andL_rReg_imm_rule; } |
| 20395 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20396 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20397 | virtual uint two_adr() const { return oper_input_base(); } |
| 20398 | public: |
| 20399 | andL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 20400 | virtual uint size_of() const { return sizeof(andL_rReg_immNode); } |
| 20401 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20402 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20403 | static const Pipeline *pipeline_class(); |
| 20404 | virtual const Pipeline *pipeline() const; |
| 20405 | #ifndef PRODUCT |
| 20406 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20407 | virtual const char *Name() const { return "andL_rReg_imm";} |
| 20408 | #endif |
| 20409 | }; |
| 20410 | |
| 20411 | class andL_rReg_memNode : public MachNode { |
| 20412 | private: |
| 20413 | MachOper *_opnd_array[3]; |
| 20414 | public: |
| 20415 | MachOper *opnd_array(uint operand_index) const { |
| 20416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20417 | return _opnd_array[operand_index]; |
| 20418 | } |
| 20419 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20420 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20421 | _opnd_array[operand_index] = operand; |
| 20422 | } |
| 20423 | private: |
| 20424 | virtual const RegMask &out_RegMask() const; |
| 20425 | virtual uint rule() const { return andL_rReg_mem_rule; } |
| 20426 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20427 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20428 | virtual uint two_adr() const { return oper_input_base(); } |
| 20429 | virtual int reloc() const; |
| 20430 | virtual uint oper_input_base() const { return 2; } |
| 20431 | public: |
| 20432 | andL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 20433 | virtual uint size_of() const { return sizeof(andL_rReg_memNode); } |
| 20434 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20435 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20436 | static const Pipeline *pipeline_class(); |
| 20437 | virtual const Pipeline *pipeline() const; |
| 20438 | virtual const MachOper *memory_operand() const; |
| 20439 | #ifndef PRODUCT |
| 20440 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20441 | virtual const char *Name() const { return "andL_rReg_mem";} |
| 20442 | #endif |
| 20443 | }; |
| 20444 | |
| 20445 | class andL_rReg_mem_0Node : public MachNode { |
| 20446 | private: |
| 20447 | MachOper *_opnd_array[3]; |
| 20448 | public: |
| 20449 | MachOper *opnd_array(uint operand_index) const { |
| 20450 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20451 | return _opnd_array[operand_index]; |
| 20452 | } |
| 20453 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20454 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20455 | _opnd_array[operand_index] = operand; |
| 20456 | } |
| 20457 | private: |
| 20458 | virtual const RegMask &out_RegMask() const; |
| 20459 | virtual uint rule() const { return andL_rReg_mem_0_rule; } |
| 20460 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20461 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20462 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 20463 | virtual int reloc() const; |
| 20464 | virtual uint oper_input_base() const { return 2; } |
| 20465 | public: |
| 20466 | andL_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20467 | virtual uint size_of() const { return sizeof(andL_rReg_mem_0Node); } |
| 20468 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20469 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20470 | static const Pipeline *pipeline_class(); |
| 20471 | virtual const Pipeline *pipeline() const; |
| 20472 | virtual const MachOper *memory_operand() const; |
| 20473 | #ifndef PRODUCT |
| 20474 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20475 | virtual const char *Name() const { return "andL_rReg_mem_0";} |
| 20476 | #endif |
| 20477 | }; |
| 20478 | |
| 20479 | class andL_mem_rRegNode : public MachTypeNode { |
| 20480 | private: |
| 20481 | MachOper *_opnd_array[4]; |
| 20482 | public: |
| 20483 | MachOper *opnd_array(uint operand_index) const { |
| 20484 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20485 | return _opnd_array[operand_index]; |
| 20486 | } |
| 20487 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20488 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20489 | _opnd_array[operand_index] = operand; |
| 20490 | } |
| 20491 | private: |
| 20492 | virtual const RegMask &out_RegMask() const; |
| 20493 | virtual uint rule() const { return andL_mem_rReg_rule; } |
| 20494 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20495 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 20496 | virtual int reloc() const; |
| 20497 | virtual uint oper_input_base() const { return 2; } |
| 20498 | public: |
| 20499 | andL_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20500 | virtual uint size_of() const { return sizeof(andL_mem_rRegNode); } |
| 20501 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20502 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20503 | static const Pipeline *pipeline_class(); |
| 20504 | virtual const Pipeline *pipeline() const; |
| 20505 | virtual const MachOper *memory_operand() const; |
| 20506 | #ifndef PRODUCT |
| 20507 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20508 | virtual const char *Name() const { return "andL_mem_rReg";} |
| 20509 | #endif |
| 20510 | }; |
| 20511 | |
| 20512 | class andL_mem_rReg_0Node : public MachTypeNode { |
| 20513 | private: |
| 20514 | MachOper *_opnd_array[4]; |
| 20515 | public: |
| 20516 | MachOper *opnd_array(uint operand_index) const { |
| 20517 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20518 | return _opnd_array[operand_index]; |
| 20519 | } |
| 20520 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20521 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20522 | _opnd_array[operand_index] = operand; |
| 20523 | } |
| 20524 | private: |
| 20525 | virtual const RegMask &out_RegMask() const; |
| 20526 | virtual uint rule() const { return andL_mem_rReg_0_rule; } |
| 20527 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20528 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 20529 | virtual int reloc() const; |
| 20530 | virtual uint oper_input_base() const { return 2; } |
| 20531 | public: |
| 20532 | andL_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20533 | virtual uint size_of() const { return sizeof(andL_mem_rReg_0Node); } |
| 20534 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20535 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20536 | static const Pipeline *pipeline_class(); |
| 20537 | virtual const Pipeline *pipeline() const; |
| 20538 | virtual const MachOper *memory_operand() const; |
| 20539 | #ifndef PRODUCT |
| 20540 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20541 | virtual const char *Name() const { return "andL_mem_rReg_0";} |
| 20542 | #endif |
| 20543 | }; |
| 20544 | |
| 20545 | class andL_mem_immNode : public MachTypeNode { |
| 20546 | private: |
| 20547 | MachOper *_opnd_array[4]; |
| 20548 | public: |
| 20549 | MachOper *opnd_array(uint operand_index) const { |
| 20550 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20551 | return _opnd_array[operand_index]; |
| 20552 | } |
| 20553 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20554 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20555 | _opnd_array[operand_index] = operand; |
| 20556 | } |
| 20557 | private: |
| 20558 | virtual const RegMask &out_RegMask() const; |
| 20559 | virtual uint rule() const { return andL_mem_imm_rule; } |
| 20560 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20561 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 20562 | virtual int reloc() const; |
| 20563 | virtual uint oper_input_base() const { return 2; } |
| 20564 | public: |
| 20565 | andL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20566 | virtual uint size_of() const { return sizeof(andL_mem_immNode); } |
| 20567 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20568 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20569 | static const Pipeline *pipeline_class(); |
| 20570 | virtual const Pipeline *pipeline() const; |
| 20571 | virtual const MachOper *memory_operand() const; |
| 20572 | #ifndef PRODUCT |
| 20573 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20574 | virtual const char *Name() const { return "andL_mem_imm";} |
| 20575 | #endif |
| 20576 | }; |
| 20577 | |
| 20578 | class andnL_rReg_rReg_memNode : public MachNode { |
| 20579 | private: |
| 20580 | MachOper *_opnd_array[4]; |
| 20581 | public: |
| 20582 | MachOper *opnd_array(uint operand_index) const { |
| 20583 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20584 | return _opnd_array[operand_index]; |
| 20585 | } |
| 20586 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20587 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20588 | _opnd_array[operand_index] = operand; |
| 20589 | } |
| 20590 | private: |
| 20591 | virtual const RegMask &out_RegMask() const; |
| 20592 | virtual uint rule() const { return andnL_rReg_rReg_mem_rule; } |
| 20593 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20594 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20595 | virtual int reloc() const; |
| 20596 | virtual uint oper_input_base() const { return 2; } |
| 20597 | public: |
| 20598 | andnL_rReg_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 20599 | virtual uint size_of() const { return sizeof(andnL_rReg_rReg_memNode); } |
| 20600 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20601 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20602 | static const Pipeline *pipeline_class(); |
| 20603 | virtual const Pipeline *pipeline() const; |
| 20604 | virtual const MachOper *memory_operand() const; |
| 20605 | #ifndef PRODUCT |
| 20606 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20607 | virtual const char *Name() const { return "andnL_rReg_rReg_mem";} |
| 20608 | #endif |
| 20609 | }; |
| 20610 | |
| 20611 | class andnL_rReg_rReg_mem_0Node : public MachNode { |
| 20612 | private: |
| 20613 | MachOper *_opnd_array[4]; |
| 20614 | public: |
| 20615 | MachOper *opnd_array(uint operand_index) const { |
| 20616 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20617 | return _opnd_array[operand_index]; |
| 20618 | } |
| 20619 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20620 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20621 | _opnd_array[operand_index] = operand; |
| 20622 | } |
| 20623 | private: |
| 20624 | virtual const RegMask &out_RegMask() const; |
| 20625 | virtual uint rule() const { return andnL_rReg_rReg_mem_0_rule; } |
| 20626 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20627 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20628 | virtual int reloc() const; |
| 20629 | virtual uint oper_input_base() const { return 2; } |
| 20630 | public: |
| 20631 | andnL_rReg_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 20632 | virtual uint size_of() const { return sizeof(andnL_rReg_rReg_mem_0Node); } |
| 20633 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20634 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20635 | static const Pipeline *pipeline_class(); |
| 20636 | virtual const Pipeline *pipeline() const; |
| 20637 | virtual const MachOper *memory_operand() const; |
| 20638 | #ifndef PRODUCT |
| 20639 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20640 | virtual const char *Name() const { return "andnL_rReg_rReg_mem_0";} |
| 20641 | #endif |
| 20642 | }; |
| 20643 | |
| 20644 | class andnL_rReg_rReg_rRegNode : public MachNode { |
| 20645 | private: |
| 20646 | MachOper *_opnd_array[4]; |
| 20647 | public: |
| 20648 | MachOper *opnd_array(uint operand_index) const { |
| 20649 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20650 | return _opnd_array[operand_index]; |
| 20651 | } |
| 20652 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20653 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20654 | _opnd_array[operand_index] = operand; |
| 20655 | } |
| 20656 | private: |
| 20657 | const RegMask *_cisc_RegMask; |
| 20658 | virtual const RegMask &out_RegMask() const; |
| 20659 | virtual uint rule() const { return andnL_rReg_rReg_rReg_rule; } |
| 20660 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20661 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20662 | virtual int cisc_operand() const { return 3; } |
| 20663 | virtual MachNode *cisc_version(int offset); |
| 20664 | virtual void use_cisc_RegMask(); |
| 20665 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 20666 | public: |
| 20667 | andnL_rReg_rReg_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 20668 | virtual uint size_of() const { return sizeof(andnL_rReg_rReg_rRegNode); } |
| 20669 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20670 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20671 | static const Pipeline *pipeline_class(); |
| 20672 | virtual const Pipeline *pipeline() const; |
| 20673 | #ifndef PRODUCT |
| 20674 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20675 | virtual const char *Name() const { return "andnL_rReg_rReg_rReg";} |
| 20676 | #endif |
| 20677 | }; |
| 20678 | |
| 20679 | class andnL_rReg_rReg_rReg_0Node : public MachNode { |
| 20680 | private: |
| 20681 | MachOper *_opnd_array[4]; |
| 20682 | public: |
| 20683 | MachOper *opnd_array(uint operand_index) const { |
| 20684 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20685 | return _opnd_array[operand_index]; |
| 20686 | } |
| 20687 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20688 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20689 | _opnd_array[operand_index] = operand; |
| 20690 | } |
| 20691 | private: |
| 20692 | const RegMask *_cisc_RegMask; |
| 20693 | virtual const RegMask &out_RegMask() const; |
| 20694 | virtual uint rule() const { return andnL_rReg_rReg_rReg_0_rule; } |
| 20695 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20696 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20697 | virtual int cisc_operand() const { return 1; } |
| 20698 | virtual MachNode *cisc_version(int offset); |
| 20699 | virtual void use_cisc_RegMask(); |
| 20700 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 20701 | public: |
| 20702 | andnL_rReg_rReg_rReg_0Node() { _cisc_RegMask = NULL; _num_opnds = 4; _opnds = _opnd_array; } |
| 20703 | virtual uint size_of() const { return sizeof(andnL_rReg_rReg_rReg_0Node); } |
| 20704 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20705 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20706 | static const Pipeline *pipeline_class(); |
| 20707 | virtual const Pipeline *pipeline() const; |
| 20708 | #ifndef PRODUCT |
| 20709 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20710 | virtual const char *Name() const { return "andnL_rReg_rReg_rReg_0";} |
| 20711 | #endif |
| 20712 | }; |
| 20713 | |
| 20714 | class blsiL_rReg_rRegNode : public MachNode { |
| 20715 | private: |
| 20716 | MachOper *_opnd_array[4]; |
| 20717 | public: |
| 20718 | MachOper *opnd_array(uint operand_index) const { |
| 20719 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20720 | return _opnd_array[operand_index]; |
| 20721 | } |
| 20722 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20723 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20724 | _opnd_array[operand_index] = operand; |
| 20725 | } |
| 20726 | private: |
| 20727 | virtual const RegMask &out_RegMask() const; |
| 20728 | virtual uint rule() const { return blsiL_rReg_rReg_rule; } |
| 20729 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20730 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20731 | public: |
| 20732 | blsiL_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20733 | virtual uint size_of() const { return sizeof(blsiL_rReg_rRegNode); } |
| 20734 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20735 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20736 | static const Pipeline *pipeline_class(); |
| 20737 | virtual const Pipeline *pipeline() const; |
| 20738 | #ifndef PRODUCT |
| 20739 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20740 | virtual const char *Name() const { return "blsiL_rReg_rReg";} |
| 20741 | #endif |
| 20742 | }; |
| 20743 | |
| 20744 | class blsiL_rReg_rReg_0Node : public MachNode { |
| 20745 | private: |
| 20746 | MachOper *_opnd_array[4]; |
| 20747 | public: |
| 20748 | MachOper *opnd_array(uint operand_index) const { |
| 20749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20750 | return _opnd_array[operand_index]; |
| 20751 | } |
| 20752 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20753 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20754 | _opnd_array[operand_index] = operand; |
| 20755 | } |
| 20756 | private: |
| 20757 | virtual const RegMask &out_RegMask() const; |
| 20758 | virtual uint rule() const { return blsiL_rReg_rReg_0_rule; } |
| 20759 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20760 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20761 | public: |
| 20762 | blsiL_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20763 | virtual uint size_of() const { return sizeof(blsiL_rReg_rReg_0Node); } |
| 20764 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20765 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20766 | static const Pipeline *pipeline_class(); |
| 20767 | virtual const Pipeline *pipeline() const; |
| 20768 | #ifndef PRODUCT |
| 20769 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20770 | virtual const char *Name() const { return "blsiL_rReg_rReg_0";} |
| 20771 | #endif |
| 20772 | }; |
| 20773 | |
| 20774 | class blsiL_rReg_memNode : public MachNode { |
| 20775 | private: |
| 20776 | MachOper *_opnd_array[4]; |
| 20777 | public: |
| 20778 | MachOper *opnd_array(uint operand_index) const { |
| 20779 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20780 | return _opnd_array[operand_index]; |
| 20781 | } |
| 20782 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20783 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20784 | _opnd_array[operand_index] = operand; |
| 20785 | } |
| 20786 | private: |
| 20787 | virtual const RegMask &out_RegMask() const; |
| 20788 | virtual uint rule() const { return blsiL_rReg_mem_rule; } |
| 20789 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20790 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20791 | virtual int reloc() const; |
| 20792 | virtual uint oper_input_base() const { return 2; } |
| 20793 | public: |
| 20794 | blsiL_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20795 | virtual uint size_of() const { return sizeof(blsiL_rReg_memNode); } |
| 20796 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20797 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20798 | static const Pipeline *pipeline_class(); |
| 20799 | virtual const Pipeline *pipeline() const; |
| 20800 | virtual const MachOper *memory_operand() const; |
| 20801 | #ifndef PRODUCT |
| 20802 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20803 | virtual const char *Name() const { return "blsiL_rReg_mem";} |
| 20804 | #endif |
| 20805 | }; |
| 20806 | |
| 20807 | class blsiL_rReg_mem_0Node : public MachNode { |
| 20808 | private: |
| 20809 | MachOper *_opnd_array[4]; |
| 20810 | public: |
| 20811 | MachOper *opnd_array(uint operand_index) const { |
| 20812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20813 | return _opnd_array[operand_index]; |
| 20814 | } |
| 20815 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20816 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20817 | _opnd_array[operand_index] = operand; |
| 20818 | } |
| 20819 | private: |
| 20820 | virtual const RegMask &out_RegMask() const; |
| 20821 | virtual uint rule() const { return blsiL_rReg_mem_0_rule; } |
| 20822 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20823 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20824 | virtual int reloc() const; |
| 20825 | virtual uint oper_input_base() const { return 2; } |
| 20826 | public: |
| 20827 | blsiL_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20828 | virtual uint size_of() const { return sizeof(blsiL_rReg_mem_0Node); } |
| 20829 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20830 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20831 | static const Pipeline *pipeline_class(); |
| 20832 | virtual const Pipeline *pipeline() const; |
| 20833 | virtual const MachOper *memory_operand() const; |
| 20834 | #ifndef PRODUCT |
| 20835 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20836 | virtual const char *Name() const { return "blsiL_rReg_mem_0";} |
| 20837 | #endif |
| 20838 | }; |
| 20839 | |
| 20840 | class blsmskL_rReg_memNode : public MachNode { |
| 20841 | private: |
| 20842 | MachOper *_opnd_array[4]; |
| 20843 | public: |
| 20844 | MachOper *opnd_array(uint operand_index) const { |
| 20845 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20846 | return _opnd_array[operand_index]; |
| 20847 | } |
| 20848 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20849 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20850 | _opnd_array[operand_index] = operand; |
| 20851 | } |
| 20852 | private: |
| 20853 | virtual const RegMask &out_RegMask() const; |
| 20854 | virtual uint rule() const { return blsmskL_rReg_mem_rule; } |
| 20855 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20856 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 20857 | virtual int reloc() const; |
| 20858 | virtual uint oper_input_base() const { return 2; } |
| 20859 | public: |
| 20860 | blsmskL_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20861 | virtual uint size_of() const { return sizeof(blsmskL_rReg_memNode); } |
| 20862 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20863 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20864 | static const Pipeline *pipeline_class(); |
| 20865 | virtual const Pipeline *pipeline() const; |
| 20866 | virtual const MachOper *memory_operand() const; |
| 20867 | #ifndef PRODUCT |
| 20868 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20869 | virtual const char *Name() const { return "blsmskL_rReg_mem";} |
| 20870 | #endif |
| 20871 | }; |
| 20872 | |
| 20873 | class blsmskL_rReg_mem_0Node : public MachNode { |
| 20874 | private: |
| 20875 | MachOper *_opnd_array[4]; |
| 20876 | public: |
| 20877 | MachOper *opnd_array(uint operand_index) const { |
| 20878 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20879 | return _opnd_array[operand_index]; |
| 20880 | } |
| 20881 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20882 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20883 | _opnd_array[operand_index] = operand; |
| 20884 | } |
| 20885 | private: |
| 20886 | virtual const RegMask &out_RegMask() const; |
| 20887 | virtual uint rule() const { return blsmskL_rReg_mem_0_rule; } |
| 20888 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20889 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 20890 | virtual int reloc() const; |
| 20891 | virtual uint oper_input_base() const { return 2; } |
| 20892 | public: |
| 20893 | blsmskL_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 20894 | virtual uint size_of() const { return sizeof(blsmskL_rReg_mem_0Node); } |
| 20895 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20896 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20897 | static const Pipeline *pipeline_class(); |
| 20898 | virtual const Pipeline *pipeline() const; |
| 20899 | virtual const MachOper *memory_operand() const; |
| 20900 | #ifndef PRODUCT |
| 20901 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20902 | virtual const char *Name() const { return "blsmskL_rReg_mem_0";} |
| 20903 | #endif |
| 20904 | }; |
| 20905 | |
| 20906 | class blsmskL_rReg_rRegNode : public MachNode { |
| 20907 | private: |
| 20908 | MachOper *_opnd_array[4]; |
| 20909 | public: |
| 20910 | MachOper *opnd_array(uint operand_index) const { |
| 20911 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20912 | return _opnd_array[operand_index]; |
| 20913 | } |
| 20914 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20915 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20916 | _opnd_array[operand_index] = operand; |
| 20917 | } |
| 20918 | private: |
| 20919 | virtual const RegMask &out_RegMask() const; |
| 20920 | virtual uint rule() const { return blsmskL_rReg_rReg_rule; } |
| 20921 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20922 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 20923 | public: |
| 20924 | blsmskL_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20925 | virtual uint size_of() const { return sizeof(blsmskL_rReg_rRegNode); } |
| 20926 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20927 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20928 | static const Pipeline *pipeline_class(); |
| 20929 | virtual const Pipeline *pipeline() const; |
| 20930 | #ifndef PRODUCT |
| 20931 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20932 | virtual const char *Name() const { return "blsmskL_rReg_rReg";} |
| 20933 | #endif |
| 20934 | }; |
| 20935 | |
| 20936 | class blsmskL_rReg_rReg_0Node : public MachNode { |
| 20937 | private: |
| 20938 | MachOper *_opnd_array[4]; |
| 20939 | public: |
| 20940 | MachOper *opnd_array(uint operand_index) const { |
| 20941 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20942 | return _opnd_array[operand_index]; |
| 20943 | } |
| 20944 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20945 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20946 | _opnd_array[operand_index] = operand; |
| 20947 | } |
| 20948 | private: |
| 20949 | virtual const RegMask &out_RegMask() const; |
| 20950 | virtual uint rule() const { return blsmskL_rReg_rReg_0_rule; } |
| 20951 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20952 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 20953 | public: |
| 20954 | blsmskL_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20955 | virtual uint size_of() const { return sizeof(blsmskL_rReg_rReg_0Node); } |
| 20956 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20957 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20958 | static const Pipeline *pipeline_class(); |
| 20959 | virtual const Pipeline *pipeline() const; |
| 20960 | #ifndef PRODUCT |
| 20961 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20962 | virtual const char *Name() const { return "blsmskL_rReg_rReg_0";} |
| 20963 | #endif |
| 20964 | }; |
| 20965 | |
| 20966 | class blsrL_rReg_rRegNode : public MachNode { |
| 20967 | private: |
| 20968 | MachOper *_opnd_array[4]; |
| 20969 | public: |
| 20970 | MachOper *opnd_array(uint operand_index) const { |
| 20971 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20972 | return _opnd_array[operand_index]; |
| 20973 | } |
| 20974 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 20975 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 20976 | _opnd_array[operand_index] = operand; |
| 20977 | } |
| 20978 | private: |
| 20979 | virtual const RegMask &out_RegMask() const; |
| 20980 | virtual uint rule() const { return blsrL_rReg_rReg_rule; } |
| 20981 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 20982 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 20983 | public: |
| 20984 | blsrL_rReg_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 20985 | virtual uint size_of() const { return sizeof(blsrL_rReg_rRegNode); } |
| 20986 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 20987 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 20988 | static const Pipeline *pipeline_class(); |
| 20989 | virtual const Pipeline *pipeline() const; |
| 20990 | #ifndef PRODUCT |
| 20991 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 20992 | virtual const char *Name() const { return "blsrL_rReg_rReg";} |
| 20993 | #endif |
| 20994 | }; |
| 20995 | |
| 20996 | class blsrL_rReg_rReg_0Node : public MachNode { |
| 20997 | private: |
| 20998 | MachOper *_opnd_array[4]; |
| 20999 | public: |
| 21000 | MachOper *opnd_array(uint operand_index) const { |
| 21001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21002 | return _opnd_array[operand_index]; |
| 21003 | } |
| 21004 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21006 | _opnd_array[operand_index] = operand; |
| 21007 | } |
| 21008 | private: |
| 21009 | virtual const RegMask &out_RegMask() const; |
| 21010 | virtual uint rule() const { return blsrL_rReg_rReg_0_rule; } |
| 21011 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21012 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 21013 | public: |
| 21014 | blsrL_rReg_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21015 | virtual uint size_of() const { return sizeof(blsrL_rReg_rReg_0Node); } |
| 21016 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21017 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21018 | static const Pipeline *pipeline_class(); |
| 21019 | virtual const Pipeline *pipeline() const; |
| 21020 | #ifndef PRODUCT |
| 21021 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21022 | virtual const char *Name() const { return "blsrL_rReg_rReg_0";} |
| 21023 | #endif |
| 21024 | }; |
| 21025 | |
| 21026 | class blsrL_rReg_memNode : public MachNode { |
| 21027 | private: |
| 21028 | MachOper *_opnd_array[4]; |
| 21029 | public: |
| 21030 | MachOper *opnd_array(uint operand_index) const { |
| 21031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21032 | return _opnd_array[operand_index]; |
| 21033 | } |
| 21034 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21036 | _opnd_array[operand_index] = operand; |
| 21037 | } |
| 21038 | private: |
| 21039 | virtual const RegMask &out_RegMask() const; |
| 21040 | virtual uint rule() const { return blsrL_rReg_mem_rule; } |
| 21041 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21042 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 21043 | virtual int reloc() const; |
| 21044 | virtual uint oper_input_base() const { return 2; } |
| 21045 | public: |
| 21046 | blsrL_rReg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 21047 | virtual uint size_of() const { return sizeof(blsrL_rReg_memNode); } |
| 21048 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21049 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21050 | static const Pipeline *pipeline_class(); |
| 21051 | virtual const Pipeline *pipeline() const; |
| 21052 | virtual const MachOper *memory_operand() const; |
| 21053 | #ifndef PRODUCT |
| 21054 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21055 | virtual const char *Name() const { return "blsrL_rReg_mem";} |
| 21056 | #endif |
| 21057 | }; |
| 21058 | |
| 21059 | class blsrL_rReg_mem_0Node : public MachNode { |
| 21060 | private: |
| 21061 | MachOper *_opnd_array[4]; |
| 21062 | public: |
| 21063 | MachOper *opnd_array(uint operand_index) const { |
| 21064 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21065 | return _opnd_array[operand_index]; |
| 21066 | } |
| 21067 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21068 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21069 | _opnd_array[operand_index] = operand; |
| 21070 | } |
| 21071 | private: |
| 21072 | virtual const RegMask &out_RegMask() const; |
| 21073 | virtual uint rule() const { return blsrL_rReg_mem_0_rule; } |
| 21074 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21075 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 21076 | virtual int reloc() const; |
| 21077 | virtual uint oper_input_base() const { return 2; } |
| 21078 | public: |
| 21079 | blsrL_rReg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 21080 | virtual uint size_of() const { return sizeof(blsrL_rReg_mem_0Node); } |
| 21081 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21082 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21083 | static const Pipeline *pipeline_class(); |
| 21084 | virtual const Pipeline *pipeline() const; |
| 21085 | virtual const MachOper *memory_operand() const; |
| 21086 | #ifndef PRODUCT |
| 21087 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21088 | virtual const char *Name() const { return "blsrL_rReg_mem_0";} |
| 21089 | #endif |
| 21090 | }; |
| 21091 | |
| 21092 | class orL_rRegNode : public MachNode { |
| 21093 | private: |
| 21094 | MachOper *_opnd_array[3]; |
| 21095 | public: |
| 21096 | MachOper *opnd_array(uint operand_index) const { |
| 21097 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21098 | return _opnd_array[operand_index]; |
| 21099 | } |
| 21100 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21101 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21102 | _opnd_array[operand_index] = operand; |
| 21103 | } |
| 21104 | private: |
| 21105 | const RegMask *_cisc_RegMask; |
| 21106 | virtual const RegMask &out_RegMask() const; |
| 21107 | virtual uint rule() const { return orL_rReg_rule; } |
| 21108 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21109 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21110 | virtual uint two_adr() const { return oper_input_base(); } |
| 21111 | virtual int cisc_operand() const { return 2; } |
| 21112 | virtual MachNode *cisc_version(int offset); |
| 21113 | virtual void use_cisc_RegMask(); |
| 21114 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 21115 | public: |
| 21116 | orL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 21117 | virtual uint size_of() const { return sizeof(orL_rRegNode); } |
| 21118 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21119 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21120 | static const Pipeline *pipeline_class(); |
| 21121 | virtual const Pipeline *pipeline() const; |
| 21122 | #ifndef PRODUCT |
| 21123 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21124 | virtual const char *Name() const { return "orL_rReg";} |
| 21125 | #endif |
| 21126 | }; |
| 21127 | |
| 21128 | class orL_rReg_castP2XNode : public MachNode { |
| 21129 | private: |
| 21130 | MachOper *_opnd_array[3]; |
| 21131 | public: |
| 21132 | MachOper *opnd_array(uint operand_index) const { |
| 21133 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21134 | return _opnd_array[operand_index]; |
| 21135 | } |
| 21136 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21138 | _opnd_array[operand_index] = operand; |
| 21139 | } |
| 21140 | private: |
| 21141 | virtual const RegMask &out_RegMask() const; |
| 21142 | virtual uint rule() const { return orL_rReg_castP2X_rule; } |
| 21143 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21144 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21145 | virtual uint two_adr() const { return oper_input_base(); } |
| 21146 | public: |
| 21147 | orL_rReg_castP2XNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21148 | virtual uint size_of() const { return sizeof(orL_rReg_castP2XNode); } |
| 21149 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21150 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21151 | static const Pipeline *pipeline_class(); |
| 21152 | virtual const Pipeline *pipeline() const; |
| 21153 | #ifndef PRODUCT |
| 21154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21155 | virtual const char *Name() const { return "orL_rReg_castP2X";} |
| 21156 | #endif |
| 21157 | }; |
| 21158 | |
| 21159 | class orL_rReg_castP2X_0Node : public MachNode { |
| 21160 | private: |
| 21161 | MachOper *_opnd_array[3]; |
| 21162 | public: |
| 21163 | MachOper *opnd_array(uint operand_index) const { |
| 21164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21165 | return _opnd_array[operand_index]; |
| 21166 | } |
| 21167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21169 | _opnd_array[operand_index] = operand; |
| 21170 | } |
| 21171 | private: |
| 21172 | virtual const RegMask &out_RegMask() const; |
| 21173 | virtual uint rule() const { return orL_rReg_castP2X_0_rule; } |
| 21174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21175 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21176 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 21177 | public: |
| 21178 | orL_rReg_castP2X_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21179 | virtual uint size_of() const { return sizeof(orL_rReg_castP2X_0Node); } |
| 21180 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21181 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21182 | static const Pipeline *pipeline_class(); |
| 21183 | virtual const Pipeline *pipeline() const; |
| 21184 | #ifndef PRODUCT |
| 21185 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21186 | virtual const char *Name() const { return "orL_rReg_castP2X_0";} |
| 21187 | #endif |
| 21188 | }; |
| 21189 | |
| 21190 | class orL_rReg_immNode : public MachNode { |
| 21191 | private: |
| 21192 | MachOper *_opnd_array[3]; |
| 21193 | public: |
| 21194 | MachOper *opnd_array(uint operand_index) const { |
| 21195 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21196 | return _opnd_array[operand_index]; |
| 21197 | } |
| 21198 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21200 | _opnd_array[operand_index] = operand; |
| 21201 | } |
| 21202 | private: |
| 21203 | virtual const RegMask &out_RegMask() const; |
| 21204 | virtual uint rule() const { return orL_rReg_imm_rule; } |
| 21205 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21206 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21207 | virtual uint two_adr() const { return oper_input_base(); } |
| 21208 | public: |
| 21209 | orL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21210 | virtual uint size_of() const { return sizeof(orL_rReg_immNode); } |
| 21211 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21212 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21213 | static const Pipeline *pipeline_class(); |
| 21214 | virtual const Pipeline *pipeline() const; |
| 21215 | #ifndef PRODUCT |
| 21216 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21217 | virtual const char *Name() const { return "orL_rReg_imm";} |
| 21218 | #endif |
| 21219 | }; |
| 21220 | |
| 21221 | class orL_rReg_memNode : public MachNode { |
| 21222 | private: |
| 21223 | MachOper *_opnd_array[3]; |
| 21224 | public: |
| 21225 | MachOper *opnd_array(uint operand_index) const { |
| 21226 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21227 | return _opnd_array[operand_index]; |
| 21228 | } |
| 21229 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21231 | _opnd_array[operand_index] = operand; |
| 21232 | } |
| 21233 | private: |
| 21234 | virtual const RegMask &out_RegMask() const; |
| 21235 | virtual uint rule() const { return orL_rReg_mem_rule; } |
| 21236 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21237 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21238 | virtual uint two_adr() const { return oper_input_base(); } |
| 21239 | virtual int reloc() const; |
| 21240 | virtual uint oper_input_base() const { return 2; } |
| 21241 | public: |
| 21242 | orL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 21243 | virtual uint size_of() const { return sizeof(orL_rReg_memNode); } |
| 21244 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21245 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21246 | static const Pipeline *pipeline_class(); |
| 21247 | virtual const Pipeline *pipeline() const; |
| 21248 | virtual const MachOper *memory_operand() const; |
| 21249 | #ifndef PRODUCT |
| 21250 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21251 | virtual const char *Name() const { return "orL_rReg_mem";} |
| 21252 | #endif |
| 21253 | }; |
| 21254 | |
| 21255 | class orL_rReg_mem_0Node : public MachNode { |
| 21256 | private: |
| 21257 | MachOper *_opnd_array[3]; |
| 21258 | public: |
| 21259 | MachOper *opnd_array(uint operand_index) const { |
| 21260 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21261 | return _opnd_array[operand_index]; |
| 21262 | } |
| 21263 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21264 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21265 | _opnd_array[operand_index] = operand; |
| 21266 | } |
| 21267 | private: |
| 21268 | virtual const RegMask &out_RegMask() const; |
| 21269 | virtual uint rule() const { return orL_rReg_mem_0_rule; } |
| 21270 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21271 | virtual int ideal_Opcode() const { return Op_OrL; } |
| 21272 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 21273 | virtual int reloc() const; |
| 21274 | virtual uint oper_input_base() const { return 2; } |
| 21275 | public: |
| 21276 | orL_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 21277 | virtual uint size_of() const { return sizeof(orL_rReg_mem_0Node); } |
| 21278 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21279 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21280 | static const Pipeline *pipeline_class(); |
| 21281 | virtual const Pipeline *pipeline() const; |
| 21282 | virtual const MachOper *memory_operand() const; |
| 21283 | #ifndef PRODUCT |
| 21284 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21285 | virtual const char *Name() const { return "orL_rReg_mem_0";} |
| 21286 | #endif |
| 21287 | }; |
| 21288 | |
| 21289 | class orL_mem_rRegNode : public MachTypeNode { |
| 21290 | private: |
| 21291 | MachOper *_opnd_array[4]; |
| 21292 | public: |
| 21293 | MachOper *opnd_array(uint operand_index) const { |
| 21294 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21295 | return _opnd_array[operand_index]; |
| 21296 | } |
| 21297 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21299 | _opnd_array[operand_index] = operand; |
| 21300 | } |
| 21301 | private: |
| 21302 | virtual const RegMask &out_RegMask() const; |
| 21303 | virtual uint rule() const { return orL_mem_rReg_rule; } |
| 21304 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21305 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21306 | virtual int reloc() const; |
| 21307 | virtual uint oper_input_base() const { return 2; } |
| 21308 | public: |
| 21309 | orL_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21310 | virtual uint size_of() const { return sizeof(orL_mem_rRegNode); } |
| 21311 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21312 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21313 | static const Pipeline *pipeline_class(); |
| 21314 | virtual const Pipeline *pipeline() const; |
| 21315 | virtual const MachOper *memory_operand() const; |
| 21316 | #ifndef PRODUCT |
| 21317 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21318 | virtual const char *Name() const { return "orL_mem_rReg";} |
| 21319 | #endif |
| 21320 | }; |
| 21321 | |
| 21322 | class orL_mem_rReg_0Node : public MachTypeNode { |
| 21323 | private: |
| 21324 | MachOper *_opnd_array[4]; |
| 21325 | public: |
| 21326 | MachOper *opnd_array(uint operand_index) const { |
| 21327 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21328 | return _opnd_array[operand_index]; |
| 21329 | } |
| 21330 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21331 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21332 | _opnd_array[operand_index] = operand; |
| 21333 | } |
| 21334 | private: |
| 21335 | virtual const RegMask &out_RegMask() const; |
| 21336 | virtual uint rule() const { return orL_mem_rReg_0_rule; } |
| 21337 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21338 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21339 | virtual int reloc() const; |
| 21340 | virtual uint oper_input_base() const { return 2; } |
| 21341 | public: |
| 21342 | orL_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21343 | virtual uint size_of() const { return sizeof(orL_mem_rReg_0Node); } |
| 21344 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21345 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21346 | static const Pipeline *pipeline_class(); |
| 21347 | virtual const Pipeline *pipeline() const; |
| 21348 | virtual const MachOper *memory_operand() const; |
| 21349 | #ifndef PRODUCT |
| 21350 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21351 | virtual const char *Name() const { return "orL_mem_rReg_0";} |
| 21352 | #endif |
| 21353 | }; |
| 21354 | |
| 21355 | class orL_mem_immNode : public MachTypeNode { |
| 21356 | private: |
| 21357 | MachOper *_opnd_array[4]; |
| 21358 | public: |
| 21359 | MachOper *opnd_array(uint operand_index) const { |
| 21360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21361 | return _opnd_array[operand_index]; |
| 21362 | } |
| 21363 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21364 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21365 | _opnd_array[operand_index] = operand; |
| 21366 | } |
| 21367 | private: |
| 21368 | virtual const RegMask &out_RegMask() const; |
| 21369 | virtual uint rule() const { return orL_mem_imm_rule; } |
| 21370 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21371 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21372 | virtual int reloc() const; |
| 21373 | virtual uint oper_input_base() const { return 2; } |
| 21374 | public: |
| 21375 | orL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21376 | virtual uint size_of() const { return sizeof(orL_mem_immNode); } |
| 21377 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21378 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21379 | static const Pipeline *pipeline_class(); |
| 21380 | virtual const Pipeline *pipeline() const; |
| 21381 | virtual const MachOper *memory_operand() const; |
| 21382 | #ifndef PRODUCT |
| 21383 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21384 | virtual const char *Name() const { return "orL_mem_imm";} |
| 21385 | #endif |
| 21386 | }; |
| 21387 | |
| 21388 | class xorL_rRegNode : public MachNode { |
| 21389 | private: |
| 21390 | MachOper *_opnd_array[3]; |
| 21391 | public: |
| 21392 | MachOper *opnd_array(uint operand_index) const { |
| 21393 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21394 | return _opnd_array[operand_index]; |
| 21395 | } |
| 21396 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21397 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21398 | _opnd_array[operand_index] = operand; |
| 21399 | } |
| 21400 | private: |
| 21401 | const RegMask *_cisc_RegMask; |
| 21402 | virtual const RegMask &out_RegMask() const; |
| 21403 | virtual uint rule() const { return xorL_rReg_rule; } |
| 21404 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21405 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 21406 | virtual uint two_adr() const { return oper_input_base(); } |
| 21407 | virtual int cisc_operand() const { return 2; } |
| 21408 | virtual MachNode *cisc_version(int offset); |
| 21409 | virtual void use_cisc_RegMask(); |
| 21410 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 21411 | public: |
| 21412 | xorL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 21413 | virtual uint size_of() const { return sizeof(xorL_rRegNode); } |
| 21414 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21415 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21416 | static const Pipeline *pipeline_class(); |
| 21417 | virtual const Pipeline *pipeline() const; |
| 21418 | #ifndef PRODUCT |
| 21419 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21420 | virtual const char *Name() const { return "xorL_rReg";} |
| 21421 | #endif |
| 21422 | }; |
| 21423 | |
| 21424 | class xorL_rReg_im1Node : public MachNode { |
| 21425 | private: |
| 21426 | MachOper *_opnd_array[3]; |
| 21427 | public: |
| 21428 | MachOper *opnd_array(uint operand_index) const { |
| 21429 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21430 | return _opnd_array[operand_index]; |
| 21431 | } |
| 21432 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21433 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21434 | _opnd_array[operand_index] = operand; |
| 21435 | } |
| 21436 | private: |
| 21437 | virtual const RegMask &out_RegMask() const; |
| 21438 | virtual uint rule() const { return xorL_rReg_im1_rule; } |
| 21439 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21440 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 21441 | virtual uint two_adr() const { return oper_input_base(); } |
| 21442 | public: |
| 21443 | xorL_rReg_im1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21444 | virtual uint size_of() const { return sizeof(xorL_rReg_im1Node); } |
| 21445 | static const Pipeline *pipeline_class(); |
| 21446 | virtual const Pipeline *pipeline() const; |
| 21447 | #ifndef PRODUCT |
| 21448 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21449 | virtual const char *Name() const { return "xorL_rReg_im1";} |
| 21450 | #endif |
| 21451 | }; |
| 21452 | |
| 21453 | class xorL_rReg_immNode : public MachNode { |
| 21454 | private: |
| 21455 | MachOper *_opnd_array[3]; |
| 21456 | public: |
| 21457 | MachOper *opnd_array(uint operand_index) const { |
| 21458 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21459 | return _opnd_array[operand_index]; |
| 21460 | } |
| 21461 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21462 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21463 | _opnd_array[operand_index] = operand; |
| 21464 | } |
| 21465 | private: |
| 21466 | virtual const RegMask &out_RegMask() const; |
| 21467 | virtual uint rule() const { return xorL_rReg_imm_rule; } |
| 21468 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21469 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 21470 | virtual uint two_adr() const { return oper_input_base(); } |
| 21471 | public: |
| 21472 | xorL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21473 | virtual uint size_of() const { return sizeof(xorL_rReg_immNode); } |
| 21474 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21475 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21476 | static const Pipeline *pipeline_class(); |
| 21477 | virtual const Pipeline *pipeline() const; |
| 21478 | #ifndef PRODUCT |
| 21479 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21480 | virtual const char *Name() const { return "xorL_rReg_imm";} |
| 21481 | #endif |
| 21482 | }; |
| 21483 | |
| 21484 | class xorL_rReg_memNode : public MachNode { |
| 21485 | private: |
| 21486 | MachOper *_opnd_array[3]; |
| 21487 | public: |
| 21488 | MachOper *opnd_array(uint operand_index) const { |
| 21489 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21490 | return _opnd_array[operand_index]; |
| 21491 | } |
| 21492 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21493 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21494 | _opnd_array[operand_index] = operand; |
| 21495 | } |
| 21496 | private: |
| 21497 | virtual const RegMask &out_RegMask() const; |
| 21498 | virtual uint rule() const { return xorL_rReg_mem_rule; } |
| 21499 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21500 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 21501 | virtual uint two_adr() const { return oper_input_base(); } |
| 21502 | virtual int reloc() const; |
| 21503 | virtual uint oper_input_base() const { return 2; } |
| 21504 | public: |
| 21505 | xorL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 21506 | virtual uint size_of() const { return sizeof(xorL_rReg_memNode); } |
| 21507 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21508 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21509 | static const Pipeline *pipeline_class(); |
| 21510 | virtual const Pipeline *pipeline() const; |
| 21511 | virtual const MachOper *memory_operand() const; |
| 21512 | #ifndef PRODUCT |
| 21513 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21514 | virtual const char *Name() const { return "xorL_rReg_mem";} |
| 21515 | #endif |
| 21516 | }; |
| 21517 | |
| 21518 | class xorL_rReg_mem_0Node : public MachNode { |
| 21519 | private: |
| 21520 | MachOper *_opnd_array[3]; |
| 21521 | public: |
| 21522 | MachOper *opnd_array(uint operand_index) const { |
| 21523 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21524 | return _opnd_array[operand_index]; |
| 21525 | } |
| 21526 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21527 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21528 | _opnd_array[operand_index] = operand; |
| 21529 | } |
| 21530 | private: |
| 21531 | virtual const RegMask &out_RegMask() const; |
| 21532 | virtual uint rule() const { return xorL_rReg_mem_0_rule; } |
| 21533 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21534 | virtual int ideal_Opcode() const { return Op_XorL; } |
| 21535 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 21536 | virtual int reloc() const; |
| 21537 | virtual uint oper_input_base() const { return 2; } |
| 21538 | public: |
| 21539 | xorL_rReg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 21540 | virtual uint size_of() const { return sizeof(xorL_rReg_mem_0Node); } |
| 21541 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21542 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21543 | static const Pipeline *pipeline_class(); |
| 21544 | virtual const Pipeline *pipeline() const; |
| 21545 | virtual const MachOper *memory_operand() const; |
| 21546 | #ifndef PRODUCT |
| 21547 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21548 | virtual const char *Name() const { return "xorL_rReg_mem_0";} |
| 21549 | #endif |
| 21550 | }; |
| 21551 | |
| 21552 | class xorL_mem_rRegNode : public MachTypeNode { |
| 21553 | private: |
| 21554 | MachOper *_opnd_array[4]; |
| 21555 | public: |
| 21556 | MachOper *opnd_array(uint operand_index) const { |
| 21557 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21558 | return _opnd_array[operand_index]; |
| 21559 | } |
| 21560 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21561 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21562 | _opnd_array[operand_index] = operand; |
| 21563 | } |
| 21564 | private: |
| 21565 | virtual const RegMask &out_RegMask() const; |
| 21566 | virtual uint rule() const { return xorL_mem_rReg_rule; } |
| 21567 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21568 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21569 | virtual int reloc() const; |
| 21570 | virtual uint oper_input_base() const { return 2; } |
| 21571 | public: |
| 21572 | xorL_mem_rRegNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21573 | virtual uint size_of() const { return sizeof(xorL_mem_rRegNode); } |
| 21574 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21575 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21576 | static const Pipeline *pipeline_class(); |
| 21577 | virtual const Pipeline *pipeline() const; |
| 21578 | virtual const MachOper *memory_operand() const; |
| 21579 | #ifndef PRODUCT |
| 21580 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21581 | virtual const char *Name() const { return "xorL_mem_rReg";} |
| 21582 | #endif |
| 21583 | }; |
| 21584 | |
| 21585 | class xorL_mem_rReg_0Node : public MachTypeNode { |
| 21586 | private: |
| 21587 | MachOper *_opnd_array[4]; |
| 21588 | public: |
| 21589 | MachOper *opnd_array(uint operand_index) const { |
| 21590 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21591 | return _opnd_array[operand_index]; |
| 21592 | } |
| 21593 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21594 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21595 | _opnd_array[operand_index] = operand; |
| 21596 | } |
| 21597 | private: |
| 21598 | virtual const RegMask &out_RegMask() const; |
| 21599 | virtual uint rule() const { return xorL_mem_rReg_0_rule; } |
| 21600 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21601 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21602 | virtual int reloc() const; |
| 21603 | virtual uint oper_input_base() const { return 2; } |
| 21604 | public: |
| 21605 | xorL_mem_rReg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21606 | virtual uint size_of() const { return sizeof(xorL_mem_rReg_0Node); } |
| 21607 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21608 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21609 | static const Pipeline *pipeline_class(); |
| 21610 | virtual const Pipeline *pipeline() const; |
| 21611 | virtual const MachOper *memory_operand() const; |
| 21612 | #ifndef PRODUCT |
| 21613 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21614 | virtual const char *Name() const { return "xorL_mem_rReg_0";} |
| 21615 | #endif |
| 21616 | }; |
| 21617 | |
| 21618 | class xorL_mem_immNode : public MachTypeNode { |
| 21619 | private: |
| 21620 | MachOper *_opnd_array[4]; |
| 21621 | public: |
| 21622 | MachOper *opnd_array(uint operand_index) const { |
| 21623 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21624 | return _opnd_array[operand_index]; |
| 21625 | } |
| 21626 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21627 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21628 | _opnd_array[operand_index] = operand; |
| 21629 | } |
| 21630 | private: |
| 21631 | virtual const RegMask &out_RegMask() const; |
| 21632 | virtual uint rule() const { return xorL_mem_imm_rule; } |
| 21633 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21634 | virtual int ideal_Opcode() const { return Op_StoreL; } |
| 21635 | virtual int reloc() const; |
| 21636 | virtual uint oper_input_base() const { return 2; } |
| 21637 | public: |
| 21638 | xorL_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21639 | virtual uint size_of() const { return sizeof(xorL_mem_immNode); } |
| 21640 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21641 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21642 | static const Pipeline *pipeline_class(); |
| 21643 | virtual const Pipeline *pipeline() const; |
| 21644 | virtual const MachOper *memory_operand() const; |
| 21645 | #ifndef PRODUCT |
| 21646 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21647 | virtual const char *Name() const { return "xorL_mem_imm";} |
| 21648 | #endif |
| 21649 | }; |
| 21650 | |
| 21651 | class convI2BNode : public MachNode { |
| 21652 | private: |
| 21653 | MachOper *_opnd_array[2]; |
| 21654 | public: |
| 21655 | MachOper *opnd_array(uint operand_index) const { |
| 21656 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21657 | return _opnd_array[operand_index]; |
| 21658 | } |
| 21659 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21660 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21661 | _opnd_array[operand_index] = operand; |
| 21662 | } |
| 21663 | private: |
| 21664 | virtual const RegMask &out_RegMask() const; |
| 21665 | virtual uint rule() const { return convI2B_rule; } |
| 21666 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21667 | virtual int ideal_Opcode() const { return Op_Conv2B; } |
| 21668 | public: |
| 21669 | convI2BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 21670 | virtual uint size_of() const { return sizeof(convI2BNode); } |
| 21671 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21672 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21673 | static const Pipeline *pipeline_class(); |
| 21674 | virtual const Pipeline *pipeline() const; |
| 21675 | #ifndef PRODUCT |
| 21676 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21677 | virtual const char *Name() const { return "convI2B";} |
| 21678 | #endif |
| 21679 | }; |
| 21680 | |
| 21681 | class convP2BNode : public MachNode { |
| 21682 | private: |
| 21683 | MachOper *_opnd_array[2]; |
| 21684 | public: |
| 21685 | MachOper *opnd_array(uint operand_index) const { |
| 21686 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21687 | return _opnd_array[operand_index]; |
| 21688 | } |
| 21689 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21690 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21691 | _opnd_array[operand_index] = operand; |
| 21692 | } |
| 21693 | private: |
| 21694 | virtual const RegMask &out_RegMask() const; |
| 21695 | virtual uint rule() const { return convP2B_rule; } |
| 21696 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21697 | virtual int ideal_Opcode() const { return Op_Conv2B; } |
| 21698 | public: |
| 21699 | convP2BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 21700 | virtual uint size_of() const { return sizeof(convP2BNode); } |
| 21701 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21702 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21703 | static const Pipeline *pipeline_class(); |
| 21704 | virtual const Pipeline *pipeline() const; |
| 21705 | #ifndef PRODUCT |
| 21706 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21707 | virtual const char *Name() const { return "convP2B";} |
| 21708 | #endif |
| 21709 | }; |
| 21710 | |
| 21711 | class cmpLTMaskNode : public MachNode { |
| 21712 | private: |
| 21713 | MachOper *_opnd_array[3]; |
| 21714 | public: |
| 21715 | MachOper *opnd_array(uint operand_index) const { |
| 21716 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21717 | return _opnd_array[operand_index]; |
| 21718 | } |
| 21719 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21720 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21721 | _opnd_array[operand_index] = operand; |
| 21722 | } |
| 21723 | private: |
| 21724 | virtual const RegMask &out_RegMask() const; |
| 21725 | virtual uint rule() const { return cmpLTMask_rule; } |
| 21726 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21727 | virtual int ideal_Opcode() const { return Op_CmpLTMask; } |
| 21728 | public: |
| 21729 | cmpLTMaskNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21730 | virtual uint size_of() const { return sizeof(cmpLTMaskNode); } |
| 21731 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21732 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21733 | static const Pipeline *pipeline_class(); |
| 21734 | virtual const Pipeline *pipeline() const; |
| 21735 | #ifndef PRODUCT |
| 21736 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21737 | virtual const char *Name() const { return "cmpLTMask";} |
| 21738 | #endif |
| 21739 | }; |
| 21740 | |
| 21741 | class cmpLTMask0Node : public MachNode { |
| 21742 | private: |
| 21743 | MachOper *_opnd_array[3]; |
| 21744 | public: |
| 21745 | MachOper *opnd_array(uint operand_index) const { |
| 21746 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21747 | return _opnd_array[operand_index]; |
| 21748 | } |
| 21749 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21750 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21751 | _opnd_array[operand_index] = operand; |
| 21752 | } |
| 21753 | private: |
| 21754 | virtual const RegMask &out_RegMask() const; |
| 21755 | virtual uint rule() const { return cmpLTMask0_rule; } |
| 21756 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21757 | virtual int ideal_Opcode() const { return Op_CmpLTMask; } |
| 21758 | virtual uint two_adr() const { return oper_input_base(); } |
| 21759 | public: |
| 21760 | cmpLTMask0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 21761 | virtual uint size_of() const { return sizeof(cmpLTMask0Node); } |
| 21762 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21763 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21764 | static const Pipeline *pipeline_class(); |
| 21765 | virtual const Pipeline *pipeline() const; |
| 21766 | #ifndef PRODUCT |
| 21767 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21768 | virtual const char *Name() const { return "cmpLTMask0";} |
| 21769 | #endif |
| 21770 | }; |
| 21771 | |
| 21772 | class cadd_cmpLTMaskNode : public MachNode { |
| 21773 | private: |
| 21774 | MachOper *_opnd_array[6]; |
| 21775 | public: |
| 21776 | MachOper *opnd_array(uint operand_index) const { |
| 21777 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21778 | return _opnd_array[operand_index]; |
| 21779 | } |
| 21780 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21781 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21782 | _opnd_array[operand_index] = operand; |
| 21783 | } |
| 21784 | private: |
| 21785 | virtual const RegMask &out_RegMask() const; |
| 21786 | virtual uint rule() const { return cadd_cmpLTMask_rule; } |
| 21787 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21788 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 21789 | virtual uint two_adr() const { return oper_input_base(); } |
| 21790 | public: |
| 21791 | cadd_cmpLTMaskNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 21792 | virtual uint size_of() const { return sizeof(cadd_cmpLTMaskNode); } |
| 21793 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21794 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21795 | static const Pipeline *pipeline_class(); |
| 21796 | virtual const Pipeline *pipeline() const; |
| 21797 | #ifndef PRODUCT |
| 21798 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21799 | virtual const char *Name() const { return "cadd_cmpLTMask";} |
| 21800 | #endif |
| 21801 | }; |
| 21802 | |
| 21803 | class cadd_cmpLTMask_1Node : public MachNode { |
| 21804 | private: |
| 21805 | MachOper *_opnd_array[6]; |
| 21806 | public: |
| 21807 | MachOper *opnd_array(uint operand_index) const { |
| 21808 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21809 | return _opnd_array[operand_index]; |
| 21810 | } |
| 21811 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21813 | _opnd_array[operand_index] = operand; |
| 21814 | } |
| 21815 | private: |
| 21816 | virtual const RegMask &out_RegMask() const; |
| 21817 | virtual uint rule() const { return cadd_cmpLTMask_1_rule; } |
| 21818 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21819 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 21820 | virtual uint two_adr() const { return oper_input_base(); } |
| 21821 | public: |
| 21822 | cadd_cmpLTMask_1Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 21823 | virtual uint size_of() const { return sizeof(cadd_cmpLTMask_1Node); } |
| 21824 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21825 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21826 | static const Pipeline *pipeline_class(); |
| 21827 | virtual const Pipeline *pipeline() const; |
| 21828 | #ifndef PRODUCT |
| 21829 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21830 | virtual const char *Name() const { return "cadd_cmpLTMask_1";} |
| 21831 | #endif |
| 21832 | }; |
| 21833 | |
| 21834 | class cadd_cmpLTMask_0Node : public MachNode { |
| 21835 | private: |
| 21836 | MachOper *_opnd_array[6]; |
| 21837 | public: |
| 21838 | MachOper *opnd_array(uint operand_index) const { |
| 21839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21840 | return _opnd_array[operand_index]; |
| 21841 | } |
| 21842 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21843 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21844 | _opnd_array[operand_index] = operand; |
| 21845 | } |
| 21846 | private: |
| 21847 | virtual const RegMask &out_RegMask() const; |
| 21848 | virtual uint rule() const { return cadd_cmpLTMask_0_rule; } |
| 21849 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21850 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 21851 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 21852 | public: |
| 21853 | cadd_cmpLTMask_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 21854 | virtual uint size_of() const { return sizeof(cadd_cmpLTMask_0Node); } |
| 21855 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21856 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21857 | static const Pipeline *pipeline_class(); |
| 21858 | virtual const Pipeline *pipeline() const; |
| 21859 | #ifndef PRODUCT |
| 21860 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21861 | virtual const char *Name() const { return "cadd_cmpLTMask_0";} |
| 21862 | #endif |
| 21863 | }; |
| 21864 | |
| 21865 | class cadd_cmpLTMask_2Node : public MachNode { |
| 21866 | private: |
| 21867 | MachOper *_opnd_array[6]; |
| 21868 | public: |
| 21869 | MachOper *opnd_array(uint operand_index) const { |
| 21870 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21871 | return _opnd_array[operand_index]; |
| 21872 | } |
| 21873 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21874 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21875 | _opnd_array[operand_index] = operand; |
| 21876 | } |
| 21877 | private: |
| 21878 | virtual const RegMask &out_RegMask() const; |
| 21879 | virtual uint rule() const { return cadd_cmpLTMask_2_rule; } |
| 21880 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21881 | virtual int ideal_Opcode() const { return Op_AddI; } |
| 21882 | virtual uint two_adr() const { return oper_input_base(); } |
| 21883 | public: |
| 21884 | cadd_cmpLTMask_2Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 21885 | virtual uint size_of() const { return sizeof(cadd_cmpLTMask_2Node); } |
| 21886 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21887 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21888 | static const Pipeline *pipeline_class(); |
| 21889 | virtual const Pipeline *pipeline() const; |
| 21890 | #ifndef PRODUCT |
| 21891 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21892 | virtual const char *Name() const { return "cadd_cmpLTMask_2";} |
| 21893 | #endif |
| 21894 | }; |
| 21895 | |
| 21896 | class and_cmpLTMaskNode : public MachNode { |
| 21897 | private: |
| 21898 | MachOper *_opnd_array[4]; |
| 21899 | public: |
| 21900 | MachOper *opnd_array(uint operand_index) const { |
| 21901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21902 | return _opnd_array[operand_index]; |
| 21903 | } |
| 21904 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21905 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21906 | _opnd_array[operand_index] = operand; |
| 21907 | } |
| 21908 | private: |
| 21909 | virtual const RegMask &out_RegMask() const; |
| 21910 | virtual uint rule() const { return and_cmpLTMask_rule; } |
| 21911 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21912 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 21913 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 21914 | public: |
| 21915 | and_cmpLTMaskNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21916 | virtual uint size_of() const { return sizeof(and_cmpLTMaskNode); } |
| 21917 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21918 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21919 | static const Pipeline *pipeline_class(); |
| 21920 | virtual const Pipeline *pipeline() const; |
| 21921 | #ifndef PRODUCT |
| 21922 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21923 | virtual const char *Name() const { return "and_cmpLTMask";} |
| 21924 | #endif |
| 21925 | }; |
| 21926 | |
| 21927 | class and_cmpLTMask_0Node : public MachNode { |
| 21928 | private: |
| 21929 | MachOper *_opnd_array[4]; |
| 21930 | public: |
| 21931 | MachOper *opnd_array(uint operand_index) const { |
| 21932 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21933 | return _opnd_array[operand_index]; |
| 21934 | } |
| 21935 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21936 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21937 | _opnd_array[operand_index] = operand; |
| 21938 | } |
| 21939 | private: |
| 21940 | virtual const RegMask &out_RegMask() const; |
| 21941 | virtual uint rule() const { return and_cmpLTMask_0_rule; } |
| 21942 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21943 | virtual int ideal_Opcode() const { return Op_AndI; } |
| 21944 | virtual uint two_adr() const { return oper_input_base(); } |
| 21945 | public: |
| 21946 | and_cmpLTMask_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 21947 | virtual uint size_of() const { return sizeof(and_cmpLTMask_0Node); } |
| 21948 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 21949 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 21950 | static const Pipeline *pipeline_class(); |
| 21951 | virtual const Pipeline *pipeline() const; |
| 21952 | #ifndef PRODUCT |
| 21953 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21954 | virtual const char *Name() const { return "and_cmpLTMask_0";} |
| 21955 | #endif |
| 21956 | }; |
| 21957 | |
| 21958 | class cmpF_cc_regNode : public MachNode { |
| 21959 | private: |
| 21960 | MachOper *_opnd_array[3]; |
| 21961 | public: |
| 21962 | MachOper *opnd_array(uint operand_index) const { |
| 21963 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21964 | return _opnd_array[operand_index]; |
| 21965 | } |
| 21966 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 21967 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21968 | _opnd_array[operand_index] = operand; |
| 21969 | } |
| 21970 | private: |
| 21971 | const RegMask *_cisc_RegMask; |
| 21972 | virtual const RegMask &out_RegMask() const; |
| 21973 | virtual uint rule() const { return cmpF_cc_reg_rule; } |
| 21974 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 21975 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 21976 | virtual int cisc_operand() const { return 2; } |
| 21977 | virtual MachNode *cisc_version(int offset); |
| 21978 | virtual void use_cisc_RegMask(); |
| 21979 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 21980 | public: |
| 21981 | cmpF_cc_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 21982 | virtual uint size_of() const { return sizeof(cmpF_cc_regNode); } |
| 21983 | // Rematerialize cmpF_cc_reg |
| 21984 | static const Pipeline *pipeline_class(); |
| 21985 | virtual const Pipeline *pipeline() const; |
| 21986 | #ifndef PRODUCT |
| 21987 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 21988 | virtual const char *Name() const { return "cmpF_cc_reg";} |
| 21989 | #endif |
| 21990 | }; |
| 21991 | |
| 21992 | class cmpF_cc_reg_CFNode : public MachNode { |
| 21993 | private: |
| 21994 | MachOper *_opnd_array[3]; |
| 21995 | public: |
| 21996 | MachOper *opnd_array(uint operand_index) const { |
| 21997 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 21998 | return _opnd_array[operand_index]; |
| 21999 | } |
| 22000 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22002 | _opnd_array[operand_index] = operand; |
| 22003 | } |
| 22004 | private: |
| 22005 | const RegMask *_cisc_RegMask; |
| 22006 | virtual const RegMask &out_RegMask() const; |
| 22007 | virtual uint rule() const { return cmpF_cc_reg_CF_rule; } |
| 22008 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22009 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 22010 | virtual int cisc_operand() const { return 2; } |
| 22011 | virtual MachNode *cisc_version(int offset); |
| 22012 | virtual void use_cisc_RegMask(); |
| 22013 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22014 | public: |
| 22015 | cmpF_cc_reg_CFNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 22016 | virtual uint size_of() const { return sizeof(cmpF_cc_reg_CFNode); } |
| 22017 | // Rematerialize cmpF_cc_reg_CF |
| 22018 | static const Pipeline *pipeline_class(); |
| 22019 | virtual const Pipeline *pipeline() const; |
| 22020 | #ifndef PRODUCT |
| 22021 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22022 | virtual const char *Name() const { return "cmpF_cc_reg_CF";} |
| 22023 | #endif |
| 22024 | }; |
| 22025 | |
| 22026 | class cmpF_cc_memNode : public MachNode { |
| 22027 | private: |
| 22028 | MachOper *_opnd_array[3]; |
| 22029 | public: |
| 22030 | MachOper *opnd_array(uint operand_index) const { |
| 22031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22032 | return _opnd_array[operand_index]; |
| 22033 | } |
| 22034 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22036 | _opnd_array[operand_index] = operand; |
| 22037 | } |
| 22038 | private: |
| 22039 | virtual const RegMask &out_RegMask() const; |
| 22040 | virtual uint rule() const { return cmpF_cc_mem_rule; } |
| 22041 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22042 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 22043 | virtual int reloc() const; |
| 22044 | virtual uint oper_input_base() const { return 2; } |
| 22045 | public: |
| 22046 | cmpF_cc_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22047 | virtual uint size_of() const { return sizeof(cmpF_cc_memNode); } |
| 22048 | // Rematerialize cmpF_cc_mem |
| 22049 | static const Pipeline *pipeline_class(); |
| 22050 | virtual const Pipeline *pipeline() const; |
| 22051 | virtual const MachOper *memory_operand() const; |
| 22052 | #ifndef PRODUCT |
| 22053 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22054 | virtual const char *Name() const { return "cmpF_cc_mem";} |
| 22055 | #endif |
| 22056 | }; |
| 22057 | |
| 22058 | class cmpF_cc_memCFNode : public MachNode { |
| 22059 | private: |
| 22060 | MachOper *_opnd_array[3]; |
| 22061 | public: |
| 22062 | MachOper *opnd_array(uint operand_index) const { |
| 22063 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22064 | return _opnd_array[operand_index]; |
| 22065 | } |
| 22066 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22067 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22068 | _opnd_array[operand_index] = operand; |
| 22069 | } |
| 22070 | private: |
| 22071 | virtual const RegMask &out_RegMask() const; |
| 22072 | virtual uint rule() const { return cmpF_cc_memCF_rule; } |
| 22073 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22074 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 22075 | virtual int reloc() const; |
| 22076 | virtual uint oper_input_base() const { return 2; } |
| 22077 | public: |
| 22078 | cmpF_cc_memCFNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22079 | virtual uint size_of() const { return sizeof(cmpF_cc_memCFNode); } |
| 22080 | // Rematerialize cmpF_cc_memCF |
| 22081 | static const Pipeline *pipeline_class(); |
| 22082 | virtual const Pipeline *pipeline() const; |
| 22083 | virtual const MachOper *memory_operand() const; |
| 22084 | #ifndef PRODUCT |
| 22085 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22086 | virtual const char *Name() const { return "cmpF_cc_memCF";} |
| 22087 | #endif |
| 22088 | }; |
| 22089 | |
| 22090 | class cmpF_cc_immNode : public MachConstantNode { |
| 22091 | private: |
| 22092 | MachOper *_opnd_array[3]; |
| 22093 | public: |
| 22094 | MachOper *opnd_array(uint operand_index) const { |
| 22095 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22096 | return _opnd_array[operand_index]; |
| 22097 | } |
| 22098 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22099 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22100 | _opnd_array[operand_index] = operand; |
| 22101 | } |
| 22102 | private: |
| 22103 | virtual const RegMask &out_RegMask() const; |
| 22104 | virtual uint rule() const { return cmpF_cc_imm_rule; } |
| 22105 | virtual void eval_constant(Compile* C); |
| 22106 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22107 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 22108 | virtual int reloc() const; |
| 22109 | virtual uint oper_input_base() const { return 1; } |
| 22110 | public: |
| 22111 | cmpF_cc_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22112 | virtual uint size_of() const { return sizeof(cmpF_cc_immNode); } |
| 22113 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22114 | // Rematerialize cmpF_cc_imm |
| 22115 | static const Pipeline *pipeline_class(); |
| 22116 | virtual const Pipeline *pipeline() const; |
| 22117 | #ifndef PRODUCT |
| 22118 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22119 | virtual const char *Name() const { return "cmpF_cc_imm";} |
| 22120 | #endif |
| 22121 | }; |
| 22122 | |
| 22123 | class cmpF_cc_immCFNode : public MachConstantNode { |
| 22124 | private: |
| 22125 | MachOper *_opnd_array[3]; |
| 22126 | public: |
| 22127 | MachOper *opnd_array(uint operand_index) const { |
| 22128 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22129 | return _opnd_array[operand_index]; |
| 22130 | } |
| 22131 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22132 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22133 | _opnd_array[operand_index] = operand; |
| 22134 | } |
| 22135 | private: |
| 22136 | virtual const RegMask &out_RegMask() const; |
| 22137 | virtual uint rule() const { return cmpF_cc_immCF_rule; } |
| 22138 | virtual void eval_constant(Compile* C); |
| 22139 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22140 | virtual int ideal_Opcode() const { return Op_CmpF; } |
| 22141 | virtual int reloc() const; |
| 22142 | virtual uint oper_input_base() const { return 1; } |
| 22143 | public: |
| 22144 | cmpF_cc_immCFNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22145 | virtual uint size_of() const { return sizeof(cmpF_cc_immCFNode); } |
| 22146 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22147 | // Rematerialize cmpF_cc_immCF |
| 22148 | static const Pipeline *pipeline_class(); |
| 22149 | virtual const Pipeline *pipeline() const; |
| 22150 | #ifndef PRODUCT |
| 22151 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22152 | virtual const char *Name() const { return "cmpF_cc_immCF";} |
| 22153 | #endif |
| 22154 | }; |
| 22155 | |
| 22156 | class cmpD_cc_regNode : public MachNode { |
| 22157 | private: |
| 22158 | MachOper *_opnd_array[3]; |
| 22159 | public: |
| 22160 | MachOper *opnd_array(uint operand_index) const { |
| 22161 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22162 | return _opnd_array[operand_index]; |
| 22163 | } |
| 22164 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22165 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22166 | _opnd_array[operand_index] = operand; |
| 22167 | } |
| 22168 | private: |
| 22169 | const RegMask *_cisc_RegMask; |
| 22170 | virtual const RegMask &out_RegMask() const; |
| 22171 | virtual uint rule() const { return cmpD_cc_reg_rule; } |
| 22172 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22173 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22174 | virtual int cisc_operand() const { return 2; } |
| 22175 | virtual MachNode *cisc_version(int offset); |
| 22176 | virtual void use_cisc_RegMask(); |
| 22177 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22178 | public: |
| 22179 | cmpD_cc_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 22180 | virtual uint size_of() const { return sizeof(cmpD_cc_regNode); } |
| 22181 | // Rematerialize cmpD_cc_reg |
| 22182 | static const Pipeline *pipeline_class(); |
| 22183 | virtual const Pipeline *pipeline() const; |
| 22184 | #ifndef PRODUCT |
| 22185 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22186 | virtual const char *Name() const { return "cmpD_cc_reg";} |
| 22187 | #endif |
| 22188 | }; |
| 22189 | |
| 22190 | class cmpD_cc_reg_CFNode : public MachNode { |
| 22191 | private: |
| 22192 | MachOper *_opnd_array[3]; |
| 22193 | public: |
| 22194 | MachOper *opnd_array(uint operand_index) const { |
| 22195 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22196 | return _opnd_array[operand_index]; |
| 22197 | } |
| 22198 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22200 | _opnd_array[operand_index] = operand; |
| 22201 | } |
| 22202 | private: |
| 22203 | const RegMask *_cisc_RegMask; |
| 22204 | virtual const RegMask &out_RegMask() const; |
| 22205 | virtual uint rule() const { return cmpD_cc_reg_CF_rule; } |
| 22206 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22207 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22208 | virtual int cisc_operand() const { return 2; } |
| 22209 | virtual MachNode *cisc_version(int offset); |
| 22210 | virtual void use_cisc_RegMask(); |
| 22211 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22212 | public: |
| 22213 | cmpD_cc_reg_CFNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 22214 | virtual uint size_of() const { return sizeof(cmpD_cc_reg_CFNode); } |
| 22215 | // Rematerialize cmpD_cc_reg_CF |
| 22216 | static const Pipeline *pipeline_class(); |
| 22217 | virtual const Pipeline *pipeline() const; |
| 22218 | #ifndef PRODUCT |
| 22219 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22220 | virtual const char *Name() const { return "cmpD_cc_reg_CF";} |
| 22221 | #endif |
| 22222 | }; |
| 22223 | |
| 22224 | class cmpD_cc_memNode : public MachNode { |
| 22225 | private: |
| 22226 | MachOper *_opnd_array[3]; |
| 22227 | public: |
| 22228 | MachOper *opnd_array(uint operand_index) const { |
| 22229 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22230 | return _opnd_array[operand_index]; |
| 22231 | } |
| 22232 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22233 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22234 | _opnd_array[operand_index] = operand; |
| 22235 | } |
| 22236 | private: |
| 22237 | virtual const RegMask &out_RegMask() const; |
| 22238 | virtual uint rule() const { return cmpD_cc_mem_rule; } |
| 22239 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22240 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22241 | virtual int reloc() const; |
| 22242 | virtual uint oper_input_base() const { return 2; } |
| 22243 | public: |
| 22244 | cmpD_cc_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22245 | virtual uint size_of() const { return sizeof(cmpD_cc_memNode); } |
| 22246 | // Rematerialize cmpD_cc_mem |
| 22247 | static const Pipeline *pipeline_class(); |
| 22248 | virtual const Pipeline *pipeline() const; |
| 22249 | virtual const MachOper *memory_operand() const; |
| 22250 | #ifndef PRODUCT |
| 22251 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22252 | virtual const char *Name() const { return "cmpD_cc_mem";} |
| 22253 | #endif |
| 22254 | }; |
| 22255 | |
| 22256 | class cmpD_cc_memCFNode : public MachNode { |
| 22257 | private: |
| 22258 | MachOper *_opnd_array[3]; |
| 22259 | public: |
| 22260 | MachOper *opnd_array(uint operand_index) const { |
| 22261 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22262 | return _opnd_array[operand_index]; |
| 22263 | } |
| 22264 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22265 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22266 | _opnd_array[operand_index] = operand; |
| 22267 | } |
| 22268 | private: |
| 22269 | virtual const RegMask &out_RegMask() const; |
| 22270 | virtual uint rule() const { return cmpD_cc_memCF_rule; } |
| 22271 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22272 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22273 | virtual int reloc() const; |
| 22274 | virtual uint oper_input_base() const { return 2; } |
| 22275 | public: |
| 22276 | cmpD_cc_memCFNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22277 | virtual uint size_of() const { return sizeof(cmpD_cc_memCFNode); } |
| 22278 | // Rematerialize cmpD_cc_memCF |
| 22279 | static const Pipeline *pipeline_class(); |
| 22280 | virtual const Pipeline *pipeline() const; |
| 22281 | virtual const MachOper *memory_operand() const; |
| 22282 | #ifndef PRODUCT |
| 22283 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22284 | virtual const char *Name() const { return "cmpD_cc_memCF";} |
| 22285 | #endif |
| 22286 | }; |
| 22287 | |
| 22288 | class cmpD_cc_immNode : public MachConstantNode { |
| 22289 | private: |
| 22290 | MachOper *_opnd_array[3]; |
| 22291 | public: |
| 22292 | MachOper *opnd_array(uint operand_index) const { |
| 22293 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22294 | return _opnd_array[operand_index]; |
| 22295 | } |
| 22296 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22297 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22298 | _opnd_array[operand_index] = operand; |
| 22299 | } |
| 22300 | private: |
| 22301 | virtual const RegMask &out_RegMask() const; |
| 22302 | virtual uint rule() const { return cmpD_cc_imm_rule; } |
| 22303 | virtual void eval_constant(Compile* C); |
| 22304 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22305 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22306 | virtual int reloc() const; |
| 22307 | virtual uint oper_input_base() const { return 1; } |
| 22308 | public: |
| 22309 | cmpD_cc_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22310 | virtual uint size_of() const { return sizeof(cmpD_cc_immNode); } |
| 22311 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22312 | // Rematerialize cmpD_cc_imm |
| 22313 | static const Pipeline *pipeline_class(); |
| 22314 | virtual const Pipeline *pipeline() const; |
| 22315 | #ifndef PRODUCT |
| 22316 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22317 | virtual const char *Name() const { return "cmpD_cc_imm";} |
| 22318 | #endif |
| 22319 | }; |
| 22320 | |
| 22321 | class cmpD_cc_immCFNode : public MachConstantNode { |
| 22322 | private: |
| 22323 | MachOper *_opnd_array[3]; |
| 22324 | public: |
| 22325 | MachOper *opnd_array(uint operand_index) const { |
| 22326 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22327 | return _opnd_array[operand_index]; |
| 22328 | } |
| 22329 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22331 | _opnd_array[operand_index] = operand; |
| 22332 | } |
| 22333 | private: |
| 22334 | virtual const RegMask &out_RegMask() const; |
| 22335 | virtual uint rule() const { return cmpD_cc_immCF_rule; } |
| 22336 | virtual void eval_constant(Compile* C); |
| 22337 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22338 | virtual int ideal_Opcode() const { return Op_CmpD; } |
| 22339 | virtual int reloc() const; |
| 22340 | virtual uint oper_input_base() const { return 1; } |
| 22341 | public: |
| 22342 | cmpD_cc_immCFNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22343 | virtual uint size_of() const { return sizeof(cmpD_cc_immCFNode); } |
| 22344 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22345 | // Rematerialize cmpD_cc_immCF |
| 22346 | static const Pipeline *pipeline_class(); |
| 22347 | virtual const Pipeline *pipeline() const; |
| 22348 | #ifndef PRODUCT |
| 22349 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22350 | virtual const char *Name() const { return "cmpD_cc_immCF";} |
| 22351 | #endif |
| 22352 | }; |
| 22353 | |
| 22354 | class cmpF_regNode : public MachNode { |
| 22355 | private: |
| 22356 | MachOper *_opnd_array[3]; |
| 22357 | public: |
| 22358 | MachOper *opnd_array(uint operand_index) const { |
| 22359 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22360 | return _opnd_array[operand_index]; |
| 22361 | } |
| 22362 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22363 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22364 | _opnd_array[operand_index] = operand; |
| 22365 | } |
| 22366 | private: |
| 22367 | const RegMask *_cisc_RegMask; |
| 22368 | virtual const RegMask &out_RegMask() const; |
| 22369 | virtual uint rule() const { return cmpF_reg_rule; } |
| 22370 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22371 | virtual int ideal_Opcode() const { return Op_CmpF3; } |
| 22372 | virtual int cisc_operand() const { return 2; } |
| 22373 | virtual MachNode *cisc_version(int offset); |
| 22374 | virtual void use_cisc_RegMask(); |
| 22375 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22376 | public: |
| 22377 | cmpF_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 22378 | virtual uint size_of() const { return sizeof(cmpF_regNode); } |
| 22379 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22380 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22381 | static const Pipeline *pipeline_class(); |
| 22382 | virtual const Pipeline *pipeline() const; |
| 22383 | #ifndef PRODUCT |
| 22384 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22385 | virtual const char *Name() const { return "cmpF_reg";} |
| 22386 | #endif |
| 22387 | }; |
| 22388 | |
| 22389 | class cmpF_memNode : public MachNode { |
| 22390 | private: |
| 22391 | MachOper *_opnd_array[3]; |
| 22392 | public: |
| 22393 | MachOper *opnd_array(uint operand_index) const { |
| 22394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22395 | return _opnd_array[operand_index]; |
| 22396 | } |
| 22397 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22399 | _opnd_array[operand_index] = operand; |
| 22400 | } |
| 22401 | private: |
| 22402 | virtual const RegMask &out_RegMask() const; |
| 22403 | virtual uint rule() const { return cmpF_mem_rule; } |
| 22404 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22405 | virtual int ideal_Opcode() const { return Op_CmpF3; } |
| 22406 | virtual int reloc() const; |
| 22407 | virtual uint oper_input_base() const { return 2; } |
| 22408 | public: |
| 22409 | cmpF_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22410 | virtual uint size_of() const { return sizeof(cmpF_memNode); } |
| 22411 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22412 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22413 | static const Pipeline *pipeline_class(); |
| 22414 | virtual const Pipeline *pipeline() const; |
| 22415 | virtual const MachOper *memory_operand() const; |
| 22416 | #ifndef PRODUCT |
| 22417 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22418 | virtual const char *Name() const { return "cmpF_mem";} |
| 22419 | #endif |
| 22420 | }; |
| 22421 | |
| 22422 | class cmpF_immNode : public MachConstantNode { |
| 22423 | private: |
| 22424 | MachOper *_opnd_array[3]; |
| 22425 | public: |
| 22426 | MachOper *opnd_array(uint operand_index) const { |
| 22427 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22428 | return _opnd_array[operand_index]; |
| 22429 | } |
| 22430 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22431 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22432 | _opnd_array[operand_index] = operand; |
| 22433 | } |
| 22434 | private: |
| 22435 | virtual const RegMask &out_RegMask() const; |
| 22436 | virtual uint rule() const { return cmpF_imm_rule; } |
| 22437 | virtual void eval_constant(Compile* C); |
| 22438 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22439 | virtual int ideal_Opcode() const { return Op_CmpF3; } |
| 22440 | virtual int reloc() const; |
| 22441 | virtual uint oper_input_base() const { return 1; } |
| 22442 | public: |
| 22443 | cmpF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22444 | virtual uint size_of() const { return sizeof(cmpF_immNode); } |
| 22445 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22446 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22447 | static const Pipeline *pipeline_class(); |
| 22448 | virtual const Pipeline *pipeline() const; |
| 22449 | #ifndef PRODUCT |
| 22450 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22451 | virtual const char *Name() const { return "cmpF_imm";} |
| 22452 | #endif |
| 22453 | }; |
| 22454 | |
| 22455 | class cmpD_regNode : public MachNode { |
| 22456 | private: |
| 22457 | MachOper *_opnd_array[3]; |
| 22458 | public: |
| 22459 | MachOper *opnd_array(uint operand_index) const { |
| 22460 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22461 | return _opnd_array[operand_index]; |
| 22462 | } |
| 22463 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22464 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22465 | _opnd_array[operand_index] = operand; |
| 22466 | } |
| 22467 | private: |
| 22468 | const RegMask *_cisc_RegMask; |
| 22469 | virtual const RegMask &out_RegMask() const; |
| 22470 | virtual uint rule() const { return cmpD_reg_rule; } |
| 22471 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22472 | virtual int ideal_Opcode() const { return Op_CmpD3; } |
| 22473 | virtual int cisc_operand() const { return 2; } |
| 22474 | virtual MachNode *cisc_version(int offset); |
| 22475 | virtual void use_cisc_RegMask(); |
| 22476 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22477 | public: |
| 22478 | cmpD_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 22479 | virtual uint size_of() const { return sizeof(cmpD_regNode); } |
| 22480 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22481 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22482 | static const Pipeline *pipeline_class(); |
| 22483 | virtual const Pipeline *pipeline() const; |
| 22484 | #ifndef PRODUCT |
| 22485 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22486 | virtual const char *Name() const { return "cmpD_reg";} |
| 22487 | #endif |
| 22488 | }; |
| 22489 | |
| 22490 | class cmpD_memNode : public MachNode { |
| 22491 | private: |
| 22492 | MachOper *_opnd_array[3]; |
| 22493 | public: |
| 22494 | MachOper *opnd_array(uint operand_index) const { |
| 22495 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22496 | return _opnd_array[operand_index]; |
| 22497 | } |
| 22498 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22499 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22500 | _opnd_array[operand_index] = operand; |
| 22501 | } |
| 22502 | private: |
| 22503 | virtual const RegMask &out_RegMask() const; |
| 22504 | virtual uint rule() const { return cmpD_mem_rule; } |
| 22505 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22506 | virtual int ideal_Opcode() const { return Op_CmpD3; } |
| 22507 | virtual int reloc() const; |
| 22508 | virtual uint oper_input_base() const { return 2; } |
| 22509 | public: |
| 22510 | cmpD_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22511 | virtual uint size_of() const { return sizeof(cmpD_memNode); } |
| 22512 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22513 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22514 | static const Pipeline *pipeline_class(); |
| 22515 | virtual const Pipeline *pipeline() const; |
| 22516 | virtual const MachOper *memory_operand() const; |
| 22517 | #ifndef PRODUCT |
| 22518 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22519 | virtual const char *Name() const { return "cmpD_mem";} |
| 22520 | #endif |
| 22521 | }; |
| 22522 | |
| 22523 | class cmpD_immNode : public MachConstantNode { |
| 22524 | private: |
| 22525 | MachOper *_opnd_array[3]; |
| 22526 | public: |
| 22527 | MachOper *opnd_array(uint operand_index) const { |
| 22528 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22529 | return _opnd_array[operand_index]; |
| 22530 | } |
| 22531 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22532 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22533 | _opnd_array[operand_index] = operand; |
| 22534 | } |
| 22535 | private: |
| 22536 | virtual const RegMask &out_RegMask() const; |
| 22537 | virtual uint rule() const { return cmpD_imm_rule; } |
| 22538 | virtual void eval_constant(Compile* C); |
| 22539 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22540 | virtual int ideal_Opcode() const { return Op_CmpD3; } |
| 22541 | virtual int reloc() const; |
| 22542 | virtual uint oper_input_base() const { return 1; } |
| 22543 | public: |
| 22544 | cmpD_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 22545 | virtual uint size_of() const { return sizeof(cmpD_immNode); } |
| 22546 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22547 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22548 | static const Pipeline *pipeline_class(); |
| 22549 | virtual const Pipeline *pipeline() const; |
| 22550 | #ifndef PRODUCT |
| 22551 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22552 | virtual const char *Name() const { return "cmpD_imm";} |
| 22553 | #endif |
| 22554 | }; |
| 22555 | |
| 22556 | class roundFloat_nopNode : public MachNode { |
| 22557 | private: |
| 22558 | MachOper *_opnd_array[2]; |
| 22559 | public: |
| 22560 | MachOper *opnd_array(uint operand_index) const { |
| 22561 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22562 | return _opnd_array[operand_index]; |
| 22563 | } |
| 22564 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22565 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22566 | _opnd_array[operand_index] = operand; |
| 22567 | } |
| 22568 | private: |
| 22569 | virtual const RegMask &out_RegMask() const; |
| 22570 | virtual uint rule() const { return roundFloat_nop_rule; } |
| 22571 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22572 | virtual int ideal_Opcode() const { return Op_RoundFloat; } |
| 22573 | virtual uint two_adr() const { return oper_input_base(); } |
| 22574 | public: |
| 22575 | roundFloat_nopNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22576 | virtual uint size_of() const { return sizeof(roundFloat_nopNode); } |
| 22577 | // Rematerialize roundFloat_nop |
| 22578 | static const Pipeline *pipeline_class(); |
| 22579 | virtual const Pipeline *pipeline() const; |
| 22580 | #ifndef PRODUCT |
| 22581 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22582 | virtual const char *Name() const { return "roundFloat_nop";} |
| 22583 | #endif |
| 22584 | }; |
| 22585 | |
| 22586 | class roundDouble_nopNode : public MachNode { |
| 22587 | private: |
| 22588 | MachOper *_opnd_array[2]; |
| 22589 | public: |
| 22590 | MachOper *opnd_array(uint operand_index) const { |
| 22591 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22592 | return _opnd_array[operand_index]; |
| 22593 | } |
| 22594 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22595 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22596 | _opnd_array[operand_index] = operand; |
| 22597 | } |
| 22598 | private: |
| 22599 | virtual const RegMask &out_RegMask() const; |
| 22600 | virtual uint rule() const { return roundDouble_nop_rule; } |
| 22601 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22602 | virtual int ideal_Opcode() const { return Op_RoundDouble; } |
| 22603 | virtual uint two_adr() const { return oper_input_base(); } |
| 22604 | public: |
| 22605 | roundDouble_nopNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22606 | virtual uint size_of() const { return sizeof(roundDouble_nopNode); } |
| 22607 | // Rematerialize roundDouble_nop |
| 22608 | static const Pipeline *pipeline_class(); |
| 22609 | virtual const Pipeline *pipeline() const; |
| 22610 | #ifndef PRODUCT |
| 22611 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22612 | virtual const char *Name() const { return "roundDouble_nop";} |
| 22613 | #endif |
| 22614 | }; |
| 22615 | |
| 22616 | class convF2D_reg_regNode : public MachNode { |
| 22617 | private: |
| 22618 | MachOper *_opnd_array[2]; |
| 22619 | public: |
| 22620 | MachOper *opnd_array(uint operand_index) const { |
| 22621 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22622 | return _opnd_array[operand_index]; |
| 22623 | } |
| 22624 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22625 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22626 | _opnd_array[operand_index] = operand; |
| 22627 | } |
| 22628 | private: |
| 22629 | const RegMask *_cisc_RegMask; |
| 22630 | virtual const RegMask &out_RegMask() const; |
| 22631 | virtual uint rule() const { return convF2D_reg_reg_rule; } |
| 22632 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22633 | virtual int ideal_Opcode() const { return Op_ConvF2D; } |
| 22634 | virtual int cisc_operand() const { return 1; } |
| 22635 | virtual MachNode *cisc_version(int offset); |
| 22636 | virtual void use_cisc_RegMask(); |
| 22637 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22638 | public: |
| 22639 | convF2D_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 22640 | virtual uint size_of() const { return sizeof(convF2D_reg_regNode); } |
| 22641 | static const Pipeline *pipeline_class(); |
| 22642 | virtual const Pipeline *pipeline() const; |
| 22643 | #ifndef PRODUCT |
| 22644 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22645 | virtual const char *Name() const { return "convF2D_reg_reg";} |
| 22646 | #endif |
| 22647 | }; |
| 22648 | |
| 22649 | class convF2D_reg_memNode : public MachNode { |
| 22650 | private: |
| 22651 | MachOper *_opnd_array[2]; |
| 22652 | public: |
| 22653 | MachOper *opnd_array(uint operand_index) const { |
| 22654 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22655 | return _opnd_array[operand_index]; |
| 22656 | } |
| 22657 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22658 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22659 | _opnd_array[operand_index] = operand; |
| 22660 | } |
| 22661 | private: |
| 22662 | virtual const RegMask &out_RegMask() const; |
| 22663 | virtual uint rule() const { return convF2D_reg_mem_rule; } |
| 22664 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22665 | virtual int ideal_Opcode() const { return Op_ConvF2D; } |
| 22666 | virtual int reloc() const; |
| 22667 | virtual uint oper_input_base() const { return 2; } |
| 22668 | public: |
| 22669 | convF2D_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22670 | virtual uint size_of() const { return sizeof(convF2D_reg_memNode); } |
| 22671 | static const Pipeline *pipeline_class(); |
| 22672 | virtual const Pipeline *pipeline() const; |
| 22673 | virtual const MachOper *memory_operand() const; |
| 22674 | #ifndef PRODUCT |
| 22675 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22676 | virtual const char *Name() const { return "convF2D_reg_mem";} |
| 22677 | #endif |
| 22678 | }; |
| 22679 | |
| 22680 | class convD2F_reg_regNode : public MachNode { |
| 22681 | private: |
| 22682 | MachOper *_opnd_array[2]; |
| 22683 | public: |
| 22684 | MachOper *opnd_array(uint operand_index) const { |
| 22685 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22686 | return _opnd_array[operand_index]; |
| 22687 | } |
| 22688 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22689 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22690 | _opnd_array[operand_index] = operand; |
| 22691 | } |
| 22692 | private: |
| 22693 | const RegMask *_cisc_RegMask; |
| 22694 | virtual const RegMask &out_RegMask() const; |
| 22695 | virtual uint rule() const { return convD2F_reg_reg_rule; } |
| 22696 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22697 | virtual int ideal_Opcode() const { return Op_ConvD2F; } |
| 22698 | virtual int cisc_operand() const { return 1; } |
| 22699 | virtual MachNode *cisc_version(int offset); |
| 22700 | virtual void use_cisc_RegMask(); |
| 22701 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 22702 | public: |
| 22703 | convD2F_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 22704 | virtual uint size_of() const { return sizeof(convD2F_reg_regNode); } |
| 22705 | static const Pipeline *pipeline_class(); |
| 22706 | virtual const Pipeline *pipeline() const; |
| 22707 | #ifndef PRODUCT |
| 22708 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22709 | virtual const char *Name() const { return "convD2F_reg_reg";} |
| 22710 | #endif |
| 22711 | }; |
| 22712 | |
| 22713 | class convD2F_reg_memNode : public MachNode { |
| 22714 | private: |
| 22715 | MachOper *_opnd_array[2]; |
| 22716 | public: |
| 22717 | MachOper *opnd_array(uint operand_index) const { |
| 22718 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22719 | return _opnd_array[operand_index]; |
| 22720 | } |
| 22721 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22722 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22723 | _opnd_array[operand_index] = operand; |
| 22724 | } |
| 22725 | private: |
| 22726 | virtual const RegMask &out_RegMask() const; |
| 22727 | virtual uint rule() const { return convD2F_reg_mem_rule; } |
| 22728 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22729 | virtual int ideal_Opcode() const { return Op_ConvD2F; } |
| 22730 | virtual int reloc() const; |
| 22731 | virtual uint oper_input_base() const { return 2; } |
| 22732 | public: |
| 22733 | convD2F_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 22734 | virtual uint size_of() const { return sizeof(convD2F_reg_memNode); } |
| 22735 | static const Pipeline *pipeline_class(); |
| 22736 | virtual const Pipeline *pipeline() const; |
| 22737 | virtual const MachOper *memory_operand() const; |
| 22738 | #ifndef PRODUCT |
| 22739 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22740 | virtual const char *Name() const { return "convD2F_reg_mem";} |
| 22741 | #endif |
| 22742 | }; |
| 22743 | |
| 22744 | class convF2I_reg_regNode : public MachNode { |
| 22745 | private: |
| 22746 | MachOper *_opnd_array[2]; |
| 22747 | public: |
| 22748 | MachOper *opnd_array(uint operand_index) const { |
| 22749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22750 | return _opnd_array[operand_index]; |
| 22751 | } |
| 22752 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22753 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22754 | _opnd_array[operand_index] = operand; |
| 22755 | } |
| 22756 | private: |
| 22757 | virtual const RegMask &out_RegMask() const; |
| 22758 | virtual uint rule() const { return convF2I_reg_reg_rule; } |
| 22759 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22760 | virtual int ideal_Opcode() const { return Op_ConvF2I; } |
| 22761 | public: |
| 22762 | convF2I_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22763 | virtual uint size_of() const { return sizeof(convF2I_reg_regNode); } |
| 22764 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22765 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22766 | static const Pipeline *pipeline_class(); |
| 22767 | virtual const Pipeline *pipeline() const; |
| 22768 | #ifndef PRODUCT |
| 22769 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22770 | virtual const char *Name() const { return "convF2I_reg_reg";} |
| 22771 | #endif |
| 22772 | }; |
| 22773 | |
| 22774 | class convF2L_reg_regNode : public MachNode { |
| 22775 | private: |
| 22776 | MachOper *_opnd_array[2]; |
| 22777 | public: |
| 22778 | MachOper *opnd_array(uint operand_index) const { |
| 22779 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22780 | return _opnd_array[operand_index]; |
| 22781 | } |
| 22782 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22783 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22784 | _opnd_array[operand_index] = operand; |
| 22785 | } |
| 22786 | private: |
| 22787 | virtual const RegMask &out_RegMask() const; |
| 22788 | virtual uint rule() const { return convF2L_reg_reg_rule; } |
| 22789 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22790 | virtual int ideal_Opcode() const { return Op_ConvF2L; } |
| 22791 | public: |
| 22792 | convF2L_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22793 | virtual uint size_of() const { return sizeof(convF2L_reg_regNode); } |
| 22794 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22795 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22796 | static const Pipeline *pipeline_class(); |
| 22797 | virtual const Pipeline *pipeline() const; |
| 22798 | #ifndef PRODUCT |
| 22799 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22800 | virtual const char *Name() const { return "convF2L_reg_reg";} |
| 22801 | #endif |
| 22802 | }; |
| 22803 | |
| 22804 | class convD2I_reg_regNode : public MachNode { |
| 22805 | private: |
| 22806 | MachOper *_opnd_array[2]; |
| 22807 | public: |
| 22808 | MachOper *opnd_array(uint operand_index) const { |
| 22809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22810 | return _opnd_array[operand_index]; |
| 22811 | } |
| 22812 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22813 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22814 | _opnd_array[operand_index] = operand; |
| 22815 | } |
| 22816 | private: |
| 22817 | virtual const RegMask &out_RegMask() const; |
| 22818 | virtual uint rule() const { return convD2I_reg_reg_rule; } |
| 22819 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22820 | virtual int ideal_Opcode() const { return Op_ConvD2I; } |
| 22821 | public: |
| 22822 | convD2I_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22823 | virtual uint size_of() const { return sizeof(convD2I_reg_regNode); } |
| 22824 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22825 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22826 | static const Pipeline *pipeline_class(); |
| 22827 | virtual const Pipeline *pipeline() const; |
| 22828 | #ifndef PRODUCT |
| 22829 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22830 | virtual const char *Name() const { return "convD2I_reg_reg";} |
| 22831 | #endif |
| 22832 | }; |
| 22833 | |
| 22834 | class convD2L_reg_regNode : public MachNode { |
| 22835 | private: |
| 22836 | MachOper *_opnd_array[2]; |
| 22837 | public: |
| 22838 | MachOper *opnd_array(uint operand_index) const { |
| 22839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22840 | return _opnd_array[operand_index]; |
| 22841 | } |
| 22842 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22843 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22844 | _opnd_array[operand_index] = operand; |
| 22845 | } |
| 22846 | private: |
| 22847 | virtual const RegMask &out_RegMask() const; |
| 22848 | virtual uint rule() const { return convD2L_reg_reg_rule; } |
| 22849 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22850 | virtual int ideal_Opcode() const { return Op_ConvD2L; } |
| 22851 | public: |
| 22852 | convD2L_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22853 | virtual uint size_of() const { return sizeof(convD2L_reg_regNode); } |
| 22854 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 22855 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 22856 | static const Pipeline *pipeline_class(); |
| 22857 | virtual const Pipeline *pipeline() const; |
| 22858 | #ifndef PRODUCT |
| 22859 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22860 | virtual const char *Name() const { return "convD2L_reg_reg";} |
| 22861 | #endif |
| 22862 | }; |
| 22863 | |
| 22864 | class convI2F_reg_regNode : public MachNode { |
| 22865 | private: |
| 22866 | MachOper *_opnd_array[2]; |
| 22867 | public: |
| 22868 | MachOper *opnd_array(uint operand_index) const { |
| 22869 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22870 | return _opnd_array[operand_index]; |
| 22871 | } |
| 22872 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22873 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22874 | _opnd_array[operand_index] = operand; |
| 22875 | } |
| 22876 | private: |
| 22877 | virtual const RegMask &out_RegMask() const; |
| 22878 | virtual uint rule() const { return convI2F_reg_reg_rule; } |
| 22879 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22880 | virtual int ideal_Opcode() const { return Op_ConvI2F; } |
| 22881 | public: |
| 22882 | convI2F_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22883 | virtual uint size_of() const { return sizeof(convI2F_reg_regNode); } |
| 22884 | static const Pipeline *pipeline_class(); |
| 22885 | virtual const Pipeline *pipeline() const; |
| 22886 | #ifndef PRODUCT |
| 22887 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22888 | virtual const char *Name() const { return "convI2F_reg_reg";} |
| 22889 | #endif |
| 22890 | }; |
| 22891 | |
| 22892 | class convI2F_reg_memNode : public MachNode { |
| 22893 | private: |
| 22894 | MachOper *_opnd_array[2]; |
| 22895 | public: |
| 22896 | MachOper *opnd_array(uint operand_index) const { |
| 22897 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22898 | return _opnd_array[operand_index]; |
| 22899 | } |
| 22900 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22902 | _opnd_array[operand_index] = operand; |
| 22903 | } |
| 22904 | private: |
| 22905 | virtual const RegMask &out_RegMask() const; |
| 22906 | virtual uint rule() const { return convI2F_reg_mem_rule; } |
| 22907 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22908 | virtual int ideal_Opcode() const { return Op_ConvI2F; } |
| 22909 | virtual int reloc() const; |
| 22910 | virtual uint oper_input_base() const { return 2; } |
| 22911 | public: |
| 22912 | convI2F_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 22913 | virtual uint size_of() const { return sizeof(convI2F_reg_memNode); } |
| 22914 | static const Pipeline *pipeline_class(); |
| 22915 | virtual const Pipeline *pipeline() const; |
| 22916 | virtual const MachOper *memory_operand() const; |
| 22917 | #ifndef PRODUCT |
| 22918 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22919 | virtual const char *Name() const { return "convI2F_reg_mem";} |
| 22920 | #endif |
| 22921 | }; |
| 22922 | |
| 22923 | class convI2D_reg_regNode : public MachNode { |
| 22924 | private: |
| 22925 | MachOper *_opnd_array[2]; |
| 22926 | public: |
| 22927 | MachOper *opnd_array(uint operand_index) const { |
| 22928 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22929 | return _opnd_array[operand_index]; |
| 22930 | } |
| 22931 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22932 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22933 | _opnd_array[operand_index] = operand; |
| 22934 | } |
| 22935 | private: |
| 22936 | virtual const RegMask &out_RegMask() const; |
| 22937 | virtual uint rule() const { return convI2D_reg_reg_rule; } |
| 22938 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22939 | virtual int ideal_Opcode() const { return Op_ConvI2D; } |
| 22940 | public: |
| 22941 | convI2D_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 22942 | virtual uint size_of() const { return sizeof(convI2D_reg_regNode); } |
| 22943 | static const Pipeline *pipeline_class(); |
| 22944 | virtual const Pipeline *pipeline() const; |
| 22945 | #ifndef PRODUCT |
| 22946 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22947 | virtual const char *Name() const { return "convI2D_reg_reg";} |
| 22948 | #endif |
| 22949 | }; |
| 22950 | |
| 22951 | class convI2D_reg_memNode : public MachNode { |
| 22952 | private: |
| 22953 | MachOper *_opnd_array[2]; |
| 22954 | public: |
| 22955 | MachOper *opnd_array(uint operand_index) const { |
| 22956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22957 | return _opnd_array[operand_index]; |
| 22958 | } |
| 22959 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22960 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22961 | _opnd_array[operand_index] = operand; |
| 22962 | } |
| 22963 | private: |
| 22964 | virtual const RegMask &out_RegMask() const; |
| 22965 | virtual uint rule() const { return convI2D_reg_mem_rule; } |
| 22966 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22967 | virtual int ideal_Opcode() const { return Op_ConvI2D; } |
| 22968 | virtual int reloc() const; |
| 22969 | virtual uint oper_input_base() const { return 2; } |
| 22970 | public: |
| 22971 | convI2D_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 22972 | virtual uint size_of() const { return sizeof(convI2D_reg_memNode); } |
| 22973 | static const Pipeline *pipeline_class(); |
| 22974 | virtual const Pipeline *pipeline() const; |
| 22975 | virtual const MachOper *memory_operand() const; |
| 22976 | #ifndef PRODUCT |
| 22977 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 22978 | virtual const char *Name() const { return "convI2D_reg_mem";} |
| 22979 | #endif |
| 22980 | }; |
| 22981 | |
| 22982 | class convXI2F_regNode : public MachNode { |
| 22983 | private: |
| 22984 | MachOper *_opnd_array[2]; |
| 22985 | public: |
| 22986 | MachOper *opnd_array(uint operand_index) const { |
| 22987 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22988 | return _opnd_array[operand_index]; |
| 22989 | } |
| 22990 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 22991 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 22992 | _opnd_array[operand_index] = operand; |
| 22993 | } |
| 22994 | private: |
| 22995 | virtual const RegMask &out_RegMask() const; |
| 22996 | virtual uint rule() const { return convXI2F_reg_rule; } |
| 22997 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 22998 | virtual int ideal_Opcode() const { return Op_ConvI2F; } |
| 22999 | public: |
| 23000 | convXI2F_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23001 | virtual uint size_of() const { return sizeof(convXI2F_regNode); } |
| 23002 | static const Pipeline *pipeline_class(); |
| 23003 | virtual const Pipeline *pipeline() const; |
| 23004 | #ifndef PRODUCT |
| 23005 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23006 | virtual const char *Name() const { return "convXI2F_reg";} |
| 23007 | #endif |
| 23008 | }; |
| 23009 | |
| 23010 | class convXI2D_regNode : public MachNode { |
| 23011 | private: |
| 23012 | MachOper *_opnd_array[2]; |
| 23013 | public: |
| 23014 | MachOper *opnd_array(uint operand_index) const { |
| 23015 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23016 | return _opnd_array[operand_index]; |
| 23017 | } |
| 23018 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23019 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23020 | _opnd_array[operand_index] = operand; |
| 23021 | } |
| 23022 | private: |
| 23023 | virtual const RegMask &out_RegMask() const; |
| 23024 | virtual uint rule() const { return convXI2D_reg_rule; } |
| 23025 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23026 | virtual int ideal_Opcode() const { return Op_ConvI2D; } |
| 23027 | public: |
| 23028 | convXI2D_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23029 | virtual uint size_of() const { return sizeof(convXI2D_regNode); } |
| 23030 | static const Pipeline *pipeline_class(); |
| 23031 | virtual const Pipeline *pipeline() const; |
| 23032 | #ifndef PRODUCT |
| 23033 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23034 | virtual const char *Name() const { return "convXI2D_reg";} |
| 23035 | #endif |
| 23036 | }; |
| 23037 | |
| 23038 | class convL2F_reg_regNode : public MachNode { |
| 23039 | private: |
| 23040 | MachOper *_opnd_array[2]; |
| 23041 | public: |
| 23042 | MachOper *opnd_array(uint operand_index) const { |
| 23043 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23044 | return _opnd_array[operand_index]; |
| 23045 | } |
| 23046 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23047 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23048 | _opnd_array[operand_index] = operand; |
| 23049 | } |
| 23050 | private: |
| 23051 | const RegMask *_cisc_RegMask; |
| 23052 | virtual const RegMask &out_RegMask() const; |
| 23053 | virtual uint rule() const { return convL2F_reg_reg_rule; } |
| 23054 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23055 | virtual int ideal_Opcode() const { return Op_ConvL2F; } |
| 23056 | virtual int cisc_operand() const { return 1; } |
| 23057 | virtual MachNode *cisc_version(int offset); |
| 23058 | virtual void use_cisc_RegMask(); |
| 23059 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23060 | public: |
| 23061 | convL2F_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23062 | virtual uint size_of() const { return sizeof(convL2F_reg_regNode); } |
| 23063 | static const Pipeline *pipeline_class(); |
| 23064 | virtual const Pipeline *pipeline() const; |
| 23065 | #ifndef PRODUCT |
| 23066 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23067 | virtual const char *Name() const { return "convL2F_reg_reg";} |
| 23068 | #endif |
| 23069 | }; |
| 23070 | |
| 23071 | class convL2F_reg_memNode : public MachNode { |
| 23072 | private: |
| 23073 | MachOper *_opnd_array[2]; |
| 23074 | public: |
| 23075 | MachOper *opnd_array(uint operand_index) const { |
| 23076 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23077 | return _opnd_array[operand_index]; |
| 23078 | } |
| 23079 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23080 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23081 | _opnd_array[operand_index] = operand; |
| 23082 | } |
| 23083 | private: |
| 23084 | virtual const RegMask &out_RegMask() const; |
| 23085 | virtual uint rule() const { return convL2F_reg_mem_rule; } |
| 23086 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23087 | virtual int ideal_Opcode() const { return Op_ConvL2F; } |
| 23088 | virtual int reloc() const; |
| 23089 | virtual uint oper_input_base() const { return 2; } |
| 23090 | public: |
| 23091 | convL2F_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 23092 | virtual uint size_of() const { return sizeof(convL2F_reg_memNode); } |
| 23093 | static const Pipeline *pipeline_class(); |
| 23094 | virtual const Pipeline *pipeline() const; |
| 23095 | virtual const MachOper *memory_operand() const; |
| 23096 | #ifndef PRODUCT |
| 23097 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23098 | virtual const char *Name() const { return "convL2F_reg_mem";} |
| 23099 | #endif |
| 23100 | }; |
| 23101 | |
| 23102 | class convL2D_reg_regNode : public MachNode { |
| 23103 | private: |
| 23104 | MachOper *_opnd_array[2]; |
| 23105 | public: |
| 23106 | MachOper *opnd_array(uint operand_index) const { |
| 23107 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23108 | return _opnd_array[operand_index]; |
| 23109 | } |
| 23110 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23111 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23112 | _opnd_array[operand_index] = operand; |
| 23113 | } |
| 23114 | private: |
| 23115 | const RegMask *_cisc_RegMask; |
| 23116 | virtual const RegMask &out_RegMask() const; |
| 23117 | virtual uint rule() const { return convL2D_reg_reg_rule; } |
| 23118 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23119 | virtual int ideal_Opcode() const { return Op_ConvL2D; } |
| 23120 | virtual int cisc_operand() const { return 1; } |
| 23121 | virtual MachNode *cisc_version(int offset); |
| 23122 | virtual void use_cisc_RegMask(); |
| 23123 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23124 | public: |
| 23125 | convL2D_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23126 | virtual uint size_of() const { return sizeof(convL2D_reg_regNode); } |
| 23127 | static const Pipeline *pipeline_class(); |
| 23128 | virtual const Pipeline *pipeline() const; |
| 23129 | #ifndef PRODUCT |
| 23130 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23131 | virtual const char *Name() const { return "convL2D_reg_reg";} |
| 23132 | #endif |
| 23133 | }; |
| 23134 | |
| 23135 | class convL2D_reg_memNode : public MachNode { |
| 23136 | private: |
| 23137 | MachOper *_opnd_array[2]; |
| 23138 | public: |
| 23139 | MachOper *opnd_array(uint operand_index) const { |
| 23140 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23141 | return _opnd_array[operand_index]; |
| 23142 | } |
| 23143 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23144 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23145 | _opnd_array[operand_index] = operand; |
| 23146 | } |
| 23147 | private: |
| 23148 | virtual const RegMask &out_RegMask() const; |
| 23149 | virtual uint rule() const { return convL2D_reg_mem_rule; } |
| 23150 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23151 | virtual int ideal_Opcode() const { return Op_ConvL2D; } |
| 23152 | virtual int reloc() const; |
| 23153 | virtual uint oper_input_base() const { return 2; } |
| 23154 | public: |
| 23155 | convL2D_reg_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 23156 | virtual uint size_of() const { return sizeof(convL2D_reg_memNode); } |
| 23157 | static const Pipeline *pipeline_class(); |
| 23158 | virtual const Pipeline *pipeline() const; |
| 23159 | virtual const MachOper *memory_operand() const; |
| 23160 | #ifndef PRODUCT |
| 23161 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23162 | virtual const char *Name() const { return "convL2D_reg_mem";} |
| 23163 | #endif |
| 23164 | }; |
| 23165 | |
| 23166 | class convI2L_reg_regNode : public MachNode { |
| 23167 | private: |
| 23168 | MachOper *_opnd_array[2]; |
| 23169 | public: |
| 23170 | MachOper *opnd_array(uint operand_index) const { |
| 23171 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23172 | return _opnd_array[operand_index]; |
| 23173 | } |
| 23174 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23175 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23176 | _opnd_array[operand_index] = operand; |
| 23177 | } |
| 23178 | private: |
| 23179 | const RegMask *_cisc_RegMask; |
| 23180 | virtual const RegMask &out_RegMask() const; |
| 23181 | virtual uint rule() const { return convI2L_reg_reg_rule; } |
| 23182 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23183 | virtual int ideal_Opcode() const { return Op_ConvI2L; } |
| 23184 | virtual int cisc_operand() const { return 1; } |
| 23185 | virtual MachNode *cisc_version(int offset); |
| 23186 | virtual void use_cisc_RegMask(); |
| 23187 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23188 | public: |
| 23189 | convI2L_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23190 | virtual uint size_of() const { return sizeof(convI2L_reg_regNode); } |
| 23191 | static const Pipeline *pipeline_class(); |
| 23192 | virtual const Pipeline *pipeline() const; |
| 23193 | #ifndef PRODUCT |
| 23194 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23195 | virtual const char *Name() const { return "convI2L_reg_reg";} |
| 23196 | #endif |
| 23197 | }; |
| 23198 | |
| 23199 | class convI2L_reg_reg_zexNode : public MachNode { |
| 23200 | private: |
| 23201 | MachOper *_opnd_array[3]; |
| 23202 | public: |
| 23203 | MachOper *opnd_array(uint operand_index) const { |
| 23204 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23205 | return _opnd_array[operand_index]; |
| 23206 | } |
| 23207 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23209 | _opnd_array[operand_index] = operand; |
| 23210 | } |
| 23211 | private: |
| 23212 | const RegMask *_cisc_RegMask; |
| 23213 | virtual const RegMask &out_RegMask() const; |
| 23214 | virtual uint rule() const { return convI2L_reg_reg_zex_rule; } |
| 23215 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23216 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 23217 | virtual int cisc_operand() const { return 1; } |
| 23218 | virtual MachNode *cisc_version(int offset); |
| 23219 | virtual void use_cisc_RegMask(); |
| 23220 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23221 | public: |
| 23222 | convI2L_reg_reg_zexNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 23223 | virtual uint size_of() const { return sizeof(convI2L_reg_reg_zexNode); } |
| 23224 | static const Pipeline *pipeline_class(); |
| 23225 | virtual const Pipeline *pipeline() const; |
| 23226 | #ifndef PRODUCT |
| 23227 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23228 | virtual const char *Name() const { return "convI2L_reg_reg_zex";} |
| 23229 | #endif |
| 23230 | }; |
| 23231 | |
| 23232 | class convI2L_reg_mem_zexNode : public MachNode { |
| 23233 | private: |
| 23234 | MachOper *_opnd_array[3]; |
| 23235 | public: |
| 23236 | MachOper *opnd_array(uint operand_index) const { |
| 23237 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23238 | return _opnd_array[operand_index]; |
| 23239 | } |
| 23240 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23241 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23242 | _opnd_array[operand_index] = operand; |
| 23243 | } |
| 23244 | private: |
| 23245 | virtual const RegMask &out_RegMask() const; |
| 23246 | virtual uint rule() const { return convI2L_reg_mem_zex_rule; } |
| 23247 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23248 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 23249 | virtual int reloc() const; |
| 23250 | virtual uint oper_input_base() const { return 2; } |
| 23251 | public: |
| 23252 | convI2L_reg_mem_zexNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23253 | virtual uint size_of() const { return sizeof(convI2L_reg_mem_zexNode); } |
| 23254 | static const Pipeline *pipeline_class(); |
| 23255 | virtual const Pipeline *pipeline() const; |
| 23256 | virtual const MachOper *memory_operand() const; |
| 23257 | #ifndef PRODUCT |
| 23258 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23259 | virtual const char *Name() const { return "convI2L_reg_mem_zex";} |
| 23260 | #endif |
| 23261 | }; |
| 23262 | |
| 23263 | class zerox_long_reg_regNode : public MachNode { |
| 23264 | private: |
| 23265 | MachOper *_opnd_array[3]; |
| 23266 | public: |
| 23267 | MachOper *opnd_array(uint operand_index) const { |
| 23268 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23269 | return _opnd_array[operand_index]; |
| 23270 | } |
| 23271 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23273 | _opnd_array[operand_index] = operand; |
| 23274 | } |
| 23275 | private: |
| 23276 | virtual const RegMask &out_RegMask() const; |
| 23277 | virtual uint rule() const { return zerox_long_reg_reg_rule; } |
| 23278 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23279 | virtual int ideal_Opcode() const { return Op_AndL; } |
| 23280 | public: |
| 23281 | zerox_long_reg_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 23282 | virtual uint size_of() const { return sizeof(zerox_long_reg_regNode); } |
| 23283 | static const Pipeline *pipeline_class(); |
| 23284 | virtual const Pipeline *pipeline() const; |
| 23285 | #ifndef PRODUCT |
| 23286 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23287 | virtual const char *Name() const { return "zerox_long_reg_reg";} |
| 23288 | #endif |
| 23289 | }; |
| 23290 | |
| 23291 | class convL2I_reg_regNode : public MachNode { |
| 23292 | private: |
| 23293 | MachOper *_opnd_array[2]; |
| 23294 | public: |
| 23295 | MachOper *opnd_array(uint operand_index) const { |
| 23296 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23297 | return _opnd_array[operand_index]; |
| 23298 | } |
| 23299 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23300 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23301 | _opnd_array[operand_index] = operand; |
| 23302 | } |
| 23303 | private: |
| 23304 | virtual const RegMask &out_RegMask() const; |
| 23305 | virtual uint rule() const { return convL2I_reg_reg_rule; } |
| 23306 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23307 | virtual int ideal_Opcode() const { return Op_ConvL2I; } |
| 23308 | public: |
| 23309 | convL2I_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23310 | virtual uint size_of() const { return sizeof(convL2I_reg_regNode); } |
| 23311 | static const Pipeline *pipeline_class(); |
| 23312 | virtual const Pipeline *pipeline() const; |
| 23313 | #ifndef PRODUCT |
| 23314 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23315 | virtual const char *Name() const { return "convL2I_reg_reg";} |
| 23316 | #endif |
| 23317 | }; |
| 23318 | |
| 23319 | class MoveF2I_stack_regNode : public MachNode { |
| 23320 | private: |
| 23321 | MachOper *_opnd_array[2]; |
| 23322 | public: |
| 23323 | MachOper *opnd_array(uint operand_index) const { |
| 23324 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23325 | return _opnd_array[operand_index]; |
| 23326 | } |
| 23327 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23328 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23329 | _opnd_array[operand_index] = operand; |
| 23330 | } |
| 23331 | private: |
| 23332 | virtual const RegMask &out_RegMask() const; |
| 23333 | virtual uint rule() const { return MoveF2I_stack_reg_rule; } |
| 23334 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23335 | virtual int ideal_Opcode() const { return Op_MoveF2I; } |
| 23336 | public: |
| 23337 | MoveF2I_stack_regNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 23338 | virtual uint size_of() const { return sizeof(MoveF2I_stack_regNode); } |
| 23339 | // Rematerialize MoveF2I_stack_reg |
| 23340 | static const Pipeline *pipeline_class(); |
| 23341 | virtual const Pipeline *pipeline() const; |
| 23342 | #ifndef PRODUCT |
| 23343 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23344 | virtual const char *Name() const { return "MoveF2I_stack_reg";} |
| 23345 | #endif |
| 23346 | }; |
| 23347 | |
| 23348 | class MoveI2F_stack_regNode : public MachNode { |
| 23349 | private: |
| 23350 | MachOper *_opnd_array[2]; |
| 23351 | public: |
| 23352 | MachOper *opnd_array(uint operand_index) const { |
| 23353 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23354 | return _opnd_array[operand_index]; |
| 23355 | } |
| 23356 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23357 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23358 | _opnd_array[operand_index] = operand; |
| 23359 | } |
| 23360 | private: |
| 23361 | virtual const RegMask &out_RegMask() const; |
| 23362 | virtual uint rule() const { return MoveI2F_stack_reg_rule; } |
| 23363 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23364 | virtual int ideal_Opcode() const { return Op_MoveI2F; } |
| 23365 | public: |
| 23366 | MoveI2F_stack_regNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 23367 | virtual uint size_of() const { return sizeof(MoveI2F_stack_regNode); } |
| 23368 | // Rematerialize MoveI2F_stack_reg |
| 23369 | static const Pipeline *pipeline_class(); |
| 23370 | virtual const Pipeline *pipeline() const; |
| 23371 | #ifndef PRODUCT |
| 23372 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23373 | virtual const char *Name() const { return "MoveI2F_stack_reg";} |
| 23374 | #endif |
| 23375 | }; |
| 23376 | |
| 23377 | class MoveD2L_stack_regNode : public MachNode { |
| 23378 | private: |
| 23379 | MachOper *_opnd_array[2]; |
| 23380 | public: |
| 23381 | MachOper *opnd_array(uint operand_index) const { |
| 23382 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23383 | return _opnd_array[operand_index]; |
| 23384 | } |
| 23385 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23386 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23387 | _opnd_array[operand_index] = operand; |
| 23388 | } |
| 23389 | private: |
| 23390 | virtual const RegMask &out_RegMask() const; |
| 23391 | virtual uint rule() const { return MoveD2L_stack_reg_rule; } |
| 23392 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23393 | virtual int ideal_Opcode() const { return Op_MoveD2L; } |
| 23394 | public: |
| 23395 | MoveD2L_stack_regNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 23396 | virtual uint size_of() const { return sizeof(MoveD2L_stack_regNode); } |
| 23397 | // Rematerialize MoveD2L_stack_reg |
| 23398 | static const Pipeline *pipeline_class(); |
| 23399 | virtual const Pipeline *pipeline() const; |
| 23400 | #ifndef PRODUCT |
| 23401 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23402 | virtual const char *Name() const { return "MoveD2L_stack_reg";} |
| 23403 | #endif |
| 23404 | }; |
| 23405 | |
| 23406 | class MoveL2D_stack_reg_partialNode : public MachNode { |
| 23407 | private: |
| 23408 | MachOper *_opnd_array[2]; |
| 23409 | public: |
| 23410 | MachOper *opnd_array(uint operand_index) const { |
| 23411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23412 | return _opnd_array[operand_index]; |
| 23413 | } |
| 23414 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23415 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23416 | _opnd_array[operand_index] = operand; |
| 23417 | } |
| 23418 | private: |
| 23419 | virtual const RegMask &out_RegMask() const; |
| 23420 | virtual uint rule() const { return MoveL2D_stack_reg_partial_rule; } |
| 23421 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23422 | virtual int ideal_Opcode() const { return Op_MoveL2D; } |
| 23423 | public: |
| 23424 | MoveL2D_stack_reg_partialNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23425 | virtual uint size_of() const { return sizeof(MoveL2D_stack_reg_partialNode); } |
| 23426 | // Rematerialize MoveL2D_stack_reg_partial |
| 23427 | static const Pipeline *pipeline_class(); |
| 23428 | virtual const Pipeline *pipeline() const; |
| 23429 | #ifndef PRODUCT |
| 23430 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23431 | virtual const char *Name() const { return "MoveL2D_stack_reg_partial";} |
| 23432 | #endif |
| 23433 | }; |
| 23434 | |
| 23435 | class MoveL2D_stack_regNode : public MachNode { |
| 23436 | private: |
| 23437 | MachOper *_opnd_array[2]; |
| 23438 | public: |
| 23439 | MachOper *opnd_array(uint operand_index) const { |
| 23440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23441 | return _opnd_array[operand_index]; |
| 23442 | } |
| 23443 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23444 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23445 | _opnd_array[operand_index] = operand; |
| 23446 | } |
| 23447 | private: |
| 23448 | virtual const RegMask &out_RegMask() const; |
| 23449 | virtual uint rule() const { return MoveL2D_stack_reg_rule; } |
| 23450 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23451 | virtual int ideal_Opcode() const { return Op_MoveL2D; } |
| 23452 | public: |
| 23453 | MoveL2D_stack_regNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23454 | virtual uint size_of() const { return sizeof(MoveL2D_stack_regNode); } |
| 23455 | // Rematerialize MoveL2D_stack_reg |
| 23456 | static const Pipeline *pipeline_class(); |
| 23457 | virtual const Pipeline *pipeline() const; |
| 23458 | #ifndef PRODUCT |
| 23459 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23460 | virtual const char *Name() const { return "MoveL2D_stack_reg";} |
| 23461 | #endif |
| 23462 | }; |
| 23463 | |
| 23464 | class MoveF2I_reg_stackNode : public MachNode { |
| 23465 | private: |
| 23466 | MachOper *_opnd_array[2]; |
| 23467 | public: |
| 23468 | MachOper *opnd_array(uint operand_index) const { |
| 23469 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23470 | return _opnd_array[operand_index]; |
| 23471 | } |
| 23472 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23473 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23474 | _opnd_array[operand_index] = operand; |
| 23475 | } |
| 23476 | private: |
| 23477 | virtual const RegMask &out_RegMask() const; |
| 23478 | virtual uint rule() const { return MoveF2I_reg_stack_rule; } |
| 23479 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23480 | virtual int ideal_Opcode() const { return Op_MoveF2I; } |
| 23481 | public: |
| 23482 | MoveF2I_reg_stackNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23483 | virtual uint size_of() const { return sizeof(MoveF2I_reg_stackNode); } |
| 23484 | static const Pipeline *pipeline_class(); |
| 23485 | virtual const Pipeline *pipeline() const; |
| 23486 | #ifndef PRODUCT |
| 23487 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23488 | virtual const char *Name() const { return "MoveF2I_reg_stack";} |
| 23489 | #endif |
| 23490 | }; |
| 23491 | |
| 23492 | class MoveI2F_reg_stackNode : public MachNode { |
| 23493 | private: |
| 23494 | MachOper *_opnd_array[2]; |
| 23495 | public: |
| 23496 | MachOper *opnd_array(uint operand_index) const { |
| 23497 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23498 | return _opnd_array[operand_index]; |
| 23499 | } |
| 23500 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23501 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23502 | _opnd_array[operand_index] = operand; |
| 23503 | } |
| 23504 | private: |
| 23505 | virtual const RegMask &out_RegMask() const; |
| 23506 | virtual uint rule() const { return MoveI2F_reg_stack_rule; } |
| 23507 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23508 | virtual int ideal_Opcode() const { return Op_MoveI2F; } |
| 23509 | public: |
| 23510 | MoveI2F_reg_stackNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23511 | virtual uint size_of() const { return sizeof(MoveI2F_reg_stackNode); } |
| 23512 | static const Pipeline *pipeline_class(); |
| 23513 | virtual const Pipeline *pipeline() const; |
| 23514 | #ifndef PRODUCT |
| 23515 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23516 | virtual const char *Name() const { return "MoveI2F_reg_stack";} |
| 23517 | #endif |
| 23518 | }; |
| 23519 | |
| 23520 | class MoveD2L_reg_stackNode : public MachNode { |
| 23521 | private: |
| 23522 | MachOper *_opnd_array[2]; |
| 23523 | public: |
| 23524 | MachOper *opnd_array(uint operand_index) const { |
| 23525 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23526 | return _opnd_array[operand_index]; |
| 23527 | } |
| 23528 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23529 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23530 | _opnd_array[operand_index] = operand; |
| 23531 | } |
| 23532 | private: |
| 23533 | virtual const RegMask &out_RegMask() const; |
| 23534 | virtual uint rule() const { return MoveD2L_reg_stack_rule; } |
| 23535 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23536 | virtual int ideal_Opcode() const { return Op_MoveD2L; } |
| 23537 | public: |
| 23538 | MoveD2L_reg_stackNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23539 | virtual uint size_of() const { return sizeof(MoveD2L_reg_stackNode); } |
| 23540 | static const Pipeline *pipeline_class(); |
| 23541 | virtual const Pipeline *pipeline() const; |
| 23542 | #ifndef PRODUCT |
| 23543 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23544 | virtual const char *Name() const { return "MoveD2L_reg_stack";} |
| 23545 | #endif |
| 23546 | }; |
| 23547 | |
| 23548 | class MoveL2D_reg_stackNode : public MachNode { |
| 23549 | private: |
| 23550 | MachOper *_opnd_array[2]; |
| 23551 | public: |
| 23552 | MachOper *opnd_array(uint operand_index) const { |
| 23553 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23554 | return _opnd_array[operand_index]; |
| 23555 | } |
| 23556 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23557 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23558 | _opnd_array[operand_index] = operand; |
| 23559 | } |
| 23560 | private: |
| 23561 | virtual const RegMask &out_RegMask() const; |
| 23562 | virtual uint rule() const { return MoveL2D_reg_stack_rule; } |
| 23563 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23564 | virtual int ideal_Opcode() const { return Op_MoveL2D; } |
| 23565 | public: |
| 23566 | MoveL2D_reg_stackNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23567 | virtual uint size_of() const { return sizeof(MoveL2D_reg_stackNode); } |
| 23568 | static const Pipeline *pipeline_class(); |
| 23569 | virtual const Pipeline *pipeline() const; |
| 23570 | #ifndef PRODUCT |
| 23571 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23572 | virtual const char *Name() const { return "MoveL2D_reg_stack";} |
| 23573 | #endif |
| 23574 | }; |
| 23575 | |
| 23576 | class MoveF2I_reg_regNode : public MachNode { |
| 23577 | private: |
| 23578 | MachOper *_opnd_array[2]; |
| 23579 | public: |
| 23580 | MachOper *opnd_array(uint operand_index) const { |
| 23581 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23582 | return _opnd_array[operand_index]; |
| 23583 | } |
| 23584 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23585 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23586 | _opnd_array[operand_index] = operand; |
| 23587 | } |
| 23588 | private: |
| 23589 | const RegMask *_cisc_RegMask; |
| 23590 | virtual const RegMask &out_RegMask() const; |
| 23591 | virtual uint rule() const { return MoveF2I_reg_reg_rule; } |
| 23592 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23593 | virtual int ideal_Opcode() const { return Op_MoveF2I; } |
| 23594 | virtual int cisc_operand() const { return 1; } |
| 23595 | virtual MachNode *cisc_version(int offset); |
| 23596 | virtual void use_cisc_RegMask(); |
| 23597 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23598 | public: |
| 23599 | MoveF2I_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23600 | virtual uint size_of() const { return sizeof(MoveF2I_reg_regNode); } |
| 23601 | // Rematerialize MoveF2I_reg_reg |
| 23602 | static const Pipeline *pipeline_class(); |
| 23603 | virtual const Pipeline *pipeline() const; |
| 23604 | #ifndef PRODUCT |
| 23605 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23606 | virtual const char *Name() const { return "MoveF2I_reg_reg";} |
| 23607 | #endif |
| 23608 | }; |
| 23609 | |
| 23610 | class MoveD2L_reg_regNode : public MachNode { |
| 23611 | private: |
| 23612 | MachOper *_opnd_array[2]; |
| 23613 | public: |
| 23614 | MachOper *opnd_array(uint operand_index) const { |
| 23615 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23616 | return _opnd_array[operand_index]; |
| 23617 | } |
| 23618 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23619 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23620 | _opnd_array[operand_index] = operand; |
| 23621 | } |
| 23622 | private: |
| 23623 | const RegMask *_cisc_RegMask; |
| 23624 | virtual const RegMask &out_RegMask() const; |
| 23625 | virtual uint rule() const { return MoveD2L_reg_reg_rule; } |
| 23626 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23627 | virtual int ideal_Opcode() const { return Op_MoveD2L; } |
| 23628 | virtual int cisc_operand() const { return 1; } |
| 23629 | virtual MachNode *cisc_version(int offset); |
| 23630 | virtual void use_cisc_RegMask(); |
| 23631 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23632 | public: |
| 23633 | MoveD2L_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23634 | virtual uint size_of() const { return sizeof(MoveD2L_reg_regNode); } |
| 23635 | // Rematerialize MoveD2L_reg_reg |
| 23636 | static const Pipeline *pipeline_class(); |
| 23637 | virtual const Pipeline *pipeline() const; |
| 23638 | #ifndef PRODUCT |
| 23639 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23640 | virtual const char *Name() const { return "MoveD2L_reg_reg";} |
| 23641 | #endif |
| 23642 | }; |
| 23643 | |
| 23644 | class MoveI2F_reg_regNode : public MachNode { |
| 23645 | private: |
| 23646 | MachOper *_opnd_array[2]; |
| 23647 | public: |
| 23648 | MachOper *opnd_array(uint operand_index) const { |
| 23649 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23650 | return _opnd_array[operand_index]; |
| 23651 | } |
| 23652 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23653 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23654 | _opnd_array[operand_index] = operand; |
| 23655 | } |
| 23656 | private: |
| 23657 | const RegMask *_cisc_RegMask; |
| 23658 | virtual const RegMask &out_RegMask() const; |
| 23659 | virtual uint rule() const { return MoveI2F_reg_reg_rule; } |
| 23660 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23661 | virtual int ideal_Opcode() const { return Op_MoveI2F; } |
| 23662 | virtual int cisc_operand() const { return 1; } |
| 23663 | virtual MachNode *cisc_version(int offset); |
| 23664 | virtual void use_cisc_RegMask(); |
| 23665 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 23666 | public: |
| 23667 | MoveI2F_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 23668 | virtual uint size_of() const { return sizeof(MoveI2F_reg_regNode); } |
| 23669 | // Rematerialize MoveI2F_reg_reg |
| 23670 | static const Pipeline *pipeline_class(); |
| 23671 | virtual const Pipeline *pipeline() const; |
| 23672 | #ifndef PRODUCT |
| 23673 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23674 | virtual const char *Name() const { return "MoveI2F_reg_reg";} |
| 23675 | #endif |
| 23676 | }; |
| 23677 | |
| 23678 | class MoveL2D_reg_regNode : public MachNode { |
| 23679 | private: |
| 23680 | MachOper *_opnd_array[2]; |
| 23681 | public: |
| 23682 | MachOper *opnd_array(uint operand_index) const { |
| 23683 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23684 | return _opnd_array[operand_index]; |
| 23685 | } |
| 23686 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23687 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23688 | _opnd_array[operand_index] = operand; |
| 23689 | } |
| 23690 | private: |
| 23691 | virtual const RegMask &out_RegMask() const; |
| 23692 | virtual uint rule() const { return MoveL2D_reg_reg_rule; } |
| 23693 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23694 | virtual int ideal_Opcode() const { return Op_MoveL2D; } |
| 23695 | public: |
| 23696 | MoveL2D_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 23697 | virtual uint size_of() const { return sizeof(MoveL2D_reg_regNode); } |
| 23698 | // Rematerialize MoveL2D_reg_reg |
| 23699 | static const Pipeline *pipeline_class(); |
| 23700 | virtual const Pipeline *pipeline() const; |
| 23701 | #ifndef PRODUCT |
| 23702 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23703 | virtual const char *Name() const { return "MoveL2D_reg_reg";} |
| 23704 | #endif |
| 23705 | }; |
| 23706 | |
| 23707 | class rep_stosNode : public MachNode { |
| 23708 | private: |
| 23709 | MachOper *_opnd_array[4]; |
| 23710 | public: |
| 23711 | MachOper *opnd_array(uint operand_index) const { |
| 23712 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23713 | return _opnd_array[operand_index]; |
| 23714 | } |
| 23715 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23716 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23717 | _opnd_array[operand_index] = operand; |
| 23718 | } |
| 23719 | private: |
| 23720 | virtual const RegMask &out_RegMask() const; |
| 23721 | virtual uint rule() const { return rep_stos_rule; } |
| 23722 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23723 | virtual int ideal_Opcode() const { return Op_ClearArray; } |
| 23724 | virtual uint oper_input_base() const { return 2; } |
| 23725 | public: |
| 23726 | rep_stosNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 23727 | virtual uint size_of() const { return sizeof(rep_stosNode); } |
| 23728 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23729 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23730 | static const Pipeline *pipeline_class(); |
| 23731 | virtual const Pipeline *pipeline() const; |
| 23732 | #ifndef PRODUCT |
| 23733 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23734 | virtual const char *Name() const { return "rep_stos";} |
| 23735 | #endif |
| 23736 | }; |
| 23737 | |
| 23738 | class rep_stos_largeNode : public MachNode { |
| 23739 | private: |
| 23740 | MachOper *_opnd_array[4]; |
| 23741 | public: |
| 23742 | MachOper *opnd_array(uint operand_index) const { |
| 23743 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23744 | return _opnd_array[operand_index]; |
| 23745 | } |
| 23746 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23747 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23748 | _opnd_array[operand_index] = operand; |
| 23749 | } |
| 23750 | private: |
| 23751 | virtual const RegMask &out_RegMask() const; |
| 23752 | virtual uint rule() const { return rep_stos_large_rule; } |
| 23753 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23754 | virtual int ideal_Opcode() const { return Op_ClearArray; } |
| 23755 | virtual uint oper_input_base() const { return 2; } |
| 23756 | public: |
| 23757 | rep_stos_largeNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 23758 | virtual uint size_of() const { return sizeof(rep_stos_largeNode); } |
| 23759 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23760 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23761 | static const Pipeline *pipeline_class(); |
| 23762 | virtual const Pipeline *pipeline() const; |
| 23763 | #ifndef PRODUCT |
| 23764 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23765 | virtual const char *Name() const { return "rep_stos_large";} |
| 23766 | #endif |
| 23767 | }; |
| 23768 | |
| 23769 | class string_compareLNode : public MachNode { |
| 23770 | private: |
| 23771 | MachOper *_opnd_array[6]; |
| 23772 | public: |
| 23773 | MachOper *opnd_array(uint operand_index) const { |
| 23774 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23775 | return _opnd_array[operand_index]; |
| 23776 | } |
| 23777 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23778 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23779 | _opnd_array[operand_index] = operand; |
| 23780 | } |
| 23781 | private: |
| 23782 | virtual const RegMask &out_RegMask() const; |
| 23783 | virtual uint rule() const { return string_compareL_rule; } |
| 23784 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23785 | virtual int ideal_Opcode() const { return Op_StrComp; } |
| 23786 | virtual uint oper_input_base() const { return 2; } |
| 23787 | public: |
| 23788 | string_compareLNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23789 | virtual uint size_of() const { return sizeof(string_compareLNode); } |
| 23790 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23791 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23792 | static const Pipeline *pipeline_class(); |
| 23793 | virtual const Pipeline *pipeline() const; |
| 23794 | #ifndef PRODUCT |
| 23795 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23796 | virtual const char *Name() const { return "string_compareL";} |
| 23797 | #endif |
| 23798 | }; |
| 23799 | |
| 23800 | class string_compareUNode : public MachNode { |
| 23801 | private: |
| 23802 | MachOper *_opnd_array[6]; |
| 23803 | public: |
| 23804 | MachOper *opnd_array(uint operand_index) const { |
| 23805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23806 | return _opnd_array[operand_index]; |
| 23807 | } |
| 23808 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23810 | _opnd_array[operand_index] = operand; |
| 23811 | } |
| 23812 | private: |
| 23813 | virtual const RegMask &out_RegMask() const; |
| 23814 | virtual uint rule() const { return string_compareU_rule; } |
| 23815 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23816 | virtual int ideal_Opcode() const { return Op_StrComp; } |
| 23817 | virtual uint oper_input_base() const { return 2; } |
| 23818 | public: |
| 23819 | string_compareUNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23820 | virtual uint size_of() const { return sizeof(string_compareUNode); } |
| 23821 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23822 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23823 | static const Pipeline *pipeline_class(); |
| 23824 | virtual const Pipeline *pipeline() const; |
| 23825 | #ifndef PRODUCT |
| 23826 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23827 | virtual const char *Name() const { return "string_compareU";} |
| 23828 | #endif |
| 23829 | }; |
| 23830 | |
| 23831 | class string_compareLUNode : public MachNode { |
| 23832 | private: |
| 23833 | MachOper *_opnd_array[6]; |
| 23834 | public: |
| 23835 | MachOper *opnd_array(uint operand_index) const { |
| 23836 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23837 | return _opnd_array[operand_index]; |
| 23838 | } |
| 23839 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23840 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23841 | _opnd_array[operand_index] = operand; |
| 23842 | } |
| 23843 | private: |
| 23844 | virtual const RegMask &out_RegMask() const; |
| 23845 | virtual uint rule() const { return string_compareLU_rule; } |
| 23846 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23847 | virtual int ideal_Opcode() const { return Op_StrComp; } |
| 23848 | virtual uint oper_input_base() const { return 2; } |
| 23849 | public: |
| 23850 | string_compareLUNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23851 | virtual uint size_of() const { return sizeof(string_compareLUNode); } |
| 23852 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23853 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23854 | static const Pipeline *pipeline_class(); |
| 23855 | virtual const Pipeline *pipeline() const; |
| 23856 | #ifndef PRODUCT |
| 23857 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23858 | virtual const char *Name() const { return "string_compareLU";} |
| 23859 | #endif |
| 23860 | }; |
| 23861 | |
| 23862 | class string_compareULNode : public MachNode { |
| 23863 | private: |
| 23864 | MachOper *_opnd_array[6]; |
| 23865 | public: |
| 23866 | MachOper *opnd_array(uint operand_index) const { |
| 23867 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23868 | return _opnd_array[operand_index]; |
| 23869 | } |
| 23870 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23871 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23872 | _opnd_array[operand_index] = operand; |
| 23873 | } |
| 23874 | private: |
| 23875 | virtual const RegMask &out_RegMask() const; |
| 23876 | virtual uint rule() const { return string_compareUL_rule; } |
| 23877 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23878 | virtual int ideal_Opcode() const { return Op_StrComp; } |
| 23879 | virtual uint oper_input_base() const { return 2; } |
| 23880 | public: |
| 23881 | string_compareULNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23882 | virtual uint size_of() const { return sizeof(string_compareULNode); } |
| 23883 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23884 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23885 | static const Pipeline *pipeline_class(); |
| 23886 | virtual const Pipeline *pipeline() const; |
| 23887 | #ifndef PRODUCT |
| 23888 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23889 | virtual const char *Name() const { return "string_compareUL";} |
| 23890 | #endif |
| 23891 | }; |
| 23892 | |
| 23893 | class string_indexof_conLNode : public MachNode { |
| 23894 | private: |
| 23895 | MachOper *_opnd_array[6]; |
| 23896 | public: |
| 23897 | MachOper *opnd_array(uint operand_index) const { |
| 23898 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23899 | return _opnd_array[operand_index]; |
| 23900 | } |
| 23901 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23902 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23903 | _opnd_array[operand_index] = operand; |
| 23904 | } |
| 23905 | private: |
| 23906 | virtual const RegMask &out_RegMask() const; |
| 23907 | virtual uint rule() const { return string_indexof_conL_rule; } |
| 23908 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23909 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 23910 | virtual uint oper_input_base() const { return 2; } |
| 23911 | public: |
| 23912 | string_indexof_conLNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23913 | virtual uint size_of() const { return sizeof(string_indexof_conLNode); } |
| 23914 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23915 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23916 | static const Pipeline *pipeline_class(); |
| 23917 | virtual const Pipeline *pipeline() const; |
| 23918 | #ifndef PRODUCT |
| 23919 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23920 | virtual const char *Name() const { return "string_indexof_conL";} |
| 23921 | #endif |
| 23922 | }; |
| 23923 | |
| 23924 | class string_indexof_conUNode : public MachNode { |
| 23925 | private: |
| 23926 | MachOper *_opnd_array[6]; |
| 23927 | public: |
| 23928 | MachOper *opnd_array(uint operand_index) const { |
| 23929 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23930 | return _opnd_array[operand_index]; |
| 23931 | } |
| 23932 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23933 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23934 | _opnd_array[operand_index] = operand; |
| 23935 | } |
| 23936 | private: |
| 23937 | virtual const RegMask &out_RegMask() const; |
| 23938 | virtual uint rule() const { return string_indexof_conU_rule; } |
| 23939 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23940 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 23941 | virtual uint oper_input_base() const { return 2; } |
| 23942 | public: |
| 23943 | string_indexof_conUNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23944 | virtual uint size_of() const { return sizeof(string_indexof_conUNode); } |
| 23945 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23946 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23947 | static const Pipeline *pipeline_class(); |
| 23948 | virtual const Pipeline *pipeline() const; |
| 23949 | #ifndef PRODUCT |
| 23950 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23951 | virtual const char *Name() const { return "string_indexof_conU";} |
| 23952 | #endif |
| 23953 | }; |
| 23954 | |
| 23955 | class string_indexof_conULNode : public MachNode { |
| 23956 | private: |
| 23957 | MachOper *_opnd_array[6]; |
| 23958 | public: |
| 23959 | MachOper *opnd_array(uint operand_index) const { |
| 23960 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23961 | return _opnd_array[operand_index]; |
| 23962 | } |
| 23963 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23964 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23965 | _opnd_array[operand_index] = operand; |
| 23966 | } |
| 23967 | private: |
| 23968 | virtual const RegMask &out_RegMask() const; |
| 23969 | virtual uint rule() const { return string_indexof_conUL_rule; } |
| 23970 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 23971 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 23972 | virtual uint oper_input_base() const { return 2; } |
| 23973 | public: |
| 23974 | string_indexof_conULNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 23975 | virtual uint size_of() const { return sizeof(string_indexof_conULNode); } |
| 23976 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 23977 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 23978 | static const Pipeline *pipeline_class(); |
| 23979 | virtual const Pipeline *pipeline() const; |
| 23980 | #ifndef PRODUCT |
| 23981 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 23982 | virtual const char *Name() const { return "string_indexof_conUL";} |
| 23983 | #endif |
| 23984 | }; |
| 23985 | |
| 23986 | class string_indexofLNode : public MachNode { |
| 23987 | private: |
| 23988 | MachOper *_opnd_array[6]; |
| 23989 | public: |
| 23990 | MachOper *opnd_array(uint operand_index) const { |
| 23991 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23992 | return _opnd_array[operand_index]; |
| 23993 | } |
| 23994 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 23995 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 23996 | _opnd_array[operand_index] = operand; |
| 23997 | } |
| 23998 | private: |
| 23999 | virtual const RegMask &out_RegMask() const; |
| 24000 | virtual uint rule() const { return string_indexofL_rule; } |
| 24001 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24002 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 24003 | virtual uint oper_input_base() const { return 2; } |
| 24004 | public: |
| 24005 | string_indexofLNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24006 | virtual uint size_of() const { return sizeof(string_indexofLNode); } |
| 24007 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24008 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24009 | static const Pipeline *pipeline_class(); |
| 24010 | virtual const Pipeline *pipeline() const; |
| 24011 | #ifndef PRODUCT |
| 24012 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24013 | virtual const char *Name() const { return "string_indexofL";} |
| 24014 | #endif |
| 24015 | }; |
| 24016 | |
| 24017 | class string_indexofUNode : public MachNode { |
| 24018 | private: |
| 24019 | MachOper *_opnd_array[6]; |
| 24020 | public: |
| 24021 | MachOper *opnd_array(uint operand_index) const { |
| 24022 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24023 | return _opnd_array[operand_index]; |
| 24024 | } |
| 24025 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24026 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24027 | _opnd_array[operand_index] = operand; |
| 24028 | } |
| 24029 | private: |
| 24030 | virtual const RegMask &out_RegMask() const; |
| 24031 | virtual uint rule() const { return string_indexofU_rule; } |
| 24032 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24033 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 24034 | virtual uint oper_input_base() const { return 2; } |
| 24035 | public: |
| 24036 | string_indexofUNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24037 | virtual uint size_of() const { return sizeof(string_indexofUNode); } |
| 24038 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24039 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24040 | static const Pipeline *pipeline_class(); |
| 24041 | virtual const Pipeline *pipeline() const; |
| 24042 | #ifndef PRODUCT |
| 24043 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24044 | virtual const char *Name() const { return "string_indexofU";} |
| 24045 | #endif |
| 24046 | }; |
| 24047 | |
| 24048 | class string_indexofULNode : public MachNode { |
| 24049 | private: |
| 24050 | MachOper *_opnd_array[6]; |
| 24051 | public: |
| 24052 | MachOper *opnd_array(uint operand_index) const { |
| 24053 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24054 | return _opnd_array[operand_index]; |
| 24055 | } |
| 24056 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24057 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24058 | _opnd_array[operand_index] = operand; |
| 24059 | } |
| 24060 | private: |
| 24061 | virtual const RegMask &out_RegMask() const; |
| 24062 | virtual uint rule() const { return string_indexofUL_rule; } |
| 24063 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24064 | virtual int ideal_Opcode() const { return Op_StrIndexOf; } |
| 24065 | virtual uint oper_input_base() const { return 2; } |
| 24066 | public: |
| 24067 | string_indexofULNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24068 | virtual uint size_of() const { return sizeof(string_indexofULNode); } |
| 24069 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24070 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24071 | static const Pipeline *pipeline_class(); |
| 24072 | virtual const Pipeline *pipeline() const; |
| 24073 | #ifndef PRODUCT |
| 24074 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24075 | virtual const char *Name() const { return "string_indexofUL";} |
| 24076 | #endif |
| 24077 | }; |
| 24078 | |
| 24079 | class string_indexofU_charNode : public MachNode { |
| 24080 | private: |
| 24081 | MachOper *_opnd_array[8]; |
| 24082 | public: |
| 24083 | MachOper *opnd_array(uint operand_index) const { |
| 24084 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24085 | return _opnd_array[operand_index]; |
| 24086 | } |
| 24087 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24088 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24089 | _opnd_array[operand_index] = operand; |
| 24090 | } |
| 24091 | private: |
| 24092 | virtual const RegMask &out_RegMask() const; |
| 24093 | virtual uint rule() const { return string_indexofU_char_rule; } |
| 24094 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24095 | virtual int ideal_Opcode() const { return Op_StrIndexOfChar; } |
| 24096 | virtual uint oper_input_base() const { return 2; } |
| 24097 | public: |
| 24098 | string_indexofU_charNode() { _num_opnds = 8; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24099 | virtual uint size_of() const { return sizeof(string_indexofU_charNode); } |
| 24100 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24101 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24102 | static const Pipeline *pipeline_class(); |
| 24103 | virtual const Pipeline *pipeline() const; |
| 24104 | #ifndef PRODUCT |
| 24105 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24106 | virtual const char *Name() const { return "string_indexofU_char";} |
| 24107 | #endif |
| 24108 | }; |
| 24109 | |
| 24110 | class string_equalsNode : public MachNode { |
| 24111 | private: |
| 24112 | MachOper *_opnd_array[6]; |
| 24113 | public: |
| 24114 | MachOper *opnd_array(uint operand_index) const { |
| 24115 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24116 | return _opnd_array[operand_index]; |
| 24117 | } |
| 24118 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24119 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24120 | _opnd_array[operand_index] = operand; |
| 24121 | } |
| 24122 | private: |
| 24123 | virtual const RegMask &out_RegMask() const; |
| 24124 | virtual uint rule() const { return string_equals_rule; } |
| 24125 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24126 | virtual int ideal_Opcode() const { return Op_StrEquals; } |
| 24127 | virtual uint oper_input_base() const { return 2; } |
| 24128 | public: |
| 24129 | string_equalsNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24130 | virtual uint size_of() const { return sizeof(string_equalsNode); } |
| 24131 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24132 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24133 | static const Pipeline *pipeline_class(); |
| 24134 | virtual const Pipeline *pipeline() const; |
| 24135 | #ifndef PRODUCT |
| 24136 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24137 | virtual const char *Name() const { return "string_equals";} |
| 24138 | #endif |
| 24139 | }; |
| 24140 | |
| 24141 | class array_equalsBNode : public MachNode { |
| 24142 | private: |
| 24143 | MachOper *_opnd_array[5]; |
| 24144 | public: |
| 24145 | MachOper *opnd_array(uint operand_index) const { |
| 24146 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24147 | return _opnd_array[operand_index]; |
| 24148 | } |
| 24149 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24150 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24151 | _opnd_array[operand_index] = operand; |
| 24152 | } |
| 24153 | private: |
| 24154 | virtual const RegMask &out_RegMask() const; |
| 24155 | virtual uint rule() const { return array_equalsB_rule; } |
| 24156 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24157 | virtual int ideal_Opcode() const { return Op_AryEq; } |
| 24158 | virtual uint oper_input_base() const { return 2; } |
| 24159 | public: |
| 24160 | array_equalsBNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24161 | virtual uint size_of() const { return sizeof(array_equalsBNode); } |
| 24162 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24163 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24164 | static const Pipeline *pipeline_class(); |
| 24165 | virtual const Pipeline *pipeline() const; |
| 24166 | #ifndef PRODUCT |
| 24167 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24168 | virtual const char *Name() const { return "array_equalsB";} |
| 24169 | #endif |
| 24170 | }; |
| 24171 | |
| 24172 | class array_equalsCNode : public MachNode { |
| 24173 | private: |
| 24174 | MachOper *_opnd_array[5]; |
| 24175 | public: |
| 24176 | MachOper *opnd_array(uint operand_index) const { |
| 24177 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24178 | return _opnd_array[operand_index]; |
| 24179 | } |
| 24180 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24181 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24182 | _opnd_array[operand_index] = operand; |
| 24183 | } |
| 24184 | private: |
| 24185 | virtual const RegMask &out_RegMask() const; |
| 24186 | virtual uint rule() const { return array_equalsC_rule; } |
| 24187 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24188 | virtual int ideal_Opcode() const { return Op_AryEq; } |
| 24189 | virtual uint oper_input_base() const { return 2; } |
| 24190 | public: |
| 24191 | array_equalsCNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24192 | virtual uint size_of() const { return sizeof(array_equalsCNode); } |
| 24193 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24194 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24195 | static const Pipeline *pipeline_class(); |
| 24196 | virtual const Pipeline *pipeline() const; |
| 24197 | #ifndef PRODUCT |
| 24198 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24199 | virtual const char *Name() const { return "array_equalsC";} |
| 24200 | #endif |
| 24201 | }; |
| 24202 | |
| 24203 | class has_negativesNode : public MachNode { |
| 24204 | private: |
| 24205 | MachOper *_opnd_array[5]; |
| 24206 | public: |
| 24207 | MachOper *opnd_array(uint operand_index) const { |
| 24208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24209 | return _opnd_array[operand_index]; |
| 24210 | } |
| 24211 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24212 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24213 | _opnd_array[operand_index] = operand; |
| 24214 | } |
| 24215 | private: |
| 24216 | virtual const RegMask &out_RegMask() const; |
| 24217 | virtual uint rule() const { return has_negatives_rule; } |
| 24218 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24219 | virtual int ideal_Opcode() const { return Op_HasNegatives; } |
| 24220 | virtual uint oper_input_base() const { return 2; } |
| 24221 | public: |
| 24222 | has_negativesNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24223 | virtual uint size_of() const { return sizeof(has_negativesNode); } |
| 24224 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24225 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24226 | static const Pipeline *pipeline_class(); |
| 24227 | virtual const Pipeline *pipeline() const; |
| 24228 | #ifndef PRODUCT |
| 24229 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24230 | virtual const char *Name() const { return "has_negatives";} |
| 24231 | #endif |
| 24232 | }; |
| 24233 | |
| 24234 | class string_compressNode : public MachNode { |
| 24235 | private: |
| 24236 | MachOper *_opnd_array[8]; |
| 24237 | public: |
| 24238 | MachOper *opnd_array(uint operand_index) const { |
| 24239 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24240 | return _opnd_array[operand_index]; |
| 24241 | } |
| 24242 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24243 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24244 | _opnd_array[operand_index] = operand; |
| 24245 | } |
| 24246 | private: |
| 24247 | virtual const RegMask &out_RegMask() const; |
| 24248 | virtual uint rule() const { return string_compress_rule; } |
| 24249 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24250 | virtual int ideal_Opcode() const { return Op_StrCompressedCopy; } |
| 24251 | virtual uint oper_input_base() const { return 2; } |
| 24252 | public: |
| 24253 | string_compressNode() { _num_opnds = 8; _opnds = _opnd_array; } |
| 24254 | virtual uint size_of() const { return sizeof(string_compressNode); } |
| 24255 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24256 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24257 | static const Pipeline *pipeline_class(); |
| 24258 | virtual const Pipeline *pipeline() const; |
| 24259 | #ifndef PRODUCT |
| 24260 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24261 | virtual const char *Name() const { return "string_compress";} |
| 24262 | #endif |
| 24263 | }; |
| 24264 | |
| 24265 | class string_inflateNode : public MachNode { |
| 24266 | private: |
| 24267 | MachOper *_opnd_array[6]; |
| 24268 | public: |
| 24269 | MachOper *opnd_array(uint operand_index) const { |
| 24270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24271 | return _opnd_array[operand_index]; |
| 24272 | } |
| 24273 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24274 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24275 | _opnd_array[operand_index] = operand; |
| 24276 | } |
| 24277 | private: |
| 24278 | virtual const RegMask &out_RegMask() const; |
| 24279 | virtual uint rule() const { return string_inflate_rule; } |
| 24280 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24281 | virtual int ideal_Opcode() const { return Op_StrInflatedCopy; } |
| 24282 | virtual uint oper_input_base() const { return 2; } |
| 24283 | public: |
| 24284 | string_inflateNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 24285 | virtual uint size_of() const { return sizeof(string_inflateNode); } |
| 24286 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24287 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24288 | static const Pipeline *pipeline_class(); |
| 24289 | virtual const Pipeline *pipeline() const; |
| 24290 | #ifndef PRODUCT |
| 24291 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24292 | virtual const char *Name() const { return "string_inflate";} |
| 24293 | #endif |
| 24294 | }; |
| 24295 | |
| 24296 | class encode_iso_arrayNode : public MachNode { |
| 24297 | private: |
| 24298 | MachOper *_opnd_array[8]; |
| 24299 | public: |
| 24300 | MachOper *opnd_array(uint operand_index) const { |
| 24301 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24302 | return _opnd_array[operand_index]; |
| 24303 | } |
| 24304 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24305 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24306 | _opnd_array[operand_index] = operand; |
| 24307 | } |
| 24308 | private: |
| 24309 | virtual const RegMask &out_RegMask() const; |
| 24310 | virtual uint rule() const { return encode_iso_array_rule; } |
| 24311 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24312 | virtual int ideal_Opcode() const { return Op_EncodeISOArray; } |
| 24313 | virtual uint oper_input_base() const { return 2; } |
| 24314 | public: |
| 24315 | encode_iso_arrayNode() { _num_opnds = 8; _opnds = _opnd_array; } |
| 24316 | virtual uint size_of() const { return sizeof(encode_iso_arrayNode); } |
| 24317 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24318 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24319 | static const Pipeline *pipeline_class(); |
| 24320 | virtual const Pipeline *pipeline() const; |
| 24321 | #ifndef PRODUCT |
| 24322 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24323 | virtual const char *Name() const { return "encode_iso_array";} |
| 24324 | #endif |
| 24325 | }; |
| 24326 | |
| 24327 | class overflowAddI_rRegNode : public MachNode { |
| 24328 | private: |
| 24329 | MachOper *_opnd_array[3]; |
| 24330 | public: |
| 24331 | MachOper *opnd_array(uint operand_index) const { |
| 24332 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24333 | return _opnd_array[operand_index]; |
| 24334 | } |
| 24335 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24336 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24337 | _opnd_array[operand_index] = operand; |
| 24338 | } |
| 24339 | private: |
| 24340 | virtual const RegMask &out_RegMask() const; |
| 24341 | virtual uint rule() const { return overflowAddI_rReg_rule; } |
| 24342 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24343 | virtual int ideal_Opcode() const { return Op_OverflowAddI; } |
| 24344 | public: |
| 24345 | overflowAddI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24346 | virtual uint size_of() const { return sizeof(overflowAddI_rRegNode); } |
| 24347 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24348 | // Rematerialize overflowAddI_rReg |
| 24349 | static const Pipeline *pipeline_class(); |
| 24350 | virtual const Pipeline *pipeline() const; |
| 24351 | #ifndef PRODUCT |
| 24352 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24353 | virtual const char *Name() const { return "overflowAddI_rReg";} |
| 24354 | #endif |
| 24355 | }; |
| 24356 | |
| 24357 | class overflowAddI_rReg_immNode : public MachNode { |
| 24358 | private: |
| 24359 | MachOper *_opnd_array[3]; |
| 24360 | public: |
| 24361 | MachOper *opnd_array(uint operand_index) const { |
| 24362 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24363 | return _opnd_array[operand_index]; |
| 24364 | } |
| 24365 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24366 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24367 | _opnd_array[operand_index] = operand; |
| 24368 | } |
| 24369 | private: |
| 24370 | virtual const RegMask &out_RegMask() const; |
| 24371 | virtual uint rule() const { return overflowAddI_rReg_imm_rule; } |
| 24372 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24373 | virtual int ideal_Opcode() const { return Op_OverflowAddI; } |
| 24374 | public: |
| 24375 | overflowAddI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24376 | virtual uint size_of() const { return sizeof(overflowAddI_rReg_immNode); } |
| 24377 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24378 | // Rematerialize overflowAddI_rReg_imm |
| 24379 | static const Pipeline *pipeline_class(); |
| 24380 | virtual const Pipeline *pipeline() const; |
| 24381 | #ifndef PRODUCT |
| 24382 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24383 | virtual const char *Name() const { return "overflowAddI_rReg_imm";} |
| 24384 | #endif |
| 24385 | }; |
| 24386 | |
| 24387 | class overflowAddL_rRegNode : public MachNode { |
| 24388 | private: |
| 24389 | MachOper *_opnd_array[3]; |
| 24390 | public: |
| 24391 | MachOper *opnd_array(uint operand_index) const { |
| 24392 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24393 | return _opnd_array[operand_index]; |
| 24394 | } |
| 24395 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24396 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24397 | _opnd_array[operand_index] = operand; |
| 24398 | } |
| 24399 | private: |
| 24400 | virtual const RegMask &out_RegMask() const; |
| 24401 | virtual uint rule() const { return overflowAddL_rReg_rule; } |
| 24402 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24403 | virtual int ideal_Opcode() const { return Op_OverflowAddL; } |
| 24404 | public: |
| 24405 | overflowAddL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24406 | virtual uint size_of() const { return sizeof(overflowAddL_rRegNode); } |
| 24407 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24408 | // Rematerialize overflowAddL_rReg |
| 24409 | static const Pipeline *pipeline_class(); |
| 24410 | virtual const Pipeline *pipeline() const; |
| 24411 | #ifndef PRODUCT |
| 24412 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24413 | virtual const char *Name() const { return "overflowAddL_rReg";} |
| 24414 | #endif |
| 24415 | }; |
| 24416 | |
| 24417 | class overflowAddL_rReg_immNode : public MachNode { |
| 24418 | private: |
| 24419 | MachOper *_opnd_array[3]; |
| 24420 | public: |
| 24421 | MachOper *opnd_array(uint operand_index) const { |
| 24422 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24423 | return _opnd_array[operand_index]; |
| 24424 | } |
| 24425 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24426 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24427 | _opnd_array[operand_index] = operand; |
| 24428 | } |
| 24429 | private: |
| 24430 | virtual const RegMask &out_RegMask() const; |
| 24431 | virtual uint rule() const { return overflowAddL_rReg_imm_rule; } |
| 24432 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24433 | virtual int ideal_Opcode() const { return Op_OverflowAddL; } |
| 24434 | public: |
| 24435 | overflowAddL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24436 | virtual uint size_of() const { return sizeof(overflowAddL_rReg_immNode); } |
| 24437 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24438 | // Rematerialize overflowAddL_rReg_imm |
| 24439 | static const Pipeline *pipeline_class(); |
| 24440 | virtual const Pipeline *pipeline() const; |
| 24441 | #ifndef PRODUCT |
| 24442 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24443 | virtual const char *Name() const { return "overflowAddL_rReg_imm";} |
| 24444 | #endif |
| 24445 | }; |
| 24446 | |
| 24447 | class overflowSubI_rRegNode : public MachNode { |
| 24448 | private: |
| 24449 | MachOper *_opnd_array[3]; |
| 24450 | public: |
| 24451 | MachOper *opnd_array(uint operand_index) const { |
| 24452 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24453 | return _opnd_array[operand_index]; |
| 24454 | } |
| 24455 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24456 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24457 | _opnd_array[operand_index] = operand; |
| 24458 | } |
| 24459 | private: |
| 24460 | virtual const RegMask &out_RegMask() const; |
| 24461 | virtual uint rule() const { return overflowSubI_rReg_rule; } |
| 24462 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24463 | virtual int ideal_Opcode() const { return Op_OverflowSubI; } |
| 24464 | public: |
| 24465 | overflowSubI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24466 | virtual uint size_of() const { return sizeof(overflowSubI_rRegNode); } |
| 24467 | // Rematerialize overflowSubI_rReg |
| 24468 | static const Pipeline *pipeline_class(); |
| 24469 | virtual const Pipeline *pipeline() const; |
| 24470 | #ifndef PRODUCT |
| 24471 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24472 | virtual const char *Name() const { return "overflowSubI_rReg";} |
| 24473 | #endif |
| 24474 | }; |
| 24475 | |
| 24476 | class overflowSubI_rReg_immNode : public MachNode { |
| 24477 | private: |
| 24478 | MachOper *_opnd_array[3]; |
| 24479 | public: |
| 24480 | MachOper *opnd_array(uint operand_index) const { |
| 24481 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24482 | return _opnd_array[operand_index]; |
| 24483 | } |
| 24484 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24485 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24486 | _opnd_array[operand_index] = operand; |
| 24487 | } |
| 24488 | private: |
| 24489 | virtual const RegMask &out_RegMask() const; |
| 24490 | virtual uint rule() const { return overflowSubI_rReg_imm_rule; } |
| 24491 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24492 | virtual int ideal_Opcode() const { return Op_OverflowSubI; } |
| 24493 | public: |
| 24494 | overflowSubI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24495 | virtual uint size_of() const { return sizeof(overflowSubI_rReg_immNode); } |
| 24496 | // Rematerialize overflowSubI_rReg_imm |
| 24497 | static const Pipeline *pipeline_class(); |
| 24498 | virtual const Pipeline *pipeline() const; |
| 24499 | #ifndef PRODUCT |
| 24500 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24501 | virtual const char *Name() const { return "overflowSubI_rReg_imm";} |
| 24502 | #endif |
| 24503 | }; |
| 24504 | |
| 24505 | class overflowSubL_rRegNode : public MachNode { |
| 24506 | private: |
| 24507 | MachOper *_opnd_array[3]; |
| 24508 | public: |
| 24509 | MachOper *opnd_array(uint operand_index) const { |
| 24510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24511 | return _opnd_array[operand_index]; |
| 24512 | } |
| 24513 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24514 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24515 | _opnd_array[operand_index] = operand; |
| 24516 | } |
| 24517 | private: |
| 24518 | virtual const RegMask &out_RegMask() const; |
| 24519 | virtual uint rule() const { return overflowSubL_rReg_rule; } |
| 24520 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24521 | virtual int ideal_Opcode() const { return Op_OverflowSubL; } |
| 24522 | public: |
| 24523 | overflowSubL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24524 | virtual uint size_of() const { return sizeof(overflowSubL_rRegNode); } |
| 24525 | // Rematerialize overflowSubL_rReg |
| 24526 | static const Pipeline *pipeline_class(); |
| 24527 | virtual const Pipeline *pipeline() const; |
| 24528 | #ifndef PRODUCT |
| 24529 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24530 | virtual const char *Name() const { return "overflowSubL_rReg";} |
| 24531 | #endif |
| 24532 | }; |
| 24533 | |
| 24534 | class overflowSubL_rReg_immNode : public MachNode { |
| 24535 | private: |
| 24536 | MachOper *_opnd_array[3]; |
| 24537 | public: |
| 24538 | MachOper *opnd_array(uint operand_index) const { |
| 24539 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24540 | return _opnd_array[operand_index]; |
| 24541 | } |
| 24542 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24543 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24544 | _opnd_array[operand_index] = operand; |
| 24545 | } |
| 24546 | private: |
| 24547 | virtual const RegMask &out_RegMask() const; |
| 24548 | virtual uint rule() const { return overflowSubL_rReg_imm_rule; } |
| 24549 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24550 | virtual int ideal_Opcode() const { return Op_OverflowSubL; } |
| 24551 | public: |
| 24552 | overflowSubL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24553 | virtual uint size_of() const { return sizeof(overflowSubL_rReg_immNode); } |
| 24554 | // Rematerialize overflowSubL_rReg_imm |
| 24555 | static const Pipeline *pipeline_class(); |
| 24556 | virtual const Pipeline *pipeline() const; |
| 24557 | #ifndef PRODUCT |
| 24558 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24559 | virtual const char *Name() const { return "overflowSubL_rReg_imm";} |
| 24560 | #endif |
| 24561 | }; |
| 24562 | |
| 24563 | class overflowNegI_rRegNode : public MachNode { |
| 24564 | private: |
| 24565 | MachOper *_opnd_array[3]; |
| 24566 | public: |
| 24567 | MachOper *opnd_array(uint operand_index) const { |
| 24568 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24569 | return _opnd_array[operand_index]; |
| 24570 | } |
| 24571 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24572 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24573 | _opnd_array[operand_index] = operand; |
| 24574 | } |
| 24575 | private: |
| 24576 | virtual const RegMask &out_RegMask() const; |
| 24577 | virtual uint rule() const { return overflowNegI_rReg_rule; } |
| 24578 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24579 | virtual int ideal_Opcode() const { return Op_OverflowSubI; } |
| 24580 | public: |
| 24581 | overflowNegI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24582 | virtual uint size_of() const { return sizeof(overflowNegI_rRegNode); } |
| 24583 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24584 | // Rematerialize overflowNegI_rReg |
| 24585 | static const Pipeline *pipeline_class(); |
| 24586 | virtual const Pipeline *pipeline() const; |
| 24587 | #ifndef PRODUCT |
| 24588 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24589 | virtual const char *Name() const { return "overflowNegI_rReg";} |
| 24590 | #endif |
| 24591 | }; |
| 24592 | |
| 24593 | class overflowNegL_rRegNode : public MachNode { |
| 24594 | private: |
| 24595 | MachOper *_opnd_array[3]; |
| 24596 | public: |
| 24597 | MachOper *opnd_array(uint operand_index) const { |
| 24598 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24599 | return _opnd_array[operand_index]; |
| 24600 | } |
| 24601 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24602 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24603 | _opnd_array[operand_index] = operand; |
| 24604 | } |
| 24605 | private: |
| 24606 | virtual const RegMask &out_RegMask() const; |
| 24607 | virtual uint rule() const { return overflowNegL_rReg_rule; } |
| 24608 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24609 | virtual int ideal_Opcode() const { return Op_OverflowSubL; } |
| 24610 | public: |
| 24611 | overflowNegL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24612 | virtual uint size_of() const { return sizeof(overflowNegL_rRegNode); } |
| 24613 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24614 | // Rematerialize overflowNegL_rReg |
| 24615 | static const Pipeline *pipeline_class(); |
| 24616 | virtual const Pipeline *pipeline() const; |
| 24617 | #ifndef PRODUCT |
| 24618 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24619 | virtual const char *Name() const { return "overflowNegL_rReg";} |
| 24620 | #endif |
| 24621 | }; |
| 24622 | |
| 24623 | class overflowMulI_rRegNode : public MachNode { |
| 24624 | private: |
| 24625 | MachOper *_opnd_array[3]; |
| 24626 | public: |
| 24627 | MachOper *opnd_array(uint operand_index) const { |
| 24628 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24629 | return _opnd_array[operand_index]; |
| 24630 | } |
| 24631 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24632 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24633 | _opnd_array[operand_index] = operand; |
| 24634 | } |
| 24635 | private: |
| 24636 | virtual const RegMask &out_RegMask() const; |
| 24637 | virtual uint rule() const { return overflowMulI_rReg_rule; } |
| 24638 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24639 | virtual int ideal_Opcode() const { return Op_OverflowMulI; } |
| 24640 | public: |
| 24641 | overflowMulI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24642 | virtual uint size_of() const { return sizeof(overflowMulI_rRegNode); } |
| 24643 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24644 | // Rematerialize overflowMulI_rReg |
| 24645 | static const Pipeline *pipeline_class(); |
| 24646 | virtual const Pipeline *pipeline() const; |
| 24647 | #ifndef PRODUCT |
| 24648 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24649 | virtual const char *Name() const { return "overflowMulI_rReg";} |
| 24650 | #endif |
| 24651 | }; |
| 24652 | |
| 24653 | class overflowMulI_rReg_immNode : public MachNode { |
| 24654 | private: |
| 24655 | MachOper *_opnd_array[4]; |
| 24656 | public: |
| 24657 | MachOper *opnd_array(uint operand_index) const { |
| 24658 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24659 | return _opnd_array[operand_index]; |
| 24660 | } |
| 24661 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24662 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24663 | _opnd_array[operand_index] = operand; |
| 24664 | } |
| 24665 | private: |
| 24666 | virtual const RegMask &out_RegMask() const; |
| 24667 | virtual uint rule() const { return overflowMulI_rReg_imm_rule; } |
| 24668 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24669 | virtual int ideal_Opcode() const { return Op_OverflowMulI; } |
| 24670 | public: |
| 24671 | overflowMulI_rReg_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 24672 | virtual uint size_of() const { return sizeof(overflowMulI_rReg_immNode); } |
| 24673 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24674 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24675 | // Rematerialize overflowMulI_rReg_imm |
| 24676 | static const Pipeline *pipeline_class(); |
| 24677 | virtual const Pipeline *pipeline() const; |
| 24678 | #ifndef PRODUCT |
| 24679 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24680 | virtual const char *Name() const { return "overflowMulI_rReg_imm";} |
| 24681 | #endif |
| 24682 | }; |
| 24683 | |
| 24684 | class overflowMulL_rRegNode : public MachNode { |
| 24685 | private: |
| 24686 | MachOper *_opnd_array[3]; |
| 24687 | public: |
| 24688 | MachOper *opnd_array(uint operand_index) const { |
| 24689 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24690 | return _opnd_array[operand_index]; |
| 24691 | } |
| 24692 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24693 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24694 | _opnd_array[operand_index] = operand; |
| 24695 | } |
| 24696 | private: |
| 24697 | virtual const RegMask &out_RegMask() const; |
| 24698 | virtual uint rule() const { return overflowMulL_rReg_rule; } |
| 24699 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24700 | virtual int ideal_Opcode() const { return Op_OverflowMulL; } |
| 24701 | public: |
| 24702 | overflowMulL_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24703 | virtual uint size_of() const { return sizeof(overflowMulL_rRegNode); } |
| 24704 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24705 | // Rematerialize overflowMulL_rReg |
| 24706 | static const Pipeline *pipeline_class(); |
| 24707 | virtual const Pipeline *pipeline() const; |
| 24708 | #ifndef PRODUCT |
| 24709 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24710 | virtual const char *Name() const { return "overflowMulL_rReg";} |
| 24711 | #endif |
| 24712 | }; |
| 24713 | |
| 24714 | class overflowMulL_rReg_immNode : public MachNode { |
| 24715 | private: |
| 24716 | MachOper *_opnd_array[4]; |
| 24717 | public: |
| 24718 | MachOper *opnd_array(uint operand_index) const { |
| 24719 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24720 | return _opnd_array[operand_index]; |
| 24721 | } |
| 24722 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24723 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24724 | _opnd_array[operand_index] = operand; |
| 24725 | } |
| 24726 | private: |
| 24727 | virtual const RegMask &out_RegMask() const; |
| 24728 | virtual uint rule() const { return overflowMulL_rReg_imm_rule; } |
| 24729 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24730 | virtual int ideal_Opcode() const { return Op_OverflowMulL; } |
| 24731 | public: |
| 24732 | overflowMulL_rReg_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 24733 | virtual uint size_of() const { return sizeof(overflowMulL_rReg_immNode); } |
| 24734 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 24735 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 24736 | // Rematerialize overflowMulL_rReg_imm |
| 24737 | static const Pipeline *pipeline_class(); |
| 24738 | virtual const Pipeline *pipeline() const; |
| 24739 | #ifndef PRODUCT |
| 24740 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24741 | virtual const char *Name() const { return "overflowMulL_rReg_imm";} |
| 24742 | #endif |
| 24743 | }; |
| 24744 | |
| 24745 | class compI_rRegNode : public MachNode { |
| 24746 | private: |
| 24747 | MachOper *_opnd_array[3]; |
| 24748 | public: |
| 24749 | MachOper *opnd_array(uint operand_index) const { |
| 24750 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24751 | return _opnd_array[operand_index]; |
| 24752 | } |
| 24753 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24754 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24755 | _opnd_array[operand_index] = operand; |
| 24756 | } |
| 24757 | private: |
| 24758 | const RegMask *_cisc_RegMask; |
| 24759 | virtual const RegMask &out_RegMask() const; |
| 24760 | virtual uint rule() const { return compI_rReg_rule; } |
| 24761 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24762 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24763 | virtual int cisc_operand() const { return 2; } |
| 24764 | virtual MachNode *cisc_version(int offset); |
| 24765 | virtual void use_cisc_RegMask(); |
| 24766 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 24767 | public: |
| 24768 | compI_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 24769 | virtual uint size_of() const { return sizeof(compI_rRegNode); } |
| 24770 | // Rematerialize compI_rReg |
| 24771 | static const Pipeline *pipeline_class(); |
| 24772 | virtual const Pipeline *pipeline() const; |
| 24773 | #ifndef PRODUCT |
| 24774 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24775 | virtual const char *Name() const { return "compI_rReg";} |
| 24776 | #endif |
| 24777 | }; |
| 24778 | |
| 24779 | class compI_rReg_immNode : public MachNode { |
| 24780 | private: |
| 24781 | MachOper *_opnd_array[3]; |
| 24782 | public: |
| 24783 | MachOper *opnd_array(uint operand_index) const { |
| 24784 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24785 | return _opnd_array[operand_index]; |
| 24786 | } |
| 24787 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24788 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24789 | _opnd_array[operand_index] = operand; |
| 24790 | } |
| 24791 | private: |
| 24792 | virtual const RegMask &out_RegMask() const; |
| 24793 | virtual uint rule() const { return compI_rReg_imm_rule; } |
| 24794 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24795 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24796 | public: |
| 24797 | compI_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24798 | virtual uint size_of() const { return sizeof(compI_rReg_immNode); } |
| 24799 | // Rematerialize compI_rReg_imm |
| 24800 | static const Pipeline *pipeline_class(); |
| 24801 | virtual const Pipeline *pipeline() const; |
| 24802 | #ifndef PRODUCT |
| 24803 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24804 | virtual const char *Name() const { return "compI_rReg_imm";} |
| 24805 | #endif |
| 24806 | }; |
| 24807 | |
| 24808 | class compI_rReg_memNode : public MachNode { |
| 24809 | private: |
| 24810 | MachOper *_opnd_array[3]; |
| 24811 | public: |
| 24812 | MachOper *opnd_array(uint operand_index) const { |
| 24813 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24814 | return _opnd_array[operand_index]; |
| 24815 | } |
| 24816 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24817 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24818 | _opnd_array[operand_index] = operand; |
| 24819 | } |
| 24820 | private: |
| 24821 | virtual const RegMask &out_RegMask() const; |
| 24822 | virtual uint rule() const { return compI_rReg_mem_rule; } |
| 24823 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24824 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24825 | virtual int reloc() const; |
| 24826 | virtual uint oper_input_base() const { return 2; } |
| 24827 | public: |
| 24828 | compI_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 24829 | virtual uint size_of() const { return sizeof(compI_rReg_memNode); } |
| 24830 | // Rematerialize compI_rReg_mem |
| 24831 | static const Pipeline *pipeline_class(); |
| 24832 | virtual const Pipeline *pipeline() const; |
| 24833 | virtual const MachOper *memory_operand() const; |
| 24834 | #ifndef PRODUCT |
| 24835 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24836 | virtual const char *Name() const { return "compI_rReg_mem";} |
| 24837 | #endif |
| 24838 | }; |
| 24839 | |
| 24840 | class testI_regNode : public MachNode { |
| 24841 | private: |
| 24842 | MachOper *_opnd_array[3]; |
| 24843 | public: |
| 24844 | MachOper *opnd_array(uint operand_index) const { |
| 24845 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24846 | return _opnd_array[operand_index]; |
| 24847 | } |
| 24848 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24849 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24850 | _opnd_array[operand_index] = operand; |
| 24851 | } |
| 24852 | private: |
| 24853 | virtual const RegMask &out_RegMask() const; |
| 24854 | virtual uint rule() const { return testI_reg_rule; } |
| 24855 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24856 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24857 | public: |
| 24858 | testI_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 24859 | virtual uint size_of() const { return sizeof(testI_regNode); } |
| 24860 | // Rematerialize testI_reg |
| 24861 | static const Pipeline *pipeline_class(); |
| 24862 | virtual const Pipeline *pipeline() const; |
| 24863 | #ifndef PRODUCT |
| 24864 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24865 | virtual const char *Name() const { return "testI_reg";} |
| 24866 | #endif |
| 24867 | }; |
| 24868 | |
| 24869 | class testI_reg_immNode : public MachNode { |
| 24870 | private: |
| 24871 | MachOper *_opnd_array[4]; |
| 24872 | public: |
| 24873 | MachOper *opnd_array(uint operand_index) const { |
| 24874 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24875 | return _opnd_array[operand_index]; |
| 24876 | } |
| 24877 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24878 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24879 | _opnd_array[operand_index] = operand; |
| 24880 | } |
| 24881 | private: |
| 24882 | virtual const RegMask &out_RegMask() const; |
| 24883 | virtual uint rule() const { return testI_reg_imm_rule; } |
| 24884 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24885 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24886 | public: |
| 24887 | testI_reg_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 24888 | virtual uint size_of() const { return sizeof(testI_reg_immNode); } |
| 24889 | // Rematerialize testI_reg_imm |
| 24890 | static const Pipeline *pipeline_class(); |
| 24891 | virtual const Pipeline *pipeline() const; |
| 24892 | #ifndef PRODUCT |
| 24893 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24894 | virtual const char *Name() const { return "testI_reg_imm";} |
| 24895 | #endif |
| 24896 | }; |
| 24897 | |
| 24898 | class testI_reg_memNode : public MachNode { |
| 24899 | private: |
| 24900 | MachOper *_opnd_array[4]; |
| 24901 | public: |
| 24902 | MachOper *opnd_array(uint operand_index) const { |
| 24903 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24904 | return _opnd_array[operand_index]; |
| 24905 | } |
| 24906 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24907 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24908 | _opnd_array[operand_index] = operand; |
| 24909 | } |
| 24910 | private: |
| 24911 | virtual const RegMask &out_RegMask() const; |
| 24912 | virtual uint rule() const { return testI_reg_mem_rule; } |
| 24913 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24914 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24915 | virtual int reloc() const; |
| 24916 | virtual uint oper_input_base() const { return 2; } |
| 24917 | public: |
| 24918 | testI_reg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24919 | virtual uint size_of() const { return sizeof(testI_reg_memNode); } |
| 24920 | // Rematerialize testI_reg_mem |
| 24921 | static const Pipeline *pipeline_class(); |
| 24922 | virtual const Pipeline *pipeline() const; |
| 24923 | virtual const MachOper *memory_operand() const; |
| 24924 | #ifndef PRODUCT |
| 24925 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24926 | virtual const char *Name() const { return "testI_reg_mem";} |
| 24927 | #endif |
| 24928 | }; |
| 24929 | |
| 24930 | class testI_reg_mem_0Node : public MachNode { |
| 24931 | private: |
| 24932 | MachOper *_opnd_array[4]; |
| 24933 | public: |
| 24934 | MachOper *opnd_array(uint operand_index) const { |
| 24935 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24936 | return _opnd_array[operand_index]; |
| 24937 | } |
| 24938 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24939 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24940 | _opnd_array[operand_index] = operand; |
| 24941 | } |
| 24942 | private: |
| 24943 | virtual const RegMask &out_RegMask() const; |
| 24944 | virtual uint rule() const { return testI_reg_mem_0_rule; } |
| 24945 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24946 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 24947 | virtual int reloc() const; |
| 24948 | virtual uint oper_input_base() const { return 2; } |
| 24949 | public: |
| 24950 | testI_reg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 24951 | virtual uint size_of() const { return sizeof(testI_reg_mem_0Node); } |
| 24952 | // Rematerialize testI_reg_mem_0 |
| 24953 | static const Pipeline *pipeline_class(); |
| 24954 | virtual const Pipeline *pipeline() const; |
| 24955 | virtual const MachOper *memory_operand() const; |
| 24956 | #ifndef PRODUCT |
| 24957 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24958 | virtual const char *Name() const { return "testI_reg_mem_0";} |
| 24959 | #endif |
| 24960 | }; |
| 24961 | |
| 24962 | class compU_rRegNode : public MachNode { |
| 24963 | private: |
| 24964 | MachOper *_opnd_array[3]; |
| 24965 | public: |
| 24966 | MachOper *opnd_array(uint operand_index) const { |
| 24967 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24968 | return _opnd_array[operand_index]; |
| 24969 | } |
| 24970 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 24971 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 24972 | _opnd_array[operand_index] = operand; |
| 24973 | } |
| 24974 | private: |
| 24975 | const RegMask *_cisc_RegMask; |
| 24976 | virtual const RegMask &out_RegMask() const; |
| 24977 | virtual uint rule() const { return compU_rReg_rule; } |
| 24978 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 24979 | virtual int ideal_Opcode() const { return Op_CmpU; } |
| 24980 | virtual int cisc_operand() const { return 2; } |
| 24981 | virtual MachNode *cisc_version(int offset); |
| 24982 | virtual void use_cisc_RegMask(); |
| 24983 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 24984 | public: |
| 24985 | compU_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 24986 | virtual uint size_of() const { return sizeof(compU_rRegNode); } |
| 24987 | // Rematerialize compU_rReg |
| 24988 | static const Pipeline *pipeline_class(); |
| 24989 | virtual const Pipeline *pipeline() const; |
| 24990 | #ifndef PRODUCT |
| 24991 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 24992 | virtual const char *Name() const { return "compU_rReg";} |
| 24993 | #endif |
| 24994 | }; |
| 24995 | |
| 24996 | class compU_rReg_immNode : public MachNode { |
| 24997 | private: |
| 24998 | MachOper *_opnd_array[3]; |
| 24999 | public: |
| 25000 | MachOper *opnd_array(uint operand_index) const { |
| 25001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25002 | return _opnd_array[operand_index]; |
| 25003 | } |
| 25004 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25006 | _opnd_array[operand_index] = operand; |
| 25007 | } |
| 25008 | private: |
| 25009 | virtual const RegMask &out_RegMask() const; |
| 25010 | virtual uint rule() const { return compU_rReg_imm_rule; } |
| 25011 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25012 | virtual int ideal_Opcode() const { return Op_CmpU; } |
| 25013 | public: |
| 25014 | compU_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25015 | virtual uint size_of() const { return sizeof(compU_rReg_immNode); } |
| 25016 | // Rematerialize compU_rReg_imm |
| 25017 | static const Pipeline *pipeline_class(); |
| 25018 | virtual const Pipeline *pipeline() const; |
| 25019 | #ifndef PRODUCT |
| 25020 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25021 | virtual const char *Name() const { return "compU_rReg_imm";} |
| 25022 | #endif |
| 25023 | }; |
| 25024 | |
| 25025 | class compU_rReg_memNode : public MachNode { |
| 25026 | private: |
| 25027 | MachOper *_opnd_array[3]; |
| 25028 | public: |
| 25029 | MachOper *opnd_array(uint operand_index) const { |
| 25030 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25031 | return _opnd_array[operand_index]; |
| 25032 | } |
| 25033 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25034 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25035 | _opnd_array[operand_index] = operand; |
| 25036 | } |
| 25037 | private: |
| 25038 | virtual const RegMask &out_RegMask() const; |
| 25039 | virtual uint rule() const { return compU_rReg_mem_rule; } |
| 25040 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25041 | virtual int ideal_Opcode() const { return Op_CmpU; } |
| 25042 | virtual int reloc() const; |
| 25043 | virtual uint oper_input_base() const { return 2; } |
| 25044 | public: |
| 25045 | compU_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 25046 | virtual uint size_of() const { return sizeof(compU_rReg_memNode); } |
| 25047 | // Rematerialize compU_rReg_mem |
| 25048 | static const Pipeline *pipeline_class(); |
| 25049 | virtual const Pipeline *pipeline() const; |
| 25050 | virtual const MachOper *memory_operand() const; |
| 25051 | #ifndef PRODUCT |
| 25052 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25053 | virtual const char *Name() const { return "compU_rReg_mem";} |
| 25054 | #endif |
| 25055 | }; |
| 25056 | |
| 25057 | class testU_regNode : public MachNode { |
| 25058 | private: |
| 25059 | MachOper *_opnd_array[3]; |
| 25060 | public: |
| 25061 | MachOper *opnd_array(uint operand_index) const { |
| 25062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25063 | return _opnd_array[operand_index]; |
| 25064 | } |
| 25065 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25066 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25067 | _opnd_array[operand_index] = operand; |
| 25068 | } |
| 25069 | private: |
| 25070 | virtual const RegMask &out_RegMask() const; |
| 25071 | virtual uint rule() const { return testU_reg_rule; } |
| 25072 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25073 | virtual int ideal_Opcode() const { return Op_CmpU; } |
| 25074 | public: |
| 25075 | testU_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25076 | virtual uint size_of() const { return sizeof(testU_regNode); } |
| 25077 | // Rematerialize testU_reg |
| 25078 | static const Pipeline *pipeline_class(); |
| 25079 | virtual const Pipeline *pipeline() const; |
| 25080 | #ifndef PRODUCT |
| 25081 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25082 | virtual const char *Name() const { return "testU_reg";} |
| 25083 | #endif |
| 25084 | }; |
| 25085 | |
| 25086 | class compP_rRegNode : public MachNode { |
| 25087 | private: |
| 25088 | MachOper *_opnd_array[3]; |
| 25089 | public: |
| 25090 | MachOper *opnd_array(uint operand_index) const { |
| 25091 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25092 | return _opnd_array[operand_index]; |
| 25093 | } |
| 25094 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25095 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25096 | _opnd_array[operand_index] = operand; |
| 25097 | } |
| 25098 | private: |
| 25099 | const RegMask *_cisc_RegMask; |
| 25100 | virtual const RegMask &out_RegMask() const; |
| 25101 | virtual uint rule() const { return compP_rReg_rule; } |
| 25102 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25103 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25104 | virtual int cisc_operand() const { return 2; } |
| 25105 | virtual MachNode *cisc_version(int offset); |
| 25106 | virtual void use_cisc_RegMask(); |
| 25107 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 25108 | public: |
| 25109 | compP_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 25110 | virtual uint size_of() const { return sizeof(compP_rRegNode); } |
| 25111 | // Rematerialize compP_rReg |
| 25112 | static const Pipeline *pipeline_class(); |
| 25113 | virtual const Pipeline *pipeline() const; |
| 25114 | #ifndef PRODUCT |
| 25115 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25116 | virtual const char *Name() const { return "compP_rReg";} |
| 25117 | #endif |
| 25118 | }; |
| 25119 | |
| 25120 | class compP_rReg_memNode : public MachNode { |
| 25121 | private: |
| 25122 | MachOper *_opnd_array[3]; |
| 25123 | public: |
| 25124 | MachOper *opnd_array(uint operand_index) const { |
| 25125 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25126 | return _opnd_array[operand_index]; |
| 25127 | } |
| 25128 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25129 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25130 | _opnd_array[operand_index] = operand; |
| 25131 | } |
| 25132 | private: |
| 25133 | virtual const RegMask &out_RegMask() const; |
| 25134 | virtual uint rule() const { return compP_rReg_mem_rule; } |
| 25135 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25136 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25137 | virtual int reloc() const; |
| 25138 | virtual uint oper_input_base() const { return 2; } |
| 25139 | public: |
| 25140 | compP_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 25141 | virtual uint size_of() const { return sizeof(compP_rReg_memNode); } |
| 25142 | // Rematerialize compP_rReg_mem |
| 25143 | static const Pipeline *pipeline_class(); |
| 25144 | virtual const Pipeline *pipeline() const; |
| 25145 | virtual const MachOper *memory_operand() const; |
| 25146 | #ifndef PRODUCT |
| 25147 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25148 | virtual const char *Name() const { return "compP_rReg_mem";} |
| 25149 | #endif |
| 25150 | }; |
| 25151 | |
| 25152 | class compP_mem_rRegNode : public MachNode { |
| 25153 | private: |
| 25154 | MachOper *_opnd_array[3]; |
| 25155 | public: |
| 25156 | MachOper *opnd_array(uint operand_index) const { |
| 25157 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25158 | return _opnd_array[operand_index]; |
| 25159 | } |
| 25160 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25161 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25162 | _opnd_array[operand_index] = operand; |
| 25163 | } |
| 25164 | private: |
| 25165 | virtual const RegMask &out_RegMask() const; |
| 25166 | virtual uint rule() const { return compP_mem_rReg_rule; } |
| 25167 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25168 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25169 | virtual int reloc() const; |
| 25170 | virtual uint oper_input_base() const { return 2; } |
| 25171 | public: |
| 25172 | compP_mem_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25173 | virtual uint size_of() const { return sizeof(compP_mem_rRegNode); } |
| 25174 | // Rematerialize compP_mem_rReg |
| 25175 | static const Pipeline *pipeline_class(); |
| 25176 | virtual const Pipeline *pipeline() const; |
| 25177 | virtual const MachOper *memory_operand() const; |
| 25178 | #ifndef PRODUCT |
| 25179 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25180 | virtual const char *Name() const { return "compP_mem_rReg";} |
| 25181 | #endif |
| 25182 | }; |
| 25183 | |
| 25184 | class testP_regNode : public MachNode { |
| 25185 | private: |
| 25186 | MachOper *_opnd_array[3]; |
| 25187 | public: |
| 25188 | MachOper *opnd_array(uint operand_index) const { |
| 25189 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25190 | return _opnd_array[operand_index]; |
| 25191 | } |
| 25192 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25193 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25194 | _opnd_array[operand_index] = operand; |
| 25195 | } |
| 25196 | private: |
| 25197 | virtual const RegMask &out_RegMask() const; |
| 25198 | virtual uint rule() const { return testP_reg_rule; } |
| 25199 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25200 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25201 | virtual int reloc() const; |
| 25202 | public: |
| 25203 | testP_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25204 | virtual uint size_of() const { return sizeof(testP_regNode); } |
| 25205 | // Rematerialize testP_reg |
| 25206 | static const Pipeline *pipeline_class(); |
| 25207 | virtual const Pipeline *pipeline() const; |
| 25208 | #ifndef PRODUCT |
| 25209 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25210 | virtual const char *Name() const { return "testP_reg";} |
| 25211 | #endif |
| 25212 | }; |
| 25213 | |
| 25214 | class testP_memNode : public MachNode { |
| 25215 | private: |
| 25216 | MachOper *_opnd_array[3]; |
| 25217 | public: |
| 25218 | MachOper *opnd_array(uint operand_index) const { |
| 25219 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25220 | return _opnd_array[operand_index]; |
| 25221 | } |
| 25222 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25223 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25224 | _opnd_array[operand_index] = operand; |
| 25225 | } |
| 25226 | private: |
| 25227 | virtual const RegMask &out_RegMask() const; |
| 25228 | virtual uint rule() const { return testP_mem_rule; } |
| 25229 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25230 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25231 | virtual int reloc() const; |
| 25232 | virtual uint oper_input_base() const { return 2; } |
| 25233 | public: |
| 25234 | testP_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25235 | virtual uint size_of() const { return sizeof(testP_memNode); } |
| 25236 | // Rematerialize testP_mem |
| 25237 | static const Pipeline *pipeline_class(); |
| 25238 | virtual const Pipeline *pipeline() const; |
| 25239 | virtual const MachOper *memory_operand() const; |
| 25240 | #ifndef PRODUCT |
| 25241 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25242 | virtual const char *Name() const { return "testP_mem";} |
| 25243 | #endif |
| 25244 | }; |
| 25245 | |
| 25246 | class testP_mem_reg0Node : public MachNode { |
| 25247 | private: |
| 25248 | MachOper *_opnd_array[3]; |
| 25249 | public: |
| 25250 | MachOper *opnd_array(uint operand_index) const { |
| 25251 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25252 | return _opnd_array[operand_index]; |
| 25253 | } |
| 25254 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25255 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25256 | _opnd_array[operand_index] = operand; |
| 25257 | } |
| 25258 | private: |
| 25259 | virtual const RegMask &out_RegMask() const; |
| 25260 | virtual uint rule() const { return testP_mem_reg0_rule; } |
| 25261 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25262 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 25263 | virtual int reloc() const; |
| 25264 | virtual uint oper_input_base() const { return 2; } |
| 25265 | public: |
| 25266 | testP_mem_reg0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25267 | virtual uint size_of() const { return sizeof(testP_mem_reg0Node); } |
| 25268 | // Rematerialize testP_mem_reg0 |
| 25269 | static const Pipeline *pipeline_class(); |
| 25270 | virtual const Pipeline *pipeline() const; |
| 25271 | virtual const MachOper *memory_operand() const; |
| 25272 | #ifndef PRODUCT |
| 25273 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25274 | virtual const char *Name() const { return "testP_mem_reg0";} |
| 25275 | #endif |
| 25276 | }; |
| 25277 | |
| 25278 | class compN_rRegNode : public MachNode { |
| 25279 | private: |
| 25280 | MachOper *_opnd_array[3]; |
| 25281 | public: |
| 25282 | MachOper *opnd_array(uint operand_index) const { |
| 25283 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25284 | return _opnd_array[operand_index]; |
| 25285 | } |
| 25286 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25287 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25288 | _opnd_array[operand_index] = operand; |
| 25289 | } |
| 25290 | private: |
| 25291 | virtual const RegMask &out_RegMask() const; |
| 25292 | virtual uint rule() const { return compN_rReg_rule; } |
| 25293 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25294 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25295 | public: |
| 25296 | compN_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25297 | virtual uint size_of() const { return sizeof(compN_rRegNode); } |
| 25298 | // Rematerialize compN_rReg |
| 25299 | static const Pipeline *pipeline_class(); |
| 25300 | virtual const Pipeline *pipeline() const; |
| 25301 | #ifndef PRODUCT |
| 25302 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25303 | virtual const char *Name() const { return "compN_rReg";} |
| 25304 | #endif |
| 25305 | }; |
| 25306 | |
| 25307 | class compN_rReg_memNode : public MachNode { |
| 25308 | private: |
| 25309 | MachOper *_opnd_array[3]; |
| 25310 | public: |
| 25311 | MachOper *opnd_array(uint operand_index) const { |
| 25312 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25313 | return _opnd_array[operand_index]; |
| 25314 | } |
| 25315 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25316 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25317 | _opnd_array[operand_index] = operand; |
| 25318 | } |
| 25319 | private: |
| 25320 | virtual const RegMask &out_RegMask() const; |
| 25321 | virtual uint rule() const { return compN_rReg_mem_rule; } |
| 25322 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25323 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25324 | virtual int reloc() const; |
| 25325 | virtual uint oper_input_base() const { return 2; } |
| 25326 | public: |
| 25327 | compN_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25328 | virtual uint size_of() const { return sizeof(compN_rReg_memNode); } |
| 25329 | // Rematerialize compN_rReg_mem |
| 25330 | static const Pipeline *pipeline_class(); |
| 25331 | virtual const Pipeline *pipeline() const; |
| 25332 | virtual const MachOper *memory_operand() const; |
| 25333 | #ifndef PRODUCT |
| 25334 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25335 | virtual const char *Name() const { return "compN_rReg_mem";} |
| 25336 | #endif |
| 25337 | }; |
| 25338 | |
| 25339 | class compN_rReg_immNode : public MachNode { |
| 25340 | private: |
| 25341 | MachOper *_opnd_array[3]; |
| 25342 | public: |
| 25343 | MachOper *opnd_array(uint operand_index) const { |
| 25344 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25345 | return _opnd_array[operand_index]; |
| 25346 | } |
| 25347 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25348 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25349 | _opnd_array[operand_index] = operand; |
| 25350 | } |
| 25351 | private: |
| 25352 | virtual const RegMask &out_RegMask() const; |
| 25353 | virtual uint rule() const { return compN_rReg_imm_rule; } |
| 25354 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25355 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25356 | public: |
| 25357 | compN_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25358 | virtual uint size_of() const { return sizeof(compN_rReg_immNode); } |
| 25359 | // Rematerialize compN_rReg_imm |
| 25360 | static const Pipeline *pipeline_class(); |
| 25361 | virtual const Pipeline *pipeline() const; |
| 25362 | #ifndef PRODUCT |
| 25363 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25364 | virtual const char *Name() const { return "compN_rReg_imm";} |
| 25365 | #endif |
| 25366 | }; |
| 25367 | |
| 25368 | class compN_mem_immNode : public MachNode { |
| 25369 | private: |
| 25370 | MachOper *_opnd_array[3]; |
| 25371 | public: |
| 25372 | MachOper *opnd_array(uint operand_index) const { |
| 25373 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25374 | return _opnd_array[operand_index]; |
| 25375 | } |
| 25376 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25377 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25378 | _opnd_array[operand_index] = operand; |
| 25379 | } |
| 25380 | private: |
| 25381 | virtual const RegMask &out_RegMask() const; |
| 25382 | virtual uint rule() const { return compN_mem_imm_rule; } |
| 25383 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25384 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25385 | virtual int reloc() const; |
| 25386 | virtual uint oper_input_base() const { return 2; } |
| 25387 | public: |
| 25388 | compN_mem_immNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25389 | virtual uint size_of() const { return sizeof(compN_mem_immNode); } |
| 25390 | // Rematerialize compN_mem_imm |
| 25391 | static const Pipeline *pipeline_class(); |
| 25392 | virtual const Pipeline *pipeline() const; |
| 25393 | virtual const MachOper *memory_operand() const; |
| 25394 | #ifndef PRODUCT |
| 25395 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25396 | virtual const char *Name() const { return "compN_mem_imm";} |
| 25397 | #endif |
| 25398 | }; |
| 25399 | |
| 25400 | class compN_rReg_imm_klassNode : public MachNode { |
| 25401 | private: |
| 25402 | MachOper *_opnd_array[3]; |
| 25403 | public: |
| 25404 | MachOper *opnd_array(uint operand_index) const { |
| 25405 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25406 | return _opnd_array[operand_index]; |
| 25407 | } |
| 25408 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25409 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25410 | _opnd_array[operand_index] = operand; |
| 25411 | } |
| 25412 | private: |
| 25413 | virtual const RegMask &out_RegMask() const; |
| 25414 | virtual uint rule() const { return compN_rReg_imm_klass_rule; } |
| 25415 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25416 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25417 | public: |
| 25418 | compN_rReg_imm_klassNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25419 | virtual uint size_of() const { return sizeof(compN_rReg_imm_klassNode); } |
| 25420 | // Rematerialize compN_rReg_imm_klass |
| 25421 | static const Pipeline *pipeline_class(); |
| 25422 | virtual const Pipeline *pipeline() const; |
| 25423 | #ifndef PRODUCT |
| 25424 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25425 | virtual const char *Name() const { return "compN_rReg_imm_klass";} |
| 25426 | #endif |
| 25427 | }; |
| 25428 | |
| 25429 | class compN_mem_imm_klassNode : public MachNode { |
| 25430 | private: |
| 25431 | MachOper *_opnd_array[3]; |
| 25432 | public: |
| 25433 | MachOper *opnd_array(uint operand_index) const { |
| 25434 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25435 | return _opnd_array[operand_index]; |
| 25436 | } |
| 25437 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25438 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25439 | _opnd_array[operand_index] = operand; |
| 25440 | } |
| 25441 | private: |
| 25442 | virtual const RegMask &out_RegMask() const; |
| 25443 | virtual uint rule() const { return compN_mem_imm_klass_rule; } |
| 25444 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25445 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25446 | virtual int reloc() const; |
| 25447 | virtual uint oper_input_base() const { return 2; } |
| 25448 | public: |
| 25449 | compN_mem_imm_klassNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25450 | virtual uint size_of() const { return sizeof(compN_mem_imm_klassNode); } |
| 25451 | // Rematerialize compN_mem_imm_klass |
| 25452 | static const Pipeline *pipeline_class(); |
| 25453 | virtual const Pipeline *pipeline() const; |
| 25454 | virtual const MachOper *memory_operand() const; |
| 25455 | #ifndef PRODUCT |
| 25456 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25457 | virtual const char *Name() const { return "compN_mem_imm_klass";} |
| 25458 | #endif |
| 25459 | }; |
| 25460 | |
| 25461 | class testN_regNode : public MachNode { |
| 25462 | private: |
| 25463 | MachOper *_opnd_array[3]; |
| 25464 | public: |
| 25465 | MachOper *opnd_array(uint operand_index) const { |
| 25466 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25467 | return _opnd_array[operand_index]; |
| 25468 | } |
| 25469 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25470 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25471 | _opnd_array[operand_index] = operand; |
| 25472 | } |
| 25473 | private: |
| 25474 | virtual const RegMask &out_RegMask() const; |
| 25475 | virtual uint rule() const { return testN_reg_rule; } |
| 25476 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25477 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25478 | public: |
| 25479 | testN_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25480 | virtual uint size_of() const { return sizeof(testN_regNode); } |
| 25481 | // Rematerialize testN_reg |
| 25482 | static const Pipeline *pipeline_class(); |
| 25483 | virtual const Pipeline *pipeline() const; |
| 25484 | #ifndef PRODUCT |
| 25485 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25486 | virtual const char *Name() const { return "testN_reg";} |
| 25487 | #endif |
| 25488 | }; |
| 25489 | |
| 25490 | class testN_memNode : public MachNode { |
| 25491 | private: |
| 25492 | MachOper *_opnd_array[3]; |
| 25493 | public: |
| 25494 | MachOper *opnd_array(uint operand_index) const { |
| 25495 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25496 | return _opnd_array[operand_index]; |
| 25497 | } |
| 25498 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25499 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25500 | _opnd_array[operand_index] = operand; |
| 25501 | } |
| 25502 | private: |
| 25503 | virtual const RegMask &out_RegMask() const; |
| 25504 | virtual uint rule() const { return testN_mem_rule; } |
| 25505 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25506 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25507 | virtual int reloc() const; |
| 25508 | virtual uint oper_input_base() const { return 2; } |
| 25509 | public: |
| 25510 | testN_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25511 | virtual uint size_of() const { return sizeof(testN_memNode); } |
| 25512 | // Rematerialize testN_mem |
| 25513 | static const Pipeline *pipeline_class(); |
| 25514 | virtual const Pipeline *pipeline() const; |
| 25515 | virtual const MachOper *memory_operand() const; |
| 25516 | #ifndef PRODUCT |
| 25517 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25518 | virtual const char *Name() const { return "testN_mem";} |
| 25519 | #endif |
| 25520 | }; |
| 25521 | |
| 25522 | class testN_mem_reg0Node : public MachNode { |
| 25523 | private: |
| 25524 | MachOper *_opnd_array[3]; |
| 25525 | public: |
| 25526 | MachOper *opnd_array(uint operand_index) const { |
| 25527 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25528 | return _opnd_array[operand_index]; |
| 25529 | } |
| 25530 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25531 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25532 | _opnd_array[operand_index] = operand; |
| 25533 | } |
| 25534 | private: |
| 25535 | virtual const RegMask &out_RegMask() const; |
| 25536 | virtual uint rule() const { return testN_mem_reg0_rule; } |
| 25537 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25538 | virtual int ideal_Opcode() const { return Op_CmpN; } |
| 25539 | virtual int reloc() const; |
| 25540 | virtual uint oper_input_base() const { return 2; } |
| 25541 | public: |
| 25542 | testN_mem_reg0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25543 | virtual uint size_of() const { return sizeof(testN_mem_reg0Node); } |
| 25544 | // Rematerialize testN_mem_reg0 |
| 25545 | static const Pipeline *pipeline_class(); |
| 25546 | virtual const Pipeline *pipeline() const; |
| 25547 | virtual const MachOper *memory_operand() const; |
| 25548 | #ifndef PRODUCT |
| 25549 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25550 | virtual const char *Name() const { return "testN_mem_reg0";} |
| 25551 | #endif |
| 25552 | }; |
| 25553 | |
| 25554 | class compL_rRegNode : public MachNode { |
| 25555 | private: |
| 25556 | MachOper *_opnd_array[3]; |
| 25557 | public: |
| 25558 | MachOper *opnd_array(uint operand_index) const { |
| 25559 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25560 | return _opnd_array[operand_index]; |
| 25561 | } |
| 25562 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25563 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25564 | _opnd_array[operand_index] = operand; |
| 25565 | } |
| 25566 | private: |
| 25567 | const RegMask *_cisc_RegMask; |
| 25568 | virtual const RegMask &out_RegMask() const; |
| 25569 | virtual uint rule() const { return compL_rReg_rule; } |
| 25570 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25571 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25572 | virtual int cisc_operand() const { return 2; } |
| 25573 | virtual MachNode *cisc_version(int offset); |
| 25574 | virtual void use_cisc_RegMask(); |
| 25575 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 25576 | public: |
| 25577 | compL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 25578 | virtual uint size_of() const { return sizeof(compL_rRegNode); } |
| 25579 | // Rematerialize compL_rReg |
| 25580 | static const Pipeline *pipeline_class(); |
| 25581 | virtual const Pipeline *pipeline() const; |
| 25582 | #ifndef PRODUCT |
| 25583 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25584 | virtual const char *Name() const { return "compL_rReg";} |
| 25585 | #endif |
| 25586 | }; |
| 25587 | |
| 25588 | class compL_rReg_immNode : public MachNode { |
| 25589 | private: |
| 25590 | MachOper *_opnd_array[3]; |
| 25591 | public: |
| 25592 | MachOper *opnd_array(uint operand_index) const { |
| 25593 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25594 | return _opnd_array[operand_index]; |
| 25595 | } |
| 25596 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25597 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25598 | _opnd_array[operand_index] = operand; |
| 25599 | } |
| 25600 | private: |
| 25601 | virtual const RegMask &out_RegMask() const; |
| 25602 | virtual uint rule() const { return compL_rReg_imm_rule; } |
| 25603 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25604 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25605 | public: |
| 25606 | compL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25607 | virtual uint size_of() const { return sizeof(compL_rReg_immNode); } |
| 25608 | // Rematerialize compL_rReg_imm |
| 25609 | static const Pipeline *pipeline_class(); |
| 25610 | virtual const Pipeline *pipeline() const; |
| 25611 | #ifndef PRODUCT |
| 25612 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25613 | virtual const char *Name() const { return "compL_rReg_imm";} |
| 25614 | #endif |
| 25615 | }; |
| 25616 | |
| 25617 | class compL_rReg_memNode : public MachNode { |
| 25618 | private: |
| 25619 | MachOper *_opnd_array[3]; |
| 25620 | public: |
| 25621 | MachOper *opnd_array(uint operand_index) const { |
| 25622 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25623 | return _opnd_array[operand_index]; |
| 25624 | } |
| 25625 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25626 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25627 | _opnd_array[operand_index] = operand; |
| 25628 | } |
| 25629 | private: |
| 25630 | virtual const RegMask &out_RegMask() const; |
| 25631 | virtual uint rule() const { return compL_rReg_mem_rule; } |
| 25632 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25633 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25634 | virtual int reloc() const; |
| 25635 | virtual uint oper_input_base() const { return 2; } |
| 25636 | public: |
| 25637 | compL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 25638 | virtual uint size_of() const { return sizeof(compL_rReg_memNode); } |
| 25639 | // Rematerialize compL_rReg_mem |
| 25640 | static const Pipeline *pipeline_class(); |
| 25641 | virtual const Pipeline *pipeline() const; |
| 25642 | virtual const MachOper *memory_operand() const; |
| 25643 | #ifndef PRODUCT |
| 25644 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25645 | virtual const char *Name() const { return "compL_rReg_mem";} |
| 25646 | #endif |
| 25647 | }; |
| 25648 | |
| 25649 | class testL_regNode : public MachNode { |
| 25650 | private: |
| 25651 | MachOper *_opnd_array[3]; |
| 25652 | public: |
| 25653 | MachOper *opnd_array(uint operand_index) const { |
| 25654 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25655 | return _opnd_array[operand_index]; |
| 25656 | } |
| 25657 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25658 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25659 | _opnd_array[operand_index] = operand; |
| 25660 | } |
| 25661 | private: |
| 25662 | virtual const RegMask &out_RegMask() const; |
| 25663 | virtual uint rule() const { return testL_reg_rule; } |
| 25664 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25665 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25666 | public: |
| 25667 | testL_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25668 | virtual uint size_of() const { return sizeof(testL_regNode); } |
| 25669 | // Rematerialize testL_reg |
| 25670 | static const Pipeline *pipeline_class(); |
| 25671 | virtual const Pipeline *pipeline() const; |
| 25672 | #ifndef PRODUCT |
| 25673 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25674 | virtual const char *Name() const { return "testL_reg";} |
| 25675 | #endif |
| 25676 | }; |
| 25677 | |
| 25678 | class testL_reg_immNode : public MachNode { |
| 25679 | private: |
| 25680 | MachOper *_opnd_array[4]; |
| 25681 | public: |
| 25682 | MachOper *opnd_array(uint operand_index) const { |
| 25683 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25684 | return _opnd_array[operand_index]; |
| 25685 | } |
| 25686 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25687 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25688 | _opnd_array[operand_index] = operand; |
| 25689 | } |
| 25690 | private: |
| 25691 | virtual const RegMask &out_RegMask() const; |
| 25692 | virtual uint rule() const { return testL_reg_imm_rule; } |
| 25693 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25694 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25695 | public: |
| 25696 | testL_reg_immNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 25697 | virtual uint size_of() const { return sizeof(testL_reg_immNode); } |
| 25698 | // Rematerialize testL_reg_imm |
| 25699 | static const Pipeline *pipeline_class(); |
| 25700 | virtual const Pipeline *pipeline() const; |
| 25701 | #ifndef PRODUCT |
| 25702 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25703 | virtual const char *Name() const { return "testL_reg_imm";} |
| 25704 | #endif |
| 25705 | }; |
| 25706 | |
| 25707 | class testL_reg_memNode : public MachNode { |
| 25708 | private: |
| 25709 | MachOper *_opnd_array[4]; |
| 25710 | public: |
| 25711 | MachOper *opnd_array(uint operand_index) const { |
| 25712 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25713 | return _opnd_array[operand_index]; |
| 25714 | } |
| 25715 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25716 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25717 | _opnd_array[operand_index] = operand; |
| 25718 | } |
| 25719 | private: |
| 25720 | virtual const RegMask &out_RegMask() const; |
| 25721 | virtual uint rule() const { return testL_reg_mem_rule; } |
| 25722 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25723 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25724 | virtual int reloc() const; |
| 25725 | virtual uint oper_input_base() const { return 2; } |
| 25726 | public: |
| 25727 | testL_reg_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25728 | virtual uint size_of() const { return sizeof(testL_reg_memNode); } |
| 25729 | // Rematerialize testL_reg_mem |
| 25730 | static const Pipeline *pipeline_class(); |
| 25731 | virtual const Pipeline *pipeline() const; |
| 25732 | virtual const MachOper *memory_operand() const; |
| 25733 | #ifndef PRODUCT |
| 25734 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25735 | virtual const char *Name() const { return "testL_reg_mem";} |
| 25736 | #endif |
| 25737 | }; |
| 25738 | |
| 25739 | class testL_reg_mem_0Node : public MachNode { |
| 25740 | private: |
| 25741 | MachOper *_opnd_array[4]; |
| 25742 | public: |
| 25743 | MachOper *opnd_array(uint operand_index) const { |
| 25744 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25745 | return _opnd_array[operand_index]; |
| 25746 | } |
| 25747 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25748 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25749 | _opnd_array[operand_index] = operand; |
| 25750 | } |
| 25751 | private: |
| 25752 | virtual const RegMask &out_RegMask() const; |
| 25753 | virtual uint rule() const { return testL_reg_mem_0_rule; } |
| 25754 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25755 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25756 | virtual int reloc() const; |
| 25757 | virtual uint oper_input_base() const { return 2; } |
| 25758 | public: |
| 25759 | testL_reg_mem_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25760 | virtual uint size_of() const { return sizeof(testL_reg_mem_0Node); } |
| 25761 | // Rematerialize testL_reg_mem_0 |
| 25762 | static const Pipeline *pipeline_class(); |
| 25763 | virtual const Pipeline *pipeline() const; |
| 25764 | virtual const MachOper *memory_operand() const; |
| 25765 | #ifndef PRODUCT |
| 25766 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25767 | virtual const char *Name() const { return "testL_reg_mem_0";} |
| 25768 | #endif |
| 25769 | }; |
| 25770 | |
| 25771 | class testL_reg_mem2Node : public MachNode { |
| 25772 | private: |
| 25773 | MachOper *_opnd_array[4]; |
| 25774 | public: |
| 25775 | MachOper *opnd_array(uint operand_index) const { |
| 25776 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25777 | return _opnd_array[operand_index]; |
| 25778 | } |
| 25779 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25780 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25781 | _opnd_array[operand_index] = operand; |
| 25782 | } |
| 25783 | private: |
| 25784 | virtual const RegMask &out_RegMask() const; |
| 25785 | virtual uint rule() const { return testL_reg_mem2_rule; } |
| 25786 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25787 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25788 | virtual int reloc() const; |
| 25789 | virtual uint oper_input_base() const { return 2; } |
| 25790 | public: |
| 25791 | testL_reg_mem2Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25792 | virtual uint size_of() const { return sizeof(testL_reg_mem2Node); } |
| 25793 | // Rematerialize testL_reg_mem2 |
| 25794 | static const Pipeline *pipeline_class(); |
| 25795 | virtual const Pipeline *pipeline() const; |
| 25796 | virtual const MachOper *memory_operand() const; |
| 25797 | #ifndef PRODUCT |
| 25798 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25799 | virtual const char *Name() const { return "testL_reg_mem2";} |
| 25800 | #endif |
| 25801 | }; |
| 25802 | |
| 25803 | class testL_reg_mem2_0Node : public MachNode { |
| 25804 | private: |
| 25805 | MachOper *_opnd_array[4]; |
| 25806 | public: |
| 25807 | MachOper *opnd_array(uint operand_index) const { |
| 25808 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25809 | return _opnd_array[operand_index]; |
| 25810 | } |
| 25811 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25813 | _opnd_array[operand_index] = operand; |
| 25814 | } |
| 25815 | private: |
| 25816 | virtual const RegMask &out_RegMask() const; |
| 25817 | virtual uint rule() const { return testL_reg_mem2_0_rule; } |
| 25818 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25819 | virtual int ideal_Opcode() const { return Op_CmpL; } |
| 25820 | virtual int reloc() const; |
| 25821 | virtual uint oper_input_base() const { return 2; } |
| 25822 | public: |
| 25823 | testL_reg_mem2_0Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 25824 | virtual uint size_of() const { return sizeof(testL_reg_mem2_0Node); } |
| 25825 | // Rematerialize testL_reg_mem2_0 |
| 25826 | static const Pipeline *pipeline_class(); |
| 25827 | virtual const Pipeline *pipeline() const; |
| 25828 | virtual const MachOper *memory_operand() const; |
| 25829 | #ifndef PRODUCT |
| 25830 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25831 | virtual const char *Name() const { return "testL_reg_mem2_0";} |
| 25832 | #endif |
| 25833 | }; |
| 25834 | |
| 25835 | class cmpL3_reg_regNode : public MachNode { |
| 25836 | private: |
| 25837 | MachOper *_opnd_array[3]; |
| 25838 | public: |
| 25839 | MachOper *opnd_array(uint operand_index) const { |
| 25840 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25841 | return _opnd_array[operand_index]; |
| 25842 | } |
| 25843 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25845 | _opnd_array[operand_index] = operand; |
| 25846 | } |
| 25847 | private: |
| 25848 | virtual const RegMask &out_RegMask() const; |
| 25849 | virtual uint rule() const { return cmpL3_reg_reg_rule; } |
| 25850 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25851 | virtual int ideal_Opcode() const { return Op_CmpL3; } |
| 25852 | public: |
| 25853 | cmpL3_reg_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25854 | virtual uint size_of() const { return sizeof(cmpL3_reg_regNode); } |
| 25855 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 25856 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 25857 | static const Pipeline *pipeline_class(); |
| 25858 | virtual const Pipeline *pipeline() const; |
| 25859 | #ifndef PRODUCT |
| 25860 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25861 | virtual const char *Name() const { return "cmpL3_reg_reg";} |
| 25862 | #endif |
| 25863 | }; |
| 25864 | |
| 25865 | class compUL_rRegNode : public MachNode { |
| 25866 | private: |
| 25867 | MachOper *_opnd_array[3]; |
| 25868 | public: |
| 25869 | MachOper *opnd_array(uint operand_index) const { |
| 25870 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25871 | return _opnd_array[operand_index]; |
| 25872 | } |
| 25873 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25874 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25875 | _opnd_array[operand_index] = operand; |
| 25876 | } |
| 25877 | private: |
| 25878 | const RegMask *_cisc_RegMask; |
| 25879 | virtual const RegMask &out_RegMask() const; |
| 25880 | virtual uint rule() const { return compUL_rReg_rule; } |
| 25881 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25882 | virtual int ideal_Opcode() const { return Op_CmpUL; } |
| 25883 | virtual int cisc_operand() const { return 2; } |
| 25884 | virtual MachNode *cisc_version(int offset); |
| 25885 | virtual void use_cisc_RegMask(); |
| 25886 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 25887 | public: |
| 25888 | compUL_rRegNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 25889 | virtual uint size_of() const { return sizeof(compUL_rRegNode); } |
| 25890 | // Rematerialize compUL_rReg |
| 25891 | static const Pipeline *pipeline_class(); |
| 25892 | virtual const Pipeline *pipeline() const; |
| 25893 | #ifndef PRODUCT |
| 25894 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25895 | virtual const char *Name() const { return "compUL_rReg";} |
| 25896 | #endif |
| 25897 | }; |
| 25898 | |
| 25899 | class compUL_rReg_immNode : public MachNode { |
| 25900 | private: |
| 25901 | MachOper *_opnd_array[3]; |
| 25902 | public: |
| 25903 | MachOper *opnd_array(uint operand_index) const { |
| 25904 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25905 | return _opnd_array[operand_index]; |
| 25906 | } |
| 25907 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25908 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25909 | _opnd_array[operand_index] = operand; |
| 25910 | } |
| 25911 | private: |
| 25912 | virtual const RegMask &out_RegMask() const; |
| 25913 | virtual uint rule() const { return compUL_rReg_imm_rule; } |
| 25914 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25915 | virtual int ideal_Opcode() const { return Op_CmpUL; } |
| 25916 | public: |
| 25917 | compUL_rReg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25918 | virtual uint size_of() const { return sizeof(compUL_rReg_immNode); } |
| 25919 | // Rematerialize compUL_rReg_imm |
| 25920 | static const Pipeline *pipeline_class(); |
| 25921 | virtual const Pipeline *pipeline() const; |
| 25922 | #ifndef PRODUCT |
| 25923 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25924 | virtual const char *Name() const { return "compUL_rReg_imm";} |
| 25925 | #endif |
| 25926 | }; |
| 25927 | |
| 25928 | class compUL_rReg_memNode : public MachNode { |
| 25929 | private: |
| 25930 | MachOper *_opnd_array[3]; |
| 25931 | public: |
| 25932 | MachOper *opnd_array(uint operand_index) const { |
| 25933 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25934 | return _opnd_array[operand_index]; |
| 25935 | } |
| 25936 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25937 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25938 | _opnd_array[operand_index] = operand; |
| 25939 | } |
| 25940 | private: |
| 25941 | virtual const RegMask &out_RegMask() const; |
| 25942 | virtual uint rule() const { return compUL_rReg_mem_rule; } |
| 25943 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25944 | virtual int ideal_Opcode() const { return Op_CmpUL; } |
| 25945 | virtual int reloc() const; |
| 25946 | virtual uint oper_input_base() const { return 2; } |
| 25947 | public: |
| 25948 | compUL_rReg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 25949 | virtual uint size_of() const { return sizeof(compUL_rReg_memNode); } |
| 25950 | // Rematerialize compUL_rReg_mem |
| 25951 | static const Pipeline *pipeline_class(); |
| 25952 | virtual const Pipeline *pipeline() const; |
| 25953 | virtual const MachOper *memory_operand() const; |
| 25954 | #ifndef PRODUCT |
| 25955 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25956 | virtual const char *Name() const { return "compUL_rReg_mem";} |
| 25957 | #endif |
| 25958 | }; |
| 25959 | |
| 25960 | class testUL_regNode : public MachNode { |
| 25961 | private: |
| 25962 | MachOper *_opnd_array[3]; |
| 25963 | public: |
| 25964 | MachOper *opnd_array(uint operand_index) const { |
| 25965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25966 | return _opnd_array[operand_index]; |
| 25967 | } |
| 25968 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25969 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25970 | _opnd_array[operand_index] = operand; |
| 25971 | } |
| 25972 | private: |
| 25973 | virtual const RegMask &out_RegMask() const; |
| 25974 | virtual uint rule() const { return testUL_reg_rule; } |
| 25975 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 25976 | virtual int ideal_Opcode() const { return Op_CmpUL; } |
| 25977 | public: |
| 25978 | testUL_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 25979 | virtual uint size_of() const { return sizeof(testUL_regNode); } |
| 25980 | // Rematerialize testUL_reg |
| 25981 | static const Pipeline *pipeline_class(); |
| 25982 | virtual const Pipeline *pipeline() const; |
| 25983 | #ifndef PRODUCT |
| 25984 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 25985 | virtual const char *Name() const { return "testUL_reg";} |
| 25986 | #endif |
| 25987 | }; |
| 25988 | |
| 25989 | class compB_mem_immNode : public MachNode { |
| 25990 | private: |
| 25991 | MachOper *_opnd_array[3]; |
| 25992 | public: |
| 25993 | MachOper *opnd_array(uint operand_index) const { |
| 25994 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25995 | return _opnd_array[operand_index]; |
| 25996 | } |
| 25997 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 25998 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 25999 | _opnd_array[operand_index] = operand; |
| 26000 | } |
| 26001 | private: |
| 26002 | virtual const RegMask &out_RegMask() const; |
| 26003 | virtual uint rule() const { return compB_mem_imm_rule; } |
| 26004 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26005 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 26006 | virtual int reloc() const; |
| 26007 | virtual uint oper_input_base() const { return 2; } |
| 26008 | public: |
| 26009 | compB_mem_immNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 26010 | virtual uint size_of() const { return sizeof(compB_mem_immNode); } |
| 26011 | // Rematerialize compB_mem_imm |
| 26012 | static const Pipeline *pipeline_class(); |
| 26013 | virtual const Pipeline *pipeline() const; |
| 26014 | virtual const MachOper *memory_operand() const; |
| 26015 | #ifndef PRODUCT |
| 26016 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26017 | virtual const char *Name() const { return "compB_mem_imm";} |
| 26018 | #endif |
| 26019 | }; |
| 26020 | |
| 26021 | class testUB_mem_immNode : public MachNode { |
| 26022 | private: |
| 26023 | MachOper *_opnd_array[4]; |
| 26024 | public: |
| 26025 | MachOper *opnd_array(uint operand_index) const { |
| 26026 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26027 | return _opnd_array[operand_index]; |
| 26028 | } |
| 26029 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26030 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26031 | _opnd_array[operand_index] = operand; |
| 26032 | } |
| 26033 | private: |
| 26034 | virtual const RegMask &out_RegMask() const; |
| 26035 | virtual uint rule() const { return testUB_mem_imm_rule; } |
| 26036 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26037 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 26038 | virtual int reloc() const; |
| 26039 | virtual uint oper_input_base() const { return 2; } |
| 26040 | public: |
| 26041 | testUB_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 26042 | virtual uint size_of() const { return sizeof(testUB_mem_immNode); } |
| 26043 | // Rematerialize testUB_mem_imm |
| 26044 | static const Pipeline *pipeline_class(); |
| 26045 | virtual const Pipeline *pipeline() const; |
| 26046 | virtual const MachOper *memory_operand() const; |
| 26047 | #ifndef PRODUCT |
| 26048 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26049 | virtual const char *Name() const { return "testUB_mem_imm";} |
| 26050 | #endif |
| 26051 | }; |
| 26052 | |
| 26053 | class testB_mem_immNode : public MachNode { |
| 26054 | private: |
| 26055 | MachOper *_opnd_array[4]; |
| 26056 | public: |
| 26057 | MachOper *opnd_array(uint operand_index) const { |
| 26058 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26059 | return _opnd_array[operand_index]; |
| 26060 | } |
| 26061 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26063 | _opnd_array[operand_index] = operand; |
| 26064 | } |
| 26065 | private: |
| 26066 | virtual const RegMask &out_RegMask() const; |
| 26067 | virtual uint rule() const { return testB_mem_imm_rule; } |
| 26068 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26069 | virtual int ideal_Opcode() const { return Op_CmpI; } |
| 26070 | virtual int reloc() const; |
| 26071 | virtual uint oper_input_base() const { return 2; } |
| 26072 | public: |
| 26073 | testB_mem_immNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 26074 | virtual uint size_of() const { return sizeof(testB_mem_immNode); } |
| 26075 | // Rematerialize testB_mem_imm |
| 26076 | static const Pipeline *pipeline_class(); |
| 26077 | virtual const Pipeline *pipeline() const; |
| 26078 | virtual const MachOper *memory_operand() const; |
| 26079 | #ifndef PRODUCT |
| 26080 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26081 | virtual const char *Name() const { return "testB_mem_imm";} |
| 26082 | #endif |
| 26083 | }; |
| 26084 | |
| 26085 | class cmovI_reg_gNode : public MachNode { |
| 26086 | private: |
| 26087 | MachOper *_opnd_array[4]; |
| 26088 | public: |
| 26089 | MachOper *opnd_array(uint operand_index) const { |
| 26090 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26091 | return _opnd_array[operand_index]; |
| 26092 | } |
| 26093 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26094 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26095 | _opnd_array[operand_index] = operand; |
| 26096 | } |
| 26097 | private: |
| 26098 | virtual const RegMask &out_RegMask() const; |
| 26099 | virtual uint rule() const { return cmovI_reg_g_rule; } |
| 26100 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26101 | virtual uint two_adr() const { return oper_input_base(); } |
| 26102 | public: |
| 26103 | cmovI_reg_gNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26104 | virtual uint size_of() const { return sizeof(cmovI_reg_gNode); } |
| 26105 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26106 | static const Pipeline *pipeline_class(); |
| 26107 | virtual const Pipeline *pipeline() const; |
| 26108 | #ifndef PRODUCT |
| 26109 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26110 | virtual const char *Name() const { return "cmovI_reg_g";} |
| 26111 | #endif |
| 26112 | }; |
| 26113 | |
| 26114 | class minI_rRegNode : public MachNode { |
| 26115 | private: |
| 26116 | MachOper *_opnd_array[3]; |
| 26117 | public: |
| 26118 | MachOper *opnd_array(uint operand_index) const { |
| 26119 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26120 | return _opnd_array[operand_index]; |
| 26121 | } |
| 26122 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26123 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26124 | _opnd_array[operand_index] = operand; |
| 26125 | } |
| 26126 | private: |
| 26127 | virtual const RegMask &out_RegMask() const; |
| 26128 | virtual uint rule() const { return minI_rReg_rule; } |
| 26129 | virtual int ideal_Opcode() const { return Op_MinI; } |
| 26130 | virtual uint two_adr() const { return oper_input_base(); } |
| 26131 | public: |
| 26132 | minI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 26133 | virtual uint size_of() const { return sizeof(minI_rRegNode); } |
| 26134 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 26135 | #ifndef PRODUCT |
| 26136 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26137 | virtual const char *Name() const { return "minI_rReg";} |
| 26138 | #endif |
| 26139 | }; |
| 26140 | |
| 26141 | class cmovI_reg_lNode : public MachNode { |
| 26142 | private: |
| 26143 | MachOper *_opnd_array[4]; |
| 26144 | public: |
| 26145 | MachOper *opnd_array(uint operand_index) const { |
| 26146 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26147 | return _opnd_array[operand_index]; |
| 26148 | } |
| 26149 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26150 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26151 | _opnd_array[operand_index] = operand; |
| 26152 | } |
| 26153 | private: |
| 26154 | virtual const RegMask &out_RegMask() const; |
| 26155 | virtual uint rule() const { return cmovI_reg_l_rule; } |
| 26156 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26157 | virtual uint two_adr() const { return oper_input_base(); } |
| 26158 | public: |
| 26159 | cmovI_reg_lNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26160 | virtual uint size_of() const { return sizeof(cmovI_reg_lNode); } |
| 26161 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26162 | static const Pipeline *pipeline_class(); |
| 26163 | virtual const Pipeline *pipeline() const; |
| 26164 | #ifndef PRODUCT |
| 26165 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26166 | virtual const char *Name() const { return "cmovI_reg_l";} |
| 26167 | #endif |
| 26168 | }; |
| 26169 | |
| 26170 | class maxI_rRegNode : public MachNode { |
| 26171 | private: |
| 26172 | MachOper *_opnd_array[3]; |
| 26173 | public: |
| 26174 | MachOper *opnd_array(uint operand_index) const { |
| 26175 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26176 | return _opnd_array[operand_index]; |
| 26177 | } |
| 26178 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26179 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26180 | _opnd_array[operand_index] = operand; |
| 26181 | } |
| 26182 | private: |
| 26183 | virtual const RegMask &out_RegMask() const; |
| 26184 | virtual uint rule() const { return maxI_rReg_rule; } |
| 26185 | virtual int ideal_Opcode() const { return Op_MaxI; } |
| 26186 | virtual uint two_adr() const { return oper_input_base(); } |
| 26187 | public: |
| 26188 | maxI_rRegNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 26189 | virtual uint size_of() const { return sizeof(maxI_rRegNode); } |
| 26190 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 26191 | #ifndef PRODUCT |
| 26192 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26193 | virtual const char *Name() const { return "maxI_rReg";} |
| 26194 | #endif |
| 26195 | }; |
| 26196 | |
| 26197 | class jmpDirNode : public MachGotoNode { |
| 26198 | private: |
| 26199 | MachOper *_opnd_array[2]; |
| 26200 | public: |
| 26201 | MachOper *opnd_array(uint operand_index) const { |
| 26202 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26203 | return _opnd_array[operand_index]; |
| 26204 | } |
| 26205 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26206 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26207 | _opnd_array[operand_index] = operand; |
| 26208 | } |
| 26209 | private: |
| 26210 | virtual const RegMask &out_RegMask() const; |
| 26211 | virtual uint rule() const { return jmpDir_rule; } |
| 26212 | virtual void label_set( Label* label, uint block_num ); |
| 26213 | virtual void save_label( Label** label, uint* block_num ); |
| 26214 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26215 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26216 | virtual int ideal_Opcode() const { return Op_Goto; } |
| 26217 | virtual uint oper_input_base() const { return 1; } |
| 26218 | public: |
| 26219 | jmpDirNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26220 | virtual uint size_of() const { return sizeof(jmpDirNode); } |
| 26221 | virtual bool pinned() const { return true; } |
| 26222 | virtual const Node *is_block_proj() const { return this; } |
| 26223 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26224 | virtual MachNode *short_branch_version(); |
| 26225 | static const Pipeline *pipeline_class(); |
| 26226 | virtual const Pipeline *pipeline() const; |
| 26227 | #ifndef PRODUCT |
| 26228 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26229 | virtual const char *Name() const { return "jmpDir";} |
| 26230 | #endif |
| 26231 | }; |
| 26232 | |
| 26233 | class jmpConNode : public MachIfNode { |
| 26234 | private: |
| 26235 | MachOper *_opnd_array[4]; |
| 26236 | public: |
| 26237 | MachOper *opnd_array(uint operand_index) const { |
| 26238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26239 | return _opnd_array[operand_index]; |
| 26240 | } |
| 26241 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26242 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26243 | _opnd_array[operand_index] = operand; |
| 26244 | } |
| 26245 | private: |
| 26246 | virtual const RegMask &out_RegMask() const; |
| 26247 | virtual uint rule() const { return jmpCon_rule; } |
| 26248 | virtual void label_set( Label* label, uint block_num ); |
| 26249 | virtual void save_label( Label** label, uint* block_num ); |
| 26250 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26251 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26252 | virtual int ideal_Opcode() const { return Op_If; } |
| 26253 | virtual void negate() { |
| 26254 | opnd_array(1)->negate(); |
| 26255 | _prob = 1.0f - _prob; |
| 26256 | }; |
| 26257 | virtual uint oper_input_base() const { return 1; } |
| 26258 | public: |
| 26259 | jmpConNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26260 | virtual uint size_of() const { return sizeof(jmpConNode); } |
| 26261 | virtual bool pinned() const { return true; } |
| 26262 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26263 | virtual MachNode *short_branch_version(); |
| 26264 | static const Pipeline *pipeline_class(); |
| 26265 | virtual const Pipeline *pipeline() const; |
| 26266 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26267 | #ifndef PRODUCT |
| 26268 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26269 | virtual const char *Name() const { return "jmpCon";} |
| 26270 | #endif |
| 26271 | }; |
| 26272 | |
| 26273 | class jmpLoopEndNode : public MachIfNode { |
| 26274 | private: |
| 26275 | MachOper *_opnd_array[4]; |
| 26276 | public: |
| 26277 | MachOper *opnd_array(uint operand_index) const { |
| 26278 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26279 | return _opnd_array[operand_index]; |
| 26280 | } |
| 26281 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26282 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26283 | _opnd_array[operand_index] = operand; |
| 26284 | } |
| 26285 | private: |
| 26286 | virtual const RegMask &out_RegMask() const; |
| 26287 | virtual uint rule() const { return jmpLoopEnd_rule; } |
| 26288 | virtual void label_set( Label* label, uint block_num ); |
| 26289 | virtual void save_label( Label** label, uint* block_num ); |
| 26290 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26291 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26292 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26293 | virtual void negate() { |
| 26294 | opnd_array(1)->negate(); |
| 26295 | _prob = 1.0f - _prob; |
| 26296 | }; |
| 26297 | virtual uint oper_input_base() const { return 1; } |
| 26298 | public: |
| 26299 | jmpLoopEndNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26300 | virtual uint size_of() const { return sizeof(jmpLoopEndNode); } |
| 26301 | virtual bool pinned() const { return true; } |
| 26302 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26303 | virtual MachNode *short_branch_version(); |
| 26304 | static const Pipeline *pipeline_class(); |
| 26305 | virtual const Pipeline *pipeline() const; |
| 26306 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26307 | #ifndef PRODUCT |
| 26308 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26309 | virtual const char *Name() const { return "jmpLoopEnd";} |
| 26310 | #endif |
| 26311 | }; |
| 26312 | |
| 26313 | class jmpLoopEndUNode : public MachIfNode { |
| 26314 | private: |
| 26315 | MachOper *_opnd_array[4]; |
| 26316 | public: |
| 26317 | MachOper *opnd_array(uint operand_index) const { |
| 26318 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26319 | return _opnd_array[operand_index]; |
| 26320 | } |
| 26321 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26322 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26323 | _opnd_array[operand_index] = operand; |
| 26324 | } |
| 26325 | private: |
| 26326 | virtual const RegMask &out_RegMask() const; |
| 26327 | virtual uint rule() const { return jmpLoopEndU_rule; } |
| 26328 | virtual void label_set( Label* label, uint block_num ); |
| 26329 | virtual void save_label( Label** label, uint* block_num ); |
| 26330 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26331 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26332 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26333 | virtual void negate() { |
| 26334 | opnd_array(1)->negate(); |
| 26335 | _prob = 1.0f - _prob; |
| 26336 | }; |
| 26337 | virtual uint oper_input_base() const { return 1; } |
| 26338 | public: |
| 26339 | jmpLoopEndUNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26340 | virtual uint size_of() const { return sizeof(jmpLoopEndUNode); } |
| 26341 | virtual bool pinned() const { return true; } |
| 26342 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26343 | virtual MachNode *short_branch_version(); |
| 26344 | static const Pipeline *pipeline_class(); |
| 26345 | virtual const Pipeline *pipeline() const; |
| 26346 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26347 | #ifndef PRODUCT |
| 26348 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26349 | virtual const char *Name() const { return "jmpLoopEndU";} |
| 26350 | #endif |
| 26351 | }; |
| 26352 | |
| 26353 | class jmpLoopEndUCFNode : public MachIfNode { |
| 26354 | private: |
| 26355 | MachOper *_opnd_array[4]; |
| 26356 | public: |
| 26357 | MachOper *opnd_array(uint operand_index) const { |
| 26358 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26359 | return _opnd_array[operand_index]; |
| 26360 | } |
| 26361 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26362 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26363 | _opnd_array[operand_index] = operand; |
| 26364 | } |
| 26365 | private: |
| 26366 | virtual const RegMask &out_RegMask() const; |
| 26367 | virtual uint rule() const { return jmpLoopEndUCF_rule; } |
| 26368 | virtual void label_set( Label* label, uint block_num ); |
| 26369 | virtual void save_label( Label** label, uint* block_num ); |
| 26370 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26371 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26372 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26373 | virtual void negate() { |
| 26374 | opnd_array(1)->negate(); |
| 26375 | _prob = 1.0f - _prob; |
| 26376 | }; |
| 26377 | virtual uint oper_input_base() const { return 1; } |
| 26378 | public: |
| 26379 | jmpLoopEndUCFNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26380 | virtual uint size_of() const { return sizeof(jmpLoopEndUCFNode); } |
| 26381 | virtual bool pinned() const { return true; } |
| 26382 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26383 | virtual MachNode *short_branch_version(); |
| 26384 | static const Pipeline *pipeline_class(); |
| 26385 | virtual const Pipeline *pipeline() const; |
| 26386 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26387 | #ifndef PRODUCT |
| 26388 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26389 | virtual const char *Name() const { return "jmpLoopEndUCF";} |
| 26390 | #endif |
| 26391 | }; |
| 26392 | |
| 26393 | class jmpLoopEnd_and_restoreMaskNode : public MachIfNode { |
| 26394 | private: |
| 26395 | MachOper *_opnd_array[4]; |
| 26396 | public: |
| 26397 | MachOper *opnd_array(uint operand_index) const { |
| 26398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26399 | return _opnd_array[operand_index]; |
| 26400 | } |
| 26401 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26402 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26403 | _opnd_array[operand_index] = operand; |
| 26404 | } |
| 26405 | private: |
| 26406 | virtual const RegMask &out_RegMask() const; |
| 26407 | virtual uint rule() const { return jmpLoopEnd_and_restoreMask_rule; } |
| 26408 | virtual void label_set( Label* label, uint block_num ); |
| 26409 | virtual void save_label( Label** label, uint* block_num ); |
| 26410 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26411 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26412 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26413 | virtual void negate() { |
| 26414 | opnd_array(1)->negate(); |
| 26415 | _prob = 1.0f - _prob; |
| 26416 | }; |
| 26417 | virtual uint oper_input_base() const { return 1; } |
| 26418 | public: |
| 26419 | jmpLoopEnd_and_restoreMaskNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26420 | virtual uint size_of() const { return sizeof(jmpLoopEnd_and_restoreMaskNode); } |
| 26421 | virtual bool pinned() const { return true; } |
| 26422 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26423 | static const Pipeline *pipeline_class(); |
| 26424 | virtual const Pipeline *pipeline() const; |
| 26425 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26426 | #ifndef PRODUCT |
| 26427 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26428 | virtual const char *Name() const { return "jmpLoopEnd_and_restoreMask";} |
| 26429 | #endif |
| 26430 | }; |
| 26431 | |
| 26432 | class jmpLoopEndU_and_restoreMaskNode : public MachIfNode { |
| 26433 | private: |
| 26434 | MachOper *_opnd_array[4]; |
| 26435 | public: |
| 26436 | MachOper *opnd_array(uint operand_index) const { |
| 26437 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26438 | return _opnd_array[operand_index]; |
| 26439 | } |
| 26440 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26441 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26442 | _opnd_array[operand_index] = operand; |
| 26443 | } |
| 26444 | private: |
| 26445 | virtual const RegMask &out_RegMask() const; |
| 26446 | virtual uint rule() const { return jmpLoopEndU_and_restoreMask_rule; } |
| 26447 | virtual void label_set( Label* label, uint block_num ); |
| 26448 | virtual void save_label( Label** label, uint* block_num ); |
| 26449 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26450 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26451 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26452 | virtual void negate() { |
| 26453 | opnd_array(1)->negate(); |
| 26454 | _prob = 1.0f - _prob; |
| 26455 | }; |
| 26456 | virtual uint oper_input_base() const { return 1; } |
| 26457 | public: |
| 26458 | jmpLoopEndU_and_restoreMaskNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26459 | virtual uint size_of() const { return sizeof(jmpLoopEndU_and_restoreMaskNode); } |
| 26460 | virtual bool pinned() const { return true; } |
| 26461 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26462 | static const Pipeline *pipeline_class(); |
| 26463 | virtual const Pipeline *pipeline() const; |
| 26464 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26465 | #ifndef PRODUCT |
| 26466 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26467 | virtual const char *Name() const { return "jmpLoopEndU_and_restoreMask";} |
| 26468 | #endif |
| 26469 | }; |
| 26470 | |
| 26471 | class jmpLoopEndUCF_and_restoreMaskNode : public MachIfNode { |
| 26472 | private: |
| 26473 | MachOper *_opnd_array[4]; |
| 26474 | public: |
| 26475 | MachOper *opnd_array(uint operand_index) const { |
| 26476 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26477 | return _opnd_array[operand_index]; |
| 26478 | } |
| 26479 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26481 | _opnd_array[operand_index] = operand; |
| 26482 | } |
| 26483 | private: |
| 26484 | virtual const RegMask &out_RegMask() const; |
| 26485 | virtual uint rule() const { return jmpLoopEndUCF_and_restoreMask_rule; } |
| 26486 | virtual void label_set( Label* label, uint block_num ); |
| 26487 | virtual void save_label( Label** label, uint* block_num ); |
| 26488 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26489 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26490 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26491 | virtual void negate() { |
| 26492 | opnd_array(1)->negate(); |
| 26493 | _prob = 1.0f - _prob; |
| 26494 | }; |
| 26495 | virtual uint oper_input_base() const { return 1; } |
| 26496 | public: |
| 26497 | jmpLoopEndUCF_and_restoreMaskNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26498 | virtual uint size_of() const { return sizeof(jmpLoopEndUCF_and_restoreMaskNode); } |
| 26499 | virtual bool pinned() const { return true; } |
| 26500 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26501 | static const Pipeline *pipeline_class(); |
| 26502 | virtual const Pipeline *pipeline() const; |
| 26503 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26504 | #ifndef PRODUCT |
| 26505 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26506 | virtual const char *Name() const { return "jmpLoopEndUCF_and_restoreMask";} |
| 26507 | #endif |
| 26508 | }; |
| 26509 | |
| 26510 | class jmpConUNode : public MachIfNode { |
| 26511 | private: |
| 26512 | MachOper *_opnd_array[4]; |
| 26513 | public: |
| 26514 | MachOper *opnd_array(uint operand_index) const { |
| 26515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26516 | return _opnd_array[operand_index]; |
| 26517 | } |
| 26518 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26519 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26520 | _opnd_array[operand_index] = operand; |
| 26521 | } |
| 26522 | private: |
| 26523 | virtual const RegMask &out_RegMask() const; |
| 26524 | virtual uint rule() const { return jmpConU_rule; } |
| 26525 | virtual void label_set( Label* label, uint block_num ); |
| 26526 | virtual void save_label( Label** label, uint* block_num ); |
| 26527 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26528 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26529 | virtual int ideal_Opcode() const { return Op_If; } |
| 26530 | virtual void negate() { |
| 26531 | opnd_array(1)->negate(); |
| 26532 | _prob = 1.0f - _prob; |
| 26533 | }; |
| 26534 | virtual uint oper_input_base() const { return 1; } |
| 26535 | public: |
| 26536 | jmpConUNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26537 | virtual uint size_of() const { return sizeof(jmpConUNode); } |
| 26538 | virtual bool pinned() const { return true; } |
| 26539 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26540 | virtual MachNode *short_branch_version(); |
| 26541 | static const Pipeline *pipeline_class(); |
| 26542 | virtual const Pipeline *pipeline() const; |
| 26543 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26544 | #ifndef PRODUCT |
| 26545 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26546 | virtual const char *Name() const { return "jmpConU";} |
| 26547 | #endif |
| 26548 | }; |
| 26549 | |
| 26550 | class jmpConUCFNode : public MachIfNode { |
| 26551 | private: |
| 26552 | MachOper *_opnd_array[4]; |
| 26553 | public: |
| 26554 | MachOper *opnd_array(uint operand_index) const { |
| 26555 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26556 | return _opnd_array[operand_index]; |
| 26557 | } |
| 26558 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26559 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26560 | _opnd_array[operand_index] = operand; |
| 26561 | } |
| 26562 | private: |
| 26563 | virtual const RegMask &out_RegMask() const; |
| 26564 | virtual uint rule() const { return jmpConUCF_rule; } |
| 26565 | virtual void label_set( Label* label, uint block_num ); |
| 26566 | virtual void save_label( Label** label, uint* block_num ); |
| 26567 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26568 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26569 | virtual int ideal_Opcode() const { return Op_If; } |
| 26570 | virtual void negate() { |
| 26571 | opnd_array(1)->negate(); |
| 26572 | _prob = 1.0f - _prob; |
| 26573 | }; |
| 26574 | virtual uint oper_input_base() const { return 1; } |
| 26575 | public: |
| 26576 | jmpConUCFNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26577 | virtual uint size_of() const { return sizeof(jmpConUCFNode); } |
| 26578 | virtual bool pinned() const { return true; } |
| 26579 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26580 | virtual MachNode *short_branch_version(); |
| 26581 | static const Pipeline *pipeline_class(); |
| 26582 | virtual const Pipeline *pipeline() const; |
| 26583 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26584 | #ifndef PRODUCT |
| 26585 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26586 | virtual const char *Name() const { return "jmpConUCF";} |
| 26587 | #endif |
| 26588 | }; |
| 26589 | |
| 26590 | class jmpConUCF2Node : public MachIfNode { |
| 26591 | private: |
| 26592 | MachOper *_opnd_array[4]; |
| 26593 | public: |
| 26594 | MachOper *opnd_array(uint operand_index) const { |
| 26595 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26596 | return _opnd_array[operand_index]; |
| 26597 | } |
| 26598 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26599 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26600 | _opnd_array[operand_index] = operand; |
| 26601 | } |
| 26602 | private: |
| 26603 | virtual const RegMask &out_RegMask() const; |
| 26604 | virtual uint rule() const { return jmpConUCF2_rule; } |
| 26605 | virtual void label_set( Label* label, uint block_num ); |
| 26606 | virtual void save_label( Label** label, uint* block_num ); |
| 26607 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26608 | virtual int ideal_Opcode() const { return Op_If; } |
| 26609 | virtual void negate() { |
| 26610 | opnd_array(1)->negate(); |
| 26611 | _prob = 1.0f - _prob; |
| 26612 | }; |
| 26613 | virtual uint oper_input_base() const { return 1; } |
| 26614 | public: |
| 26615 | jmpConUCF2Node() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_may_be_short_branch); } |
| 26616 | virtual uint size_of() const { return sizeof(jmpConUCF2Node); } |
| 26617 | virtual bool pinned() const { return true; } |
| 26618 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26619 | virtual MachNode *short_branch_version(); |
| 26620 | static const Pipeline *pipeline_class(); |
| 26621 | virtual const Pipeline *pipeline() const; |
| 26622 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26623 | #ifndef PRODUCT |
| 26624 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26625 | virtual const char *Name() const { return "jmpConUCF2";} |
| 26626 | #endif |
| 26627 | }; |
| 26628 | |
| 26629 | class partialSubtypeCheckNode : public MachNode { |
| 26630 | private: |
| 26631 | MachOper *_opnd_array[3]; |
| 26632 | public: |
| 26633 | MachOper *opnd_array(uint operand_index) const { |
| 26634 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26635 | return _opnd_array[operand_index]; |
| 26636 | } |
| 26637 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26638 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26639 | _opnd_array[operand_index] = operand; |
| 26640 | } |
| 26641 | private: |
| 26642 | virtual const RegMask &out_RegMask() const; |
| 26643 | virtual uint rule() const { return partialSubtypeCheck_rule; } |
| 26644 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26645 | virtual int ideal_Opcode() const { return Op_PartialSubtypeCheck; } |
| 26646 | public: |
| 26647 | partialSubtypeCheckNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 26648 | virtual uint size_of() const { return sizeof(partialSubtypeCheckNode); } |
| 26649 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 26650 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26651 | static const Pipeline *pipeline_class(); |
| 26652 | virtual const Pipeline *pipeline() const; |
| 26653 | #ifndef PRODUCT |
| 26654 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26655 | virtual const char *Name() const { return "partialSubtypeCheck";} |
| 26656 | #endif |
| 26657 | }; |
| 26658 | |
| 26659 | class partialSubtypeCheck_vs_ZeroNode : public MachNode { |
| 26660 | private: |
| 26661 | MachOper *_opnd_array[4]; |
| 26662 | public: |
| 26663 | MachOper *opnd_array(uint operand_index) const { |
| 26664 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26665 | return _opnd_array[operand_index]; |
| 26666 | } |
| 26667 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26668 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26669 | _opnd_array[operand_index] = operand; |
| 26670 | } |
| 26671 | private: |
| 26672 | virtual const RegMask &out_RegMask() const; |
| 26673 | virtual uint rule() const { return partialSubtypeCheck_vs_Zero_rule; } |
| 26674 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26675 | virtual int ideal_Opcode() const { return Op_CmpP; } |
| 26676 | virtual int reloc() const; |
| 26677 | public: |
| 26678 | partialSubtypeCheck_vs_ZeroNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26679 | virtual uint size_of() const { return sizeof(partialSubtypeCheck_vs_ZeroNode); } |
| 26680 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 26681 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26682 | // Rematerialize partialSubtypeCheck_vs_Zero |
| 26683 | static const Pipeline *pipeline_class(); |
| 26684 | virtual const Pipeline *pipeline() const; |
| 26685 | #ifndef PRODUCT |
| 26686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26687 | virtual const char *Name() const { return "partialSubtypeCheck_vs_Zero";} |
| 26688 | #endif |
| 26689 | }; |
| 26690 | |
| 26691 | class jmpDir_shortNode : public MachGotoNode { |
| 26692 | private: |
| 26693 | MachOper *_opnd_array[2]; |
| 26694 | public: |
| 26695 | MachOper *opnd_array(uint operand_index) const { |
| 26696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26697 | return _opnd_array[operand_index]; |
| 26698 | } |
| 26699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26701 | _opnd_array[operand_index] = operand; |
| 26702 | } |
| 26703 | private: |
| 26704 | virtual const RegMask &out_RegMask() const; |
| 26705 | virtual uint rule() const { return jmpDir_short_rule; } |
| 26706 | virtual void label_set( Label* label, uint block_num ); |
| 26707 | virtual void save_label( Label** label, uint* block_num ); |
| 26708 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26709 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26710 | virtual int ideal_Opcode() const { return Op_Goto; } |
| 26711 | virtual uint oper_input_base() const { return 1; } |
| 26712 | public: |
| 26713 | jmpDir_shortNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 26714 | virtual uint size_of() const { return sizeof(jmpDir_shortNode); } |
| 26715 | virtual bool pinned() const { return true; } |
| 26716 | virtual const Node *is_block_proj() const { return this; } |
| 26717 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26718 | static const Pipeline *pipeline_class(); |
| 26719 | virtual const Pipeline *pipeline() const; |
| 26720 | #ifndef PRODUCT |
| 26721 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26722 | virtual const char *Name() const { return "jmpDir_short";} |
| 26723 | #endif |
| 26724 | }; |
| 26725 | |
| 26726 | class jmpCon_shortNode : public MachIfNode { |
| 26727 | private: |
| 26728 | MachOper *_opnd_array[4]; |
| 26729 | public: |
| 26730 | MachOper *opnd_array(uint operand_index) const { |
| 26731 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26732 | return _opnd_array[operand_index]; |
| 26733 | } |
| 26734 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26735 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26736 | _opnd_array[operand_index] = operand; |
| 26737 | } |
| 26738 | private: |
| 26739 | virtual const RegMask &out_RegMask() const; |
| 26740 | virtual uint rule() const { return jmpCon_short_rule; } |
| 26741 | virtual void label_set( Label* label, uint block_num ); |
| 26742 | virtual void save_label( Label** label, uint* block_num ); |
| 26743 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26744 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26745 | virtual int ideal_Opcode() const { return Op_If; } |
| 26746 | virtual void negate() { |
| 26747 | opnd_array(1)->negate(); |
| 26748 | _prob = 1.0f - _prob; |
| 26749 | }; |
| 26750 | virtual uint oper_input_base() const { return 1; } |
| 26751 | public: |
| 26752 | jmpCon_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26753 | virtual uint size_of() const { return sizeof(jmpCon_shortNode); } |
| 26754 | virtual bool pinned() const { return true; } |
| 26755 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26756 | static const Pipeline *pipeline_class(); |
| 26757 | virtual const Pipeline *pipeline() const; |
| 26758 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26759 | #ifndef PRODUCT |
| 26760 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26761 | virtual const char *Name() const { return "jmpCon_short";} |
| 26762 | #endif |
| 26763 | }; |
| 26764 | |
| 26765 | class jmpLoopEnd_shortNode : public MachIfNode { |
| 26766 | private: |
| 26767 | MachOper *_opnd_array[4]; |
| 26768 | public: |
| 26769 | MachOper *opnd_array(uint operand_index) const { |
| 26770 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26771 | return _opnd_array[operand_index]; |
| 26772 | } |
| 26773 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26774 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26775 | _opnd_array[operand_index] = operand; |
| 26776 | } |
| 26777 | private: |
| 26778 | virtual const RegMask &out_RegMask() const; |
| 26779 | virtual uint rule() const { return jmpLoopEnd_short_rule; } |
| 26780 | virtual void label_set( Label* label, uint block_num ); |
| 26781 | virtual void save_label( Label** label, uint* block_num ); |
| 26782 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26783 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26784 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26785 | virtual void negate() { |
| 26786 | opnd_array(1)->negate(); |
| 26787 | _prob = 1.0f - _prob; |
| 26788 | }; |
| 26789 | virtual uint oper_input_base() const { return 1; } |
| 26790 | public: |
| 26791 | jmpLoopEnd_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26792 | virtual uint size_of() const { return sizeof(jmpLoopEnd_shortNode); } |
| 26793 | virtual bool pinned() const { return true; } |
| 26794 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26795 | static const Pipeline *pipeline_class(); |
| 26796 | virtual const Pipeline *pipeline() const; |
| 26797 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26798 | #ifndef PRODUCT |
| 26799 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26800 | virtual const char *Name() const { return "jmpLoopEnd_short";} |
| 26801 | #endif |
| 26802 | }; |
| 26803 | |
| 26804 | class jmpLoopEndU_shortNode : public MachIfNode { |
| 26805 | private: |
| 26806 | MachOper *_opnd_array[4]; |
| 26807 | public: |
| 26808 | MachOper *opnd_array(uint operand_index) const { |
| 26809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26810 | return _opnd_array[operand_index]; |
| 26811 | } |
| 26812 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26813 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26814 | _opnd_array[operand_index] = operand; |
| 26815 | } |
| 26816 | private: |
| 26817 | virtual const RegMask &out_RegMask() const; |
| 26818 | virtual uint rule() const { return jmpLoopEndU_short_rule; } |
| 26819 | virtual void label_set( Label* label, uint block_num ); |
| 26820 | virtual void save_label( Label** label, uint* block_num ); |
| 26821 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26822 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26823 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26824 | virtual void negate() { |
| 26825 | opnd_array(1)->negate(); |
| 26826 | _prob = 1.0f - _prob; |
| 26827 | }; |
| 26828 | virtual uint oper_input_base() const { return 1; } |
| 26829 | public: |
| 26830 | jmpLoopEndU_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26831 | virtual uint size_of() const { return sizeof(jmpLoopEndU_shortNode); } |
| 26832 | virtual bool pinned() const { return true; } |
| 26833 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26834 | static const Pipeline *pipeline_class(); |
| 26835 | virtual const Pipeline *pipeline() const; |
| 26836 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26837 | #ifndef PRODUCT |
| 26838 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26839 | virtual const char *Name() const { return "jmpLoopEndU_short";} |
| 26840 | #endif |
| 26841 | }; |
| 26842 | |
| 26843 | class jmpLoopEndUCF_shortNode : public MachIfNode { |
| 26844 | private: |
| 26845 | MachOper *_opnd_array[4]; |
| 26846 | public: |
| 26847 | MachOper *opnd_array(uint operand_index) const { |
| 26848 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26849 | return _opnd_array[operand_index]; |
| 26850 | } |
| 26851 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26852 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26853 | _opnd_array[operand_index] = operand; |
| 26854 | } |
| 26855 | private: |
| 26856 | virtual const RegMask &out_RegMask() const; |
| 26857 | virtual uint rule() const { return jmpLoopEndUCF_short_rule; } |
| 26858 | virtual void label_set( Label* label, uint block_num ); |
| 26859 | virtual void save_label( Label** label, uint* block_num ); |
| 26860 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26861 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26862 | virtual int ideal_Opcode() const { return Op_CountedLoopEnd; } |
| 26863 | virtual void negate() { |
| 26864 | opnd_array(1)->negate(); |
| 26865 | _prob = 1.0f - _prob; |
| 26866 | }; |
| 26867 | virtual uint oper_input_base() const { return 1; } |
| 26868 | public: |
| 26869 | jmpLoopEndUCF_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26870 | virtual uint size_of() const { return sizeof(jmpLoopEndUCF_shortNode); } |
| 26871 | virtual bool pinned() const { return true; } |
| 26872 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26873 | static const Pipeline *pipeline_class(); |
| 26874 | virtual const Pipeline *pipeline() const; |
| 26875 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26876 | #ifndef PRODUCT |
| 26877 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26878 | virtual const char *Name() const { return "jmpLoopEndUCF_short";} |
| 26879 | #endif |
| 26880 | }; |
| 26881 | |
| 26882 | class jmpConU_shortNode : public MachIfNode { |
| 26883 | private: |
| 26884 | MachOper *_opnd_array[4]; |
| 26885 | public: |
| 26886 | MachOper *opnd_array(uint operand_index) const { |
| 26887 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26888 | return _opnd_array[operand_index]; |
| 26889 | } |
| 26890 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26891 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26892 | _opnd_array[operand_index] = operand; |
| 26893 | } |
| 26894 | private: |
| 26895 | virtual const RegMask &out_RegMask() const; |
| 26896 | virtual uint rule() const { return jmpConU_short_rule; } |
| 26897 | virtual void label_set( Label* label, uint block_num ); |
| 26898 | virtual void save_label( Label** label, uint* block_num ); |
| 26899 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26900 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26901 | virtual int ideal_Opcode() const { return Op_If; } |
| 26902 | virtual void negate() { |
| 26903 | opnd_array(1)->negate(); |
| 26904 | _prob = 1.0f - _prob; |
| 26905 | }; |
| 26906 | virtual uint oper_input_base() const { return 1; } |
| 26907 | public: |
| 26908 | jmpConU_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26909 | virtual uint size_of() const { return sizeof(jmpConU_shortNode); } |
| 26910 | virtual bool pinned() const { return true; } |
| 26911 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26912 | static const Pipeline *pipeline_class(); |
| 26913 | virtual const Pipeline *pipeline() const; |
| 26914 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26915 | #ifndef PRODUCT |
| 26916 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26917 | virtual const char *Name() const { return "jmpConU_short";} |
| 26918 | #endif |
| 26919 | }; |
| 26920 | |
| 26921 | class jmpConUCF_shortNode : public MachIfNode { |
| 26922 | private: |
| 26923 | MachOper *_opnd_array[4]; |
| 26924 | public: |
| 26925 | MachOper *opnd_array(uint operand_index) const { |
| 26926 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26927 | return _opnd_array[operand_index]; |
| 26928 | } |
| 26929 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26930 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26931 | _opnd_array[operand_index] = operand; |
| 26932 | } |
| 26933 | private: |
| 26934 | virtual const RegMask &out_RegMask() const; |
| 26935 | virtual uint rule() const { return jmpConUCF_short_rule; } |
| 26936 | virtual void label_set( Label* label, uint block_num ); |
| 26937 | virtual void save_label( Label** label, uint* block_num ); |
| 26938 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26939 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26940 | virtual int ideal_Opcode() const { return Op_If; } |
| 26941 | virtual void negate() { |
| 26942 | opnd_array(1)->negate(); |
| 26943 | _prob = 1.0f - _prob; |
| 26944 | }; |
| 26945 | virtual uint oper_input_base() const { return 1; } |
| 26946 | public: |
| 26947 | jmpConUCF_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26948 | virtual uint size_of() const { return sizeof(jmpConUCF_shortNode); } |
| 26949 | virtual bool pinned() const { return true; } |
| 26950 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26951 | static const Pipeline *pipeline_class(); |
| 26952 | virtual const Pipeline *pipeline() const; |
| 26953 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26954 | #ifndef PRODUCT |
| 26955 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26956 | virtual const char *Name() const { return "jmpConUCF_short";} |
| 26957 | #endif |
| 26958 | }; |
| 26959 | |
| 26960 | class jmpConUCF2_shortNode : public MachIfNode { |
| 26961 | private: |
| 26962 | MachOper *_opnd_array[4]; |
| 26963 | public: |
| 26964 | MachOper *opnd_array(uint operand_index) const { |
| 26965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26966 | return _opnd_array[operand_index]; |
| 26967 | } |
| 26968 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 26969 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 26970 | _opnd_array[operand_index] = operand; |
| 26971 | } |
| 26972 | private: |
| 26973 | virtual const RegMask &out_RegMask() const; |
| 26974 | virtual uint rule() const { return jmpConUCF2_short_rule; } |
| 26975 | virtual void label_set( Label* label, uint block_num ); |
| 26976 | virtual void save_label( Label** label, uint* block_num ); |
| 26977 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 26978 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 26979 | virtual int ideal_Opcode() const { return Op_If; } |
| 26980 | virtual void negate() { |
| 26981 | opnd_array(1)->negate(); |
| 26982 | _prob = 1.0f - _prob; |
| 26983 | }; |
| 26984 | virtual uint oper_input_base() const { return 1; } |
| 26985 | public: |
| 26986 | jmpConUCF2_shortNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 26987 | virtual uint size_of() const { return sizeof(jmpConUCF2_shortNode); } |
| 26988 | virtual bool pinned() const { return true; } |
| 26989 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 26990 | static const Pipeline *pipeline_class(); |
| 26991 | virtual const Pipeline *pipeline() const; |
| 26992 | const Type *bottom_type() const { return TypeTuple::IFBOTH; } // matched IfNode |
| 26993 | #ifndef PRODUCT |
| 26994 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 26995 | virtual const char *Name() const { return "jmpConUCF2_short";} |
| 26996 | #endif |
| 26997 | }; |
| 26998 | |
| 26999 | class cmpFastLockRTMNode : public MachFastLockNode { |
| 27000 | private: |
| 27001 | MachOper *_opnd_array[7]; |
| 27002 | public: |
| 27003 | MachOper *opnd_array(uint operand_index) const { |
| 27004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27005 | return _opnd_array[operand_index]; |
| 27006 | } |
| 27007 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27008 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27009 | _opnd_array[operand_index] = operand; |
| 27010 | } |
| 27011 | private: |
| 27012 | virtual const RegMask &out_RegMask() const; |
| 27013 | virtual uint rule() const { return cmpFastLockRTM_rule; } |
| 27014 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27015 | virtual int ideal_Opcode() const { return Op_FastLock; } |
| 27016 | virtual uint oper_input_base() const { return 1; } |
| 27017 | public: |
| 27018 | cmpFastLockRTMNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 27019 | virtual uint size_of() const { return sizeof(cmpFastLockRTMNode); } |
| 27020 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27021 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27022 | // Rematerialize cmpFastLockRTM |
| 27023 | static const Pipeline *pipeline_class(); |
| 27024 | virtual const Pipeline *pipeline() const; |
| 27025 | #ifndef PRODUCT |
| 27026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27027 | virtual const char *Name() const { return "cmpFastLockRTM";} |
| 27028 | #endif |
| 27029 | }; |
| 27030 | |
| 27031 | class cmpFastLockNode : public MachFastLockNode { |
| 27032 | private: |
| 27033 | MachOper *_opnd_array[5]; |
| 27034 | public: |
| 27035 | MachOper *opnd_array(uint operand_index) const { |
| 27036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27037 | return _opnd_array[operand_index]; |
| 27038 | } |
| 27039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27041 | _opnd_array[operand_index] = operand; |
| 27042 | } |
| 27043 | private: |
| 27044 | virtual const RegMask &out_RegMask() const; |
| 27045 | virtual uint rule() const { return cmpFastLock_rule; } |
| 27046 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27047 | virtual int ideal_Opcode() const { return Op_FastLock; } |
| 27048 | virtual uint oper_input_base() const { return 1; } |
| 27049 | public: |
| 27050 | cmpFastLockNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 27051 | virtual uint size_of() const { return sizeof(cmpFastLockNode); } |
| 27052 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27053 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27054 | // Rematerialize cmpFastLock |
| 27055 | static const Pipeline *pipeline_class(); |
| 27056 | virtual const Pipeline *pipeline() const; |
| 27057 | #ifndef PRODUCT |
| 27058 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27059 | virtual const char *Name() const { return "cmpFastLock";} |
| 27060 | #endif |
| 27061 | }; |
| 27062 | |
| 27063 | class cmpFastUnlockNode : public MachNode { |
| 27064 | private: |
| 27065 | MachOper *_opnd_array[4]; |
| 27066 | public: |
| 27067 | MachOper *opnd_array(uint operand_index) const { |
| 27068 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27069 | return _opnd_array[operand_index]; |
| 27070 | } |
| 27071 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27072 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27073 | _opnd_array[operand_index] = operand; |
| 27074 | } |
| 27075 | private: |
| 27076 | virtual const RegMask &out_RegMask() const; |
| 27077 | virtual uint rule() const { return cmpFastUnlock_rule; } |
| 27078 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27079 | virtual int ideal_Opcode() const { return Op_FastUnlock; } |
| 27080 | public: |
| 27081 | cmpFastUnlockNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 27082 | virtual uint size_of() const { return sizeof(cmpFastUnlockNode); } |
| 27083 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27084 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27085 | // Rematerialize cmpFastUnlock |
| 27086 | static const Pipeline *pipeline_class(); |
| 27087 | virtual const Pipeline *pipeline() const; |
| 27088 | #ifndef PRODUCT |
| 27089 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27090 | virtual const char *Name() const { return "cmpFastUnlock";} |
| 27091 | #endif |
| 27092 | }; |
| 27093 | |
| 27094 | class safePoint_pollNode : public MachSafePointNode { |
| 27095 | private: |
| 27096 | MachOper *_opnd_array[2]; |
| 27097 | public: |
| 27098 | MachOper *opnd_array(uint operand_index) const { |
| 27099 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27100 | return _opnd_array[operand_index]; |
| 27101 | } |
| 27102 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27103 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27104 | _opnd_array[operand_index] = operand; |
| 27105 | } |
| 27106 | private: |
| 27107 | virtual const RegMask &out_RegMask() const; |
| 27108 | virtual uint rule() const { return safePoint_poll_rule; } |
| 27109 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27110 | virtual int ideal_Opcode() const { return Op_SafePoint; } |
| 27111 | virtual int reloc() const; |
| 27112 | virtual uint oper_input_base() const { return 5; } |
| 27113 | public: |
| 27114 | safePoint_pollNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27115 | virtual uint size_of() const { return sizeof(safePoint_pollNode); } |
| 27116 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27117 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27118 | // Rematerialize safePoint_poll |
| 27119 | static const Pipeline *pipeline_class(); |
| 27120 | virtual const Pipeline *pipeline() const; |
| 27121 | #ifndef PRODUCT |
| 27122 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27123 | virtual const char *Name() const { return "safePoint_poll";} |
| 27124 | #endif |
| 27125 | }; |
| 27126 | |
| 27127 | class safePoint_poll_farNode : public MachSafePointNode { |
| 27128 | private: |
| 27129 | MachOper *_opnd_array[2]; |
| 27130 | public: |
| 27131 | MachOper *opnd_array(uint operand_index) const { |
| 27132 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27133 | return _opnd_array[operand_index]; |
| 27134 | } |
| 27135 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27136 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27137 | _opnd_array[operand_index] = operand; |
| 27138 | } |
| 27139 | private: |
| 27140 | virtual const RegMask &out_RegMask() const; |
| 27141 | virtual uint rule() const { return safePoint_poll_far_rule; } |
| 27142 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27143 | virtual int ideal_Opcode() const { return Op_SafePoint; } |
| 27144 | virtual int reloc() const; |
| 27145 | virtual uint oper_input_base() const { return 5; } |
| 27146 | public: |
| 27147 | safePoint_poll_farNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27148 | virtual uint size_of() const { return sizeof(safePoint_poll_farNode); } |
| 27149 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27150 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27151 | static const Pipeline *pipeline_class(); |
| 27152 | virtual const Pipeline *pipeline() const; |
| 27153 | #ifndef PRODUCT |
| 27154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27155 | virtual const char *Name() const { return "safePoint_poll_far";} |
| 27156 | #endif |
| 27157 | }; |
| 27158 | |
| 27159 | class safePoint_poll_tlsNode : public MachSafePointNode { |
| 27160 | private: |
| 27161 | MachOper *_opnd_array[2]; |
| 27162 | public: |
| 27163 | MachOper *opnd_array(uint operand_index) const { |
| 27164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27165 | return _opnd_array[operand_index]; |
| 27166 | } |
| 27167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27169 | _opnd_array[operand_index] = operand; |
| 27170 | } |
| 27171 | private: |
| 27172 | virtual const RegMask &out_RegMask() const; |
| 27173 | virtual uint rule() const { return safePoint_poll_tls_rule; } |
| 27174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27175 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 27176 | virtual int ideal_Opcode() const { return Op_SafePoint; } |
| 27177 | virtual int reloc() const; |
| 27178 | virtual uint oper_input_base() const { return 5; } |
| 27179 | public: |
| 27180 | safePoint_poll_tlsNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27181 | virtual uint size_of() const { return sizeof(safePoint_poll_tlsNode); } |
| 27182 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27183 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27184 | static const Pipeline *pipeline_class(); |
| 27185 | virtual const Pipeline *pipeline() const; |
| 27186 | #ifndef PRODUCT |
| 27187 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27188 | virtual const char *Name() const { return "safePoint_poll_tls";} |
| 27189 | #endif |
| 27190 | }; |
| 27191 | |
| 27192 | class CallStaticJavaDirectNode : public MachCallStaticJavaNode { |
| 27193 | private: |
| 27194 | MachOper *_opnd_array[2]; |
| 27195 | public: |
| 27196 | MachOper *opnd_array(uint operand_index) const { |
| 27197 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27198 | return _opnd_array[operand_index]; |
| 27199 | } |
| 27200 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27201 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27202 | _opnd_array[operand_index] = operand; |
| 27203 | } |
| 27204 | private: |
| 27205 | virtual const RegMask &out_RegMask() const; |
| 27206 | virtual uint rule() const { return CallStaticJavaDirect_rule; } |
| 27207 | virtual void method_set( intptr_t method ); |
| 27208 | virtual int ins_alignment() const { return 4; } |
| 27209 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27210 | virtual int ideal_Opcode() const { return Op_CallStaticJava; } |
| 27211 | virtual int reloc() const; |
| 27212 | virtual int alignment_required() const { return 4; } |
| 27213 | virtual int compute_padding(int current_offset) const; |
| 27214 | virtual uint oper_input_base() const { return 1; } |
| 27215 | public: |
| 27216 | CallStaticJavaDirectNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27217 | virtual uint size_of() const { return sizeof(CallStaticJavaDirectNode); } |
| 27218 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27219 | static const Pipeline *pipeline_class(); |
| 27220 | virtual const Pipeline *pipeline() const; |
| 27221 | #ifndef PRODUCT |
| 27222 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27223 | virtual const char *Name() const { return "CallStaticJavaDirect";} |
| 27224 | #endif |
| 27225 | }; |
| 27226 | |
| 27227 | class CallDynamicJavaDirectNode : public MachCallDynamicJavaNode { |
| 27228 | private: |
| 27229 | MachOper *_opnd_array[2]; |
| 27230 | public: |
| 27231 | MachOper *opnd_array(uint operand_index) const { |
| 27232 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27233 | return _opnd_array[operand_index]; |
| 27234 | } |
| 27235 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27236 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27237 | _opnd_array[operand_index] = operand; |
| 27238 | } |
| 27239 | private: |
| 27240 | virtual const RegMask &out_RegMask() const; |
| 27241 | virtual uint rule() const { return CallDynamicJavaDirect_rule; } |
| 27242 | virtual void method_set( intptr_t method ); |
| 27243 | virtual int ins_alignment() const { return 4; } |
| 27244 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27245 | virtual int ideal_Opcode() const { return Op_CallDynamicJava; } |
| 27246 | virtual int reloc() const; |
| 27247 | virtual int alignment_required() const { return 4; } |
| 27248 | virtual int compute_padding(int current_offset) const; |
| 27249 | virtual uint oper_input_base() const { return 1; } |
| 27250 | public: |
| 27251 | CallDynamicJavaDirectNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27252 | virtual uint size_of() const { return sizeof(CallDynamicJavaDirectNode); } |
| 27253 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27254 | static const Pipeline *pipeline_class(); |
| 27255 | virtual const Pipeline *pipeline() const; |
| 27256 | #ifndef PRODUCT |
| 27257 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27258 | virtual const char *Name() const { return "CallDynamicJavaDirect";} |
| 27259 | #endif |
| 27260 | }; |
| 27261 | |
| 27262 | class CallRuntimeDirectNode : public MachCallRuntimeNode { |
| 27263 | private: |
| 27264 | MachOper *_opnd_array[2]; |
| 27265 | public: |
| 27266 | MachOper *opnd_array(uint operand_index) const { |
| 27267 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27268 | return _opnd_array[operand_index]; |
| 27269 | } |
| 27270 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27271 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27272 | _opnd_array[operand_index] = operand; |
| 27273 | } |
| 27274 | private: |
| 27275 | virtual const RegMask &out_RegMask() const; |
| 27276 | virtual uint rule() const { return CallRuntimeDirect_rule; } |
| 27277 | virtual void method_set( intptr_t method ); |
| 27278 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27279 | virtual int ideal_Opcode() const { return Op_CallRuntime; } |
| 27280 | virtual int reloc() const; |
| 27281 | virtual uint oper_input_base() const { return 1; } |
| 27282 | public: |
| 27283 | CallRuntimeDirectNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27284 | virtual uint size_of() const { return sizeof(CallRuntimeDirectNode); } |
| 27285 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27286 | static const Pipeline *pipeline_class(); |
| 27287 | virtual const Pipeline *pipeline() const; |
| 27288 | #ifndef PRODUCT |
| 27289 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27290 | virtual const char *Name() const { return "CallRuntimeDirect";} |
| 27291 | #endif |
| 27292 | }; |
| 27293 | |
| 27294 | class CallLeafDirectNode : public MachCallLeafNode { |
| 27295 | private: |
| 27296 | MachOper *_opnd_array[2]; |
| 27297 | public: |
| 27298 | MachOper *opnd_array(uint operand_index) const { |
| 27299 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27300 | return _opnd_array[operand_index]; |
| 27301 | } |
| 27302 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27303 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27304 | _opnd_array[operand_index] = operand; |
| 27305 | } |
| 27306 | private: |
| 27307 | virtual const RegMask &out_RegMask() const; |
| 27308 | virtual uint rule() const { return CallLeafDirect_rule; } |
| 27309 | virtual void method_set( intptr_t method ); |
| 27310 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27311 | virtual int ideal_Opcode() const { return Op_CallLeaf; } |
| 27312 | virtual int reloc() const; |
| 27313 | virtual uint oper_input_base() const { return 1; } |
| 27314 | public: |
| 27315 | CallLeafDirectNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27316 | virtual uint size_of() const { return sizeof(CallLeafDirectNode); } |
| 27317 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27318 | static const Pipeline *pipeline_class(); |
| 27319 | virtual const Pipeline *pipeline() const; |
| 27320 | #ifndef PRODUCT |
| 27321 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27322 | virtual const char *Name() const { return "CallLeafDirect";} |
| 27323 | #endif |
| 27324 | }; |
| 27325 | |
| 27326 | class CallLeafNoFPDirectNode : public MachCallLeafNode { |
| 27327 | private: |
| 27328 | MachOper *_opnd_array[2]; |
| 27329 | public: |
| 27330 | MachOper *opnd_array(uint operand_index) const { |
| 27331 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27332 | return _opnd_array[operand_index]; |
| 27333 | } |
| 27334 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27335 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27336 | _opnd_array[operand_index] = operand; |
| 27337 | } |
| 27338 | private: |
| 27339 | virtual const RegMask &out_RegMask() const; |
| 27340 | virtual uint rule() const { return CallLeafNoFPDirect_rule; } |
| 27341 | virtual void method_set( intptr_t method ); |
| 27342 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27343 | virtual int ideal_Opcode() const { return Op_CallLeafNoFP; } |
| 27344 | virtual int reloc() const; |
| 27345 | virtual uint oper_input_base() const { return 1; } |
| 27346 | public: |
| 27347 | CallLeafNoFPDirectNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 27348 | virtual uint size_of() const { return sizeof(CallLeafNoFPDirectNode); } |
| 27349 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27350 | static const Pipeline *pipeline_class(); |
| 27351 | virtual const Pipeline *pipeline() const; |
| 27352 | #ifndef PRODUCT |
| 27353 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27354 | virtual const char *Name() const { return "CallLeafNoFPDirect";} |
| 27355 | #endif |
| 27356 | }; |
| 27357 | |
| 27358 | class RetNode : public MachReturnNode { |
| 27359 | private: |
| 27360 | MachOper *_opnd_array[1]; |
| 27361 | public: |
| 27362 | MachOper *opnd_array(uint operand_index) const { |
| 27363 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27364 | return _opnd_array[operand_index]; |
| 27365 | } |
| 27366 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27367 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27368 | _opnd_array[operand_index] = operand; |
| 27369 | } |
| 27370 | private: |
| 27371 | virtual const RegMask &out_RegMask() const; |
| 27372 | virtual uint rule() const { return Ret_rule; } |
| 27373 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27374 | virtual int ideal_Opcode() const { return Op_Return; } |
| 27375 | virtual int reloc() const; |
| 27376 | virtual uint oper_input_base() const { return 5; } |
| 27377 | public: |
| 27378 | RetNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 27379 | virtual uint size_of() const { return sizeof(RetNode); } |
| 27380 | virtual bool pinned() const { return true; } |
| 27381 | virtual const Node *is_block_proj() const { return this; } |
| 27382 | static const Pipeline *pipeline_class(); |
| 27383 | virtual const Pipeline *pipeline() const; |
| 27384 | #ifndef PRODUCT |
| 27385 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27386 | virtual const char *Name() const { return "Ret";} |
| 27387 | #endif |
| 27388 | }; |
| 27389 | |
| 27390 | class TailCalljmpIndNode : public MachReturnNode { |
| 27391 | private: |
| 27392 | MachOper *_opnd_array[3]; |
| 27393 | public: |
| 27394 | MachOper *opnd_array(uint operand_index) const { |
| 27395 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27396 | return _opnd_array[operand_index]; |
| 27397 | } |
| 27398 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27399 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27400 | _opnd_array[operand_index] = operand; |
| 27401 | } |
| 27402 | private: |
| 27403 | virtual const RegMask &out_RegMask() const; |
| 27404 | virtual uint rule() const { return TailCalljmpInd_rule; } |
| 27405 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27406 | virtual int ideal_Opcode() const { return Op_TailCall; } |
| 27407 | virtual int reloc() const; |
| 27408 | virtual uint oper_input_base() const { return 5; } |
| 27409 | public: |
| 27410 | TailCalljmpIndNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27411 | virtual uint size_of() const { return sizeof(TailCalljmpIndNode); } |
| 27412 | virtual bool pinned() const { return true; } |
| 27413 | virtual const Node *is_block_proj() const { return this; } |
| 27414 | static const Pipeline *pipeline_class(); |
| 27415 | virtual const Pipeline *pipeline() const; |
| 27416 | #ifndef PRODUCT |
| 27417 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27418 | virtual const char *Name() const { return "TailCalljmpInd";} |
| 27419 | #endif |
| 27420 | }; |
| 27421 | |
| 27422 | class tailjmpIndNode : public MachReturnNode { |
| 27423 | private: |
| 27424 | MachOper *_opnd_array[3]; |
| 27425 | public: |
| 27426 | MachOper *opnd_array(uint operand_index) const { |
| 27427 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27428 | return _opnd_array[operand_index]; |
| 27429 | } |
| 27430 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27431 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27432 | _opnd_array[operand_index] = operand; |
| 27433 | } |
| 27434 | private: |
| 27435 | virtual const RegMask &out_RegMask() const; |
| 27436 | virtual uint rule() const { return tailjmpInd_rule; } |
| 27437 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27438 | virtual int ideal_Opcode() const { return Op_TailJump; } |
| 27439 | virtual int reloc() const; |
| 27440 | virtual uint oper_input_base() const { return 5; } |
| 27441 | public: |
| 27442 | tailjmpIndNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27443 | virtual uint size_of() const { return sizeof(tailjmpIndNode); } |
| 27444 | virtual bool pinned() const { return true; } |
| 27445 | virtual const Node *is_block_proj() const { return this; } |
| 27446 | static const Pipeline *pipeline_class(); |
| 27447 | virtual const Pipeline *pipeline() const; |
| 27448 | #ifndef PRODUCT |
| 27449 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27450 | virtual const char *Name() const { return "tailjmpInd";} |
| 27451 | #endif |
| 27452 | }; |
| 27453 | |
| 27454 | class CreateExceptionNode : public MachTypeNode { |
| 27455 | private: |
| 27456 | MachOper *_opnd_array[1]; |
| 27457 | public: |
| 27458 | MachOper *opnd_array(uint operand_index) const { |
| 27459 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27460 | return _opnd_array[operand_index]; |
| 27461 | } |
| 27462 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27463 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27464 | _opnd_array[operand_index] = operand; |
| 27465 | } |
| 27466 | private: |
| 27467 | virtual const RegMask &out_RegMask() const; |
| 27468 | virtual uint rule() const { return CreateException_rule; } |
| 27469 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27470 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 27471 | virtual int ideal_Opcode() const { return Op_CreateEx; } |
| 27472 | virtual uint oper_input_base() const { return 1; } |
| 27473 | public: |
| 27474 | CreateExceptionNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 27475 | virtual uint size_of() const { return sizeof(CreateExceptionNode); } |
| 27476 | static const Pipeline *pipeline_class(); |
| 27477 | virtual const Pipeline *pipeline() const; |
| 27478 | #ifndef PRODUCT |
| 27479 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27480 | virtual const char *Name() const { return "CreateException";} |
| 27481 | #endif |
| 27482 | }; |
| 27483 | |
| 27484 | class RethrowExceptionNode : public MachReturnNode { |
| 27485 | private: |
| 27486 | MachOper *_opnd_array[1]; |
| 27487 | public: |
| 27488 | MachOper *opnd_array(uint operand_index) const { |
| 27489 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27490 | return _opnd_array[operand_index]; |
| 27491 | } |
| 27492 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27493 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27494 | _opnd_array[operand_index] = operand; |
| 27495 | } |
| 27496 | private: |
| 27497 | virtual const RegMask &out_RegMask() const; |
| 27498 | virtual uint rule() const { return RethrowException_rule; } |
| 27499 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27500 | virtual int ideal_Opcode() const { return Op_Rethrow; } |
| 27501 | virtual int reloc() const; |
| 27502 | virtual uint oper_input_base() const { return 5; } |
| 27503 | public: |
| 27504 | RethrowExceptionNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 27505 | virtual uint size_of() const { return sizeof(RethrowExceptionNode); } |
| 27506 | virtual bool pinned() const { return true; } |
| 27507 | virtual const Node *is_block_proj() const { return this; } |
| 27508 | static const Pipeline *pipeline_class(); |
| 27509 | virtual const Pipeline *pipeline() const; |
| 27510 | #ifndef PRODUCT |
| 27511 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27512 | virtual const char *Name() const { return "RethrowException";} |
| 27513 | #endif |
| 27514 | }; |
| 27515 | |
| 27516 | class tlsLoadPNode : public MachNode { |
| 27517 | private: |
| 27518 | MachOper *_opnd_array[1]; |
| 27519 | public: |
| 27520 | MachOper *opnd_array(uint operand_index) const { |
| 27521 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27522 | return _opnd_array[operand_index]; |
| 27523 | } |
| 27524 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27525 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27526 | _opnd_array[operand_index] = operand; |
| 27527 | } |
| 27528 | private: |
| 27529 | virtual const RegMask &out_RegMask() const; |
| 27530 | virtual uint rule() const { return tlsLoadP_rule; } |
| 27531 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27532 | virtual uint size(PhaseRegAlloc *ra_) const; |
| 27533 | virtual int ideal_Opcode() const { return Op_ThreadLocal; } |
| 27534 | public: |
| 27535 | tlsLoadPNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 27536 | virtual uint size_of() const { return sizeof(tlsLoadPNode); } |
| 27537 | // Rematerialize tlsLoadP |
| 27538 | static const Pipeline *pipeline_class(); |
| 27539 | virtual const Pipeline *pipeline() const; |
| 27540 | const Type *bottom_type() const { return TypeRawPtr::BOTTOM; } // tlsLoadP |
| 27541 | #ifndef PRODUCT |
| 27542 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27543 | virtual const char *Name() const { return "tlsLoadP";} |
| 27544 | #endif |
| 27545 | }; |
| 27546 | |
| 27547 | class ShouldNotReachHereNode : public MachHaltNode { |
| 27548 | private: |
| 27549 | MachOper *_opnd_array[1]; |
| 27550 | public: |
| 27551 | MachOper *opnd_array(uint operand_index) const { |
| 27552 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27553 | return _opnd_array[operand_index]; |
| 27554 | } |
| 27555 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27556 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27557 | _opnd_array[operand_index] = operand; |
| 27558 | } |
| 27559 | private: |
| 27560 | virtual const RegMask &out_RegMask() const; |
| 27561 | virtual uint rule() const { return ShouldNotReachHere_rule; } |
| 27562 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27563 | virtual int ideal_Opcode() const { return Op_Halt; } |
| 27564 | virtual uint oper_input_base() const { return 5; } |
| 27565 | public: |
| 27566 | ShouldNotReachHereNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 27567 | virtual uint size_of() const { return sizeof(ShouldNotReachHereNode); } |
| 27568 | virtual bool pinned() const { return true; } |
| 27569 | virtual const Node *is_block_proj() const { return this; } |
| 27570 | static const Pipeline *pipeline_class(); |
| 27571 | virtual const Pipeline *pipeline() const; |
| 27572 | #ifndef PRODUCT |
| 27573 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27574 | virtual const char *Name() const { return "ShouldNotReachHere";} |
| 27575 | #endif |
| 27576 | }; |
| 27577 | |
| 27578 | class setMaskNode : public MachNode { |
| 27579 | private: |
| 27580 | MachOper *_opnd_array[3]; |
| 27581 | public: |
| 27582 | MachOper *opnd_array(uint operand_index) const { |
| 27583 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27584 | return _opnd_array[operand_index]; |
| 27585 | } |
| 27586 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27587 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27588 | _opnd_array[operand_index] = operand; |
| 27589 | } |
| 27590 | private: |
| 27591 | virtual const RegMask &out_RegMask() const; |
| 27592 | virtual uint rule() const { return setMask_rule; } |
| 27593 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27594 | virtual int ideal_Opcode() const { return Op_SetVectMaskI; } |
| 27595 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 27596 | public: |
| 27597 | setMaskNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27598 | virtual uint size_of() const { return sizeof(setMaskNode); } |
| 27599 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27600 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 27601 | static const Pipeline *pipeline_class(); |
| 27602 | virtual const Pipeline *pipeline() const; |
| 27603 | #ifndef PRODUCT |
| 27604 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27605 | virtual const char *Name() const { return "setMask";} |
| 27606 | #endif |
| 27607 | }; |
| 27608 | |
| 27609 | class addF_regNode : public MachNode { |
| 27610 | private: |
| 27611 | MachOper *_opnd_array[3]; |
| 27612 | public: |
| 27613 | MachOper *opnd_array(uint operand_index) const { |
| 27614 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27615 | return _opnd_array[operand_index]; |
| 27616 | } |
| 27617 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27619 | _opnd_array[operand_index] = operand; |
| 27620 | } |
| 27621 | private: |
| 27622 | const RegMask *_cisc_RegMask; |
| 27623 | virtual const RegMask &out_RegMask() const; |
| 27624 | virtual uint rule() const { return addF_reg_rule; } |
| 27625 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27626 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27627 | virtual uint two_adr() const { return oper_input_base(); } |
| 27628 | virtual int cisc_operand() const { return 2; } |
| 27629 | virtual MachNode *cisc_version(int offset); |
| 27630 | virtual void use_cisc_RegMask(); |
| 27631 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 27632 | public: |
| 27633 | addF_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 27634 | virtual uint size_of() const { return sizeof(addF_regNode); } |
| 27635 | static const Pipeline *pipeline_class(); |
| 27636 | virtual const Pipeline *pipeline() const; |
| 27637 | #ifndef PRODUCT |
| 27638 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27639 | virtual const char *Name() const { return "addF_reg";} |
| 27640 | #endif |
| 27641 | }; |
| 27642 | |
| 27643 | class addF_memNode : public MachNode { |
| 27644 | private: |
| 27645 | MachOper *_opnd_array[3]; |
| 27646 | public: |
| 27647 | MachOper *opnd_array(uint operand_index) const { |
| 27648 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27649 | return _opnd_array[operand_index]; |
| 27650 | } |
| 27651 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27652 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27653 | _opnd_array[operand_index] = operand; |
| 27654 | } |
| 27655 | private: |
| 27656 | virtual const RegMask &out_RegMask() const; |
| 27657 | virtual uint rule() const { return addF_mem_rule; } |
| 27658 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27659 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27660 | virtual uint two_adr() const { return oper_input_base(); } |
| 27661 | virtual int reloc() const; |
| 27662 | virtual uint oper_input_base() const { return 2; } |
| 27663 | public: |
| 27664 | addF_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 27665 | virtual uint size_of() const { return sizeof(addF_memNode); } |
| 27666 | static const Pipeline *pipeline_class(); |
| 27667 | virtual const Pipeline *pipeline() const; |
| 27668 | virtual const MachOper *memory_operand() const; |
| 27669 | #ifndef PRODUCT |
| 27670 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27671 | virtual const char *Name() const { return "addF_mem";} |
| 27672 | #endif |
| 27673 | }; |
| 27674 | |
| 27675 | class addF_mem_0Node : public MachNode { |
| 27676 | private: |
| 27677 | MachOper *_opnd_array[3]; |
| 27678 | public: |
| 27679 | MachOper *opnd_array(uint operand_index) const { |
| 27680 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27681 | return _opnd_array[operand_index]; |
| 27682 | } |
| 27683 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27684 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27685 | _opnd_array[operand_index] = operand; |
| 27686 | } |
| 27687 | private: |
| 27688 | virtual const RegMask &out_RegMask() const; |
| 27689 | virtual uint rule() const { return addF_mem_0_rule; } |
| 27690 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27691 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27692 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 27693 | virtual int reloc() const; |
| 27694 | virtual uint oper_input_base() const { return 2; } |
| 27695 | public: |
| 27696 | addF_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 27697 | virtual uint size_of() const { return sizeof(addF_mem_0Node); } |
| 27698 | static const Pipeline *pipeline_class(); |
| 27699 | virtual const Pipeline *pipeline() const; |
| 27700 | virtual const MachOper *memory_operand() const; |
| 27701 | #ifndef PRODUCT |
| 27702 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27703 | virtual const char *Name() const { return "addF_mem_0";} |
| 27704 | #endif |
| 27705 | }; |
| 27706 | |
| 27707 | class addF_immNode : public MachConstantNode { |
| 27708 | private: |
| 27709 | MachOper *_opnd_array[3]; |
| 27710 | public: |
| 27711 | MachOper *opnd_array(uint operand_index) const { |
| 27712 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27713 | return _opnd_array[operand_index]; |
| 27714 | } |
| 27715 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27716 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27717 | _opnd_array[operand_index] = operand; |
| 27718 | } |
| 27719 | private: |
| 27720 | virtual const RegMask &out_RegMask() const; |
| 27721 | virtual uint rule() const { return addF_imm_rule; } |
| 27722 | virtual void eval_constant(Compile* C); |
| 27723 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27724 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27725 | virtual uint two_adr() const { return oper_input_base(); } |
| 27726 | virtual int reloc() const; |
| 27727 | virtual uint oper_input_base() const { return 1; } |
| 27728 | public: |
| 27729 | addF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27730 | virtual uint size_of() const { return sizeof(addF_immNode); } |
| 27731 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27732 | static const Pipeline *pipeline_class(); |
| 27733 | virtual const Pipeline *pipeline() const; |
| 27734 | #ifndef PRODUCT |
| 27735 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27736 | virtual const char *Name() const { return "addF_imm";} |
| 27737 | #endif |
| 27738 | }; |
| 27739 | |
| 27740 | class addF_reg_regNode : public MachNode { |
| 27741 | private: |
| 27742 | MachOper *_opnd_array[3]; |
| 27743 | public: |
| 27744 | MachOper *opnd_array(uint operand_index) const { |
| 27745 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27746 | return _opnd_array[operand_index]; |
| 27747 | } |
| 27748 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27750 | _opnd_array[operand_index] = operand; |
| 27751 | } |
| 27752 | private: |
| 27753 | const RegMask *_cisc_RegMask; |
| 27754 | virtual const RegMask &out_RegMask() const; |
| 27755 | virtual uint rule() const { return addF_reg_reg_rule; } |
| 27756 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27757 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27758 | virtual int cisc_operand() const { return 2; } |
| 27759 | virtual MachNode *cisc_version(int offset); |
| 27760 | virtual void use_cisc_RegMask(); |
| 27761 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 27762 | public: |
| 27763 | addF_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 27764 | virtual uint size_of() const { return sizeof(addF_reg_regNode); } |
| 27765 | static const Pipeline *pipeline_class(); |
| 27766 | virtual const Pipeline *pipeline() const; |
| 27767 | #ifndef PRODUCT |
| 27768 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27769 | virtual const char *Name() const { return "addF_reg_reg";} |
| 27770 | #endif |
| 27771 | }; |
| 27772 | |
| 27773 | class addF_reg_memNode : public MachNode { |
| 27774 | private: |
| 27775 | MachOper *_opnd_array[3]; |
| 27776 | public: |
| 27777 | MachOper *opnd_array(uint operand_index) const { |
| 27778 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27779 | return _opnd_array[operand_index]; |
| 27780 | } |
| 27781 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27782 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27783 | _opnd_array[operand_index] = operand; |
| 27784 | } |
| 27785 | private: |
| 27786 | virtual const RegMask &out_RegMask() const; |
| 27787 | virtual uint rule() const { return addF_reg_mem_rule; } |
| 27788 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27789 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27790 | virtual int reloc() const; |
| 27791 | virtual uint oper_input_base() const { return 2; } |
| 27792 | public: |
| 27793 | addF_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 27794 | virtual uint size_of() const { return sizeof(addF_reg_memNode); } |
| 27795 | static const Pipeline *pipeline_class(); |
| 27796 | virtual const Pipeline *pipeline() const; |
| 27797 | virtual const MachOper *memory_operand() const; |
| 27798 | #ifndef PRODUCT |
| 27799 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27800 | virtual const char *Name() const { return "addF_reg_mem";} |
| 27801 | #endif |
| 27802 | }; |
| 27803 | |
| 27804 | class addF_reg_mem_0Node : public MachNode { |
| 27805 | private: |
| 27806 | MachOper *_opnd_array[3]; |
| 27807 | public: |
| 27808 | MachOper *opnd_array(uint operand_index) const { |
| 27809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27810 | return _opnd_array[operand_index]; |
| 27811 | } |
| 27812 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27813 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27814 | _opnd_array[operand_index] = operand; |
| 27815 | } |
| 27816 | private: |
| 27817 | virtual const RegMask &out_RegMask() const; |
| 27818 | virtual uint rule() const { return addF_reg_mem_0_rule; } |
| 27819 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27820 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27821 | virtual int reloc() const; |
| 27822 | virtual uint oper_input_base() const { return 2; } |
| 27823 | public: |
| 27824 | addF_reg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 27825 | virtual uint size_of() const { return sizeof(addF_reg_mem_0Node); } |
| 27826 | static const Pipeline *pipeline_class(); |
| 27827 | virtual const Pipeline *pipeline() const; |
| 27828 | virtual const MachOper *memory_operand() const; |
| 27829 | #ifndef PRODUCT |
| 27830 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27831 | virtual const char *Name() const { return "addF_reg_mem_0";} |
| 27832 | #endif |
| 27833 | }; |
| 27834 | |
| 27835 | class addF_reg_immNode : public MachConstantNode { |
| 27836 | private: |
| 27837 | MachOper *_opnd_array[3]; |
| 27838 | public: |
| 27839 | MachOper *opnd_array(uint operand_index) const { |
| 27840 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27841 | return _opnd_array[operand_index]; |
| 27842 | } |
| 27843 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27845 | _opnd_array[operand_index] = operand; |
| 27846 | } |
| 27847 | private: |
| 27848 | virtual const RegMask &out_RegMask() const; |
| 27849 | virtual uint rule() const { return addF_reg_imm_rule; } |
| 27850 | virtual void eval_constant(Compile* C); |
| 27851 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27852 | virtual int ideal_Opcode() const { return Op_AddF; } |
| 27853 | virtual int reloc() const; |
| 27854 | virtual uint oper_input_base() const { return 1; } |
| 27855 | public: |
| 27856 | addF_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27857 | virtual uint size_of() const { return sizeof(addF_reg_immNode); } |
| 27858 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27859 | static const Pipeline *pipeline_class(); |
| 27860 | virtual const Pipeline *pipeline() const; |
| 27861 | #ifndef PRODUCT |
| 27862 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27863 | virtual const char *Name() const { return "addF_reg_imm";} |
| 27864 | #endif |
| 27865 | }; |
| 27866 | |
| 27867 | class addD_regNode : public MachNode { |
| 27868 | private: |
| 27869 | MachOper *_opnd_array[3]; |
| 27870 | public: |
| 27871 | MachOper *opnd_array(uint operand_index) const { |
| 27872 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27873 | return _opnd_array[operand_index]; |
| 27874 | } |
| 27875 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27876 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27877 | _opnd_array[operand_index] = operand; |
| 27878 | } |
| 27879 | private: |
| 27880 | const RegMask *_cisc_RegMask; |
| 27881 | virtual const RegMask &out_RegMask() const; |
| 27882 | virtual uint rule() const { return addD_reg_rule; } |
| 27883 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27884 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 27885 | virtual uint two_adr() const { return oper_input_base(); } |
| 27886 | virtual int cisc_operand() const { return 2; } |
| 27887 | virtual MachNode *cisc_version(int offset); |
| 27888 | virtual void use_cisc_RegMask(); |
| 27889 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 27890 | public: |
| 27891 | addD_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 27892 | virtual uint size_of() const { return sizeof(addD_regNode); } |
| 27893 | static const Pipeline *pipeline_class(); |
| 27894 | virtual const Pipeline *pipeline() const; |
| 27895 | #ifndef PRODUCT |
| 27896 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27897 | virtual const char *Name() const { return "addD_reg";} |
| 27898 | #endif |
| 27899 | }; |
| 27900 | |
| 27901 | class addD_memNode : public MachNode { |
| 27902 | private: |
| 27903 | MachOper *_opnd_array[3]; |
| 27904 | public: |
| 27905 | MachOper *opnd_array(uint operand_index) const { |
| 27906 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27907 | return _opnd_array[operand_index]; |
| 27908 | } |
| 27909 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27910 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27911 | _opnd_array[operand_index] = operand; |
| 27912 | } |
| 27913 | private: |
| 27914 | virtual const RegMask &out_RegMask() const; |
| 27915 | virtual uint rule() const { return addD_mem_rule; } |
| 27916 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27917 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 27918 | virtual uint two_adr() const { return oper_input_base(); } |
| 27919 | virtual int reloc() const; |
| 27920 | virtual uint oper_input_base() const { return 2; } |
| 27921 | public: |
| 27922 | addD_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 27923 | virtual uint size_of() const { return sizeof(addD_memNode); } |
| 27924 | static const Pipeline *pipeline_class(); |
| 27925 | virtual const Pipeline *pipeline() const; |
| 27926 | virtual const MachOper *memory_operand() const; |
| 27927 | #ifndef PRODUCT |
| 27928 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27929 | virtual const char *Name() const { return "addD_mem";} |
| 27930 | #endif |
| 27931 | }; |
| 27932 | |
| 27933 | class addD_mem_0Node : public MachNode { |
| 27934 | private: |
| 27935 | MachOper *_opnd_array[3]; |
| 27936 | public: |
| 27937 | MachOper *opnd_array(uint operand_index) const { |
| 27938 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27939 | return _opnd_array[operand_index]; |
| 27940 | } |
| 27941 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27942 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27943 | _opnd_array[operand_index] = operand; |
| 27944 | } |
| 27945 | private: |
| 27946 | virtual const RegMask &out_RegMask() const; |
| 27947 | virtual uint rule() const { return addD_mem_0_rule; } |
| 27948 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27949 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 27950 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 27951 | virtual int reloc() const; |
| 27952 | virtual uint oper_input_base() const { return 2; } |
| 27953 | public: |
| 27954 | addD_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 27955 | virtual uint size_of() const { return sizeof(addD_mem_0Node); } |
| 27956 | static const Pipeline *pipeline_class(); |
| 27957 | virtual const Pipeline *pipeline() const; |
| 27958 | virtual const MachOper *memory_operand() const; |
| 27959 | #ifndef PRODUCT |
| 27960 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27961 | virtual const char *Name() const { return "addD_mem_0";} |
| 27962 | #endif |
| 27963 | }; |
| 27964 | |
| 27965 | class addD_immNode : public MachConstantNode { |
| 27966 | private: |
| 27967 | MachOper *_opnd_array[3]; |
| 27968 | public: |
| 27969 | MachOper *opnd_array(uint operand_index) const { |
| 27970 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27971 | return _opnd_array[operand_index]; |
| 27972 | } |
| 27973 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 27974 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 27975 | _opnd_array[operand_index] = operand; |
| 27976 | } |
| 27977 | private: |
| 27978 | virtual const RegMask &out_RegMask() const; |
| 27979 | virtual uint rule() const { return addD_imm_rule; } |
| 27980 | virtual void eval_constant(Compile* C); |
| 27981 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 27982 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 27983 | virtual uint two_adr() const { return oper_input_base(); } |
| 27984 | virtual int reloc() const; |
| 27985 | virtual uint oper_input_base() const { return 1; } |
| 27986 | public: |
| 27987 | addD_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 27988 | virtual uint size_of() const { return sizeof(addD_immNode); } |
| 27989 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 27990 | static const Pipeline *pipeline_class(); |
| 27991 | virtual const Pipeline *pipeline() const; |
| 27992 | #ifndef PRODUCT |
| 27993 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 27994 | virtual const char *Name() const { return "addD_imm";} |
| 27995 | #endif |
| 27996 | }; |
| 27997 | |
| 27998 | class addD_reg_regNode : public MachNode { |
| 27999 | private: |
| 28000 | MachOper *_opnd_array[3]; |
| 28001 | public: |
| 28002 | MachOper *opnd_array(uint operand_index) const { |
| 28003 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28004 | return _opnd_array[operand_index]; |
| 28005 | } |
| 28006 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28007 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28008 | _opnd_array[operand_index] = operand; |
| 28009 | } |
| 28010 | private: |
| 28011 | const RegMask *_cisc_RegMask; |
| 28012 | virtual const RegMask &out_RegMask() const; |
| 28013 | virtual uint rule() const { return addD_reg_reg_rule; } |
| 28014 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28015 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 28016 | virtual int cisc_operand() const { return 2; } |
| 28017 | virtual MachNode *cisc_version(int offset); |
| 28018 | virtual void use_cisc_RegMask(); |
| 28019 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28020 | public: |
| 28021 | addD_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28022 | virtual uint size_of() const { return sizeof(addD_reg_regNode); } |
| 28023 | static const Pipeline *pipeline_class(); |
| 28024 | virtual const Pipeline *pipeline() const; |
| 28025 | #ifndef PRODUCT |
| 28026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28027 | virtual const char *Name() const { return "addD_reg_reg";} |
| 28028 | #endif |
| 28029 | }; |
| 28030 | |
| 28031 | class addD_reg_memNode : public MachNode { |
| 28032 | private: |
| 28033 | MachOper *_opnd_array[3]; |
| 28034 | public: |
| 28035 | MachOper *opnd_array(uint operand_index) const { |
| 28036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28037 | return _opnd_array[operand_index]; |
| 28038 | } |
| 28039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28041 | _opnd_array[operand_index] = operand; |
| 28042 | } |
| 28043 | private: |
| 28044 | virtual const RegMask &out_RegMask() const; |
| 28045 | virtual uint rule() const { return addD_reg_mem_rule; } |
| 28046 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28047 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 28048 | virtual int reloc() const; |
| 28049 | virtual uint oper_input_base() const { return 2; } |
| 28050 | public: |
| 28051 | addD_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28052 | virtual uint size_of() const { return sizeof(addD_reg_memNode); } |
| 28053 | static const Pipeline *pipeline_class(); |
| 28054 | virtual const Pipeline *pipeline() const; |
| 28055 | virtual const MachOper *memory_operand() const; |
| 28056 | #ifndef PRODUCT |
| 28057 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28058 | virtual const char *Name() const { return "addD_reg_mem";} |
| 28059 | #endif |
| 28060 | }; |
| 28061 | |
| 28062 | class addD_reg_mem_0Node : public MachNode { |
| 28063 | private: |
| 28064 | MachOper *_opnd_array[3]; |
| 28065 | public: |
| 28066 | MachOper *opnd_array(uint operand_index) const { |
| 28067 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28068 | return _opnd_array[operand_index]; |
| 28069 | } |
| 28070 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28071 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28072 | _opnd_array[operand_index] = operand; |
| 28073 | } |
| 28074 | private: |
| 28075 | virtual const RegMask &out_RegMask() const; |
| 28076 | virtual uint rule() const { return addD_reg_mem_0_rule; } |
| 28077 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28078 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 28079 | virtual int reloc() const; |
| 28080 | virtual uint oper_input_base() const { return 2; } |
| 28081 | public: |
| 28082 | addD_reg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 28083 | virtual uint size_of() const { return sizeof(addD_reg_mem_0Node); } |
| 28084 | static const Pipeline *pipeline_class(); |
| 28085 | virtual const Pipeline *pipeline() const; |
| 28086 | virtual const MachOper *memory_operand() const; |
| 28087 | #ifndef PRODUCT |
| 28088 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28089 | virtual const char *Name() const { return "addD_reg_mem_0";} |
| 28090 | #endif |
| 28091 | }; |
| 28092 | |
| 28093 | class addD_reg_immNode : public MachConstantNode { |
| 28094 | private: |
| 28095 | MachOper *_opnd_array[3]; |
| 28096 | public: |
| 28097 | MachOper *opnd_array(uint operand_index) const { |
| 28098 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28099 | return _opnd_array[operand_index]; |
| 28100 | } |
| 28101 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28102 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28103 | _opnd_array[operand_index] = operand; |
| 28104 | } |
| 28105 | private: |
| 28106 | virtual const RegMask &out_RegMask() const; |
| 28107 | virtual uint rule() const { return addD_reg_imm_rule; } |
| 28108 | virtual void eval_constant(Compile* C); |
| 28109 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28110 | virtual int ideal_Opcode() const { return Op_AddD; } |
| 28111 | virtual int reloc() const; |
| 28112 | virtual uint oper_input_base() const { return 1; } |
| 28113 | public: |
| 28114 | addD_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28115 | virtual uint size_of() const { return sizeof(addD_reg_immNode); } |
| 28116 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28117 | static const Pipeline *pipeline_class(); |
| 28118 | virtual const Pipeline *pipeline() const; |
| 28119 | #ifndef PRODUCT |
| 28120 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28121 | virtual const char *Name() const { return "addD_reg_imm";} |
| 28122 | #endif |
| 28123 | }; |
| 28124 | |
| 28125 | class subF_regNode : public MachNode { |
| 28126 | private: |
| 28127 | MachOper *_opnd_array[3]; |
| 28128 | public: |
| 28129 | MachOper *opnd_array(uint operand_index) const { |
| 28130 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28131 | return _opnd_array[operand_index]; |
| 28132 | } |
| 28133 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28134 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28135 | _opnd_array[operand_index] = operand; |
| 28136 | } |
| 28137 | private: |
| 28138 | const RegMask *_cisc_RegMask; |
| 28139 | virtual const RegMask &out_RegMask() const; |
| 28140 | virtual uint rule() const { return subF_reg_rule; } |
| 28141 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28142 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28143 | virtual uint two_adr() const { return oper_input_base(); } |
| 28144 | virtual int cisc_operand() const { return 2; } |
| 28145 | virtual MachNode *cisc_version(int offset); |
| 28146 | virtual void use_cisc_RegMask(); |
| 28147 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28148 | public: |
| 28149 | subF_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28150 | virtual uint size_of() const { return sizeof(subF_regNode); } |
| 28151 | static const Pipeline *pipeline_class(); |
| 28152 | virtual const Pipeline *pipeline() const; |
| 28153 | #ifndef PRODUCT |
| 28154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28155 | virtual const char *Name() const { return "subF_reg";} |
| 28156 | #endif |
| 28157 | }; |
| 28158 | |
| 28159 | class subF_memNode : public MachNode { |
| 28160 | private: |
| 28161 | MachOper *_opnd_array[3]; |
| 28162 | public: |
| 28163 | MachOper *opnd_array(uint operand_index) const { |
| 28164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28165 | return _opnd_array[operand_index]; |
| 28166 | } |
| 28167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28169 | _opnd_array[operand_index] = operand; |
| 28170 | } |
| 28171 | private: |
| 28172 | virtual const RegMask &out_RegMask() const; |
| 28173 | virtual uint rule() const { return subF_mem_rule; } |
| 28174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28175 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28176 | virtual uint two_adr() const { return oper_input_base(); } |
| 28177 | virtual int reloc() const; |
| 28178 | virtual uint oper_input_base() const { return 2; } |
| 28179 | public: |
| 28180 | subF_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28181 | virtual uint size_of() const { return sizeof(subF_memNode); } |
| 28182 | static const Pipeline *pipeline_class(); |
| 28183 | virtual const Pipeline *pipeline() const; |
| 28184 | virtual const MachOper *memory_operand() const; |
| 28185 | #ifndef PRODUCT |
| 28186 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28187 | virtual const char *Name() const { return "subF_mem";} |
| 28188 | #endif |
| 28189 | }; |
| 28190 | |
| 28191 | class subF_immNode : public MachConstantNode { |
| 28192 | private: |
| 28193 | MachOper *_opnd_array[3]; |
| 28194 | public: |
| 28195 | MachOper *opnd_array(uint operand_index) const { |
| 28196 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28197 | return _opnd_array[operand_index]; |
| 28198 | } |
| 28199 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28200 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28201 | _opnd_array[operand_index] = operand; |
| 28202 | } |
| 28203 | private: |
| 28204 | virtual const RegMask &out_RegMask() const; |
| 28205 | virtual uint rule() const { return subF_imm_rule; } |
| 28206 | virtual void eval_constant(Compile* C); |
| 28207 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28208 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28209 | virtual uint two_adr() const { return oper_input_base(); } |
| 28210 | virtual int reloc() const; |
| 28211 | virtual uint oper_input_base() const { return 1; } |
| 28212 | public: |
| 28213 | subF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28214 | virtual uint size_of() const { return sizeof(subF_immNode); } |
| 28215 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28216 | static const Pipeline *pipeline_class(); |
| 28217 | virtual const Pipeline *pipeline() const; |
| 28218 | #ifndef PRODUCT |
| 28219 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28220 | virtual const char *Name() const { return "subF_imm";} |
| 28221 | #endif |
| 28222 | }; |
| 28223 | |
| 28224 | class subF_reg_regNode : public MachNode { |
| 28225 | private: |
| 28226 | MachOper *_opnd_array[3]; |
| 28227 | public: |
| 28228 | MachOper *opnd_array(uint operand_index) const { |
| 28229 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28230 | return _opnd_array[operand_index]; |
| 28231 | } |
| 28232 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28233 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28234 | _opnd_array[operand_index] = operand; |
| 28235 | } |
| 28236 | private: |
| 28237 | const RegMask *_cisc_RegMask; |
| 28238 | virtual const RegMask &out_RegMask() const; |
| 28239 | virtual uint rule() const { return subF_reg_reg_rule; } |
| 28240 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28241 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28242 | virtual int cisc_operand() const { return 2; } |
| 28243 | virtual MachNode *cisc_version(int offset); |
| 28244 | virtual void use_cisc_RegMask(); |
| 28245 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28246 | public: |
| 28247 | subF_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28248 | virtual uint size_of() const { return sizeof(subF_reg_regNode); } |
| 28249 | static const Pipeline *pipeline_class(); |
| 28250 | virtual const Pipeline *pipeline() const; |
| 28251 | #ifndef PRODUCT |
| 28252 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28253 | virtual const char *Name() const { return "subF_reg_reg";} |
| 28254 | #endif |
| 28255 | }; |
| 28256 | |
| 28257 | class subF_reg_memNode : public MachNode { |
| 28258 | private: |
| 28259 | MachOper *_opnd_array[3]; |
| 28260 | public: |
| 28261 | MachOper *opnd_array(uint operand_index) const { |
| 28262 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28263 | return _opnd_array[operand_index]; |
| 28264 | } |
| 28265 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28266 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28267 | _opnd_array[operand_index] = operand; |
| 28268 | } |
| 28269 | private: |
| 28270 | virtual const RegMask &out_RegMask() const; |
| 28271 | virtual uint rule() const { return subF_reg_mem_rule; } |
| 28272 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28273 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28274 | virtual int reloc() const; |
| 28275 | virtual uint oper_input_base() const { return 2; } |
| 28276 | public: |
| 28277 | subF_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28278 | virtual uint size_of() const { return sizeof(subF_reg_memNode); } |
| 28279 | static const Pipeline *pipeline_class(); |
| 28280 | virtual const Pipeline *pipeline() const; |
| 28281 | virtual const MachOper *memory_operand() const; |
| 28282 | #ifndef PRODUCT |
| 28283 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28284 | virtual const char *Name() const { return "subF_reg_mem";} |
| 28285 | #endif |
| 28286 | }; |
| 28287 | |
| 28288 | class subF_reg_immNode : public MachConstantNode { |
| 28289 | private: |
| 28290 | MachOper *_opnd_array[3]; |
| 28291 | public: |
| 28292 | MachOper *opnd_array(uint operand_index) const { |
| 28293 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28294 | return _opnd_array[operand_index]; |
| 28295 | } |
| 28296 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28297 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28298 | _opnd_array[operand_index] = operand; |
| 28299 | } |
| 28300 | private: |
| 28301 | virtual const RegMask &out_RegMask() const; |
| 28302 | virtual uint rule() const { return subF_reg_imm_rule; } |
| 28303 | virtual void eval_constant(Compile* C); |
| 28304 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28305 | virtual int ideal_Opcode() const { return Op_SubF; } |
| 28306 | virtual int reloc() const; |
| 28307 | virtual uint oper_input_base() const { return 1; } |
| 28308 | public: |
| 28309 | subF_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28310 | virtual uint size_of() const { return sizeof(subF_reg_immNode); } |
| 28311 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28312 | static const Pipeline *pipeline_class(); |
| 28313 | virtual const Pipeline *pipeline() const; |
| 28314 | #ifndef PRODUCT |
| 28315 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28316 | virtual const char *Name() const { return "subF_reg_imm";} |
| 28317 | #endif |
| 28318 | }; |
| 28319 | |
| 28320 | class subD_regNode : public MachNode { |
| 28321 | private: |
| 28322 | MachOper *_opnd_array[3]; |
| 28323 | public: |
| 28324 | MachOper *opnd_array(uint operand_index) const { |
| 28325 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28326 | return _opnd_array[operand_index]; |
| 28327 | } |
| 28328 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28329 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28330 | _opnd_array[operand_index] = operand; |
| 28331 | } |
| 28332 | private: |
| 28333 | const RegMask *_cisc_RegMask; |
| 28334 | virtual const RegMask &out_RegMask() const; |
| 28335 | virtual uint rule() const { return subD_reg_rule; } |
| 28336 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28337 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28338 | virtual uint two_adr() const { return oper_input_base(); } |
| 28339 | virtual int cisc_operand() const { return 2; } |
| 28340 | virtual MachNode *cisc_version(int offset); |
| 28341 | virtual void use_cisc_RegMask(); |
| 28342 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28343 | public: |
| 28344 | subD_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28345 | virtual uint size_of() const { return sizeof(subD_regNode); } |
| 28346 | static const Pipeline *pipeline_class(); |
| 28347 | virtual const Pipeline *pipeline() const; |
| 28348 | #ifndef PRODUCT |
| 28349 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28350 | virtual const char *Name() const { return "subD_reg";} |
| 28351 | #endif |
| 28352 | }; |
| 28353 | |
| 28354 | class subD_memNode : public MachNode { |
| 28355 | private: |
| 28356 | MachOper *_opnd_array[3]; |
| 28357 | public: |
| 28358 | MachOper *opnd_array(uint operand_index) const { |
| 28359 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28360 | return _opnd_array[operand_index]; |
| 28361 | } |
| 28362 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28363 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28364 | _opnd_array[operand_index] = operand; |
| 28365 | } |
| 28366 | private: |
| 28367 | virtual const RegMask &out_RegMask() const; |
| 28368 | virtual uint rule() const { return subD_mem_rule; } |
| 28369 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28370 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28371 | virtual uint two_adr() const { return oper_input_base(); } |
| 28372 | virtual int reloc() const; |
| 28373 | virtual uint oper_input_base() const { return 2; } |
| 28374 | public: |
| 28375 | subD_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28376 | virtual uint size_of() const { return sizeof(subD_memNode); } |
| 28377 | static const Pipeline *pipeline_class(); |
| 28378 | virtual const Pipeline *pipeline() const; |
| 28379 | virtual const MachOper *memory_operand() const; |
| 28380 | #ifndef PRODUCT |
| 28381 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28382 | virtual const char *Name() const { return "subD_mem";} |
| 28383 | #endif |
| 28384 | }; |
| 28385 | |
| 28386 | class subD_immNode : public MachConstantNode { |
| 28387 | private: |
| 28388 | MachOper *_opnd_array[3]; |
| 28389 | public: |
| 28390 | MachOper *opnd_array(uint operand_index) const { |
| 28391 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28392 | return _opnd_array[operand_index]; |
| 28393 | } |
| 28394 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28395 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28396 | _opnd_array[operand_index] = operand; |
| 28397 | } |
| 28398 | private: |
| 28399 | virtual const RegMask &out_RegMask() const; |
| 28400 | virtual uint rule() const { return subD_imm_rule; } |
| 28401 | virtual void eval_constant(Compile* C); |
| 28402 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28403 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28404 | virtual uint two_adr() const { return oper_input_base(); } |
| 28405 | virtual int reloc() const; |
| 28406 | virtual uint oper_input_base() const { return 1; } |
| 28407 | public: |
| 28408 | subD_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28409 | virtual uint size_of() const { return sizeof(subD_immNode); } |
| 28410 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28411 | static const Pipeline *pipeline_class(); |
| 28412 | virtual const Pipeline *pipeline() const; |
| 28413 | #ifndef PRODUCT |
| 28414 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28415 | virtual const char *Name() const { return "subD_imm";} |
| 28416 | #endif |
| 28417 | }; |
| 28418 | |
| 28419 | class subD_reg_regNode : public MachNode { |
| 28420 | private: |
| 28421 | MachOper *_opnd_array[3]; |
| 28422 | public: |
| 28423 | MachOper *opnd_array(uint operand_index) const { |
| 28424 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28425 | return _opnd_array[operand_index]; |
| 28426 | } |
| 28427 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28428 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28429 | _opnd_array[operand_index] = operand; |
| 28430 | } |
| 28431 | private: |
| 28432 | const RegMask *_cisc_RegMask; |
| 28433 | virtual const RegMask &out_RegMask() const; |
| 28434 | virtual uint rule() const { return subD_reg_reg_rule; } |
| 28435 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28436 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28437 | virtual int cisc_operand() const { return 2; } |
| 28438 | virtual MachNode *cisc_version(int offset); |
| 28439 | virtual void use_cisc_RegMask(); |
| 28440 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28441 | public: |
| 28442 | subD_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28443 | virtual uint size_of() const { return sizeof(subD_reg_regNode); } |
| 28444 | static const Pipeline *pipeline_class(); |
| 28445 | virtual const Pipeline *pipeline() const; |
| 28446 | #ifndef PRODUCT |
| 28447 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28448 | virtual const char *Name() const { return "subD_reg_reg";} |
| 28449 | #endif |
| 28450 | }; |
| 28451 | |
| 28452 | class subD_reg_memNode : public MachNode { |
| 28453 | private: |
| 28454 | MachOper *_opnd_array[3]; |
| 28455 | public: |
| 28456 | MachOper *opnd_array(uint operand_index) const { |
| 28457 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28458 | return _opnd_array[operand_index]; |
| 28459 | } |
| 28460 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28461 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28462 | _opnd_array[operand_index] = operand; |
| 28463 | } |
| 28464 | private: |
| 28465 | virtual const RegMask &out_RegMask() const; |
| 28466 | virtual uint rule() const { return subD_reg_mem_rule; } |
| 28467 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28468 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28469 | virtual int reloc() const; |
| 28470 | virtual uint oper_input_base() const { return 2; } |
| 28471 | public: |
| 28472 | subD_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28473 | virtual uint size_of() const { return sizeof(subD_reg_memNode); } |
| 28474 | static const Pipeline *pipeline_class(); |
| 28475 | virtual const Pipeline *pipeline() const; |
| 28476 | virtual const MachOper *memory_operand() const; |
| 28477 | #ifndef PRODUCT |
| 28478 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28479 | virtual const char *Name() const { return "subD_reg_mem";} |
| 28480 | #endif |
| 28481 | }; |
| 28482 | |
| 28483 | class subD_reg_immNode : public MachConstantNode { |
| 28484 | private: |
| 28485 | MachOper *_opnd_array[3]; |
| 28486 | public: |
| 28487 | MachOper *opnd_array(uint operand_index) const { |
| 28488 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28489 | return _opnd_array[operand_index]; |
| 28490 | } |
| 28491 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28492 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28493 | _opnd_array[operand_index] = operand; |
| 28494 | } |
| 28495 | private: |
| 28496 | virtual const RegMask &out_RegMask() const; |
| 28497 | virtual uint rule() const { return subD_reg_imm_rule; } |
| 28498 | virtual void eval_constant(Compile* C); |
| 28499 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28500 | virtual int ideal_Opcode() const { return Op_SubD; } |
| 28501 | virtual int reloc() const; |
| 28502 | virtual uint oper_input_base() const { return 1; } |
| 28503 | public: |
| 28504 | subD_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28505 | virtual uint size_of() const { return sizeof(subD_reg_immNode); } |
| 28506 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28507 | static const Pipeline *pipeline_class(); |
| 28508 | virtual const Pipeline *pipeline() const; |
| 28509 | #ifndef PRODUCT |
| 28510 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28511 | virtual const char *Name() const { return "subD_reg_imm";} |
| 28512 | #endif |
| 28513 | }; |
| 28514 | |
| 28515 | class mulF_regNode : public MachNode { |
| 28516 | private: |
| 28517 | MachOper *_opnd_array[3]; |
| 28518 | public: |
| 28519 | MachOper *opnd_array(uint operand_index) const { |
| 28520 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28521 | return _opnd_array[operand_index]; |
| 28522 | } |
| 28523 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28524 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28525 | _opnd_array[operand_index] = operand; |
| 28526 | } |
| 28527 | private: |
| 28528 | const RegMask *_cisc_RegMask; |
| 28529 | virtual const RegMask &out_RegMask() const; |
| 28530 | virtual uint rule() const { return mulF_reg_rule; } |
| 28531 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28532 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28533 | virtual uint two_adr() const { return oper_input_base(); } |
| 28534 | virtual int cisc_operand() const { return 2; } |
| 28535 | virtual MachNode *cisc_version(int offset); |
| 28536 | virtual void use_cisc_RegMask(); |
| 28537 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28538 | public: |
| 28539 | mulF_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28540 | virtual uint size_of() const { return sizeof(mulF_regNode); } |
| 28541 | static const Pipeline *pipeline_class(); |
| 28542 | virtual const Pipeline *pipeline() const; |
| 28543 | #ifndef PRODUCT |
| 28544 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28545 | virtual const char *Name() const { return "mulF_reg";} |
| 28546 | #endif |
| 28547 | }; |
| 28548 | |
| 28549 | class mulF_memNode : public MachNode { |
| 28550 | private: |
| 28551 | MachOper *_opnd_array[3]; |
| 28552 | public: |
| 28553 | MachOper *opnd_array(uint operand_index) const { |
| 28554 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28555 | return _opnd_array[operand_index]; |
| 28556 | } |
| 28557 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28558 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28559 | _opnd_array[operand_index] = operand; |
| 28560 | } |
| 28561 | private: |
| 28562 | virtual const RegMask &out_RegMask() const; |
| 28563 | virtual uint rule() const { return mulF_mem_rule; } |
| 28564 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28565 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28566 | virtual uint two_adr() const { return oper_input_base(); } |
| 28567 | virtual int reloc() const; |
| 28568 | virtual uint oper_input_base() const { return 2; } |
| 28569 | public: |
| 28570 | mulF_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28571 | virtual uint size_of() const { return sizeof(mulF_memNode); } |
| 28572 | static const Pipeline *pipeline_class(); |
| 28573 | virtual const Pipeline *pipeline() const; |
| 28574 | virtual const MachOper *memory_operand() const; |
| 28575 | #ifndef PRODUCT |
| 28576 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28577 | virtual const char *Name() const { return "mulF_mem";} |
| 28578 | #endif |
| 28579 | }; |
| 28580 | |
| 28581 | class mulF_mem_0Node : public MachNode { |
| 28582 | private: |
| 28583 | MachOper *_opnd_array[3]; |
| 28584 | public: |
| 28585 | MachOper *opnd_array(uint operand_index) const { |
| 28586 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28587 | return _opnd_array[operand_index]; |
| 28588 | } |
| 28589 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28590 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28591 | _opnd_array[operand_index] = operand; |
| 28592 | } |
| 28593 | private: |
| 28594 | virtual const RegMask &out_RegMask() const; |
| 28595 | virtual uint rule() const { return mulF_mem_0_rule; } |
| 28596 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28597 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28598 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 28599 | virtual int reloc() const; |
| 28600 | virtual uint oper_input_base() const { return 2; } |
| 28601 | public: |
| 28602 | mulF_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 28603 | virtual uint size_of() const { return sizeof(mulF_mem_0Node); } |
| 28604 | static const Pipeline *pipeline_class(); |
| 28605 | virtual const Pipeline *pipeline() const; |
| 28606 | virtual const MachOper *memory_operand() const; |
| 28607 | #ifndef PRODUCT |
| 28608 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28609 | virtual const char *Name() const { return "mulF_mem_0";} |
| 28610 | #endif |
| 28611 | }; |
| 28612 | |
| 28613 | class mulF_immNode : public MachConstantNode { |
| 28614 | private: |
| 28615 | MachOper *_opnd_array[3]; |
| 28616 | public: |
| 28617 | MachOper *opnd_array(uint operand_index) const { |
| 28618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28619 | return _opnd_array[operand_index]; |
| 28620 | } |
| 28621 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28622 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28623 | _opnd_array[operand_index] = operand; |
| 28624 | } |
| 28625 | private: |
| 28626 | virtual const RegMask &out_RegMask() const; |
| 28627 | virtual uint rule() const { return mulF_imm_rule; } |
| 28628 | virtual void eval_constant(Compile* C); |
| 28629 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28630 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28631 | virtual uint two_adr() const { return oper_input_base(); } |
| 28632 | virtual int reloc() const; |
| 28633 | virtual uint oper_input_base() const { return 1; } |
| 28634 | public: |
| 28635 | mulF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28636 | virtual uint size_of() const { return sizeof(mulF_immNode); } |
| 28637 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28638 | static const Pipeline *pipeline_class(); |
| 28639 | virtual const Pipeline *pipeline() const; |
| 28640 | #ifndef PRODUCT |
| 28641 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28642 | virtual const char *Name() const { return "mulF_imm";} |
| 28643 | #endif |
| 28644 | }; |
| 28645 | |
| 28646 | class mulF_reg_regNode : public MachNode { |
| 28647 | private: |
| 28648 | MachOper *_opnd_array[3]; |
| 28649 | public: |
| 28650 | MachOper *opnd_array(uint operand_index) const { |
| 28651 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28652 | return _opnd_array[operand_index]; |
| 28653 | } |
| 28654 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28655 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28656 | _opnd_array[operand_index] = operand; |
| 28657 | } |
| 28658 | private: |
| 28659 | const RegMask *_cisc_RegMask; |
| 28660 | virtual const RegMask &out_RegMask() const; |
| 28661 | virtual uint rule() const { return mulF_reg_reg_rule; } |
| 28662 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28663 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28664 | virtual int cisc_operand() const { return 2; } |
| 28665 | virtual MachNode *cisc_version(int offset); |
| 28666 | virtual void use_cisc_RegMask(); |
| 28667 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28668 | public: |
| 28669 | mulF_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28670 | virtual uint size_of() const { return sizeof(mulF_reg_regNode); } |
| 28671 | static const Pipeline *pipeline_class(); |
| 28672 | virtual const Pipeline *pipeline() const; |
| 28673 | #ifndef PRODUCT |
| 28674 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28675 | virtual const char *Name() const { return "mulF_reg_reg";} |
| 28676 | #endif |
| 28677 | }; |
| 28678 | |
| 28679 | class mulF_reg_memNode : public MachNode { |
| 28680 | private: |
| 28681 | MachOper *_opnd_array[3]; |
| 28682 | public: |
| 28683 | MachOper *opnd_array(uint operand_index) const { |
| 28684 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28685 | return _opnd_array[operand_index]; |
| 28686 | } |
| 28687 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28688 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28689 | _opnd_array[operand_index] = operand; |
| 28690 | } |
| 28691 | private: |
| 28692 | virtual const RegMask &out_RegMask() const; |
| 28693 | virtual uint rule() const { return mulF_reg_mem_rule; } |
| 28694 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28695 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28696 | virtual int reloc() const; |
| 28697 | virtual uint oper_input_base() const { return 2; } |
| 28698 | public: |
| 28699 | mulF_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28700 | virtual uint size_of() const { return sizeof(mulF_reg_memNode); } |
| 28701 | static const Pipeline *pipeline_class(); |
| 28702 | virtual const Pipeline *pipeline() const; |
| 28703 | virtual const MachOper *memory_operand() const; |
| 28704 | #ifndef PRODUCT |
| 28705 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28706 | virtual const char *Name() const { return "mulF_reg_mem";} |
| 28707 | #endif |
| 28708 | }; |
| 28709 | |
| 28710 | class mulF_reg_mem_0Node : public MachNode { |
| 28711 | private: |
| 28712 | MachOper *_opnd_array[3]; |
| 28713 | public: |
| 28714 | MachOper *opnd_array(uint operand_index) const { |
| 28715 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28716 | return _opnd_array[operand_index]; |
| 28717 | } |
| 28718 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28719 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28720 | _opnd_array[operand_index] = operand; |
| 28721 | } |
| 28722 | private: |
| 28723 | virtual const RegMask &out_RegMask() const; |
| 28724 | virtual uint rule() const { return mulF_reg_mem_0_rule; } |
| 28725 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28726 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28727 | virtual int reloc() const; |
| 28728 | virtual uint oper_input_base() const { return 2; } |
| 28729 | public: |
| 28730 | mulF_reg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 28731 | virtual uint size_of() const { return sizeof(mulF_reg_mem_0Node); } |
| 28732 | static const Pipeline *pipeline_class(); |
| 28733 | virtual const Pipeline *pipeline() const; |
| 28734 | virtual const MachOper *memory_operand() const; |
| 28735 | #ifndef PRODUCT |
| 28736 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28737 | virtual const char *Name() const { return "mulF_reg_mem_0";} |
| 28738 | #endif |
| 28739 | }; |
| 28740 | |
| 28741 | class mulF_reg_immNode : public MachConstantNode { |
| 28742 | private: |
| 28743 | MachOper *_opnd_array[3]; |
| 28744 | public: |
| 28745 | MachOper *opnd_array(uint operand_index) const { |
| 28746 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28747 | return _opnd_array[operand_index]; |
| 28748 | } |
| 28749 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28750 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28751 | _opnd_array[operand_index] = operand; |
| 28752 | } |
| 28753 | private: |
| 28754 | virtual const RegMask &out_RegMask() const; |
| 28755 | virtual uint rule() const { return mulF_reg_imm_rule; } |
| 28756 | virtual void eval_constant(Compile* C); |
| 28757 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28758 | virtual int ideal_Opcode() const { return Op_MulF; } |
| 28759 | virtual int reloc() const; |
| 28760 | virtual uint oper_input_base() const { return 1; } |
| 28761 | public: |
| 28762 | mulF_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28763 | virtual uint size_of() const { return sizeof(mulF_reg_immNode); } |
| 28764 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28765 | static const Pipeline *pipeline_class(); |
| 28766 | virtual const Pipeline *pipeline() const; |
| 28767 | #ifndef PRODUCT |
| 28768 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28769 | virtual const char *Name() const { return "mulF_reg_imm";} |
| 28770 | #endif |
| 28771 | }; |
| 28772 | |
| 28773 | class mulD_regNode : public MachNode { |
| 28774 | private: |
| 28775 | MachOper *_opnd_array[3]; |
| 28776 | public: |
| 28777 | MachOper *opnd_array(uint operand_index) const { |
| 28778 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28779 | return _opnd_array[operand_index]; |
| 28780 | } |
| 28781 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28782 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28783 | _opnd_array[operand_index] = operand; |
| 28784 | } |
| 28785 | private: |
| 28786 | const RegMask *_cisc_RegMask; |
| 28787 | virtual const RegMask &out_RegMask() const; |
| 28788 | virtual uint rule() const { return mulD_reg_rule; } |
| 28789 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28790 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28791 | virtual uint two_adr() const { return oper_input_base(); } |
| 28792 | virtual int cisc_operand() const { return 2; } |
| 28793 | virtual MachNode *cisc_version(int offset); |
| 28794 | virtual void use_cisc_RegMask(); |
| 28795 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28796 | public: |
| 28797 | mulD_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28798 | virtual uint size_of() const { return sizeof(mulD_regNode); } |
| 28799 | static const Pipeline *pipeline_class(); |
| 28800 | virtual const Pipeline *pipeline() const; |
| 28801 | #ifndef PRODUCT |
| 28802 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28803 | virtual const char *Name() const { return "mulD_reg";} |
| 28804 | #endif |
| 28805 | }; |
| 28806 | |
| 28807 | class mulD_memNode : public MachNode { |
| 28808 | private: |
| 28809 | MachOper *_opnd_array[3]; |
| 28810 | public: |
| 28811 | MachOper *opnd_array(uint operand_index) const { |
| 28812 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28813 | return _opnd_array[operand_index]; |
| 28814 | } |
| 28815 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28816 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28817 | _opnd_array[operand_index] = operand; |
| 28818 | } |
| 28819 | private: |
| 28820 | virtual const RegMask &out_RegMask() const; |
| 28821 | virtual uint rule() const { return mulD_mem_rule; } |
| 28822 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28823 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28824 | virtual uint two_adr() const { return oper_input_base(); } |
| 28825 | virtual int reloc() const; |
| 28826 | virtual uint oper_input_base() const { return 2; } |
| 28827 | public: |
| 28828 | mulD_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28829 | virtual uint size_of() const { return sizeof(mulD_memNode); } |
| 28830 | static const Pipeline *pipeline_class(); |
| 28831 | virtual const Pipeline *pipeline() const; |
| 28832 | virtual const MachOper *memory_operand() const; |
| 28833 | #ifndef PRODUCT |
| 28834 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28835 | virtual const char *Name() const { return "mulD_mem";} |
| 28836 | #endif |
| 28837 | }; |
| 28838 | |
| 28839 | class mulD_mem_0Node : public MachNode { |
| 28840 | private: |
| 28841 | MachOper *_opnd_array[3]; |
| 28842 | public: |
| 28843 | MachOper *opnd_array(uint operand_index) const { |
| 28844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28845 | return _opnd_array[operand_index]; |
| 28846 | } |
| 28847 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28848 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28849 | _opnd_array[operand_index] = operand; |
| 28850 | } |
| 28851 | private: |
| 28852 | virtual const RegMask &out_RegMask() const; |
| 28853 | virtual uint rule() const { return mulD_mem_0_rule; } |
| 28854 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28855 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28856 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 28857 | virtual int reloc() const; |
| 28858 | virtual uint oper_input_base() const { return 2; } |
| 28859 | public: |
| 28860 | mulD_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 28861 | virtual uint size_of() const { return sizeof(mulD_mem_0Node); } |
| 28862 | static const Pipeline *pipeline_class(); |
| 28863 | virtual const Pipeline *pipeline() const; |
| 28864 | virtual const MachOper *memory_operand() const; |
| 28865 | #ifndef PRODUCT |
| 28866 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28867 | virtual const char *Name() const { return "mulD_mem_0";} |
| 28868 | #endif |
| 28869 | }; |
| 28870 | |
| 28871 | class mulD_immNode : public MachConstantNode { |
| 28872 | private: |
| 28873 | MachOper *_opnd_array[3]; |
| 28874 | public: |
| 28875 | MachOper *opnd_array(uint operand_index) const { |
| 28876 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28877 | return _opnd_array[operand_index]; |
| 28878 | } |
| 28879 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28880 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28881 | _opnd_array[operand_index] = operand; |
| 28882 | } |
| 28883 | private: |
| 28884 | virtual const RegMask &out_RegMask() const; |
| 28885 | virtual uint rule() const { return mulD_imm_rule; } |
| 28886 | virtual void eval_constant(Compile* C); |
| 28887 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28888 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28889 | virtual uint two_adr() const { return oper_input_base(); } |
| 28890 | virtual int reloc() const; |
| 28891 | virtual uint oper_input_base() const { return 1; } |
| 28892 | public: |
| 28893 | mulD_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 28894 | virtual uint size_of() const { return sizeof(mulD_immNode); } |
| 28895 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 28896 | static const Pipeline *pipeline_class(); |
| 28897 | virtual const Pipeline *pipeline() const; |
| 28898 | #ifndef PRODUCT |
| 28899 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28900 | virtual const char *Name() const { return "mulD_imm";} |
| 28901 | #endif |
| 28902 | }; |
| 28903 | |
| 28904 | class mulD_reg_regNode : public MachNode { |
| 28905 | private: |
| 28906 | MachOper *_opnd_array[3]; |
| 28907 | public: |
| 28908 | MachOper *opnd_array(uint operand_index) const { |
| 28909 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28910 | return _opnd_array[operand_index]; |
| 28911 | } |
| 28912 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28913 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28914 | _opnd_array[operand_index] = operand; |
| 28915 | } |
| 28916 | private: |
| 28917 | const RegMask *_cisc_RegMask; |
| 28918 | virtual const RegMask &out_RegMask() const; |
| 28919 | virtual uint rule() const { return mulD_reg_reg_rule; } |
| 28920 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28921 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28922 | virtual int cisc_operand() const { return 2; } |
| 28923 | virtual MachNode *cisc_version(int offset); |
| 28924 | virtual void use_cisc_RegMask(); |
| 28925 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 28926 | public: |
| 28927 | mulD_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 28928 | virtual uint size_of() const { return sizeof(mulD_reg_regNode); } |
| 28929 | static const Pipeline *pipeline_class(); |
| 28930 | virtual const Pipeline *pipeline() const; |
| 28931 | #ifndef PRODUCT |
| 28932 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28933 | virtual const char *Name() const { return "mulD_reg_reg";} |
| 28934 | #endif |
| 28935 | }; |
| 28936 | |
| 28937 | class mulD_reg_memNode : public MachNode { |
| 28938 | private: |
| 28939 | MachOper *_opnd_array[3]; |
| 28940 | public: |
| 28941 | MachOper *opnd_array(uint operand_index) const { |
| 28942 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28943 | return _opnd_array[operand_index]; |
| 28944 | } |
| 28945 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28946 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28947 | _opnd_array[operand_index] = operand; |
| 28948 | } |
| 28949 | private: |
| 28950 | virtual const RegMask &out_RegMask() const; |
| 28951 | virtual uint rule() const { return mulD_reg_mem_rule; } |
| 28952 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28953 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28954 | virtual int reloc() const; |
| 28955 | virtual uint oper_input_base() const { return 2; } |
| 28956 | public: |
| 28957 | mulD_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 28958 | virtual uint size_of() const { return sizeof(mulD_reg_memNode); } |
| 28959 | static const Pipeline *pipeline_class(); |
| 28960 | virtual const Pipeline *pipeline() const; |
| 28961 | virtual const MachOper *memory_operand() const; |
| 28962 | #ifndef PRODUCT |
| 28963 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28964 | virtual const char *Name() const { return "mulD_reg_mem";} |
| 28965 | #endif |
| 28966 | }; |
| 28967 | |
| 28968 | class mulD_reg_mem_0Node : public MachNode { |
| 28969 | private: |
| 28970 | MachOper *_opnd_array[3]; |
| 28971 | public: |
| 28972 | MachOper *opnd_array(uint operand_index) const { |
| 28973 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28974 | return _opnd_array[operand_index]; |
| 28975 | } |
| 28976 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 28977 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 28978 | _opnd_array[operand_index] = operand; |
| 28979 | } |
| 28980 | private: |
| 28981 | virtual const RegMask &out_RegMask() const; |
| 28982 | virtual uint rule() const { return mulD_reg_mem_0_rule; } |
| 28983 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 28984 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 28985 | virtual int reloc() const; |
| 28986 | virtual uint oper_input_base() const { return 2; } |
| 28987 | public: |
| 28988 | mulD_reg_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 28989 | virtual uint size_of() const { return sizeof(mulD_reg_mem_0Node); } |
| 28990 | static const Pipeline *pipeline_class(); |
| 28991 | virtual const Pipeline *pipeline() const; |
| 28992 | virtual const MachOper *memory_operand() const; |
| 28993 | #ifndef PRODUCT |
| 28994 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 28995 | virtual const char *Name() const { return "mulD_reg_mem_0";} |
| 28996 | #endif |
| 28997 | }; |
| 28998 | |
| 28999 | class mulD_reg_immNode : public MachConstantNode { |
| 29000 | private: |
| 29001 | MachOper *_opnd_array[3]; |
| 29002 | public: |
| 29003 | MachOper *opnd_array(uint operand_index) const { |
| 29004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29005 | return _opnd_array[operand_index]; |
| 29006 | } |
| 29007 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29008 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29009 | _opnd_array[operand_index] = operand; |
| 29010 | } |
| 29011 | private: |
| 29012 | virtual const RegMask &out_RegMask() const; |
| 29013 | virtual uint rule() const { return mulD_reg_imm_rule; } |
| 29014 | virtual void eval_constant(Compile* C); |
| 29015 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29016 | virtual int ideal_Opcode() const { return Op_MulD; } |
| 29017 | virtual int reloc() const; |
| 29018 | virtual uint oper_input_base() const { return 1; } |
| 29019 | public: |
| 29020 | mulD_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 29021 | virtual uint size_of() const { return sizeof(mulD_reg_immNode); } |
| 29022 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29023 | static const Pipeline *pipeline_class(); |
| 29024 | virtual const Pipeline *pipeline() const; |
| 29025 | #ifndef PRODUCT |
| 29026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29027 | virtual const char *Name() const { return "mulD_reg_imm";} |
| 29028 | #endif |
| 29029 | }; |
| 29030 | |
| 29031 | class divF_regNode : public MachNode { |
| 29032 | private: |
| 29033 | MachOper *_opnd_array[3]; |
| 29034 | public: |
| 29035 | MachOper *opnd_array(uint operand_index) const { |
| 29036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29037 | return _opnd_array[operand_index]; |
| 29038 | } |
| 29039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29041 | _opnd_array[operand_index] = operand; |
| 29042 | } |
| 29043 | private: |
| 29044 | const RegMask *_cisc_RegMask; |
| 29045 | virtual const RegMask &out_RegMask() const; |
| 29046 | virtual uint rule() const { return divF_reg_rule; } |
| 29047 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29048 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29049 | virtual uint two_adr() const { return oper_input_base(); } |
| 29050 | virtual int cisc_operand() const { return 2; } |
| 29051 | virtual MachNode *cisc_version(int offset); |
| 29052 | virtual void use_cisc_RegMask(); |
| 29053 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29054 | public: |
| 29055 | divF_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 29056 | virtual uint size_of() const { return sizeof(divF_regNode); } |
| 29057 | static const Pipeline *pipeline_class(); |
| 29058 | virtual const Pipeline *pipeline() const; |
| 29059 | #ifndef PRODUCT |
| 29060 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29061 | virtual const char *Name() const { return "divF_reg";} |
| 29062 | #endif |
| 29063 | }; |
| 29064 | |
| 29065 | class divF_memNode : public MachNode { |
| 29066 | private: |
| 29067 | MachOper *_opnd_array[3]; |
| 29068 | public: |
| 29069 | MachOper *opnd_array(uint operand_index) const { |
| 29070 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29071 | return _opnd_array[operand_index]; |
| 29072 | } |
| 29073 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29075 | _opnd_array[operand_index] = operand; |
| 29076 | } |
| 29077 | private: |
| 29078 | virtual const RegMask &out_RegMask() const; |
| 29079 | virtual uint rule() const { return divF_mem_rule; } |
| 29080 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29081 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29082 | virtual uint two_adr() const { return oper_input_base(); } |
| 29083 | virtual int reloc() const; |
| 29084 | virtual uint oper_input_base() const { return 2; } |
| 29085 | public: |
| 29086 | divF_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29087 | virtual uint size_of() const { return sizeof(divF_memNode); } |
| 29088 | static const Pipeline *pipeline_class(); |
| 29089 | virtual const Pipeline *pipeline() const; |
| 29090 | virtual const MachOper *memory_operand() const; |
| 29091 | #ifndef PRODUCT |
| 29092 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29093 | virtual const char *Name() const { return "divF_mem";} |
| 29094 | #endif |
| 29095 | }; |
| 29096 | |
| 29097 | class divF_immNode : public MachConstantNode { |
| 29098 | private: |
| 29099 | MachOper *_opnd_array[3]; |
| 29100 | public: |
| 29101 | MachOper *opnd_array(uint operand_index) const { |
| 29102 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29103 | return _opnd_array[operand_index]; |
| 29104 | } |
| 29105 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29107 | _opnd_array[operand_index] = operand; |
| 29108 | } |
| 29109 | private: |
| 29110 | virtual const RegMask &out_RegMask() const; |
| 29111 | virtual uint rule() const { return divF_imm_rule; } |
| 29112 | virtual void eval_constant(Compile* C); |
| 29113 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29114 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29115 | virtual uint two_adr() const { return oper_input_base(); } |
| 29116 | virtual int reloc() const; |
| 29117 | virtual uint oper_input_base() const { return 1; } |
| 29118 | public: |
| 29119 | divF_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 29120 | virtual uint size_of() const { return sizeof(divF_immNode); } |
| 29121 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29122 | static const Pipeline *pipeline_class(); |
| 29123 | virtual const Pipeline *pipeline() const; |
| 29124 | #ifndef PRODUCT |
| 29125 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29126 | virtual const char *Name() const { return "divF_imm";} |
| 29127 | #endif |
| 29128 | }; |
| 29129 | |
| 29130 | class divF_reg_regNode : public MachNode { |
| 29131 | private: |
| 29132 | MachOper *_opnd_array[3]; |
| 29133 | public: |
| 29134 | MachOper *opnd_array(uint operand_index) const { |
| 29135 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29136 | return _opnd_array[operand_index]; |
| 29137 | } |
| 29138 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29139 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29140 | _opnd_array[operand_index] = operand; |
| 29141 | } |
| 29142 | private: |
| 29143 | const RegMask *_cisc_RegMask; |
| 29144 | virtual const RegMask &out_RegMask() const; |
| 29145 | virtual uint rule() const { return divF_reg_reg_rule; } |
| 29146 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29147 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29148 | virtual int cisc_operand() const { return 2; } |
| 29149 | virtual MachNode *cisc_version(int offset); |
| 29150 | virtual void use_cisc_RegMask(); |
| 29151 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29152 | public: |
| 29153 | divF_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 29154 | virtual uint size_of() const { return sizeof(divF_reg_regNode); } |
| 29155 | static const Pipeline *pipeline_class(); |
| 29156 | virtual const Pipeline *pipeline() const; |
| 29157 | #ifndef PRODUCT |
| 29158 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29159 | virtual const char *Name() const { return "divF_reg_reg";} |
| 29160 | #endif |
| 29161 | }; |
| 29162 | |
| 29163 | class divF_reg_memNode : public MachNode { |
| 29164 | private: |
| 29165 | MachOper *_opnd_array[3]; |
| 29166 | public: |
| 29167 | MachOper *opnd_array(uint operand_index) const { |
| 29168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29169 | return _opnd_array[operand_index]; |
| 29170 | } |
| 29171 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29172 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29173 | _opnd_array[operand_index] = operand; |
| 29174 | } |
| 29175 | private: |
| 29176 | virtual const RegMask &out_RegMask() const; |
| 29177 | virtual uint rule() const { return divF_reg_mem_rule; } |
| 29178 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29179 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29180 | virtual int reloc() const; |
| 29181 | virtual uint oper_input_base() const { return 2; } |
| 29182 | public: |
| 29183 | divF_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29184 | virtual uint size_of() const { return sizeof(divF_reg_memNode); } |
| 29185 | static const Pipeline *pipeline_class(); |
| 29186 | virtual const Pipeline *pipeline() const; |
| 29187 | virtual const MachOper *memory_operand() const; |
| 29188 | #ifndef PRODUCT |
| 29189 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29190 | virtual const char *Name() const { return "divF_reg_mem";} |
| 29191 | #endif |
| 29192 | }; |
| 29193 | |
| 29194 | class divF_reg_immNode : public MachConstantNode { |
| 29195 | private: |
| 29196 | MachOper *_opnd_array[3]; |
| 29197 | public: |
| 29198 | MachOper *opnd_array(uint operand_index) const { |
| 29199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29200 | return _opnd_array[operand_index]; |
| 29201 | } |
| 29202 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29203 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29204 | _opnd_array[operand_index] = operand; |
| 29205 | } |
| 29206 | private: |
| 29207 | virtual const RegMask &out_RegMask() const; |
| 29208 | virtual uint rule() const { return divF_reg_imm_rule; } |
| 29209 | virtual void eval_constant(Compile* C); |
| 29210 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29211 | virtual int ideal_Opcode() const { return Op_DivF; } |
| 29212 | virtual int reloc() const; |
| 29213 | virtual uint oper_input_base() const { return 1; } |
| 29214 | public: |
| 29215 | divF_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 29216 | virtual uint size_of() const { return sizeof(divF_reg_immNode); } |
| 29217 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29218 | static const Pipeline *pipeline_class(); |
| 29219 | virtual const Pipeline *pipeline() const; |
| 29220 | #ifndef PRODUCT |
| 29221 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29222 | virtual const char *Name() const { return "divF_reg_imm";} |
| 29223 | #endif |
| 29224 | }; |
| 29225 | |
| 29226 | class divD_regNode : public MachNode { |
| 29227 | private: |
| 29228 | MachOper *_opnd_array[3]; |
| 29229 | public: |
| 29230 | MachOper *opnd_array(uint operand_index) const { |
| 29231 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29232 | return _opnd_array[operand_index]; |
| 29233 | } |
| 29234 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29235 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29236 | _opnd_array[operand_index] = operand; |
| 29237 | } |
| 29238 | private: |
| 29239 | const RegMask *_cisc_RegMask; |
| 29240 | virtual const RegMask &out_RegMask() const; |
| 29241 | virtual uint rule() const { return divD_reg_rule; } |
| 29242 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29243 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29244 | virtual uint two_adr() const { return oper_input_base(); } |
| 29245 | virtual int cisc_operand() const { return 2; } |
| 29246 | virtual MachNode *cisc_version(int offset); |
| 29247 | virtual void use_cisc_RegMask(); |
| 29248 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29249 | public: |
| 29250 | divD_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 29251 | virtual uint size_of() const { return sizeof(divD_regNode); } |
| 29252 | static const Pipeline *pipeline_class(); |
| 29253 | virtual const Pipeline *pipeline() const; |
| 29254 | #ifndef PRODUCT |
| 29255 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29256 | virtual const char *Name() const { return "divD_reg";} |
| 29257 | #endif |
| 29258 | }; |
| 29259 | |
| 29260 | class divD_memNode : public MachNode { |
| 29261 | private: |
| 29262 | MachOper *_opnd_array[3]; |
| 29263 | public: |
| 29264 | MachOper *opnd_array(uint operand_index) const { |
| 29265 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29266 | return _opnd_array[operand_index]; |
| 29267 | } |
| 29268 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29269 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29270 | _opnd_array[operand_index] = operand; |
| 29271 | } |
| 29272 | private: |
| 29273 | virtual const RegMask &out_RegMask() const; |
| 29274 | virtual uint rule() const { return divD_mem_rule; } |
| 29275 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29276 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29277 | virtual uint two_adr() const { return oper_input_base(); } |
| 29278 | virtual int reloc() const; |
| 29279 | virtual uint oper_input_base() const { return 2; } |
| 29280 | public: |
| 29281 | divD_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29282 | virtual uint size_of() const { return sizeof(divD_memNode); } |
| 29283 | static const Pipeline *pipeline_class(); |
| 29284 | virtual const Pipeline *pipeline() const; |
| 29285 | virtual const MachOper *memory_operand() const; |
| 29286 | #ifndef PRODUCT |
| 29287 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29288 | virtual const char *Name() const { return "divD_mem";} |
| 29289 | #endif |
| 29290 | }; |
| 29291 | |
| 29292 | class divD_immNode : public MachConstantNode { |
| 29293 | private: |
| 29294 | MachOper *_opnd_array[3]; |
| 29295 | public: |
| 29296 | MachOper *opnd_array(uint operand_index) const { |
| 29297 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29298 | return _opnd_array[operand_index]; |
| 29299 | } |
| 29300 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29301 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29302 | _opnd_array[operand_index] = operand; |
| 29303 | } |
| 29304 | private: |
| 29305 | virtual const RegMask &out_RegMask() const; |
| 29306 | virtual uint rule() const { return divD_imm_rule; } |
| 29307 | virtual void eval_constant(Compile* C); |
| 29308 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29309 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29310 | virtual uint two_adr() const { return oper_input_base(); } |
| 29311 | virtual int reloc() const; |
| 29312 | virtual uint oper_input_base() const { return 1; } |
| 29313 | public: |
| 29314 | divD_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 29315 | virtual uint size_of() const { return sizeof(divD_immNode); } |
| 29316 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29317 | static const Pipeline *pipeline_class(); |
| 29318 | virtual const Pipeline *pipeline() const; |
| 29319 | #ifndef PRODUCT |
| 29320 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29321 | virtual const char *Name() const { return "divD_imm";} |
| 29322 | #endif |
| 29323 | }; |
| 29324 | |
| 29325 | class divD_reg_regNode : public MachNode { |
| 29326 | private: |
| 29327 | MachOper *_opnd_array[3]; |
| 29328 | public: |
| 29329 | MachOper *opnd_array(uint operand_index) const { |
| 29330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29331 | return _opnd_array[operand_index]; |
| 29332 | } |
| 29333 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29334 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29335 | _opnd_array[operand_index] = operand; |
| 29336 | } |
| 29337 | private: |
| 29338 | const RegMask *_cisc_RegMask; |
| 29339 | virtual const RegMask &out_RegMask() const; |
| 29340 | virtual uint rule() const { return divD_reg_reg_rule; } |
| 29341 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29342 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29343 | virtual int cisc_operand() const { return 2; } |
| 29344 | virtual MachNode *cisc_version(int offset); |
| 29345 | virtual void use_cisc_RegMask(); |
| 29346 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29347 | public: |
| 29348 | divD_reg_regNode() { _cisc_RegMask = NULL; _num_opnds = 3; _opnds = _opnd_array; } |
| 29349 | virtual uint size_of() const { return sizeof(divD_reg_regNode); } |
| 29350 | static const Pipeline *pipeline_class(); |
| 29351 | virtual const Pipeline *pipeline() const; |
| 29352 | #ifndef PRODUCT |
| 29353 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29354 | virtual const char *Name() const { return "divD_reg_reg";} |
| 29355 | #endif |
| 29356 | }; |
| 29357 | |
| 29358 | class divD_reg_memNode : public MachNode { |
| 29359 | private: |
| 29360 | MachOper *_opnd_array[3]; |
| 29361 | public: |
| 29362 | MachOper *opnd_array(uint operand_index) const { |
| 29363 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29364 | return _opnd_array[operand_index]; |
| 29365 | } |
| 29366 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29367 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29368 | _opnd_array[operand_index] = operand; |
| 29369 | } |
| 29370 | private: |
| 29371 | virtual const RegMask &out_RegMask() const; |
| 29372 | virtual uint rule() const { return divD_reg_mem_rule; } |
| 29373 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29374 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29375 | virtual int reloc() const; |
| 29376 | virtual uint oper_input_base() const { return 2; } |
| 29377 | public: |
| 29378 | divD_reg_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29379 | virtual uint size_of() const { return sizeof(divD_reg_memNode); } |
| 29380 | static const Pipeline *pipeline_class(); |
| 29381 | virtual const Pipeline *pipeline() const; |
| 29382 | virtual const MachOper *memory_operand() const; |
| 29383 | #ifndef PRODUCT |
| 29384 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29385 | virtual const char *Name() const { return "divD_reg_mem";} |
| 29386 | #endif |
| 29387 | }; |
| 29388 | |
| 29389 | class divD_reg_immNode : public MachConstantNode { |
| 29390 | private: |
| 29391 | MachOper *_opnd_array[3]; |
| 29392 | public: |
| 29393 | MachOper *opnd_array(uint operand_index) const { |
| 29394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29395 | return _opnd_array[operand_index]; |
| 29396 | } |
| 29397 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29399 | _opnd_array[operand_index] = operand; |
| 29400 | } |
| 29401 | private: |
| 29402 | virtual const RegMask &out_RegMask() const; |
| 29403 | virtual uint rule() const { return divD_reg_imm_rule; } |
| 29404 | virtual void eval_constant(Compile* C); |
| 29405 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29406 | virtual int ideal_Opcode() const { return Op_DivD; } |
| 29407 | virtual int reloc() const; |
| 29408 | virtual uint oper_input_base() const { return 1; } |
| 29409 | public: |
| 29410 | divD_reg_immNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 29411 | virtual uint size_of() const { return sizeof(divD_reg_immNode); } |
| 29412 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29413 | static const Pipeline *pipeline_class(); |
| 29414 | virtual const Pipeline *pipeline() const; |
| 29415 | #ifndef PRODUCT |
| 29416 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29417 | virtual const char *Name() const { return "divD_reg_imm";} |
| 29418 | #endif |
| 29419 | }; |
| 29420 | |
| 29421 | class absF_regNode : public MachNode { |
| 29422 | private: |
| 29423 | MachOper *_opnd_array[2]; |
| 29424 | public: |
| 29425 | MachOper *opnd_array(uint operand_index) const { |
| 29426 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29427 | return _opnd_array[operand_index]; |
| 29428 | } |
| 29429 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29430 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29431 | _opnd_array[operand_index] = operand; |
| 29432 | } |
| 29433 | private: |
| 29434 | virtual const RegMask &out_RegMask() const; |
| 29435 | virtual uint rule() const { return absF_reg_rule; } |
| 29436 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29437 | virtual int ideal_Opcode() const { return Op_AbsF; } |
| 29438 | virtual uint two_adr() const { return oper_input_base(); } |
| 29439 | public: |
| 29440 | absF_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29441 | virtual uint size_of() const { return sizeof(absF_regNode); } |
| 29442 | // Rematerialize absF_reg |
| 29443 | static const Pipeline *pipeline_class(); |
| 29444 | virtual const Pipeline *pipeline() const; |
| 29445 | #ifndef PRODUCT |
| 29446 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29447 | virtual const char *Name() const { return "absF_reg";} |
| 29448 | #endif |
| 29449 | }; |
| 29450 | |
| 29451 | class absF_reg_regNode : public MachNode { |
| 29452 | private: |
| 29453 | MachOper *_opnd_array[2]; |
| 29454 | public: |
| 29455 | MachOper *opnd_array(uint operand_index) const { |
| 29456 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29457 | return _opnd_array[operand_index]; |
| 29458 | } |
| 29459 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29460 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29461 | _opnd_array[operand_index] = operand; |
| 29462 | } |
| 29463 | private: |
| 29464 | virtual const RegMask &out_RegMask() const; |
| 29465 | virtual uint rule() const { return absF_reg_reg_rule; } |
| 29466 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29467 | virtual int ideal_Opcode() const { return Op_AbsF; } |
| 29468 | public: |
| 29469 | absF_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29470 | virtual uint size_of() const { return sizeof(absF_reg_regNode); } |
| 29471 | // Rematerialize absF_reg_reg |
| 29472 | static const Pipeline *pipeline_class(); |
| 29473 | virtual const Pipeline *pipeline() const; |
| 29474 | #ifndef PRODUCT |
| 29475 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29476 | virtual const char *Name() const { return "absF_reg_reg";} |
| 29477 | #endif |
| 29478 | }; |
| 29479 | |
| 29480 | class absD_regNode : public MachNode { |
| 29481 | private: |
| 29482 | MachOper *_opnd_array[2]; |
| 29483 | public: |
| 29484 | MachOper *opnd_array(uint operand_index) const { |
| 29485 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29486 | return _opnd_array[operand_index]; |
| 29487 | } |
| 29488 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29489 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29490 | _opnd_array[operand_index] = operand; |
| 29491 | } |
| 29492 | private: |
| 29493 | virtual const RegMask &out_RegMask() const; |
| 29494 | virtual uint rule() const { return absD_reg_rule; } |
| 29495 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29496 | virtual int ideal_Opcode() const { return Op_AbsD; } |
| 29497 | virtual uint two_adr() const { return oper_input_base(); } |
| 29498 | public: |
| 29499 | absD_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29500 | virtual uint size_of() const { return sizeof(absD_regNode); } |
| 29501 | // Rematerialize absD_reg |
| 29502 | static const Pipeline *pipeline_class(); |
| 29503 | virtual const Pipeline *pipeline() const; |
| 29504 | #ifndef PRODUCT |
| 29505 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29506 | virtual const char *Name() const { return "absD_reg";} |
| 29507 | #endif |
| 29508 | }; |
| 29509 | |
| 29510 | class absD_reg_regNode : public MachNode { |
| 29511 | private: |
| 29512 | MachOper *_opnd_array[2]; |
| 29513 | public: |
| 29514 | MachOper *opnd_array(uint operand_index) const { |
| 29515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29516 | return _opnd_array[operand_index]; |
| 29517 | } |
| 29518 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29519 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29520 | _opnd_array[operand_index] = operand; |
| 29521 | } |
| 29522 | private: |
| 29523 | virtual const RegMask &out_RegMask() const; |
| 29524 | virtual uint rule() const { return absD_reg_reg_rule; } |
| 29525 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29526 | virtual int ideal_Opcode() const { return Op_AbsD; } |
| 29527 | public: |
| 29528 | absD_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29529 | virtual uint size_of() const { return sizeof(absD_reg_regNode); } |
| 29530 | // Rematerialize absD_reg_reg |
| 29531 | static const Pipeline *pipeline_class(); |
| 29532 | virtual const Pipeline *pipeline() const; |
| 29533 | #ifndef PRODUCT |
| 29534 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29535 | virtual const char *Name() const { return "absD_reg_reg";} |
| 29536 | #endif |
| 29537 | }; |
| 29538 | |
| 29539 | class negF_regNode : public MachNode { |
| 29540 | private: |
| 29541 | MachOper *_opnd_array[2]; |
| 29542 | public: |
| 29543 | MachOper *opnd_array(uint operand_index) const { |
| 29544 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29545 | return _opnd_array[operand_index]; |
| 29546 | } |
| 29547 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29548 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29549 | _opnd_array[operand_index] = operand; |
| 29550 | } |
| 29551 | private: |
| 29552 | virtual const RegMask &out_RegMask() const; |
| 29553 | virtual uint rule() const { return negF_reg_rule; } |
| 29554 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29555 | virtual int ideal_Opcode() const { return Op_NegF; } |
| 29556 | virtual uint two_adr() const { return oper_input_base(); } |
| 29557 | public: |
| 29558 | negF_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29559 | virtual uint size_of() const { return sizeof(negF_regNode); } |
| 29560 | // Rematerialize negF_reg |
| 29561 | static const Pipeline *pipeline_class(); |
| 29562 | virtual const Pipeline *pipeline() const; |
| 29563 | #ifndef PRODUCT |
| 29564 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29565 | virtual const char *Name() const { return "negF_reg";} |
| 29566 | #endif |
| 29567 | }; |
| 29568 | |
| 29569 | class negF_reg_regNode : public MachNode { |
| 29570 | private: |
| 29571 | MachOper *_opnd_array[2]; |
| 29572 | public: |
| 29573 | MachOper *opnd_array(uint operand_index) const { |
| 29574 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29575 | return _opnd_array[operand_index]; |
| 29576 | } |
| 29577 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29578 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29579 | _opnd_array[operand_index] = operand; |
| 29580 | } |
| 29581 | private: |
| 29582 | virtual const RegMask &out_RegMask() const; |
| 29583 | virtual uint rule() const { return negF_reg_reg_rule; } |
| 29584 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29585 | virtual int ideal_Opcode() const { return Op_NegF; } |
| 29586 | public: |
| 29587 | negF_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29588 | virtual uint size_of() const { return sizeof(negF_reg_regNode); } |
| 29589 | // Rematerialize negF_reg_reg |
| 29590 | static const Pipeline *pipeline_class(); |
| 29591 | virtual const Pipeline *pipeline() const; |
| 29592 | #ifndef PRODUCT |
| 29593 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29594 | virtual const char *Name() const { return "negF_reg_reg";} |
| 29595 | #endif |
| 29596 | }; |
| 29597 | |
| 29598 | class negD_regNode : public MachNode { |
| 29599 | private: |
| 29600 | MachOper *_opnd_array[2]; |
| 29601 | public: |
| 29602 | MachOper *opnd_array(uint operand_index) const { |
| 29603 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29604 | return _opnd_array[operand_index]; |
| 29605 | } |
| 29606 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29607 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29608 | _opnd_array[operand_index] = operand; |
| 29609 | } |
| 29610 | private: |
| 29611 | virtual const RegMask &out_RegMask() const; |
| 29612 | virtual uint rule() const { return negD_reg_rule; } |
| 29613 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29614 | virtual int ideal_Opcode() const { return Op_NegD; } |
| 29615 | virtual uint two_adr() const { return oper_input_base(); } |
| 29616 | public: |
| 29617 | negD_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29618 | virtual uint size_of() const { return sizeof(negD_regNode); } |
| 29619 | // Rematerialize negD_reg |
| 29620 | static const Pipeline *pipeline_class(); |
| 29621 | virtual const Pipeline *pipeline() const; |
| 29622 | #ifndef PRODUCT |
| 29623 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29624 | virtual const char *Name() const { return "negD_reg";} |
| 29625 | #endif |
| 29626 | }; |
| 29627 | |
| 29628 | class negD_reg_regNode : public MachNode { |
| 29629 | private: |
| 29630 | MachOper *_opnd_array[2]; |
| 29631 | public: |
| 29632 | MachOper *opnd_array(uint operand_index) const { |
| 29633 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29634 | return _opnd_array[operand_index]; |
| 29635 | } |
| 29636 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29637 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29638 | _opnd_array[operand_index] = operand; |
| 29639 | } |
| 29640 | private: |
| 29641 | virtual const RegMask &out_RegMask() const; |
| 29642 | virtual uint rule() const { return negD_reg_reg_rule; } |
| 29643 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29644 | virtual int ideal_Opcode() const { return Op_NegD; } |
| 29645 | public: |
| 29646 | negD_reg_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29647 | virtual uint size_of() const { return sizeof(negD_reg_regNode); } |
| 29648 | // Rematerialize negD_reg_reg |
| 29649 | static const Pipeline *pipeline_class(); |
| 29650 | virtual const Pipeline *pipeline() const; |
| 29651 | #ifndef PRODUCT |
| 29652 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29653 | virtual const char *Name() const { return "negD_reg_reg";} |
| 29654 | #endif |
| 29655 | }; |
| 29656 | |
| 29657 | class sqrtF_regNode : public MachNode { |
| 29658 | private: |
| 29659 | MachOper *_opnd_array[2]; |
| 29660 | public: |
| 29661 | MachOper *opnd_array(uint operand_index) const { |
| 29662 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29663 | return _opnd_array[operand_index]; |
| 29664 | } |
| 29665 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29666 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29667 | _opnd_array[operand_index] = operand; |
| 29668 | } |
| 29669 | private: |
| 29670 | const RegMask *_cisc_RegMask; |
| 29671 | virtual const RegMask &out_RegMask() const; |
| 29672 | virtual uint rule() const { return sqrtF_reg_rule; } |
| 29673 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29674 | virtual int ideal_Opcode() const { return Op_SqrtF; } |
| 29675 | virtual int cisc_operand() const { return 1; } |
| 29676 | virtual MachNode *cisc_version(int offset); |
| 29677 | virtual void use_cisc_RegMask(); |
| 29678 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29679 | public: |
| 29680 | sqrtF_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 29681 | virtual uint size_of() const { return sizeof(sqrtF_regNode); } |
| 29682 | static const Pipeline *pipeline_class(); |
| 29683 | virtual const Pipeline *pipeline() const; |
| 29684 | #ifndef PRODUCT |
| 29685 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29686 | virtual const char *Name() const { return "sqrtF_reg";} |
| 29687 | #endif |
| 29688 | }; |
| 29689 | |
| 29690 | class sqrtF_memNode : public MachNode { |
| 29691 | private: |
| 29692 | MachOper *_opnd_array[2]; |
| 29693 | public: |
| 29694 | MachOper *opnd_array(uint operand_index) const { |
| 29695 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29696 | return _opnd_array[operand_index]; |
| 29697 | } |
| 29698 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29699 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29700 | _opnd_array[operand_index] = operand; |
| 29701 | } |
| 29702 | private: |
| 29703 | virtual const RegMask &out_RegMask() const; |
| 29704 | virtual uint rule() const { return sqrtF_mem_rule; } |
| 29705 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29706 | virtual int ideal_Opcode() const { return Op_SqrtF; } |
| 29707 | virtual int reloc() const; |
| 29708 | virtual uint oper_input_base() const { return 2; } |
| 29709 | public: |
| 29710 | sqrtF_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29711 | virtual uint size_of() const { return sizeof(sqrtF_memNode); } |
| 29712 | static const Pipeline *pipeline_class(); |
| 29713 | virtual const Pipeline *pipeline() const; |
| 29714 | virtual const MachOper *memory_operand() const; |
| 29715 | #ifndef PRODUCT |
| 29716 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29717 | virtual const char *Name() const { return "sqrtF_mem";} |
| 29718 | #endif |
| 29719 | }; |
| 29720 | |
| 29721 | class sqrtF_immNode : public MachConstantNode { |
| 29722 | private: |
| 29723 | MachOper *_opnd_array[2]; |
| 29724 | public: |
| 29725 | MachOper *opnd_array(uint operand_index) const { |
| 29726 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29727 | return _opnd_array[operand_index]; |
| 29728 | } |
| 29729 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29730 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29731 | _opnd_array[operand_index] = operand; |
| 29732 | } |
| 29733 | private: |
| 29734 | virtual const RegMask &out_RegMask() const; |
| 29735 | virtual uint rule() const { return sqrtF_imm_rule; } |
| 29736 | virtual void eval_constant(Compile* C); |
| 29737 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29738 | virtual int ideal_Opcode() const { return Op_SqrtF; } |
| 29739 | virtual int reloc() const; |
| 29740 | virtual uint oper_input_base() const { return 1; } |
| 29741 | public: |
| 29742 | sqrtF_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29743 | virtual uint size_of() const { return sizeof(sqrtF_immNode); } |
| 29744 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29745 | static const Pipeline *pipeline_class(); |
| 29746 | virtual const Pipeline *pipeline() const; |
| 29747 | #ifndef PRODUCT |
| 29748 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29749 | virtual const char *Name() const { return "sqrtF_imm";} |
| 29750 | #endif |
| 29751 | }; |
| 29752 | |
| 29753 | class sqrtD_regNode : public MachNode { |
| 29754 | private: |
| 29755 | MachOper *_opnd_array[2]; |
| 29756 | public: |
| 29757 | MachOper *opnd_array(uint operand_index) const { |
| 29758 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29759 | return _opnd_array[operand_index]; |
| 29760 | } |
| 29761 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29762 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29763 | _opnd_array[operand_index] = operand; |
| 29764 | } |
| 29765 | private: |
| 29766 | const RegMask *_cisc_RegMask; |
| 29767 | virtual const RegMask &out_RegMask() const; |
| 29768 | virtual uint rule() const { return sqrtD_reg_rule; } |
| 29769 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29770 | virtual int ideal_Opcode() const { return Op_SqrtD; } |
| 29771 | virtual int cisc_operand() const { return 1; } |
| 29772 | virtual MachNode *cisc_version(int offset); |
| 29773 | virtual void use_cisc_RegMask(); |
| 29774 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 29775 | public: |
| 29776 | sqrtD_regNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 29777 | virtual uint size_of() const { return sizeof(sqrtD_regNode); } |
| 29778 | static const Pipeline *pipeline_class(); |
| 29779 | virtual const Pipeline *pipeline() const; |
| 29780 | #ifndef PRODUCT |
| 29781 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29782 | virtual const char *Name() const { return "sqrtD_reg";} |
| 29783 | #endif |
| 29784 | }; |
| 29785 | |
| 29786 | class sqrtD_memNode : public MachNode { |
| 29787 | private: |
| 29788 | MachOper *_opnd_array[2]; |
| 29789 | public: |
| 29790 | MachOper *opnd_array(uint operand_index) const { |
| 29791 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29792 | return _opnd_array[operand_index]; |
| 29793 | } |
| 29794 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29795 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29796 | _opnd_array[operand_index] = operand; |
| 29797 | } |
| 29798 | private: |
| 29799 | virtual const RegMask &out_RegMask() const; |
| 29800 | virtual uint rule() const { return sqrtD_mem_rule; } |
| 29801 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29802 | virtual int ideal_Opcode() const { return Op_SqrtD; } |
| 29803 | virtual int reloc() const; |
| 29804 | virtual uint oper_input_base() const { return 2; } |
| 29805 | public: |
| 29806 | sqrtD_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 29807 | virtual uint size_of() const { return sizeof(sqrtD_memNode); } |
| 29808 | static const Pipeline *pipeline_class(); |
| 29809 | virtual const Pipeline *pipeline() const; |
| 29810 | virtual const MachOper *memory_operand() const; |
| 29811 | #ifndef PRODUCT |
| 29812 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29813 | virtual const char *Name() const { return "sqrtD_mem";} |
| 29814 | #endif |
| 29815 | }; |
| 29816 | |
| 29817 | class sqrtD_immNode : public MachConstantNode { |
| 29818 | private: |
| 29819 | MachOper *_opnd_array[2]; |
| 29820 | public: |
| 29821 | MachOper *opnd_array(uint operand_index) const { |
| 29822 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29823 | return _opnd_array[operand_index]; |
| 29824 | } |
| 29825 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29826 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29827 | _opnd_array[operand_index] = operand; |
| 29828 | } |
| 29829 | private: |
| 29830 | virtual const RegMask &out_RegMask() const; |
| 29831 | virtual uint rule() const { return sqrtD_imm_rule; } |
| 29832 | virtual void eval_constant(Compile* C); |
| 29833 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29834 | virtual int ideal_Opcode() const { return Op_SqrtD; } |
| 29835 | virtual int reloc() const; |
| 29836 | virtual uint oper_input_base() const { return 1; } |
| 29837 | public: |
| 29838 | sqrtD_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29839 | virtual uint size_of() const { return sizeof(sqrtD_immNode); } |
| 29840 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 29841 | static const Pipeline *pipeline_class(); |
| 29842 | virtual const Pipeline *pipeline() const; |
| 29843 | #ifndef PRODUCT |
| 29844 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29845 | virtual const char *Name() const { return "sqrtD_imm";} |
| 29846 | #endif |
| 29847 | }; |
| 29848 | |
| 29849 | class onspinwaitNode : public MachMemBarNode { |
| 29850 | private: |
| 29851 | MachOper *_opnd_array[1]; |
| 29852 | public: |
| 29853 | MachOper *opnd_array(uint operand_index) const { |
| 29854 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29855 | return _opnd_array[operand_index]; |
| 29856 | } |
| 29857 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29858 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29859 | _opnd_array[operand_index] = operand; |
| 29860 | } |
| 29861 | private: |
| 29862 | virtual const RegMask &out_RegMask() const; |
| 29863 | virtual uint rule() const { return onspinwait_rule; } |
| 29864 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29865 | virtual int ideal_Opcode() const { return Op_OnSpinWait; } |
| 29866 | virtual uint oper_input_base() const { return 1; } |
| 29867 | public: |
| 29868 | onspinwaitNode() { _num_opnds = 1; _opnds = _opnd_array; } |
| 29869 | virtual uint size_of() const { return sizeof(onspinwaitNode); } |
| 29870 | static const Pipeline *pipeline_class(); |
| 29871 | virtual const Pipeline *pipeline() const; |
| 29872 | const Type *bottom_type() const { return TypeTuple::MEMBAR; } // matched MemBar |
| 29873 | #ifndef PRODUCT |
| 29874 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29875 | virtual const char *Name() const { return "onspinwait";} |
| 29876 | #endif |
| 29877 | }; |
| 29878 | |
| 29879 | class fmaD_regNode : public MachNode { |
| 29880 | private: |
| 29881 | MachOper *_opnd_array[4]; |
| 29882 | public: |
| 29883 | MachOper *opnd_array(uint operand_index) const { |
| 29884 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29885 | return _opnd_array[operand_index]; |
| 29886 | } |
| 29887 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29889 | _opnd_array[operand_index] = operand; |
| 29890 | } |
| 29891 | private: |
| 29892 | virtual const RegMask &out_RegMask() const; |
| 29893 | virtual uint rule() const { return fmaD_reg_rule; } |
| 29894 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29895 | virtual int ideal_Opcode() const { return Op_FmaD; } |
| 29896 | virtual uint two_adr() const { return oper_input_base(); } |
| 29897 | public: |
| 29898 | fmaD_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 29899 | virtual uint size_of() const { return sizeof(fmaD_regNode); } |
| 29900 | static const Pipeline *pipeline_class(); |
| 29901 | virtual const Pipeline *pipeline() const; |
| 29902 | #ifndef PRODUCT |
| 29903 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29904 | virtual const char *Name() const { return "fmaD_reg";} |
| 29905 | #endif |
| 29906 | }; |
| 29907 | |
| 29908 | class fmaF_regNode : public MachNode { |
| 29909 | private: |
| 29910 | MachOper *_opnd_array[4]; |
| 29911 | public: |
| 29912 | MachOper *opnd_array(uint operand_index) const { |
| 29913 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29914 | return _opnd_array[operand_index]; |
| 29915 | } |
| 29916 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29917 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29918 | _opnd_array[operand_index] = operand; |
| 29919 | } |
| 29920 | private: |
| 29921 | virtual const RegMask &out_RegMask() const; |
| 29922 | virtual uint rule() const { return fmaF_reg_rule; } |
| 29923 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29924 | virtual int ideal_Opcode() const { return Op_FmaF; } |
| 29925 | virtual uint two_adr() const { return oper_input_base(); } |
| 29926 | public: |
| 29927 | fmaF_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 29928 | virtual uint size_of() const { return sizeof(fmaF_regNode); } |
| 29929 | static const Pipeline *pipeline_class(); |
| 29930 | virtual const Pipeline *pipeline() const; |
| 29931 | #ifndef PRODUCT |
| 29932 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29933 | virtual const char *Name() const { return "fmaF_reg";} |
| 29934 | #endif |
| 29935 | }; |
| 29936 | |
| 29937 | class loadV4Node : public MachTypeNode { |
| 29938 | private: |
| 29939 | MachOper *_opnd_array[2]; |
| 29940 | public: |
| 29941 | MachOper *opnd_array(uint operand_index) const { |
| 29942 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29943 | return _opnd_array[operand_index]; |
| 29944 | } |
| 29945 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29946 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29947 | _opnd_array[operand_index] = operand; |
| 29948 | } |
| 29949 | private: |
| 29950 | virtual const RegMask &out_RegMask() const; |
| 29951 | virtual uint rule() const { return loadV4_rule; } |
| 29952 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29953 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 29954 | virtual int reloc() const; |
| 29955 | virtual uint oper_input_base() const { return 2; } |
| 29956 | public: |
| 29957 | loadV4Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 29958 | virtual uint size_of() const { return sizeof(loadV4Node); } |
| 29959 | static const Pipeline *pipeline_class(); |
| 29960 | virtual const Pipeline *pipeline() const; |
| 29961 | virtual const MachOper *memory_operand() const; |
| 29962 | #ifndef PRODUCT |
| 29963 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29964 | virtual const char *Name() const { return "loadV4";} |
| 29965 | #endif |
| 29966 | }; |
| 29967 | |
| 29968 | class MoveVecS2LegNode : public MachNode { |
| 29969 | private: |
| 29970 | MachOper *_opnd_array[2]; |
| 29971 | public: |
| 29972 | MachOper *opnd_array(uint operand_index) const { |
| 29973 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29974 | return _opnd_array[operand_index]; |
| 29975 | } |
| 29976 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 29977 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 29978 | _opnd_array[operand_index] = operand; |
| 29979 | } |
| 29980 | private: |
| 29981 | virtual const RegMask &out_RegMask() const; |
| 29982 | virtual uint rule() const { return MoveVecS2Leg_rule; } |
| 29983 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 29984 | virtual int ideal_Opcode() const { return Op_VecS; } |
| 29985 | public: |
| 29986 | MoveVecS2LegNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 29987 | virtual uint size_of() const { return sizeof(MoveVecS2LegNode); } |
| 29988 | // Rematerialize MoveVecS2Leg |
| 29989 | static const Pipeline *pipeline_class(); |
| 29990 | virtual const Pipeline *pipeline() const; |
| 29991 | #ifndef PRODUCT |
| 29992 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 29993 | virtual const char *Name() const { return "MoveVecS2Leg";} |
| 29994 | #endif |
| 29995 | }; |
| 29996 | |
| 29997 | class MoveLeg2VecSNode : public MachNode { |
| 29998 | private: |
| 29999 | MachOper *_opnd_array[2]; |
| 30000 | public: |
| 30001 | MachOper *opnd_array(uint operand_index) const { |
| 30002 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30003 | return _opnd_array[operand_index]; |
| 30004 | } |
| 30005 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30006 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30007 | _opnd_array[operand_index] = operand; |
| 30008 | } |
| 30009 | private: |
| 30010 | virtual const RegMask &out_RegMask() const; |
| 30011 | virtual uint rule() const { return MoveLeg2VecS_rule; } |
| 30012 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30013 | virtual int ideal_Opcode() const { return Op_VecS; } |
| 30014 | public: |
| 30015 | MoveLeg2VecSNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30016 | virtual uint size_of() const { return sizeof(MoveLeg2VecSNode); } |
| 30017 | // Rematerialize MoveLeg2VecS |
| 30018 | static const Pipeline *pipeline_class(); |
| 30019 | virtual const Pipeline *pipeline() const; |
| 30020 | #ifndef PRODUCT |
| 30021 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30022 | virtual const char *Name() const { return "MoveLeg2VecS";} |
| 30023 | #endif |
| 30024 | }; |
| 30025 | |
| 30026 | class loadV8Node : public MachTypeNode { |
| 30027 | private: |
| 30028 | MachOper *_opnd_array[2]; |
| 30029 | public: |
| 30030 | MachOper *opnd_array(uint operand_index) const { |
| 30031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30032 | return _opnd_array[operand_index]; |
| 30033 | } |
| 30034 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30036 | _opnd_array[operand_index] = operand; |
| 30037 | } |
| 30038 | private: |
| 30039 | virtual const RegMask &out_RegMask() const; |
| 30040 | virtual uint rule() const { return loadV8_rule; } |
| 30041 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30042 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 30043 | virtual int reloc() const; |
| 30044 | virtual uint oper_input_base() const { return 2; } |
| 30045 | public: |
| 30046 | loadV8Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30047 | virtual uint size_of() const { return sizeof(loadV8Node); } |
| 30048 | static const Pipeline *pipeline_class(); |
| 30049 | virtual const Pipeline *pipeline() const; |
| 30050 | virtual const MachOper *memory_operand() const; |
| 30051 | #ifndef PRODUCT |
| 30052 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30053 | virtual const char *Name() const { return "loadV8";} |
| 30054 | #endif |
| 30055 | }; |
| 30056 | |
| 30057 | class MoveVecD2LegNode : public MachNode { |
| 30058 | private: |
| 30059 | MachOper *_opnd_array[2]; |
| 30060 | public: |
| 30061 | MachOper *opnd_array(uint operand_index) const { |
| 30062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30063 | return _opnd_array[operand_index]; |
| 30064 | } |
| 30065 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30066 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30067 | _opnd_array[operand_index] = operand; |
| 30068 | } |
| 30069 | private: |
| 30070 | virtual const RegMask &out_RegMask() const; |
| 30071 | virtual uint rule() const { return MoveVecD2Leg_rule; } |
| 30072 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30073 | virtual int ideal_Opcode() const { return Op_VecD; } |
| 30074 | public: |
| 30075 | MoveVecD2LegNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30076 | virtual uint size_of() const { return sizeof(MoveVecD2LegNode); } |
| 30077 | // Rematerialize MoveVecD2Leg |
| 30078 | static const Pipeline *pipeline_class(); |
| 30079 | virtual const Pipeline *pipeline() const; |
| 30080 | #ifndef PRODUCT |
| 30081 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30082 | virtual const char *Name() const { return "MoveVecD2Leg";} |
| 30083 | #endif |
| 30084 | }; |
| 30085 | |
| 30086 | class MoveLeg2VecDNode : public MachNode { |
| 30087 | private: |
| 30088 | MachOper *_opnd_array[2]; |
| 30089 | public: |
| 30090 | MachOper *opnd_array(uint operand_index) const { |
| 30091 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30092 | return _opnd_array[operand_index]; |
| 30093 | } |
| 30094 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30095 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30096 | _opnd_array[operand_index] = operand; |
| 30097 | } |
| 30098 | private: |
| 30099 | virtual const RegMask &out_RegMask() const; |
| 30100 | virtual uint rule() const { return MoveLeg2VecD_rule; } |
| 30101 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30102 | virtual int ideal_Opcode() const { return Op_VecD; } |
| 30103 | public: |
| 30104 | MoveLeg2VecDNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30105 | virtual uint size_of() const { return sizeof(MoveLeg2VecDNode); } |
| 30106 | // Rematerialize MoveLeg2VecD |
| 30107 | static const Pipeline *pipeline_class(); |
| 30108 | virtual const Pipeline *pipeline() const; |
| 30109 | #ifndef PRODUCT |
| 30110 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30111 | virtual const char *Name() const { return "MoveLeg2VecD";} |
| 30112 | #endif |
| 30113 | }; |
| 30114 | |
| 30115 | class loadV16Node : public MachTypeNode { |
| 30116 | private: |
| 30117 | MachOper *_opnd_array[2]; |
| 30118 | public: |
| 30119 | MachOper *opnd_array(uint operand_index) const { |
| 30120 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30121 | return _opnd_array[operand_index]; |
| 30122 | } |
| 30123 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30124 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30125 | _opnd_array[operand_index] = operand; |
| 30126 | } |
| 30127 | private: |
| 30128 | virtual const RegMask &out_RegMask() const; |
| 30129 | virtual uint rule() const { return loadV16_rule; } |
| 30130 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30131 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 30132 | virtual int reloc() const; |
| 30133 | virtual uint oper_input_base() const { return 2; } |
| 30134 | public: |
| 30135 | loadV16Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30136 | virtual uint size_of() const { return sizeof(loadV16Node); } |
| 30137 | static const Pipeline *pipeline_class(); |
| 30138 | virtual const Pipeline *pipeline() const; |
| 30139 | virtual const MachOper *memory_operand() const; |
| 30140 | #ifndef PRODUCT |
| 30141 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30142 | virtual const char *Name() const { return "loadV16";} |
| 30143 | #endif |
| 30144 | }; |
| 30145 | |
| 30146 | class MoveVecX2LegNode : public MachNode { |
| 30147 | private: |
| 30148 | MachOper *_opnd_array[2]; |
| 30149 | public: |
| 30150 | MachOper *opnd_array(uint operand_index) const { |
| 30151 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30152 | return _opnd_array[operand_index]; |
| 30153 | } |
| 30154 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30155 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30156 | _opnd_array[operand_index] = operand; |
| 30157 | } |
| 30158 | private: |
| 30159 | virtual const RegMask &out_RegMask() const; |
| 30160 | virtual uint rule() const { return MoveVecX2Leg_rule; } |
| 30161 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30162 | virtual int ideal_Opcode() const { return Op_VecX; } |
| 30163 | public: |
| 30164 | MoveVecX2LegNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30165 | virtual uint size_of() const { return sizeof(MoveVecX2LegNode); } |
| 30166 | // Rematerialize MoveVecX2Leg |
| 30167 | static const Pipeline *pipeline_class(); |
| 30168 | virtual const Pipeline *pipeline() const; |
| 30169 | #ifndef PRODUCT |
| 30170 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30171 | virtual const char *Name() const { return "MoveVecX2Leg";} |
| 30172 | #endif |
| 30173 | }; |
| 30174 | |
| 30175 | class MoveLeg2VecXNode : public MachNode { |
| 30176 | private: |
| 30177 | MachOper *_opnd_array[2]; |
| 30178 | public: |
| 30179 | MachOper *opnd_array(uint operand_index) const { |
| 30180 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30181 | return _opnd_array[operand_index]; |
| 30182 | } |
| 30183 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30184 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30185 | _opnd_array[operand_index] = operand; |
| 30186 | } |
| 30187 | private: |
| 30188 | virtual const RegMask &out_RegMask() const; |
| 30189 | virtual uint rule() const { return MoveLeg2VecX_rule; } |
| 30190 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30191 | virtual int ideal_Opcode() const { return Op_VecX; } |
| 30192 | public: |
| 30193 | MoveLeg2VecXNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30194 | virtual uint size_of() const { return sizeof(MoveLeg2VecXNode); } |
| 30195 | // Rematerialize MoveLeg2VecX |
| 30196 | static const Pipeline *pipeline_class(); |
| 30197 | virtual const Pipeline *pipeline() const; |
| 30198 | #ifndef PRODUCT |
| 30199 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30200 | virtual const char *Name() const { return "MoveLeg2VecX";} |
| 30201 | #endif |
| 30202 | }; |
| 30203 | |
| 30204 | class loadV32Node : public MachTypeNode { |
| 30205 | private: |
| 30206 | MachOper *_opnd_array[2]; |
| 30207 | public: |
| 30208 | MachOper *opnd_array(uint operand_index) const { |
| 30209 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30210 | return _opnd_array[operand_index]; |
| 30211 | } |
| 30212 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30213 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30214 | _opnd_array[operand_index] = operand; |
| 30215 | } |
| 30216 | private: |
| 30217 | virtual const RegMask &out_RegMask() const; |
| 30218 | virtual uint rule() const { return loadV32_rule; } |
| 30219 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30220 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 30221 | virtual int reloc() const; |
| 30222 | virtual uint oper_input_base() const { return 2; } |
| 30223 | public: |
| 30224 | loadV32Node() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30225 | virtual uint size_of() const { return sizeof(loadV32Node); } |
| 30226 | static const Pipeline *pipeline_class(); |
| 30227 | virtual const Pipeline *pipeline() const; |
| 30228 | virtual const MachOper *memory_operand() const; |
| 30229 | #ifndef PRODUCT |
| 30230 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30231 | virtual const char *Name() const { return "loadV32";} |
| 30232 | #endif |
| 30233 | }; |
| 30234 | |
| 30235 | class MoveVecY2LegNode : public MachNode { |
| 30236 | private: |
| 30237 | MachOper *_opnd_array[2]; |
| 30238 | public: |
| 30239 | MachOper *opnd_array(uint operand_index) const { |
| 30240 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30241 | return _opnd_array[operand_index]; |
| 30242 | } |
| 30243 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30244 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30245 | _opnd_array[operand_index] = operand; |
| 30246 | } |
| 30247 | private: |
| 30248 | virtual const RegMask &out_RegMask() const; |
| 30249 | virtual uint rule() const { return MoveVecY2Leg_rule; } |
| 30250 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30251 | virtual int ideal_Opcode() const { return Op_VecY; } |
| 30252 | public: |
| 30253 | MoveVecY2LegNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30254 | virtual uint size_of() const { return sizeof(MoveVecY2LegNode); } |
| 30255 | // Rematerialize MoveVecY2Leg |
| 30256 | static const Pipeline *pipeline_class(); |
| 30257 | virtual const Pipeline *pipeline() const; |
| 30258 | #ifndef PRODUCT |
| 30259 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30260 | virtual const char *Name() const { return "MoveVecY2Leg";} |
| 30261 | #endif |
| 30262 | }; |
| 30263 | |
| 30264 | class MoveLeg2VecYNode : public MachNode { |
| 30265 | private: |
| 30266 | MachOper *_opnd_array[2]; |
| 30267 | public: |
| 30268 | MachOper *opnd_array(uint operand_index) const { |
| 30269 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30270 | return _opnd_array[operand_index]; |
| 30271 | } |
| 30272 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30273 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30274 | _opnd_array[operand_index] = operand; |
| 30275 | } |
| 30276 | private: |
| 30277 | virtual const RegMask &out_RegMask() const; |
| 30278 | virtual uint rule() const { return MoveLeg2VecY_rule; } |
| 30279 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30280 | virtual int ideal_Opcode() const { return Op_VecY; } |
| 30281 | public: |
| 30282 | MoveLeg2VecYNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30283 | virtual uint size_of() const { return sizeof(MoveLeg2VecYNode); } |
| 30284 | // Rematerialize MoveLeg2VecY |
| 30285 | static const Pipeline *pipeline_class(); |
| 30286 | virtual const Pipeline *pipeline() const; |
| 30287 | #ifndef PRODUCT |
| 30288 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30289 | virtual const char *Name() const { return "MoveLeg2VecY";} |
| 30290 | #endif |
| 30291 | }; |
| 30292 | |
| 30293 | class loadV64_dwordNode : public MachTypeNode { |
| 30294 | private: |
| 30295 | MachOper *_opnd_array[2]; |
| 30296 | public: |
| 30297 | MachOper *opnd_array(uint operand_index) const { |
| 30298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30299 | return _opnd_array[operand_index]; |
| 30300 | } |
| 30301 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30302 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30303 | _opnd_array[operand_index] = operand; |
| 30304 | } |
| 30305 | private: |
| 30306 | virtual const RegMask &out_RegMask() const; |
| 30307 | virtual uint rule() const { return loadV64_dword_rule; } |
| 30308 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30309 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 30310 | virtual int reloc() const; |
| 30311 | virtual uint oper_input_base() const { return 2; } |
| 30312 | public: |
| 30313 | loadV64_dwordNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30314 | virtual uint size_of() const { return sizeof(loadV64_dwordNode); } |
| 30315 | static const Pipeline *pipeline_class(); |
| 30316 | virtual const Pipeline *pipeline() const; |
| 30317 | virtual const MachOper *memory_operand() const; |
| 30318 | #ifndef PRODUCT |
| 30319 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30320 | virtual const char *Name() const { return "loadV64_dword";} |
| 30321 | #endif |
| 30322 | }; |
| 30323 | |
| 30324 | class loadV64_qwordNode : public MachTypeNode { |
| 30325 | private: |
| 30326 | MachOper *_opnd_array[2]; |
| 30327 | public: |
| 30328 | MachOper *opnd_array(uint operand_index) const { |
| 30329 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30330 | return _opnd_array[operand_index]; |
| 30331 | } |
| 30332 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30333 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30334 | _opnd_array[operand_index] = operand; |
| 30335 | } |
| 30336 | private: |
| 30337 | virtual const RegMask &out_RegMask() const; |
| 30338 | virtual uint rule() const { return loadV64_qword_rule; } |
| 30339 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30340 | virtual int ideal_Opcode() const { return Op_LoadVector; } |
| 30341 | virtual int reloc() const; |
| 30342 | virtual uint oper_input_base() const { return 2; } |
| 30343 | public: |
| 30344 | loadV64_qwordNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30345 | virtual uint size_of() const { return sizeof(loadV64_qwordNode); } |
| 30346 | static const Pipeline *pipeline_class(); |
| 30347 | virtual const Pipeline *pipeline() const; |
| 30348 | virtual const MachOper *memory_operand() const; |
| 30349 | #ifndef PRODUCT |
| 30350 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30351 | virtual const char *Name() const { return "loadV64_qword";} |
| 30352 | #endif |
| 30353 | }; |
| 30354 | |
| 30355 | class MoveVecZ2LegNode : public MachNode { |
| 30356 | private: |
| 30357 | MachOper *_opnd_array[2]; |
| 30358 | public: |
| 30359 | MachOper *opnd_array(uint operand_index) const { |
| 30360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30361 | return _opnd_array[operand_index]; |
| 30362 | } |
| 30363 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30364 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30365 | _opnd_array[operand_index] = operand; |
| 30366 | } |
| 30367 | private: |
| 30368 | virtual const RegMask &out_RegMask() const; |
| 30369 | virtual uint rule() const { return MoveVecZ2Leg_rule; } |
| 30370 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30371 | virtual int ideal_Opcode() const { return Op_VecZ; } |
| 30372 | public: |
| 30373 | MoveVecZ2LegNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30374 | virtual uint size_of() const { return sizeof(MoveVecZ2LegNode); } |
| 30375 | // Rematerialize MoveVecZ2Leg |
| 30376 | static const Pipeline *pipeline_class(); |
| 30377 | virtual const Pipeline *pipeline() const; |
| 30378 | #ifndef PRODUCT |
| 30379 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30380 | virtual const char *Name() const { return "MoveVecZ2Leg";} |
| 30381 | #endif |
| 30382 | }; |
| 30383 | |
| 30384 | class MoveLeg2VecZNode : public MachNode { |
| 30385 | private: |
| 30386 | MachOper *_opnd_array[2]; |
| 30387 | public: |
| 30388 | MachOper *opnd_array(uint operand_index) const { |
| 30389 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30390 | return _opnd_array[operand_index]; |
| 30391 | } |
| 30392 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30393 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30394 | _opnd_array[operand_index] = operand; |
| 30395 | } |
| 30396 | private: |
| 30397 | virtual const RegMask &out_RegMask() const; |
| 30398 | virtual uint rule() const { return MoveLeg2VecZ_rule; } |
| 30399 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30400 | virtual int ideal_Opcode() const { return Op_VecZ; } |
| 30401 | public: |
| 30402 | MoveLeg2VecZNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30403 | virtual uint size_of() const { return sizeof(MoveLeg2VecZNode); } |
| 30404 | // Rematerialize MoveLeg2VecZ |
| 30405 | static const Pipeline *pipeline_class(); |
| 30406 | virtual const Pipeline *pipeline() const; |
| 30407 | #ifndef PRODUCT |
| 30408 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30409 | virtual const char *Name() const { return "MoveLeg2VecZ";} |
| 30410 | #endif |
| 30411 | }; |
| 30412 | |
| 30413 | class storeV4Node : public MachTypeNode { |
| 30414 | private: |
| 30415 | MachOper *_opnd_array[3]; |
| 30416 | public: |
| 30417 | MachOper *opnd_array(uint operand_index) const { |
| 30418 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30419 | return _opnd_array[operand_index]; |
| 30420 | } |
| 30421 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30422 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30423 | _opnd_array[operand_index] = operand; |
| 30424 | } |
| 30425 | private: |
| 30426 | virtual const RegMask &out_RegMask() const; |
| 30427 | virtual uint rule() const { return storeV4_rule; } |
| 30428 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30429 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30430 | virtual int reloc() const; |
| 30431 | virtual uint oper_input_base() const { return 2; } |
| 30432 | public: |
| 30433 | storeV4Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30434 | virtual uint size_of() const { return sizeof(storeV4Node); } |
| 30435 | static const Pipeline *pipeline_class(); |
| 30436 | virtual const Pipeline *pipeline() const; |
| 30437 | virtual const MachOper *memory_operand() const; |
| 30438 | #ifndef PRODUCT |
| 30439 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30440 | virtual const char *Name() const { return "storeV4";} |
| 30441 | #endif |
| 30442 | }; |
| 30443 | |
| 30444 | class storeV8Node : public MachTypeNode { |
| 30445 | private: |
| 30446 | MachOper *_opnd_array[3]; |
| 30447 | public: |
| 30448 | MachOper *opnd_array(uint operand_index) const { |
| 30449 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30450 | return _opnd_array[operand_index]; |
| 30451 | } |
| 30452 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30453 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30454 | _opnd_array[operand_index] = operand; |
| 30455 | } |
| 30456 | private: |
| 30457 | virtual const RegMask &out_RegMask() const; |
| 30458 | virtual uint rule() const { return storeV8_rule; } |
| 30459 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30460 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30461 | virtual int reloc() const; |
| 30462 | virtual uint oper_input_base() const { return 2; } |
| 30463 | public: |
| 30464 | storeV8Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30465 | virtual uint size_of() const { return sizeof(storeV8Node); } |
| 30466 | static const Pipeline *pipeline_class(); |
| 30467 | virtual const Pipeline *pipeline() const; |
| 30468 | virtual const MachOper *memory_operand() const; |
| 30469 | #ifndef PRODUCT |
| 30470 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30471 | virtual const char *Name() const { return "storeV8";} |
| 30472 | #endif |
| 30473 | }; |
| 30474 | |
| 30475 | class storeV16Node : public MachTypeNode { |
| 30476 | private: |
| 30477 | MachOper *_opnd_array[3]; |
| 30478 | public: |
| 30479 | MachOper *opnd_array(uint operand_index) const { |
| 30480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30481 | return _opnd_array[operand_index]; |
| 30482 | } |
| 30483 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30484 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30485 | _opnd_array[operand_index] = operand; |
| 30486 | } |
| 30487 | private: |
| 30488 | virtual const RegMask &out_RegMask() const; |
| 30489 | virtual uint rule() const { return storeV16_rule; } |
| 30490 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30491 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30492 | virtual int reloc() const; |
| 30493 | virtual uint oper_input_base() const { return 2; } |
| 30494 | public: |
| 30495 | storeV16Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30496 | virtual uint size_of() const { return sizeof(storeV16Node); } |
| 30497 | static const Pipeline *pipeline_class(); |
| 30498 | virtual const Pipeline *pipeline() const; |
| 30499 | virtual const MachOper *memory_operand() const; |
| 30500 | #ifndef PRODUCT |
| 30501 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30502 | virtual const char *Name() const { return "storeV16";} |
| 30503 | #endif |
| 30504 | }; |
| 30505 | |
| 30506 | class storeV32Node : public MachTypeNode { |
| 30507 | private: |
| 30508 | MachOper *_opnd_array[3]; |
| 30509 | public: |
| 30510 | MachOper *opnd_array(uint operand_index) const { |
| 30511 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30512 | return _opnd_array[operand_index]; |
| 30513 | } |
| 30514 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30516 | _opnd_array[operand_index] = operand; |
| 30517 | } |
| 30518 | private: |
| 30519 | virtual const RegMask &out_RegMask() const; |
| 30520 | virtual uint rule() const { return storeV32_rule; } |
| 30521 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30522 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30523 | virtual int reloc() const; |
| 30524 | virtual uint oper_input_base() const { return 2; } |
| 30525 | public: |
| 30526 | storeV32Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30527 | virtual uint size_of() const { return sizeof(storeV32Node); } |
| 30528 | static const Pipeline *pipeline_class(); |
| 30529 | virtual const Pipeline *pipeline() const; |
| 30530 | virtual const MachOper *memory_operand() const; |
| 30531 | #ifndef PRODUCT |
| 30532 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30533 | virtual const char *Name() const { return "storeV32";} |
| 30534 | #endif |
| 30535 | }; |
| 30536 | |
| 30537 | class storeV64_dwordNode : public MachTypeNode { |
| 30538 | private: |
| 30539 | MachOper *_opnd_array[3]; |
| 30540 | public: |
| 30541 | MachOper *opnd_array(uint operand_index) const { |
| 30542 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30543 | return _opnd_array[operand_index]; |
| 30544 | } |
| 30545 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30546 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30547 | _opnd_array[operand_index] = operand; |
| 30548 | } |
| 30549 | private: |
| 30550 | virtual const RegMask &out_RegMask() const; |
| 30551 | virtual uint rule() const { return storeV64_dword_rule; } |
| 30552 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30553 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30554 | virtual int reloc() const; |
| 30555 | virtual uint oper_input_base() const { return 2; } |
| 30556 | public: |
| 30557 | storeV64_dwordNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30558 | virtual uint size_of() const { return sizeof(storeV64_dwordNode); } |
| 30559 | static const Pipeline *pipeline_class(); |
| 30560 | virtual const Pipeline *pipeline() const; |
| 30561 | virtual const MachOper *memory_operand() const; |
| 30562 | #ifndef PRODUCT |
| 30563 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30564 | virtual const char *Name() const { return "storeV64_dword";} |
| 30565 | #endif |
| 30566 | }; |
| 30567 | |
| 30568 | class storeV64_qwordNode : public MachTypeNode { |
| 30569 | private: |
| 30570 | MachOper *_opnd_array[3]; |
| 30571 | public: |
| 30572 | MachOper *opnd_array(uint operand_index) const { |
| 30573 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30574 | return _opnd_array[operand_index]; |
| 30575 | } |
| 30576 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30577 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30578 | _opnd_array[operand_index] = operand; |
| 30579 | } |
| 30580 | private: |
| 30581 | virtual const RegMask &out_RegMask() const; |
| 30582 | virtual uint rule() const { return storeV64_qword_rule; } |
| 30583 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30584 | virtual int ideal_Opcode() const { return Op_StoreVector; } |
| 30585 | virtual int reloc() const; |
| 30586 | virtual uint oper_input_base() const { return 2; } |
| 30587 | public: |
| 30588 | storeV64_qwordNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 30589 | virtual uint size_of() const { return sizeof(storeV64_qwordNode); } |
| 30590 | static const Pipeline *pipeline_class(); |
| 30591 | virtual const Pipeline *pipeline() const; |
| 30592 | virtual const MachOper *memory_operand() const; |
| 30593 | #ifndef PRODUCT |
| 30594 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30595 | virtual const char *Name() const { return "storeV64_qword";} |
| 30596 | #endif |
| 30597 | }; |
| 30598 | |
| 30599 | class Repl16BNode : public MachTypeNode { |
| 30600 | private: |
| 30601 | MachOper *_opnd_array[2]; |
| 30602 | public: |
| 30603 | MachOper *opnd_array(uint operand_index) const { |
| 30604 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30605 | return _opnd_array[operand_index]; |
| 30606 | } |
| 30607 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30608 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30609 | _opnd_array[operand_index] = operand; |
| 30610 | } |
| 30611 | private: |
| 30612 | virtual const RegMask &out_RegMask() const; |
| 30613 | virtual uint rule() const { return Repl16B_rule; } |
| 30614 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30615 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30616 | virtual uint oper_input_base() const { return 1; } |
| 30617 | public: |
| 30618 | Repl16BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30619 | virtual uint size_of() const { return sizeof(Repl16BNode); } |
| 30620 | static const Pipeline *pipeline_class(); |
| 30621 | virtual const Pipeline *pipeline() const; |
| 30622 | #ifndef PRODUCT |
| 30623 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30624 | virtual const char *Name() const { return "Repl16B";} |
| 30625 | #endif |
| 30626 | }; |
| 30627 | |
| 30628 | class Repl32BNode : public MachTypeNode { |
| 30629 | private: |
| 30630 | MachOper *_opnd_array[2]; |
| 30631 | public: |
| 30632 | MachOper *opnd_array(uint operand_index) const { |
| 30633 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30634 | return _opnd_array[operand_index]; |
| 30635 | } |
| 30636 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30637 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30638 | _opnd_array[operand_index] = operand; |
| 30639 | } |
| 30640 | private: |
| 30641 | virtual const RegMask &out_RegMask() const; |
| 30642 | virtual uint rule() const { return Repl32B_rule; } |
| 30643 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30644 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30645 | virtual uint oper_input_base() const { return 1; } |
| 30646 | public: |
| 30647 | Repl32BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30648 | virtual uint size_of() const { return sizeof(Repl32BNode); } |
| 30649 | static const Pipeline *pipeline_class(); |
| 30650 | virtual const Pipeline *pipeline() const; |
| 30651 | #ifndef PRODUCT |
| 30652 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30653 | virtual const char *Name() const { return "Repl32B";} |
| 30654 | #endif |
| 30655 | }; |
| 30656 | |
| 30657 | class Repl64BNode : public MachTypeNode { |
| 30658 | private: |
| 30659 | MachOper *_opnd_array[2]; |
| 30660 | public: |
| 30661 | MachOper *opnd_array(uint operand_index) const { |
| 30662 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30663 | return _opnd_array[operand_index]; |
| 30664 | } |
| 30665 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30666 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30667 | _opnd_array[operand_index] = operand; |
| 30668 | } |
| 30669 | private: |
| 30670 | virtual const RegMask &out_RegMask() const; |
| 30671 | virtual uint rule() const { return Repl64B_rule; } |
| 30672 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30673 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30674 | virtual uint oper_input_base() const { return 1; } |
| 30675 | public: |
| 30676 | Repl64BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30677 | virtual uint size_of() const { return sizeof(Repl64BNode); } |
| 30678 | static const Pipeline *pipeline_class(); |
| 30679 | virtual const Pipeline *pipeline() const; |
| 30680 | #ifndef PRODUCT |
| 30681 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30682 | virtual const char *Name() const { return "Repl64B";} |
| 30683 | #endif |
| 30684 | }; |
| 30685 | |
| 30686 | class Repl16B_immNode : public MachConstantNode { |
| 30687 | private: |
| 30688 | MachOper *_opnd_array[2]; |
| 30689 | public: |
| 30690 | MachOper *opnd_array(uint operand_index) const { |
| 30691 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30692 | return _opnd_array[operand_index]; |
| 30693 | } |
| 30694 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30695 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30696 | _opnd_array[operand_index] = operand; |
| 30697 | } |
| 30698 | private: |
| 30699 | virtual const RegMask &out_RegMask() const; |
| 30700 | virtual uint rule() const { return Repl16B_imm_rule; } |
| 30701 | virtual void eval_constant(Compile* C); |
| 30702 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30703 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30704 | virtual uint oper_input_base() const { return 1; } |
| 30705 | public: |
| 30706 | Repl16B_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30707 | virtual uint size_of() const { return sizeof(Repl16B_immNode); } |
| 30708 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 30709 | static const Pipeline *pipeline_class(); |
| 30710 | virtual const Pipeline *pipeline() const; |
| 30711 | #ifndef PRODUCT |
| 30712 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30713 | virtual const char *Name() const { return "Repl16B_imm";} |
| 30714 | #endif |
| 30715 | }; |
| 30716 | |
| 30717 | class Repl32B_immNode : public MachConstantNode { |
| 30718 | private: |
| 30719 | MachOper *_opnd_array[2]; |
| 30720 | public: |
| 30721 | MachOper *opnd_array(uint operand_index) const { |
| 30722 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30723 | return _opnd_array[operand_index]; |
| 30724 | } |
| 30725 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30726 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30727 | _opnd_array[operand_index] = operand; |
| 30728 | } |
| 30729 | private: |
| 30730 | virtual const RegMask &out_RegMask() const; |
| 30731 | virtual uint rule() const { return Repl32B_imm_rule; } |
| 30732 | virtual void eval_constant(Compile* C); |
| 30733 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30734 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30735 | virtual uint oper_input_base() const { return 1; } |
| 30736 | public: |
| 30737 | Repl32B_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30738 | virtual uint size_of() const { return sizeof(Repl32B_immNode); } |
| 30739 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 30740 | static const Pipeline *pipeline_class(); |
| 30741 | virtual const Pipeline *pipeline() const; |
| 30742 | #ifndef PRODUCT |
| 30743 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30744 | virtual const char *Name() const { return "Repl32B_imm";} |
| 30745 | #endif |
| 30746 | }; |
| 30747 | |
| 30748 | class Repl64B_immNode : public MachConstantNode { |
| 30749 | private: |
| 30750 | MachOper *_opnd_array[2]; |
| 30751 | public: |
| 30752 | MachOper *opnd_array(uint operand_index) const { |
| 30753 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30754 | return _opnd_array[operand_index]; |
| 30755 | } |
| 30756 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30757 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30758 | _opnd_array[operand_index] = operand; |
| 30759 | } |
| 30760 | private: |
| 30761 | virtual const RegMask &out_RegMask() const; |
| 30762 | virtual uint rule() const { return Repl64B_imm_rule; } |
| 30763 | virtual void eval_constant(Compile* C); |
| 30764 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30765 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 30766 | virtual uint oper_input_base() const { return 1; } |
| 30767 | public: |
| 30768 | Repl64B_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30769 | virtual uint size_of() const { return sizeof(Repl64B_immNode); } |
| 30770 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 30771 | static const Pipeline *pipeline_class(); |
| 30772 | virtual const Pipeline *pipeline() const; |
| 30773 | #ifndef PRODUCT |
| 30774 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30775 | virtual const char *Name() const { return "Repl64B_imm";} |
| 30776 | #endif |
| 30777 | }; |
| 30778 | |
| 30779 | class Repl4SNode : public MachTypeNode { |
| 30780 | private: |
| 30781 | MachOper *_opnd_array[2]; |
| 30782 | public: |
| 30783 | MachOper *opnd_array(uint operand_index) const { |
| 30784 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30785 | return _opnd_array[operand_index]; |
| 30786 | } |
| 30787 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30788 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30789 | _opnd_array[operand_index] = operand; |
| 30790 | } |
| 30791 | private: |
| 30792 | virtual const RegMask &out_RegMask() const; |
| 30793 | virtual uint rule() const { return Repl4S_rule; } |
| 30794 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30795 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30796 | virtual uint oper_input_base() const { return 1; } |
| 30797 | public: |
| 30798 | Repl4SNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30799 | virtual uint size_of() const { return sizeof(Repl4SNode); } |
| 30800 | static const Pipeline *pipeline_class(); |
| 30801 | virtual const Pipeline *pipeline() const; |
| 30802 | #ifndef PRODUCT |
| 30803 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30804 | virtual const char *Name() const { return "Repl4S";} |
| 30805 | #endif |
| 30806 | }; |
| 30807 | |
| 30808 | class Repl4S_memNode : public MachTypeNode { |
| 30809 | private: |
| 30810 | MachOper *_opnd_array[2]; |
| 30811 | public: |
| 30812 | MachOper *opnd_array(uint operand_index) const { |
| 30813 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30814 | return _opnd_array[operand_index]; |
| 30815 | } |
| 30816 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30817 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30818 | _opnd_array[operand_index] = operand; |
| 30819 | } |
| 30820 | private: |
| 30821 | virtual const RegMask &out_RegMask() const; |
| 30822 | virtual uint rule() const { return Repl4S_mem_rule; } |
| 30823 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30824 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30825 | virtual int reloc() const; |
| 30826 | virtual uint oper_input_base() const { return 2; } |
| 30827 | public: |
| 30828 | Repl4S_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30829 | virtual uint size_of() const { return sizeof(Repl4S_memNode); } |
| 30830 | static const Pipeline *pipeline_class(); |
| 30831 | virtual const Pipeline *pipeline() const; |
| 30832 | virtual const MachOper *memory_operand() const; |
| 30833 | #ifndef PRODUCT |
| 30834 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30835 | virtual const char *Name() const { return "Repl4S_mem";} |
| 30836 | #endif |
| 30837 | }; |
| 30838 | |
| 30839 | class Repl8SNode : public MachTypeNode { |
| 30840 | private: |
| 30841 | MachOper *_opnd_array[2]; |
| 30842 | public: |
| 30843 | MachOper *opnd_array(uint operand_index) const { |
| 30844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30845 | return _opnd_array[operand_index]; |
| 30846 | } |
| 30847 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30848 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30849 | _opnd_array[operand_index] = operand; |
| 30850 | } |
| 30851 | private: |
| 30852 | virtual const RegMask &out_RegMask() const; |
| 30853 | virtual uint rule() const { return Repl8S_rule; } |
| 30854 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30855 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30856 | virtual uint oper_input_base() const { return 1; } |
| 30857 | public: |
| 30858 | Repl8SNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30859 | virtual uint size_of() const { return sizeof(Repl8SNode); } |
| 30860 | static const Pipeline *pipeline_class(); |
| 30861 | virtual const Pipeline *pipeline() const; |
| 30862 | #ifndef PRODUCT |
| 30863 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30864 | virtual const char *Name() const { return "Repl8S";} |
| 30865 | #endif |
| 30866 | }; |
| 30867 | |
| 30868 | class Repl8S_memNode : public MachTypeNode { |
| 30869 | private: |
| 30870 | MachOper *_opnd_array[2]; |
| 30871 | public: |
| 30872 | MachOper *opnd_array(uint operand_index) const { |
| 30873 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30874 | return _opnd_array[operand_index]; |
| 30875 | } |
| 30876 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30877 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30878 | _opnd_array[operand_index] = operand; |
| 30879 | } |
| 30880 | private: |
| 30881 | virtual const RegMask &out_RegMask() const; |
| 30882 | virtual uint rule() const { return Repl8S_mem_rule; } |
| 30883 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30884 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30885 | virtual int reloc() const; |
| 30886 | virtual uint oper_input_base() const { return 2; } |
| 30887 | public: |
| 30888 | Repl8S_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30889 | virtual uint size_of() const { return sizeof(Repl8S_memNode); } |
| 30890 | static const Pipeline *pipeline_class(); |
| 30891 | virtual const Pipeline *pipeline() const; |
| 30892 | virtual const MachOper *memory_operand() const; |
| 30893 | #ifndef PRODUCT |
| 30894 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30895 | virtual const char *Name() const { return "Repl8S_mem";} |
| 30896 | #endif |
| 30897 | }; |
| 30898 | |
| 30899 | class Repl8S_immNode : public MachConstantNode { |
| 30900 | private: |
| 30901 | MachOper *_opnd_array[2]; |
| 30902 | public: |
| 30903 | MachOper *opnd_array(uint operand_index) const { |
| 30904 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30905 | return _opnd_array[operand_index]; |
| 30906 | } |
| 30907 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30908 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30909 | _opnd_array[operand_index] = operand; |
| 30910 | } |
| 30911 | private: |
| 30912 | virtual const RegMask &out_RegMask() const; |
| 30913 | virtual uint rule() const { return Repl8S_imm_rule; } |
| 30914 | virtual void eval_constant(Compile* C); |
| 30915 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30916 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30917 | virtual uint oper_input_base() const { return 1; } |
| 30918 | public: |
| 30919 | Repl8S_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30920 | virtual uint size_of() const { return sizeof(Repl8S_immNode); } |
| 30921 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 30922 | static const Pipeline *pipeline_class(); |
| 30923 | virtual const Pipeline *pipeline() const; |
| 30924 | #ifndef PRODUCT |
| 30925 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30926 | virtual const char *Name() const { return "Repl8S_imm";} |
| 30927 | #endif |
| 30928 | }; |
| 30929 | |
| 30930 | class Repl16SNode : public MachTypeNode { |
| 30931 | private: |
| 30932 | MachOper *_opnd_array[2]; |
| 30933 | public: |
| 30934 | MachOper *opnd_array(uint operand_index) const { |
| 30935 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30936 | return _opnd_array[operand_index]; |
| 30937 | } |
| 30938 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30939 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30940 | _opnd_array[operand_index] = operand; |
| 30941 | } |
| 30942 | private: |
| 30943 | virtual const RegMask &out_RegMask() const; |
| 30944 | virtual uint rule() const { return Repl16S_rule; } |
| 30945 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30946 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30947 | virtual uint oper_input_base() const { return 1; } |
| 30948 | public: |
| 30949 | Repl16SNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 30950 | virtual uint size_of() const { return sizeof(Repl16SNode); } |
| 30951 | static const Pipeline *pipeline_class(); |
| 30952 | virtual const Pipeline *pipeline() const; |
| 30953 | #ifndef PRODUCT |
| 30954 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30955 | virtual const char *Name() const { return "Repl16S";} |
| 30956 | #endif |
| 30957 | }; |
| 30958 | |
| 30959 | class Repl16S_memNode : public MachTypeNode { |
| 30960 | private: |
| 30961 | MachOper *_opnd_array[2]; |
| 30962 | public: |
| 30963 | MachOper *opnd_array(uint operand_index) const { |
| 30964 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30965 | return _opnd_array[operand_index]; |
| 30966 | } |
| 30967 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30968 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30969 | _opnd_array[operand_index] = operand; |
| 30970 | } |
| 30971 | private: |
| 30972 | virtual const RegMask &out_RegMask() const; |
| 30973 | virtual uint rule() const { return Repl16S_mem_rule; } |
| 30974 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 30975 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 30976 | virtual int reloc() const; |
| 30977 | virtual uint oper_input_base() const { return 2; } |
| 30978 | public: |
| 30979 | Repl16S_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 30980 | virtual uint size_of() const { return sizeof(Repl16S_memNode); } |
| 30981 | static const Pipeline *pipeline_class(); |
| 30982 | virtual const Pipeline *pipeline() const; |
| 30983 | virtual const MachOper *memory_operand() const; |
| 30984 | #ifndef PRODUCT |
| 30985 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 30986 | virtual const char *Name() const { return "Repl16S_mem";} |
| 30987 | #endif |
| 30988 | }; |
| 30989 | |
| 30990 | class Repl16S_immNode : public MachConstantNode { |
| 30991 | private: |
| 30992 | MachOper *_opnd_array[2]; |
| 30993 | public: |
| 30994 | MachOper *opnd_array(uint operand_index) const { |
| 30995 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 30996 | return _opnd_array[operand_index]; |
| 30997 | } |
| 30998 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 30999 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31000 | _opnd_array[operand_index] = operand; |
| 31001 | } |
| 31002 | private: |
| 31003 | virtual const RegMask &out_RegMask() const; |
| 31004 | virtual uint rule() const { return Repl16S_imm_rule; } |
| 31005 | virtual void eval_constant(Compile* C); |
| 31006 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31007 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 31008 | virtual uint oper_input_base() const { return 1; } |
| 31009 | public: |
| 31010 | Repl16S_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31011 | virtual uint size_of() const { return sizeof(Repl16S_immNode); } |
| 31012 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31013 | static const Pipeline *pipeline_class(); |
| 31014 | virtual const Pipeline *pipeline() const; |
| 31015 | #ifndef PRODUCT |
| 31016 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31017 | virtual const char *Name() const { return "Repl16S_imm";} |
| 31018 | #endif |
| 31019 | }; |
| 31020 | |
| 31021 | class Repl32SNode : public MachTypeNode { |
| 31022 | private: |
| 31023 | MachOper *_opnd_array[2]; |
| 31024 | public: |
| 31025 | MachOper *opnd_array(uint operand_index) const { |
| 31026 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31027 | return _opnd_array[operand_index]; |
| 31028 | } |
| 31029 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31030 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31031 | _opnd_array[operand_index] = operand; |
| 31032 | } |
| 31033 | private: |
| 31034 | virtual const RegMask &out_RegMask() const; |
| 31035 | virtual uint rule() const { return Repl32S_rule; } |
| 31036 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31037 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 31038 | virtual uint oper_input_base() const { return 1; } |
| 31039 | public: |
| 31040 | Repl32SNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31041 | virtual uint size_of() const { return sizeof(Repl32SNode); } |
| 31042 | static const Pipeline *pipeline_class(); |
| 31043 | virtual const Pipeline *pipeline() const; |
| 31044 | #ifndef PRODUCT |
| 31045 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31046 | virtual const char *Name() const { return "Repl32S";} |
| 31047 | #endif |
| 31048 | }; |
| 31049 | |
| 31050 | class Repl32S_memNode : public MachTypeNode { |
| 31051 | private: |
| 31052 | MachOper *_opnd_array[2]; |
| 31053 | public: |
| 31054 | MachOper *opnd_array(uint operand_index) const { |
| 31055 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31056 | return _opnd_array[operand_index]; |
| 31057 | } |
| 31058 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31059 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31060 | _opnd_array[operand_index] = operand; |
| 31061 | } |
| 31062 | private: |
| 31063 | virtual const RegMask &out_RegMask() const; |
| 31064 | virtual uint rule() const { return Repl32S_mem_rule; } |
| 31065 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31066 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 31067 | virtual int reloc() const; |
| 31068 | virtual uint oper_input_base() const { return 2; } |
| 31069 | public: |
| 31070 | Repl32S_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31071 | virtual uint size_of() const { return sizeof(Repl32S_memNode); } |
| 31072 | static const Pipeline *pipeline_class(); |
| 31073 | virtual const Pipeline *pipeline() const; |
| 31074 | virtual const MachOper *memory_operand() const; |
| 31075 | #ifndef PRODUCT |
| 31076 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31077 | virtual const char *Name() const { return "Repl32S_mem";} |
| 31078 | #endif |
| 31079 | }; |
| 31080 | |
| 31081 | class Repl32S_immNode : public MachConstantNode { |
| 31082 | private: |
| 31083 | MachOper *_opnd_array[2]; |
| 31084 | public: |
| 31085 | MachOper *opnd_array(uint operand_index) const { |
| 31086 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31087 | return _opnd_array[operand_index]; |
| 31088 | } |
| 31089 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31090 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31091 | _opnd_array[operand_index] = operand; |
| 31092 | } |
| 31093 | private: |
| 31094 | virtual const RegMask &out_RegMask() const; |
| 31095 | virtual uint rule() const { return Repl32S_imm_rule; } |
| 31096 | virtual void eval_constant(Compile* C); |
| 31097 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31098 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 31099 | virtual uint oper_input_base() const { return 1; } |
| 31100 | public: |
| 31101 | Repl32S_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31102 | virtual uint size_of() const { return sizeof(Repl32S_immNode); } |
| 31103 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31104 | static const Pipeline *pipeline_class(); |
| 31105 | virtual const Pipeline *pipeline() const; |
| 31106 | #ifndef PRODUCT |
| 31107 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31108 | virtual const char *Name() const { return "Repl32S_imm";} |
| 31109 | #endif |
| 31110 | }; |
| 31111 | |
| 31112 | class Repl4INode : public MachTypeNode { |
| 31113 | private: |
| 31114 | MachOper *_opnd_array[2]; |
| 31115 | public: |
| 31116 | MachOper *opnd_array(uint operand_index) const { |
| 31117 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31118 | return _opnd_array[operand_index]; |
| 31119 | } |
| 31120 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31121 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31122 | _opnd_array[operand_index] = operand; |
| 31123 | } |
| 31124 | private: |
| 31125 | virtual const RegMask &out_RegMask() const; |
| 31126 | virtual uint rule() const { return Repl4I_rule; } |
| 31127 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31128 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31129 | virtual uint oper_input_base() const { return 1; } |
| 31130 | public: |
| 31131 | Repl4INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31132 | virtual uint size_of() const { return sizeof(Repl4INode); } |
| 31133 | static const Pipeline *pipeline_class(); |
| 31134 | virtual const Pipeline *pipeline() const; |
| 31135 | #ifndef PRODUCT |
| 31136 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31137 | virtual const char *Name() const { return "Repl4I";} |
| 31138 | #endif |
| 31139 | }; |
| 31140 | |
| 31141 | class Repl4I_memNode : public MachTypeNode { |
| 31142 | private: |
| 31143 | MachOper *_opnd_array[2]; |
| 31144 | public: |
| 31145 | MachOper *opnd_array(uint operand_index) const { |
| 31146 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31147 | return _opnd_array[operand_index]; |
| 31148 | } |
| 31149 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31150 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31151 | _opnd_array[operand_index] = operand; |
| 31152 | } |
| 31153 | private: |
| 31154 | virtual const RegMask &out_RegMask() const; |
| 31155 | virtual uint rule() const { return Repl4I_mem_rule; } |
| 31156 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31157 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31158 | virtual int reloc() const; |
| 31159 | virtual uint oper_input_base() const { return 2; } |
| 31160 | public: |
| 31161 | Repl4I_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31162 | virtual uint size_of() const { return sizeof(Repl4I_memNode); } |
| 31163 | static const Pipeline *pipeline_class(); |
| 31164 | virtual const Pipeline *pipeline() const; |
| 31165 | virtual const MachOper *memory_operand() const; |
| 31166 | #ifndef PRODUCT |
| 31167 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31168 | virtual const char *Name() const { return "Repl4I_mem";} |
| 31169 | #endif |
| 31170 | }; |
| 31171 | |
| 31172 | class Repl8INode : public MachTypeNode { |
| 31173 | private: |
| 31174 | MachOper *_opnd_array[2]; |
| 31175 | public: |
| 31176 | MachOper *opnd_array(uint operand_index) const { |
| 31177 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31178 | return _opnd_array[operand_index]; |
| 31179 | } |
| 31180 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31181 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31182 | _opnd_array[operand_index] = operand; |
| 31183 | } |
| 31184 | private: |
| 31185 | const RegMask *_cisc_RegMask; |
| 31186 | virtual const RegMask &out_RegMask() const; |
| 31187 | virtual uint rule() const { return Repl8I_rule; } |
| 31188 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31189 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31190 | virtual int cisc_operand() const { return 1; } |
| 31191 | virtual MachNode *cisc_version(int offset); |
| 31192 | virtual void use_cisc_RegMask(); |
| 31193 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 31194 | virtual uint oper_input_base() const { return 1; } |
| 31195 | public: |
| 31196 | Repl8INode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 31197 | virtual uint size_of() const { return sizeof(Repl8INode); } |
| 31198 | static const Pipeline *pipeline_class(); |
| 31199 | virtual const Pipeline *pipeline() const; |
| 31200 | #ifndef PRODUCT |
| 31201 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31202 | virtual const char *Name() const { return "Repl8I";} |
| 31203 | #endif |
| 31204 | }; |
| 31205 | |
| 31206 | class Repl8I_memNode : public MachTypeNode { |
| 31207 | private: |
| 31208 | MachOper *_opnd_array[2]; |
| 31209 | public: |
| 31210 | MachOper *opnd_array(uint operand_index) const { |
| 31211 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31212 | return _opnd_array[operand_index]; |
| 31213 | } |
| 31214 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31215 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31216 | _opnd_array[operand_index] = operand; |
| 31217 | } |
| 31218 | private: |
| 31219 | virtual const RegMask &out_RegMask() const; |
| 31220 | virtual uint rule() const { return Repl8I_mem_rule; } |
| 31221 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31222 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31223 | virtual int reloc() const; |
| 31224 | virtual uint oper_input_base() const { return 2; } |
| 31225 | public: |
| 31226 | Repl8I_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 31227 | virtual uint size_of() const { return sizeof(Repl8I_memNode); } |
| 31228 | static const Pipeline *pipeline_class(); |
| 31229 | virtual const Pipeline *pipeline() const; |
| 31230 | virtual const MachOper *memory_operand() const; |
| 31231 | #ifndef PRODUCT |
| 31232 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31233 | virtual const char *Name() const { return "Repl8I_mem";} |
| 31234 | #endif |
| 31235 | }; |
| 31236 | |
| 31237 | class Repl16INode : public MachTypeNode { |
| 31238 | private: |
| 31239 | MachOper *_opnd_array[2]; |
| 31240 | public: |
| 31241 | MachOper *opnd_array(uint operand_index) const { |
| 31242 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31243 | return _opnd_array[operand_index]; |
| 31244 | } |
| 31245 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31246 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31247 | _opnd_array[operand_index] = operand; |
| 31248 | } |
| 31249 | private: |
| 31250 | const RegMask *_cisc_RegMask; |
| 31251 | virtual const RegMask &out_RegMask() const; |
| 31252 | virtual uint rule() const { return Repl16I_rule; } |
| 31253 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31254 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31255 | virtual int cisc_operand() const { return 1; } |
| 31256 | virtual MachNode *cisc_version(int offset); |
| 31257 | virtual void use_cisc_RegMask(); |
| 31258 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 31259 | virtual uint oper_input_base() const { return 1; } |
| 31260 | public: |
| 31261 | Repl16INode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 31262 | virtual uint size_of() const { return sizeof(Repl16INode); } |
| 31263 | static const Pipeline *pipeline_class(); |
| 31264 | virtual const Pipeline *pipeline() const; |
| 31265 | #ifndef PRODUCT |
| 31266 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31267 | virtual const char *Name() const { return "Repl16I";} |
| 31268 | #endif |
| 31269 | }; |
| 31270 | |
| 31271 | class Repl16I_memNode : public MachTypeNode { |
| 31272 | private: |
| 31273 | MachOper *_opnd_array[2]; |
| 31274 | public: |
| 31275 | MachOper *opnd_array(uint operand_index) const { |
| 31276 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31277 | return _opnd_array[operand_index]; |
| 31278 | } |
| 31279 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31280 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31281 | _opnd_array[operand_index] = operand; |
| 31282 | } |
| 31283 | private: |
| 31284 | virtual const RegMask &out_RegMask() const; |
| 31285 | virtual uint rule() const { return Repl16I_mem_rule; } |
| 31286 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31287 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31288 | virtual int reloc() const; |
| 31289 | virtual uint oper_input_base() const { return 2; } |
| 31290 | public: |
| 31291 | Repl16I_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 31292 | virtual uint size_of() const { return sizeof(Repl16I_memNode); } |
| 31293 | static const Pipeline *pipeline_class(); |
| 31294 | virtual const Pipeline *pipeline() const; |
| 31295 | virtual const MachOper *memory_operand() const; |
| 31296 | #ifndef PRODUCT |
| 31297 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31298 | virtual const char *Name() const { return "Repl16I_mem";} |
| 31299 | #endif |
| 31300 | }; |
| 31301 | |
| 31302 | class Repl4I_immNode : public MachConstantNode { |
| 31303 | private: |
| 31304 | MachOper *_opnd_array[2]; |
| 31305 | public: |
| 31306 | MachOper *opnd_array(uint operand_index) const { |
| 31307 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31308 | return _opnd_array[operand_index]; |
| 31309 | } |
| 31310 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31311 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31312 | _opnd_array[operand_index] = operand; |
| 31313 | } |
| 31314 | private: |
| 31315 | virtual const RegMask &out_RegMask() const; |
| 31316 | virtual uint rule() const { return Repl4I_imm_rule; } |
| 31317 | virtual void eval_constant(Compile* C); |
| 31318 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31319 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31320 | virtual uint oper_input_base() const { return 1; } |
| 31321 | public: |
| 31322 | Repl4I_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31323 | virtual uint size_of() const { return sizeof(Repl4I_immNode); } |
| 31324 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31325 | static const Pipeline *pipeline_class(); |
| 31326 | virtual const Pipeline *pipeline() const; |
| 31327 | #ifndef PRODUCT |
| 31328 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31329 | virtual const char *Name() const { return "Repl4I_imm";} |
| 31330 | #endif |
| 31331 | }; |
| 31332 | |
| 31333 | class Repl8I_immNode : public MachConstantNode { |
| 31334 | private: |
| 31335 | MachOper *_opnd_array[2]; |
| 31336 | public: |
| 31337 | MachOper *opnd_array(uint operand_index) const { |
| 31338 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31339 | return _opnd_array[operand_index]; |
| 31340 | } |
| 31341 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31342 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31343 | _opnd_array[operand_index] = operand; |
| 31344 | } |
| 31345 | private: |
| 31346 | virtual const RegMask &out_RegMask() const; |
| 31347 | virtual uint rule() const { return Repl8I_imm_rule; } |
| 31348 | virtual void eval_constant(Compile* C); |
| 31349 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31350 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31351 | virtual uint oper_input_base() const { return 1; } |
| 31352 | public: |
| 31353 | Repl8I_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31354 | virtual uint size_of() const { return sizeof(Repl8I_immNode); } |
| 31355 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31356 | static const Pipeline *pipeline_class(); |
| 31357 | virtual const Pipeline *pipeline() const; |
| 31358 | #ifndef PRODUCT |
| 31359 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31360 | virtual const char *Name() const { return "Repl8I_imm";} |
| 31361 | #endif |
| 31362 | }; |
| 31363 | |
| 31364 | class Repl16I_immNode : public MachConstantNode { |
| 31365 | private: |
| 31366 | MachOper *_opnd_array[2]; |
| 31367 | public: |
| 31368 | MachOper *opnd_array(uint operand_index) const { |
| 31369 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31370 | return _opnd_array[operand_index]; |
| 31371 | } |
| 31372 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31373 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31374 | _opnd_array[operand_index] = operand; |
| 31375 | } |
| 31376 | private: |
| 31377 | virtual const RegMask &out_RegMask() const; |
| 31378 | virtual uint rule() const { return Repl16I_imm_rule; } |
| 31379 | virtual void eval_constant(Compile* C); |
| 31380 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31381 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 31382 | virtual uint oper_input_base() const { return 1; } |
| 31383 | public: |
| 31384 | Repl16I_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31385 | virtual uint size_of() const { return sizeof(Repl16I_immNode); } |
| 31386 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31387 | static const Pipeline *pipeline_class(); |
| 31388 | virtual const Pipeline *pipeline() const; |
| 31389 | #ifndef PRODUCT |
| 31390 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31391 | virtual const char *Name() const { return "Repl16I_imm";} |
| 31392 | #endif |
| 31393 | }; |
| 31394 | |
| 31395 | class Repl2L_memNode : public MachTypeNode { |
| 31396 | private: |
| 31397 | MachOper *_opnd_array[2]; |
| 31398 | public: |
| 31399 | MachOper *opnd_array(uint operand_index) const { |
| 31400 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31401 | return _opnd_array[operand_index]; |
| 31402 | } |
| 31403 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31404 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31405 | _opnd_array[operand_index] = operand; |
| 31406 | } |
| 31407 | private: |
| 31408 | virtual const RegMask &out_RegMask() const; |
| 31409 | virtual uint rule() const { return Repl2L_mem_rule; } |
| 31410 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31411 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31412 | virtual int reloc() const; |
| 31413 | virtual uint oper_input_base() const { return 2; } |
| 31414 | public: |
| 31415 | Repl2L_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31416 | virtual uint size_of() const { return sizeof(Repl2L_memNode); } |
| 31417 | static const Pipeline *pipeline_class(); |
| 31418 | virtual const Pipeline *pipeline() const; |
| 31419 | virtual const MachOper *memory_operand() const; |
| 31420 | #ifndef PRODUCT |
| 31421 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31422 | virtual const char *Name() const { return "Repl2L_mem";} |
| 31423 | #endif |
| 31424 | }; |
| 31425 | |
| 31426 | class Repl4LNode : public MachTypeNode { |
| 31427 | private: |
| 31428 | MachOper *_opnd_array[2]; |
| 31429 | public: |
| 31430 | MachOper *opnd_array(uint operand_index) const { |
| 31431 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31432 | return _opnd_array[operand_index]; |
| 31433 | } |
| 31434 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31435 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31436 | _opnd_array[operand_index] = operand; |
| 31437 | } |
| 31438 | private: |
| 31439 | const RegMask *_cisc_RegMask; |
| 31440 | virtual const RegMask &out_RegMask() const; |
| 31441 | virtual uint rule() const { return Repl4L_rule; } |
| 31442 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31443 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31444 | virtual int cisc_operand() const { return 1; } |
| 31445 | virtual MachNode *cisc_version(int offset); |
| 31446 | virtual void use_cisc_RegMask(); |
| 31447 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 31448 | virtual uint oper_input_base() const { return 1; } |
| 31449 | public: |
| 31450 | Repl4LNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 31451 | virtual uint size_of() const { return sizeof(Repl4LNode); } |
| 31452 | static const Pipeline *pipeline_class(); |
| 31453 | virtual const Pipeline *pipeline() const; |
| 31454 | #ifndef PRODUCT |
| 31455 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31456 | virtual const char *Name() const { return "Repl4L";} |
| 31457 | #endif |
| 31458 | }; |
| 31459 | |
| 31460 | class Repl8LNode : public MachTypeNode { |
| 31461 | private: |
| 31462 | MachOper *_opnd_array[2]; |
| 31463 | public: |
| 31464 | MachOper *opnd_array(uint operand_index) const { |
| 31465 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31466 | return _opnd_array[operand_index]; |
| 31467 | } |
| 31468 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31469 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31470 | _opnd_array[operand_index] = operand; |
| 31471 | } |
| 31472 | private: |
| 31473 | const RegMask *_cisc_RegMask; |
| 31474 | virtual const RegMask &out_RegMask() const; |
| 31475 | virtual uint rule() const { return Repl8L_rule; } |
| 31476 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31477 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31478 | virtual int cisc_operand() const { return 1; } |
| 31479 | virtual MachNode *cisc_version(int offset); |
| 31480 | virtual void use_cisc_RegMask(); |
| 31481 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 31482 | virtual uint oper_input_base() const { return 1; } |
| 31483 | public: |
| 31484 | Repl8LNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 31485 | virtual uint size_of() const { return sizeof(Repl8LNode); } |
| 31486 | static const Pipeline *pipeline_class(); |
| 31487 | virtual const Pipeline *pipeline() const; |
| 31488 | #ifndef PRODUCT |
| 31489 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31490 | virtual const char *Name() const { return "Repl8L";} |
| 31491 | #endif |
| 31492 | }; |
| 31493 | |
| 31494 | class Repl4L_immNode : public MachConstantNode { |
| 31495 | private: |
| 31496 | MachOper *_opnd_array[2]; |
| 31497 | public: |
| 31498 | MachOper *opnd_array(uint operand_index) const { |
| 31499 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31500 | return _opnd_array[operand_index]; |
| 31501 | } |
| 31502 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31503 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31504 | _opnd_array[operand_index] = operand; |
| 31505 | } |
| 31506 | private: |
| 31507 | virtual const RegMask &out_RegMask() const; |
| 31508 | virtual uint rule() const { return Repl4L_imm_rule; } |
| 31509 | virtual void eval_constant(Compile* C); |
| 31510 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31511 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31512 | virtual uint oper_input_base() const { return 1; } |
| 31513 | public: |
| 31514 | Repl4L_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31515 | virtual uint size_of() const { return sizeof(Repl4L_immNode); } |
| 31516 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31517 | static const Pipeline *pipeline_class(); |
| 31518 | virtual const Pipeline *pipeline() const; |
| 31519 | #ifndef PRODUCT |
| 31520 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31521 | virtual const char *Name() const { return "Repl4L_imm";} |
| 31522 | #endif |
| 31523 | }; |
| 31524 | |
| 31525 | class Repl8L_immNode : public MachConstantNode { |
| 31526 | private: |
| 31527 | MachOper *_opnd_array[2]; |
| 31528 | public: |
| 31529 | MachOper *opnd_array(uint operand_index) const { |
| 31530 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31531 | return _opnd_array[operand_index]; |
| 31532 | } |
| 31533 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31534 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31535 | _opnd_array[operand_index] = operand; |
| 31536 | } |
| 31537 | private: |
| 31538 | virtual const RegMask &out_RegMask() const; |
| 31539 | virtual uint rule() const { return Repl8L_imm_rule; } |
| 31540 | virtual void eval_constant(Compile* C); |
| 31541 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31542 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31543 | virtual uint oper_input_base() const { return 1; } |
| 31544 | public: |
| 31545 | Repl8L_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31546 | virtual uint size_of() const { return sizeof(Repl8L_immNode); } |
| 31547 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 31548 | static const Pipeline *pipeline_class(); |
| 31549 | virtual const Pipeline *pipeline() const; |
| 31550 | #ifndef PRODUCT |
| 31551 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31552 | virtual const char *Name() const { return "Repl8L_imm";} |
| 31553 | #endif |
| 31554 | }; |
| 31555 | |
| 31556 | class Repl4L_memNode : public MachTypeNode { |
| 31557 | private: |
| 31558 | MachOper *_opnd_array[2]; |
| 31559 | public: |
| 31560 | MachOper *opnd_array(uint operand_index) const { |
| 31561 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31562 | return _opnd_array[operand_index]; |
| 31563 | } |
| 31564 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31565 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31566 | _opnd_array[operand_index] = operand; |
| 31567 | } |
| 31568 | private: |
| 31569 | virtual const RegMask &out_RegMask() const; |
| 31570 | virtual uint rule() const { return Repl4L_mem_rule; } |
| 31571 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31572 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31573 | virtual int reloc() const; |
| 31574 | virtual uint oper_input_base() const { return 2; } |
| 31575 | public: |
| 31576 | Repl4L_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 31577 | virtual uint size_of() const { return sizeof(Repl4L_memNode); } |
| 31578 | static const Pipeline *pipeline_class(); |
| 31579 | virtual const Pipeline *pipeline() const; |
| 31580 | virtual const MachOper *memory_operand() const; |
| 31581 | #ifndef PRODUCT |
| 31582 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31583 | virtual const char *Name() const { return "Repl4L_mem";} |
| 31584 | #endif |
| 31585 | }; |
| 31586 | |
| 31587 | class Repl8L_memNode : public MachTypeNode { |
| 31588 | private: |
| 31589 | MachOper *_opnd_array[2]; |
| 31590 | public: |
| 31591 | MachOper *opnd_array(uint operand_index) const { |
| 31592 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31593 | return _opnd_array[operand_index]; |
| 31594 | } |
| 31595 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31596 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31597 | _opnd_array[operand_index] = operand; |
| 31598 | } |
| 31599 | private: |
| 31600 | virtual const RegMask &out_RegMask() const; |
| 31601 | virtual uint rule() const { return Repl8L_mem_rule; } |
| 31602 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31603 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 31604 | virtual int reloc() const; |
| 31605 | virtual uint oper_input_base() const { return 2; } |
| 31606 | public: |
| 31607 | Repl8L_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 31608 | virtual uint size_of() const { return sizeof(Repl8L_memNode); } |
| 31609 | static const Pipeline *pipeline_class(); |
| 31610 | virtual const Pipeline *pipeline() const; |
| 31611 | virtual const MachOper *memory_operand() const; |
| 31612 | #ifndef PRODUCT |
| 31613 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31614 | virtual const char *Name() const { return "Repl8L_mem";} |
| 31615 | #endif |
| 31616 | }; |
| 31617 | |
| 31618 | class Repl2F_memNode : public MachTypeNode { |
| 31619 | private: |
| 31620 | MachOper *_opnd_array[2]; |
| 31621 | public: |
| 31622 | MachOper *opnd_array(uint operand_index) const { |
| 31623 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31624 | return _opnd_array[operand_index]; |
| 31625 | } |
| 31626 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31627 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31628 | _opnd_array[operand_index] = operand; |
| 31629 | } |
| 31630 | private: |
| 31631 | virtual const RegMask &out_RegMask() const; |
| 31632 | virtual uint rule() const { return Repl2F_mem_rule; } |
| 31633 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31634 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31635 | virtual int reloc() const; |
| 31636 | virtual uint oper_input_base() const { return 2; } |
| 31637 | public: |
| 31638 | Repl2F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31639 | virtual uint size_of() const { return sizeof(Repl2F_memNode); } |
| 31640 | static const Pipeline *pipeline_class(); |
| 31641 | virtual const Pipeline *pipeline() const; |
| 31642 | virtual const MachOper *memory_operand() const; |
| 31643 | #ifndef PRODUCT |
| 31644 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31645 | virtual const char *Name() const { return "Repl2F_mem";} |
| 31646 | #endif |
| 31647 | }; |
| 31648 | |
| 31649 | class Repl4F_memNode : public MachTypeNode { |
| 31650 | private: |
| 31651 | MachOper *_opnd_array[2]; |
| 31652 | public: |
| 31653 | MachOper *opnd_array(uint operand_index) const { |
| 31654 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31655 | return _opnd_array[operand_index]; |
| 31656 | } |
| 31657 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31658 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31659 | _opnd_array[operand_index] = operand; |
| 31660 | } |
| 31661 | private: |
| 31662 | virtual const RegMask &out_RegMask() const; |
| 31663 | virtual uint rule() const { return Repl4F_mem_rule; } |
| 31664 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31665 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31666 | virtual int reloc() const; |
| 31667 | virtual uint oper_input_base() const { return 2; } |
| 31668 | public: |
| 31669 | Repl4F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31670 | virtual uint size_of() const { return sizeof(Repl4F_memNode); } |
| 31671 | static const Pipeline *pipeline_class(); |
| 31672 | virtual const Pipeline *pipeline() const; |
| 31673 | virtual const MachOper *memory_operand() const; |
| 31674 | #ifndef PRODUCT |
| 31675 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31676 | virtual const char *Name() const { return "Repl4F_mem";} |
| 31677 | #endif |
| 31678 | }; |
| 31679 | |
| 31680 | class Repl8FNode : public MachTypeNode { |
| 31681 | private: |
| 31682 | MachOper *_opnd_array[2]; |
| 31683 | public: |
| 31684 | MachOper *opnd_array(uint operand_index) const { |
| 31685 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31686 | return _opnd_array[operand_index]; |
| 31687 | } |
| 31688 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31689 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31690 | _opnd_array[operand_index] = operand; |
| 31691 | } |
| 31692 | private: |
| 31693 | virtual const RegMask &out_RegMask() const; |
| 31694 | virtual uint rule() const { return Repl8F_rule; } |
| 31695 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31696 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31697 | virtual uint oper_input_base() const { return 1; } |
| 31698 | public: |
| 31699 | Repl8FNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31700 | virtual uint size_of() const { return sizeof(Repl8FNode); } |
| 31701 | static const Pipeline *pipeline_class(); |
| 31702 | virtual const Pipeline *pipeline() const; |
| 31703 | #ifndef PRODUCT |
| 31704 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31705 | virtual const char *Name() const { return "Repl8F";} |
| 31706 | #endif |
| 31707 | }; |
| 31708 | |
| 31709 | class Repl8F_memNode : public MachTypeNode { |
| 31710 | private: |
| 31711 | MachOper *_opnd_array[2]; |
| 31712 | public: |
| 31713 | MachOper *opnd_array(uint operand_index) const { |
| 31714 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31715 | return _opnd_array[operand_index]; |
| 31716 | } |
| 31717 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31718 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31719 | _opnd_array[operand_index] = operand; |
| 31720 | } |
| 31721 | private: |
| 31722 | virtual const RegMask &out_RegMask() const; |
| 31723 | virtual uint rule() const { return Repl8F_mem_rule; } |
| 31724 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31725 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31726 | virtual int reloc() const; |
| 31727 | virtual uint oper_input_base() const { return 2; } |
| 31728 | public: |
| 31729 | Repl8F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31730 | virtual uint size_of() const { return sizeof(Repl8F_memNode); } |
| 31731 | static const Pipeline *pipeline_class(); |
| 31732 | virtual const Pipeline *pipeline() const; |
| 31733 | virtual const MachOper *memory_operand() const; |
| 31734 | #ifndef PRODUCT |
| 31735 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31736 | virtual const char *Name() const { return "Repl8F_mem";} |
| 31737 | #endif |
| 31738 | }; |
| 31739 | |
| 31740 | class Repl16FNode : public MachTypeNode { |
| 31741 | private: |
| 31742 | MachOper *_opnd_array[2]; |
| 31743 | public: |
| 31744 | MachOper *opnd_array(uint operand_index) const { |
| 31745 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31746 | return _opnd_array[operand_index]; |
| 31747 | } |
| 31748 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31750 | _opnd_array[operand_index] = operand; |
| 31751 | } |
| 31752 | private: |
| 31753 | virtual const RegMask &out_RegMask() const; |
| 31754 | virtual uint rule() const { return Repl16F_rule; } |
| 31755 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31756 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31757 | virtual uint oper_input_base() const { return 1; } |
| 31758 | public: |
| 31759 | Repl16FNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31760 | virtual uint size_of() const { return sizeof(Repl16FNode); } |
| 31761 | static const Pipeline *pipeline_class(); |
| 31762 | virtual const Pipeline *pipeline() const; |
| 31763 | #ifndef PRODUCT |
| 31764 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31765 | virtual const char *Name() const { return "Repl16F";} |
| 31766 | #endif |
| 31767 | }; |
| 31768 | |
| 31769 | class Repl16F_memNode : public MachTypeNode { |
| 31770 | private: |
| 31771 | MachOper *_opnd_array[2]; |
| 31772 | public: |
| 31773 | MachOper *opnd_array(uint operand_index) const { |
| 31774 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31775 | return _opnd_array[operand_index]; |
| 31776 | } |
| 31777 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31778 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31779 | _opnd_array[operand_index] = operand; |
| 31780 | } |
| 31781 | private: |
| 31782 | virtual const RegMask &out_RegMask() const; |
| 31783 | virtual uint rule() const { return Repl16F_mem_rule; } |
| 31784 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31785 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31786 | virtual int reloc() const; |
| 31787 | virtual uint oper_input_base() const { return 2; } |
| 31788 | public: |
| 31789 | Repl16F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31790 | virtual uint size_of() const { return sizeof(Repl16F_memNode); } |
| 31791 | static const Pipeline *pipeline_class(); |
| 31792 | virtual const Pipeline *pipeline() const; |
| 31793 | virtual const MachOper *memory_operand() const; |
| 31794 | #ifndef PRODUCT |
| 31795 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31796 | virtual const char *Name() const { return "Repl16F_mem";} |
| 31797 | #endif |
| 31798 | }; |
| 31799 | |
| 31800 | class Repl2F_zeroNode : public MachTypeNode { |
| 31801 | private: |
| 31802 | MachOper *_opnd_array[2]; |
| 31803 | public: |
| 31804 | MachOper *opnd_array(uint operand_index) const { |
| 31805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31806 | return _opnd_array[operand_index]; |
| 31807 | } |
| 31808 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31809 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31810 | _opnd_array[operand_index] = operand; |
| 31811 | } |
| 31812 | private: |
| 31813 | virtual const RegMask &out_RegMask() const; |
| 31814 | virtual uint rule() const { return Repl2F_zero_rule; } |
| 31815 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31816 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31817 | virtual int reloc() const; |
| 31818 | virtual uint oper_input_base() const { return 1; } |
| 31819 | public: |
| 31820 | Repl2F_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31821 | virtual uint size_of() const { return sizeof(Repl2F_zeroNode); } |
| 31822 | static const Pipeline *pipeline_class(); |
| 31823 | virtual const Pipeline *pipeline() const; |
| 31824 | #ifndef PRODUCT |
| 31825 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31826 | virtual const char *Name() const { return "Repl2F_zero";} |
| 31827 | #endif |
| 31828 | }; |
| 31829 | |
| 31830 | class Repl4F_zeroNode : public MachTypeNode { |
| 31831 | private: |
| 31832 | MachOper *_opnd_array[2]; |
| 31833 | public: |
| 31834 | MachOper *opnd_array(uint operand_index) const { |
| 31835 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31836 | return _opnd_array[operand_index]; |
| 31837 | } |
| 31838 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31840 | _opnd_array[operand_index] = operand; |
| 31841 | } |
| 31842 | private: |
| 31843 | virtual const RegMask &out_RegMask() const; |
| 31844 | virtual uint rule() const { return Repl4F_zero_rule; } |
| 31845 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31846 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31847 | virtual int reloc() const; |
| 31848 | virtual uint oper_input_base() const { return 1; } |
| 31849 | public: |
| 31850 | Repl4F_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31851 | virtual uint size_of() const { return sizeof(Repl4F_zeroNode); } |
| 31852 | static const Pipeline *pipeline_class(); |
| 31853 | virtual const Pipeline *pipeline() const; |
| 31854 | #ifndef PRODUCT |
| 31855 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31856 | virtual const char *Name() const { return "Repl4F_zero";} |
| 31857 | #endif |
| 31858 | }; |
| 31859 | |
| 31860 | class Repl8F_zeroNode : public MachTypeNode { |
| 31861 | private: |
| 31862 | MachOper *_opnd_array[2]; |
| 31863 | public: |
| 31864 | MachOper *opnd_array(uint operand_index) const { |
| 31865 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31866 | return _opnd_array[operand_index]; |
| 31867 | } |
| 31868 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31869 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31870 | _opnd_array[operand_index] = operand; |
| 31871 | } |
| 31872 | private: |
| 31873 | virtual const RegMask &out_RegMask() const; |
| 31874 | virtual uint rule() const { return Repl8F_zero_rule; } |
| 31875 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31876 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 31877 | virtual int reloc() const; |
| 31878 | virtual uint oper_input_base() const { return 1; } |
| 31879 | public: |
| 31880 | Repl8F_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31881 | virtual uint size_of() const { return sizeof(Repl8F_zeroNode); } |
| 31882 | static const Pipeline *pipeline_class(); |
| 31883 | virtual const Pipeline *pipeline() const; |
| 31884 | #ifndef PRODUCT |
| 31885 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31886 | virtual const char *Name() const { return "Repl8F_zero";} |
| 31887 | #endif |
| 31888 | }; |
| 31889 | |
| 31890 | class Repl2D_memNode : public MachTypeNode { |
| 31891 | private: |
| 31892 | MachOper *_opnd_array[2]; |
| 31893 | public: |
| 31894 | MachOper *opnd_array(uint operand_index) const { |
| 31895 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31896 | return _opnd_array[operand_index]; |
| 31897 | } |
| 31898 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31899 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31900 | _opnd_array[operand_index] = operand; |
| 31901 | } |
| 31902 | private: |
| 31903 | virtual const RegMask &out_RegMask() const; |
| 31904 | virtual uint rule() const { return Repl2D_mem_rule; } |
| 31905 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31906 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 31907 | virtual int reloc() const; |
| 31908 | virtual uint oper_input_base() const { return 2; } |
| 31909 | public: |
| 31910 | Repl2D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31911 | virtual uint size_of() const { return sizeof(Repl2D_memNode); } |
| 31912 | static const Pipeline *pipeline_class(); |
| 31913 | virtual const Pipeline *pipeline() const; |
| 31914 | virtual const MachOper *memory_operand() const; |
| 31915 | #ifndef PRODUCT |
| 31916 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31917 | virtual const char *Name() const { return "Repl2D_mem";} |
| 31918 | #endif |
| 31919 | }; |
| 31920 | |
| 31921 | class Repl4DNode : public MachTypeNode { |
| 31922 | private: |
| 31923 | MachOper *_opnd_array[2]; |
| 31924 | public: |
| 31925 | MachOper *opnd_array(uint operand_index) const { |
| 31926 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31927 | return _opnd_array[operand_index]; |
| 31928 | } |
| 31929 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31930 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31931 | _opnd_array[operand_index] = operand; |
| 31932 | } |
| 31933 | private: |
| 31934 | virtual const RegMask &out_RegMask() const; |
| 31935 | virtual uint rule() const { return Repl4D_rule; } |
| 31936 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31937 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 31938 | virtual uint oper_input_base() const { return 1; } |
| 31939 | public: |
| 31940 | Repl4DNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 31941 | virtual uint size_of() const { return sizeof(Repl4DNode); } |
| 31942 | static const Pipeline *pipeline_class(); |
| 31943 | virtual const Pipeline *pipeline() const; |
| 31944 | #ifndef PRODUCT |
| 31945 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31946 | virtual const char *Name() const { return "Repl4D";} |
| 31947 | #endif |
| 31948 | }; |
| 31949 | |
| 31950 | class Repl4D_memNode : public MachTypeNode { |
| 31951 | private: |
| 31952 | MachOper *_opnd_array[2]; |
| 31953 | public: |
| 31954 | MachOper *opnd_array(uint operand_index) const { |
| 31955 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31956 | return _opnd_array[operand_index]; |
| 31957 | } |
| 31958 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31959 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31960 | _opnd_array[operand_index] = operand; |
| 31961 | } |
| 31962 | private: |
| 31963 | virtual const RegMask &out_RegMask() const; |
| 31964 | virtual uint rule() const { return Repl4D_mem_rule; } |
| 31965 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31966 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 31967 | virtual int reloc() const; |
| 31968 | virtual uint oper_input_base() const { return 2; } |
| 31969 | public: |
| 31970 | Repl4D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 31971 | virtual uint size_of() const { return sizeof(Repl4D_memNode); } |
| 31972 | static const Pipeline *pipeline_class(); |
| 31973 | virtual const Pipeline *pipeline() const; |
| 31974 | virtual const MachOper *memory_operand() const; |
| 31975 | #ifndef PRODUCT |
| 31976 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 31977 | virtual const char *Name() const { return "Repl4D_mem";} |
| 31978 | #endif |
| 31979 | }; |
| 31980 | |
| 31981 | class Repl8DNode : public MachTypeNode { |
| 31982 | private: |
| 31983 | MachOper *_opnd_array[2]; |
| 31984 | public: |
| 31985 | MachOper *opnd_array(uint operand_index) const { |
| 31986 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31987 | return _opnd_array[operand_index]; |
| 31988 | } |
| 31989 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 31990 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 31991 | _opnd_array[operand_index] = operand; |
| 31992 | } |
| 31993 | private: |
| 31994 | virtual const RegMask &out_RegMask() const; |
| 31995 | virtual uint rule() const { return Repl8D_rule; } |
| 31996 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 31997 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 31998 | virtual uint oper_input_base() const { return 1; } |
| 31999 | public: |
| 32000 | Repl8DNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32001 | virtual uint size_of() const { return sizeof(Repl8DNode); } |
| 32002 | static const Pipeline *pipeline_class(); |
| 32003 | virtual const Pipeline *pipeline() const; |
| 32004 | #ifndef PRODUCT |
| 32005 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32006 | virtual const char *Name() const { return "Repl8D";} |
| 32007 | #endif |
| 32008 | }; |
| 32009 | |
| 32010 | class Repl8D_memNode : public MachTypeNode { |
| 32011 | private: |
| 32012 | MachOper *_opnd_array[2]; |
| 32013 | public: |
| 32014 | MachOper *opnd_array(uint operand_index) const { |
| 32015 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32016 | return _opnd_array[operand_index]; |
| 32017 | } |
| 32018 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32019 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32020 | _opnd_array[operand_index] = operand; |
| 32021 | } |
| 32022 | private: |
| 32023 | virtual const RegMask &out_RegMask() const; |
| 32024 | virtual uint rule() const { return Repl8D_mem_rule; } |
| 32025 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32026 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 32027 | virtual int reloc() const; |
| 32028 | virtual uint oper_input_base() const { return 2; } |
| 32029 | public: |
| 32030 | Repl8D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 32031 | virtual uint size_of() const { return sizeof(Repl8D_memNode); } |
| 32032 | static const Pipeline *pipeline_class(); |
| 32033 | virtual const Pipeline *pipeline() const; |
| 32034 | virtual const MachOper *memory_operand() const; |
| 32035 | #ifndef PRODUCT |
| 32036 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32037 | virtual const char *Name() const { return "Repl8D_mem";} |
| 32038 | #endif |
| 32039 | }; |
| 32040 | |
| 32041 | class Repl2D_zeroNode : public MachTypeNode { |
| 32042 | private: |
| 32043 | MachOper *_opnd_array[2]; |
| 32044 | public: |
| 32045 | MachOper *opnd_array(uint operand_index) const { |
| 32046 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32047 | return _opnd_array[operand_index]; |
| 32048 | } |
| 32049 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32050 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32051 | _opnd_array[operand_index] = operand; |
| 32052 | } |
| 32053 | private: |
| 32054 | virtual const RegMask &out_RegMask() const; |
| 32055 | virtual uint rule() const { return Repl2D_zero_rule; } |
| 32056 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32057 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 32058 | virtual int reloc() const; |
| 32059 | virtual uint oper_input_base() const { return 1; } |
| 32060 | public: |
| 32061 | Repl2D_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32062 | virtual uint size_of() const { return sizeof(Repl2D_zeroNode); } |
| 32063 | static const Pipeline *pipeline_class(); |
| 32064 | virtual const Pipeline *pipeline() const; |
| 32065 | #ifndef PRODUCT |
| 32066 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32067 | virtual const char *Name() const { return "Repl2D_zero";} |
| 32068 | #endif |
| 32069 | }; |
| 32070 | |
| 32071 | class Repl4D_zeroNode : public MachTypeNode { |
| 32072 | private: |
| 32073 | MachOper *_opnd_array[2]; |
| 32074 | public: |
| 32075 | MachOper *opnd_array(uint operand_index) const { |
| 32076 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32077 | return _opnd_array[operand_index]; |
| 32078 | } |
| 32079 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32080 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32081 | _opnd_array[operand_index] = operand; |
| 32082 | } |
| 32083 | private: |
| 32084 | virtual const RegMask &out_RegMask() const; |
| 32085 | virtual uint rule() const { return Repl4D_zero_rule; } |
| 32086 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32087 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 32088 | virtual int reloc() const; |
| 32089 | virtual uint oper_input_base() const { return 1; } |
| 32090 | public: |
| 32091 | Repl4D_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32092 | virtual uint size_of() const { return sizeof(Repl4D_zeroNode); } |
| 32093 | static const Pipeline *pipeline_class(); |
| 32094 | virtual const Pipeline *pipeline() const; |
| 32095 | #ifndef PRODUCT |
| 32096 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32097 | virtual const char *Name() const { return "Repl4D_zero";} |
| 32098 | #endif |
| 32099 | }; |
| 32100 | |
| 32101 | class Repl4BNode : public MachTypeNode { |
| 32102 | private: |
| 32103 | MachOper *_opnd_array[2]; |
| 32104 | public: |
| 32105 | MachOper *opnd_array(uint operand_index) const { |
| 32106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32107 | return _opnd_array[operand_index]; |
| 32108 | } |
| 32109 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32110 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32111 | _opnd_array[operand_index] = operand; |
| 32112 | } |
| 32113 | private: |
| 32114 | virtual const RegMask &out_RegMask() const; |
| 32115 | virtual uint rule() const { return Repl4B_rule; } |
| 32116 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32117 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32118 | virtual uint oper_input_base() const { return 1; } |
| 32119 | public: |
| 32120 | Repl4BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32121 | virtual uint size_of() const { return sizeof(Repl4BNode); } |
| 32122 | static const Pipeline *pipeline_class(); |
| 32123 | virtual const Pipeline *pipeline() const; |
| 32124 | #ifndef PRODUCT |
| 32125 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32126 | virtual const char *Name() const { return "Repl4B";} |
| 32127 | #endif |
| 32128 | }; |
| 32129 | |
| 32130 | class Repl8BNode : public MachTypeNode { |
| 32131 | private: |
| 32132 | MachOper *_opnd_array[2]; |
| 32133 | public: |
| 32134 | MachOper *opnd_array(uint operand_index) const { |
| 32135 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32136 | return _opnd_array[operand_index]; |
| 32137 | } |
| 32138 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32139 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32140 | _opnd_array[operand_index] = operand; |
| 32141 | } |
| 32142 | private: |
| 32143 | virtual const RegMask &out_RegMask() const; |
| 32144 | virtual uint rule() const { return Repl8B_rule; } |
| 32145 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32146 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32147 | virtual uint oper_input_base() const { return 1; } |
| 32148 | public: |
| 32149 | Repl8BNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32150 | virtual uint size_of() const { return sizeof(Repl8BNode); } |
| 32151 | static const Pipeline *pipeline_class(); |
| 32152 | virtual const Pipeline *pipeline() const; |
| 32153 | #ifndef PRODUCT |
| 32154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32155 | virtual const char *Name() const { return "Repl8B";} |
| 32156 | #endif |
| 32157 | }; |
| 32158 | |
| 32159 | class Repl4B_immNode : public MachConstantNode { |
| 32160 | private: |
| 32161 | MachOper *_opnd_array[2]; |
| 32162 | public: |
| 32163 | MachOper *opnd_array(uint operand_index) const { |
| 32164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32165 | return _opnd_array[operand_index]; |
| 32166 | } |
| 32167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32169 | _opnd_array[operand_index] = operand; |
| 32170 | } |
| 32171 | private: |
| 32172 | virtual const RegMask &out_RegMask() const; |
| 32173 | virtual uint rule() const { return Repl4B_imm_rule; } |
| 32174 | virtual void eval_constant(Compile* C); |
| 32175 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32176 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32177 | virtual uint oper_input_base() const { return 1; } |
| 32178 | public: |
| 32179 | Repl4B_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32180 | virtual uint size_of() const { return sizeof(Repl4B_immNode); } |
| 32181 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32182 | static const Pipeline *pipeline_class(); |
| 32183 | virtual const Pipeline *pipeline() const; |
| 32184 | #ifndef PRODUCT |
| 32185 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32186 | virtual const char *Name() const { return "Repl4B_imm";} |
| 32187 | #endif |
| 32188 | }; |
| 32189 | |
| 32190 | class Repl8B_immNode : public MachConstantNode { |
| 32191 | private: |
| 32192 | MachOper *_opnd_array[2]; |
| 32193 | public: |
| 32194 | MachOper *opnd_array(uint operand_index) const { |
| 32195 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32196 | return _opnd_array[operand_index]; |
| 32197 | } |
| 32198 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32200 | _opnd_array[operand_index] = operand; |
| 32201 | } |
| 32202 | private: |
| 32203 | virtual const RegMask &out_RegMask() const; |
| 32204 | virtual uint rule() const { return Repl8B_imm_rule; } |
| 32205 | virtual void eval_constant(Compile* C); |
| 32206 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32207 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32208 | virtual uint oper_input_base() const { return 1; } |
| 32209 | public: |
| 32210 | Repl8B_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32211 | virtual uint size_of() const { return sizeof(Repl8B_immNode); } |
| 32212 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32213 | static const Pipeline *pipeline_class(); |
| 32214 | virtual const Pipeline *pipeline() const; |
| 32215 | #ifndef PRODUCT |
| 32216 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32217 | virtual const char *Name() const { return "Repl8B_imm";} |
| 32218 | #endif |
| 32219 | }; |
| 32220 | |
| 32221 | class Repl4B_zeroNode : public MachTypeNode { |
| 32222 | private: |
| 32223 | MachOper *_opnd_array[2]; |
| 32224 | public: |
| 32225 | MachOper *opnd_array(uint operand_index) const { |
| 32226 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32227 | return _opnd_array[operand_index]; |
| 32228 | } |
| 32229 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32231 | _opnd_array[operand_index] = operand; |
| 32232 | } |
| 32233 | private: |
| 32234 | virtual const RegMask &out_RegMask() const; |
| 32235 | virtual uint rule() const { return Repl4B_zero_rule; } |
| 32236 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32237 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32238 | virtual uint oper_input_base() const { return 1; } |
| 32239 | public: |
| 32240 | Repl4B_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32241 | virtual uint size_of() const { return sizeof(Repl4B_zeroNode); } |
| 32242 | static const Pipeline *pipeline_class(); |
| 32243 | virtual const Pipeline *pipeline() const; |
| 32244 | #ifndef PRODUCT |
| 32245 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32246 | virtual const char *Name() const { return "Repl4B_zero";} |
| 32247 | #endif |
| 32248 | }; |
| 32249 | |
| 32250 | class Repl8B_zeroNode : public MachTypeNode { |
| 32251 | private: |
| 32252 | MachOper *_opnd_array[2]; |
| 32253 | public: |
| 32254 | MachOper *opnd_array(uint operand_index) const { |
| 32255 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32256 | return _opnd_array[operand_index]; |
| 32257 | } |
| 32258 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32259 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32260 | _opnd_array[operand_index] = operand; |
| 32261 | } |
| 32262 | private: |
| 32263 | virtual const RegMask &out_RegMask() const; |
| 32264 | virtual uint rule() const { return Repl8B_zero_rule; } |
| 32265 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32266 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32267 | virtual uint oper_input_base() const { return 1; } |
| 32268 | public: |
| 32269 | Repl8B_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32270 | virtual uint size_of() const { return sizeof(Repl8B_zeroNode); } |
| 32271 | static const Pipeline *pipeline_class(); |
| 32272 | virtual const Pipeline *pipeline() const; |
| 32273 | #ifndef PRODUCT |
| 32274 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32275 | virtual const char *Name() const { return "Repl8B_zero";} |
| 32276 | #endif |
| 32277 | }; |
| 32278 | |
| 32279 | class Repl16B_zeroNode : public MachTypeNode { |
| 32280 | private: |
| 32281 | MachOper *_opnd_array[2]; |
| 32282 | public: |
| 32283 | MachOper *opnd_array(uint operand_index) const { |
| 32284 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32285 | return _opnd_array[operand_index]; |
| 32286 | } |
| 32287 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32288 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32289 | _opnd_array[operand_index] = operand; |
| 32290 | } |
| 32291 | private: |
| 32292 | virtual const RegMask &out_RegMask() const; |
| 32293 | virtual uint rule() const { return Repl16B_zero_rule; } |
| 32294 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32295 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32296 | virtual uint oper_input_base() const { return 1; } |
| 32297 | public: |
| 32298 | Repl16B_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32299 | virtual uint size_of() const { return sizeof(Repl16B_zeroNode); } |
| 32300 | static const Pipeline *pipeline_class(); |
| 32301 | virtual const Pipeline *pipeline() const; |
| 32302 | #ifndef PRODUCT |
| 32303 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32304 | virtual const char *Name() const { return "Repl16B_zero";} |
| 32305 | #endif |
| 32306 | }; |
| 32307 | |
| 32308 | class Repl32B_zeroNode : public MachTypeNode { |
| 32309 | private: |
| 32310 | MachOper *_opnd_array[2]; |
| 32311 | public: |
| 32312 | MachOper *opnd_array(uint operand_index) const { |
| 32313 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32314 | return _opnd_array[operand_index]; |
| 32315 | } |
| 32316 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32317 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32318 | _opnd_array[operand_index] = operand; |
| 32319 | } |
| 32320 | private: |
| 32321 | virtual const RegMask &out_RegMask() const; |
| 32322 | virtual uint rule() const { return Repl32B_zero_rule; } |
| 32323 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32324 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32325 | virtual uint oper_input_base() const { return 1; } |
| 32326 | public: |
| 32327 | Repl32B_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32328 | virtual uint size_of() const { return sizeof(Repl32B_zeroNode); } |
| 32329 | static const Pipeline *pipeline_class(); |
| 32330 | virtual const Pipeline *pipeline() const; |
| 32331 | #ifndef PRODUCT |
| 32332 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32333 | virtual const char *Name() const { return "Repl32B_zero";} |
| 32334 | #endif |
| 32335 | }; |
| 32336 | |
| 32337 | class Repl2SNode : public MachTypeNode { |
| 32338 | private: |
| 32339 | MachOper *_opnd_array[2]; |
| 32340 | public: |
| 32341 | MachOper *opnd_array(uint operand_index) const { |
| 32342 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32343 | return _opnd_array[operand_index]; |
| 32344 | } |
| 32345 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32346 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32347 | _opnd_array[operand_index] = operand; |
| 32348 | } |
| 32349 | private: |
| 32350 | virtual const RegMask &out_RegMask() const; |
| 32351 | virtual uint rule() const { return Repl2S_rule; } |
| 32352 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32353 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32354 | virtual uint oper_input_base() const { return 1; } |
| 32355 | public: |
| 32356 | Repl2SNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32357 | virtual uint size_of() const { return sizeof(Repl2SNode); } |
| 32358 | static const Pipeline *pipeline_class(); |
| 32359 | virtual const Pipeline *pipeline() const; |
| 32360 | #ifndef PRODUCT |
| 32361 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32362 | virtual const char *Name() const { return "Repl2S";} |
| 32363 | #endif |
| 32364 | }; |
| 32365 | |
| 32366 | class Repl2S_immNode : public MachConstantNode { |
| 32367 | private: |
| 32368 | MachOper *_opnd_array[2]; |
| 32369 | public: |
| 32370 | MachOper *opnd_array(uint operand_index) const { |
| 32371 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32372 | return _opnd_array[operand_index]; |
| 32373 | } |
| 32374 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32375 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32376 | _opnd_array[operand_index] = operand; |
| 32377 | } |
| 32378 | private: |
| 32379 | virtual const RegMask &out_RegMask() const; |
| 32380 | virtual uint rule() const { return Repl2S_imm_rule; } |
| 32381 | virtual void eval_constant(Compile* C); |
| 32382 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32383 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32384 | virtual uint oper_input_base() const { return 1; } |
| 32385 | public: |
| 32386 | Repl2S_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32387 | virtual uint size_of() const { return sizeof(Repl2S_immNode); } |
| 32388 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32389 | static const Pipeline *pipeline_class(); |
| 32390 | virtual const Pipeline *pipeline() const; |
| 32391 | #ifndef PRODUCT |
| 32392 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32393 | virtual const char *Name() const { return "Repl2S_imm";} |
| 32394 | #endif |
| 32395 | }; |
| 32396 | |
| 32397 | class Repl4S_immNode : public MachConstantNode { |
| 32398 | private: |
| 32399 | MachOper *_opnd_array[2]; |
| 32400 | public: |
| 32401 | MachOper *opnd_array(uint operand_index) const { |
| 32402 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32403 | return _opnd_array[operand_index]; |
| 32404 | } |
| 32405 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32406 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32407 | _opnd_array[operand_index] = operand; |
| 32408 | } |
| 32409 | private: |
| 32410 | virtual const RegMask &out_RegMask() const; |
| 32411 | virtual uint rule() const { return Repl4S_imm_rule; } |
| 32412 | virtual void eval_constant(Compile* C); |
| 32413 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32414 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32415 | virtual uint oper_input_base() const { return 1; } |
| 32416 | public: |
| 32417 | Repl4S_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32418 | virtual uint size_of() const { return sizeof(Repl4S_immNode); } |
| 32419 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32420 | static const Pipeline *pipeline_class(); |
| 32421 | virtual const Pipeline *pipeline() const; |
| 32422 | #ifndef PRODUCT |
| 32423 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32424 | virtual const char *Name() const { return "Repl4S_imm";} |
| 32425 | #endif |
| 32426 | }; |
| 32427 | |
| 32428 | class Repl2S_zeroNode : public MachTypeNode { |
| 32429 | private: |
| 32430 | MachOper *_opnd_array[2]; |
| 32431 | public: |
| 32432 | MachOper *opnd_array(uint operand_index) const { |
| 32433 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32434 | return _opnd_array[operand_index]; |
| 32435 | } |
| 32436 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32437 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32438 | _opnd_array[operand_index] = operand; |
| 32439 | } |
| 32440 | private: |
| 32441 | virtual const RegMask &out_RegMask() const; |
| 32442 | virtual uint rule() const { return Repl2S_zero_rule; } |
| 32443 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32444 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32445 | virtual uint oper_input_base() const { return 1; } |
| 32446 | public: |
| 32447 | Repl2S_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32448 | virtual uint size_of() const { return sizeof(Repl2S_zeroNode); } |
| 32449 | static const Pipeline *pipeline_class(); |
| 32450 | virtual const Pipeline *pipeline() const; |
| 32451 | #ifndef PRODUCT |
| 32452 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32453 | virtual const char *Name() const { return "Repl2S_zero";} |
| 32454 | #endif |
| 32455 | }; |
| 32456 | |
| 32457 | class Repl4S_zeroNode : public MachTypeNode { |
| 32458 | private: |
| 32459 | MachOper *_opnd_array[2]; |
| 32460 | public: |
| 32461 | MachOper *opnd_array(uint operand_index) const { |
| 32462 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32463 | return _opnd_array[operand_index]; |
| 32464 | } |
| 32465 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32466 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32467 | _opnd_array[operand_index] = operand; |
| 32468 | } |
| 32469 | private: |
| 32470 | virtual const RegMask &out_RegMask() const; |
| 32471 | virtual uint rule() const { return Repl4S_zero_rule; } |
| 32472 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32473 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32474 | virtual uint oper_input_base() const { return 1; } |
| 32475 | public: |
| 32476 | Repl4S_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32477 | virtual uint size_of() const { return sizeof(Repl4S_zeroNode); } |
| 32478 | static const Pipeline *pipeline_class(); |
| 32479 | virtual const Pipeline *pipeline() const; |
| 32480 | #ifndef PRODUCT |
| 32481 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32482 | virtual const char *Name() const { return "Repl4S_zero";} |
| 32483 | #endif |
| 32484 | }; |
| 32485 | |
| 32486 | class Repl8S_zeroNode : public MachTypeNode { |
| 32487 | private: |
| 32488 | MachOper *_opnd_array[2]; |
| 32489 | public: |
| 32490 | MachOper *opnd_array(uint operand_index) const { |
| 32491 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32492 | return _opnd_array[operand_index]; |
| 32493 | } |
| 32494 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32495 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32496 | _opnd_array[operand_index] = operand; |
| 32497 | } |
| 32498 | private: |
| 32499 | virtual const RegMask &out_RegMask() const; |
| 32500 | virtual uint rule() const { return Repl8S_zero_rule; } |
| 32501 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32502 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32503 | virtual uint oper_input_base() const { return 1; } |
| 32504 | public: |
| 32505 | Repl8S_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32506 | virtual uint size_of() const { return sizeof(Repl8S_zeroNode); } |
| 32507 | static const Pipeline *pipeline_class(); |
| 32508 | virtual const Pipeline *pipeline() const; |
| 32509 | #ifndef PRODUCT |
| 32510 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32511 | virtual const char *Name() const { return "Repl8S_zero";} |
| 32512 | #endif |
| 32513 | }; |
| 32514 | |
| 32515 | class Repl16S_zeroNode : public MachTypeNode { |
| 32516 | private: |
| 32517 | MachOper *_opnd_array[2]; |
| 32518 | public: |
| 32519 | MachOper *opnd_array(uint operand_index) const { |
| 32520 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32521 | return _opnd_array[operand_index]; |
| 32522 | } |
| 32523 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32524 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32525 | _opnd_array[operand_index] = operand; |
| 32526 | } |
| 32527 | private: |
| 32528 | virtual const RegMask &out_RegMask() const; |
| 32529 | virtual uint rule() const { return Repl16S_zero_rule; } |
| 32530 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32531 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 32532 | virtual uint oper_input_base() const { return 1; } |
| 32533 | public: |
| 32534 | Repl16S_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32535 | virtual uint size_of() const { return sizeof(Repl16S_zeroNode); } |
| 32536 | static const Pipeline *pipeline_class(); |
| 32537 | virtual const Pipeline *pipeline() const; |
| 32538 | #ifndef PRODUCT |
| 32539 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32540 | virtual const char *Name() const { return "Repl16S_zero";} |
| 32541 | #endif |
| 32542 | }; |
| 32543 | |
| 32544 | class Repl2INode : public MachTypeNode { |
| 32545 | private: |
| 32546 | MachOper *_opnd_array[2]; |
| 32547 | public: |
| 32548 | MachOper *opnd_array(uint operand_index) const { |
| 32549 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32550 | return _opnd_array[operand_index]; |
| 32551 | } |
| 32552 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32553 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32554 | _opnd_array[operand_index] = operand; |
| 32555 | } |
| 32556 | private: |
| 32557 | const RegMask *_cisc_RegMask; |
| 32558 | virtual const RegMask &out_RegMask() const; |
| 32559 | virtual uint rule() const { return Repl2I_rule; } |
| 32560 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32561 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32562 | virtual int cisc_operand() const { return 1; } |
| 32563 | virtual MachNode *cisc_version(int offset); |
| 32564 | virtual void use_cisc_RegMask(); |
| 32565 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 32566 | virtual uint oper_input_base() const { return 1; } |
| 32567 | public: |
| 32568 | Repl2INode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 32569 | virtual uint size_of() const { return sizeof(Repl2INode); } |
| 32570 | static const Pipeline *pipeline_class(); |
| 32571 | virtual const Pipeline *pipeline() const; |
| 32572 | #ifndef PRODUCT |
| 32573 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32574 | virtual const char *Name() const { return "Repl2I";} |
| 32575 | #endif |
| 32576 | }; |
| 32577 | |
| 32578 | class Repl2I_memNode : public MachTypeNode { |
| 32579 | private: |
| 32580 | MachOper *_opnd_array[2]; |
| 32581 | public: |
| 32582 | MachOper *opnd_array(uint operand_index) const { |
| 32583 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32584 | return _opnd_array[operand_index]; |
| 32585 | } |
| 32586 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32587 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32588 | _opnd_array[operand_index] = operand; |
| 32589 | } |
| 32590 | private: |
| 32591 | virtual const RegMask &out_RegMask() const; |
| 32592 | virtual uint rule() const { return Repl2I_mem_rule; } |
| 32593 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32594 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32595 | virtual int reloc() const; |
| 32596 | virtual uint oper_input_base() const { return 2; } |
| 32597 | public: |
| 32598 | Repl2I_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 32599 | virtual uint size_of() const { return sizeof(Repl2I_memNode); } |
| 32600 | static const Pipeline *pipeline_class(); |
| 32601 | virtual const Pipeline *pipeline() const; |
| 32602 | virtual const MachOper *memory_operand() const; |
| 32603 | #ifndef PRODUCT |
| 32604 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32605 | virtual const char *Name() const { return "Repl2I_mem";} |
| 32606 | #endif |
| 32607 | }; |
| 32608 | |
| 32609 | class Repl2I_immNode : public MachConstantNode { |
| 32610 | private: |
| 32611 | MachOper *_opnd_array[2]; |
| 32612 | public: |
| 32613 | MachOper *opnd_array(uint operand_index) const { |
| 32614 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32615 | return _opnd_array[operand_index]; |
| 32616 | } |
| 32617 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32619 | _opnd_array[operand_index] = operand; |
| 32620 | } |
| 32621 | private: |
| 32622 | virtual const RegMask &out_RegMask() const; |
| 32623 | virtual uint rule() const { return Repl2I_imm_rule; } |
| 32624 | virtual void eval_constant(Compile* C); |
| 32625 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32626 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32627 | virtual uint oper_input_base() const { return 1; } |
| 32628 | public: |
| 32629 | Repl2I_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32630 | virtual uint size_of() const { return sizeof(Repl2I_immNode); } |
| 32631 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32632 | static const Pipeline *pipeline_class(); |
| 32633 | virtual const Pipeline *pipeline() const; |
| 32634 | #ifndef PRODUCT |
| 32635 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32636 | virtual const char *Name() const { return "Repl2I_imm";} |
| 32637 | #endif |
| 32638 | }; |
| 32639 | |
| 32640 | class Repl2I_zeroNode : public MachTypeNode { |
| 32641 | private: |
| 32642 | MachOper *_opnd_array[2]; |
| 32643 | public: |
| 32644 | MachOper *opnd_array(uint operand_index) const { |
| 32645 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32646 | return _opnd_array[operand_index]; |
| 32647 | } |
| 32648 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32649 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32650 | _opnd_array[operand_index] = operand; |
| 32651 | } |
| 32652 | private: |
| 32653 | virtual const RegMask &out_RegMask() const; |
| 32654 | virtual uint rule() const { return Repl2I_zero_rule; } |
| 32655 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32656 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32657 | virtual uint oper_input_base() const { return 1; } |
| 32658 | public: |
| 32659 | Repl2I_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32660 | virtual uint size_of() const { return sizeof(Repl2I_zeroNode); } |
| 32661 | static const Pipeline *pipeline_class(); |
| 32662 | virtual const Pipeline *pipeline() const; |
| 32663 | #ifndef PRODUCT |
| 32664 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32665 | virtual const char *Name() const { return "Repl2I_zero";} |
| 32666 | #endif |
| 32667 | }; |
| 32668 | |
| 32669 | class Repl4I_zeroNode : public MachTypeNode { |
| 32670 | private: |
| 32671 | MachOper *_opnd_array[2]; |
| 32672 | public: |
| 32673 | MachOper *opnd_array(uint operand_index) const { |
| 32674 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32675 | return _opnd_array[operand_index]; |
| 32676 | } |
| 32677 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32678 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32679 | _opnd_array[operand_index] = operand; |
| 32680 | } |
| 32681 | private: |
| 32682 | virtual const RegMask &out_RegMask() const; |
| 32683 | virtual uint rule() const { return Repl4I_zero_rule; } |
| 32684 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32685 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32686 | virtual uint oper_input_base() const { return 1; } |
| 32687 | public: |
| 32688 | Repl4I_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32689 | virtual uint size_of() const { return sizeof(Repl4I_zeroNode); } |
| 32690 | static const Pipeline *pipeline_class(); |
| 32691 | virtual const Pipeline *pipeline() const; |
| 32692 | #ifndef PRODUCT |
| 32693 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32694 | virtual const char *Name() const { return "Repl4I_zero";} |
| 32695 | #endif |
| 32696 | }; |
| 32697 | |
| 32698 | class Repl8I_zeroNode : public MachTypeNode { |
| 32699 | private: |
| 32700 | MachOper *_opnd_array[2]; |
| 32701 | public: |
| 32702 | MachOper *opnd_array(uint operand_index) const { |
| 32703 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32704 | return _opnd_array[operand_index]; |
| 32705 | } |
| 32706 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32707 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32708 | _opnd_array[operand_index] = operand; |
| 32709 | } |
| 32710 | private: |
| 32711 | virtual const RegMask &out_RegMask() const; |
| 32712 | virtual uint rule() const { return Repl8I_zero_rule; } |
| 32713 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32714 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 32715 | virtual uint oper_input_base() const { return 1; } |
| 32716 | public: |
| 32717 | Repl8I_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32718 | virtual uint size_of() const { return sizeof(Repl8I_zeroNode); } |
| 32719 | static const Pipeline *pipeline_class(); |
| 32720 | virtual const Pipeline *pipeline() const; |
| 32721 | #ifndef PRODUCT |
| 32722 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32723 | virtual const char *Name() const { return "Repl8I_zero";} |
| 32724 | #endif |
| 32725 | }; |
| 32726 | |
| 32727 | class Repl2LNode : public MachTypeNode { |
| 32728 | private: |
| 32729 | MachOper *_opnd_array[2]; |
| 32730 | public: |
| 32731 | MachOper *opnd_array(uint operand_index) const { |
| 32732 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32733 | return _opnd_array[operand_index]; |
| 32734 | } |
| 32735 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32736 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32737 | _opnd_array[operand_index] = operand; |
| 32738 | } |
| 32739 | private: |
| 32740 | virtual const RegMask &out_RegMask() const; |
| 32741 | virtual uint rule() const { return Repl2L_rule; } |
| 32742 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32743 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 32744 | virtual uint oper_input_base() const { return 1; } |
| 32745 | public: |
| 32746 | Repl2LNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32747 | virtual uint size_of() const { return sizeof(Repl2LNode); } |
| 32748 | static const Pipeline *pipeline_class(); |
| 32749 | virtual const Pipeline *pipeline() const; |
| 32750 | #ifndef PRODUCT |
| 32751 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32752 | virtual const char *Name() const { return "Repl2L";} |
| 32753 | #endif |
| 32754 | }; |
| 32755 | |
| 32756 | class Repl2L_immNode : public MachConstantNode { |
| 32757 | private: |
| 32758 | MachOper *_opnd_array[2]; |
| 32759 | public: |
| 32760 | MachOper *opnd_array(uint operand_index) const { |
| 32761 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32762 | return _opnd_array[operand_index]; |
| 32763 | } |
| 32764 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32765 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32766 | _opnd_array[operand_index] = operand; |
| 32767 | } |
| 32768 | private: |
| 32769 | virtual const RegMask &out_RegMask() const; |
| 32770 | virtual uint rule() const { return Repl2L_imm_rule; } |
| 32771 | virtual void eval_constant(Compile* C); |
| 32772 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32773 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 32774 | virtual uint oper_input_base() const { return 1; } |
| 32775 | public: |
| 32776 | Repl2L_immNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32777 | virtual uint size_of() const { return sizeof(Repl2L_immNode); } |
| 32778 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 32779 | static const Pipeline *pipeline_class(); |
| 32780 | virtual const Pipeline *pipeline() const; |
| 32781 | #ifndef PRODUCT |
| 32782 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32783 | virtual const char *Name() const { return "Repl2L_imm";} |
| 32784 | #endif |
| 32785 | }; |
| 32786 | |
| 32787 | class Repl2L_zeroNode : public MachTypeNode { |
| 32788 | private: |
| 32789 | MachOper *_opnd_array[2]; |
| 32790 | public: |
| 32791 | MachOper *opnd_array(uint operand_index) const { |
| 32792 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32793 | return _opnd_array[operand_index]; |
| 32794 | } |
| 32795 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32797 | _opnd_array[operand_index] = operand; |
| 32798 | } |
| 32799 | private: |
| 32800 | virtual const RegMask &out_RegMask() const; |
| 32801 | virtual uint rule() const { return Repl2L_zero_rule; } |
| 32802 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32803 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 32804 | virtual uint oper_input_base() const { return 1; } |
| 32805 | public: |
| 32806 | Repl2L_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32807 | virtual uint size_of() const { return sizeof(Repl2L_zeroNode); } |
| 32808 | static const Pipeline *pipeline_class(); |
| 32809 | virtual const Pipeline *pipeline() const; |
| 32810 | #ifndef PRODUCT |
| 32811 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32812 | virtual const char *Name() const { return "Repl2L_zero";} |
| 32813 | #endif |
| 32814 | }; |
| 32815 | |
| 32816 | class Repl4L_zeroNode : public MachTypeNode { |
| 32817 | private: |
| 32818 | MachOper *_opnd_array[2]; |
| 32819 | public: |
| 32820 | MachOper *opnd_array(uint operand_index) const { |
| 32821 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32822 | return _opnd_array[operand_index]; |
| 32823 | } |
| 32824 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32825 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32826 | _opnd_array[operand_index] = operand; |
| 32827 | } |
| 32828 | private: |
| 32829 | virtual const RegMask &out_RegMask() const; |
| 32830 | virtual uint rule() const { return Repl4L_zero_rule; } |
| 32831 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32832 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 32833 | virtual uint oper_input_base() const { return 1; } |
| 32834 | public: |
| 32835 | Repl4L_zeroNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32836 | virtual uint size_of() const { return sizeof(Repl4L_zeroNode); } |
| 32837 | static const Pipeline *pipeline_class(); |
| 32838 | virtual const Pipeline *pipeline() const; |
| 32839 | #ifndef PRODUCT |
| 32840 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32841 | virtual const char *Name() const { return "Repl4L_zero";} |
| 32842 | #endif |
| 32843 | }; |
| 32844 | |
| 32845 | class Repl2FNode : public MachTypeNode { |
| 32846 | private: |
| 32847 | MachOper *_opnd_array[2]; |
| 32848 | public: |
| 32849 | MachOper *opnd_array(uint operand_index) const { |
| 32850 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32851 | return _opnd_array[operand_index]; |
| 32852 | } |
| 32853 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32854 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32855 | _opnd_array[operand_index] = operand; |
| 32856 | } |
| 32857 | private: |
| 32858 | virtual const RegMask &out_RegMask() const; |
| 32859 | virtual uint rule() const { return Repl2F_rule; } |
| 32860 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32861 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 32862 | virtual uint oper_input_base() const { return 1; } |
| 32863 | public: |
| 32864 | Repl2FNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32865 | virtual uint size_of() const { return sizeof(Repl2FNode); } |
| 32866 | static const Pipeline *pipeline_class(); |
| 32867 | virtual const Pipeline *pipeline() const; |
| 32868 | #ifndef PRODUCT |
| 32869 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32870 | virtual const char *Name() const { return "Repl2F";} |
| 32871 | #endif |
| 32872 | }; |
| 32873 | |
| 32874 | class Repl4FNode : public MachTypeNode { |
| 32875 | private: |
| 32876 | MachOper *_opnd_array[2]; |
| 32877 | public: |
| 32878 | MachOper *opnd_array(uint operand_index) const { |
| 32879 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32880 | return _opnd_array[operand_index]; |
| 32881 | } |
| 32882 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32883 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32884 | _opnd_array[operand_index] = operand; |
| 32885 | } |
| 32886 | private: |
| 32887 | virtual const RegMask &out_RegMask() const; |
| 32888 | virtual uint rule() const { return Repl4F_rule; } |
| 32889 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32890 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 32891 | virtual uint oper_input_base() const { return 1; } |
| 32892 | public: |
| 32893 | Repl4FNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32894 | virtual uint size_of() const { return sizeof(Repl4FNode); } |
| 32895 | static const Pipeline *pipeline_class(); |
| 32896 | virtual const Pipeline *pipeline() const; |
| 32897 | #ifndef PRODUCT |
| 32898 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32899 | virtual const char *Name() const { return "Repl4F";} |
| 32900 | #endif |
| 32901 | }; |
| 32902 | |
| 32903 | class Repl2DNode : public MachTypeNode { |
| 32904 | private: |
| 32905 | MachOper *_opnd_array[2]; |
| 32906 | public: |
| 32907 | MachOper *opnd_array(uint operand_index) const { |
| 32908 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32909 | return _opnd_array[operand_index]; |
| 32910 | } |
| 32911 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32912 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32913 | _opnd_array[operand_index] = operand; |
| 32914 | } |
| 32915 | private: |
| 32916 | virtual const RegMask &out_RegMask() const; |
| 32917 | virtual uint rule() const { return Repl2D_rule; } |
| 32918 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32919 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 32920 | virtual uint oper_input_base() const { return 1; } |
| 32921 | public: |
| 32922 | Repl2DNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 32923 | virtual uint size_of() const { return sizeof(Repl2DNode); } |
| 32924 | static const Pipeline *pipeline_class(); |
| 32925 | virtual const Pipeline *pipeline() const; |
| 32926 | #ifndef PRODUCT |
| 32927 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32928 | virtual const char *Name() const { return "Repl2D";} |
| 32929 | #endif |
| 32930 | }; |
| 32931 | |
| 32932 | class Repl4B_mem_evexNode : public MachTypeNode { |
| 32933 | private: |
| 32934 | MachOper *_opnd_array[2]; |
| 32935 | public: |
| 32936 | MachOper *opnd_array(uint operand_index) const { |
| 32937 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32938 | return _opnd_array[operand_index]; |
| 32939 | } |
| 32940 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32941 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32942 | _opnd_array[operand_index] = operand; |
| 32943 | } |
| 32944 | private: |
| 32945 | virtual const RegMask &out_RegMask() const; |
| 32946 | virtual uint rule() const { return Repl4B_mem_evex_rule; } |
| 32947 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32948 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32949 | virtual int reloc() const; |
| 32950 | virtual uint oper_input_base() const { return 2; } |
| 32951 | public: |
| 32952 | Repl4B_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 32953 | virtual uint size_of() const { return sizeof(Repl4B_mem_evexNode); } |
| 32954 | static const Pipeline *pipeline_class(); |
| 32955 | virtual const Pipeline *pipeline() const; |
| 32956 | virtual const MachOper *memory_operand() const; |
| 32957 | #ifndef PRODUCT |
| 32958 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32959 | virtual const char *Name() const { return "Repl4B_mem_evex";} |
| 32960 | #endif |
| 32961 | }; |
| 32962 | |
| 32963 | class Repl8B_mem_evexNode : public MachTypeNode { |
| 32964 | private: |
| 32965 | MachOper *_opnd_array[2]; |
| 32966 | public: |
| 32967 | MachOper *opnd_array(uint operand_index) const { |
| 32968 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32969 | return _opnd_array[operand_index]; |
| 32970 | } |
| 32971 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 32972 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 32973 | _opnd_array[operand_index] = operand; |
| 32974 | } |
| 32975 | private: |
| 32976 | virtual const RegMask &out_RegMask() const; |
| 32977 | virtual uint rule() const { return Repl8B_mem_evex_rule; } |
| 32978 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 32979 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 32980 | virtual int reloc() const; |
| 32981 | virtual uint oper_input_base() const { return 2; } |
| 32982 | public: |
| 32983 | Repl8B_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 32984 | virtual uint size_of() const { return sizeof(Repl8B_mem_evexNode); } |
| 32985 | static const Pipeline *pipeline_class(); |
| 32986 | virtual const Pipeline *pipeline() const; |
| 32987 | virtual const MachOper *memory_operand() const; |
| 32988 | #ifndef PRODUCT |
| 32989 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 32990 | virtual const char *Name() const { return "Repl8B_mem_evex";} |
| 32991 | #endif |
| 32992 | }; |
| 32993 | |
| 32994 | class Repl16B_evexNode : public MachTypeNode { |
| 32995 | private: |
| 32996 | MachOper *_opnd_array[2]; |
| 32997 | public: |
| 32998 | MachOper *opnd_array(uint operand_index) const { |
| 32999 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33000 | return _opnd_array[operand_index]; |
| 33001 | } |
| 33002 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33003 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33004 | _opnd_array[operand_index] = operand; |
| 33005 | } |
| 33006 | private: |
| 33007 | virtual const RegMask &out_RegMask() const; |
| 33008 | virtual uint rule() const { return Repl16B_evex_rule; } |
| 33009 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33010 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33011 | virtual uint oper_input_base() const { return 1; } |
| 33012 | public: |
| 33013 | Repl16B_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33014 | virtual uint size_of() const { return sizeof(Repl16B_evexNode); } |
| 33015 | static const Pipeline *pipeline_class(); |
| 33016 | virtual const Pipeline *pipeline() const; |
| 33017 | #ifndef PRODUCT |
| 33018 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33019 | virtual const char *Name() const { return "Repl16B_evex";} |
| 33020 | #endif |
| 33021 | }; |
| 33022 | |
| 33023 | class Repl16B_mem_evexNode : public MachTypeNode { |
| 33024 | private: |
| 33025 | MachOper *_opnd_array[2]; |
| 33026 | public: |
| 33027 | MachOper *opnd_array(uint operand_index) const { |
| 33028 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33029 | return _opnd_array[operand_index]; |
| 33030 | } |
| 33031 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33032 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33033 | _opnd_array[operand_index] = operand; |
| 33034 | } |
| 33035 | private: |
| 33036 | virtual const RegMask &out_RegMask() const; |
| 33037 | virtual uint rule() const { return Repl16B_mem_evex_rule; } |
| 33038 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33039 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33040 | virtual int reloc() const; |
| 33041 | virtual uint oper_input_base() const { return 2; } |
| 33042 | public: |
| 33043 | Repl16B_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33044 | virtual uint size_of() const { return sizeof(Repl16B_mem_evexNode); } |
| 33045 | static const Pipeline *pipeline_class(); |
| 33046 | virtual const Pipeline *pipeline() const; |
| 33047 | virtual const MachOper *memory_operand() const; |
| 33048 | #ifndef PRODUCT |
| 33049 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33050 | virtual const char *Name() const { return "Repl16B_mem_evex";} |
| 33051 | #endif |
| 33052 | }; |
| 33053 | |
| 33054 | class Repl32B_evexNode : public MachTypeNode { |
| 33055 | private: |
| 33056 | MachOper *_opnd_array[2]; |
| 33057 | public: |
| 33058 | MachOper *opnd_array(uint operand_index) const { |
| 33059 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33060 | return _opnd_array[operand_index]; |
| 33061 | } |
| 33062 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33063 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33064 | _opnd_array[operand_index] = operand; |
| 33065 | } |
| 33066 | private: |
| 33067 | virtual const RegMask &out_RegMask() const; |
| 33068 | virtual uint rule() const { return Repl32B_evex_rule; } |
| 33069 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33070 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33071 | virtual uint oper_input_base() const { return 1; } |
| 33072 | public: |
| 33073 | Repl32B_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33074 | virtual uint size_of() const { return sizeof(Repl32B_evexNode); } |
| 33075 | static const Pipeline *pipeline_class(); |
| 33076 | virtual const Pipeline *pipeline() const; |
| 33077 | #ifndef PRODUCT |
| 33078 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33079 | virtual const char *Name() const { return "Repl32B_evex";} |
| 33080 | #endif |
| 33081 | }; |
| 33082 | |
| 33083 | class Repl32B_mem_evexNode : public MachTypeNode { |
| 33084 | private: |
| 33085 | MachOper *_opnd_array[2]; |
| 33086 | public: |
| 33087 | MachOper *opnd_array(uint operand_index) const { |
| 33088 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33089 | return _opnd_array[operand_index]; |
| 33090 | } |
| 33091 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33092 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33093 | _opnd_array[operand_index] = operand; |
| 33094 | } |
| 33095 | private: |
| 33096 | virtual const RegMask &out_RegMask() const; |
| 33097 | virtual uint rule() const { return Repl32B_mem_evex_rule; } |
| 33098 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33099 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33100 | virtual int reloc() const; |
| 33101 | virtual uint oper_input_base() const { return 2; } |
| 33102 | public: |
| 33103 | Repl32B_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33104 | virtual uint size_of() const { return sizeof(Repl32B_mem_evexNode); } |
| 33105 | static const Pipeline *pipeline_class(); |
| 33106 | virtual const Pipeline *pipeline() const; |
| 33107 | virtual const MachOper *memory_operand() const; |
| 33108 | #ifndef PRODUCT |
| 33109 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33110 | virtual const char *Name() const { return "Repl32B_mem_evex";} |
| 33111 | #endif |
| 33112 | }; |
| 33113 | |
| 33114 | class Repl64B_evexNode : public MachTypeNode { |
| 33115 | private: |
| 33116 | MachOper *_opnd_array[2]; |
| 33117 | public: |
| 33118 | MachOper *opnd_array(uint operand_index) const { |
| 33119 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33120 | return _opnd_array[operand_index]; |
| 33121 | } |
| 33122 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33123 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33124 | _opnd_array[operand_index] = operand; |
| 33125 | } |
| 33126 | private: |
| 33127 | virtual const RegMask &out_RegMask() const; |
| 33128 | virtual uint rule() const { return Repl64B_evex_rule; } |
| 33129 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33130 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33131 | virtual uint oper_input_base() const { return 1; } |
| 33132 | public: |
| 33133 | Repl64B_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33134 | virtual uint size_of() const { return sizeof(Repl64B_evexNode); } |
| 33135 | static const Pipeline *pipeline_class(); |
| 33136 | virtual const Pipeline *pipeline() const; |
| 33137 | #ifndef PRODUCT |
| 33138 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33139 | virtual const char *Name() const { return "Repl64B_evex";} |
| 33140 | #endif |
| 33141 | }; |
| 33142 | |
| 33143 | class Repl64B_mem_evexNode : public MachTypeNode { |
| 33144 | private: |
| 33145 | MachOper *_opnd_array[2]; |
| 33146 | public: |
| 33147 | MachOper *opnd_array(uint operand_index) const { |
| 33148 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33149 | return _opnd_array[operand_index]; |
| 33150 | } |
| 33151 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33152 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33153 | _opnd_array[operand_index] = operand; |
| 33154 | } |
| 33155 | private: |
| 33156 | virtual const RegMask &out_RegMask() const; |
| 33157 | virtual uint rule() const { return Repl64B_mem_evex_rule; } |
| 33158 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33159 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33160 | virtual int reloc() const; |
| 33161 | virtual uint oper_input_base() const { return 2; } |
| 33162 | public: |
| 33163 | Repl64B_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33164 | virtual uint size_of() const { return sizeof(Repl64B_mem_evexNode); } |
| 33165 | static const Pipeline *pipeline_class(); |
| 33166 | virtual const Pipeline *pipeline() const; |
| 33167 | virtual const MachOper *memory_operand() const; |
| 33168 | #ifndef PRODUCT |
| 33169 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33170 | virtual const char *Name() const { return "Repl64B_mem_evex";} |
| 33171 | #endif |
| 33172 | }; |
| 33173 | |
| 33174 | class Repl16B_imm_evexNode : public MachConstantNode { |
| 33175 | private: |
| 33176 | MachOper *_opnd_array[2]; |
| 33177 | public: |
| 33178 | MachOper *opnd_array(uint operand_index) const { |
| 33179 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33180 | return _opnd_array[operand_index]; |
| 33181 | } |
| 33182 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33183 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33184 | _opnd_array[operand_index] = operand; |
| 33185 | } |
| 33186 | private: |
| 33187 | virtual const RegMask &out_RegMask() const; |
| 33188 | virtual uint rule() const { return Repl16B_imm_evex_rule; } |
| 33189 | virtual void eval_constant(Compile* C); |
| 33190 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33191 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33192 | virtual uint oper_input_base() const { return 1; } |
| 33193 | public: |
| 33194 | Repl16B_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33195 | virtual uint size_of() const { return sizeof(Repl16B_imm_evexNode); } |
| 33196 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33197 | static const Pipeline *pipeline_class(); |
| 33198 | virtual const Pipeline *pipeline() const; |
| 33199 | #ifndef PRODUCT |
| 33200 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33201 | virtual const char *Name() const { return "Repl16B_imm_evex";} |
| 33202 | #endif |
| 33203 | }; |
| 33204 | |
| 33205 | class Repl32B_imm_evexNode : public MachConstantNode { |
| 33206 | private: |
| 33207 | MachOper *_opnd_array[2]; |
| 33208 | public: |
| 33209 | MachOper *opnd_array(uint operand_index) const { |
| 33210 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33211 | return _opnd_array[operand_index]; |
| 33212 | } |
| 33213 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33214 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33215 | _opnd_array[operand_index] = operand; |
| 33216 | } |
| 33217 | private: |
| 33218 | virtual const RegMask &out_RegMask() const; |
| 33219 | virtual uint rule() const { return Repl32B_imm_evex_rule; } |
| 33220 | virtual void eval_constant(Compile* C); |
| 33221 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33222 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33223 | virtual uint oper_input_base() const { return 1; } |
| 33224 | public: |
| 33225 | Repl32B_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33226 | virtual uint size_of() const { return sizeof(Repl32B_imm_evexNode); } |
| 33227 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33228 | static const Pipeline *pipeline_class(); |
| 33229 | virtual const Pipeline *pipeline() const; |
| 33230 | #ifndef PRODUCT |
| 33231 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33232 | virtual const char *Name() const { return "Repl32B_imm_evex";} |
| 33233 | #endif |
| 33234 | }; |
| 33235 | |
| 33236 | class Repl64B_imm_evexNode : public MachConstantNode { |
| 33237 | private: |
| 33238 | MachOper *_opnd_array[2]; |
| 33239 | public: |
| 33240 | MachOper *opnd_array(uint operand_index) const { |
| 33241 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33242 | return _opnd_array[operand_index]; |
| 33243 | } |
| 33244 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33245 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33246 | _opnd_array[operand_index] = operand; |
| 33247 | } |
| 33248 | private: |
| 33249 | virtual const RegMask &out_RegMask() const; |
| 33250 | virtual uint rule() const { return Repl64B_imm_evex_rule; } |
| 33251 | virtual void eval_constant(Compile* C); |
| 33252 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33253 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33254 | virtual uint oper_input_base() const { return 1; } |
| 33255 | public: |
| 33256 | Repl64B_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33257 | virtual uint size_of() const { return sizeof(Repl64B_imm_evexNode); } |
| 33258 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33259 | static const Pipeline *pipeline_class(); |
| 33260 | virtual const Pipeline *pipeline() const; |
| 33261 | #ifndef PRODUCT |
| 33262 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33263 | virtual const char *Name() const { return "Repl64B_imm_evex";} |
| 33264 | #endif |
| 33265 | }; |
| 33266 | |
| 33267 | class Repl64B_zero_evexNode : public MachTypeNode { |
| 33268 | private: |
| 33269 | MachOper *_opnd_array[2]; |
| 33270 | public: |
| 33271 | MachOper *opnd_array(uint operand_index) const { |
| 33272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33273 | return _opnd_array[operand_index]; |
| 33274 | } |
| 33275 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33276 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33277 | _opnd_array[operand_index] = operand; |
| 33278 | } |
| 33279 | private: |
| 33280 | virtual const RegMask &out_RegMask() const; |
| 33281 | virtual uint rule() const { return Repl64B_zero_evex_rule; } |
| 33282 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33283 | virtual int ideal_Opcode() const { return Op_ReplicateB; } |
| 33284 | virtual uint oper_input_base() const { return 1; } |
| 33285 | public: |
| 33286 | Repl64B_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33287 | virtual uint size_of() const { return sizeof(Repl64B_zero_evexNode); } |
| 33288 | static const Pipeline *pipeline_class(); |
| 33289 | virtual const Pipeline *pipeline() const; |
| 33290 | #ifndef PRODUCT |
| 33291 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33292 | virtual const char *Name() const { return "Repl64B_zero_evex";} |
| 33293 | #endif |
| 33294 | }; |
| 33295 | |
| 33296 | class Repl4S_evexNode : public MachTypeNode { |
| 33297 | private: |
| 33298 | MachOper *_opnd_array[2]; |
| 33299 | public: |
| 33300 | MachOper *opnd_array(uint operand_index) const { |
| 33301 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33302 | return _opnd_array[operand_index]; |
| 33303 | } |
| 33304 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33305 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33306 | _opnd_array[operand_index] = operand; |
| 33307 | } |
| 33308 | private: |
| 33309 | virtual const RegMask &out_RegMask() const; |
| 33310 | virtual uint rule() const { return Repl4S_evex_rule; } |
| 33311 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33312 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33313 | virtual uint oper_input_base() const { return 1; } |
| 33314 | public: |
| 33315 | Repl4S_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33316 | virtual uint size_of() const { return sizeof(Repl4S_evexNode); } |
| 33317 | static const Pipeline *pipeline_class(); |
| 33318 | virtual const Pipeline *pipeline() const; |
| 33319 | #ifndef PRODUCT |
| 33320 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33321 | virtual const char *Name() const { return "Repl4S_evex";} |
| 33322 | #endif |
| 33323 | }; |
| 33324 | |
| 33325 | class Repl4S_mem_evexNode : public MachTypeNode { |
| 33326 | private: |
| 33327 | MachOper *_opnd_array[2]; |
| 33328 | public: |
| 33329 | MachOper *opnd_array(uint operand_index) const { |
| 33330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33331 | return _opnd_array[operand_index]; |
| 33332 | } |
| 33333 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33334 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33335 | _opnd_array[operand_index] = operand; |
| 33336 | } |
| 33337 | private: |
| 33338 | virtual const RegMask &out_RegMask() const; |
| 33339 | virtual uint rule() const { return Repl4S_mem_evex_rule; } |
| 33340 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33341 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33342 | virtual int reloc() const; |
| 33343 | virtual uint oper_input_base() const { return 2; } |
| 33344 | public: |
| 33345 | Repl4S_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33346 | virtual uint size_of() const { return sizeof(Repl4S_mem_evexNode); } |
| 33347 | static const Pipeline *pipeline_class(); |
| 33348 | virtual const Pipeline *pipeline() const; |
| 33349 | virtual const MachOper *memory_operand() const; |
| 33350 | #ifndef PRODUCT |
| 33351 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33352 | virtual const char *Name() const { return "Repl4S_mem_evex";} |
| 33353 | #endif |
| 33354 | }; |
| 33355 | |
| 33356 | class Repl8S_evexNode : public MachTypeNode { |
| 33357 | private: |
| 33358 | MachOper *_opnd_array[2]; |
| 33359 | public: |
| 33360 | MachOper *opnd_array(uint operand_index) const { |
| 33361 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33362 | return _opnd_array[operand_index]; |
| 33363 | } |
| 33364 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33365 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33366 | _opnd_array[operand_index] = operand; |
| 33367 | } |
| 33368 | private: |
| 33369 | virtual const RegMask &out_RegMask() const; |
| 33370 | virtual uint rule() const { return Repl8S_evex_rule; } |
| 33371 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33372 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33373 | virtual uint oper_input_base() const { return 1; } |
| 33374 | public: |
| 33375 | Repl8S_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33376 | virtual uint size_of() const { return sizeof(Repl8S_evexNode); } |
| 33377 | static const Pipeline *pipeline_class(); |
| 33378 | virtual const Pipeline *pipeline() const; |
| 33379 | #ifndef PRODUCT |
| 33380 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33381 | virtual const char *Name() const { return "Repl8S_evex";} |
| 33382 | #endif |
| 33383 | }; |
| 33384 | |
| 33385 | class Repl8S_mem_evexNode : public MachTypeNode { |
| 33386 | private: |
| 33387 | MachOper *_opnd_array[2]; |
| 33388 | public: |
| 33389 | MachOper *opnd_array(uint operand_index) const { |
| 33390 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33391 | return _opnd_array[operand_index]; |
| 33392 | } |
| 33393 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33395 | _opnd_array[operand_index] = operand; |
| 33396 | } |
| 33397 | private: |
| 33398 | virtual const RegMask &out_RegMask() const; |
| 33399 | virtual uint rule() const { return Repl8S_mem_evex_rule; } |
| 33400 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33401 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33402 | virtual int reloc() const; |
| 33403 | virtual uint oper_input_base() const { return 2; } |
| 33404 | public: |
| 33405 | Repl8S_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33406 | virtual uint size_of() const { return sizeof(Repl8S_mem_evexNode); } |
| 33407 | static const Pipeline *pipeline_class(); |
| 33408 | virtual const Pipeline *pipeline() const; |
| 33409 | virtual const MachOper *memory_operand() const; |
| 33410 | #ifndef PRODUCT |
| 33411 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33412 | virtual const char *Name() const { return "Repl8S_mem_evex";} |
| 33413 | #endif |
| 33414 | }; |
| 33415 | |
| 33416 | class Repl16S_evexNode : public MachTypeNode { |
| 33417 | private: |
| 33418 | MachOper *_opnd_array[2]; |
| 33419 | public: |
| 33420 | MachOper *opnd_array(uint operand_index) const { |
| 33421 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33422 | return _opnd_array[operand_index]; |
| 33423 | } |
| 33424 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33425 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33426 | _opnd_array[operand_index] = operand; |
| 33427 | } |
| 33428 | private: |
| 33429 | virtual const RegMask &out_RegMask() const; |
| 33430 | virtual uint rule() const { return Repl16S_evex_rule; } |
| 33431 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33432 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33433 | virtual uint oper_input_base() const { return 1; } |
| 33434 | public: |
| 33435 | Repl16S_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33436 | virtual uint size_of() const { return sizeof(Repl16S_evexNode); } |
| 33437 | static const Pipeline *pipeline_class(); |
| 33438 | virtual const Pipeline *pipeline() const; |
| 33439 | #ifndef PRODUCT |
| 33440 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33441 | virtual const char *Name() const { return "Repl16S_evex";} |
| 33442 | #endif |
| 33443 | }; |
| 33444 | |
| 33445 | class Repl16S_mem_evexNode : public MachTypeNode { |
| 33446 | private: |
| 33447 | MachOper *_opnd_array[2]; |
| 33448 | public: |
| 33449 | MachOper *opnd_array(uint operand_index) const { |
| 33450 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33451 | return _opnd_array[operand_index]; |
| 33452 | } |
| 33453 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33454 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33455 | _opnd_array[operand_index] = operand; |
| 33456 | } |
| 33457 | private: |
| 33458 | virtual const RegMask &out_RegMask() const; |
| 33459 | virtual uint rule() const { return Repl16S_mem_evex_rule; } |
| 33460 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33461 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33462 | virtual int reloc() const; |
| 33463 | virtual uint oper_input_base() const { return 2; } |
| 33464 | public: |
| 33465 | Repl16S_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33466 | virtual uint size_of() const { return sizeof(Repl16S_mem_evexNode); } |
| 33467 | static const Pipeline *pipeline_class(); |
| 33468 | virtual const Pipeline *pipeline() const; |
| 33469 | virtual const MachOper *memory_operand() const; |
| 33470 | #ifndef PRODUCT |
| 33471 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33472 | virtual const char *Name() const { return "Repl16S_mem_evex";} |
| 33473 | #endif |
| 33474 | }; |
| 33475 | |
| 33476 | class Repl32S_evexNode : public MachTypeNode { |
| 33477 | private: |
| 33478 | MachOper *_opnd_array[2]; |
| 33479 | public: |
| 33480 | MachOper *opnd_array(uint operand_index) const { |
| 33481 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33482 | return _opnd_array[operand_index]; |
| 33483 | } |
| 33484 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33485 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33486 | _opnd_array[operand_index] = operand; |
| 33487 | } |
| 33488 | private: |
| 33489 | virtual const RegMask &out_RegMask() const; |
| 33490 | virtual uint rule() const { return Repl32S_evex_rule; } |
| 33491 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33492 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33493 | virtual uint oper_input_base() const { return 1; } |
| 33494 | public: |
| 33495 | Repl32S_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33496 | virtual uint size_of() const { return sizeof(Repl32S_evexNode); } |
| 33497 | static const Pipeline *pipeline_class(); |
| 33498 | virtual const Pipeline *pipeline() const; |
| 33499 | #ifndef PRODUCT |
| 33500 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33501 | virtual const char *Name() const { return "Repl32S_evex";} |
| 33502 | #endif |
| 33503 | }; |
| 33504 | |
| 33505 | class Repl32S_mem_evexNode : public MachTypeNode { |
| 33506 | private: |
| 33507 | MachOper *_opnd_array[2]; |
| 33508 | public: |
| 33509 | MachOper *opnd_array(uint operand_index) const { |
| 33510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33511 | return _opnd_array[operand_index]; |
| 33512 | } |
| 33513 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33514 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33515 | _opnd_array[operand_index] = operand; |
| 33516 | } |
| 33517 | private: |
| 33518 | virtual const RegMask &out_RegMask() const; |
| 33519 | virtual uint rule() const { return Repl32S_mem_evex_rule; } |
| 33520 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33521 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33522 | virtual int reloc() const; |
| 33523 | virtual uint oper_input_base() const { return 2; } |
| 33524 | public: |
| 33525 | Repl32S_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 33526 | virtual uint size_of() const { return sizeof(Repl32S_mem_evexNode); } |
| 33527 | static const Pipeline *pipeline_class(); |
| 33528 | virtual const Pipeline *pipeline() const; |
| 33529 | virtual const MachOper *memory_operand() const; |
| 33530 | #ifndef PRODUCT |
| 33531 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33532 | virtual const char *Name() const { return "Repl32S_mem_evex";} |
| 33533 | #endif |
| 33534 | }; |
| 33535 | |
| 33536 | class Repl8S_imm_evexNode : public MachConstantNode { |
| 33537 | private: |
| 33538 | MachOper *_opnd_array[2]; |
| 33539 | public: |
| 33540 | MachOper *opnd_array(uint operand_index) const { |
| 33541 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33542 | return _opnd_array[operand_index]; |
| 33543 | } |
| 33544 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33545 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33546 | _opnd_array[operand_index] = operand; |
| 33547 | } |
| 33548 | private: |
| 33549 | virtual const RegMask &out_RegMask() const; |
| 33550 | virtual uint rule() const { return Repl8S_imm_evex_rule; } |
| 33551 | virtual void eval_constant(Compile* C); |
| 33552 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33553 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33554 | virtual uint oper_input_base() const { return 1; } |
| 33555 | public: |
| 33556 | Repl8S_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33557 | virtual uint size_of() const { return sizeof(Repl8S_imm_evexNode); } |
| 33558 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33559 | static const Pipeline *pipeline_class(); |
| 33560 | virtual const Pipeline *pipeline() const; |
| 33561 | #ifndef PRODUCT |
| 33562 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33563 | virtual const char *Name() const { return "Repl8S_imm_evex";} |
| 33564 | #endif |
| 33565 | }; |
| 33566 | |
| 33567 | class Repl16S_imm_evexNode : public MachConstantNode { |
| 33568 | private: |
| 33569 | MachOper *_opnd_array[2]; |
| 33570 | public: |
| 33571 | MachOper *opnd_array(uint operand_index) const { |
| 33572 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33573 | return _opnd_array[operand_index]; |
| 33574 | } |
| 33575 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33576 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33577 | _opnd_array[operand_index] = operand; |
| 33578 | } |
| 33579 | private: |
| 33580 | virtual const RegMask &out_RegMask() const; |
| 33581 | virtual uint rule() const { return Repl16S_imm_evex_rule; } |
| 33582 | virtual void eval_constant(Compile* C); |
| 33583 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33584 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33585 | virtual uint oper_input_base() const { return 1; } |
| 33586 | public: |
| 33587 | Repl16S_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33588 | virtual uint size_of() const { return sizeof(Repl16S_imm_evexNode); } |
| 33589 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33590 | static const Pipeline *pipeline_class(); |
| 33591 | virtual const Pipeline *pipeline() const; |
| 33592 | #ifndef PRODUCT |
| 33593 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33594 | virtual const char *Name() const { return "Repl16S_imm_evex";} |
| 33595 | #endif |
| 33596 | }; |
| 33597 | |
| 33598 | class Repl32S_imm_evexNode : public MachConstantNode { |
| 33599 | private: |
| 33600 | MachOper *_opnd_array[2]; |
| 33601 | public: |
| 33602 | MachOper *opnd_array(uint operand_index) const { |
| 33603 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33604 | return _opnd_array[operand_index]; |
| 33605 | } |
| 33606 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33607 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33608 | _opnd_array[operand_index] = operand; |
| 33609 | } |
| 33610 | private: |
| 33611 | virtual const RegMask &out_RegMask() const; |
| 33612 | virtual uint rule() const { return Repl32S_imm_evex_rule; } |
| 33613 | virtual void eval_constant(Compile* C); |
| 33614 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33615 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33616 | virtual uint oper_input_base() const { return 1; } |
| 33617 | public: |
| 33618 | Repl32S_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33619 | virtual uint size_of() const { return sizeof(Repl32S_imm_evexNode); } |
| 33620 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33621 | static const Pipeline *pipeline_class(); |
| 33622 | virtual const Pipeline *pipeline() const; |
| 33623 | #ifndef PRODUCT |
| 33624 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33625 | virtual const char *Name() const { return "Repl32S_imm_evex";} |
| 33626 | #endif |
| 33627 | }; |
| 33628 | |
| 33629 | class Repl32S_zero_evexNode : public MachTypeNode { |
| 33630 | private: |
| 33631 | MachOper *_opnd_array[2]; |
| 33632 | public: |
| 33633 | MachOper *opnd_array(uint operand_index) const { |
| 33634 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33635 | return _opnd_array[operand_index]; |
| 33636 | } |
| 33637 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33638 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33639 | _opnd_array[operand_index] = operand; |
| 33640 | } |
| 33641 | private: |
| 33642 | virtual const RegMask &out_RegMask() const; |
| 33643 | virtual uint rule() const { return Repl32S_zero_evex_rule; } |
| 33644 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33645 | virtual int ideal_Opcode() const { return Op_ReplicateS; } |
| 33646 | virtual uint oper_input_base() const { return 1; } |
| 33647 | public: |
| 33648 | Repl32S_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33649 | virtual uint size_of() const { return sizeof(Repl32S_zero_evexNode); } |
| 33650 | static const Pipeline *pipeline_class(); |
| 33651 | virtual const Pipeline *pipeline() const; |
| 33652 | #ifndef PRODUCT |
| 33653 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33654 | virtual const char *Name() const { return "Repl32S_zero_evex";} |
| 33655 | #endif |
| 33656 | }; |
| 33657 | |
| 33658 | class Repl4I_evexNode : public MachTypeNode { |
| 33659 | private: |
| 33660 | MachOper *_opnd_array[2]; |
| 33661 | public: |
| 33662 | MachOper *opnd_array(uint operand_index) const { |
| 33663 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33664 | return _opnd_array[operand_index]; |
| 33665 | } |
| 33666 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33667 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33668 | _opnd_array[operand_index] = operand; |
| 33669 | } |
| 33670 | private: |
| 33671 | const RegMask *_cisc_RegMask; |
| 33672 | virtual const RegMask &out_RegMask() const; |
| 33673 | virtual uint rule() const { return Repl4I_evex_rule; } |
| 33674 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33675 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33676 | virtual int cisc_operand() const { return 1; } |
| 33677 | virtual MachNode *cisc_version(int offset); |
| 33678 | virtual void use_cisc_RegMask(); |
| 33679 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 33680 | virtual uint oper_input_base() const { return 1; } |
| 33681 | public: |
| 33682 | Repl4I_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 33683 | virtual uint size_of() const { return sizeof(Repl4I_evexNode); } |
| 33684 | static const Pipeline *pipeline_class(); |
| 33685 | virtual const Pipeline *pipeline() const; |
| 33686 | #ifndef PRODUCT |
| 33687 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33688 | virtual const char *Name() const { return "Repl4I_evex";} |
| 33689 | #endif |
| 33690 | }; |
| 33691 | |
| 33692 | class Repl4I_mem_evexNode : public MachTypeNode { |
| 33693 | private: |
| 33694 | MachOper *_opnd_array[2]; |
| 33695 | public: |
| 33696 | MachOper *opnd_array(uint operand_index) const { |
| 33697 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33698 | return _opnd_array[operand_index]; |
| 33699 | } |
| 33700 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33701 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33702 | _opnd_array[operand_index] = operand; |
| 33703 | } |
| 33704 | private: |
| 33705 | virtual const RegMask &out_RegMask() const; |
| 33706 | virtual uint rule() const { return Repl4I_mem_evex_rule; } |
| 33707 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33708 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33709 | virtual int reloc() const; |
| 33710 | virtual uint oper_input_base() const { return 2; } |
| 33711 | public: |
| 33712 | Repl4I_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 33713 | virtual uint size_of() const { return sizeof(Repl4I_mem_evexNode); } |
| 33714 | static const Pipeline *pipeline_class(); |
| 33715 | virtual const Pipeline *pipeline() const; |
| 33716 | virtual const MachOper *memory_operand() const; |
| 33717 | #ifndef PRODUCT |
| 33718 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33719 | virtual const char *Name() const { return "Repl4I_mem_evex";} |
| 33720 | #endif |
| 33721 | }; |
| 33722 | |
| 33723 | class Repl8I_evexNode : public MachTypeNode { |
| 33724 | private: |
| 33725 | MachOper *_opnd_array[2]; |
| 33726 | public: |
| 33727 | MachOper *opnd_array(uint operand_index) const { |
| 33728 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33729 | return _opnd_array[operand_index]; |
| 33730 | } |
| 33731 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33732 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33733 | _opnd_array[operand_index] = operand; |
| 33734 | } |
| 33735 | private: |
| 33736 | const RegMask *_cisc_RegMask; |
| 33737 | virtual const RegMask &out_RegMask() const; |
| 33738 | virtual uint rule() const { return Repl8I_evex_rule; } |
| 33739 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33740 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33741 | virtual int cisc_operand() const { return 1; } |
| 33742 | virtual MachNode *cisc_version(int offset); |
| 33743 | virtual void use_cisc_RegMask(); |
| 33744 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 33745 | virtual uint oper_input_base() const { return 1; } |
| 33746 | public: |
| 33747 | Repl8I_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 33748 | virtual uint size_of() const { return sizeof(Repl8I_evexNode); } |
| 33749 | static const Pipeline *pipeline_class(); |
| 33750 | virtual const Pipeline *pipeline() const; |
| 33751 | #ifndef PRODUCT |
| 33752 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33753 | virtual const char *Name() const { return "Repl8I_evex";} |
| 33754 | #endif |
| 33755 | }; |
| 33756 | |
| 33757 | class Repl8I_mem_evexNode : public MachTypeNode { |
| 33758 | private: |
| 33759 | MachOper *_opnd_array[2]; |
| 33760 | public: |
| 33761 | MachOper *opnd_array(uint operand_index) const { |
| 33762 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33763 | return _opnd_array[operand_index]; |
| 33764 | } |
| 33765 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33766 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33767 | _opnd_array[operand_index] = operand; |
| 33768 | } |
| 33769 | private: |
| 33770 | virtual const RegMask &out_RegMask() const; |
| 33771 | virtual uint rule() const { return Repl8I_mem_evex_rule; } |
| 33772 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33773 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33774 | virtual int reloc() const; |
| 33775 | virtual uint oper_input_base() const { return 2; } |
| 33776 | public: |
| 33777 | Repl8I_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 33778 | virtual uint size_of() const { return sizeof(Repl8I_mem_evexNode); } |
| 33779 | static const Pipeline *pipeline_class(); |
| 33780 | virtual const Pipeline *pipeline() const; |
| 33781 | virtual const MachOper *memory_operand() const; |
| 33782 | #ifndef PRODUCT |
| 33783 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33784 | virtual const char *Name() const { return "Repl8I_mem_evex";} |
| 33785 | #endif |
| 33786 | }; |
| 33787 | |
| 33788 | class Repl16I_evexNode : public MachTypeNode { |
| 33789 | private: |
| 33790 | MachOper *_opnd_array[2]; |
| 33791 | public: |
| 33792 | MachOper *opnd_array(uint operand_index) const { |
| 33793 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33794 | return _opnd_array[operand_index]; |
| 33795 | } |
| 33796 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33797 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33798 | _opnd_array[operand_index] = operand; |
| 33799 | } |
| 33800 | private: |
| 33801 | const RegMask *_cisc_RegMask; |
| 33802 | virtual const RegMask &out_RegMask() const; |
| 33803 | virtual uint rule() const { return Repl16I_evex_rule; } |
| 33804 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33805 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33806 | virtual int cisc_operand() const { return 1; } |
| 33807 | virtual MachNode *cisc_version(int offset); |
| 33808 | virtual void use_cisc_RegMask(); |
| 33809 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 33810 | virtual uint oper_input_base() const { return 1; } |
| 33811 | public: |
| 33812 | Repl16I_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 33813 | virtual uint size_of() const { return sizeof(Repl16I_evexNode); } |
| 33814 | static const Pipeline *pipeline_class(); |
| 33815 | virtual const Pipeline *pipeline() const; |
| 33816 | #ifndef PRODUCT |
| 33817 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33818 | virtual const char *Name() const { return "Repl16I_evex";} |
| 33819 | #endif |
| 33820 | }; |
| 33821 | |
| 33822 | class Repl16I_mem_evexNode : public MachTypeNode { |
| 33823 | private: |
| 33824 | MachOper *_opnd_array[2]; |
| 33825 | public: |
| 33826 | MachOper *opnd_array(uint operand_index) const { |
| 33827 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33828 | return _opnd_array[operand_index]; |
| 33829 | } |
| 33830 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33831 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33832 | _opnd_array[operand_index] = operand; |
| 33833 | } |
| 33834 | private: |
| 33835 | virtual const RegMask &out_RegMask() const; |
| 33836 | virtual uint rule() const { return Repl16I_mem_evex_rule; } |
| 33837 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33838 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33839 | virtual int reloc() const; |
| 33840 | virtual uint oper_input_base() const { return 2; } |
| 33841 | public: |
| 33842 | Repl16I_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 33843 | virtual uint size_of() const { return sizeof(Repl16I_mem_evexNode); } |
| 33844 | static const Pipeline *pipeline_class(); |
| 33845 | virtual const Pipeline *pipeline() const; |
| 33846 | virtual const MachOper *memory_operand() const; |
| 33847 | #ifndef PRODUCT |
| 33848 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33849 | virtual const char *Name() const { return "Repl16I_mem_evex";} |
| 33850 | #endif |
| 33851 | }; |
| 33852 | |
| 33853 | class Repl4I_imm_evexNode : public MachConstantNode { |
| 33854 | private: |
| 33855 | MachOper *_opnd_array[2]; |
| 33856 | public: |
| 33857 | MachOper *opnd_array(uint operand_index) const { |
| 33858 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33859 | return _opnd_array[operand_index]; |
| 33860 | } |
| 33861 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33862 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33863 | _opnd_array[operand_index] = operand; |
| 33864 | } |
| 33865 | private: |
| 33866 | virtual const RegMask &out_RegMask() const; |
| 33867 | virtual uint rule() const { return Repl4I_imm_evex_rule; } |
| 33868 | virtual void eval_constant(Compile* C); |
| 33869 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33870 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33871 | virtual uint oper_input_base() const { return 1; } |
| 33872 | public: |
| 33873 | Repl4I_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33874 | virtual uint size_of() const { return sizeof(Repl4I_imm_evexNode); } |
| 33875 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33876 | static const Pipeline *pipeline_class(); |
| 33877 | virtual const Pipeline *pipeline() const; |
| 33878 | #ifndef PRODUCT |
| 33879 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33880 | virtual const char *Name() const { return "Repl4I_imm_evex";} |
| 33881 | #endif |
| 33882 | }; |
| 33883 | |
| 33884 | class Repl8I_imm_evexNode : public MachConstantNode { |
| 33885 | private: |
| 33886 | MachOper *_opnd_array[2]; |
| 33887 | public: |
| 33888 | MachOper *opnd_array(uint operand_index) const { |
| 33889 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33890 | return _opnd_array[operand_index]; |
| 33891 | } |
| 33892 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33893 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33894 | _opnd_array[operand_index] = operand; |
| 33895 | } |
| 33896 | private: |
| 33897 | virtual const RegMask &out_RegMask() const; |
| 33898 | virtual uint rule() const { return Repl8I_imm_evex_rule; } |
| 33899 | virtual void eval_constant(Compile* C); |
| 33900 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33901 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33902 | virtual uint oper_input_base() const { return 1; } |
| 33903 | public: |
| 33904 | Repl8I_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33905 | virtual uint size_of() const { return sizeof(Repl8I_imm_evexNode); } |
| 33906 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33907 | static const Pipeline *pipeline_class(); |
| 33908 | virtual const Pipeline *pipeline() const; |
| 33909 | #ifndef PRODUCT |
| 33910 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33911 | virtual const char *Name() const { return "Repl8I_imm_evex";} |
| 33912 | #endif |
| 33913 | }; |
| 33914 | |
| 33915 | class Repl16I_imm_evexNode : public MachConstantNode { |
| 33916 | private: |
| 33917 | MachOper *_opnd_array[2]; |
| 33918 | public: |
| 33919 | MachOper *opnd_array(uint operand_index) const { |
| 33920 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33921 | return _opnd_array[operand_index]; |
| 33922 | } |
| 33923 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33924 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33925 | _opnd_array[operand_index] = operand; |
| 33926 | } |
| 33927 | private: |
| 33928 | virtual const RegMask &out_RegMask() const; |
| 33929 | virtual uint rule() const { return Repl16I_imm_evex_rule; } |
| 33930 | virtual void eval_constant(Compile* C); |
| 33931 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33932 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33933 | virtual uint oper_input_base() const { return 1; } |
| 33934 | public: |
| 33935 | Repl16I_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33936 | virtual uint size_of() const { return sizeof(Repl16I_imm_evexNode); } |
| 33937 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 33938 | static const Pipeline *pipeline_class(); |
| 33939 | virtual const Pipeline *pipeline() const; |
| 33940 | #ifndef PRODUCT |
| 33941 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33942 | virtual const char *Name() const { return "Repl16I_imm_evex";} |
| 33943 | #endif |
| 33944 | }; |
| 33945 | |
| 33946 | class Repl16I_zero_evexNode : public MachTypeNode { |
| 33947 | private: |
| 33948 | MachOper *_opnd_array[2]; |
| 33949 | public: |
| 33950 | MachOper *opnd_array(uint operand_index) const { |
| 33951 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33952 | return _opnd_array[operand_index]; |
| 33953 | } |
| 33954 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33955 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33956 | _opnd_array[operand_index] = operand; |
| 33957 | } |
| 33958 | private: |
| 33959 | virtual const RegMask &out_RegMask() const; |
| 33960 | virtual uint rule() const { return Repl16I_zero_evex_rule; } |
| 33961 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33962 | virtual int ideal_Opcode() const { return Op_ReplicateI; } |
| 33963 | virtual uint oper_input_base() const { return 1; } |
| 33964 | public: |
| 33965 | Repl16I_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 33966 | virtual uint size_of() const { return sizeof(Repl16I_zero_evexNode); } |
| 33967 | static const Pipeline *pipeline_class(); |
| 33968 | virtual const Pipeline *pipeline() const; |
| 33969 | #ifndef PRODUCT |
| 33970 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 33971 | virtual const char *Name() const { return "Repl16I_zero_evex";} |
| 33972 | #endif |
| 33973 | }; |
| 33974 | |
| 33975 | class Repl4L_evexNode : public MachTypeNode { |
| 33976 | private: |
| 33977 | MachOper *_opnd_array[2]; |
| 33978 | public: |
| 33979 | MachOper *opnd_array(uint operand_index) const { |
| 33980 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33981 | return _opnd_array[operand_index]; |
| 33982 | } |
| 33983 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 33984 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 33985 | _opnd_array[operand_index] = operand; |
| 33986 | } |
| 33987 | private: |
| 33988 | const RegMask *_cisc_RegMask; |
| 33989 | virtual const RegMask &out_RegMask() const; |
| 33990 | virtual uint rule() const { return Repl4L_evex_rule; } |
| 33991 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 33992 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 33993 | virtual int cisc_operand() const { return 1; } |
| 33994 | virtual MachNode *cisc_version(int offset); |
| 33995 | virtual void use_cisc_RegMask(); |
| 33996 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 33997 | virtual uint oper_input_base() const { return 1; } |
| 33998 | public: |
| 33999 | Repl4L_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34000 | virtual uint size_of() const { return sizeof(Repl4L_evexNode); } |
| 34001 | static const Pipeline *pipeline_class(); |
| 34002 | virtual const Pipeline *pipeline() const; |
| 34003 | #ifndef PRODUCT |
| 34004 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34005 | virtual const char *Name() const { return "Repl4L_evex";} |
| 34006 | #endif |
| 34007 | }; |
| 34008 | |
| 34009 | class Repl8L_evexNode : public MachTypeNode { |
| 34010 | private: |
| 34011 | MachOper *_opnd_array[2]; |
| 34012 | public: |
| 34013 | MachOper *opnd_array(uint operand_index) const { |
| 34014 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34015 | return _opnd_array[operand_index]; |
| 34016 | } |
| 34017 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34018 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34019 | _opnd_array[operand_index] = operand; |
| 34020 | } |
| 34021 | private: |
| 34022 | const RegMask *_cisc_RegMask; |
| 34023 | virtual const RegMask &out_RegMask() const; |
| 34024 | virtual uint rule() const { return Repl8L_evex_rule; } |
| 34025 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34026 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34027 | virtual int cisc_operand() const { return 1; } |
| 34028 | virtual MachNode *cisc_version(int offset); |
| 34029 | virtual void use_cisc_RegMask(); |
| 34030 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 34031 | virtual uint oper_input_base() const { return 1; } |
| 34032 | public: |
| 34033 | Repl8L_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34034 | virtual uint size_of() const { return sizeof(Repl8L_evexNode); } |
| 34035 | static const Pipeline *pipeline_class(); |
| 34036 | virtual const Pipeline *pipeline() const; |
| 34037 | #ifndef PRODUCT |
| 34038 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34039 | virtual const char *Name() const { return "Repl8L_evex";} |
| 34040 | #endif |
| 34041 | }; |
| 34042 | |
| 34043 | class Repl4L_imm_evexNode : public MachConstantNode { |
| 34044 | private: |
| 34045 | MachOper *_opnd_array[2]; |
| 34046 | public: |
| 34047 | MachOper *opnd_array(uint operand_index) const { |
| 34048 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34049 | return _opnd_array[operand_index]; |
| 34050 | } |
| 34051 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34052 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34053 | _opnd_array[operand_index] = operand; |
| 34054 | } |
| 34055 | private: |
| 34056 | virtual const RegMask &out_RegMask() const; |
| 34057 | virtual uint rule() const { return Repl4L_imm_evex_rule; } |
| 34058 | virtual void eval_constant(Compile* C); |
| 34059 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34060 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34061 | virtual uint oper_input_base() const { return 1; } |
| 34062 | public: |
| 34063 | Repl4L_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34064 | virtual uint size_of() const { return sizeof(Repl4L_imm_evexNode); } |
| 34065 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34066 | static const Pipeline *pipeline_class(); |
| 34067 | virtual const Pipeline *pipeline() const; |
| 34068 | #ifndef PRODUCT |
| 34069 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34070 | virtual const char *Name() const { return "Repl4L_imm_evex";} |
| 34071 | #endif |
| 34072 | }; |
| 34073 | |
| 34074 | class Repl8L_imm_evexNode : public MachConstantNode { |
| 34075 | private: |
| 34076 | MachOper *_opnd_array[2]; |
| 34077 | public: |
| 34078 | MachOper *opnd_array(uint operand_index) const { |
| 34079 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34080 | return _opnd_array[operand_index]; |
| 34081 | } |
| 34082 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34083 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34084 | _opnd_array[operand_index] = operand; |
| 34085 | } |
| 34086 | private: |
| 34087 | virtual const RegMask &out_RegMask() const; |
| 34088 | virtual uint rule() const { return Repl8L_imm_evex_rule; } |
| 34089 | virtual void eval_constant(Compile* C); |
| 34090 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34091 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34092 | virtual uint oper_input_base() const { return 1; } |
| 34093 | public: |
| 34094 | Repl8L_imm_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34095 | virtual uint size_of() const { return sizeof(Repl8L_imm_evexNode); } |
| 34096 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34097 | static const Pipeline *pipeline_class(); |
| 34098 | virtual const Pipeline *pipeline() const; |
| 34099 | #ifndef PRODUCT |
| 34100 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34101 | virtual const char *Name() const { return "Repl8L_imm_evex";} |
| 34102 | #endif |
| 34103 | }; |
| 34104 | |
| 34105 | class Repl2L_mem_evexNode : public MachTypeNode { |
| 34106 | private: |
| 34107 | MachOper *_opnd_array[2]; |
| 34108 | public: |
| 34109 | MachOper *opnd_array(uint operand_index) const { |
| 34110 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34111 | return _opnd_array[operand_index]; |
| 34112 | } |
| 34113 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34114 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34115 | _opnd_array[operand_index] = operand; |
| 34116 | } |
| 34117 | private: |
| 34118 | virtual const RegMask &out_RegMask() const; |
| 34119 | virtual uint rule() const { return Repl2L_mem_evex_rule; } |
| 34120 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34121 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34122 | virtual int reloc() const; |
| 34123 | virtual uint oper_input_base() const { return 2; } |
| 34124 | public: |
| 34125 | Repl2L_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 34126 | virtual uint size_of() const { return sizeof(Repl2L_mem_evexNode); } |
| 34127 | static const Pipeline *pipeline_class(); |
| 34128 | virtual const Pipeline *pipeline() const; |
| 34129 | virtual const MachOper *memory_operand() const; |
| 34130 | #ifndef PRODUCT |
| 34131 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34132 | virtual const char *Name() const { return "Repl2L_mem_evex";} |
| 34133 | #endif |
| 34134 | }; |
| 34135 | |
| 34136 | class Repl4L_mem_evexNode : public MachTypeNode { |
| 34137 | private: |
| 34138 | MachOper *_opnd_array[2]; |
| 34139 | public: |
| 34140 | MachOper *opnd_array(uint operand_index) const { |
| 34141 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34142 | return _opnd_array[operand_index]; |
| 34143 | } |
| 34144 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34145 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34146 | _opnd_array[operand_index] = operand; |
| 34147 | } |
| 34148 | private: |
| 34149 | virtual const RegMask &out_RegMask() const; |
| 34150 | virtual uint rule() const { return Repl4L_mem_evex_rule; } |
| 34151 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34152 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34153 | virtual int reloc() const; |
| 34154 | virtual uint oper_input_base() const { return 2; } |
| 34155 | public: |
| 34156 | Repl4L_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34157 | virtual uint size_of() const { return sizeof(Repl4L_mem_evexNode); } |
| 34158 | static const Pipeline *pipeline_class(); |
| 34159 | virtual const Pipeline *pipeline() const; |
| 34160 | virtual const MachOper *memory_operand() const; |
| 34161 | #ifndef PRODUCT |
| 34162 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34163 | virtual const char *Name() const { return "Repl4L_mem_evex";} |
| 34164 | #endif |
| 34165 | }; |
| 34166 | |
| 34167 | class Repl8L_mem_evexNode : public MachTypeNode { |
| 34168 | private: |
| 34169 | MachOper *_opnd_array[2]; |
| 34170 | public: |
| 34171 | MachOper *opnd_array(uint operand_index) const { |
| 34172 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34173 | return _opnd_array[operand_index]; |
| 34174 | } |
| 34175 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34176 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34177 | _opnd_array[operand_index] = operand; |
| 34178 | } |
| 34179 | private: |
| 34180 | virtual const RegMask &out_RegMask() const; |
| 34181 | virtual uint rule() const { return Repl8L_mem_evex_rule; } |
| 34182 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34183 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34184 | virtual int reloc() const; |
| 34185 | virtual uint oper_input_base() const { return 2; } |
| 34186 | public: |
| 34187 | Repl8L_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34188 | virtual uint size_of() const { return sizeof(Repl8L_mem_evexNode); } |
| 34189 | static const Pipeline *pipeline_class(); |
| 34190 | virtual const Pipeline *pipeline() const; |
| 34191 | virtual const MachOper *memory_operand() const; |
| 34192 | #ifndef PRODUCT |
| 34193 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34194 | virtual const char *Name() const { return "Repl8L_mem_evex";} |
| 34195 | #endif |
| 34196 | }; |
| 34197 | |
| 34198 | class Repl8L_zero_evexNode : public MachTypeNode { |
| 34199 | private: |
| 34200 | MachOper *_opnd_array[2]; |
| 34201 | public: |
| 34202 | MachOper *opnd_array(uint operand_index) const { |
| 34203 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34204 | return _opnd_array[operand_index]; |
| 34205 | } |
| 34206 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34207 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34208 | _opnd_array[operand_index] = operand; |
| 34209 | } |
| 34210 | private: |
| 34211 | virtual const RegMask &out_RegMask() const; |
| 34212 | virtual uint rule() const { return Repl8L_zero_evex_rule; } |
| 34213 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34214 | virtual int ideal_Opcode() const { return Op_ReplicateL; } |
| 34215 | virtual uint oper_input_base() const { return 1; } |
| 34216 | public: |
| 34217 | Repl8L_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34218 | virtual uint size_of() const { return sizeof(Repl8L_zero_evexNode); } |
| 34219 | static const Pipeline *pipeline_class(); |
| 34220 | virtual const Pipeline *pipeline() const; |
| 34221 | #ifndef PRODUCT |
| 34222 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34223 | virtual const char *Name() const { return "Repl8L_zero_evex";} |
| 34224 | #endif |
| 34225 | }; |
| 34226 | |
| 34227 | class Repl8F_evexNode : public MachTypeNode { |
| 34228 | private: |
| 34229 | MachOper *_opnd_array[2]; |
| 34230 | public: |
| 34231 | MachOper *opnd_array(uint operand_index) const { |
| 34232 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34233 | return _opnd_array[operand_index]; |
| 34234 | } |
| 34235 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34236 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34237 | _opnd_array[operand_index] = operand; |
| 34238 | } |
| 34239 | private: |
| 34240 | const RegMask *_cisc_RegMask; |
| 34241 | virtual const RegMask &out_RegMask() const; |
| 34242 | virtual uint rule() const { return Repl8F_evex_rule; } |
| 34243 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34244 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34245 | virtual int cisc_operand() const { return 1; } |
| 34246 | virtual MachNode *cisc_version(int offset); |
| 34247 | virtual void use_cisc_RegMask(); |
| 34248 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 34249 | virtual uint oper_input_base() const { return 1; } |
| 34250 | public: |
| 34251 | Repl8F_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34252 | virtual uint size_of() const { return sizeof(Repl8F_evexNode); } |
| 34253 | static const Pipeline *pipeline_class(); |
| 34254 | virtual const Pipeline *pipeline() const; |
| 34255 | #ifndef PRODUCT |
| 34256 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34257 | virtual const char *Name() const { return "Repl8F_evex";} |
| 34258 | #endif |
| 34259 | }; |
| 34260 | |
| 34261 | class Repl8F_mem_evexNode : public MachTypeNode { |
| 34262 | private: |
| 34263 | MachOper *_opnd_array[2]; |
| 34264 | public: |
| 34265 | MachOper *opnd_array(uint operand_index) const { |
| 34266 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34267 | return _opnd_array[operand_index]; |
| 34268 | } |
| 34269 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34271 | _opnd_array[operand_index] = operand; |
| 34272 | } |
| 34273 | private: |
| 34274 | virtual const RegMask &out_RegMask() const; |
| 34275 | virtual uint rule() const { return Repl8F_mem_evex_rule; } |
| 34276 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34277 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34278 | virtual int reloc() const; |
| 34279 | virtual uint oper_input_base() const { return 2; } |
| 34280 | public: |
| 34281 | Repl8F_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34282 | virtual uint size_of() const { return sizeof(Repl8F_mem_evexNode); } |
| 34283 | static const Pipeline *pipeline_class(); |
| 34284 | virtual const Pipeline *pipeline() const; |
| 34285 | virtual const MachOper *memory_operand() const; |
| 34286 | #ifndef PRODUCT |
| 34287 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34288 | virtual const char *Name() const { return "Repl8F_mem_evex";} |
| 34289 | #endif |
| 34290 | }; |
| 34291 | |
| 34292 | class Repl16F_evexNode : public MachTypeNode { |
| 34293 | private: |
| 34294 | MachOper *_opnd_array[2]; |
| 34295 | public: |
| 34296 | MachOper *opnd_array(uint operand_index) const { |
| 34297 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34298 | return _opnd_array[operand_index]; |
| 34299 | } |
| 34300 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34301 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34302 | _opnd_array[operand_index] = operand; |
| 34303 | } |
| 34304 | private: |
| 34305 | const RegMask *_cisc_RegMask; |
| 34306 | virtual const RegMask &out_RegMask() const; |
| 34307 | virtual uint rule() const { return Repl16F_evex_rule; } |
| 34308 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34309 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34310 | virtual int cisc_operand() const { return 1; } |
| 34311 | virtual MachNode *cisc_version(int offset); |
| 34312 | virtual void use_cisc_RegMask(); |
| 34313 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 34314 | virtual uint oper_input_base() const { return 1; } |
| 34315 | public: |
| 34316 | Repl16F_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34317 | virtual uint size_of() const { return sizeof(Repl16F_evexNode); } |
| 34318 | static const Pipeline *pipeline_class(); |
| 34319 | virtual const Pipeline *pipeline() const; |
| 34320 | #ifndef PRODUCT |
| 34321 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34322 | virtual const char *Name() const { return "Repl16F_evex";} |
| 34323 | #endif |
| 34324 | }; |
| 34325 | |
| 34326 | class Repl16F_mem_evexNode : public MachTypeNode { |
| 34327 | private: |
| 34328 | MachOper *_opnd_array[2]; |
| 34329 | public: |
| 34330 | MachOper *opnd_array(uint operand_index) const { |
| 34331 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34332 | return _opnd_array[operand_index]; |
| 34333 | } |
| 34334 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34335 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34336 | _opnd_array[operand_index] = operand; |
| 34337 | } |
| 34338 | private: |
| 34339 | virtual const RegMask &out_RegMask() const; |
| 34340 | virtual uint rule() const { return Repl16F_mem_evex_rule; } |
| 34341 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34342 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34343 | virtual int reloc() const; |
| 34344 | virtual uint oper_input_base() const { return 2; } |
| 34345 | public: |
| 34346 | Repl16F_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34347 | virtual uint size_of() const { return sizeof(Repl16F_mem_evexNode); } |
| 34348 | static const Pipeline *pipeline_class(); |
| 34349 | virtual const Pipeline *pipeline() const; |
| 34350 | virtual const MachOper *memory_operand() const; |
| 34351 | #ifndef PRODUCT |
| 34352 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34353 | virtual const char *Name() const { return "Repl16F_mem_evex";} |
| 34354 | #endif |
| 34355 | }; |
| 34356 | |
| 34357 | class Repl2F_zero_evexNode : public MachTypeNode { |
| 34358 | private: |
| 34359 | MachOper *_opnd_array[2]; |
| 34360 | public: |
| 34361 | MachOper *opnd_array(uint operand_index) const { |
| 34362 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34363 | return _opnd_array[operand_index]; |
| 34364 | } |
| 34365 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34366 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34367 | _opnd_array[operand_index] = operand; |
| 34368 | } |
| 34369 | private: |
| 34370 | virtual const RegMask &out_RegMask() const; |
| 34371 | virtual uint rule() const { return Repl2F_zero_evex_rule; } |
| 34372 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34373 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34374 | virtual int reloc() const; |
| 34375 | virtual uint oper_input_base() const { return 1; } |
| 34376 | public: |
| 34377 | Repl2F_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34378 | virtual uint size_of() const { return sizeof(Repl2F_zero_evexNode); } |
| 34379 | static const Pipeline *pipeline_class(); |
| 34380 | virtual const Pipeline *pipeline() const; |
| 34381 | #ifndef PRODUCT |
| 34382 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34383 | virtual const char *Name() const { return "Repl2F_zero_evex";} |
| 34384 | #endif |
| 34385 | }; |
| 34386 | |
| 34387 | class Repl4F_zero_evexNode : public MachTypeNode { |
| 34388 | private: |
| 34389 | MachOper *_opnd_array[2]; |
| 34390 | public: |
| 34391 | MachOper *opnd_array(uint operand_index) const { |
| 34392 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34393 | return _opnd_array[operand_index]; |
| 34394 | } |
| 34395 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34396 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34397 | _opnd_array[operand_index] = operand; |
| 34398 | } |
| 34399 | private: |
| 34400 | virtual const RegMask &out_RegMask() const; |
| 34401 | virtual uint rule() const { return Repl4F_zero_evex_rule; } |
| 34402 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34403 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34404 | virtual int reloc() const; |
| 34405 | virtual uint oper_input_base() const { return 1; } |
| 34406 | public: |
| 34407 | Repl4F_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34408 | virtual uint size_of() const { return sizeof(Repl4F_zero_evexNode); } |
| 34409 | static const Pipeline *pipeline_class(); |
| 34410 | virtual const Pipeline *pipeline() const; |
| 34411 | #ifndef PRODUCT |
| 34412 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34413 | virtual const char *Name() const { return "Repl4F_zero_evex";} |
| 34414 | #endif |
| 34415 | }; |
| 34416 | |
| 34417 | class Repl8F_zero_evexNode : public MachTypeNode { |
| 34418 | private: |
| 34419 | MachOper *_opnd_array[2]; |
| 34420 | public: |
| 34421 | MachOper *opnd_array(uint operand_index) const { |
| 34422 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34423 | return _opnd_array[operand_index]; |
| 34424 | } |
| 34425 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34426 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34427 | _opnd_array[operand_index] = operand; |
| 34428 | } |
| 34429 | private: |
| 34430 | virtual const RegMask &out_RegMask() const; |
| 34431 | virtual uint rule() const { return Repl8F_zero_evex_rule; } |
| 34432 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34433 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34434 | virtual int reloc() const; |
| 34435 | virtual uint oper_input_base() const { return 1; } |
| 34436 | public: |
| 34437 | Repl8F_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34438 | virtual uint size_of() const { return sizeof(Repl8F_zero_evexNode); } |
| 34439 | static const Pipeline *pipeline_class(); |
| 34440 | virtual const Pipeline *pipeline() const; |
| 34441 | #ifndef PRODUCT |
| 34442 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34443 | virtual const char *Name() const { return "Repl8F_zero_evex";} |
| 34444 | #endif |
| 34445 | }; |
| 34446 | |
| 34447 | class Repl16F_zero_evexNode : public MachTypeNode { |
| 34448 | private: |
| 34449 | MachOper *_opnd_array[2]; |
| 34450 | public: |
| 34451 | MachOper *opnd_array(uint operand_index) const { |
| 34452 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34453 | return _opnd_array[operand_index]; |
| 34454 | } |
| 34455 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34456 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34457 | _opnd_array[operand_index] = operand; |
| 34458 | } |
| 34459 | private: |
| 34460 | virtual const RegMask &out_RegMask() const; |
| 34461 | virtual uint rule() const { return Repl16F_zero_evex_rule; } |
| 34462 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34463 | virtual int ideal_Opcode() const { return Op_ReplicateF; } |
| 34464 | virtual int reloc() const; |
| 34465 | virtual uint oper_input_base() const { return 1; } |
| 34466 | public: |
| 34467 | Repl16F_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34468 | virtual uint size_of() const { return sizeof(Repl16F_zero_evexNode); } |
| 34469 | static const Pipeline *pipeline_class(); |
| 34470 | virtual const Pipeline *pipeline() const; |
| 34471 | #ifndef PRODUCT |
| 34472 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34473 | virtual const char *Name() const { return "Repl16F_zero_evex";} |
| 34474 | #endif |
| 34475 | }; |
| 34476 | |
| 34477 | class Repl4D_evexNode : public MachTypeNode { |
| 34478 | private: |
| 34479 | MachOper *_opnd_array[2]; |
| 34480 | public: |
| 34481 | MachOper *opnd_array(uint operand_index) const { |
| 34482 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34483 | return _opnd_array[operand_index]; |
| 34484 | } |
| 34485 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34486 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34487 | _opnd_array[operand_index] = operand; |
| 34488 | } |
| 34489 | private: |
| 34490 | const RegMask *_cisc_RegMask; |
| 34491 | virtual const RegMask &out_RegMask() const; |
| 34492 | virtual uint rule() const { return Repl4D_evex_rule; } |
| 34493 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34494 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34495 | virtual int cisc_operand() const { return 1; } |
| 34496 | virtual MachNode *cisc_version(int offset); |
| 34497 | virtual void use_cisc_RegMask(); |
| 34498 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 34499 | virtual uint oper_input_base() const { return 1; } |
| 34500 | public: |
| 34501 | Repl4D_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34502 | virtual uint size_of() const { return sizeof(Repl4D_evexNode); } |
| 34503 | static const Pipeline *pipeline_class(); |
| 34504 | virtual const Pipeline *pipeline() const; |
| 34505 | #ifndef PRODUCT |
| 34506 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34507 | virtual const char *Name() const { return "Repl4D_evex";} |
| 34508 | #endif |
| 34509 | }; |
| 34510 | |
| 34511 | class Repl4D_mem_evexNode : public MachTypeNode { |
| 34512 | private: |
| 34513 | MachOper *_opnd_array[2]; |
| 34514 | public: |
| 34515 | MachOper *opnd_array(uint operand_index) const { |
| 34516 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34517 | return _opnd_array[operand_index]; |
| 34518 | } |
| 34519 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34520 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34521 | _opnd_array[operand_index] = operand; |
| 34522 | } |
| 34523 | private: |
| 34524 | virtual const RegMask &out_RegMask() const; |
| 34525 | virtual uint rule() const { return Repl4D_mem_evex_rule; } |
| 34526 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34527 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34528 | virtual int reloc() const; |
| 34529 | virtual uint oper_input_base() const { return 2; } |
| 34530 | public: |
| 34531 | Repl4D_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34532 | virtual uint size_of() const { return sizeof(Repl4D_mem_evexNode); } |
| 34533 | static const Pipeline *pipeline_class(); |
| 34534 | virtual const Pipeline *pipeline() const; |
| 34535 | virtual const MachOper *memory_operand() const; |
| 34536 | #ifndef PRODUCT |
| 34537 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34538 | virtual const char *Name() const { return "Repl4D_mem_evex";} |
| 34539 | #endif |
| 34540 | }; |
| 34541 | |
| 34542 | class Repl8D_evexNode : public MachTypeNode { |
| 34543 | private: |
| 34544 | MachOper *_opnd_array[2]; |
| 34545 | public: |
| 34546 | MachOper *opnd_array(uint operand_index) const { |
| 34547 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34548 | return _opnd_array[operand_index]; |
| 34549 | } |
| 34550 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34551 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34552 | _opnd_array[operand_index] = operand; |
| 34553 | } |
| 34554 | private: |
| 34555 | const RegMask *_cisc_RegMask; |
| 34556 | virtual const RegMask &out_RegMask() const; |
| 34557 | virtual uint rule() const { return Repl8D_evex_rule; } |
| 34558 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34559 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34560 | virtual int cisc_operand() const { return 1; } |
| 34561 | virtual MachNode *cisc_version(int offset); |
| 34562 | virtual void use_cisc_RegMask(); |
| 34563 | virtual const RegMask *cisc_RegMask() const { return _cisc_RegMask; } |
| 34564 | virtual uint oper_input_base() const { return 1; } |
| 34565 | public: |
| 34566 | Repl8D_evexNode() { _cisc_RegMask = NULL; _num_opnds = 2; _opnds = _opnd_array; } |
| 34567 | virtual uint size_of() const { return sizeof(Repl8D_evexNode); } |
| 34568 | static const Pipeline *pipeline_class(); |
| 34569 | virtual const Pipeline *pipeline() const; |
| 34570 | #ifndef PRODUCT |
| 34571 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34572 | virtual const char *Name() const { return "Repl8D_evex";} |
| 34573 | #endif |
| 34574 | }; |
| 34575 | |
| 34576 | class Repl8D_mem_evexNode : public MachTypeNode { |
| 34577 | private: |
| 34578 | MachOper *_opnd_array[2]; |
| 34579 | public: |
| 34580 | MachOper *opnd_array(uint operand_index) const { |
| 34581 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34582 | return _opnd_array[operand_index]; |
| 34583 | } |
| 34584 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34585 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34586 | _opnd_array[operand_index] = operand; |
| 34587 | } |
| 34588 | private: |
| 34589 | virtual const RegMask &out_RegMask() const; |
| 34590 | virtual uint rule() const { return Repl8D_mem_evex_rule; } |
| 34591 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34592 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34593 | virtual int reloc() const; |
| 34594 | virtual uint oper_input_base() const { return 2; } |
| 34595 | public: |
| 34596 | Repl8D_mem_evexNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_is_cisc_alternate | Flag_needs_anti_dependence_check); } |
| 34597 | virtual uint size_of() const { return sizeof(Repl8D_mem_evexNode); } |
| 34598 | static const Pipeline *pipeline_class(); |
| 34599 | virtual const Pipeline *pipeline() const; |
| 34600 | virtual const MachOper *memory_operand() const; |
| 34601 | #ifndef PRODUCT |
| 34602 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34603 | virtual const char *Name() const { return "Repl8D_mem_evex";} |
| 34604 | #endif |
| 34605 | }; |
| 34606 | |
| 34607 | class Repl2D_zero_evexNode : public MachTypeNode { |
| 34608 | private: |
| 34609 | MachOper *_opnd_array[2]; |
| 34610 | public: |
| 34611 | MachOper *opnd_array(uint operand_index) const { |
| 34612 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34613 | return _opnd_array[operand_index]; |
| 34614 | } |
| 34615 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34616 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34617 | _opnd_array[operand_index] = operand; |
| 34618 | } |
| 34619 | private: |
| 34620 | virtual const RegMask &out_RegMask() const; |
| 34621 | virtual uint rule() const { return Repl2D_zero_evex_rule; } |
| 34622 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34623 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34624 | virtual int reloc() const; |
| 34625 | virtual uint oper_input_base() const { return 1; } |
| 34626 | public: |
| 34627 | Repl2D_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34628 | virtual uint size_of() const { return sizeof(Repl2D_zero_evexNode); } |
| 34629 | static const Pipeline *pipeline_class(); |
| 34630 | virtual const Pipeline *pipeline() const; |
| 34631 | #ifndef PRODUCT |
| 34632 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34633 | virtual const char *Name() const { return "Repl2D_zero_evex";} |
| 34634 | #endif |
| 34635 | }; |
| 34636 | |
| 34637 | class Repl4D_zero_evexNode : public MachTypeNode { |
| 34638 | private: |
| 34639 | MachOper *_opnd_array[2]; |
| 34640 | public: |
| 34641 | MachOper *opnd_array(uint operand_index) const { |
| 34642 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34643 | return _opnd_array[operand_index]; |
| 34644 | } |
| 34645 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34646 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34647 | _opnd_array[operand_index] = operand; |
| 34648 | } |
| 34649 | private: |
| 34650 | virtual const RegMask &out_RegMask() const; |
| 34651 | virtual uint rule() const { return Repl4D_zero_evex_rule; } |
| 34652 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34653 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34654 | virtual int reloc() const; |
| 34655 | virtual uint oper_input_base() const { return 1; } |
| 34656 | public: |
| 34657 | Repl4D_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34658 | virtual uint size_of() const { return sizeof(Repl4D_zero_evexNode); } |
| 34659 | static const Pipeline *pipeline_class(); |
| 34660 | virtual const Pipeline *pipeline() const; |
| 34661 | #ifndef PRODUCT |
| 34662 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34663 | virtual const char *Name() const { return "Repl4D_zero_evex";} |
| 34664 | #endif |
| 34665 | }; |
| 34666 | |
| 34667 | class Repl8D_zero_evexNode : public MachTypeNode { |
| 34668 | private: |
| 34669 | MachOper *_opnd_array[2]; |
| 34670 | public: |
| 34671 | MachOper *opnd_array(uint operand_index) const { |
| 34672 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34673 | return _opnd_array[operand_index]; |
| 34674 | } |
| 34675 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34676 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34677 | _opnd_array[operand_index] = operand; |
| 34678 | } |
| 34679 | private: |
| 34680 | virtual const RegMask &out_RegMask() const; |
| 34681 | virtual uint rule() const { return Repl8D_zero_evex_rule; } |
| 34682 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34683 | virtual int ideal_Opcode() const { return Op_ReplicateD; } |
| 34684 | virtual int reloc() const; |
| 34685 | virtual uint oper_input_base() const { return 1; } |
| 34686 | public: |
| 34687 | Repl8D_zero_evexNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 34688 | virtual uint size_of() const { return sizeof(Repl8D_zero_evexNode); } |
| 34689 | static const Pipeline *pipeline_class(); |
| 34690 | virtual const Pipeline *pipeline() const; |
| 34691 | #ifndef PRODUCT |
| 34692 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34693 | virtual const char *Name() const { return "Repl8D_zero_evex";} |
| 34694 | #endif |
| 34695 | }; |
| 34696 | |
| 34697 | class rsadd2I_reduction_regNode : public MachTypeNode { |
| 34698 | private: |
| 34699 | MachOper *_opnd_array[5]; |
| 34700 | public: |
| 34701 | MachOper *opnd_array(uint operand_index) const { |
| 34702 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34703 | return _opnd_array[operand_index]; |
| 34704 | } |
| 34705 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34706 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34707 | _opnd_array[operand_index] = operand; |
| 34708 | } |
| 34709 | private: |
| 34710 | virtual const RegMask &out_RegMask() const; |
| 34711 | virtual uint rule() const { return rsadd2I_reduction_reg_rule; } |
| 34712 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34713 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34714 | virtual uint oper_input_base() const { return 1; } |
| 34715 | public: |
| 34716 | rsadd2I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34717 | virtual uint size_of() const { return sizeof(rsadd2I_reduction_regNode); } |
| 34718 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34719 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34720 | static const Pipeline *pipeline_class(); |
| 34721 | virtual const Pipeline *pipeline() const; |
| 34722 | #ifndef PRODUCT |
| 34723 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34724 | virtual const char *Name() const { return "rsadd2I_reduction_reg";} |
| 34725 | #endif |
| 34726 | }; |
| 34727 | |
| 34728 | class rvadd2I_reduction_regNode : public MachTypeNode { |
| 34729 | private: |
| 34730 | MachOper *_opnd_array[5]; |
| 34731 | public: |
| 34732 | MachOper *opnd_array(uint operand_index) const { |
| 34733 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34734 | return _opnd_array[operand_index]; |
| 34735 | } |
| 34736 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34737 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34738 | _opnd_array[operand_index] = operand; |
| 34739 | } |
| 34740 | private: |
| 34741 | virtual const RegMask &out_RegMask() const; |
| 34742 | virtual uint rule() const { return rvadd2I_reduction_reg_rule; } |
| 34743 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34744 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34745 | virtual uint oper_input_base() const { return 1; } |
| 34746 | public: |
| 34747 | rvadd2I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34748 | virtual uint size_of() const { return sizeof(rvadd2I_reduction_regNode); } |
| 34749 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34750 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34751 | static const Pipeline *pipeline_class(); |
| 34752 | virtual const Pipeline *pipeline() const; |
| 34753 | #ifndef PRODUCT |
| 34754 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34755 | virtual const char *Name() const { return "rvadd2I_reduction_reg";} |
| 34756 | #endif |
| 34757 | }; |
| 34758 | |
| 34759 | class rvadd2I_reduction_reg_evexNode : public MachTypeNode { |
| 34760 | private: |
| 34761 | MachOper *_opnd_array[5]; |
| 34762 | public: |
| 34763 | MachOper *opnd_array(uint operand_index) const { |
| 34764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34765 | return _opnd_array[operand_index]; |
| 34766 | } |
| 34767 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34768 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34769 | _opnd_array[operand_index] = operand; |
| 34770 | } |
| 34771 | private: |
| 34772 | virtual const RegMask &out_RegMask() const; |
| 34773 | virtual uint rule() const { return rvadd2I_reduction_reg_evex_rule; } |
| 34774 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34775 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34776 | virtual uint oper_input_base() const { return 1; } |
| 34777 | public: |
| 34778 | rvadd2I_reduction_reg_evexNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34779 | virtual uint size_of() const { return sizeof(rvadd2I_reduction_reg_evexNode); } |
| 34780 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34781 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34782 | static const Pipeline *pipeline_class(); |
| 34783 | virtual const Pipeline *pipeline() const; |
| 34784 | #ifndef PRODUCT |
| 34785 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34786 | virtual const char *Name() const { return "rvadd2I_reduction_reg_evex";} |
| 34787 | #endif |
| 34788 | }; |
| 34789 | |
| 34790 | class rsadd4I_reduction_regNode : public MachTypeNode { |
| 34791 | private: |
| 34792 | MachOper *_opnd_array[5]; |
| 34793 | public: |
| 34794 | MachOper *opnd_array(uint operand_index) const { |
| 34795 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34796 | return _opnd_array[operand_index]; |
| 34797 | } |
| 34798 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34799 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34800 | _opnd_array[operand_index] = operand; |
| 34801 | } |
| 34802 | private: |
| 34803 | virtual const RegMask &out_RegMask() const; |
| 34804 | virtual uint rule() const { return rsadd4I_reduction_reg_rule; } |
| 34805 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34806 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34807 | virtual uint oper_input_base() const { return 1; } |
| 34808 | public: |
| 34809 | rsadd4I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34810 | virtual uint size_of() const { return sizeof(rsadd4I_reduction_regNode); } |
| 34811 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34812 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34813 | static const Pipeline *pipeline_class(); |
| 34814 | virtual const Pipeline *pipeline() const; |
| 34815 | #ifndef PRODUCT |
| 34816 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34817 | virtual const char *Name() const { return "rsadd4I_reduction_reg";} |
| 34818 | #endif |
| 34819 | }; |
| 34820 | |
| 34821 | class rvadd4I_reduction_regNode : public MachTypeNode { |
| 34822 | private: |
| 34823 | MachOper *_opnd_array[5]; |
| 34824 | public: |
| 34825 | MachOper *opnd_array(uint operand_index) const { |
| 34826 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34827 | return _opnd_array[operand_index]; |
| 34828 | } |
| 34829 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34831 | _opnd_array[operand_index] = operand; |
| 34832 | } |
| 34833 | private: |
| 34834 | virtual const RegMask &out_RegMask() const; |
| 34835 | virtual uint rule() const { return rvadd4I_reduction_reg_rule; } |
| 34836 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34837 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34838 | virtual uint oper_input_base() const { return 1; } |
| 34839 | public: |
| 34840 | rvadd4I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34841 | virtual uint size_of() const { return sizeof(rvadd4I_reduction_regNode); } |
| 34842 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34843 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34844 | static const Pipeline *pipeline_class(); |
| 34845 | virtual const Pipeline *pipeline() const; |
| 34846 | #ifndef PRODUCT |
| 34847 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34848 | virtual const char *Name() const { return "rvadd4I_reduction_reg";} |
| 34849 | #endif |
| 34850 | }; |
| 34851 | |
| 34852 | class rvadd4I_reduction_reg_evexNode : public MachTypeNode { |
| 34853 | private: |
| 34854 | MachOper *_opnd_array[5]; |
| 34855 | public: |
| 34856 | MachOper *opnd_array(uint operand_index) const { |
| 34857 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34858 | return _opnd_array[operand_index]; |
| 34859 | } |
| 34860 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34862 | _opnd_array[operand_index] = operand; |
| 34863 | } |
| 34864 | private: |
| 34865 | virtual const RegMask &out_RegMask() const; |
| 34866 | virtual uint rule() const { return rvadd4I_reduction_reg_evex_rule; } |
| 34867 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34868 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34869 | virtual uint oper_input_base() const { return 1; } |
| 34870 | public: |
| 34871 | rvadd4I_reduction_reg_evexNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34872 | virtual uint size_of() const { return sizeof(rvadd4I_reduction_reg_evexNode); } |
| 34873 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34874 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34875 | static const Pipeline *pipeline_class(); |
| 34876 | virtual const Pipeline *pipeline() const; |
| 34877 | #ifndef PRODUCT |
| 34878 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34879 | virtual const char *Name() const { return "rvadd4I_reduction_reg_evex";} |
| 34880 | #endif |
| 34881 | }; |
| 34882 | |
| 34883 | class rvadd8I_reduction_regNode : public MachTypeNode { |
| 34884 | private: |
| 34885 | MachOper *_opnd_array[5]; |
| 34886 | public: |
| 34887 | MachOper *opnd_array(uint operand_index) const { |
| 34888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34889 | return _opnd_array[operand_index]; |
| 34890 | } |
| 34891 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34893 | _opnd_array[operand_index] = operand; |
| 34894 | } |
| 34895 | private: |
| 34896 | virtual const RegMask &out_RegMask() const; |
| 34897 | virtual uint rule() const { return rvadd8I_reduction_reg_rule; } |
| 34898 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34899 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34900 | virtual uint oper_input_base() const { return 1; } |
| 34901 | public: |
| 34902 | rvadd8I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34903 | virtual uint size_of() const { return sizeof(rvadd8I_reduction_regNode); } |
| 34904 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34905 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34906 | static const Pipeline *pipeline_class(); |
| 34907 | virtual const Pipeline *pipeline() const; |
| 34908 | #ifndef PRODUCT |
| 34909 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34910 | virtual const char *Name() const { return "rvadd8I_reduction_reg";} |
| 34911 | #endif |
| 34912 | }; |
| 34913 | |
| 34914 | class rvadd8I_reduction_reg_evexNode : public MachTypeNode { |
| 34915 | private: |
| 34916 | MachOper *_opnd_array[5]; |
| 34917 | public: |
| 34918 | MachOper *opnd_array(uint operand_index) const { |
| 34919 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34920 | return _opnd_array[operand_index]; |
| 34921 | } |
| 34922 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34923 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34924 | _opnd_array[operand_index] = operand; |
| 34925 | } |
| 34926 | private: |
| 34927 | virtual const RegMask &out_RegMask() const; |
| 34928 | virtual uint rule() const { return rvadd8I_reduction_reg_evex_rule; } |
| 34929 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34930 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34931 | virtual uint oper_input_base() const { return 1; } |
| 34932 | public: |
| 34933 | rvadd8I_reduction_reg_evexNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34934 | virtual uint size_of() const { return sizeof(rvadd8I_reduction_reg_evexNode); } |
| 34935 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34936 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34937 | static const Pipeline *pipeline_class(); |
| 34938 | virtual const Pipeline *pipeline() const; |
| 34939 | #ifndef PRODUCT |
| 34940 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34941 | virtual const char *Name() const { return "rvadd8I_reduction_reg_evex";} |
| 34942 | #endif |
| 34943 | }; |
| 34944 | |
| 34945 | class rvadd16I_reduction_reg_evexNode : public MachTypeNode { |
| 34946 | private: |
| 34947 | MachOper *_opnd_array[6]; |
| 34948 | public: |
| 34949 | MachOper *opnd_array(uint operand_index) const { |
| 34950 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34951 | return _opnd_array[operand_index]; |
| 34952 | } |
| 34953 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34954 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34955 | _opnd_array[operand_index] = operand; |
| 34956 | } |
| 34957 | private: |
| 34958 | virtual const RegMask &out_RegMask() const; |
| 34959 | virtual uint rule() const { return rvadd16I_reduction_reg_evex_rule; } |
| 34960 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34961 | virtual int ideal_Opcode() const { return Op_AddReductionVI; } |
| 34962 | virtual uint oper_input_base() const { return 1; } |
| 34963 | public: |
| 34964 | rvadd16I_reduction_reg_evexNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 34965 | virtual uint size_of() const { return sizeof(rvadd16I_reduction_reg_evexNode); } |
| 34966 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34967 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34968 | static const Pipeline *pipeline_class(); |
| 34969 | virtual const Pipeline *pipeline() const; |
| 34970 | #ifndef PRODUCT |
| 34971 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 34972 | virtual const char *Name() const { return "rvadd16I_reduction_reg_evex";} |
| 34973 | #endif |
| 34974 | }; |
| 34975 | |
| 34976 | class rvadd2L_reduction_regNode : public MachTypeNode { |
| 34977 | private: |
| 34978 | MachOper *_opnd_array[5]; |
| 34979 | public: |
| 34980 | MachOper *opnd_array(uint operand_index) const { |
| 34981 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34982 | return _opnd_array[operand_index]; |
| 34983 | } |
| 34984 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 34985 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 34986 | _opnd_array[operand_index] = operand; |
| 34987 | } |
| 34988 | private: |
| 34989 | virtual const RegMask &out_RegMask() const; |
| 34990 | virtual uint rule() const { return rvadd2L_reduction_reg_rule; } |
| 34991 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 34992 | virtual int ideal_Opcode() const { return Op_AddReductionVL; } |
| 34993 | virtual uint oper_input_base() const { return 1; } |
| 34994 | public: |
| 34995 | rvadd2L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 34996 | virtual uint size_of() const { return sizeof(rvadd2L_reduction_regNode); } |
| 34997 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 34998 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 34999 | static const Pipeline *pipeline_class(); |
| 35000 | virtual const Pipeline *pipeline() const; |
| 35001 | #ifndef PRODUCT |
| 35002 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35003 | virtual const char *Name() const { return "rvadd2L_reduction_reg";} |
| 35004 | #endif |
| 35005 | }; |
| 35006 | |
| 35007 | class rvadd4L_reduction_regNode : public MachTypeNode { |
| 35008 | private: |
| 35009 | MachOper *_opnd_array[5]; |
| 35010 | public: |
| 35011 | MachOper *opnd_array(uint operand_index) const { |
| 35012 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35013 | return _opnd_array[operand_index]; |
| 35014 | } |
| 35015 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35017 | _opnd_array[operand_index] = operand; |
| 35018 | } |
| 35019 | private: |
| 35020 | virtual const RegMask &out_RegMask() const; |
| 35021 | virtual uint rule() const { return rvadd4L_reduction_reg_rule; } |
| 35022 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35023 | virtual int ideal_Opcode() const { return Op_AddReductionVL; } |
| 35024 | virtual uint oper_input_base() const { return 1; } |
| 35025 | public: |
| 35026 | rvadd4L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35027 | virtual uint size_of() const { return sizeof(rvadd4L_reduction_regNode); } |
| 35028 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35029 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35030 | static const Pipeline *pipeline_class(); |
| 35031 | virtual const Pipeline *pipeline() const; |
| 35032 | #ifndef PRODUCT |
| 35033 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35034 | virtual const char *Name() const { return "rvadd4L_reduction_reg";} |
| 35035 | #endif |
| 35036 | }; |
| 35037 | |
| 35038 | class rvadd8L_reduction_regNode : public MachTypeNode { |
| 35039 | private: |
| 35040 | MachOper *_opnd_array[5]; |
| 35041 | public: |
| 35042 | MachOper *opnd_array(uint operand_index) const { |
| 35043 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35044 | return _opnd_array[operand_index]; |
| 35045 | } |
| 35046 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35047 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35048 | _opnd_array[operand_index] = operand; |
| 35049 | } |
| 35050 | private: |
| 35051 | virtual const RegMask &out_RegMask() const; |
| 35052 | virtual uint rule() const { return rvadd8L_reduction_reg_rule; } |
| 35053 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35054 | virtual int ideal_Opcode() const { return Op_AddReductionVL; } |
| 35055 | virtual uint oper_input_base() const { return 1; } |
| 35056 | public: |
| 35057 | rvadd8L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35058 | virtual uint size_of() const { return sizeof(rvadd8L_reduction_regNode); } |
| 35059 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35060 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35061 | static const Pipeline *pipeline_class(); |
| 35062 | virtual const Pipeline *pipeline() const; |
| 35063 | #ifndef PRODUCT |
| 35064 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35065 | virtual const char *Name() const { return "rvadd8L_reduction_reg";} |
| 35066 | #endif |
| 35067 | }; |
| 35068 | |
| 35069 | class rsadd2F_reduction_regNode : public MachTypeNode { |
| 35070 | private: |
| 35071 | MachOper *_opnd_array[5]; |
| 35072 | public: |
| 35073 | MachOper *opnd_array(uint operand_index) const { |
| 35074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35075 | return _opnd_array[operand_index]; |
| 35076 | } |
| 35077 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35078 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35079 | _opnd_array[operand_index] = operand; |
| 35080 | } |
| 35081 | private: |
| 35082 | virtual const RegMask &out_RegMask() const; |
| 35083 | virtual uint rule() const { return rsadd2F_reduction_reg_rule; } |
| 35084 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35085 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35086 | virtual uint two_adr() const { return oper_input_base(); } |
| 35087 | virtual uint oper_input_base() const { return 1; } |
| 35088 | public: |
| 35089 | rsadd2F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35090 | virtual uint size_of() const { return sizeof(rsadd2F_reduction_regNode); } |
| 35091 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35092 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35093 | static const Pipeline *pipeline_class(); |
| 35094 | virtual const Pipeline *pipeline() const; |
| 35095 | #ifndef PRODUCT |
| 35096 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35097 | virtual const char *Name() const { return "rsadd2F_reduction_reg";} |
| 35098 | #endif |
| 35099 | }; |
| 35100 | |
| 35101 | class rvadd2F_reduction_regNode : public MachTypeNode { |
| 35102 | private: |
| 35103 | MachOper *_opnd_array[5]; |
| 35104 | public: |
| 35105 | MachOper *opnd_array(uint operand_index) const { |
| 35106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35107 | return _opnd_array[operand_index]; |
| 35108 | } |
| 35109 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35110 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35111 | _opnd_array[operand_index] = operand; |
| 35112 | } |
| 35113 | private: |
| 35114 | virtual const RegMask &out_RegMask() const; |
| 35115 | virtual uint rule() const { return rvadd2F_reduction_reg_rule; } |
| 35116 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35117 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35118 | virtual uint two_adr() const { return oper_input_base(); } |
| 35119 | virtual uint oper_input_base() const { return 1; } |
| 35120 | public: |
| 35121 | rvadd2F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35122 | virtual uint size_of() const { return sizeof(rvadd2F_reduction_regNode); } |
| 35123 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35124 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35125 | static const Pipeline *pipeline_class(); |
| 35126 | virtual const Pipeline *pipeline() const; |
| 35127 | #ifndef PRODUCT |
| 35128 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35129 | virtual const char *Name() const { return "rvadd2F_reduction_reg";} |
| 35130 | #endif |
| 35131 | }; |
| 35132 | |
| 35133 | class rsadd4F_reduction_regNode : public MachTypeNode { |
| 35134 | private: |
| 35135 | MachOper *_opnd_array[5]; |
| 35136 | public: |
| 35137 | MachOper *opnd_array(uint operand_index) const { |
| 35138 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35139 | return _opnd_array[operand_index]; |
| 35140 | } |
| 35141 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35142 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35143 | _opnd_array[operand_index] = operand; |
| 35144 | } |
| 35145 | private: |
| 35146 | virtual const RegMask &out_RegMask() const; |
| 35147 | virtual uint rule() const { return rsadd4F_reduction_reg_rule; } |
| 35148 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35149 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35150 | virtual uint two_adr() const { return oper_input_base(); } |
| 35151 | virtual uint oper_input_base() const { return 1; } |
| 35152 | public: |
| 35153 | rsadd4F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35154 | virtual uint size_of() const { return sizeof(rsadd4F_reduction_regNode); } |
| 35155 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35156 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35157 | static const Pipeline *pipeline_class(); |
| 35158 | virtual const Pipeline *pipeline() const; |
| 35159 | #ifndef PRODUCT |
| 35160 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35161 | virtual const char *Name() const { return "rsadd4F_reduction_reg";} |
| 35162 | #endif |
| 35163 | }; |
| 35164 | |
| 35165 | class rvadd4F_reduction_regNode : public MachTypeNode { |
| 35166 | private: |
| 35167 | MachOper *_opnd_array[5]; |
| 35168 | public: |
| 35169 | MachOper *opnd_array(uint operand_index) const { |
| 35170 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35171 | return _opnd_array[operand_index]; |
| 35172 | } |
| 35173 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35174 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35175 | _opnd_array[operand_index] = operand; |
| 35176 | } |
| 35177 | private: |
| 35178 | virtual const RegMask &out_RegMask() const; |
| 35179 | virtual uint rule() const { return rvadd4F_reduction_reg_rule; } |
| 35180 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35181 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35182 | virtual uint two_adr() const { return oper_input_base(); } |
| 35183 | virtual uint oper_input_base() const { return 1; } |
| 35184 | public: |
| 35185 | rvadd4F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35186 | virtual uint size_of() const { return sizeof(rvadd4F_reduction_regNode); } |
| 35187 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35188 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35189 | static const Pipeline *pipeline_class(); |
| 35190 | virtual const Pipeline *pipeline() const; |
| 35191 | #ifndef PRODUCT |
| 35192 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35193 | virtual const char *Name() const { return "rvadd4F_reduction_reg";} |
| 35194 | #endif |
| 35195 | }; |
| 35196 | |
| 35197 | class radd8F_reduction_regNode : public MachTypeNode { |
| 35198 | private: |
| 35199 | MachOper *_opnd_array[6]; |
| 35200 | public: |
| 35201 | MachOper *opnd_array(uint operand_index) const { |
| 35202 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35203 | return _opnd_array[operand_index]; |
| 35204 | } |
| 35205 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35206 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35207 | _opnd_array[operand_index] = operand; |
| 35208 | } |
| 35209 | private: |
| 35210 | virtual const RegMask &out_RegMask() const; |
| 35211 | virtual uint rule() const { return radd8F_reduction_reg_rule; } |
| 35212 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35213 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35214 | virtual uint two_adr() const { return oper_input_base(); } |
| 35215 | virtual uint oper_input_base() const { return 1; } |
| 35216 | public: |
| 35217 | radd8F_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35218 | virtual uint size_of() const { return sizeof(radd8F_reduction_regNode); } |
| 35219 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35220 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35221 | static const Pipeline *pipeline_class(); |
| 35222 | virtual const Pipeline *pipeline() const; |
| 35223 | #ifndef PRODUCT |
| 35224 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35225 | virtual const char *Name() const { return "radd8F_reduction_reg";} |
| 35226 | #endif |
| 35227 | }; |
| 35228 | |
| 35229 | class radd16F_reduction_regNode : public MachTypeNode { |
| 35230 | private: |
| 35231 | MachOper *_opnd_array[6]; |
| 35232 | public: |
| 35233 | MachOper *opnd_array(uint operand_index) const { |
| 35234 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35235 | return _opnd_array[operand_index]; |
| 35236 | } |
| 35237 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35239 | _opnd_array[operand_index] = operand; |
| 35240 | } |
| 35241 | private: |
| 35242 | virtual const RegMask &out_RegMask() const; |
| 35243 | virtual uint rule() const { return radd16F_reduction_reg_rule; } |
| 35244 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35245 | virtual int ideal_Opcode() const { return Op_AddReductionVF; } |
| 35246 | virtual uint two_adr() const { return oper_input_base(); } |
| 35247 | virtual uint oper_input_base() const { return 1; } |
| 35248 | public: |
| 35249 | radd16F_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35250 | virtual uint size_of() const { return sizeof(radd16F_reduction_regNode); } |
| 35251 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35252 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35253 | static const Pipeline *pipeline_class(); |
| 35254 | virtual const Pipeline *pipeline() const; |
| 35255 | #ifndef PRODUCT |
| 35256 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35257 | virtual const char *Name() const { return "radd16F_reduction_reg";} |
| 35258 | #endif |
| 35259 | }; |
| 35260 | |
| 35261 | class rsadd2D_reduction_regNode : public MachTypeNode { |
| 35262 | private: |
| 35263 | MachOper *_opnd_array[5]; |
| 35264 | public: |
| 35265 | MachOper *opnd_array(uint operand_index) const { |
| 35266 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35267 | return _opnd_array[operand_index]; |
| 35268 | } |
| 35269 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35271 | _opnd_array[operand_index] = operand; |
| 35272 | } |
| 35273 | private: |
| 35274 | virtual const RegMask &out_RegMask() const; |
| 35275 | virtual uint rule() const { return rsadd2D_reduction_reg_rule; } |
| 35276 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35277 | virtual int ideal_Opcode() const { return Op_AddReductionVD; } |
| 35278 | virtual uint two_adr() const { return oper_input_base(); } |
| 35279 | virtual uint oper_input_base() const { return 1; } |
| 35280 | public: |
| 35281 | rsadd2D_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35282 | virtual uint size_of() const { return sizeof(rsadd2D_reduction_regNode); } |
| 35283 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35284 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35285 | static const Pipeline *pipeline_class(); |
| 35286 | virtual const Pipeline *pipeline() const; |
| 35287 | #ifndef PRODUCT |
| 35288 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35289 | virtual const char *Name() const { return "rsadd2D_reduction_reg";} |
| 35290 | #endif |
| 35291 | }; |
| 35292 | |
| 35293 | class rvadd2D_reduction_regNode : public MachTypeNode { |
| 35294 | private: |
| 35295 | MachOper *_opnd_array[5]; |
| 35296 | public: |
| 35297 | MachOper *opnd_array(uint operand_index) const { |
| 35298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35299 | return _opnd_array[operand_index]; |
| 35300 | } |
| 35301 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35302 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35303 | _opnd_array[operand_index] = operand; |
| 35304 | } |
| 35305 | private: |
| 35306 | virtual const RegMask &out_RegMask() const; |
| 35307 | virtual uint rule() const { return rvadd2D_reduction_reg_rule; } |
| 35308 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35309 | virtual int ideal_Opcode() const { return Op_AddReductionVD; } |
| 35310 | virtual uint two_adr() const { return oper_input_base(); } |
| 35311 | virtual uint oper_input_base() const { return 1; } |
| 35312 | public: |
| 35313 | rvadd2D_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35314 | virtual uint size_of() const { return sizeof(rvadd2D_reduction_regNode); } |
| 35315 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35316 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35317 | static const Pipeline *pipeline_class(); |
| 35318 | virtual const Pipeline *pipeline() const; |
| 35319 | #ifndef PRODUCT |
| 35320 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35321 | virtual const char *Name() const { return "rvadd2D_reduction_reg";} |
| 35322 | #endif |
| 35323 | }; |
| 35324 | |
| 35325 | class rvadd4D_reduction_regNode : public MachTypeNode { |
| 35326 | private: |
| 35327 | MachOper *_opnd_array[6]; |
| 35328 | public: |
| 35329 | MachOper *opnd_array(uint operand_index) const { |
| 35330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35331 | return _opnd_array[operand_index]; |
| 35332 | } |
| 35333 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35334 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35335 | _opnd_array[operand_index] = operand; |
| 35336 | } |
| 35337 | private: |
| 35338 | virtual const RegMask &out_RegMask() const; |
| 35339 | virtual uint rule() const { return rvadd4D_reduction_reg_rule; } |
| 35340 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35341 | virtual int ideal_Opcode() const { return Op_AddReductionVD; } |
| 35342 | virtual uint two_adr() const { return oper_input_base(); } |
| 35343 | virtual uint oper_input_base() const { return 1; } |
| 35344 | public: |
| 35345 | rvadd4D_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35346 | virtual uint size_of() const { return sizeof(rvadd4D_reduction_regNode); } |
| 35347 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35348 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35349 | static const Pipeline *pipeline_class(); |
| 35350 | virtual const Pipeline *pipeline() const; |
| 35351 | #ifndef PRODUCT |
| 35352 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35353 | virtual const char *Name() const { return "rvadd4D_reduction_reg";} |
| 35354 | #endif |
| 35355 | }; |
| 35356 | |
| 35357 | class rvadd8D_reduction_regNode : public MachTypeNode { |
| 35358 | private: |
| 35359 | MachOper *_opnd_array[6]; |
| 35360 | public: |
| 35361 | MachOper *opnd_array(uint operand_index) const { |
| 35362 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35363 | return _opnd_array[operand_index]; |
| 35364 | } |
| 35365 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35366 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35367 | _opnd_array[operand_index] = operand; |
| 35368 | } |
| 35369 | private: |
| 35370 | virtual const RegMask &out_RegMask() const; |
| 35371 | virtual uint rule() const { return rvadd8D_reduction_reg_rule; } |
| 35372 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35373 | virtual int ideal_Opcode() const { return Op_AddReductionVD; } |
| 35374 | virtual uint two_adr() const { return oper_input_base(); } |
| 35375 | virtual uint oper_input_base() const { return 1; } |
| 35376 | public: |
| 35377 | rvadd8D_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35378 | virtual uint size_of() const { return sizeof(rvadd8D_reduction_regNode); } |
| 35379 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35380 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35381 | static const Pipeline *pipeline_class(); |
| 35382 | virtual const Pipeline *pipeline() const; |
| 35383 | #ifndef PRODUCT |
| 35384 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35385 | virtual const char *Name() const { return "rvadd8D_reduction_reg";} |
| 35386 | #endif |
| 35387 | }; |
| 35388 | |
| 35389 | class rsmul2I_reduction_regNode : public MachTypeNode { |
| 35390 | private: |
| 35391 | MachOper *_opnd_array[5]; |
| 35392 | public: |
| 35393 | MachOper *opnd_array(uint operand_index) const { |
| 35394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35395 | return _opnd_array[operand_index]; |
| 35396 | } |
| 35397 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35399 | _opnd_array[operand_index] = operand; |
| 35400 | } |
| 35401 | private: |
| 35402 | virtual const RegMask &out_RegMask() const; |
| 35403 | virtual uint rule() const { return rsmul2I_reduction_reg_rule; } |
| 35404 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35405 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35406 | virtual uint oper_input_base() const { return 1; } |
| 35407 | public: |
| 35408 | rsmul2I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35409 | virtual uint size_of() const { return sizeof(rsmul2I_reduction_regNode); } |
| 35410 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35411 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35412 | static const Pipeline *pipeline_class(); |
| 35413 | virtual const Pipeline *pipeline() const; |
| 35414 | #ifndef PRODUCT |
| 35415 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35416 | virtual const char *Name() const { return "rsmul2I_reduction_reg";} |
| 35417 | #endif |
| 35418 | }; |
| 35419 | |
| 35420 | class rvmul2I_reduction_regNode : public MachTypeNode { |
| 35421 | private: |
| 35422 | MachOper *_opnd_array[5]; |
| 35423 | public: |
| 35424 | MachOper *opnd_array(uint operand_index) const { |
| 35425 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35426 | return _opnd_array[operand_index]; |
| 35427 | } |
| 35428 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35429 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35430 | _opnd_array[operand_index] = operand; |
| 35431 | } |
| 35432 | private: |
| 35433 | virtual const RegMask &out_RegMask() const; |
| 35434 | virtual uint rule() const { return rvmul2I_reduction_reg_rule; } |
| 35435 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35436 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35437 | virtual uint oper_input_base() const { return 1; } |
| 35438 | public: |
| 35439 | rvmul2I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35440 | virtual uint size_of() const { return sizeof(rvmul2I_reduction_regNode); } |
| 35441 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35442 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35443 | static const Pipeline *pipeline_class(); |
| 35444 | virtual const Pipeline *pipeline() const; |
| 35445 | #ifndef PRODUCT |
| 35446 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35447 | virtual const char *Name() const { return "rvmul2I_reduction_reg";} |
| 35448 | #endif |
| 35449 | }; |
| 35450 | |
| 35451 | class rsmul4I_reduction_regNode : public MachTypeNode { |
| 35452 | private: |
| 35453 | MachOper *_opnd_array[5]; |
| 35454 | public: |
| 35455 | MachOper *opnd_array(uint operand_index) const { |
| 35456 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35457 | return _opnd_array[operand_index]; |
| 35458 | } |
| 35459 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35460 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35461 | _opnd_array[operand_index] = operand; |
| 35462 | } |
| 35463 | private: |
| 35464 | virtual const RegMask &out_RegMask() const; |
| 35465 | virtual uint rule() const { return rsmul4I_reduction_reg_rule; } |
| 35466 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35467 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35468 | virtual uint oper_input_base() const { return 1; } |
| 35469 | public: |
| 35470 | rsmul4I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35471 | virtual uint size_of() const { return sizeof(rsmul4I_reduction_regNode); } |
| 35472 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35473 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35474 | static const Pipeline *pipeline_class(); |
| 35475 | virtual const Pipeline *pipeline() const; |
| 35476 | #ifndef PRODUCT |
| 35477 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35478 | virtual const char *Name() const { return "rsmul4I_reduction_reg";} |
| 35479 | #endif |
| 35480 | }; |
| 35481 | |
| 35482 | class rvmul4I_reduction_regNode : public MachTypeNode { |
| 35483 | private: |
| 35484 | MachOper *_opnd_array[5]; |
| 35485 | public: |
| 35486 | MachOper *opnd_array(uint operand_index) const { |
| 35487 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35488 | return _opnd_array[operand_index]; |
| 35489 | } |
| 35490 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35491 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35492 | _opnd_array[operand_index] = operand; |
| 35493 | } |
| 35494 | private: |
| 35495 | virtual const RegMask &out_RegMask() const; |
| 35496 | virtual uint rule() const { return rvmul4I_reduction_reg_rule; } |
| 35497 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35498 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35499 | virtual uint oper_input_base() const { return 1; } |
| 35500 | public: |
| 35501 | rvmul4I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35502 | virtual uint size_of() const { return sizeof(rvmul4I_reduction_regNode); } |
| 35503 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35504 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35505 | static const Pipeline *pipeline_class(); |
| 35506 | virtual const Pipeline *pipeline() const; |
| 35507 | #ifndef PRODUCT |
| 35508 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35509 | virtual const char *Name() const { return "rvmul4I_reduction_reg";} |
| 35510 | #endif |
| 35511 | }; |
| 35512 | |
| 35513 | class rvmul8I_reduction_regNode : public MachTypeNode { |
| 35514 | private: |
| 35515 | MachOper *_opnd_array[5]; |
| 35516 | public: |
| 35517 | MachOper *opnd_array(uint operand_index) const { |
| 35518 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35519 | return _opnd_array[operand_index]; |
| 35520 | } |
| 35521 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35522 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35523 | _opnd_array[operand_index] = operand; |
| 35524 | } |
| 35525 | private: |
| 35526 | virtual const RegMask &out_RegMask() const; |
| 35527 | virtual uint rule() const { return rvmul8I_reduction_reg_rule; } |
| 35528 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35529 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35530 | virtual uint oper_input_base() const { return 1; } |
| 35531 | public: |
| 35532 | rvmul8I_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35533 | virtual uint size_of() const { return sizeof(rvmul8I_reduction_regNode); } |
| 35534 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35535 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35536 | static const Pipeline *pipeline_class(); |
| 35537 | virtual const Pipeline *pipeline() const; |
| 35538 | #ifndef PRODUCT |
| 35539 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35540 | virtual const char *Name() const { return "rvmul8I_reduction_reg";} |
| 35541 | #endif |
| 35542 | }; |
| 35543 | |
| 35544 | class rvmul16I_reduction_regNode : public MachTypeNode { |
| 35545 | private: |
| 35546 | MachOper *_opnd_array[6]; |
| 35547 | public: |
| 35548 | MachOper *opnd_array(uint operand_index) const { |
| 35549 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35550 | return _opnd_array[operand_index]; |
| 35551 | } |
| 35552 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35553 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35554 | _opnd_array[operand_index] = operand; |
| 35555 | } |
| 35556 | private: |
| 35557 | virtual const RegMask &out_RegMask() const; |
| 35558 | virtual uint rule() const { return rvmul16I_reduction_reg_rule; } |
| 35559 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35560 | virtual int ideal_Opcode() const { return Op_MulReductionVI; } |
| 35561 | virtual uint oper_input_base() const { return 1; } |
| 35562 | public: |
| 35563 | rvmul16I_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35564 | virtual uint size_of() const { return sizeof(rvmul16I_reduction_regNode); } |
| 35565 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35566 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35567 | static const Pipeline *pipeline_class(); |
| 35568 | virtual const Pipeline *pipeline() const; |
| 35569 | #ifndef PRODUCT |
| 35570 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35571 | virtual const char *Name() const { return "rvmul16I_reduction_reg";} |
| 35572 | #endif |
| 35573 | }; |
| 35574 | |
| 35575 | class rvmul2L_reduction_regNode : public MachTypeNode { |
| 35576 | private: |
| 35577 | MachOper *_opnd_array[5]; |
| 35578 | public: |
| 35579 | MachOper *opnd_array(uint operand_index) const { |
| 35580 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35581 | return _opnd_array[operand_index]; |
| 35582 | } |
| 35583 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35584 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35585 | _opnd_array[operand_index] = operand; |
| 35586 | } |
| 35587 | private: |
| 35588 | virtual const RegMask &out_RegMask() const; |
| 35589 | virtual uint rule() const { return rvmul2L_reduction_reg_rule; } |
| 35590 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35591 | virtual int ideal_Opcode() const { return Op_MulReductionVL; } |
| 35592 | virtual uint oper_input_base() const { return 1; } |
| 35593 | public: |
| 35594 | rvmul2L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35595 | virtual uint size_of() const { return sizeof(rvmul2L_reduction_regNode); } |
| 35596 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35597 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35598 | static const Pipeline *pipeline_class(); |
| 35599 | virtual const Pipeline *pipeline() const; |
| 35600 | #ifndef PRODUCT |
| 35601 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35602 | virtual const char *Name() const { return "rvmul2L_reduction_reg";} |
| 35603 | #endif |
| 35604 | }; |
| 35605 | |
| 35606 | class rvmul4L_reduction_regNode : public MachTypeNode { |
| 35607 | private: |
| 35608 | MachOper *_opnd_array[5]; |
| 35609 | public: |
| 35610 | MachOper *opnd_array(uint operand_index) const { |
| 35611 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35612 | return _opnd_array[operand_index]; |
| 35613 | } |
| 35614 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35615 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35616 | _opnd_array[operand_index] = operand; |
| 35617 | } |
| 35618 | private: |
| 35619 | virtual const RegMask &out_RegMask() const; |
| 35620 | virtual uint rule() const { return rvmul4L_reduction_reg_rule; } |
| 35621 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35622 | virtual int ideal_Opcode() const { return Op_MulReductionVL; } |
| 35623 | virtual uint oper_input_base() const { return 1; } |
| 35624 | public: |
| 35625 | rvmul4L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35626 | virtual uint size_of() const { return sizeof(rvmul4L_reduction_regNode); } |
| 35627 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35628 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35629 | static const Pipeline *pipeline_class(); |
| 35630 | virtual const Pipeline *pipeline() const; |
| 35631 | #ifndef PRODUCT |
| 35632 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35633 | virtual const char *Name() const { return "rvmul4L_reduction_reg";} |
| 35634 | #endif |
| 35635 | }; |
| 35636 | |
| 35637 | class rvmul8L_reduction_regNode : public MachTypeNode { |
| 35638 | private: |
| 35639 | MachOper *_opnd_array[5]; |
| 35640 | public: |
| 35641 | MachOper *opnd_array(uint operand_index) const { |
| 35642 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35643 | return _opnd_array[operand_index]; |
| 35644 | } |
| 35645 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35646 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35647 | _opnd_array[operand_index] = operand; |
| 35648 | } |
| 35649 | private: |
| 35650 | virtual const RegMask &out_RegMask() const; |
| 35651 | virtual uint rule() const { return rvmul8L_reduction_reg_rule; } |
| 35652 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35653 | virtual int ideal_Opcode() const { return Op_MulReductionVL; } |
| 35654 | virtual uint oper_input_base() const { return 1; } |
| 35655 | public: |
| 35656 | rvmul8L_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35657 | virtual uint size_of() const { return sizeof(rvmul8L_reduction_regNode); } |
| 35658 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35659 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35660 | static const Pipeline *pipeline_class(); |
| 35661 | virtual const Pipeline *pipeline() const; |
| 35662 | #ifndef PRODUCT |
| 35663 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35664 | virtual const char *Name() const { return "rvmul8L_reduction_reg";} |
| 35665 | #endif |
| 35666 | }; |
| 35667 | |
| 35668 | class rsmul2F_reductionNode : public MachTypeNode { |
| 35669 | private: |
| 35670 | MachOper *_opnd_array[5]; |
| 35671 | public: |
| 35672 | MachOper *opnd_array(uint operand_index) const { |
| 35673 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35674 | return _opnd_array[operand_index]; |
| 35675 | } |
| 35676 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35677 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35678 | _opnd_array[operand_index] = operand; |
| 35679 | } |
| 35680 | private: |
| 35681 | virtual const RegMask &out_RegMask() const; |
| 35682 | virtual uint rule() const { return rsmul2F_reduction_rule; } |
| 35683 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35684 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35685 | virtual uint two_adr() const { return oper_input_base(); } |
| 35686 | virtual uint oper_input_base() const { return 1; } |
| 35687 | public: |
| 35688 | rsmul2F_reductionNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35689 | virtual uint size_of() const { return sizeof(rsmul2F_reductionNode); } |
| 35690 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35691 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35692 | static const Pipeline *pipeline_class(); |
| 35693 | virtual const Pipeline *pipeline() const; |
| 35694 | #ifndef PRODUCT |
| 35695 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35696 | virtual const char *Name() const { return "rsmul2F_reduction";} |
| 35697 | #endif |
| 35698 | }; |
| 35699 | |
| 35700 | class rvmul2F_reduction_regNode : public MachTypeNode { |
| 35701 | private: |
| 35702 | MachOper *_opnd_array[5]; |
| 35703 | public: |
| 35704 | MachOper *opnd_array(uint operand_index) const { |
| 35705 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35706 | return _opnd_array[operand_index]; |
| 35707 | } |
| 35708 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35709 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35710 | _opnd_array[operand_index] = operand; |
| 35711 | } |
| 35712 | private: |
| 35713 | virtual const RegMask &out_RegMask() const; |
| 35714 | virtual uint rule() const { return rvmul2F_reduction_reg_rule; } |
| 35715 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35716 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35717 | virtual uint two_adr() const { return oper_input_base(); } |
| 35718 | virtual uint oper_input_base() const { return 1; } |
| 35719 | public: |
| 35720 | rvmul2F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35721 | virtual uint size_of() const { return sizeof(rvmul2F_reduction_regNode); } |
| 35722 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35723 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35724 | static const Pipeline *pipeline_class(); |
| 35725 | virtual const Pipeline *pipeline() const; |
| 35726 | #ifndef PRODUCT |
| 35727 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35728 | virtual const char *Name() const { return "rvmul2F_reduction_reg";} |
| 35729 | #endif |
| 35730 | }; |
| 35731 | |
| 35732 | class rsmul4F_reduction_regNode : public MachTypeNode { |
| 35733 | private: |
| 35734 | MachOper *_opnd_array[5]; |
| 35735 | public: |
| 35736 | MachOper *opnd_array(uint operand_index) const { |
| 35737 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35738 | return _opnd_array[operand_index]; |
| 35739 | } |
| 35740 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35741 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35742 | _opnd_array[operand_index] = operand; |
| 35743 | } |
| 35744 | private: |
| 35745 | virtual const RegMask &out_RegMask() const; |
| 35746 | virtual uint rule() const { return rsmul4F_reduction_reg_rule; } |
| 35747 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35748 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35749 | virtual uint two_adr() const { return oper_input_base(); } |
| 35750 | virtual uint oper_input_base() const { return 1; } |
| 35751 | public: |
| 35752 | rsmul4F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35753 | virtual uint size_of() const { return sizeof(rsmul4F_reduction_regNode); } |
| 35754 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35755 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35756 | static const Pipeline *pipeline_class(); |
| 35757 | virtual const Pipeline *pipeline() const; |
| 35758 | #ifndef PRODUCT |
| 35759 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35760 | virtual const char *Name() const { return "rsmul4F_reduction_reg";} |
| 35761 | #endif |
| 35762 | }; |
| 35763 | |
| 35764 | class rvmul4F_reduction_regNode : public MachTypeNode { |
| 35765 | private: |
| 35766 | MachOper *_opnd_array[5]; |
| 35767 | public: |
| 35768 | MachOper *opnd_array(uint operand_index) const { |
| 35769 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35770 | return _opnd_array[operand_index]; |
| 35771 | } |
| 35772 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35773 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35774 | _opnd_array[operand_index] = operand; |
| 35775 | } |
| 35776 | private: |
| 35777 | virtual const RegMask &out_RegMask() const; |
| 35778 | virtual uint rule() const { return rvmul4F_reduction_reg_rule; } |
| 35779 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35780 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35781 | virtual uint two_adr() const { return oper_input_base(); } |
| 35782 | virtual uint oper_input_base() const { return 1; } |
| 35783 | public: |
| 35784 | rvmul4F_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35785 | virtual uint size_of() const { return sizeof(rvmul4F_reduction_regNode); } |
| 35786 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35787 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35788 | static const Pipeline *pipeline_class(); |
| 35789 | virtual const Pipeline *pipeline() const; |
| 35790 | #ifndef PRODUCT |
| 35791 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35792 | virtual const char *Name() const { return "rvmul4F_reduction_reg";} |
| 35793 | #endif |
| 35794 | }; |
| 35795 | |
| 35796 | class rvmul8F_reduction_regNode : public MachTypeNode { |
| 35797 | private: |
| 35798 | MachOper *_opnd_array[6]; |
| 35799 | public: |
| 35800 | MachOper *opnd_array(uint operand_index) const { |
| 35801 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35802 | return _opnd_array[operand_index]; |
| 35803 | } |
| 35804 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35806 | _opnd_array[operand_index] = operand; |
| 35807 | } |
| 35808 | private: |
| 35809 | virtual const RegMask &out_RegMask() const; |
| 35810 | virtual uint rule() const { return rvmul8F_reduction_reg_rule; } |
| 35811 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35812 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35813 | virtual uint two_adr() const { return oper_input_base(); } |
| 35814 | virtual uint oper_input_base() const { return 1; } |
| 35815 | public: |
| 35816 | rvmul8F_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35817 | virtual uint size_of() const { return sizeof(rvmul8F_reduction_regNode); } |
| 35818 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35819 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35820 | static const Pipeline *pipeline_class(); |
| 35821 | virtual const Pipeline *pipeline() const; |
| 35822 | #ifndef PRODUCT |
| 35823 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35824 | virtual const char *Name() const { return "rvmul8F_reduction_reg";} |
| 35825 | #endif |
| 35826 | }; |
| 35827 | |
| 35828 | class rvmul16F_reduction_regNode : public MachTypeNode { |
| 35829 | private: |
| 35830 | MachOper *_opnd_array[6]; |
| 35831 | public: |
| 35832 | MachOper *opnd_array(uint operand_index) const { |
| 35833 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35834 | return _opnd_array[operand_index]; |
| 35835 | } |
| 35836 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35837 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35838 | _opnd_array[operand_index] = operand; |
| 35839 | } |
| 35840 | private: |
| 35841 | virtual const RegMask &out_RegMask() const; |
| 35842 | virtual uint rule() const { return rvmul16F_reduction_reg_rule; } |
| 35843 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35844 | virtual int ideal_Opcode() const { return Op_MulReductionVF; } |
| 35845 | virtual uint two_adr() const { return oper_input_base(); } |
| 35846 | virtual uint oper_input_base() const { return 1; } |
| 35847 | public: |
| 35848 | rvmul16F_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35849 | virtual uint size_of() const { return sizeof(rvmul16F_reduction_regNode); } |
| 35850 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35851 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35852 | static const Pipeline *pipeline_class(); |
| 35853 | virtual const Pipeline *pipeline() const; |
| 35854 | #ifndef PRODUCT |
| 35855 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35856 | virtual const char *Name() const { return "rvmul16F_reduction_reg";} |
| 35857 | #endif |
| 35858 | }; |
| 35859 | |
| 35860 | class rsmul2D_reduction_regNode : public MachTypeNode { |
| 35861 | private: |
| 35862 | MachOper *_opnd_array[5]; |
| 35863 | public: |
| 35864 | MachOper *opnd_array(uint operand_index) const { |
| 35865 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35866 | return _opnd_array[operand_index]; |
| 35867 | } |
| 35868 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35869 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35870 | _opnd_array[operand_index] = operand; |
| 35871 | } |
| 35872 | private: |
| 35873 | virtual const RegMask &out_RegMask() const; |
| 35874 | virtual uint rule() const { return rsmul2D_reduction_reg_rule; } |
| 35875 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35876 | virtual int ideal_Opcode() const { return Op_MulReductionVD; } |
| 35877 | virtual uint two_adr() const { return oper_input_base(); } |
| 35878 | virtual uint oper_input_base() const { return 1; } |
| 35879 | public: |
| 35880 | rsmul2D_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35881 | virtual uint size_of() const { return sizeof(rsmul2D_reduction_regNode); } |
| 35882 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35883 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35884 | static const Pipeline *pipeline_class(); |
| 35885 | virtual const Pipeline *pipeline() const; |
| 35886 | #ifndef PRODUCT |
| 35887 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35888 | virtual const char *Name() const { return "rsmul2D_reduction_reg";} |
| 35889 | #endif |
| 35890 | }; |
| 35891 | |
| 35892 | class rvmul2D_reduction_regNode : public MachTypeNode { |
| 35893 | private: |
| 35894 | MachOper *_opnd_array[5]; |
| 35895 | public: |
| 35896 | MachOper *opnd_array(uint operand_index) const { |
| 35897 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35898 | return _opnd_array[operand_index]; |
| 35899 | } |
| 35900 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35902 | _opnd_array[operand_index] = operand; |
| 35903 | } |
| 35904 | private: |
| 35905 | virtual const RegMask &out_RegMask() const; |
| 35906 | virtual uint rule() const { return rvmul2D_reduction_reg_rule; } |
| 35907 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35908 | virtual int ideal_Opcode() const { return Op_MulReductionVD; } |
| 35909 | virtual uint two_adr() const { return oper_input_base(); } |
| 35910 | virtual uint oper_input_base() const { return 1; } |
| 35911 | public: |
| 35912 | rvmul2D_reduction_regNode() { _num_opnds = 5; _opnds = _opnd_array; } |
| 35913 | virtual uint size_of() const { return sizeof(rvmul2D_reduction_regNode); } |
| 35914 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35915 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35916 | static const Pipeline *pipeline_class(); |
| 35917 | virtual const Pipeline *pipeline() const; |
| 35918 | #ifndef PRODUCT |
| 35919 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35920 | virtual const char *Name() const { return "rvmul2D_reduction_reg";} |
| 35921 | #endif |
| 35922 | }; |
| 35923 | |
| 35924 | class rvmul4D_reduction_regNode : public MachTypeNode { |
| 35925 | private: |
| 35926 | MachOper *_opnd_array[6]; |
| 35927 | public: |
| 35928 | MachOper *opnd_array(uint operand_index) const { |
| 35929 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35930 | return _opnd_array[operand_index]; |
| 35931 | } |
| 35932 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35933 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35934 | _opnd_array[operand_index] = operand; |
| 35935 | } |
| 35936 | private: |
| 35937 | virtual const RegMask &out_RegMask() const; |
| 35938 | virtual uint rule() const { return rvmul4D_reduction_reg_rule; } |
| 35939 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35940 | virtual int ideal_Opcode() const { return Op_MulReductionVD; } |
| 35941 | virtual uint two_adr() const { return oper_input_base(); } |
| 35942 | virtual uint oper_input_base() const { return 1; } |
| 35943 | public: |
| 35944 | rvmul4D_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35945 | virtual uint size_of() const { return sizeof(rvmul4D_reduction_regNode); } |
| 35946 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35947 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35948 | static const Pipeline *pipeline_class(); |
| 35949 | virtual const Pipeline *pipeline() const; |
| 35950 | #ifndef PRODUCT |
| 35951 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35952 | virtual const char *Name() const { return "rvmul4D_reduction_reg";} |
| 35953 | #endif |
| 35954 | }; |
| 35955 | |
| 35956 | class rvmul8D_reduction_regNode : public MachTypeNode { |
| 35957 | private: |
| 35958 | MachOper *_opnd_array[6]; |
| 35959 | public: |
| 35960 | MachOper *opnd_array(uint operand_index) const { |
| 35961 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35962 | return _opnd_array[operand_index]; |
| 35963 | } |
| 35964 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35966 | _opnd_array[operand_index] = operand; |
| 35967 | } |
| 35968 | private: |
| 35969 | virtual const RegMask &out_RegMask() const; |
| 35970 | virtual uint rule() const { return rvmul8D_reduction_reg_rule; } |
| 35971 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 35972 | virtual int ideal_Opcode() const { return Op_MulReductionVD; } |
| 35973 | virtual uint two_adr() const { return oper_input_base(); } |
| 35974 | virtual uint oper_input_base() const { return 1; } |
| 35975 | public: |
| 35976 | rvmul8D_reduction_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 35977 | virtual uint size_of() const { return sizeof(rvmul8D_reduction_regNode); } |
| 35978 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 35979 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 35980 | static const Pipeline *pipeline_class(); |
| 35981 | virtual const Pipeline *pipeline() const; |
| 35982 | #ifndef PRODUCT |
| 35983 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 35984 | virtual const char *Name() const { return "rvmul8D_reduction_reg";} |
| 35985 | #endif |
| 35986 | }; |
| 35987 | |
| 35988 | class vadd4BNode : public MachTypeNode { |
| 35989 | private: |
| 35990 | MachOper *_opnd_array[3]; |
| 35991 | public: |
| 35992 | MachOper *opnd_array(uint operand_index) const { |
| 35993 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35994 | return _opnd_array[operand_index]; |
| 35995 | } |
| 35996 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 35997 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 35998 | _opnd_array[operand_index] = operand; |
| 35999 | } |
| 36000 | private: |
| 36001 | virtual const RegMask &out_RegMask() const; |
| 36002 | virtual uint rule() const { return vadd4B_rule; } |
| 36003 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36004 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36005 | virtual uint two_adr() const { return oper_input_base(); } |
| 36006 | virtual uint oper_input_base() const { return 1; } |
| 36007 | public: |
| 36008 | vadd4BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36009 | virtual uint size_of() const { return sizeof(vadd4BNode); } |
| 36010 | static const Pipeline *pipeline_class(); |
| 36011 | virtual const Pipeline *pipeline() const; |
| 36012 | #ifndef PRODUCT |
| 36013 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36014 | virtual const char *Name() const { return "vadd4B";} |
| 36015 | #endif |
| 36016 | }; |
| 36017 | |
| 36018 | class vadd4B_regNode : public MachTypeNode { |
| 36019 | private: |
| 36020 | MachOper *_opnd_array[3]; |
| 36021 | public: |
| 36022 | MachOper *opnd_array(uint operand_index) const { |
| 36023 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36024 | return _opnd_array[operand_index]; |
| 36025 | } |
| 36026 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36027 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36028 | _opnd_array[operand_index] = operand; |
| 36029 | } |
| 36030 | private: |
| 36031 | virtual const RegMask &out_RegMask() const; |
| 36032 | virtual uint rule() const { return vadd4B_reg_rule; } |
| 36033 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36034 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36035 | virtual uint oper_input_base() const { return 1; } |
| 36036 | public: |
| 36037 | vadd4B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36038 | virtual uint size_of() const { return sizeof(vadd4B_regNode); } |
| 36039 | static const Pipeline *pipeline_class(); |
| 36040 | virtual const Pipeline *pipeline() const; |
| 36041 | #ifndef PRODUCT |
| 36042 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36043 | virtual const char *Name() const { return "vadd4B_reg";} |
| 36044 | #endif |
| 36045 | }; |
| 36046 | |
| 36047 | class vadd4B_memNode : public MachTypeNode { |
| 36048 | private: |
| 36049 | MachOper *_opnd_array[3]; |
| 36050 | public: |
| 36051 | MachOper *opnd_array(uint operand_index) const { |
| 36052 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36053 | return _opnd_array[operand_index]; |
| 36054 | } |
| 36055 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36056 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36057 | _opnd_array[operand_index] = operand; |
| 36058 | } |
| 36059 | private: |
| 36060 | virtual const RegMask &out_RegMask() const; |
| 36061 | virtual uint rule() const { return vadd4B_mem_rule; } |
| 36062 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36063 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36064 | virtual int reloc() const; |
| 36065 | virtual uint oper_input_base() const { return 2; } |
| 36066 | public: |
| 36067 | vadd4B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36068 | virtual uint size_of() const { return sizeof(vadd4B_memNode); } |
| 36069 | static const Pipeline *pipeline_class(); |
| 36070 | virtual const Pipeline *pipeline() const; |
| 36071 | virtual const MachOper *memory_operand() const; |
| 36072 | #ifndef PRODUCT |
| 36073 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36074 | virtual const char *Name() const { return "vadd4B_mem";} |
| 36075 | #endif |
| 36076 | }; |
| 36077 | |
| 36078 | class vadd4B_mem_0Node : public MachTypeNode { |
| 36079 | private: |
| 36080 | MachOper *_opnd_array[3]; |
| 36081 | public: |
| 36082 | MachOper *opnd_array(uint operand_index) const { |
| 36083 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36084 | return _opnd_array[operand_index]; |
| 36085 | } |
| 36086 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36087 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36088 | _opnd_array[operand_index] = operand; |
| 36089 | } |
| 36090 | private: |
| 36091 | virtual const RegMask &out_RegMask() const; |
| 36092 | virtual uint rule() const { return vadd4B_mem_0_rule; } |
| 36093 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36094 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36095 | virtual int reloc() const; |
| 36096 | virtual uint oper_input_base() const { return 2; } |
| 36097 | public: |
| 36098 | vadd4B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36099 | virtual uint size_of() const { return sizeof(vadd4B_mem_0Node); } |
| 36100 | static const Pipeline *pipeline_class(); |
| 36101 | virtual const Pipeline *pipeline() const; |
| 36102 | virtual const MachOper *memory_operand() const; |
| 36103 | #ifndef PRODUCT |
| 36104 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36105 | virtual const char *Name() const { return "vadd4B_mem_0";} |
| 36106 | #endif |
| 36107 | }; |
| 36108 | |
| 36109 | class vadd8BNode : public MachTypeNode { |
| 36110 | private: |
| 36111 | MachOper *_opnd_array[3]; |
| 36112 | public: |
| 36113 | MachOper *opnd_array(uint operand_index) const { |
| 36114 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36115 | return _opnd_array[operand_index]; |
| 36116 | } |
| 36117 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36118 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36119 | _opnd_array[operand_index] = operand; |
| 36120 | } |
| 36121 | private: |
| 36122 | virtual const RegMask &out_RegMask() const; |
| 36123 | virtual uint rule() const { return vadd8B_rule; } |
| 36124 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36125 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36126 | virtual uint two_adr() const { return oper_input_base(); } |
| 36127 | virtual uint oper_input_base() const { return 1; } |
| 36128 | public: |
| 36129 | vadd8BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36130 | virtual uint size_of() const { return sizeof(vadd8BNode); } |
| 36131 | static const Pipeline *pipeline_class(); |
| 36132 | virtual const Pipeline *pipeline() const; |
| 36133 | #ifndef PRODUCT |
| 36134 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36135 | virtual const char *Name() const { return "vadd8B";} |
| 36136 | #endif |
| 36137 | }; |
| 36138 | |
| 36139 | class vadd8B_regNode : public MachTypeNode { |
| 36140 | private: |
| 36141 | MachOper *_opnd_array[3]; |
| 36142 | public: |
| 36143 | MachOper *opnd_array(uint operand_index) const { |
| 36144 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36145 | return _opnd_array[operand_index]; |
| 36146 | } |
| 36147 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36148 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36149 | _opnd_array[operand_index] = operand; |
| 36150 | } |
| 36151 | private: |
| 36152 | virtual const RegMask &out_RegMask() const; |
| 36153 | virtual uint rule() const { return vadd8B_reg_rule; } |
| 36154 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36155 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36156 | virtual uint oper_input_base() const { return 1; } |
| 36157 | public: |
| 36158 | vadd8B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36159 | virtual uint size_of() const { return sizeof(vadd8B_regNode); } |
| 36160 | static const Pipeline *pipeline_class(); |
| 36161 | virtual const Pipeline *pipeline() const; |
| 36162 | #ifndef PRODUCT |
| 36163 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36164 | virtual const char *Name() const { return "vadd8B_reg";} |
| 36165 | #endif |
| 36166 | }; |
| 36167 | |
| 36168 | class vadd8B_memNode : public MachTypeNode { |
| 36169 | private: |
| 36170 | MachOper *_opnd_array[3]; |
| 36171 | public: |
| 36172 | MachOper *opnd_array(uint operand_index) const { |
| 36173 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36174 | return _opnd_array[operand_index]; |
| 36175 | } |
| 36176 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36177 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36178 | _opnd_array[operand_index] = operand; |
| 36179 | } |
| 36180 | private: |
| 36181 | virtual const RegMask &out_RegMask() const; |
| 36182 | virtual uint rule() const { return vadd8B_mem_rule; } |
| 36183 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36184 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36185 | virtual int reloc() const; |
| 36186 | virtual uint oper_input_base() const { return 2; } |
| 36187 | public: |
| 36188 | vadd8B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36189 | virtual uint size_of() const { return sizeof(vadd8B_memNode); } |
| 36190 | static const Pipeline *pipeline_class(); |
| 36191 | virtual const Pipeline *pipeline() const; |
| 36192 | virtual const MachOper *memory_operand() const; |
| 36193 | #ifndef PRODUCT |
| 36194 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36195 | virtual const char *Name() const { return "vadd8B_mem";} |
| 36196 | #endif |
| 36197 | }; |
| 36198 | |
| 36199 | class vadd8B_mem_0Node : public MachTypeNode { |
| 36200 | private: |
| 36201 | MachOper *_opnd_array[3]; |
| 36202 | public: |
| 36203 | MachOper *opnd_array(uint operand_index) const { |
| 36204 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36205 | return _opnd_array[operand_index]; |
| 36206 | } |
| 36207 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36209 | _opnd_array[operand_index] = operand; |
| 36210 | } |
| 36211 | private: |
| 36212 | virtual const RegMask &out_RegMask() const; |
| 36213 | virtual uint rule() const { return vadd8B_mem_0_rule; } |
| 36214 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36215 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36216 | virtual int reloc() const; |
| 36217 | virtual uint oper_input_base() const { return 2; } |
| 36218 | public: |
| 36219 | vadd8B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36220 | virtual uint size_of() const { return sizeof(vadd8B_mem_0Node); } |
| 36221 | static const Pipeline *pipeline_class(); |
| 36222 | virtual const Pipeline *pipeline() const; |
| 36223 | virtual const MachOper *memory_operand() const; |
| 36224 | #ifndef PRODUCT |
| 36225 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36226 | virtual const char *Name() const { return "vadd8B_mem_0";} |
| 36227 | #endif |
| 36228 | }; |
| 36229 | |
| 36230 | class vadd16BNode : public MachTypeNode { |
| 36231 | private: |
| 36232 | MachOper *_opnd_array[3]; |
| 36233 | public: |
| 36234 | MachOper *opnd_array(uint operand_index) const { |
| 36235 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36236 | return _opnd_array[operand_index]; |
| 36237 | } |
| 36238 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36239 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36240 | _opnd_array[operand_index] = operand; |
| 36241 | } |
| 36242 | private: |
| 36243 | virtual const RegMask &out_RegMask() const; |
| 36244 | virtual uint rule() const { return vadd16B_rule; } |
| 36245 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36246 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36247 | virtual uint two_adr() const { return oper_input_base(); } |
| 36248 | virtual uint oper_input_base() const { return 1; } |
| 36249 | public: |
| 36250 | vadd16BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36251 | virtual uint size_of() const { return sizeof(vadd16BNode); } |
| 36252 | static const Pipeline *pipeline_class(); |
| 36253 | virtual const Pipeline *pipeline() const; |
| 36254 | #ifndef PRODUCT |
| 36255 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36256 | virtual const char *Name() const { return "vadd16B";} |
| 36257 | #endif |
| 36258 | }; |
| 36259 | |
| 36260 | class vadd16B_regNode : public MachTypeNode { |
| 36261 | private: |
| 36262 | MachOper *_opnd_array[3]; |
| 36263 | public: |
| 36264 | MachOper *opnd_array(uint operand_index) const { |
| 36265 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36266 | return _opnd_array[operand_index]; |
| 36267 | } |
| 36268 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36269 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36270 | _opnd_array[operand_index] = operand; |
| 36271 | } |
| 36272 | private: |
| 36273 | virtual const RegMask &out_RegMask() const; |
| 36274 | virtual uint rule() const { return vadd16B_reg_rule; } |
| 36275 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36276 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36277 | virtual uint oper_input_base() const { return 1; } |
| 36278 | public: |
| 36279 | vadd16B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36280 | virtual uint size_of() const { return sizeof(vadd16B_regNode); } |
| 36281 | static const Pipeline *pipeline_class(); |
| 36282 | virtual const Pipeline *pipeline() const; |
| 36283 | #ifndef PRODUCT |
| 36284 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36285 | virtual const char *Name() const { return "vadd16B_reg";} |
| 36286 | #endif |
| 36287 | }; |
| 36288 | |
| 36289 | class vadd16B_memNode : public MachTypeNode { |
| 36290 | private: |
| 36291 | MachOper *_opnd_array[3]; |
| 36292 | public: |
| 36293 | MachOper *opnd_array(uint operand_index) const { |
| 36294 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36295 | return _opnd_array[operand_index]; |
| 36296 | } |
| 36297 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36299 | _opnd_array[operand_index] = operand; |
| 36300 | } |
| 36301 | private: |
| 36302 | virtual const RegMask &out_RegMask() const; |
| 36303 | virtual uint rule() const { return vadd16B_mem_rule; } |
| 36304 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36305 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36306 | virtual int reloc() const; |
| 36307 | virtual uint oper_input_base() const { return 2; } |
| 36308 | public: |
| 36309 | vadd16B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36310 | virtual uint size_of() const { return sizeof(vadd16B_memNode); } |
| 36311 | static const Pipeline *pipeline_class(); |
| 36312 | virtual const Pipeline *pipeline() const; |
| 36313 | virtual const MachOper *memory_operand() const; |
| 36314 | #ifndef PRODUCT |
| 36315 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36316 | virtual const char *Name() const { return "vadd16B_mem";} |
| 36317 | #endif |
| 36318 | }; |
| 36319 | |
| 36320 | class vadd16B_mem_0Node : public MachTypeNode { |
| 36321 | private: |
| 36322 | MachOper *_opnd_array[3]; |
| 36323 | public: |
| 36324 | MachOper *opnd_array(uint operand_index) const { |
| 36325 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36326 | return _opnd_array[operand_index]; |
| 36327 | } |
| 36328 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36329 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36330 | _opnd_array[operand_index] = operand; |
| 36331 | } |
| 36332 | private: |
| 36333 | virtual const RegMask &out_RegMask() const; |
| 36334 | virtual uint rule() const { return vadd16B_mem_0_rule; } |
| 36335 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36336 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36337 | virtual int reloc() const; |
| 36338 | virtual uint oper_input_base() const { return 2; } |
| 36339 | public: |
| 36340 | vadd16B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36341 | virtual uint size_of() const { return sizeof(vadd16B_mem_0Node); } |
| 36342 | static const Pipeline *pipeline_class(); |
| 36343 | virtual const Pipeline *pipeline() const; |
| 36344 | virtual const MachOper *memory_operand() const; |
| 36345 | #ifndef PRODUCT |
| 36346 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36347 | virtual const char *Name() const { return "vadd16B_mem_0";} |
| 36348 | #endif |
| 36349 | }; |
| 36350 | |
| 36351 | class vadd32B_regNode : public MachTypeNode { |
| 36352 | private: |
| 36353 | MachOper *_opnd_array[3]; |
| 36354 | public: |
| 36355 | MachOper *opnd_array(uint operand_index) const { |
| 36356 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36357 | return _opnd_array[operand_index]; |
| 36358 | } |
| 36359 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36361 | _opnd_array[operand_index] = operand; |
| 36362 | } |
| 36363 | private: |
| 36364 | virtual const RegMask &out_RegMask() const; |
| 36365 | virtual uint rule() const { return vadd32B_reg_rule; } |
| 36366 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36367 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36368 | virtual uint oper_input_base() const { return 1; } |
| 36369 | public: |
| 36370 | vadd32B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36371 | virtual uint size_of() const { return sizeof(vadd32B_regNode); } |
| 36372 | static const Pipeline *pipeline_class(); |
| 36373 | virtual const Pipeline *pipeline() const; |
| 36374 | #ifndef PRODUCT |
| 36375 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36376 | virtual const char *Name() const { return "vadd32B_reg";} |
| 36377 | #endif |
| 36378 | }; |
| 36379 | |
| 36380 | class vadd32B_memNode : public MachTypeNode { |
| 36381 | private: |
| 36382 | MachOper *_opnd_array[3]; |
| 36383 | public: |
| 36384 | MachOper *opnd_array(uint operand_index) const { |
| 36385 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36386 | return _opnd_array[operand_index]; |
| 36387 | } |
| 36388 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36389 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36390 | _opnd_array[operand_index] = operand; |
| 36391 | } |
| 36392 | private: |
| 36393 | virtual const RegMask &out_RegMask() const; |
| 36394 | virtual uint rule() const { return vadd32B_mem_rule; } |
| 36395 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36396 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36397 | virtual int reloc() const; |
| 36398 | virtual uint oper_input_base() const { return 2; } |
| 36399 | public: |
| 36400 | vadd32B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36401 | virtual uint size_of() const { return sizeof(vadd32B_memNode); } |
| 36402 | static const Pipeline *pipeline_class(); |
| 36403 | virtual const Pipeline *pipeline() const; |
| 36404 | virtual const MachOper *memory_operand() const; |
| 36405 | #ifndef PRODUCT |
| 36406 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36407 | virtual const char *Name() const { return "vadd32B_mem";} |
| 36408 | #endif |
| 36409 | }; |
| 36410 | |
| 36411 | class vadd32B_mem_0Node : public MachTypeNode { |
| 36412 | private: |
| 36413 | MachOper *_opnd_array[3]; |
| 36414 | public: |
| 36415 | MachOper *opnd_array(uint operand_index) const { |
| 36416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36417 | return _opnd_array[operand_index]; |
| 36418 | } |
| 36419 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36420 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36421 | _opnd_array[operand_index] = operand; |
| 36422 | } |
| 36423 | private: |
| 36424 | virtual const RegMask &out_RegMask() const; |
| 36425 | virtual uint rule() const { return vadd32B_mem_0_rule; } |
| 36426 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36427 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36428 | virtual int reloc() const; |
| 36429 | virtual uint oper_input_base() const { return 2; } |
| 36430 | public: |
| 36431 | vadd32B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36432 | virtual uint size_of() const { return sizeof(vadd32B_mem_0Node); } |
| 36433 | static const Pipeline *pipeline_class(); |
| 36434 | virtual const Pipeline *pipeline() const; |
| 36435 | virtual const MachOper *memory_operand() const; |
| 36436 | #ifndef PRODUCT |
| 36437 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36438 | virtual const char *Name() const { return "vadd32B_mem_0";} |
| 36439 | #endif |
| 36440 | }; |
| 36441 | |
| 36442 | class vadd64B_regNode : public MachTypeNode { |
| 36443 | private: |
| 36444 | MachOper *_opnd_array[3]; |
| 36445 | public: |
| 36446 | MachOper *opnd_array(uint operand_index) const { |
| 36447 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36448 | return _opnd_array[operand_index]; |
| 36449 | } |
| 36450 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36451 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36452 | _opnd_array[operand_index] = operand; |
| 36453 | } |
| 36454 | private: |
| 36455 | virtual const RegMask &out_RegMask() const; |
| 36456 | virtual uint rule() const { return vadd64B_reg_rule; } |
| 36457 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36458 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36459 | virtual uint oper_input_base() const { return 1; } |
| 36460 | public: |
| 36461 | vadd64B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36462 | virtual uint size_of() const { return sizeof(vadd64B_regNode); } |
| 36463 | static const Pipeline *pipeline_class(); |
| 36464 | virtual const Pipeline *pipeline() const; |
| 36465 | #ifndef PRODUCT |
| 36466 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36467 | virtual const char *Name() const { return "vadd64B_reg";} |
| 36468 | #endif |
| 36469 | }; |
| 36470 | |
| 36471 | class vadd64B_memNode : public MachTypeNode { |
| 36472 | private: |
| 36473 | MachOper *_opnd_array[3]; |
| 36474 | public: |
| 36475 | MachOper *opnd_array(uint operand_index) const { |
| 36476 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36477 | return _opnd_array[operand_index]; |
| 36478 | } |
| 36479 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36481 | _opnd_array[operand_index] = operand; |
| 36482 | } |
| 36483 | private: |
| 36484 | virtual const RegMask &out_RegMask() const; |
| 36485 | virtual uint rule() const { return vadd64B_mem_rule; } |
| 36486 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36487 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36488 | virtual int reloc() const; |
| 36489 | virtual uint oper_input_base() const { return 2; } |
| 36490 | public: |
| 36491 | vadd64B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36492 | virtual uint size_of() const { return sizeof(vadd64B_memNode); } |
| 36493 | static const Pipeline *pipeline_class(); |
| 36494 | virtual const Pipeline *pipeline() const; |
| 36495 | virtual const MachOper *memory_operand() const; |
| 36496 | #ifndef PRODUCT |
| 36497 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36498 | virtual const char *Name() const { return "vadd64B_mem";} |
| 36499 | #endif |
| 36500 | }; |
| 36501 | |
| 36502 | class vadd64B_mem_0Node : public MachTypeNode { |
| 36503 | private: |
| 36504 | MachOper *_opnd_array[3]; |
| 36505 | public: |
| 36506 | MachOper *opnd_array(uint operand_index) const { |
| 36507 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36508 | return _opnd_array[operand_index]; |
| 36509 | } |
| 36510 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36511 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36512 | _opnd_array[operand_index] = operand; |
| 36513 | } |
| 36514 | private: |
| 36515 | virtual const RegMask &out_RegMask() const; |
| 36516 | virtual uint rule() const { return vadd64B_mem_0_rule; } |
| 36517 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36518 | virtual int ideal_Opcode() const { return Op_AddVB; } |
| 36519 | virtual int reloc() const; |
| 36520 | virtual uint oper_input_base() const { return 2; } |
| 36521 | public: |
| 36522 | vadd64B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36523 | virtual uint size_of() const { return sizeof(vadd64B_mem_0Node); } |
| 36524 | static const Pipeline *pipeline_class(); |
| 36525 | virtual const Pipeline *pipeline() const; |
| 36526 | virtual const MachOper *memory_operand() const; |
| 36527 | #ifndef PRODUCT |
| 36528 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36529 | virtual const char *Name() const { return "vadd64B_mem_0";} |
| 36530 | #endif |
| 36531 | }; |
| 36532 | |
| 36533 | class vadd2SNode : public MachTypeNode { |
| 36534 | private: |
| 36535 | MachOper *_opnd_array[3]; |
| 36536 | public: |
| 36537 | MachOper *opnd_array(uint operand_index) const { |
| 36538 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36539 | return _opnd_array[operand_index]; |
| 36540 | } |
| 36541 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36542 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36543 | _opnd_array[operand_index] = operand; |
| 36544 | } |
| 36545 | private: |
| 36546 | virtual const RegMask &out_RegMask() const; |
| 36547 | virtual uint rule() const { return vadd2S_rule; } |
| 36548 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36549 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36550 | virtual uint two_adr() const { return oper_input_base(); } |
| 36551 | virtual uint oper_input_base() const { return 1; } |
| 36552 | public: |
| 36553 | vadd2SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36554 | virtual uint size_of() const { return sizeof(vadd2SNode); } |
| 36555 | static const Pipeline *pipeline_class(); |
| 36556 | virtual const Pipeline *pipeline() const; |
| 36557 | #ifndef PRODUCT |
| 36558 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36559 | virtual const char *Name() const { return "vadd2S";} |
| 36560 | #endif |
| 36561 | }; |
| 36562 | |
| 36563 | class vadd2S_regNode : public MachTypeNode { |
| 36564 | private: |
| 36565 | MachOper *_opnd_array[3]; |
| 36566 | public: |
| 36567 | MachOper *opnd_array(uint operand_index) const { |
| 36568 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36569 | return _opnd_array[operand_index]; |
| 36570 | } |
| 36571 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36572 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36573 | _opnd_array[operand_index] = operand; |
| 36574 | } |
| 36575 | private: |
| 36576 | virtual const RegMask &out_RegMask() const; |
| 36577 | virtual uint rule() const { return vadd2S_reg_rule; } |
| 36578 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36579 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36580 | virtual uint oper_input_base() const { return 1; } |
| 36581 | public: |
| 36582 | vadd2S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36583 | virtual uint size_of() const { return sizeof(vadd2S_regNode); } |
| 36584 | static const Pipeline *pipeline_class(); |
| 36585 | virtual const Pipeline *pipeline() const; |
| 36586 | #ifndef PRODUCT |
| 36587 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36588 | virtual const char *Name() const { return "vadd2S_reg";} |
| 36589 | #endif |
| 36590 | }; |
| 36591 | |
| 36592 | class vadd2S_memNode : public MachTypeNode { |
| 36593 | private: |
| 36594 | MachOper *_opnd_array[3]; |
| 36595 | public: |
| 36596 | MachOper *opnd_array(uint operand_index) const { |
| 36597 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36598 | return _opnd_array[operand_index]; |
| 36599 | } |
| 36600 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36601 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36602 | _opnd_array[operand_index] = operand; |
| 36603 | } |
| 36604 | private: |
| 36605 | virtual const RegMask &out_RegMask() const; |
| 36606 | virtual uint rule() const { return vadd2S_mem_rule; } |
| 36607 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36608 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36609 | virtual int reloc() const; |
| 36610 | virtual uint oper_input_base() const { return 2; } |
| 36611 | public: |
| 36612 | vadd2S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36613 | virtual uint size_of() const { return sizeof(vadd2S_memNode); } |
| 36614 | static const Pipeline *pipeline_class(); |
| 36615 | virtual const Pipeline *pipeline() const; |
| 36616 | virtual const MachOper *memory_operand() const; |
| 36617 | #ifndef PRODUCT |
| 36618 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36619 | virtual const char *Name() const { return "vadd2S_mem";} |
| 36620 | #endif |
| 36621 | }; |
| 36622 | |
| 36623 | class vadd2S_mem_0Node : public MachTypeNode { |
| 36624 | private: |
| 36625 | MachOper *_opnd_array[3]; |
| 36626 | public: |
| 36627 | MachOper *opnd_array(uint operand_index) const { |
| 36628 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36629 | return _opnd_array[operand_index]; |
| 36630 | } |
| 36631 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36632 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36633 | _opnd_array[operand_index] = operand; |
| 36634 | } |
| 36635 | private: |
| 36636 | virtual const RegMask &out_RegMask() const; |
| 36637 | virtual uint rule() const { return vadd2S_mem_0_rule; } |
| 36638 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36639 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36640 | virtual int reloc() const; |
| 36641 | virtual uint oper_input_base() const { return 2; } |
| 36642 | public: |
| 36643 | vadd2S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36644 | virtual uint size_of() const { return sizeof(vadd2S_mem_0Node); } |
| 36645 | static const Pipeline *pipeline_class(); |
| 36646 | virtual const Pipeline *pipeline() const; |
| 36647 | virtual const MachOper *memory_operand() const; |
| 36648 | #ifndef PRODUCT |
| 36649 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36650 | virtual const char *Name() const { return "vadd2S_mem_0";} |
| 36651 | #endif |
| 36652 | }; |
| 36653 | |
| 36654 | class vadd4SNode : public MachTypeNode { |
| 36655 | private: |
| 36656 | MachOper *_opnd_array[3]; |
| 36657 | public: |
| 36658 | MachOper *opnd_array(uint operand_index) const { |
| 36659 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36660 | return _opnd_array[operand_index]; |
| 36661 | } |
| 36662 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36663 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36664 | _opnd_array[operand_index] = operand; |
| 36665 | } |
| 36666 | private: |
| 36667 | virtual const RegMask &out_RegMask() const; |
| 36668 | virtual uint rule() const { return vadd4S_rule; } |
| 36669 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36670 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36671 | virtual uint two_adr() const { return oper_input_base(); } |
| 36672 | virtual uint oper_input_base() const { return 1; } |
| 36673 | public: |
| 36674 | vadd4SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36675 | virtual uint size_of() const { return sizeof(vadd4SNode); } |
| 36676 | static const Pipeline *pipeline_class(); |
| 36677 | virtual const Pipeline *pipeline() const; |
| 36678 | #ifndef PRODUCT |
| 36679 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36680 | virtual const char *Name() const { return "vadd4S";} |
| 36681 | #endif |
| 36682 | }; |
| 36683 | |
| 36684 | class vadd4S_regNode : public MachTypeNode { |
| 36685 | private: |
| 36686 | MachOper *_opnd_array[3]; |
| 36687 | public: |
| 36688 | MachOper *opnd_array(uint operand_index) const { |
| 36689 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36690 | return _opnd_array[operand_index]; |
| 36691 | } |
| 36692 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36693 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36694 | _opnd_array[operand_index] = operand; |
| 36695 | } |
| 36696 | private: |
| 36697 | virtual const RegMask &out_RegMask() const; |
| 36698 | virtual uint rule() const { return vadd4S_reg_rule; } |
| 36699 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36700 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36701 | virtual uint oper_input_base() const { return 1; } |
| 36702 | public: |
| 36703 | vadd4S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36704 | virtual uint size_of() const { return sizeof(vadd4S_regNode); } |
| 36705 | static const Pipeline *pipeline_class(); |
| 36706 | virtual const Pipeline *pipeline() const; |
| 36707 | #ifndef PRODUCT |
| 36708 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36709 | virtual const char *Name() const { return "vadd4S_reg";} |
| 36710 | #endif |
| 36711 | }; |
| 36712 | |
| 36713 | class vadd4S_memNode : public MachTypeNode { |
| 36714 | private: |
| 36715 | MachOper *_opnd_array[3]; |
| 36716 | public: |
| 36717 | MachOper *opnd_array(uint operand_index) const { |
| 36718 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36719 | return _opnd_array[operand_index]; |
| 36720 | } |
| 36721 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36722 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36723 | _opnd_array[operand_index] = operand; |
| 36724 | } |
| 36725 | private: |
| 36726 | virtual const RegMask &out_RegMask() const; |
| 36727 | virtual uint rule() const { return vadd4S_mem_rule; } |
| 36728 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36729 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36730 | virtual int reloc() const; |
| 36731 | virtual uint oper_input_base() const { return 2; } |
| 36732 | public: |
| 36733 | vadd4S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36734 | virtual uint size_of() const { return sizeof(vadd4S_memNode); } |
| 36735 | static const Pipeline *pipeline_class(); |
| 36736 | virtual const Pipeline *pipeline() const; |
| 36737 | virtual const MachOper *memory_operand() const; |
| 36738 | #ifndef PRODUCT |
| 36739 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36740 | virtual const char *Name() const { return "vadd4S_mem";} |
| 36741 | #endif |
| 36742 | }; |
| 36743 | |
| 36744 | class vadd4S_mem_0Node : public MachTypeNode { |
| 36745 | private: |
| 36746 | MachOper *_opnd_array[3]; |
| 36747 | public: |
| 36748 | MachOper *opnd_array(uint operand_index) const { |
| 36749 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36750 | return _opnd_array[operand_index]; |
| 36751 | } |
| 36752 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36753 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36754 | _opnd_array[operand_index] = operand; |
| 36755 | } |
| 36756 | private: |
| 36757 | virtual const RegMask &out_RegMask() const; |
| 36758 | virtual uint rule() const { return vadd4S_mem_0_rule; } |
| 36759 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36760 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36761 | virtual int reloc() const; |
| 36762 | virtual uint oper_input_base() const { return 2; } |
| 36763 | public: |
| 36764 | vadd4S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36765 | virtual uint size_of() const { return sizeof(vadd4S_mem_0Node); } |
| 36766 | static const Pipeline *pipeline_class(); |
| 36767 | virtual const Pipeline *pipeline() const; |
| 36768 | virtual const MachOper *memory_operand() const; |
| 36769 | #ifndef PRODUCT |
| 36770 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36771 | virtual const char *Name() const { return "vadd4S_mem_0";} |
| 36772 | #endif |
| 36773 | }; |
| 36774 | |
| 36775 | class vadd8SNode : public MachTypeNode { |
| 36776 | private: |
| 36777 | MachOper *_opnd_array[3]; |
| 36778 | public: |
| 36779 | MachOper *opnd_array(uint operand_index) const { |
| 36780 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36781 | return _opnd_array[operand_index]; |
| 36782 | } |
| 36783 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36784 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36785 | _opnd_array[operand_index] = operand; |
| 36786 | } |
| 36787 | private: |
| 36788 | virtual const RegMask &out_RegMask() const; |
| 36789 | virtual uint rule() const { return vadd8S_rule; } |
| 36790 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36791 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36792 | virtual uint two_adr() const { return oper_input_base(); } |
| 36793 | virtual uint oper_input_base() const { return 1; } |
| 36794 | public: |
| 36795 | vadd8SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36796 | virtual uint size_of() const { return sizeof(vadd8SNode); } |
| 36797 | static const Pipeline *pipeline_class(); |
| 36798 | virtual const Pipeline *pipeline() const; |
| 36799 | #ifndef PRODUCT |
| 36800 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36801 | virtual const char *Name() const { return "vadd8S";} |
| 36802 | #endif |
| 36803 | }; |
| 36804 | |
| 36805 | class vadd8S_regNode : public MachTypeNode { |
| 36806 | private: |
| 36807 | MachOper *_opnd_array[3]; |
| 36808 | public: |
| 36809 | MachOper *opnd_array(uint operand_index) const { |
| 36810 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36811 | return _opnd_array[operand_index]; |
| 36812 | } |
| 36813 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36814 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36815 | _opnd_array[operand_index] = operand; |
| 36816 | } |
| 36817 | private: |
| 36818 | virtual const RegMask &out_RegMask() const; |
| 36819 | virtual uint rule() const { return vadd8S_reg_rule; } |
| 36820 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36821 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36822 | virtual uint oper_input_base() const { return 1; } |
| 36823 | public: |
| 36824 | vadd8S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36825 | virtual uint size_of() const { return sizeof(vadd8S_regNode); } |
| 36826 | static const Pipeline *pipeline_class(); |
| 36827 | virtual const Pipeline *pipeline() const; |
| 36828 | #ifndef PRODUCT |
| 36829 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36830 | virtual const char *Name() const { return "vadd8S_reg";} |
| 36831 | #endif |
| 36832 | }; |
| 36833 | |
| 36834 | class vadd8S_memNode : public MachTypeNode { |
| 36835 | private: |
| 36836 | MachOper *_opnd_array[3]; |
| 36837 | public: |
| 36838 | MachOper *opnd_array(uint operand_index) const { |
| 36839 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36840 | return _opnd_array[operand_index]; |
| 36841 | } |
| 36842 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36843 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36844 | _opnd_array[operand_index] = operand; |
| 36845 | } |
| 36846 | private: |
| 36847 | virtual const RegMask &out_RegMask() const; |
| 36848 | virtual uint rule() const { return vadd8S_mem_rule; } |
| 36849 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36850 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36851 | virtual int reloc() const; |
| 36852 | virtual uint oper_input_base() const { return 2; } |
| 36853 | public: |
| 36854 | vadd8S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36855 | virtual uint size_of() const { return sizeof(vadd8S_memNode); } |
| 36856 | static const Pipeline *pipeline_class(); |
| 36857 | virtual const Pipeline *pipeline() const; |
| 36858 | virtual const MachOper *memory_operand() const; |
| 36859 | #ifndef PRODUCT |
| 36860 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36861 | virtual const char *Name() const { return "vadd8S_mem";} |
| 36862 | #endif |
| 36863 | }; |
| 36864 | |
| 36865 | class vadd8S_mem_0Node : public MachTypeNode { |
| 36866 | private: |
| 36867 | MachOper *_opnd_array[3]; |
| 36868 | public: |
| 36869 | MachOper *opnd_array(uint operand_index) const { |
| 36870 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36871 | return _opnd_array[operand_index]; |
| 36872 | } |
| 36873 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36874 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36875 | _opnd_array[operand_index] = operand; |
| 36876 | } |
| 36877 | private: |
| 36878 | virtual const RegMask &out_RegMask() const; |
| 36879 | virtual uint rule() const { return vadd8S_mem_0_rule; } |
| 36880 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36881 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36882 | virtual int reloc() const; |
| 36883 | virtual uint oper_input_base() const { return 2; } |
| 36884 | public: |
| 36885 | vadd8S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36886 | virtual uint size_of() const { return sizeof(vadd8S_mem_0Node); } |
| 36887 | static const Pipeline *pipeline_class(); |
| 36888 | virtual const Pipeline *pipeline() const; |
| 36889 | virtual const MachOper *memory_operand() const; |
| 36890 | #ifndef PRODUCT |
| 36891 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36892 | virtual const char *Name() const { return "vadd8S_mem_0";} |
| 36893 | #endif |
| 36894 | }; |
| 36895 | |
| 36896 | class vadd16S_regNode : public MachTypeNode { |
| 36897 | private: |
| 36898 | MachOper *_opnd_array[3]; |
| 36899 | public: |
| 36900 | MachOper *opnd_array(uint operand_index) const { |
| 36901 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36902 | return _opnd_array[operand_index]; |
| 36903 | } |
| 36904 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36905 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36906 | _opnd_array[operand_index] = operand; |
| 36907 | } |
| 36908 | private: |
| 36909 | virtual const RegMask &out_RegMask() const; |
| 36910 | virtual uint rule() const { return vadd16S_reg_rule; } |
| 36911 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36912 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36913 | virtual uint oper_input_base() const { return 1; } |
| 36914 | public: |
| 36915 | vadd16S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 36916 | virtual uint size_of() const { return sizeof(vadd16S_regNode); } |
| 36917 | static const Pipeline *pipeline_class(); |
| 36918 | virtual const Pipeline *pipeline() const; |
| 36919 | #ifndef PRODUCT |
| 36920 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36921 | virtual const char *Name() const { return "vadd16S_reg";} |
| 36922 | #endif |
| 36923 | }; |
| 36924 | |
| 36925 | class vadd16S_memNode : public MachTypeNode { |
| 36926 | private: |
| 36927 | MachOper *_opnd_array[3]; |
| 36928 | public: |
| 36929 | MachOper *opnd_array(uint operand_index) const { |
| 36930 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36931 | return _opnd_array[operand_index]; |
| 36932 | } |
| 36933 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36934 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36935 | _opnd_array[operand_index] = operand; |
| 36936 | } |
| 36937 | private: |
| 36938 | virtual const RegMask &out_RegMask() const; |
| 36939 | virtual uint rule() const { return vadd16S_mem_rule; } |
| 36940 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36941 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36942 | virtual int reloc() const; |
| 36943 | virtual uint oper_input_base() const { return 2; } |
| 36944 | public: |
| 36945 | vadd16S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36946 | virtual uint size_of() const { return sizeof(vadd16S_memNode); } |
| 36947 | static const Pipeline *pipeline_class(); |
| 36948 | virtual const Pipeline *pipeline() const; |
| 36949 | virtual const MachOper *memory_operand() const; |
| 36950 | #ifndef PRODUCT |
| 36951 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36952 | virtual const char *Name() const { return "vadd16S_mem";} |
| 36953 | #endif |
| 36954 | }; |
| 36955 | |
| 36956 | class vadd16S_mem_0Node : public MachTypeNode { |
| 36957 | private: |
| 36958 | MachOper *_opnd_array[3]; |
| 36959 | public: |
| 36960 | MachOper *opnd_array(uint operand_index) const { |
| 36961 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36962 | return _opnd_array[operand_index]; |
| 36963 | } |
| 36964 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36966 | _opnd_array[operand_index] = operand; |
| 36967 | } |
| 36968 | private: |
| 36969 | virtual const RegMask &out_RegMask() const; |
| 36970 | virtual uint rule() const { return vadd16S_mem_0_rule; } |
| 36971 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 36972 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 36973 | virtual int reloc() const; |
| 36974 | virtual uint oper_input_base() const { return 2; } |
| 36975 | public: |
| 36976 | vadd16S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 36977 | virtual uint size_of() const { return sizeof(vadd16S_mem_0Node); } |
| 36978 | static const Pipeline *pipeline_class(); |
| 36979 | virtual const Pipeline *pipeline() const; |
| 36980 | virtual const MachOper *memory_operand() const; |
| 36981 | #ifndef PRODUCT |
| 36982 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 36983 | virtual const char *Name() const { return "vadd16S_mem_0";} |
| 36984 | #endif |
| 36985 | }; |
| 36986 | |
| 36987 | class vadd32S_regNode : public MachTypeNode { |
| 36988 | private: |
| 36989 | MachOper *_opnd_array[3]; |
| 36990 | public: |
| 36991 | MachOper *opnd_array(uint operand_index) const { |
| 36992 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36993 | return _opnd_array[operand_index]; |
| 36994 | } |
| 36995 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 36996 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 36997 | _opnd_array[operand_index] = operand; |
| 36998 | } |
| 36999 | private: |
| 37000 | virtual const RegMask &out_RegMask() const; |
| 37001 | virtual uint rule() const { return vadd32S_reg_rule; } |
| 37002 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37003 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 37004 | virtual uint oper_input_base() const { return 1; } |
| 37005 | public: |
| 37006 | vadd32S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37007 | virtual uint size_of() const { return sizeof(vadd32S_regNode); } |
| 37008 | static const Pipeline *pipeline_class(); |
| 37009 | virtual const Pipeline *pipeline() const; |
| 37010 | #ifndef PRODUCT |
| 37011 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37012 | virtual const char *Name() const { return "vadd32S_reg";} |
| 37013 | #endif |
| 37014 | }; |
| 37015 | |
| 37016 | class vadd32S_memNode : public MachTypeNode { |
| 37017 | private: |
| 37018 | MachOper *_opnd_array[3]; |
| 37019 | public: |
| 37020 | MachOper *opnd_array(uint operand_index) const { |
| 37021 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37022 | return _opnd_array[operand_index]; |
| 37023 | } |
| 37024 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37025 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37026 | _opnd_array[operand_index] = operand; |
| 37027 | } |
| 37028 | private: |
| 37029 | virtual const RegMask &out_RegMask() const; |
| 37030 | virtual uint rule() const { return vadd32S_mem_rule; } |
| 37031 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37032 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 37033 | virtual int reloc() const; |
| 37034 | virtual uint oper_input_base() const { return 2; } |
| 37035 | public: |
| 37036 | vadd32S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37037 | virtual uint size_of() const { return sizeof(vadd32S_memNode); } |
| 37038 | static const Pipeline *pipeline_class(); |
| 37039 | virtual const Pipeline *pipeline() const; |
| 37040 | virtual const MachOper *memory_operand() const; |
| 37041 | #ifndef PRODUCT |
| 37042 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37043 | virtual const char *Name() const { return "vadd32S_mem";} |
| 37044 | #endif |
| 37045 | }; |
| 37046 | |
| 37047 | class vadd32S_mem_0Node : public MachTypeNode { |
| 37048 | private: |
| 37049 | MachOper *_opnd_array[3]; |
| 37050 | public: |
| 37051 | MachOper *opnd_array(uint operand_index) const { |
| 37052 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37053 | return _opnd_array[operand_index]; |
| 37054 | } |
| 37055 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37056 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37057 | _opnd_array[operand_index] = operand; |
| 37058 | } |
| 37059 | private: |
| 37060 | virtual const RegMask &out_RegMask() const; |
| 37061 | virtual uint rule() const { return vadd32S_mem_0_rule; } |
| 37062 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37063 | virtual int ideal_Opcode() const { return Op_AddVS; } |
| 37064 | virtual int reloc() const; |
| 37065 | virtual uint oper_input_base() const { return 2; } |
| 37066 | public: |
| 37067 | vadd32S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37068 | virtual uint size_of() const { return sizeof(vadd32S_mem_0Node); } |
| 37069 | static const Pipeline *pipeline_class(); |
| 37070 | virtual const Pipeline *pipeline() const; |
| 37071 | virtual const MachOper *memory_operand() const; |
| 37072 | #ifndef PRODUCT |
| 37073 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37074 | virtual const char *Name() const { return "vadd32S_mem_0";} |
| 37075 | #endif |
| 37076 | }; |
| 37077 | |
| 37078 | class vadd2INode : public MachTypeNode { |
| 37079 | private: |
| 37080 | MachOper *_opnd_array[3]; |
| 37081 | public: |
| 37082 | MachOper *opnd_array(uint operand_index) const { |
| 37083 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37084 | return _opnd_array[operand_index]; |
| 37085 | } |
| 37086 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37087 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37088 | _opnd_array[operand_index] = operand; |
| 37089 | } |
| 37090 | private: |
| 37091 | virtual const RegMask &out_RegMask() const; |
| 37092 | virtual uint rule() const { return vadd2I_rule; } |
| 37093 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37094 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37095 | virtual uint two_adr() const { return oper_input_base(); } |
| 37096 | virtual uint oper_input_base() const { return 1; } |
| 37097 | public: |
| 37098 | vadd2INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37099 | virtual uint size_of() const { return sizeof(vadd2INode); } |
| 37100 | static const Pipeline *pipeline_class(); |
| 37101 | virtual const Pipeline *pipeline() const; |
| 37102 | #ifndef PRODUCT |
| 37103 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37104 | virtual const char *Name() const { return "vadd2I";} |
| 37105 | #endif |
| 37106 | }; |
| 37107 | |
| 37108 | class vadd2I_regNode : public MachTypeNode { |
| 37109 | private: |
| 37110 | MachOper *_opnd_array[3]; |
| 37111 | public: |
| 37112 | MachOper *opnd_array(uint operand_index) const { |
| 37113 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37114 | return _opnd_array[operand_index]; |
| 37115 | } |
| 37116 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37117 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37118 | _opnd_array[operand_index] = operand; |
| 37119 | } |
| 37120 | private: |
| 37121 | virtual const RegMask &out_RegMask() const; |
| 37122 | virtual uint rule() const { return vadd2I_reg_rule; } |
| 37123 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37124 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37125 | virtual uint oper_input_base() const { return 1; } |
| 37126 | public: |
| 37127 | vadd2I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37128 | virtual uint size_of() const { return sizeof(vadd2I_regNode); } |
| 37129 | static const Pipeline *pipeline_class(); |
| 37130 | virtual const Pipeline *pipeline() const; |
| 37131 | #ifndef PRODUCT |
| 37132 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37133 | virtual const char *Name() const { return "vadd2I_reg";} |
| 37134 | #endif |
| 37135 | }; |
| 37136 | |
| 37137 | class vadd2I_memNode : public MachTypeNode { |
| 37138 | private: |
| 37139 | MachOper *_opnd_array[3]; |
| 37140 | public: |
| 37141 | MachOper *opnd_array(uint operand_index) const { |
| 37142 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37143 | return _opnd_array[operand_index]; |
| 37144 | } |
| 37145 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37146 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37147 | _opnd_array[operand_index] = operand; |
| 37148 | } |
| 37149 | private: |
| 37150 | virtual const RegMask &out_RegMask() const; |
| 37151 | virtual uint rule() const { return vadd2I_mem_rule; } |
| 37152 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37153 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37154 | virtual int reloc() const; |
| 37155 | virtual uint oper_input_base() const { return 2; } |
| 37156 | public: |
| 37157 | vadd2I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37158 | virtual uint size_of() const { return sizeof(vadd2I_memNode); } |
| 37159 | static const Pipeline *pipeline_class(); |
| 37160 | virtual const Pipeline *pipeline() const; |
| 37161 | virtual const MachOper *memory_operand() const; |
| 37162 | #ifndef PRODUCT |
| 37163 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37164 | virtual const char *Name() const { return "vadd2I_mem";} |
| 37165 | #endif |
| 37166 | }; |
| 37167 | |
| 37168 | class vadd2I_mem_0Node : public MachTypeNode { |
| 37169 | private: |
| 37170 | MachOper *_opnd_array[3]; |
| 37171 | public: |
| 37172 | MachOper *opnd_array(uint operand_index) const { |
| 37173 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37174 | return _opnd_array[operand_index]; |
| 37175 | } |
| 37176 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37177 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37178 | _opnd_array[operand_index] = operand; |
| 37179 | } |
| 37180 | private: |
| 37181 | virtual const RegMask &out_RegMask() const; |
| 37182 | virtual uint rule() const { return vadd2I_mem_0_rule; } |
| 37183 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37184 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37185 | virtual int reloc() const; |
| 37186 | virtual uint oper_input_base() const { return 2; } |
| 37187 | public: |
| 37188 | vadd2I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37189 | virtual uint size_of() const { return sizeof(vadd2I_mem_0Node); } |
| 37190 | static const Pipeline *pipeline_class(); |
| 37191 | virtual const Pipeline *pipeline() const; |
| 37192 | virtual const MachOper *memory_operand() const; |
| 37193 | #ifndef PRODUCT |
| 37194 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37195 | virtual const char *Name() const { return "vadd2I_mem_0";} |
| 37196 | #endif |
| 37197 | }; |
| 37198 | |
| 37199 | class vadd4INode : public MachTypeNode { |
| 37200 | private: |
| 37201 | MachOper *_opnd_array[3]; |
| 37202 | public: |
| 37203 | MachOper *opnd_array(uint operand_index) const { |
| 37204 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37205 | return _opnd_array[operand_index]; |
| 37206 | } |
| 37207 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37209 | _opnd_array[operand_index] = operand; |
| 37210 | } |
| 37211 | private: |
| 37212 | virtual const RegMask &out_RegMask() const; |
| 37213 | virtual uint rule() const { return vadd4I_rule; } |
| 37214 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37215 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37216 | virtual uint two_adr() const { return oper_input_base(); } |
| 37217 | virtual uint oper_input_base() const { return 1; } |
| 37218 | public: |
| 37219 | vadd4INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37220 | virtual uint size_of() const { return sizeof(vadd4INode); } |
| 37221 | static const Pipeline *pipeline_class(); |
| 37222 | virtual const Pipeline *pipeline() const; |
| 37223 | #ifndef PRODUCT |
| 37224 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37225 | virtual const char *Name() const { return "vadd4I";} |
| 37226 | #endif |
| 37227 | }; |
| 37228 | |
| 37229 | class vadd4I_regNode : public MachTypeNode { |
| 37230 | private: |
| 37231 | MachOper *_opnd_array[3]; |
| 37232 | public: |
| 37233 | MachOper *opnd_array(uint operand_index) const { |
| 37234 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37235 | return _opnd_array[operand_index]; |
| 37236 | } |
| 37237 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37239 | _opnd_array[operand_index] = operand; |
| 37240 | } |
| 37241 | private: |
| 37242 | virtual const RegMask &out_RegMask() const; |
| 37243 | virtual uint rule() const { return vadd4I_reg_rule; } |
| 37244 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37245 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37246 | virtual uint oper_input_base() const { return 1; } |
| 37247 | public: |
| 37248 | vadd4I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37249 | virtual uint size_of() const { return sizeof(vadd4I_regNode); } |
| 37250 | static const Pipeline *pipeline_class(); |
| 37251 | virtual const Pipeline *pipeline() const; |
| 37252 | #ifndef PRODUCT |
| 37253 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37254 | virtual const char *Name() const { return "vadd4I_reg";} |
| 37255 | #endif |
| 37256 | }; |
| 37257 | |
| 37258 | class vadd4I_memNode : public MachTypeNode { |
| 37259 | private: |
| 37260 | MachOper *_opnd_array[3]; |
| 37261 | public: |
| 37262 | MachOper *opnd_array(uint operand_index) const { |
| 37263 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37264 | return _opnd_array[operand_index]; |
| 37265 | } |
| 37266 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37267 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37268 | _opnd_array[operand_index] = operand; |
| 37269 | } |
| 37270 | private: |
| 37271 | virtual const RegMask &out_RegMask() const; |
| 37272 | virtual uint rule() const { return vadd4I_mem_rule; } |
| 37273 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37274 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37275 | virtual int reloc() const; |
| 37276 | virtual uint oper_input_base() const { return 2; } |
| 37277 | public: |
| 37278 | vadd4I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37279 | virtual uint size_of() const { return sizeof(vadd4I_memNode); } |
| 37280 | static const Pipeline *pipeline_class(); |
| 37281 | virtual const Pipeline *pipeline() const; |
| 37282 | virtual const MachOper *memory_operand() const; |
| 37283 | #ifndef PRODUCT |
| 37284 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37285 | virtual const char *Name() const { return "vadd4I_mem";} |
| 37286 | #endif |
| 37287 | }; |
| 37288 | |
| 37289 | class vadd4I_mem_0Node : public MachTypeNode { |
| 37290 | private: |
| 37291 | MachOper *_opnd_array[3]; |
| 37292 | public: |
| 37293 | MachOper *opnd_array(uint operand_index) const { |
| 37294 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37295 | return _opnd_array[operand_index]; |
| 37296 | } |
| 37297 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37298 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37299 | _opnd_array[operand_index] = operand; |
| 37300 | } |
| 37301 | private: |
| 37302 | virtual const RegMask &out_RegMask() const; |
| 37303 | virtual uint rule() const { return vadd4I_mem_0_rule; } |
| 37304 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37305 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37306 | virtual int reloc() const; |
| 37307 | virtual uint oper_input_base() const { return 2; } |
| 37308 | public: |
| 37309 | vadd4I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37310 | virtual uint size_of() const { return sizeof(vadd4I_mem_0Node); } |
| 37311 | static const Pipeline *pipeline_class(); |
| 37312 | virtual const Pipeline *pipeline() const; |
| 37313 | virtual const MachOper *memory_operand() const; |
| 37314 | #ifndef PRODUCT |
| 37315 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37316 | virtual const char *Name() const { return "vadd4I_mem_0";} |
| 37317 | #endif |
| 37318 | }; |
| 37319 | |
| 37320 | class vadd8I_regNode : public MachTypeNode { |
| 37321 | private: |
| 37322 | MachOper *_opnd_array[3]; |
| 37323 | public: |
| 37324 | MachOper *opnd_array(uint operand_index) const { |
| 37325 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37326 | return _opnd_array[operand_index]; |
| 37327 | } |
| 37328 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37329 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37330 | _opnd_array[operand_index] = operand; |
| 37331 | } |
| 37332 | private: |
| 37333 | virtual const RegMask &out_RegMask() const; |
| 37334 | virtual uint rule() const { return vadd8I_reg_rule; } |
| 37335 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37336 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37337 | virtual uint oper_input_base() const { return 1; } |
| 37338 | public: |
| 37339 | vadd8I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37340 | virtual uint size_of() const { return sizeof(vadd8I_regNode); } |
| 37341 | static const Pipeline *pipeline_class(); |
| 37342 | virtual const Pipeline *pipeline() const; |
| 37343 | #ifndef PRODUCT |
| 37344 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37345 | virtual const char *Name() const { return "vadd8I_reg";} |
| 37346 | #endif |
| 37347 | }; |
| 37348 | |
| 37349 | class vadd8I_memNode : public MachTypeNode { |
| 37350 | private: |
| 37351 | MachOper *_opnd_array[3]; |
| 37352 | public: |
| 37353 | MachOper *opnd_array(uint operand_index) const { |
| 37354 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37355 | return _opnd_array[operand_index]; |
| 37356 | } |
| 37357 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37358 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37359 | _opnd_array[operand_index] = operand; |
| 37360 | } |
| 37361 | private: |
| 37362 | virtual const RegMask &out_RegMask() const; |
| 37363 | virtual uint rule() const { return vadd8I_mem_rule; } |
| 37364 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37365 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37366 | virtual int reloc() const; |
| 37367 | virtual uint oper_input_base() const { return 2; } |
| 37368 | public: |
| 37369 | vadd8I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37370 | virtual uint size_of() const { return sizeof(vadd8I_memNode); } |
| 37371 | static const Pipeline *pipeline_class(); |
| 37372 | virtual const Pipeline *pipeline() const; |
| 37373 | virtual const MachOper *memory_operand() const; |
| 37374 | #ifndef PRODUCT |
| 37375 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37376 | virtual const char *Name() const { return "vadd8I_mem";} |
| 37377 | #endif |
| 37378 | }; |
| 37379 | |
| 37380 | class vadd8I_mem_0Node : public MachTypeNode { |
| 37381 | private: |
| 37382 | MachOper *_opnd_array[3]; |
| 37383 | public: |
| 37384 | MachOper *opnd_array(uint operand_index) const { |
| 37385 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37386 | return _opnd_array[operand_index]; |
| 37387 | } |
| 37388 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37389 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37390 | _opnd_array[operand_index] = operand; |
| 37391 | } |
| 37392 | private: |
| 37393 | virtual const RegMask &out_RegMask() const; |
| 37394 | virtual uint rule() const { return vadd8I_mem_0_rule; } |
| 37395 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37396 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37397 | virtual int reloc() const; |
| 37398 | virtual uint oper_input_base() const { return 2; } |
| 37399 | public: |
| 37400 | vadd8I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37401 | virtual uint size_of() const { return sizeof(vadd8I_mem_0Node); } |
| 37402 | static const Pipeline *pipeline_class(); |
| 37403 | virtual const Pipeline *pipeline() const; |
| 37404 | virtual const MachOper *memory_operand() const; |
| 37405 | #ifndef PRODUCT |
| 37406 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37407 | virtual const char *Name() const { return "vadd8I_mem_0";} |
| 37408 | #endif |
| 37409 | }; |
| 37410 | |
| 37411 | class vadd16I_regNode : public MachTypeNode { |
| 37412 | private: |
| 37413 | MachOper *_opnd_array[3]; |
| 37414 | public: |
| 37415 | MachOper *opnd_array(uint operand_index) const { |
| 37416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37417 | return _opnd_array[operand_index]; |
| 37418 | } |
| 37419 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37420 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37421 | _opnd_array[operand_index] = operand; |
| 37422 | } |
| 37423 | private: |
| 37424 | virtual const RegMask &out_RegMask() const; |
| 37425 | virtual uint rule() const { return vadd16I_reg_rule; } |
| 37426 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37427 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37428 | virtual uint oper_input_base() const { return 1; } |
| 37429 | public: |
| 37430 | vadd16I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37431 | virtual uint size_of() const { return sizeof(vadd16I_regNode); } |
| 37432 | static const Pipeline *pipeline_class(); |
| 37433 | virtual const Pipeline *pipeline() const; |
| 37434 | #ifndef PRODUCT |
| 37435 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37436 | virtual const char *Name() const { return "vadd16I_reg";} |
| 37437 | #endif |
| 37438 | }; |
| 37439 | |
| 37440 | class vadd16I_memNode : public MachTypeNode { |
| 37441 | private: |
| 37442 | MachOper *_opnd_array[3]; |
| 37443 | public: |
| 37444 | MachOper *opnd_array(uint operand_index) const { |
| 37445 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37446 | return _opnd_array[operand_index]; |
| 37447 | } |
| 37448 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37449 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37450 | _opnd_array[operand_index] = operand; |
| 37451 | } |
| 37452 | private: |
| 37453 | virtual const RegMask &out_RegMask() const; |
| 37454 | virtual uint rule() const { return vadd16I_mem_rule; } |
| 37455 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37456 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37457 | virtual int reloc() const; |
| 37458 | virtual uint oper_input_base() const { return 2; } |
| 37459 | public: |
| 37460 | vadd16I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37461 | virtual uint size_of() const { return sizeof(vadd16I_memNode); } |
| 37462 | static const Pipeline *pipeline_class(); |
| 37463 | virtual const Pipeline *pipeline() const; |
| 37464 | virtual const MachOper *memory_operand() const; |
| 37465 | #ifndef PRODUCT |
| 37466 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37467 | virtual const char *Name() const { return "vadd16I_mem";} |
| 37468 | #endif |
| 37469 | }; |
| 37470 | |
| 37471 | class vadd16I_mem_0Node : public MachTypeNode { |
| 37472 | private: |
| 37473 | MachOper *_opnd_array[3]; |
| 37474 | public: |
| 37475 | MachOper *opnd_array(uint operand_index) const { |
| 37476 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37477 | return _opnd_array[operand_index]; |
| 37478 | } |
| 37479 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37481 | _opnd_array[operand_index] = operand; |
| 37482 | } |
| 37483 | private: |
| 37484 | virtual const RegMask &out_RegMask() const; |
| 37485 | virtual uint rule() const { return vadd16I_mem_0_rule; } |
| 37486 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37487 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 37488 | virtual int reloc() const; |
| 37489 | virtual uint oper_input_base() const { return 2; } |
| 37490 | public: |
| 37491 | vadd16I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37492 | virtual uint size_of() const { return sizeof(vadd16I_mem_0Node); } |
| 37493 | static const Pipeline *pipeline_class(); |
| 37494 | virtual const Pipeline *pipeline() const; |
| 37495 | virtual const MachOper *memory_operand() const; |
| 37496 | #ifndef PRODUCT |
| 37497 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37498 | virtual const char *Name() const { return "vadd16I_mem_0";} |
| 37499 | #endif |
| 37500 | }; |
| 37501 | |
| 37502 | class vadd2LNode : public MachTypeNode { |
| 37503 | private: |
| 37504 | MachOper *_opnd_array[3]; |
| 37505 | public: |
| 37506 | MachOper *opnd_array(uint operand_index) const { |
| 37507 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37508 | return _opnd_array[operand_index]; |
| 37509 | } |
| 37510 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37511 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37512 | _opnd_array[operand_index] = operand; |
| 37513 | } |
| 37514 | private: |
| 37515 | virtual const RegMask &out_RegMask() const; |
| 37516 | virtual uint rule() const { return vadd2L_rule; } |
| 37517 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37518 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37519 | virtual uint two_adr() const { return oper_input_base(); } |
| 37520 | virtual uint oper_input_base() const { return 1; } |
| 37521 | public: |
| 37522 | vadd2LNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37523 | virtual uint size_of() const { return sizeof(vadd2LNode); } |
| 37524 | static const Pipeline *pipeline_class(); |
| 37525 | virtual const Pipeline *pipeline() const; |
| 37526 | #ifndef PRODUCT |
| 37527 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37528 | virtual const char *Name() const { return "vadd2L";} |
| 37529 | #endif |
| 37530 | }; |
| 37531 | |
| 37532 | class vadd2L_regNode : public MachTypeNode { |
| 37533 | private: |
| 37534 | MachOper *_opnd_array[3]; |
| 37535 | public: |
| 37536 | MachOper *opnd_array(uint operand_index) const { |
| 37537 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37538 | return _opnd_array[operand_index]; |
| 37539 | } |
| 37540 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37541 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37542 | _opnd_array[operand_index] = operand; |
| 37543 | } |
| 37544 | private: |
| 37545 | virtual const RegMask &out_RegMask() const; |
| 37546 | virtual uint rule() const { return vadd2L_reg_rule; } |
| 37547 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37548 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37549 | virtual uint oper_input_base() const { return 1; } |
| 37550 | public: |
| 37551 | vadd2L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37552 | virtual uint size_of() const { return sizeof(vadd2L_regNode); } |
| 37553 | static const Pipeline *pipeline_class(); |
| 37554 | virtual const Pipeline *pipeline() const; |
| 37555 | #ifndef PRODUCT |
| 37556 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37557 | virtual const char *Name() const { return "vadd2L_reg";} |
| 37558 | #endif |
| 37559 | }; |
| 37560 | |
| 37561 | class vadd2L_memNode : public MachTypeNode { |
| 37562 | private: |
| 37563 | MachOper *_opnd_array[3]; |
| 37564 | public: |
| 37565 | MachOper *opnd_array(uint operand_index) const { |
| 37566 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37567 | return _opnd_array[operand_index]; |
| 37568 | } |
| 37569 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37570 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37571 | _opnd_array[operand_index] = operand; |
| 37572 | } |
| 37573 | private: |
| 37574 | virtual const RegMask &out_RegMask() const; |
| 37575 | virtual uint rule() const { return vadd2L_mem_rule; } |
| 37576 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37577 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37578 | virtual int reloc() const; |
| 37579 | virtual uint oper_input_base() const { return 2; } |
| 37580 | public: |
| 37581 | vadd2L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37582 | virtual uint size_of() const { return sizeof(vadd2L_memNode); } |
| 37583 | static const Pipeline *pipeline_class(); |
| 37584 | virtual const Pipeline *pipeline() const; |
| 37585 | virtual const MachOper *memory_operand() const; |
| 37586 | #ifndef PRODUCT |
| 37587 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37588 | virtual const char *Name() const { return "vadd2L_mem";} |
| 37589 | #endif |
| 37590 | }; |
| 37591 | |
| 37592 | class vadd2L_mem_0Node : public MachTypeNode { |
| 37593 | private: |
| 37594 | MachOper *_opnd_array[3]; |
| 37595 | public: |
| 37596 | MachOper *opnd_array(uint operand_index) const { |
| 37597 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37598 | return _opnd_array[operand_index]; |
| 37599 | } |
| 37600 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37601 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37602 | _opnd_array[operand_index] = operand; |
| 37603 | } |
| 37604 | private: |
| 37605 | virtual const RegMask &out_RegMask() const; |
| 37606 | virtual uint rule() const { return vadd2L_mem_0_rule; } |
| 37607 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37608 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37609 | virtual int reloc() const; |
| 37610 | virtual uint oper_input_base() const { return 2; } |
| 37611 | public: |
| 37612 | vadd2L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37613 | virtual uint size_of() const { return sizeof(vadd2L_mem_0Node); } |
| 37614 | static const Pipeline *pipeline_class(); |
| 37615 | virtual const Pipeline *pipeline() const; |
| 37616 | virtual const MachOper *memory_operand() const; |
| 37617 | #ifndef PRODUCT |
| 37618 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37619 | virtual const char *Name() const { return "vadd2L_mem_0";} |
| 37620 | #endif |
| 37621 | }; |
| 37622 | |
| 37623 | class vadd4L_regNode : public MachTypeNode { |
| 37624 | private: |
| 37625 | MachOper *_opnd_array[3]; |
| 37626 | public: |
| 37627 | MachOper *opnd_array(uint operand_index) const { |
| 37628 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37629 | return _opnd_array[operand_index]; |
| 37630 | } |
| 37631 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37632 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37633 | _opnd_array[operand_index] = operand; |
| 37634 | } |
| 37635 | private: |
| 37636 | virtual const RegMask &out_RegMask() const; |
| 37637 | virtual uint rule() const { return vadd4L_reg_rule; } |
| 37638 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37639 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37640 | virtual uint oper_input_base() const { return 1; } |
| 37641 | public: |
| 37642 | vadd4L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37643 | virtual uint size_of() const { return sizeof(vadd4L_regNode); } |
| 37644 | static const Pipeline *pipeline_class(); |
| 37645 | virtual const Pipeline *pipeline() const; |
| 37646 | #ifndef PRODUCT |
| 37647 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37648 | virtual const char *Name() const { return "vadd4L_reg";} |
| 37649 | #endif |
| 37650 | }; |
| 37651 | |
| 37652 | class vadd4L_memNode : public MachTypeNode { |
| 37653 | private: |
| 37654 | MachOper *_opnd_array[3]; |
| 37655 | public: |
| 37656 | MachOper *opnd_array(uint operand_index) const { |
| 37657 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37658 | return _opnd_array[operand_index]; |
| 37659 | } |
| 37660 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37661 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37662 | _opnd_array[operand_index] = operand; |
| 37663 | } |
| 37664 | private: |
| 37665 | virtual const RegMask &out_RegMask() const; |
| 37666 | virtual uint rule() const { return vadd4L_mem_rule; } |
| 37667 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37668 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37669 | virtual int reloc() const; |
| 37670 | virtual uint oper_input_base() const { return 2; } |
| 37671 | public: |
| 37672 | vadd4L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37673 | virtual uint size_of() const { return sizeof(vadd4L_memNode); } |
| 37674 | static const Pipeline *pipeline_class(); |
| 37675 | virtual const Pipeline *pipeline() const; |
| 37676 | virtual const MachOper *memory_operand() const; |
| 37677 | #ifndef PRODUCT |
| 37678 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37679 | virtual const char *Name() const { return "vadd4L_mem";} |
| 37680 | #endif |
| 37681 | }; |
| 37682 | |
| 37683 | class vadd4L_mem_0Node : public MachTypeNode { |
| 37684 | private: |
| 37685 | MachOper *_opnd_array[3]; |
| 37686 | public: |
| 37687 | MachOper *opnd_array(uint operand_index) const { |
| 37688 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37689 | return _opnd_array[operand_index]; |
| 37690 | } |
| 37691 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37692 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37693 | _opnd_array[operand_index] = operand; |
| 37694 | } |
| 37695 | private: |
| 37696 | virtual const RegMask &out_RegMask() const; |
| 37697 | virtual uint rule() const { return vadd4L_mem_0_rule; } |
| 37698 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37699 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37700 | virtual int reloc() const; |
| 37701 | virtual uint oper_input_base() const { return 2; } |
| 37702 | public: |
| 37703 | vadd4L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37704 | virtual uint size_of() const { return sizeof(vadd4L_mem_0Node); } |
| 37705 | static const Pipeline *pipeline_class(); |
| 37706 | virtual const Pipeline *pipeline() const; |
| 37707 | virtual const MachOper *memory_operand() const; |
| 37708 | #ifndef PRODUCT |
| 37709 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37710 | virtual const char *Name() const { return "vadd4L_mem_0";} |
| 37711 | #endif |
| 37712 | }; |
| 37713 | |
| 37714 | class vadd8L_regNode : public MachTypeNode { |
| 37715 | private: |
| 37716 | MachOper *_opnd_array[3]; |
| 37717 | public: |
| 37718 | MachOper *opnd_array(uint operand_index) const { |
| 37719 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37720 | return _opnd_array[operand_index]; |
| 37721 | } |
| 37722 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37723 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37724 | _opnd_array[operand_index] = operand; |
| 37725 | } |
| 37726 | private: |
| 37727 | virtual const RegMask &out_RegMask() const; |
| 37728 | virtual uint rule() const { return vadd8L_reg_rule; } |
| 37729 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37730 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37731 | virtual uint oper_input_base() const { return 1; } |
| 37732 | public: |
| 37733 | vadd8L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37734 | virtual uint size_of() const { return sizeof(vadd8L_regNode); } |
| 37735 | static const Pipeline *pipeline_class(); |
| 37736 | virtual const Pipeline *pipeline() const; |
| 37737 | #ifndef PRODUCT |
| 37738 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37739 | virtual const char *Name() const { return "vadd8L_reg";} |
| 37740 | #endif |
| 37741 | }; |
| 37742 | |
| 37743 | class vadd8L_memNode : public MachTypeNode { |
| 37744 | private: |
| 37745 | MachOper *_opnd_array[3]; |
| 37746 | public: |
| 37747 | MachOper *opnd_array(uint operand_index) const { |
| 37748 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37749 | return _opnd_array[operand_index]; |
| 37750 | } |
| 37751 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37752 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37753 | _opnd_array[operand_index] = operand; |
| 37754 | } |
| 37755 | private: |
| 37756 | virtual const RegMask &out_RegMask() const; |
| 37757 | virtual uint rule() const { return vadd8L_mem_rule; } |
| 37758 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37759 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37760 | virtual int reloc() const; |
| 37761 | virtual uint oper_input_base() const { return 2; } |
| 37762 | public: |
| 37763 | vadd8L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37764 | virtual uint size_of() const { return sizeof(vadd8L_memNode); } |
| 37765 | static const Pipeline *pipeline_class(); |
| 37766 | virtual const Pipeline *pipeline() const; |
| 37767 | virtual const MachOper *memory_operand() const; |
| 37768 | #ifndef PRODUCT |
| 37769 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37770 | virtual const char *Name() const { return "vadd8L_mem";} |
| 37771 | #endif |
| 37772 | }; |
| 37773 | |
| 37774 | class vadd8L_mem_0Node : public MachTypeNode { |
| 37775 | private: |
| 37776 | MachOper *_opnd_array[3]; |
| 37777 | public: |
| 37778 | MachOper *opnd_array(uint operand_index) const { |
| 37779 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37780 | return _opnd_array[operand_index]; |
| 37781 | } |
| 37782 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37783 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37784 | _opnd_array[operand_index] = operand; |
| 37785 | } |
| 37786 | private: |
| 37787 | virtual const RegMask &out_RegMask() const; |
| 37788 | virtual uint rule() const { return vadd8L_mem_0_rule; } |
| 37789 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37790 | virtual int ideal_Opcode() const { return Op_AddVL; } |
| 37791 | virtual int reloc() const; |
| 37792 | virtual uint oper_input_base() const { return 2; } |
| 37793 | public: |
| 37794 | vadd8L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37795 | virtual uint size_of() const { return sizeof(vadd8L_mem_0Node); } |
| 37796 | static const Pipeline *pipeline_class(); |
| 37797 | virtual const Pipeline *pipeline() const; |
| 37798 | virtual const MachOper *memory_operand() const; |
| 37799 | #ifndef PRODUCT |
| 37800 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37801 | virtual const char *Name() const { return "vadd8L_mem_0";} |
| 37802 | #endif |
| 37803 | }; |
| 37804 | |
| 37805 | class vadd2FNode : public MachTypeNode { |
| 37806 | private: |
| 37807 | MachOper *_opnd_array[3]; |
| 37808 | public: |
| 37809 | MachOper *opnd_array(uint operand_index) const { |
| 37810 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37811 | return _opnd_array[operand_index]; |
| 37812 | } |
| 37813 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37814 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37815 | _opnd_array[operand_index] = operand; |
| 37816 | } |
| 37817 | private: |
| 37818 | virtual const RegMask &out_RegMask() const; |
| 37819 | virtual uint rule() const { return vadd2F_rule; } |
| 37820 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37821 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37822 | virtual uint two_adr() const { return oper_input_base(); } |
| 37823 | virtual uint oper_input_base() const { return 1; } |
| 37824 | public: |
| 37825 | vadd2FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37826 | virtual uint size_of() const { return sizeof(vadd2FNode); } |
| 37827 | static const Pipeline *pipeline_class(); |
| 37828 | virtual const Pipeline *pipeline() const; |
| 37829 | #ifndef PRODUCT |
| 37830 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37831 | virtual const char *Name() const { return "vadd2F";} |
| 37832 | #endif |
| 37833 | }; |
| 37834 | |
| 37835 | class vadd2F_regNode : public MachTypeNode { |
| 37836 | private: |
| 37837 | MachOper *_opnd_array[3]; |
| 37838 | public: |
| 37839 | MachOper *opnd_array(uint operand_index) const { |
| 37840 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37841 | return _opnd_array[operand_index]; |
| 37842 | } |
| 37843 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37844 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37845 | _opnd_array[operand_index] = operand; |
| 37846 | } |
| 37847 | private: |
| 37848 | virtual const RegMask &out_RegMask() const; |
| 37849 | virtual uint rule() const { return vadd2F_reg_rule; } |
| 37850 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37851 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37852 | virtual uint oper_input_base() const { return 1; } |
| 37853 | public: |
| 37854 | vadd2F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37855 | virtual uint size_of() const { return sizeof(vadd2F_regNode); } |
| 37856 | static const Pipeline *pipeline_class(); |
| 37857 | virtual const Pipeline *pipeline() const; |
| 37858 | #ifndef PRODUCT |
| 37859 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37860 | virtual const char *Name() const { return "vadd2F_reg";} |
| 37861 | #endif |
| 37862 | }; |
| 37863 | |
| 37864 | class vadd2F_memNode : public MachTypeNode { |
| 37865 | private: |
| 37866 | MachOper *_opnd_array[3]; |
| 37867 | public: |
| 37868 | MachOper *opnd_array(uint operand_index) const { |
| 37869 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37870 | return _opnd_array[operand_index]; |
| 37871 | } |
| 37872 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37873 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37874 | _opnd_array[operand_index] = operand; |
| 37875 | } |
| 37876 | private: |
| 37877 | virtual const RegMask &out_RegMask() const; |
| 37878 | virtual uint rule() const { return vadd2F_mem_rule; } |
| 37879 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37880 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37881 | virtual int reloc() const; |
| 37882 | virtual uint oper_input_base() const { return 2; } |
| 37883 | public: |
| 37884 | vadd2F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37885 | virtual uint size_of() const { return sizeof(vadd2F_memNode); } |
| 37886 | static const Pipeline *pipeline_class(); |
| 37887 | virtual const Pipeline *pipeline() const; |
| 37888 | virtual const MachOper *memory_operand() const; |
| 37889 | #ifndef PRODUCT |
| 37890 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37891 | virtual const char *Name() const { return "vadd2F_mem";} |
| 37892 | #endif |
| 37893 | }; |
| 37894 | |
| 37895 | class vadd2F_mem_0Node : public MachTypeNode { |
| 37896 | private: |
| 37897 | MachOper *_opnd_array[3]; |
| 37898 | public: |
| 37899 | MachOper *opnd_array(uint operand_index) const { |
| 37900 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37901 | return _opnd_array[operand_index]; |
| 37902 | } |
| 37903 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37904 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37905 | _opnd_array[operand_index] = operand; |
| 37906 | } |
| 37907 | private: |
| 37908 | virtual const RegMask &out_RegMask() const; |
| 37909 | virtual uint rule() const { return vadd2F_mem_0_rule; } |
| 37910 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37911 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37912 | virtual int reloc() const; |
| 37913 | virtual uint oper_input_base() const { return 2; } |
| 37914 | public: |
| 37915 | vadd2F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 37916 | virtual uint size_of() const { return sizeof(vadd2F_mem_0Node); } |
| 37917 | static const Pipeline *pipeline_class(); |
| 37918 | virtual const Pipeline *pipeline() const; |
| 37919 | virtual const MachOper *memory_operand() const; |
| 37920 | #ifndef PRODUCT |
| 37921 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37922 | virtual const char *Name() const { return "vadd2F_mem_0";} |
| 37923 | #endif |
| 37924 | }; |
| 37925 | |
| 37926 | class vadd4FNode : public MachTypeNode { |
| 37927 | private: |
| 37928 | MachOper *_opnd_array[3]; |
| 37929 | public: |
| 37930 | MachOper *opnd_array(uint operand_index) const { |
| 37931 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37932 | return _opnd_array[operand_index]; |
| 37933 | } |
| 37934 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37935 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37936 | _opnd_array[operand_index] = operand; |
| 37937 | } |
| 37938 | private: |
| 37939 | virtual const RegMask &out_RegMask() const; |
| 37940 | virtual uint rule() const { return vadd4F_rule; } |
| 37941 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37942 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37943 | virtual uint two_adr() const { return oper_input_base(); } |
| 37944 | virtual uint oper_input_base() const { return 1; } |
| 37945 | public: |
| 37946 | vadd4FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37947 | virtual uint size_of() const { return sizeof(vadd4FNode); } |
| 37948 | static const Pipeline *pipeline_class(); |
| 37949 | virtual const Pipeline *pipeline() const; |
| 37950 | #ifndef PRODUCT |
| 37951 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37952 | virtual const char *Name() const { return "vadd4F";} |
| 37953 | #endif |
| 37954 | }; |
| 37955 | |
| 37956 | class vadd4F_regNode : public MachTypeNode { |
| 37957 | private: |
| 37958 | MachOper *_opnd_array[3]; |
| 37959 | public: |
| 37960 | MachOper *opnd_array(uint operand_index) const { |
| 37961 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37962 | return _opnd_array[operand_index]; |
| 37963 | } |
| 37964 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37965 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37966 | _opnd_array[operand_index] = operand; |
| 37967 | } |
| 37968 | private: |
| 37969 | virtual const RegMask &out_RegMask() const; |
| 37970 | virtual uint rule() const { return vadd4F_reg_rule; } |
| 37971 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 37972 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 37973 | virtual uint oper_input_base() const { return 1; } |
| 37974 | public: |
| 37975 | vadd4F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 37976 | virtual uint size_of() const { return sizeof(vadd4F_regNode); } |
| 37977 | static const Pipeline *pipeline_class(); |
| 37978 | virtual const Pipeline *pipeline() const; |
| 37979 | #ifndef PRODUCT |
| 37980 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 37981 | virtual const char *Name() const { return "vadd4F_reg";} |
| 37982 | #endif |
| 37983 | }; |
| 37984 | |
| 37985 | class vadd4F_memNode : public MachTypeNode { |
| 37986 | private: |
| 37987 | MachOper *_opnd_array[3]; |
| 37988 | public: |
| 37989 | MachOper *opnd_array(uint operand_index) const { |
| 37990 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37991 | return _opnd_array[operand_index]; |
| 37992 | } |
| 37993 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 37994 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 37995 | _opnd_array[operand_index] = operand; |
| 37996 | } |
| 37997 | private: |
| 37998 | virtual const RegMask &out_RegMask() const; |
| 37999 | virtual uint rule() const { return vadd4F_mem_rule; } |
| 38000 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38001 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38002 | virtual int reloc() const; |
| 38003 | virtual uint oper_input_base() const { return 2; } |
| 38004 | public: |
| 38005 | vadd4F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38006 | virtual uint size_of() const { return sizeof(vadd4F_memNode); } |
| 38007 | static const Pipeline *pipeline_class(); |
| 38008 | virtual const Pipeline *pipeline() const; |
| 38009 | virtual const MachOper *memory_operand() const; |
| 38010 | #ifndef PRODUCT |
| 38011 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38012 | virtual const char *Name() const { return "vadd4F_mem";} |
| 38013 | #endif |
| 38014 | }; |
| 38015 | |
| 38016 | class vadd4F_mem_0Node : public MachTypeNode { |
| 38017 | private: |
| 38018 | MachOper *_opnd_array[3]; |
| 38019 | public: |
| 38020 | MachOper *opnd_array(uint operand_index) const { |
| 38021 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38022 | return _opnd_array[operand_index]; |
| 38023 | } |
| 38024 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38025 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38026 | _opnd_array[operand_index] = operand; |
| 38027 | } |
| 38028 | private: |
| 38029 | virtual const RegMask &out_RegMask() const; |
| 38030 | virtual uint rule() const { return vadd4F_mem_0_rule; } |
| 38031 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38032 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38033 | virtual int reloc() const; |
| 38034 | virtual uint oper_input_base() const { return 2; } |
| 38035 | public: |
| 38036 | vadd4F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38037 | virtual uint size_of() const { return sizeof(vadd4F_mem_0Node); } |
| 38038 | static const Pipeline *pipeline_class(); |
| 38039 | virtual const Pipeline *pipeline() const; |
| 38040 | virtual const MachOper *memory_operand() const; |
| 38041 | #ifndef PRODUCT |
| 38042 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38043 | virtual const char *Name() const { return "vadd4F_mem_0";} |
| 38044 | #endif |
| 38045 | }; |
| 38046 | |
| 38047 | class vadd8F_regNode : public MachTypeNode { |
| 38048 | private: |
| 38049 | MachOper *_opnd_array[3]; |
| 38050 | public: |
| 38051 | MachOper *opnd_array(uint operand_index) const { |
| 38052 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38053 | return _opnd_array[operand_index]; |
| 38054 | } |
| 38055 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38056 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38057 | _opnd_array[operand_index] = operand; |
| 38058 | } |
| 38059 | private: |
| 38060 | virtual const RegMask &out_RegMask() const; |
| 38061 | virtual uint rule() const { return vadd8F_reg_rule; } |
| 38062 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38063 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38064 | virtual uint oper_input_base() const { return 1; } |
| 38065 | public: |
| 38066 | vadd8F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38067 | virtual uint size_of() const { return sizeof(vadd8F_regNode); } |
| 38068 | static const Pipeline *pipeline_class(); |
| 38069 | virtual const Pipeline *pipeline() const; |
| 38070 | #ifndef PRODUCT |
| 38071 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38072 | virtual const char *Name() const { return "vadd8F_reg";} |
| 38073 | #endif |
| 38074 | }; |
| 38075 | |
| 38076 | class vadd8F_memNode : public MachTypeNode { |
| 38077 | private: |
| 38078 | MachOper *_opnd_array[3]; |
| 38079 | public: |
| 38080 | MachOper *opnd_array(uint operand_index) const { |
| 38081 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38082 | return _opnd_array[operand_index]; |
| 38083 | } |
| 38084 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38085 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38086 | _opnd_array[operand_index] = operand; |
| 38087 | } |
| 38088 | private: |
| 38089 | virtual const RegMask &out_RegMask() const; |
| 38090 | virtual uint rule() const { return vadd8F_mem_rule; } |
| 38091 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38092 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38093 | virtual int reloc() const; |
| 38094 | virtual uint oper_input_base() const { return 2; } |
| 38095 | public: |
| 38096 | vadd8F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38097 | virtual uint size_of() const { return sizeof(vadd8F_memNode); } |
| 38098 | static const Pipeline *pipeline_class(); |
| 38099 | virtual const Pipeline *pipeline() const; |
| 38100 | virtual const MachOper *memory_operand() const; |
| 38101 | #ifndef PRODUCT |
| 38102 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38103 | virtual const char *Name() const { return "vadd8F_mem";} |
| 38104 | #endif |
| 38105 | }; |
| 38106 | |
| 38107 | class vadd8F_mem_0Node : public MachTypeNode { |
| 38108 | private: |
| 38109 | MachOper *_opnd_array[3]; |
| 38110 | public: |
| 38111 | MachOper *opnd_array(uint operand_index) const { |
| 38112 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38113 | return _opnd_array[operand_index]; |
| 38114 | } |
| 38115 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38116 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38117 | _opnd_array[operand_index] = operand; |
| 38118 | } |
| 38119 | private: |
| 38120 | virtual const RegMask &out_RegMask() const; |
| 38121 | virtual uint rule() const { return vadd8F_mem_0_rule; } |
| 38122 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38123 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38124 | virtual int reloc() const; |
| 38125 | virtual uint oper_input_base() const { return 2; } |
| 38126 | public: |
| 38127 | vadd8F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38128 | virtual uint size_of() const { return sizeof(vadd8F_mem_0Node); } |
| 38129 | static const Pipeline *pipeline_class(); |
| 38130 | virtual const Pipeline *pipeline() const; |
| 38131 | virtual const MachOper *memory_operand() const; |
| 38132 | #ifndef PRODUCT |
| 38133 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38134 | virtual const char *Name() const { return "vadd8F_mem_0";} |
| 38135 | #endif |
| 38136 | }; |
| 38137 | |
| 38138 | class vadd16F_regNode : public MachTypeNode { |
| 38139 | private: |
| 38140 | MachOper *_opnd_array[3]; |
| 38141 | public: |
| 38142 | MachOper *opnd_array(uint operand_index) const { |
| 38143 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38144 | return _opnd_array[operand_index]; |
| 38145 | } |
| 38146 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38147 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38148 | _opnd_array[operand_index] = operand; |
| 38149 | } |
| 38150 | private: |
| 38151 | virtual const RegMask &out_RegMask() const; |
| 38152 | virtual uint rule() const { return vadd16F_reg_rule; } |
| 38153 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38154 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38155 | virtual uint oper_input_base() const { return 1; } |
| 38156 | public: |
| 38157 | vadd16F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38158 | virtual uint size_of() const { return sizeof(vadd16F_regNode); } |
| 38159 | static const Pipeline *pipeline_class(); |
| 38160 | virtual const Pipeline *pipeline() const; |
| 38161 | #ifndef PRODUCT |
| 38162 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38163 | virtual const char *Name() const { return "vadd16F_reg";} |
| 38164 | #endif |
| 38165 | }; |
| 38166 | |
| 38167 | class vadd16F_memNode : public MachTypeNode { |
| 38168 | private: |
| 38169 | MachOper *_opnd_array[3]; |
| 38170 | public: |
| 38171 | MachOper *opnd_array(uint operand_index) const { |
| 38172 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38173 | return _opnd_array[operand_index]; |
| 38174 | } |
| 38175 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38176 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38177 | _opnd_array[operand_index] = operand; |
| 38178 | } |
| 38179 | private: |
| 38180 | virtual const RegMask &out_RegMask() const; |
| 38181 | virtual uint rule() const { return vadd16F_mem_rule; } |
| 38182 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38183 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38184 | virtual int reloc() const; |
| 38185 | virtual uint oper_input_base() const { return 2; } |
| 38186 | public: |
| 38187 | vadd16F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38188 | virtual uint size_of() const { return sizeof(vadd16F_memNode); } |
| 38189 | static const Pipeline *pipeline_class(); |
| 38190 | virtual const Pipeline *pipeline() const; |
| 38191 | virtual const MachOper *memory_operand() const; |
| 38192 | #ifndef PRODUCT |
| 38193 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38194 | virtual const char *Name() const { return "vadd16F_mem";} |
| 38195 | #endif |
| 38196 | }; |
| 38197 | |
| 38198 | class vadd16F_mem_0Node : public MachTypeNode { |
| 38199 | private: |
| 38200 | MachOper *_opnd_array[3]; |
| 38201 | public: |
| 38202 | MachOper *opnd_array(uint operand_index) const { |
| 38203 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38204 | return _opnd_array[operand_index]; |
| 38205 | } |
| 38206 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38207 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38208 | _opnd_array[operand_index] = operand; |
| 38209 | } |
| 38210 | private: |
| 38211 | virtual const RegMask &out_RegMask() const; |
| 38212 | virtual uint rule() const { return vadd16F_mem_0_rule; } |
| 38213 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38214 | virtual int ideal_Opcode() const { return Op_AddVF; } |
| 38215 | virtual int reloc() const; |
| 38216 | virtual uint oper_input_base() const { return 2; } |
| 38217 | public: |
| 38218 | vadd16F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38219 | virtual uint size_of() const { return sizeof(vadd16F_mem_0Node); } |
| 38220 | static const Pipeline *pipeline_class(); |
| 38221 | virtual const Pipeline *pipeline() const; |
| 38222 | virtual const MachOper *memory_operand() const; |
| 38223 | #ifndef PRODUCT |
| 38224 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38225 | virtual const char *Name() const { return "vadd16F_mem_0";} |
| 38226 | #endif |
| 38227 | }; |
| 38228 | |
| 38229 | class vadd2DNode : public MachTypeNode { |
| 38230 | private: |
| 38231 | MachOper *_opnd_array[3]; |
| 38232 | public: |
| 38233 | MachOper *opnd_array(uint operand_index) const { |
| 38234 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38235 | return _opnd_array[operand_index]; |
| 38236 | } |
| 38237 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38238 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38239 | _opnd_array[operand_index] = operand; |
| 38240 | } |
| 38241 | private: |
| 38242 | virtual const RegMask &out_RegMask() const; |
| 38243 | virtual uint rule() const { return vadd2D_rule; } |
| 38244 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38245 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38246 | virtual uint two_adr() const { return oper_input_base(); } |
| 38247 | virtual uint oper_input_base() const { return 1; } |
| 38248 | public: |
| 38249 | vadd2DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38250 | virtual uint size_of() const { return sizeof(vadd2DNode); } |
| 38251 | static const Pipeline *pipeline_class(); |
| 38252 | virtual const Pipeline *pipeline() const; |
| 38253 | #ifndef PRODUCT |
| 38254 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38255 | virtual const char *Name() const { return "vadd2D";} |
| 38256 | #endif |
| 38257 | }; |
| 38258 | |
| 38259 | class vadd2D_regNode : public MachTypeNode { |
| 38260 | private: |
| 38261 | MachOper *_opnd_array[3]; |
| 38262 | public: |
| 38263 | MachOper *opnd_array(uint operand_index) const { |
| 38264 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38265 | return _opnd_array[operand_index]; |
| 38266 | } |
| 38267 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38268 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38269 | _opnd_array[operand_index] = operand; |
| 38270 | } |
| 38271 | private: |
| 38272 | virtual const RegMask &out_RegMask() const; |
| 38273 | virtual uint rule() const { return vadd2D_reg_rule; } |
| 38274 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38275 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38276 | virtual uint oper_input_base() const { return 1; } |
| 38277 | public: |
| 38278 | vadd2D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38279 | virtual uint size_of() const { return sizeof(vadd2D_regNode); } |
| 38280 | static const Pipeline *pipeline_class(); |
| 38281 | virtual const Pipeline *pipeline() const; |
| 38282 | #ifndef PRODUCT |
| 38283 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38284 | virtual const char *Name() const { return "vadd2D_reg";} |
| 38285 | #endif |
| 38286 | }; |
| 38287 | |
| 38288 | class vadd2D_memNode : public MachTypeNode { |
| 38289 | private: |
| 38290 | MachOper *_opnd_array[3]; |
| 38291 | public: |
| 38292 | MachOper *opnd_array(uint operand_index) const { |
| 38293 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38294 | return _opnd_array[operand_index]; |
| 38295 | } |
| 38296 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38297 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38298 | _opnd_array[operand_index] = operand; |
| 38299 | } |
| 38300 | private: |
| 38301 | virtual const RegMask &out_RegMask() const; |
| 38302 | virtual uint rule() const { return vadd2D_mem_rule; } |
| 38303 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38304 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38305 | virtual int reloc() const; |
| 38306 | virtual uint oper_input_base() const { return 2; } |
| 38307 | public: |
| 38308 | vadd2D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38309 | virtual uint size_of() const { return sizeof(vadd2D_memNode); } |
| 38310 | static const Pipeline *pipeline_class(); |
| 38311 | virtual const Pipeline *pipeline() const; |
| 38312 | virtual const MachOper *memory_operand() const; |
| 38313 | #ifndef PRODUCT |
| 38314 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38315 | virtual const char *Name() const { return "vadd2D_mem";} |
| 38316 | #endif |
| 38317 | }; |
| 38318 | |
| 38319 | class vadd2D_mem_0Node : public MachTypeNode { |
| 38320 | private: |
| 38321 | MachOper *_opnd_array[3]; |
| 38322 | public: |
| 38323 | MachOper *opnd_array(uint operand_index) const { |
| 38324 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38325 | return _opnd_array[operand_index]; |
| 38326 | } |
| 38327 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38328 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38329 | _opnd_array[operand_index] = operand; |
| 38330 | } |
| 38331 | private: |
| 38332 | virtual const RegMask &out_RegMask() const; |
| 38333 | virtual uint rule() const { return vadd2D_mem_0_rule; } |
| 38334 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38335 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38336 | virtual int reloc() const; |
| 38337 | virtual uint oper_input_base() const { return 2; } |
| 38338 | public: |
| 38339 | vadd2D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38340 | virtual uint size_of() const { return sizeof(vadd2D_mem_0Node); } |
| 38341 | static const Pipeline *pipeline_class(); |
| 38342 | virtual const Pipeline *pipeline() const; |
| 38343 | virtual const MachOper *memory_operand() const; |
| 38344 | #ifndef PRODUCT |
| 38345 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38346 | virtual const char *Name() const { return "vadd2D_mem_0";} |
| 38347 | #endif |
| 38348 | }; |
| 38349 | |
| 38350 | class vadd4D_regNode : public MachTypeNode { |
| 38351 | private: |
| 38352 | MachOper *_opnd_array[3]; |
| 38353 | public: |
| 38354 | MachOper *opnd_array(uint operand_index) const { |
| 38355 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38356 | return _opnd_array[operand_index]; |
| 38357 | } |
| 38358 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38359 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38360 | _opnd_array[operand_index] = operand; |
| 38361 | } |
| 38362 | private: |
| 38363 | virtual const RegMask &out_RegMask() const; |
| 38364 | virtual uint rule() const { return vadd4D_reg_rule; } |
| 38365 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38366 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38367 | virtual uint oper_input_base() const { return 1; } |
| 38368 | public: |
| 38369 | vadd4D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38370 | virtual uint size_of() const { return sizeof(vadd4D_regNode); } |
| 38371 | static const Pipeline *pipeline_class(); |
| 38372 | virtual const Pipeline *pipeline() const; |
| 38373 | #ifndef PRODUCT |
| 38374 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38375 | virtual const char *Name() const { return "vadd4D_reg";} |
| 38376 | #endif |
| 38377 | }; |
| 38378 | |
| 38379 | class vadd4D_memNode : public MachTypeNode { |
| 38380 | private: |
| 38381 | MachOper *_opnd_array[3]; |
| 38382 | public: |
| 38383 | MachOper *opnd_array(uint operand_index) const { |
| 38384 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38385 | return _opnd_array[operand_index]; |
| 38386 | } |
| 38387 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38388 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38389 | _opnd_array[operand_index] = operand; |
| 38390 | } |
| 38391 | private: |
| 38392 | virtual const RegMask &out_RegMask() const; |
| 38393 | virtual uint rule() const { return vadd4D_mem_rule; } |
| 38394 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38395 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38396 | virtual int reloc() const; |
| 38397 | virtual uint oper_input_base() const { return 2; } |
| 38398 | public: |
| 38399 | vadd4D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38400 | virtual uint size_of() const { return sizeof(vadd4D_memNode); } |
| 38401 | static const Pipeline *pipeline_class(); |
| 38402 | virtual const Pipeline *pipeline() const; |
| 38403 | virtual const MachOper *memory_operand() const; |
| 38404 | #ifndef PRODUCT |
| 38405 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38406 | virtual const char *Name() const { return "vadd4D_mem";} |
| 38407 | #endif |
| 38408 | }; |
| 38409 | |
| 38410 | class vadd4D_mem_0Node : public MachTypeNode { |
| 38411 | private: |
| 38412 | MachOper *_opnd_array[3]; |
| 38413 | public: |
| 38414 | MachOper *opnd_array(uint operand_index) const { |
| 38415 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38416 | return _opnd_array[operand_index]; |
| 38417 | } |
| 38418 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38419 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38420 | _opnd_array[operand_index] = operand; |
| 38421 | } |
| 38422 | private: |
| 38423 | virtual const RegMask &out_RegMask() const; |
| 38424 | virtual uint rule() const { return vadd4D_mem_0_rule; } |
| 38425 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38426 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38427 | virtual int reloc() const; |
| 38428 | virtual uint oper_input_base() const { return 2; } |
| 38429 | public: |
| 38430 | vadd4D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38431 | virtual uint size_of() const { return sizeof(vadd4D_mem_0Node); } |
| 38432 | static const Pipeline *pipeline_class(); |
| 38433 | virtual const Pipeline *pipeline() const; |
| 38434 | virtual const MachOper *memory_operand() const; |
| 38435 | #ifndef PRODUCT |
| 38436 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38437 | virtual const char *Name() const { return "vadd4D_mem_0";} |
| 38438 | #endif |
| 38439 | }; |
| 38440 | |
| 38441 | class vadd8D_regNode : public MachTypeNode { |
| 38442 | private: |
| 38443 | MachOper *_opnd_array[3]; |
| 38444 | public: |
| 38445 | MachOper *opnd_array(uint operand_index) const { |
| 38446 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38447 | return _opnd_array[operand_index]; |
| 38448 | } |
| 38449 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38450 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38451 | _opnd_array[operand_index] = operand; |
| 38452 | } |
| 38453 | private: |
| 38454 | virtual const RegMask &out_RegMask() const; |
| 38455 | virtual uint rule() const { return vadd8D_reg_rule; } |
| 38456 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38457 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38458 | virtual uint oper_input_base() const { return 1; } |
| 38459 | public: |
| 38460 | vadd8D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38461 | virtual uint size_of() const { return sizeof(vadd8D_regNode); } |
| 38462 | static const Pipeline *pipeline_class(); |
| 38463 | virtual const Pipeline *pipeline() const; |
| 38464 | #ifndef PRODUCT |
| 38465 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38466 | virtual const char *Name() const { return "vadd8D_reg";} |
| 38467 | #endif |
| 38468 | }; |
| 38469 | |
| 38470 | class vadd8D_memNode : public MachTypeNode { |
| 38471 | private: |
| 38472 | MachOper *_opnd_array[3]; |
| 38473 | public: |
| 38474 | MachOper *opnd_array(uint operand_index) const { |
| 38475 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38476 | return _opnd_array[operand_index]; |
| 38477 | } |
| 38478 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38479 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38480 | _opnd_array[operand_index] = operand; |
| 38481 | } |
| 38482 | private: |
| 38483 | virtual const RegMask &out_RegMask() const; |
| 38484 | virtual uint rule() const { return vadd8D_mem_rule; } |
| 38485 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38486 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38487 | virtual int reloc() const; |
| 38488 | virtual uint oper_input_base() const { return 2; } |
| 38489 | public: |
| 38490 | vadd8D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38491 | virtual uint size_of() const { return sizeof(vadd8D_memNode); } |
| 38492 | static const Pipeline *pipeline_class(); |
| 38493 | virtual const Pipeline *pipeline() const; |
| 38494 | virtual const MachOper *memory_operand() const; |
| 38495 | #ifndef PRODUCT |
| 38496 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38497 | virtual const char *Name() const { return "vadd8D_mem";} |
| 38498 | #endif |
| 38499 | }; |
| 38500 | |
| 38501 | class vadd8D_mem_0Node : public MachTypeNode { |
| 38502 | private: |
| 38503 | MachOper *_opnd_array[3]; |
| 38504 | public: |
| 38505 | MachOper *opnd_array(uint operand_index) const { |
| 38506 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38507 | return _opnd_array[operand_index]; |
| 38508 | } |
| 38509 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38511 | _opnd_array[operand_index] = operand; |
| 38512 | } |
| 38513 | private: |
| 38514 | virtual const RegMask &out_RegMask() const; |
| 38515 | virtual uint rule() const { return vadd8D_mem_0_rule; } |
| 38516 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38517 | virtual int ideal_Opcode() const { return Op_AddVD; } |
| 38518 | virtual int reloc() const; |
| 38519 | virtual uint oper_input_base() const { return 2; } |
| 38520 | public: |
| 38521 | vadd8D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38522 | virtual uint size_of() const { return sizeof(vadd8D_mem_0Node); } |
| 38523 | static const Pipeline *pipeline_class(); |
| 38524 | virtual const Pipeline *pipeline() const; |
| 38525 | virtual const MachOper *memory_operand() const; |
| 38526 | #ifndef PRODUCT |
| 38527 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38528 | virtual const char *Name() const { return "vadd8D_mem_0";} |
| 38529 | #endif |
| 38530 | }; |
| 38531 | |
| 38532 | class vsub4BNode : public MachTypeNode { |
| 38533 | private: |
| 38534 | MachOper *_opnd_array[3]; |
| 38535 | public: |
| 38536 | MachOper *opnd_array(uint operand_index) const { |
| 38537 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38538 | return _opnd_array[operand_index]; |
| 38539 | } |
| 38540 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38541 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38542 | _opnd_array[operand_index] = operand; |
| 38543 | } |
| 38544 | private: |
| 38545 | virtual const RegMask &out_RegMask() const; |
| 38546 | virtual uint rule() const { return vsub4B_rule; } |
| 38547 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38548 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38549 | virtual uint two_adr() const { return oper_input_base(); } |
| 38550 | virtual uint oper_input_base() const { return 1; } |
| 38551 | public: |
| 38552 | vsub4BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38553 | virtual uint size_of() const { return sizeof(vsub4BNode); } |
| 38554 | static const Pipeline *pipeline_class(); |
| 38555 | virtual const Pipeline *pipeline() const; |
| 38556 | #ifndef PRODUCT |
| 38557 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38558 | virtual const char *Name() const { return "vsub4B";} |
| 38559 | #endif |
| 38560 | }; |
| 38561 | |
| 38562 | class vsub4B_regNode : public MachTypeNode { |
| 38563 | private: |
| 38564 | MachOper *_opnd_array[3]; |
| 38565 | public: |
| 38566 | MachOper *opnd_array(uint operand_index) const { |
| 38567 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38568 | return _opnd_array[operand_index]; |
| 38569 | } |
| 38570 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38571 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38572 | _opnd_array[operand_index] = operand; |
| 38573 | } |
| 38574 | private: |
| 38575 | virtual const RegMask &out_RegMask() const; |
| 38576 | virtual uint rule() const { return vsub4B_reg_rule; } |
| 38577 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38578 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38579 | virtual uint oper_input_base() const { return 1; } |
| 38580 | public: |
| 38581 | vsub4B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38582 | virtual uint size_of() const { return sizeof(vsub4B_regNode); } |
| 38583 | static const Pipeline *pipeline_class(); |
| 38584 | virtual const Pipeline *pipeline() const; |
| 38585 | #ifndef PRODUCT |
| 38586 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38587 | virtual const char *Name() const { return "vsub4B_reg";} |
| 38588 | #endif |
| 38589 | }; |
| 38590 | |
| 38591 | class vsub4B_memNode : public MachTypeNode { |
| 38592 | private: |
| 38593 | MachOper *_opnd_array[3]; |
| 38594 | public: |
| 38595 | MachOper *opnd_array(uint operand_index) const { |
| 38596 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38597 | return _opnd_array[operand_index]; |
| 38598 | } |
| 38599 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38600 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38601 | _opnd_array[operand_index] = operand; |
| 38602 | } |
| 38603 | private: |
| 38604 | virtual const RegMask &out_RegMask() const; |
| 38605 | virtual uint rule() const { return vsub4B_mem_rule; } |
| 38606 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38607 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38608 | virtual int reloc() const; |
| 38609 | virtual uint oper_input_base() const { return 2; } |
| 38610 | public: |
| 38611 | vsub4B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38612 | virtual uint size_of() const { return sizeof(vsub4B_memNode); } |
| 38613 | static const Pipeline *pipeline_class(); |
| 38614 | virtual const Pipeline *pipeline() const; |
| 38615 | virtual const MachOper *memory_operand() const; |
| 38616 | #ifndef PRODUCT |
| 38617 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38618 | virtual const char *Name() const { return "vsub4B_mem";} |
| 38619 | #endif |
| 38620 | }; |
| 38621 | |
| 38622 | class vsub8BNode : public MachTypeNode { |
| 38623 | private: |
| 38624 | MachOper *_opnd_array[3]; |
| 38625 | public: |
| 38626 | MachOper *opnd_array(uint operand_index) const { |
| 38627 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38628 | return _opnd_array[operand_index]; |
| 38629 | } |
| 38630 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38631 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38632 | _opnd_array[operand_index] = operand; |
| 38633 | } |
| 38634 | private: |
| 38635 | virtual const RegMask &out_RegMask() const; |
| 38636 | virtual uint rule() const { return vsub8B_rule; } |
| 38637 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38638 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38639 | virtual uint two_adr() const { return oper_input_base(); } |
| 38640 | virtual uint oper_input_base() const { return 1; } |
| 38641 | public: |
| 38642 | vsub8BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38643 | virtual uint size_of() const { return sizeof(vsub8BNode); } |
| 38644 | static const Pipeline *pipeline_class(); |
| 38645 | virtual const Pipeline *pipeline() const; |
| 38646 | #ifndef PRODUCT |
| 38647 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38648 | virtual const char *Name() const { return "vsub8B";} |
| 38649 | #endif |
| 38650 | }; |
| 38651 | |
| 38652 | class vsub8B_regNode : public MachTypeNode { |
| 38653 | private: |
| 38654 | MachOper *_opnd_array[3]; |
| 38655 | public: |
| 38656 | MachOper *opnd_array(uint operand_index) const { |
| 38657 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38658 | return _opnd_array[operand_index]; |
| 38659 | } |
| 38660 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38661 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38662 | _opnd_array[operand_index] = operand; |
| 38663 | } |
| 38664 | private: |
| 38665 | virtual const RegMask &out_RegMask() const; |
| 38666 | virtual uint rule() const { return vsub8B_reg_rule; } |
| 38667 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38668 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38669 | virtual uint oper_input_base() const { return 1; } |
| 38670 | public: |
| 38671 | vsub8B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38672 | virtual uint size_of() const { return sizeof(vsub8B_regNode); } |
| 38673 | static const Pipeline *pipeline_class(); |
| 38674 | virtual const Pipeline *pipeline() const; |
| 38675 | #ifndef PRODUCT |
| 38676 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38677 | virtual const char *Name() const { return "vsub8B_reg";} |
| 38678 | #endif |
| 38679 | }; |
| 38680 | |
| 38681 | class vsub8B_memNode : public MachTypeNode { |
| 38682 | private: |
| 38683 | MachOper *_opnd_array[3]; |
| 38684 | public: |
| 38685 | MachOper *opnd_array(uint operand_index) const { |
| 38686 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38687 | return _opnd_array[operand_index]; |
| 38688 | } |
| 38689 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38690 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38691 | _opnd_array[operand_index] = operand; |
| 38692 | } |
| 38693 | private: |
| 38694 | virtual const RegMask &out_RegMask() const; |
| 38695 | virtual uint rule() const { return vsub8B_mem_rule; } |
| 38696 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38697 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38698 | virtual int reloc() const; |
| 38699 | virtual uint oper_input_base() const { return 2; } |
| 38700 | public: |
| 38701 | vsub8B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38702 | virtual uint size_of() const { return sizeof(vsub8B_memNode); } |
| 38703 | static const Pipeline *pipeline_class(); |
| 38704 | virtual const Pipeline *pipeline() const; |
| 38705 | virtual const MachOper *memory_operand() const; |
| 38706 | #ifndef PRODUCT |
| 38707 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38708 | virtual const char *Name() const { return "vsub8B_mem";} |
| 38709 | #endif |
| 38710 | }; |
| 38711 | |
| 38712 | class vsub16BNode : public MachTypeNode { |
| 38713 | private: |
| 38714 | MachOper *_opnd_array[3]; |
| 38715 | public: |
| 38716 | MachOper *opnd_array(uint operand_index) const { |
| 38717 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38718 | return _opnd_array[operand_index]; |
| 38719 | } |
| 38720 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38721 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38722 | _opnd_array[operand_index] = operand; |
| 38723 | } |
| 38724 | private: |
| 38725 | virtual const RegMask &out_RegMask() const; |
| 38726 | virtual uint rule() const { return vsub16B_rule; } |
| 38727 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38728 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38729 | virtual uint two_adr() const { return oper_input_base(); } |
| 38730 | virtual uint oper_input_base() const { return 1; } |
| 38731 | public: |
| 38732 | vsub16BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38733 | virtual uint size_of() const { return sizeof(vsub16BNode); } |
| 38734 | static const Pipeline *pipeline_class(); |
| 38735 | virtual const Pipeline *pipeline() const; |
| 38736 | #ifndef PRODUCT |
| 38737 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38738 | virtual const char *Name() const { return "vsub16B";} |
| 38739 | #endif |
| 38740 | }; |
| 38741 | |
| 38742 | class vsub16B_regNode : public MachTypeNode { |
| 38743 | private: |
| 38744 | MachOper *_opnd_array[3]; |
| 38745 | public: |
| 38746 | MachOper *opnd_array(uint operand_index) const { |
| 38747 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38748 | return _opnd_array[operand_index]; |
| 38749 | } |
| 38750 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38751 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38752 | _opnd_array[operand_index] = operand; |
| 38753 | } |
| 38754 | private: |
| 38755 | virtual const RegMask &out_RegMask() const; |
| 38756 | virtual uint rule() const { return vsub16B_reg_rule; } |
| 38757 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38758 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38759 | virtual uint oper_input_base() const { return 1; } |
| 38760 | public: |
| 38761 | vsub16B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38762 | virtual uint size_of() const { return sizeof(vsub16B_regNode); } |
| 38763 | static const Pipeline *pipeline_class(); |
| 38764 | virtual const Pipeline *pipeline() const; |
| 38765 | #ifndef PRODUCT |
| 38766 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38767 | virtual const char *Name() const { return "vsub16B_reg";} |
| 38768 | #endif |
| 38769 | }; |
| 38770 | |
| 38771 | class vsub16B_memNode : public MachTypeNode { |
| 38772 | private: |
| 38773 | MachOper *_opnd_array[3]; |
| 38774 | public: |
| 38775 | MachOper *opnd_array(uint operand_index) const { |
| 38776 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38777 | return _opnd_array[operand_index]; |
| 38778 | } |
| 38779 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38780 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38781 | _opnd_array[operand_index] = operand; |
| 38782 | } |
| 38783 | private: |
| 38784 | virtual const RegMask &out_RegMask() const; |
| 38785 | virtual uint rule() const { return vsub16B_mem_rule; } |
| 38786 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38787 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38788 | virtual int reloc() const; |
| 38789 | virtual uint oper_input_base() const { return 2; } |
| 38790 | public: |
| 38791 | vsub16B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38792 | virtual uint size_of() const { return sizeof(vsub16B_memNode); } |
| 38793 | static const Pipeline *pipeline_class(); |
| 38794 | virtual const Pipeline *pipeline() const; |
| 38795 | virtual const MachOper *memory_operand() const; |
| 38796 | #ifndef PRODUCT |
| 38797 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38798 | virtual const char *Name() const { return "vsub16B_mem";} |
| 38799 | #endif |
| 38800 | }; |
| 38801 | |
| 38802 | class vsub32B_regNode : public MachTypeNode { |
| 38803 | private: |
| 38804 | MachOper *_opnd_array[3]; |
| 38805 | public: |
| 38806 | MachOper *opnd_array(uint operand_index) const { |
| 38807 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38808 | return _opnd_array[operand_index]; |
| 38809 | } |
| 38810 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38811 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38812 | _opnd_array[operand_index] = operand; |
| 38813 | } |
| 38814 | private: |
| 38815 | virtual const RegMask &out_RegMask() const; |
| 38816 | virtual uint rule() const { return vsub32B_reg_rule; } |
| 38817 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38818 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38819 | virtual uint oper_input_base() const { return 1; } |
| 38820 | public: |
| 38821 | vsub32B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38822 | virtual uint size_of() const { return sizeof(vsub32B_regNode); } |
| 38823 | static const Pipeline *pipeline_class(); |
| 38824 | virtual const Pipeline *pipeline() const; |
| 38825 | #ifndef PRODUCT |
| 38826 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38827 | virtual const char *Name() const { return "vsub32B_reg";} |
| 38828 | #endif |
| 38829 | }; |
| 38830 | |
| 38831 | class vsub32B_memNode : public MachTypeNode { |
| 38832 | private: |
| 38833 | MachOper *_opnd_array[3]; |
| 38834 | public: |
| 38835 | MachOper *opnd_array(uint operand_index) const { |
| 38836 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38837 | return _opnd_array[operand_index]; |
| 38838 | } |
| 38839 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38840 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38841 | _opnd_array[operand_index] = operand; |
| 38842 | } |
| 38843 | private: |
| 38844 | virtual const RegMask &out_RegMask() const; |
| 38845 | virtual uint rule() const { return vsub32B_mem_rule; } |
| 38846 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38847 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38848 | virtual int reloc() const; |
| 38849 | virtual uint oper_input_base() const { return 2; } |
| 38850 | public: |
| 38851 | vsub32B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38852 | virtual uint size_of() const { return sizeof(vsub32B_memNode); } |
| 38853 | static const Pipeline *pipeline_class(); |
| 38854 | virtual const Pipeline *pipeline() const; |
| 38855 | virtual const MachOper *memory_operand() const; |
| 38856 | #ifndef PRODUCT |
| 38857 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38858 | virtual const char *Name() const { return "vsub32B_mem";} |
| 38859 | #endif |
| 38860 | }; |
| 38861 | |
| 38862 | class vsub64B_regNode : public MachTypeNode { |
| 38863 | private: |
| 38864 | MachOper *_opnd_array[3]; |
| 38865 | public: |
| 38866 | MachOper *opnd_array(uint operand_index) const { |
| 38867 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38868 | return _opnd_array[operand_index]; |
| 38869 | } |
| 38870 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38871 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38872 | _opnd_array[operand_index] = operand; |
| 38873 | } |
| 38874 | private: |
| 38875 | virtual const RegMask &out_RegMask() const; |
| 38876 | virtual uint rule() const { return vsub64B_reg_rule; } |
| 38877 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38878 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38879 | virtual uint oper_input_base() const { return 1; } |
| 38880 | public: |
| 38881 | vsub64B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38882 | virtual uint size_of() const { return sizeof(vsub64B_regNode); } |
| 38883 | static const Pipeline *pipeline_class(); |
| 38884 | virtual const Pipeline *pipeline() const; |
| 38885 | #ifndef PRODUCT |
| 38886 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38887 | virtual const char *Name() const { return "vsub64B_reg";} |
| 38888 | #endif |
| 38889 | }; |
| 38890 | |
| 38891 | class vsub64B_memNode : public MachTypeNode { |
| 38892 | private: |
| 38893 | MachOper *_opnd_array[3]; |
| 38894 | public: |
| 38895 | MachOper *opnd_array(uint operand_index) const { |
| 38896 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38897 | return _opnd_array[operand_index]; |
| 38898 | } |
| 38899 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38900 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38901 | _opnd_array[operand_index] = operand; |
| 38902 | } |
| 38903 | private: |
| 38904 | virtual const RegMask &out_RegMask() const; |
| 38905 | virtual uint rule() const { return vsub64B_mem_rule; } |
| 38906 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38907 | virtual int ideal_Opcode() const { return Op_SubVB; } |
| 38908 | virtual int reloc() const; |
| 38909 | virtual uint oper_input_base() const { return 2; } |
| 38910 | public: |
| 38911 | vsub64B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 38912 | virtual uint size_of() const { return sizeof(vsub64B_memNode); } |
| 38913 | static const Pipeline *pipeline_class(); |
| 38914 | virtual const Pipeline *pipeline() const; |
| 38915 | virtual const MachOper *memory_operand() const; |
| 38916 | #ifndef PRODUCT |
| 38917 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38918 | virtual const char *Name() const { return "vsub64B_mem";} |
| 38919 | #endif |
| 38920 | }; |
| 38921 | |
| 38922 | class vsub2SNode : public MachTypeNode { |
| 38923 | private: |
| 38924 | MachOper *_opnd_array[3]; |
| 38925 | public: |
| 38926 | MachOper *opnd_array(uint operand_index) const { |
| 38927 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38928 | return _opnd_array[operand_index]; |
| 38929 | } |
| 38930 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38931 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38932 | _opnd_array[operand_index] = operand; |
| 38933 | } |
| 38934 | private: |
| 38935 | virtual const RegMask &out_RegMask() const; |
| 38936 | virtual uint rule() const { return vsub2S_rule; } |
| 38937 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38938 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 38939 | virtual uint two_adr() const { return oper_input_base(); } |
| 38940 | virtual uint oper_input_base() const { return 1; } |
| 38941 | public: |
| 38942 | vsub2SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38943 | virtual uint size_of() const { return sizeof(vsub2SNode); } |
| 38944 | static const Pipeline *pipeline_class(); |
| 38945 | virtual const Pipeline *pipeline() const; |
| 38946 | #ifndef PRODUCT |
| 38947 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38948 | virtual const char *Name() const { return "vsub2S";} |
| 38949 | #endif |
| 38950 | }; |
| 38951 | |
| 38952 | class vsub2S_regNode : public MachTypeNode { |
| 38953 | private: |
| 38954 | MachOper *_opnd_array[3]; |
| 38955 | public: |
| 38956 | MachOper *opnd_array(uint operand_index) const { |
| 38957 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38958 | return _opnd_array[operand_index]; |
| 38959 | } |
| 38960 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38961 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38962 | _opnd_array[operand_index] = operand; |
| 38963 | } |
| 38964 | private: |
| 38965 | virtual const RegMask &out_RegMask() const; |
| 38966 | virtual uint rule() const { return vsub2S_reg_rule; } |
| 38967 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38968 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 38969 | virtual uint oper_input_base() const { return 1; } |
| 38970 | public: |
| 38971 | vsub2S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 38972 | virtual uint size_of() const { return sizeof(vsub2S_regNode); } |
| 38973 | static const Pipeline *pipeline_class(); |
| 38974 | virtual const Pipeline *pipeline() const; |
| 38975 | #ifndef PRODUCT |
| 38976 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 38977 | virtual const char *Name() const { return "vsub2S_reg";} |
| 38978 | #endif |
| 38979 | }; |
| 38980 | |
| 38981 | class vsub2S_memNode : public MachTypeNode { |
| 38982 | private: |
| 38983 | MachOper *_opnd_array[3]; |
| 38984 | public: |
| 38985 | MachOper *opnd_array(uint operand_index) const { |
| 38986 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38987 | return _opnd_array[operand_index]; |
| 38988 | } |
| 38989 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 38990 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 38991 | _opnd_array[operand_index] = operand; |
| 38992 | } |
| 38993 | private: |
| 38994 | virtual const RegMask &out_RegMask() const; |
| 38995 | virtual uint rule() const { return vsub2S_mem_rule; } |
| 38996 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 38997 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 38998 | virtual int reloc() const; |
| 38999 | virtual uint oper_input_base() const { return 2; } |
| 39000 | public: |
| 39001 | vsub2S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39002 | virtual uint size_of() const { return sizeof(vsub2S_memNode); } |
| 39003 | static const Pipeline *pipeline_class(); |
| 39004 | virtual const Pipeline *pipeline() const; |
| 39005 | virtual const MachOper *memory_operand() const; |
| 39006 | #ifndef PRODUCT |
| 39007 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39008 | virtual const char *Name() const { return "vsub2S_mem";} |
| 39009 | #endif |
| 39010 | }; |
| 39011 | |
| 39012 | class vsub4SNode : public MachTypeNode { |
| 39013 | private: |
| 39014 | MachOper *_opnd_array[3]; |
| 39015 | public: |
| 39016 | MachOper *opnd_array(uint operand_index) const { |
| 39017 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39018 | return _opnd_array[operand_index]; |
| 39019 | } |
| 39020 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39021 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39022 | _opnd_array[operand_index] = operand; |
| 39023 | } |
| 39024 | private: |
| 39025 | virtual const RegMask &out_RegMask() const; |
| 39026 | virtual uint rule() const { return vsub4S_rule; } |
| 39027 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39028 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39029 | virtual uint two_adr() const { return oper_input_base(); } |
| 39030 | virtual uint oper_input_base() const { return 1; } |
| 39031 | public: |
| 39032 | vsub4SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39033 | virtual uint size_of() const { return sizeof(vsub4SNode); } |
| 39034 | static const Pipeline *pipeline_class(); |
| 39035 | virtual const Pipeline *pipeline() const; |
| 39036 | #ifndef PRODUCT |
| 39037 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39038 | virtual const char *Name() const { return "vsub4S";} |
| 39039 | #endif |
| 39040 | }; |
| 39041 | |
| 39042 | class vsub4S_regNode : public MachTypeNode { |
| 39043 | private: |
| 39044 | MachOper *_opnd_array[3]; |
| 39045 | public: |
| 39046 | MachOper *opnd_array(uint operand_index) const { |
| 39047 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39048 | return _opnd_array[operand_index]; |
| 39049 | } |
| 39050 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39051 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39052 | _opnd_array[operand_index] = operand; |
| 39053 | } |
| 39054 | private: |
| 39055 | virtual const RegMask &out_RegMask() const; |
| 39056 | virtual uint rule() const { return vsub4S_reg_rule; } |
| 39057 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39058 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39059 | virtual uint oper_input_base() const { return 1; } |
| 39060 | public: |
| 39061 | vsub4S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39062 | virtual uint size_of() const { return sizeof(vsub4S_regNode); } |
| 39063 | static const Pipeline *pipeline_class(); |
| 39064 | virtual const Pipeline *pipeline() const; |
| 39065 | #ifndef PRODUCT |
| 39066 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39067 | virtual const char *Name() const { return "vsub4S_reg";} |
| 39068 | #endif |
| 39069 | }; |
| 39070 | |
| 39071 | class vsub4S_memNode : public MachTypeNode { |
| 39072 | private: |
| 39073 | MachOper *_opnd_array[3]; |
| 39074 | public: |
| 39075 | MachOper *opnd_array(uint operand_index) const { |
| 39076 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39077 | return _opnd_array[operand_index]; |
| 39078 | } |
| 39079 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39080 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39081 | _opnd_array[operand_index] = operand; |
| 39082 | } |
| 39083 | private: |
| 39084 | virtual const RegMask &out_RegMask() const; |
| 39085 | virtual uint rule() const { return vsub4S_mem_rule; } |
| 39086 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39087 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39088 | virtual int reloc() const; |
| 39089 | virtual uint oper_input_base() const { return 2; } |
| 39090 | public: |
| 39091 | vsub4S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39092 | virtual uint size_of() const { return sizeof(vsub4S_memNode); } |
| 39093 | static const Pipeline *pipeline_class(); |
| 39094 | virtual const Pipeline *pipeline() const; |
| 39095 | virtual const MachOper *memory_operand() const; |
| 39096 | #ifndef PRODUCT |
| 39097 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39098 | virtual const char *Name() const { return "vsub4S_mem";} |
| 39099 | #endif |
| 39100 | }; |
| 39101 | |
| 39102 | class vsub8SNode : public MachTypeNode { |
| 39103 | private: |
| 39104 | MachOper *_opnd_array[3]; |
| 39105 | public: |
| 39106 | MachOper *opnd_array(uint operand_index) const { |
| 39107 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39108 | return _opnd_array[operand_index]; |
| 39109 | } |
| 39110 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39111 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39112 | _opnd_array[operand_index] = operand; |
| 39113 | } |
| 39114 | private: |
| 39115 | virtual const RegMask &out_RegMask() const; |
| 39116 | virtual uint rule() const { return vsub8S_rule; } |
| 39117 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39118 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39119 | virtual uint two_adr() const { return oper_input_base(); } |
| 39120 | virtual uint oper_input_base() const { return 1; } |
| 39121 | public: |
| 39122 | vsub8SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39123 | virtual uint size_of() const { return sizeof(vsub8SNode); } |
| 39124 | static const Pipeline *pipeline_class(); |
| 39125 | virtual const Pipeline *pipeline() const; |
| 39126 | #ifndef PRODUCT |
| 39127 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39128 | virtual const char *Name() const { return "vsub8S";} |
| 39129 | #endif |
| 39130 | }; |
| 39131 | |
| 39132 | class vsub8S_regNode : public MachTypeNode { |
| 39133 | private: |
| 39134 | MachOper *_opnd_array[3]; |
| 39135 | public: |
| 39136 | MachOper *opnd_array(uint operand_index) const { |
| 39137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39138 | return _opnd_array[operand_index]; |
| 39139 | } |
| 39140 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39141 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39142 | _opnd_array[operand_index] = operand; |
| 39143 | } |
| 39144 | private: |
| 39145 | virtual const RegMask &out_RegMask() const; |
| 39146 | virtual uint rule() const { return vsub8S_reg_rule; } |
| 39147 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39148 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39149 | virtual uint oper_input_base() const { return 1; } |
| 39150 | public: |
| 39151 | vsub8S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39152 | virtual uint size_of() const { return sizeof(vsub8S_regNode); } |
| 39153 | static const Pipeline *pipeline_class(); |
| 39154 | virtual const Pipeline *pipeline() const; |
| 39155 | #ifndef PRODUCT |
| 39156 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39157 | virtual const char *Name() const { return "vsub8S_reg";} |
| 39158 | #endif |
| 39159 | }; |
| 39160 | |
| 39161 | class vsub8S_memNode : public MachTypeNode { |
| 39162 | private: |
| 39163 | MachOper *_opnd_array[3]; |
| 39164 | public: |
| 39165 | MachOper *opnd_array(uint operand_index) const { |
| 39166 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39167 | return _opnd_array[operand_index]; |
| 39168 | } |
| 39169 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39170 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39171 | _opnd_array[operand_index] = operand; |
| 39172 | } |
| 39173 | private: |
| 39174 | virtual const RegMask &out_RegMask() const; |
| 39175 | virtual uint rule() const { return vsub8S_mem_rule; } |
| 39176 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39177 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39178 | virtual int reloc() const; |
| 39179 | virtual uint oper_input_base() const { return 2; } |
| 39180 | public: |
| 39181 | vsub8S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39182 | virtual uint size_of() const { return sizeof(vsub8S_memNode); } |
| 39183 | static const Pipeline *pipeline_class(); |
| 39184 | virtual const Pipeline *pipeline() const; |
| 39185 | virtual const MachOper *memory_operand() const; |
| 39186 | #ifndef PRODUCT |
| 39187 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39188 | virtual const char *Name() const { return "vsub8S_mem";} |
| 39189 | #endif |
| 39190 | }; |
| 39191 | |
| 39192 | class vsub16S_regNode : public MachTypeNode { |
| 39193 | private: |
| 39194 | MachOper *_opnd_array[3]; |
| 39195 | public: |
| 39196 | MachOper *opnd_array(uint operand_index) const { |
| 39197 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39198 | return _opnd_array[operand_index]; |
| 39199 | } |
| 39200 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39201 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39202 | _opnd_array[operand_index] = operand; |
| 39203 | } |
| 39204 | private: |
| 39205 | virtual const RegMask &out_RegMask() const; |
| 39206 | virtual uint rule() const { return vsub16S_reg_rule; } |
| 39207 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39208 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39209 | virtual uint oper_input_base() const { return 1; } |
| 39210 | public: |
| 39211 | vsub16S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39212 | virtual uint size_of() const { return sizeof(vsub16S_regNode); } |
| 39213 | static const Pipeline *pipeline_class(); |
| 39214 | virtual const Pipeline *pipeline() const; |
| 39215 | #ifndef PRODUCT |
| 39216 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39217 | virtual const char *Name() const { return "vsub16S_reg";} |
| 39218 | #endif |
| 39219 | }; |
| 39220 | |
| 39221 | class vsub16S_memNode : public MachTypeNode { |
| 39222 | private: |
| 39223 | MachOper *_opnd_array[3]; |
| 39224 | public: |
| 39225 | MachOper *opnd_array(uint operand_index) const { |
| 39226 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39227 | return _opnd_array[operand_index]; |
| 39228 | } |
| 39229 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39231 | _opnd_array[operand_index] = operand; |
| 39232 | } |
| 39233 | private: |
| 39234 | virtual const RegMask &out_RegMask() const; |
| 39235 | virtual uint rule() const { return vsub16S_mem_rule; } |
| 39236 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39237 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39238 | virtual int reloc() const; |
| 39239 | virtual uint oper_input_base() const { return 2; } |
| 39240 | public: |
| 39241 | vsub16S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39242 | virtual uint size_of() const { return sizeof(vsub16S_memNode); } |
| 39243 | static const Pipeline *pipeline_class(); |
| 39244 | virtual const Pipeline *pipeline() const; |
| 39245 | virtual const MachOper *memory_operand() const; |
| 39246 | #ifndef PRODUCT |
| 39247 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39248 | virtual const char *Name() const { return "vsub16S_mem";} |
| 39249 | #endif |
| 39250 | }; |
| 39251 | |
| 39252 | class vsub32S_regNode : public MachTypeNode { |
| 39253 | private: |
| 39254 | MachOper *_opnd_array[3]; |
| 39255 | public: |
| 39256 | MachOper *opnd_array(uint operand_index) const { |
| 39257 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39258 | return _opnd_array[operand_index]; |
| 39259 | } |
| 39260 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39261 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39262 | _opnd_array[operand_index] = operand; |
| 39263 | } |
| 39264 | private: |
| 39265 | virtual const RegMask &out_RegMask() const; |
| 39266 | virtual uint rule() const { return vsub32S_reg_rule; } |
| 39267 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39268 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39269 | virtual uint oper_input_base() const { return 1; } |
| 39270 | public: |
| 39271 | vsub32S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39272 | virtual uint size_of() const { return sizeof(vsub32S_regNode); } |
| 39273 | static const Pipeline *pipeline_class(); |
| 39274 | virtual const Pipeline *pipeline() const; |
| 39275 | #ifndef PRODUCT |
| 39276 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39277 | virtual const char *Name() const { return "vsub32S_reg";} |
| 39278 | #endif |
| 39279 | }; |
| 39280 | |
| 39281 | class vsub32S_memNode : public MachTypeNode { |
| 39282 | private: |
| 39283 | MachOper *_opnd_array[3]; |
| 39284 | public: |
| 39285 | MachOper *opnd_array(uint operand_index) const { |
| 39286 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39287 | return _opnd_array[operand_index]; |
| 39288 | } |
| 39289 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39290 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39291 | _opnd_array[operand_index] = operand; |
| 39292 | } |
| 39293 | private: |
| 39294 | virtual const RegMask &out_RegMask() const; |
| 39295 | virtual uint rule() const { return vsub32S_mem_rule; } |
| 39296 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39297 | virtual int ideal_Opcode() const { return Op_SubVS; } |
| 39298 | virtual int reloc() const; |
| 39299 | virtual uint oper_input_base() const { return 2; } |
| 39300 | public: |
| 39301 | vsub32S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39302 | virtual uint size_of() const { return sizeof(vsub32S_memNode); } |
| 39303 | static const Pipeline *pipeline_class(); |
| 39304 | virtual const Pipeline *pipeline() const; |
| 39305 | virtual const MachOper *memory_operand() const; |
| 39306 | #ifndef PRODUCT |
| 39307 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39308 | virtual const char *Name() const { return "vsub32S_mem";} |
| 39309 | #endif |
| 39310 | }; |
| 39311 | |
| 39312 | class vsub2INode : public MachTypeNode { |
| 39313 | private: |
| 39314 | MachOper *_opnd_array[3]; |
| 39315 | public: |
| 39316 | MachOper *opnd_array(uint operand_index) const { |
| 39317 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39318 | return _opnd_array[operand_index]; |
| 39319 | } |
| 39320 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39321 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39322 | _opnd_array[operand_index] = operand; |
| 39323 | } |
| 39324 | private: |
| 39325 | virtual const RegMask &out_RegMask() const; |
| 39326 | virtual uint rule() const { return vsub2I_rule; } |
| 39327 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39328 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39329 | virtual uint two_adr() const { return oper_input_base(); } |
| 39330 | virtual uint oper_input_base() const { return 1; } |
| 39331 | public: |
| 39332 | vsub2INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39333 | virtual uint size_of() const { return sizeof(vsub2INode); } |
| 39334 | static const Pipeline *pipeline_class(); |
| 39335 | virtual const Pipeline *pipeline() const; |
| 39336 | #ifndef PRODUCT |
| 39337 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39338 | virtual const char *Name() const { return "vsub2I";} |
| 39339 | #endif |
| 39340 | }; |
| 39341 | |
| 39342 | class vsub2I_regNode : public MachTypeNode { |
| 39343 | private: |
| 39344 | MachOper *_opnd_array[3]; |
| 39345 | public: |
| 39346 | MachOper *opnd_array(uint operand_index) const { |
| 39347 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39348 | return _opnd_array[operand_index]; |
| 39349 | } |
| 39350 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39351 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39352 | _opnd_array[operand_index] = operand; |
| 39353 | } |
| 39354 | private: |
| 39355 | virtual const RegMask &out_RegMask() const; |
| 39356 | virtual uint rule() const { return vsub2I_reg_rule; } |
| 39357 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39358 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39359 | virtual uint oper_input_base() const { return 1; } |
| 39360 | public: |
| 39361 | vsub2I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39362 | virtual uint size_of() const { return sizeof(vsub2I_regNode); } |
| 39363 | static const Pipeline *pipeline_class(); |
| 39364 | virtual const Pipeline *pipeline() const; |
| 39365 | #ifndef PRODUCT |
| 39366 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39367 | virtual const char *Name() const { return "vsub2I_reg";} |
| 39368 | #endif |
| 39369 | }; |
| 39370 | |
| 39371 | class vsub2I_memNode : public MachTypeNode { |
| 39372 | private: |
| 39373 | MachOper *_opnd_array[3]; |
| 39374 | public: |
| 39375 | MachOper *opnd_array(uint operand_index) const { |
| 39376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39377 | return _opnd_array[operand_index]; |
| 39378 | } |
| 39379 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39380 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39381 | _opnd_array[operand_index] = operand; |
| 39382 | } |
| 39383 | private: |
| 39384 | virtual const RegMask &out_RegMask() const; |
| 39385 | virtual uint rule() const { return vsub2I_mem_rule; } |
| 39386 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39387 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39388 | virtual int reloc() const; |
| 39389 | virtual uint oper_input_base() const { return 2; } |
| 39390 | public: |
| 39391 | vsub2I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39392 | virtual uint size_of() const { return sizeof(vsub2I_memNode); } |
| 39393 | static const Pipeline *pipeline_class(); |
| 39394 | virtual const Pipeline *pipeline() const; |
| 39395 | virtual const MachOper *memory_operand() const; |
| 39396 | #ifndef PRODUCT |
| 39397 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39398 | virtual const char *Name() const { return "vsub2I_mem";} |
| 39399 | #endif |
| 39400 | }; |
| 39401 | |
| 39402 | class vsub4INode : public MachTypeNode { |
| 39403 | private: |
| 39404 | MachOper *_opnd_array[3]; |
| 39405 | public: |
| 39406 | MachOper *opnd_array(uint operand_index) const { |
| 39407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39408 | return _opnd_array[operand_index]; |
| 39409 | } |
| 39410 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39412 | _opnd_array[operand_index] = operand; |
| 39413 | } |
| 39414 | private: |
| 39415 | virtual const RegMask &out_RegMask() const; |
| 39416 | virtual uint rule() const { return vsub4I_rule; } |
| 39417 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39418 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39419 | virtual uint two_adr() const { return oper_input_base(); } |
| 39420 | virtual uint oper_input_base() const { return 1; } |
| 39421 | public: |
| 39422 | vsub4INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39423 | virtual uint size_of() const { return sizeof(vsub4INode); } |
| 39424 | static const Pipeline *pipeline_class(); |
| 39425 | virtual const Pipeline *pipeline() const; |
| 39426 | #ifndef PRODUCT |
| 39427 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39428 | virtual const char *Name() const { return "vsub4I";} |
| 39429 | #endif |
| 39430 | }; |
| 39431 | |
| 39432 | class vsub4I_regNode : public MachTypeNode { |
| 39433 | private: |
| 39434 | MachOper *_opnd_array[3]; |
| 39435 | public: |
| 39436 | MachOper *opnd_array(uint operand_index) const { |
| 39437 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39438 | return _opnd_array[operand_index]; |
| 39439 | } |
| 39440 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39441 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39442 | _opnd_array[operand_index] = operand; |
| 39443 | } |
| 39444 | private: |
| 39445 | virtual const RegMask &out_RegMask() const; |
| 39446 | virtual uint rule() const { return vsub4I_reg_rule; } |
| 39447 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39448 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39449 | virtual uint oper_input_base() const { return 1; } |
| 39450 | public: |
| 39451 | vsub4I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39452 | virtual uint size_of() const { return sizeof(vsub4I_regNode); } |
| 39453 | static const Pipeline *pipeline_class(); |
| 39454 | virtual const Pipeline *pipeline() const; |
| 39455 | #ifndef PRODUCT |
| 39456 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39457 | virtual const char *Name() const { return "vsub4I_reg";} |
| 39458 | #endif |
| 39459 | }; |
| 39460 | |
| 39461 | class vsub4I_memNode : public MachTypeNode { |
| 39462 | private: |
| 39463 | MachOper *_opnd_array[3]; |
| 39464 | public: |
| 39465 | MachOper *opnd_array(uint operand_index) const { |
| 39466 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39467 | return _opnd_array[operand_index]; |
| 39468 | } |
| 39469 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39470 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39471 | _opnd_array[operand_index] = operand; |
| 39472 | } |
| 39473 | private: |
| 39474 | virtual const RegMask &out_RegMask() const; |
| 39475 | virtual uint rule() const { return vsub4I_mem_rule; } |
| 39476 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39477 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39478 | virtual int reloc() const; |
| 39479 | virtual uint oper_input_base() const { return 2; } |
| 39480 | public: |
| 39481 | vsub4I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39482 | virtual uint size_of() const { return sizeof(vsub4I_memNode); } |
| 39483 | static const Pipeline *pipeline_class(); |
| 39484 | virtual const Pipeline *pipeline() const; |
| 39485 | virtual const MachOper *memory_operand() const; |
| 39486 | #ifndef PRODUCT |
| 39487 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39488 | virtual const char *Name() const { return "vsub4I_mem";} |
| 39489 | #endif |
| 39490 | }; |
| 39491 | |
| 39492 | class vsub8I_regNode : public MachTypeNode { |
| 39493 | private: |
| 39494 | MachOper *_opnd_array[3]; |
| 39495 | public: |
| 39496 | MachOper *opnd_array(uint operand_index) const { |
| 39497 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39498 | return _opnd_array[operand_index]; |
| 39499 | } |
| 39500 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39501 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39502 | _opnd_array[operand_index] = operand; |
| 39503 | } |
| 39504 | private: |
| 39505 | virtual const RegMask &out_RegMask() const; |
| 39506 | virtual uint rule() const { return vsub8I_reg_rule; } |
| 39507 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39508 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39509 | virtual uint oper_input_base() const { return 1; } |
| 39510 | public: |
| 39511 | vsub8I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39512 | virtual uint size_of() const { return sizeof(vsub8I_regNode); } |
| 39513 | static const Pipeline *pipeline_class(); |
| 39514 | virtual const Pipeline *pipeline() const; |
| 39515 | #ifndef PRODUCT |
| 39516 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39517 | virtual const char *Name() const { return "vsub8I_reg";} |
| 39518 | #endif |
| 39519 | }; |
| 39520 | |
| 39521 | class vsub8I_memNode : public MachTypeNode { |
| 39522 | private: |
| 39523 | MachOper *_opnd_array[3]; |
| 39524 | public: |
| 39525 | MachOper *opnd_array(uint operand_index) const { |
| 39526 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39527 | return _opnd_array[operand_index]; |
| 39528 | } |
| 39529 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39530 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39531 | _opnd_array[operand_index] = operand; |
| 39532 | } |
| 39533 | private: |
| 39534 | virtual const RegMask &out_RegMask() const; |
| 39535 | virtual uint rule() const { return vsub8I_mem_rule; } |
| 39536 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39537 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39538 | virtual int reloc() const; |
| 39539 | virtual uint oper_input_base() const { return 2; } |
| 39540 | public: |
| 39541 | vsub8I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39542 | virtual uint size_of() const { return sizeof(vsub8I_memNode); } |
| 39543 | static const Pipeline *pipeline_class(); |
| 39544 | virtual const Pipeline *pipeline() const; |
| 39545 | virtual const MachOper *memory_operand() const; |
| 39546 | #ifndef PRODUCT |
| 39547 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39548 | virtual const char *Name() const { return "vsub8I_mem";} |
| 39549 | #endif |
| 39550 | }; |
| 39551 | |
| 39552 | class vsub16I_regNode : public MachTypeNode { |
| 39553 | private: |
| 39554 | MachOper *_opnd_array[3]; |
| 39555 | public: |
| 39556 | MachOper *opnd_array(uint operand_index) const { |
| 39557 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39558 | return _opnd_array[operand_index]; |
| 39559 | } |
| 39560 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39561 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39562 | _opnd_array[operand_index] = operand; |
| 39563 | } |
| 39564 | private: |
| 39565 | virtual const RegMask &out_RegMask() const; |
| 39566 | virtual uint rule() const { return vsub16I_reg_rule; } |
| 39567 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39568 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39569 | virtual uint oper_input_base() const { return 1; } |
| 39570 | public: |
| 39571 | vsub16I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39572 | virtual uint size_of() const { return sizeof(vsub16I_regNode); } |
| 39573 | static const Pipeline *pipeline_class(); |
| 39574 | virtual const Pipeline *pipeline() const; |
| 39575 | #ifndef PRODUCT |
| 39576 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39577 | virtual const char *Name() const { return "vsub16I_reg";} |
| 39578 | #endif |
| 39579 | }; |
| 39580 | |
| 39581 | class vsub16I_memNode : public MachTypeNode { |
| 39582 | private: |
| 39583 | MachOper *_opnd_array[3]; |
| 39584 | public: |
| 39585 | MachOper *opnd_array(uint operand_index) const { |
| 39586 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39587 | return _opnd_array[operand_index]; |
| 39588 | } |
| 39589 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39590 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39591 | _opnd_array[operand_index] = operand; |
| 39592 | } |
| 39593 | private: |
| 39594 | virtual const RegMask &out_RegMask() const; |
| 39595 | virtual uint rule() const { return vsub16I_mem_rule; } |
| 39596 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39597 | virtual int ideal_Opcode() const { return Op_SubVI; } |
| 39598 | virtual int reloc() const; |
| 39599 | virtual uint oper_input_base() const { return 2; } |
| 39600 | public: |
| 39601 | vsub16I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39602 | virtual uint size_of() const { return sizeof(vsub16I_memNode); } |
| 39603 | static const Pipeline *pipeline_class(); |
| 39604 | virtual const Pipeline *pipeline() const; |
| 39605 | virtual const MachOper *memory_operand() const; |
| 39606 | #ifndef PRODUCT |
| 39607 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39608 | virtual const char *Name() const { return "vsub16I_mem";} |
| 39609 | #endif |
| 39610 | }; |
| 39611 | |
| 39612 | class vsub2LNode : public MachTypeNode { |
| 39613 | private: |
| 39614 | MachOper *_opnd_array[3]; |
| 39615 | public: |
| 39616 | MachOper *opnd_array(uint operand_index) const { |
| 39617 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39618 | return _opnd_array[operand_index]; |
| 39619 | } |
| 39620 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39621 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39622 | _opnd_array[operand_index] = operand; |
| 39623 | } |
| 39624 | private: |
| 39625 | virtual const RegMask &out_RegMask() const; |
| 39626 | virtual uint rule() const { return vsub2L_rule; } |
| 39627 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39628 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39629 | virtual uint two_adr() const { return oper_input_base(); } |
| 39630 | virtual uint oper_input_base() const { return 1; } |
| 39631 | public: |
| 39632 | vsub2LNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39633 | virtual uint size_of() const { return sizeof(vsub2LNode); } |
| 39634 | static const Pipeline *pipeline_class(); |
| 39635 | virtual const Pipeline *pipeline() const; |
| 39636 | #ifndef PRODUCT |
| 39637 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39638 | virtual const char *Name() const { return "vsub2L";} |
| 39639 | #endif |
| 39640 | }; |
| 39641 | |
| 39642 | class vsub2L_regNode : public MachTypeNode { |
| 39643 | private: |
| 39644 | MachOper *_opnd_array[3]; |
| 39645 | public: |
| 39646 | MachOper *opnd_array(uint operand_index) const { |
| 39647 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39648 | return _opnd_array[operand_index]; |
| 39649 | } |
| 39650 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39651 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39652 | _opnd_array[operand_index] = operand; |
| 39653 | } |
| 39654 | private: |
| 39655 | virtual const RegMask &out_RegMask() const; |
| 39656 | virtual uint rule() const { return vsub2L_reg_rule; } |
| 39657 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39658 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39659 | virtual uint oper_input_base() const { return 1; } |
| 39660 | public: |
| 39661 | vsub2L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39662 | virtual uint size_of() const { return sizeof(vsub2L_regNode); } |
| 39663 | static const Pipeline *pipeline_class(); |
| 39664 | virtual const Pipeline *pipeline() const; |
| 39665 | #ifndef PRODUCT |
| 39666 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39667 | virtual const char *Name() const { return "vsub2L_reg";} |
| 39668 | #endif |
| 39669 | }; |
| 39670 | |
| 39671 | class vsub2L_memNode : public MachTypeNode { |
| 39672 | private: |
| 39673 | MachOper *_opnd_array[3]; |
| 39674 | public: |
| 39675 | MachOper *opnd_array(uint operand_index) const { |
| 39676 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39677 | return _opnd_array[operand_index]; |
| 39678 | } |
| 39679 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39680 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39681 | _opnd_array[operand_index] = operand; |
| 39682 | } |
| 39683 | private: |
| 39684 | virtual const RegMask &out_RegMask() const; |
| 39685 | virtual uint rule() const { return vsub2L_mem_rule; } |
| 39686 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39687 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39688 | virtual int reloc() const; |
| 39689 | virtual uint oper_input_base() const { return 2; } |
| 39690 | public: |
| 39691 | vsub2L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39692 | virtual uint size_of() const { return sizeof(vsub2L_memNode); } |
| 39693 | static const Pipeline *pipeline_class(); |
| 39694 | virtual const Pipeline *pipeline() const; |
| 39695 | virtual const MachOper *memory_operand() const; |
| 39696 | #ifndef PRODUCT |
| 39697 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39698 | virtual const char *Name() const { return "vsub2L_mem";} |
| 39699 | #endif |
| 39700 | }; |
| 39701 | |
| 39702 | class vsub4L_regNode : public MachTypeNode { |
| 39703 | private: |
| 39704 | MachOper *_opnd_array[3]; |
| 39705 | public: |
| 39706 | MachOper *opnd_array(uint operand_index) const { |
| 39707 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39708 | return _opnd_array[operand_index]; |
| 39709 | } |
| 39710 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39711 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39712 | _opnd_array[operand_index] = operand; |
| 39713 | } |
| 39714 | private: |
| 39715 | virtual const RegMask &out_RegMask() const; |
| 39716 | virtual uint rule() const { return vsub4L_reg_rule; } |
| 39717 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39718 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39719 | virtual uint oper_input_base() const { return 1; } |
| 39720 | public: |
| 39721 | vsub4L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39722 | virtual uint size_of() const { return sizeof(vsub4L_regNode); } |
| 39723 | static const Pipeline *pipeline_class(); |
| 39724 | virtual const Pipeline *pipeline() const; |
| 39725 | #ifndef PRODUCT |
| 39726 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39727 | virtual const char *Name() const { return "vsub4L_reg";} |
| 39728 | #endif |
| 39729 | }; |
| 39730 | |
| 39731 | class vsub4L_memNode : public MachTypeNode { |
| 39732 | private: |
| 39733 | MachOper *_opnd_array[3]; |
| 39734 | public: |
| 39735 | MachOper *opnd_array(uint operand_index) const { |
| 39736 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39737 | return _opnd_array[operand_index]; |
| 39738 | } |
| 39739 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39740 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39741 | _opnd_array[operand_index] = operand; |
| 39742 | } |
| 39743 | private: |
| 39744 | virtual const RegMask &out_RegMask() const; |
| 39745 | virtual uint rule() const { return vsub4L_mem_rule; } |
| 39746 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39747 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39748 | virtual int reloc() const; |
| 39749 | virtual uint oper_input_base() const { return 2; } |
| 39750 | public: |
| 39751 | vsub4L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39752 | virtual uint size_of() const { return sizeof(vsub4L_memNode); } |
| 39753 | static const Pipeline *pipeline_class(); |
| 39754 | virtual const Pipeline *pipeline() const; |
| 39755 | virtual const MachOper *memory_operand() const; |
| 39756 | #ifndef PRODUCT |
| 39757 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39758 | virtual const char *Name() const { return "vsub4L_mem";} |
| 39759 | #endif |
| 39760 | }; |
| 39761 | |
| 39762 | class vsub8L_regNode : public MachTypeNode { |
| 39763 | private: |
| 39764 | MachOper *_opnd_array[3]; |
| 39765 | public: |
| 39766 | MachOper *opnd_array(uint operand_index) const { |
| 39767 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39768 | return _opnd_array[operand_index]; |
| 39769 | } |
| 39770 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39771 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39772 | _opnd_array[operand_index] = operand; |
| 39773 | } |
| 39774 | private: |
| 39775 | virtual const RegMask &out_RegMask() const; |
| 39776 | virtual uint rule() const { return vsub8L_reg_rule; } |
| 39777 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39778 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39779 | virtual uint oper_input_base() const { return 1; } |
| 39780 | public: |
| 39781 | vsub8L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39782 | virtual uint size_of() const { return sizeof(vsub8L_regNode); } |
| 39783 | static const Pipeline *pipeline_class(); |
| 39784 | virtual const Pipeline *pipeline() const; |
| 39785 | #ifndef PRODUCT |
| 39786 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39787 | virtual const char *Name() const { return "vsub8L_reg";} |
| 39788 | #endif |
| 39789 | }; |
| 39790 | |
| 39791 | class vsub8L_memNode : public MachTypeNode { |
| 39792 | private: |
| 39793 | MachOper *_opnd_array[3]; |
| 39794 | public: |
| 39795 | MachOper *opnd_array(uint operand_index) const { |
| 39796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39797 | return _opnd_array[operand_index]; |
| 39798 | } |
| 39799 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39800 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39801 | _opnd_array[operand_index] = operand; |
| 39802 | } |
| 39803 | private: |
| 39804 | virtual const RegMask &out_RegMask() const; |
| 39805 | virtual uint rule() const { return vsub8L_mem_rule; } |
| 39806 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39807 | virtual int ideal_Opcode() const { return Op_SubVL; } |
| 39808 | virtual int reloc() const; |
| 39809 | virtual uint oper_input_base() const { return 2; } |
| 39810 | public: |
| 39811 | vsub8L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39812 | virtual uint size_of() const { return sizeof(vsub8L_memNode); } |
| 39813 | static const Pipeline *pipeline_class(); |
| 39814 | virtual const Pipeline *pipeline() const; |
| 39815 | virtual const MachOper *memory_operand() const; |
| 39816 | #ifndef PRODUCT |
| 39817 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39818 | virtual const char *Name() const { return "vsub8L_mem";} |
| 39819 | #endif |
| 39820 | }; |
| 39821 | |
| 39822 | class vsub2FNode : public MachTypeNode { |
| 39823 | private: |
| 39824 | MachOper *_opnd_array[3]; |
| 39825 | public: |
| 39826 | MachOper *opnd_array(uint operand_index) const { |
| 39827 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39828 | return _opnd_array[operand_index]; |
| 39829 | } |
| 39830 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39831 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39832 | _opnd_array[operand_index] = operand; |
| 39833 | } |
| 39834 | private: |
| 39835 | virtual const RegMask &out_RegMask() const; |
| 39836 | virtual uint rule() const { return vsub2F_rule; } |
| 39837 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39838 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39839 | virtual uint two_adr() const { return oper_input_base(); } |
| 39840 | virtual uint oper_input_base() const { return 1; } |
| 39841 | public: |
| 39842 | vsub2FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39843 | virtual uint size_of() const { return sizeof(vsub2FNode); } |
| 39844 | static const Pipeline *pipeline_class(); |
| 39845 | virtual const Pipeline *pipeline() const; |
| 39846 | #ifndef PRODUCT |
| 39847 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39848 | virtual const char *Name() const { return "vsub2F";} |
| 39849 | #endif |
| 39850 | }; |
| 39851 | |
| 39852 | class vsub2F_regNode : public MachTypeNode { |
| 39853 | private: |
| 39854 | MachOper *_opnd_array[3]; |
| 39855 | public: |
| 39856 | MachOper *opnd_array(uint operand_index) const { |
| 39857 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39858 | return _opnd_array[operand_index]; |
| 39859 | } |
| 39860 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39862 | _opnd_array[operand_index] = operand; |
| 39863 | } |
| 39864 | private: |
| 39865 | virtual const RegMask &out_RegMask() const; |
| 39866 | virtual uint rule() const { return vsub2F_reg_rule; } |
| 39867 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39868 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39869 | virtual uint oper_input_base() const { return 1; } |
| 39870 | public: |
| 39871 | vsub2F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39872 | virtual uint size_of() const { return sizeof(vsub2F_regNode); } |
| 39873 | static const Pipeline *pipeline_class(); |
| 39874 | virtual const Pipeline *pipeline() const; |
| 39875 | #ifndef PRODUCT |
| 39876 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39877 | virtual const char *Name() const { return "vsub2F_reg";} |
| 39878 | #endif |
| 39879 | }; |
| 39880 | |
| 39881 | class vsub2F_memNode : public MachTypeNode { |
| 39882 | private: |
| 39883 | MachOper *_opnd_array[3]; |
| 39884 | public: |
| 39885 | MachOper *opnd_array(uint operand_index) const { |
| 39886 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39887 | return _opnd_array[operand_index]; |
| 39888 | } |
| 39889 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39890 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39891 | _opnd_array[operand_index] = operand; |
| 39892 | } |
| 39893 | private: |
| 39894 | virtual const RegMask &out_RegMask() const; |
| 39895 | virtual uint rule() const { return vsub2F_mem_rule; } |
| 39896 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39897 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39898 | virtual int reloc() const; |
| 39899 | virtual uint oper_input_base() const { return 2; } |
| 39900 | public: |
| 39901 | vsub2F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39902 | virtual uint size_of() const { return sizeof(vsub2F_memNode); } |
| 39903 | static const Pipeline *pipeline_class(); |
| 39904 | virtual const Pipeline *pipeline() const; |
| 39905 | virtual const MachOper *memory_operand() const; |
| 39906 | #ifndef PRODUCT |
| 39907 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39908 | virtual const char *Name() const { return "vsub2F_mem";} |
| 39909 | #endif |
| 39910 | }; |
| 39911 | |
| 39912 | class vsub4FNode : public MachTypeNode { |
| 39913 | private: |
| 39914 | MachOper *_opnd_array[3]; |
| 39915 | public: |
| 39916 | MachOper *opnd_array(uint operand_index) const { |
| 39917 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39918 | return _opnd_array[operand_index]; |
| 39919 | } |
| 39920 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39921 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39922 | _opnd_array[operand_index] = operand; |
| 39923 | } |
| 39924 | private: |
| 39925 | virtual const RegMask &out_RegMask() const; |
| 39926 | virtual uint rule() const { return vsub4F_rule; } |
| 39927 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39928 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39929 | virtual uint two_adr() const { return oper_input_base(); } |
| 39930 | virtual uint oper_input_base() const { return 1; } |
| 39931 | public: |
| 39932 | vsub4FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39933 | virtual uint size_of() const { return sizeof(vsub4FNode); } |
| 39934 | static const Pipeline *pipeline_class(); |
| 39935 | virtual const Pipeline *pipeline() const; |
| 39936 | #ifndef PRODUCT |
| 39937 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39938 | virtual const char *Name() const { return "vsub4F";} |
| 39939 | #endif |
| 39940 | }; |
| 39941 | |
| 39942 | class vsub4F_regNode : public MachTypeNode { |
| 39943 | private: |
| 39944 | MachOper *_opnd_array[3]; |
| 39945 | public: |
| 39946 | MachOper *opnd_array(uint operand_index) const { |
| 39947 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39948 | return _opnd_array[operand_index]; |
| 39949 | } |
| 39950 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39951 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39952 | _opnd_array[operand_index] = operand; |
| 39953 | } |
| 39954 | private: |
| 39955 | virtual const RegMask &out_RegMask() const; |
| 39956 | virtual uint rule() const { return vsub4F_reg_rule; } |
| 39957 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39958 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39959 | virtual uint oper_input_base() const { return 1; } |
| 39960 | public: |
| 39961 | vsub4F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 39962 | virtual uint size_of() const { return sizeof(vsub4F_regNode); } |
| 39963 | static const Pipeline *pipeline_class(); |
| 39964 | virtual const Pipeline *pipeline() const; |
| 39965 | #ifndef PRODUCT |
| 39966 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39967 | virtual const char *Name() const { return "vsub4F_reg";} |
| 39968 | #endif |
| 39969 | }; |
| 39970 | |
| 39971 | class vsub4F_memNode : public MachTypeNode { |
| 39972 | private: |
| 39973 | MachOper *_opnd_array[3]; |
| 39974 | public: |
| 39975 | MachOper *opnd_array(uint operand_index) const { |
| 39976 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39977 | return _opnd_array[operand_index]; |
| 39978 | } |
| 39979 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 39980 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 39981 | _opnd_array[operand_index] = operand; |
| 39982 | } |
| 39983 | private: |
| 39984 | virtual const RegMask &out_RegMask() const; |
| 39985 | virtual uint rule() const { return vsub4F_mem_rule; } |
| 39986 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 39987 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 39988 | virtual int reloc() const; |
| 39989 | virtual uint oper_input_base() const { return 2; } |
| 39990 | public: |
| 39991 | vsub4F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 39992 | virtual uint size_of() const { return sizeof(vsub4F_memNode); } |
| 39993 | static const Pipeline *pipeline_class(); |
| 39994 | virtual const Pipeline *pipeline() const; |
| 39995 | virtual const MachOper *memory_operand() const; |
| 39996 | #ifndef PRODUCT |
| 39997 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 39998 | virtual const char *Name() const { return "vsub4F_mem";} |
| 39999 | #endif |
| 40000 | }; |
| 40001 | |
| 40002 | class vsub8F_regNode : public MachTypeNode { |
| 40003 | private: |
| 40004 | MachOper *_opnd_array[3]; |
| 40005 | public: |
| 40006 | MachOper *opnd_array(uint operand_index) const { |
| 40007 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40008 | return _opnd_array[operand_index]; |
| 40009 | } |
| 40010 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40011 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40012 | _opnd_array[operand_index] = operand; |
| 40013 | } |
| 40014 | private: |
| 40015 | virtual const RegMask &out_RegMask() const; |
| 40016 | virtual uint rule() const { return vsub8F_reg_rule; } |
| 40017 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40018 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 40019 | virtual uint oper_input_base() const { return 1; } |
| 40020 | public: |
| 40021 | vsub8F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40022 | virtual uint size_of() const { return sizeof(vsub8F_regNode); } |
| 40023 | static const Pipeline *pipeline_class(); |
| 40024 | virtual const Pipeline *pipeline() const; |
| 40025 | #ifndef PRODUCT |
| 40026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40027 | virtual const char *Name() const { return "vsub8F_reg";} |
| 40028 | #endif |
| 40029 | }; |
| 40030 | |
| 40031 | class vsub8F_memNode : public MachTypeNode { |
| 40032 | private: |
| 40033 | MachOper *_opnd_array[3]; |
| 40034 | public: |
| 40035 | MachOper *opnd_array(uint operand_index) const { |
| 40036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40037 | return _opnd_array[operand_index]; |
| 40038 | } |
| 40039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40041 | _opnd_array[operand_index] = operand; |
| 40042 | } |
| 40043 | private: |
| 40044 | virtual const RegMask &out_RegMask() const; |
| 40045 | virtual uint rule() const { return vsub8F_mem_rule; } |
| 40046 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40047 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 40048 | virtual int reloc() const; |
| 40049 | virtual uint oper_input_base() const { return 2; } |
| 40050 | public: |
| 40051 | vsub8F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40052 | virtual uint size_of() const { return sizeof(vsub8F_memNode); } |
| 40053 | static const Pipeline *pipeline_class(); |
| 40054 | virtual const Pipeline *pipeline() const; |
| 40055 | virtual const MachOper *memory_operand() const; |
| 40056 | #ifndef PRODUCT |
| 40057 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40058 | virtual const char *Name() const { return "vsub8F_mem";} |
| 40059 | #endif |
| 40060 | }; |
| 40061 | |
| 40062 | class vsub16F_regNode : public MachTypeNode { |
| 40063 | private: |
| 40064 | MachOper *_opnd_array[3]; |
| 40065 | public: |
| 40066 | MachOper *opnd_array(uint operand_index) const { |
| 40067 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40068 | return _opnd_array[operand_index]; |
| 40069 | } |
| 40070 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40071 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40072 | _opnd_array[operand_index] = operand; |
| 40073 | } |
| 40074 | private: |
| 40075 | virtual const RegMask &out_RegMask() const; |
| 40076 | virtual uint rule() const { return vsub16F_reg_rule; } |
| 40077 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40078 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 40079 | virtual uint oper_input_base() const { return 1; } |
| 40080 | public: |
| 40081 | vsub16F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40082 | virtual uint size_of() const { return sizeof(vsub16F_regNode); } |
| 40083 | static const Pipeline *pipeline_class(); |
| 40084 | virtual const Pipeline *pipeline() const; |
| 40085 | #ifndef PRODUCT |
| 40086 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40087 | virtual const char *Name() const { return "vsub16F_reg";} |
| 40088 | #endif |
| 40089 | }; |
| 40090 | |
| 40091 | class vsub16F_memNode : public MachTypeNode { |
| 40092 | private: |
| 40093 | MachOper *_opnd_array[3]; |
| 40094 | public: |
| 40095 | MachOper *opnd_array(uint operand_index) const { |
| 40096 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40097 | return _opnd_array[operand_index]; |
| 40098 | } |
| 40099 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40100 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40101 | _opnd_array[operand_index] = operand; |
| 40102 | } |
| 40103 | private: |
| 40104 | virtual const RegMask &out_RegMask() const; |
| 40105 | virtual uint rule() const { return vsub16F_mem_rule; } |
| 40106 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40107 | virtual int ideal_Opcode() const { return Op_SubVF; } |
| 40108 | virtual int reloc() const; |
| 40109 | virtual uint oper_input_base() const { return 2; } |
| 40110 | public: |
| 40111 | vsub16F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40112 | virtual uint size_of() const { return sizeof(vsub16F_memNode); } |
| 40113 | static const Pipeline *pipeline_class(); |
| 40114 | virtual const Pipeline *pipeline() const; |
| 40115 | virtual const MachOper *memory_operand() const; |
| 40116 | #ifndef PRODUCT |
| 40117 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40118 | virtual const char *Name() const { return "vsub16F_mem";} |
| 40119 | #endif |
| 40120 | }; |
| 40121 | |
| 40122 | class vsub2DNode : public MachTypeNode { |
| 40123 | private: |
| 40124 | MachOper *_opnd_array[3]; |
| 40125 | public: |
| 40126 | MachOper *opnd_array(uint operand_index) const { |
| 40127 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40128 | return _opnd_array[operand_index]; |
| 40129 | } |
| 40130 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40131 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40132 | _opnd_array[operand_index] = operand; |
| 40133 | } |
| 40134 | private: |
| 40135 | virtual const RegMask &out_RegMask() const; |
| 40136 | virtual uint rule() const { return vsub2D_rule; } |
| 40137 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40138 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40139 | virtual uint two_adr() const { return oper_input_base(); } |
| 40140 | virtual uint oper_input_base() const { return 1; } |
| 40141 | public: |
| 40142 | vsub2DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40143 | virtual uint size_of() const { return sizeof(vsub2DNode); } |
| 40144 | static const Pipeline *pipeline_class(); |
| 40145 | virtual const Pipeline *pipeline() const; |
| 40146 | #ifndef PRODUCT |
| 40147 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40148 | virtual const char *Name() const { return "vsub2D";} |
| 40149 | #endif |
| 40150 | }; |
| 40151 | |
| 40152 | class vsub2D_regNode : public MachTypeNode { |
| 40153 | private: |
| 40154 | MachOper *_opnd_array[3]; |
| 40155 | public: |
| 40156 | MachOper *opnd_array(uint operand_index) const { |
| 40157 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40158 | return _opnd_array[operand_index]; |
| 40159 | } |
| 40160 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40161 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40162 | _opnd_array[operand_index] = operand; |
| 40163 | } |
| 40164 | private: |
| 40165 | virtual const RegMask &out_RegMask() const; |
| 40166 | virtual uint rule() const { return vsub2D_reg_rule; } |
| 40167 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40168 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40169 | virtual uint oper_input_base() const { return 1; } |
| 40170 | public: |
| 40171 | vsub2D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40172 | virtual uint size_of() const { return sizeof(vsub2D_regNode); } |
| 40173 | static const Pipeline *pipeline_class(); |
| 40174 | virtual const Pipeline *pipeline() const; |
| 40175 | #ifndef PRODUCT |
| 40176 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40177 | virtual const char *Name() const { return "vsub2D_reg";} |
| 40178 | #endif |
| 40179 | }; |
| 40180 | |
| 40181 | class vsub2D_memNode : public MachTypeNode { |
| 40182 | private: |
| 40183 | MachOper *_opnd_array[3]; |
| 40184 | public: |
| 40185 | MachOper *opnd_array(uint operand_index) const { |
| 40186 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40187 | return _opnd_array[operand_index]; |
| 40188 | } |
| 40189 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40190 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40191 | _opnd_array[operand_index] = operand; |
| 40192 | } |
| 40193 | private: |
| 40194 | virtual const RegMask &out_RegMask() const; |
| 40195 | virtual uint rule() const { return vsub2D_mem_rule; } |
| 40196 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40197 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40198 | virtual int reloc() const; |
| 40199 | virtual uint oper_input_base() const { return 2; } |
| 40200 | public: |
| 40201 | vsub2D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40202 | virtual uint size_of() const { return sizeof(vsub2D_memNode); } |
| 40203 | static const Pipeline *pipeline_class(); |
| 40204 | virtual const Pipeline *pipeline() const; |
| 40205 | virtual const MachOper *memory_operand() const; |
| 40206 | #ifndef PRODUCT |
| 40207 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40208 | virtual const char *Name() const { return "vsub2D_mem";} |
| 40209 | #endif |
| 40210 | }; |
| 40211 | |
| 40212 | class vsub4D_regNode : public MachTypeNode { |
| 40213 | private: |
| 40214 | MachOper *_opnd_array[3]; |
| 40215 | public: |
| 40216 | MachOper *opnd_array(uint operand_index) const { |
| 40217 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40218 | return _opnd_array[operand_index]; |
| 40219 | } |
| 40220 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40221 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40222 | _opnd_array[operand_index] = operand; |
| 40223 | } |
| 40224 | private: |
| 40225 | virtual const RegMask &out_RegMask() const; |
| 40226 | virtual uint rule() const { return vsub4D_reg_rule; } |
| 40227 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40228 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40229 | virtual uint oper_input_base() const { return 1; } |
| 40230 | public: |
| 40231 | vsub4D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40232 | virtual uint size_of() const { return sizeof(vsub4D_regNode); } |
| 40233 | static const Pipeline *pipeline_class(); |
| 40234 | virtual const Pipeline *pipeline() const; |
| 40235 | #ifndef PRODUCT |
| 40236 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40237 | virtual const char *Name() const { return "vsub4D_reg";} |
| 40238 | #endif |
| 40239 | }; |
| 40240 | |
| 40241 | class vsub4D_memNode : public MachTypeNode { |
| 40242 | private: |
| 40243 | MachOper *_opnd_array[3]; |
| 40244 | public: |
| 40245 | MachOper *opnd_array(uint operand_index) const { |
| 40246 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40247 | return _opnd_array[operand_index]; |
| 40248 | } |
| 40249 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40250 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40251 | _opnd_array[operand_index] = operand; |
| 40252 | } |
| 40253 | private: |
| 40254 | virtual const RegMask &out_RegMask() const; |
| 40255 | virtual uint rule() const { return vsub4D_mem_rule; } |
| 40256 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40257 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40258 | virtual int reloc() const; |
| 40259 | virtual uint oper_input_base() const { return 2; } |
| 40260 | public: |
| 40261 | vsub4D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40262 | virtual uint size_of() const { return sizeof(vsub4D_memNode); } |
| 40263 | static const Pipeline *pipeline_class(); |
| 40264 | virtual const Pipeline *pipeline() const; |
| 40265 | virtual const MachOper *memory_operand() const; |
| 40266 | #ifndef PRODUCT |
| 40267 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40268 | virtual const char *Name() const { return "vsub4D_mem";} |
| 40269 | #endif |
| 40270 | }; |
| 40271 | |
| 40272 | class vsub8D_regNode : public MachTypeNode { |
| 40273 | private: |
| 40274 | MachOper *_opnd_array[3]; |
| 40275 | public: |
| 40276 | MachOper *opnd_array(uint operand_index) const { |
| 40277 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40278 | return _opnd_array[operand_index]; |
| 40279 | } |
| 40280 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40281 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40282 | _opnd_array[operand_index] = operand; |
| 40283 | } |
| 40284 | private: |
| 40285 | virtual const RegMask &out_RegMask() const; |
| 40286 | virtual uint rule() const { return vsub8D_reg_rule; } |
| 40287 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40288 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40289 | virtual uint oper_input_base() const { return 1; } |
| 40290 | public: |
| 40291 | vsub8D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40292 | virtual uint size_of() const { return sizeof(vsub8D_regNode); } |
| 40293 | static const Pipeline *pipeline_class(); |
| 40294 | virtual const Pipeline *pipeline() const; |
| 40295 | #ifndef PRODUCT |
| 40296 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40297 | virtual const char *Name() const { return "vsub8D_reg";} |
| 40298 | #endif |
| 40299 | }; |
| 40300 | |
| 40301 | class vsub8D_memNode : public MachTypeNode { |
| 40302 | private: |
| 40303 | MachOper *_opnd_array[3]; |
| 40304 | public: |
| 40305 | MachOper *opnd_array(uint operand_index) const { |
| 40306 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40307 | return _opnd_array[operand_index]; |
| 40308 | } |
| 40309 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40310 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40311 | _opnd_array[operand_index] = operand; |
| 40312 | } |
| 40313 | private: |
| 40314 | virtual const RegMask &out_RegMask() const; |
| 40315 | virtual uint rule() const { return vsub8D_mem_rule; } |
| 40316 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40317 | virtual int ideal_Opcode() const { return Op_SubVD; } |
| 40318 | virtual int reloc() const; |
| 40319 | virtual uint oper_input_base() const { return 2; } |
| 40320 | public: |
| 40321 | vsub8D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40322 | virtual uint size_of() const { return sizeof(vsub8D_memNode); } |
| 40323 | static const Pipeline *pipeline_class(); |
| 40324 | virtual const Pipeline *pipeline() const; |
| 40325 | virtual const MachOper *memory_operand() const; |
| 40326 | #ifndef PRODUCT |
| 40327 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40328 | virtual const char *Name() const { return "vsub8D_mem";} |
| 40329 | #endif |
| 40330 | }; |
| 40331 | |
| 40332 | class mul4B_regNode : public MachTypeNode { |
| 40333 | private: |
| 40334 | MachOper *_opnd_array[6]; |
| 40335 | public: |
| 40336 | MachOper *opnd_array(uint operand_index) const { |
| 40337 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40338 | return _opnd_array[operand_index]; |
| 40339 | } |
| 40340 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40341 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40342 | _opnd_array[operand_index] = operand; |
| 40343 | } |
| 40344 | private: |
| 40345 | virtual const RegMask &out_RegMask() const; |
| 40346 | virtual uint rule() const { return mul4B_reg_rule; } |
| 40347 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40348 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40349 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40350 | virtual uint oper_input_base() const { return 1; } |
| 40351 | public: |
| 40352 | mul4B_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 40353 | virtual uint size_of() const { return sizeof(mul4B_regNode); } |
| 40354 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40355 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40356 | static const Pipeline *pipeline_class(); |
| 40357 | virtual const Pipeline *pipeline() const; |
| 40358 | #ifndef PRODUCT |
| 40359 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40360 | virtual const char *Name() const { return "mul4B_reg";} |
| 40361 | #endif |
| 40362 | }; |
| 40363 | |
| 40364 | class mul8B_regNode : public MachTypeNode { |
| 40365 | private: |
| 40366 | MachOper *_opnd_array[6]; |
| 40367 | public: |
| 40368 | MachOper *opnd_array(uint operand_index) const { |
| 40369 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40370 | return _opnd_array[operand_index]; |
| 40371 | } |
| 40372 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40373 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40374 | _opnd_array[operand_index] = operand; |
| 40375 | } |
| 40376 | private: |
| 40377 | virtual const RegMask &out_RegMask() const; |
| 40378 | virtual uint rule() const { return mul8B_reg_rule; } |
| 40379 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40380 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40381 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40382 | virtual uint oper_input_base() const { return 1; } |
| 40383 | public: |
| 40384 | mul8B_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 40385 | virtual uint size_of() const { return sizeof(mul8B_regNode); } |
| 40386 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40387 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40388 | static const Pipeline *pipeline_class(); |
| 40389 | virtual const Pipeline *pipeline() const; |
| 40390 | #ifndef PRODUCT |
| 40391 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40392 | virtual const char *Name() const { return "mul8B_reg";} |
| 40393 | #endif |
| 40394 | }; |
| 40395 | |
| 40396 | class mul16B_regNode : public MachTypeNode { |
| 40397 | private: |
| 40398 | MachOper *_opnd_array[7]; |
| 40399 | public: |
| 40400 | MachOper *opnd_array(uint operand_index) const { |
| 40401 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40402 | return _opnd_array[operand_index]; |
| 40403 | } |
| 40404 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40405 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40406 | _opnd_array[operand_index] = operand; |
| 40407 | } |
| 40408 | private: |
| 40409 | virtual const RegMask &out_RegMask() const; |
| 40410 | virtual uint rule() const { return mul16B_reg_rule; } |
| 40411 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40412 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40413 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40414 | virtual uint oper_input_base() const { return 1; } |
| 40415 | public: |
| 40416 | mul16B_regNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 40417 | virtual uint size_of() const { return sizeof(mul16B_regNode); } |
| 40418 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40419 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40420 | static const Pipeline *pipeline_class(); |
| 40421 | virtual const Pipeline *pipeline() const; |
| 40422 | #ifndef PRODUCT |
| 40423 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40424 | virtual const char *Name() const { return "mul16B_reg";} |
| 40425 | #endif |
| 40426 | }; |
| 40427 | |
| 40428 | class vmul16B_reg_avxNode : public MachTypeNode { |
| 40429 | private: |
| 40430 | MachOper *_opnd_array[6]; |
| 40431 | public: |
| 40432 | MachOper *opnd_array(uint operand_index) const { |
| 40433 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40434 | return _opnd_array[operand_index]; |
| 40435 | } |
| 40436 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40437 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40438 | _opnd_array[operand_index] = operand; |
| 40439 | } |
| 40440 | private: |
| 40441 | virtual const RegMask &out_RegMask() const; |
| 40442 | virtual uint rule() const { return vmul16B_reg_avx_rule; } |
| 40443 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40444 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40445 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40446 | virtual uint oper_input_base() const { return 1; } |
| 40447 | public: |
| 40448 | vmul16B_reg_avxNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 40449 | virtual uint size_of() const { return sizeof(vmul16B_reg_avxNode); } |
| 40450 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40451 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40452 | static const Pipeline *pipeline_class(); |
| 40453 | virtual const Pipeline *pipeline() const; |
| 40454 | #ifndef PRODUCT |
| 40455 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40456 | virtual const char *Name() const { return "vmul16B_reg_avx";} |
| 40457 | #endif |
| 40458 | }; |
| 40459 | |
| 40460 | class vmul32B_reg_avxNode : public MachTypeNode { |
| 40461 | private: |
| 40462 | MachOper *_opnd_array[7]; |
| 40463 | public: |
| 40464 | MachOper *opnd_array(uint operand_index) const { |
| 40465 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40466 | return _opnd_array[operand_index]; |
| 40467 | } |
| 40468 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40469 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40470 | _opnd_array[operand_index] = operand; |
| 40471 | } |
| 40472 | private: |
| 40473 | virtual const RegMask &out_RegMask() const; |
| 40474 | virtual uint rule() const { return vmul32B_reg_avx_rule; } |
| 40475 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40476 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40477 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40478 | virtual uint oper_input_base() const { return 1; } |
| 40479 | public: |
| 40480 | vmul32B_reg_avxNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 40481 | virtual uint size_of() const { return sizeof(vmul32B_reg_avxNode); } |
| 40482 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40483 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40484 | static const Pipeline *pipeline_class(); |
| 40485 | virtual const Pipeline *pipeline() const; |
| 40486 | #ifndef PRODUCT |
| 40487 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40488 | virtual const char *Name() const { return "vmul32B_reg_avx";} |
| 40489 | #endif |
| 40490 | }; |
| 40491 | |
| 40492 | class vmul64B_reg_avxNode : public MachTypeNode { |
| 40493 | private: |
| 40494 | MachOper *_opnd_array[7]; |
| 40495 | public: |
| 40496 | MachOper *opnd_array(uint operand_index) const { |
| 40497 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40498 | return _opnd_array[operand_index]; |
| 40499 | } |
| 40500 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40501 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40502 | _opnd_array[operand_index] = operand; |
| 40503 | } |
| 40504 | private: |
| 40505 | virtual const RegMask &out_RegMask() const; |
| 40506 | virtual uint rule() const { return vmul64B_reg_avx_rule; } |
| 40507 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40508 | virtual int ideal_Opcode() const { return Op_MulVB; } |
| 40509 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 40510 | virtual uint oper_input_base() const { return 1; } |
| 40511 | public: |
| 40512 | vmul64B_reg_avxNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 40513 | virtual uint size_of() const { return sizeof(vmul64B_reg_avxNode); } |
| 40514 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 40515 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 40516 | static const Pipeline *pipeline_class(); |
| 40517 | virtual const Pipeline *pipeline() const; |
| 40518 | #ifndef PRODUCT |
| 40519 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40520 | virtual const char *Name() const { return "vmul64B_reg_avx";} |
| 40521 | #endif |
| 40522 | }; |
| 40523 | |
| 40524 | class vmul2SNode : public MachTypeNode { |
| 40525 | private: |
| 40526 | MachOper *_opnd_array[3]; |
| 40527 | public: |
| 40528 | MachOper *opnd_array(uint operand_index) const { |
| 40529 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40530 | return _opnd_array[operand_index]; |
| 40531 | } |
| 40532 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40533 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40534 | _opnd_array[operand_index] = operand; |
| 40535 | } |
| 40536 | private: |
| 40537 | virtual const RegMask &out_RegMask() const; |
| 40538 | virtual uint rule() const { return vmul2S_rule; } |
| 40539 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40540 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40541 | virtual uint two_adr() const { return oper_input_base(); } |
| 40542 | virtual uint oper_input_base() const { return 1; } |
| 40543 | public: |
| 40544 | vmul2SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40545 | virtual uint size_of() const { return sizeof(vmul2SNode); } |
| 40546 | static const Pipeline *pipeline_class(); |
| 40547 | virtual const Pipeline *pipeline() const; |
| 40548 | #ifndef PRODUCT |
| 40549 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40550 | virtual const char *Name() const { return "vmul2S";} |
| 40551 | #endif |
| 40552 | }; |
| 40553 | |
| 40554 | class vmul2S_regNode : public MachTypeNode { |
| 40555 | private: |
| 40556 | MachOper *_opnd_array[3]; |
| 40557 | public: |
| 40558 | MachOper *opnd_array(uint operand_index) const { |
| 40559 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40560 | return _opnd_array[operand_index]; |
| 40561 | } |
| 40562 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40563 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40564 | _opnd_array[operand_index] = operand; |
| 40565 | } |
| 40566 | private: |
| 40567 | virtual const RegMask &out_RegMask() const; |
| 40568 | virtual uint rule() const { return vmul2S_reg_rule; } |
| 40569 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40570 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40571 | virtual uint oper_input_base() const { return 1; } |
| 40572 | public: |
| 40573 | vmul2S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40574 | virtual uint size_of() const { return sizeof(vmul2S_regNode); } |
| 40575 | static const Pipeline *pipeline_class(); |
| 40576 | virtual const Pipeline *pipeline() const; |
| 40577 | #ifndef PRODUCT |
| 40578 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40579 | virtual const char *Name() const { return "vmul2S_reg";} |
| 40580 | #endif |
| 40581 | }; |
| 40582 | |
| 40583 | class vmul2S_memNode : public MachTypeNode { |
| 40584 | private: |
| 40585 | MachOper *_opnd_array[3]; |
| 40586 | public: |
| 40587 | MachOper *opnd_array(uint operand_index) const { |
| 40588 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40589 | return _opnd_array[operand_index]; |
| 40590 | } |
| 40591 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40592 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40593 | _opnd_array[operand_index] = operand; |
| 40594 | } |
| 40595 | private: |
| 40596 | virtual const RegMask &out_RegMask() const; |
| 40597 | virtual uint rule() const { return vmul2S_mem_rule; } |
| 40598 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40599 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40600 | virtual int reloc() const; |
| 40601 | virtual uint oper_input_base() const { return 2; } |
| 40602 | public: |
| 40603 | vmul2S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40604 | virtual uint size_of() const { return sizeof(vmul2S_memNode); } |
| 40605 | static const Pipeline *pipeline_class(); |
| 40606 | virtual const Pipeline *pipeline() const; |
| 40607 | virtual const MachOper *memory_operand() const; |
| 40608 | #ifndef PRODUCT |
| 40609 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40610 | virtual const char *Name() const { return "vmul2S_mem";} |
| 40611 | #endif |
| 40612 | }; |
| 40613 | |
| 40614 | class vmul2S_mem_0Node : public MachTypeNode { |
| 40615 | private: |
| 40616 | MachOper *_opnd_array[3]; |
| 40617 | public: |
| 40618 | MachOper *opnd_array(uint operand_index) const { |
| 40619 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40620 | return _opnd_array[operand_index]; |
| 40621 | } |
| 40622 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40623 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40624 | _opnd_array[operand_index] = operand; |
| 40625 | } |
| 40626 | private: |
| 40627 | virtual const RegMask &out_RegMask() const; |
| 40628 | virtual uint rule() const { return vmul2S_mem_0_rule; } |
| 40629 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40630 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40631 | virtual int reloc() const; |
| 40632 | virtual uint oper_input_base() const { return 2; } |
| 40633 | public: |
| 40634 | vmul2S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40635 | virtual uint size_of() const { return sizeof(vmul2S_mem_0Node); } |
| 40636 | static const Pipeline *pipeline_class(); |
| 40637 | virtual const Pipeline *pipeline() const; |
| 40638 | virtual const MachOper *memory_operand() const; |
| 40639 | #ifndef PRODUCT |
| 40640 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40641 | virtual const char *Name() const { return "vmul2S_mem_0";} |
| 40642 | #endif |
| 40643 | }; |
| 40644 | |
| 40645 | class vmul4SNode : public MachTypeNode { |
| 40646 | private: |
| 40647 | MachOper *_opnd_array[3]; |
| 40648 | public: |
| 40649 | MachOper *opnd_array(uint operand_index) const { |
| 40650 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40651 | return _opnd_array[operand_index]; |
| 40652 | } |
| 40653 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40654 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40655 | _opnd_array[operand_index] = operand; |
| 40656 | } |
| 40657 | private: |
| 40658 | virtual const RegMask &out_RegMask() const; |
| 40659 | virtual uint rule() const { return vmul4S_rule; } |
| 40660 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40661 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40662 | virtual uint two_adr() const { return oper_input_base(); } |
| 40663 | virtual uint oper_input_base() const { return 1; } |
| 40664 | public: |
| 40665 | vmul4SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40666 | virtual uint size_of() const { return sizeof(vmul4SNode); } |
| 40667 | static const Pipeline *pipeline_class(); |
| 40668 | virtual const Pipeline *pipeline() const; |
| 40669 | #ifndef PRODUCT |
| 40670 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40671 | virtual const char *Name() const { return "vmul4S";} |
| 40672 | #endif |
| 40673 | }; |
| 40674 | |
| 40675 | class vmul4S_regNode : public MachTypeNode { |
| 40676 | private: |
| 40677 | MachOper *_opnd_array[3]; |
| 40678 | public: |
| 40679 | MachOper *opnd_array(uint operand_index) const { |
| 40680 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40681 | return _opnd_array[operand_index]; |
| 40682 | } |
| 40683 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40684 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40685 | _opnd_array[operand_index] = operand; |
| 40686 | } |
| 40687 | private: |
| 40688 | virtual const RegMask &out_RegMask() const; |
| 40689 | virtual uint rule() const { return vmul4S_reg_rule; } |
| 40690 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40691 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40692 | virtual uint oper_input_base() const { return 1; } |
| 40693 | public: |
| 40694 | vmul4S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40695 | virtual uint size_of() const { return sizeof(vmul4S_regNode); } |
| 40696 | static const Pipeline *pipeline_class(); |
| 40697 | virtual const Pipeline *pipeline() const; |
| 40698 | #ifndef PRODUCT |
| 40699 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40700 | virtual const char *Name() const { return "vmul4S_reg";} |
| 40701 | #endif |
| 40702 | }; |
| 40703 | |
| 40704 | class vmul4S_memNode : public MachTypeNode { |
| 40705 | private: |
| 40706 | MachOper *_opnd_array[3]; |
| 40707 | public: |
| 40708 | MachOper *opnd_array(uint operand_index) const { |
| 40709 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40710 | return _opnd_array[operand_index]; |
| 40711 | } |
| 40712 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40713 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40714 | _opnd_array[operand_index] = operand; |
| 40715 | } |
| 40716 | private: |
| 40717 | virtual const RegMask &out_RegMask() const; |
| 40718 | virtual uint rule() const { return vmul4S_mem_rule; } |
| 40719 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40720 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40721 | virtual int reloc() const; |
| 40722 | virtual uint oper_input_base() const { return 2; } |
| 40723 | public: |
| 40724 | vmul4S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40725 | virtual uint size_of() const { return sizeof(vmul4S_memNode); } |
| 40726 | static const Pipeline *pipeline_class(); |
| 40727 | virtual const Pipeline *pipeline() const; |
| 40728 | virtual const MachOper *memory_operand() const; |
| 40729 | #ifndef PRODUCT |
| 40730 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40731 | virtual const char *Name() const { return "vmul4S_mem";} |
| 40732 | #endif |
| 40733 | }; |
| 40734 | |
| 40735 | class vmul4S_mem_0Node : public MachTypeNode { |
| 40736 | private: |
| 40737 | MachOper *_opnd_array[3]; |
| 40738 | public: |
| 40739 | MachOper *opnd_array(uint operand_index) const { |
| 40740 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40741 | return _opnd_array[operand_index]; |
| 40742 | } |
| 40743 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40744 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40745 | _opnd_array[operand_index] = operand; |
| 40746 | } |
| 40747 | private: |
| 40748 | virtual const RegMask &out_RegMask() const; |
| 40749 | virtual uint rule() const { return vmul4S_mem_0_rule; } |
| 40750 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40751 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40752 | virtual int reloc() const; |
| 40753 | virtual uint oper_input_base() const { return 2; } |
| 40754 | public: |
| 40755 | vmul4S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40756 | virtual uint size_of() const { return sizeof(vmul4S_mem_0Node); } |
| 40757 | static const Pipeline *pipeline_class(); |
| 40758 | virtual const Pipeline *pipeline() const; |
| 40759 | virtual const MachOper *memory_operand() const; |
| 40760 | #ifndef PRODUCT |
| 40761 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40762 | virtual const char *Name() const { return "vmul4S_mem_0";} |
| 40763 | #endif |
| 40764 | }; |
| 40765 | |
| 40766 | class vmul8SNode : public MachTypeNode { |
| 40767 | private: |
| 40768 | MachOper *_opnd_array[3]; |
| 40769 | public: |
| 40770 | MachOper *opnd_array(uint operand_index) const { |
| 40771 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40772 | return _opnd_array[operand_index]; |
| 40773 | } |
| 40774 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40775 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40776 | _opnd_array[operand_index] = operand; |
| 40777 | } |
| 40778 | private: |
| 40779 | virtual const RegMask &out_RegMask() const; |
| 40780 | virtual uint rule() const { return vmul8S_rule; } |
| 40781 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40782 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40783 | virtual uint two_adr() const { return oper_input_base(); } |
| 40784 | virtual uint oper_input_base() const { return 1; } |
| 40785 | public: |
| 40786 | vmul8SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40787 | virtual uint size_of() const { return sizeof(vmul8SNode); } |
| 40788 | static const Pipeline *pipeline_class(); |
| 40789 | virtual const Pipeline *pipeline() const; |
| 40790 | #ifndef PRODUCT |
| 40791 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40792 | virtual const char *Name() const { return "vmul8S";} |
| 40793 | #endif |
| 40794 | }; |
| 40795 | |
| 40796 | class vmul8S_regNode : public MachTypeNode { |
| 40797 | private: |
| 40798 | MachOper *_opnd_array[3]; |
| 40799 | public: |
| 40800 | MachOper *opnd_array(uint operand_index) const { |
| 40801 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40802 | return _opnd_array[operand_index]; |
| 40803 | } |
| 40804 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40806 | _opnd_array[operand_index] = operand; |
| 40807 | } |
| 40808 | private: |
| 40809 | virtual const RegMask &out_RegMask() const; |
| 40810 | virtual uint rule() const { return vmul8S_reg_rule; } |
| 40811 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40812 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40813 | virtual uint oper_input_base() const { return 1; } |
| 40814 | public: |
| 40815 | vmul8S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40816 | virtual uint size_of() const { return sizeof(vmul8S_regNode); } |
| 40817 | static const Pipeline *pipeline_class(); |
| 40818 | virtual const Pipeline *pipeline() const; |
| 40819 | #ifndef PRODUCT |
| 40820 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40821 | virtual const char *Name() const { return "vmul8S_reg";} |
| 40822 | #endif |
| 40823 | }; |
| 40824 | |
| 40825 | class vmul8S_memNode : public MachTypeNode { |
| 40826 | private: |
| 40827 | MachOper *_opnd_array[3]; |
| 40828 | public: |
| 40829 | MachOper *opnd_array(uint operand_index) const { |
| 40830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40831 | return _opnd_array[operand_index]; |
| 40832 | } |
| 40833 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40834 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40835 | _opnd_array[operand_index] = operand; |
| 40836 | } |
| 40837 | private: |
| 40838 | virtual const RegMask &out_RegMask() const; |
| 40839 | virtual uint rule() const { return vmul8S_mem_rule; } |
| 40840 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40841 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40842 | virtual int reloc() const; |
| 40843 | virtual uint oper_input_base() const { return 2; } |
| 40844 | public: |
| 40845 | vmul8S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40846 | virtual uint size_of() const { return sizeof(vmul8S_memNode); } |
| 40847 | static const Pipeline *pipeline_class(); |
| 40848 | virtual const Pipeline *pipeline() const; |
| 40849 | virtual const MachOper *memory_operand() const; |
| 40850 | #ifndef PRODUCT |
| 40851 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40852 | virtual const char *Name() const { return "vmul8S_mem";} |
| 40853 | #endif |
| 40854 | }; |
| 40855 | |
| 40856 | class vmul8S_mem_0Node : public MachTypeNode { |
| 40857 | private: |
| 40858 | MachOper *_opnd_array[3]; |
| 40859 | public: |
| 40860 | MachOper *opnd_array(uint operand_index) const { |
| 40861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40862 | return _opnd_array[operand_index]; |
| 40863 | } |
| 40864 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40865 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40866 | _opnd_array[operand_index] = operand; |
| 40867 | } |
| 40868 | private: |
| 40869 | virtual const RegMask &out_RegMask() const; |
| 40870 | virtual uint rule() const { return vmul8S_mem_0_rule; } |
| 40871 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40872 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40873 | virtual int reloc() const; |
| 40874 | virtual uint oper_input_base() const { return 2; } |
| 40875 | public: |
| 40876 | vmul8S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40877 | virtual uint size_of() const { return sizeof(vmul8S_mem_0Node); } |
| 40878 | static const Pipeline *pipeline_class(); |
| 40879 | virtual const Pipeline *pipeline() const; |
| 40880 | virtual const MachOper *memory_operand() const; |
| 40881 | #ifndef PRODUCT |
| 40882 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40883 | virtual const char *Name() const { return "vmul8S_mem_0";} |
| 40884 | #endif |
| 40885 | }; |
| 40886 | |
| 40887 | class vmul16S_regNode : public MachTypeNode { |
| 40888 | private: |
| 40889 | MachOper *_opnd_array[3]; |
| 40890 | public: |
| 40891 | MachOper *opnd_array(uint operand_index) const { |
| 40892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40893 | return _opnd_array[operand_index]; |
| 40894 | } |
| 40895 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40896 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40897 | _opnd_array[operand_index] = operand; |
| 40898 | } |
| 40899 | private: |
| 40900 | virtual const RegMask &out_RegMask() const; |
| 40901 | virtual uint rule() const { return vmul16S_reg_rule; } |
| 40902 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40903 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40904 | virtual uint oper_input_base() const { return 1; } |
| 40905 | public: |
| 40906 | vmul16S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40907 | virtual uint size_of() const { return sizeof(vmul16S_regNode); } |
| 40908 | static const Pipeline *pipeline_class(); |
| 40909 | virtual const Pipeline *pipeline() const; |
| 40910 | #ifndef PRODUCT |
| 40911 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40912 | virtual const char *Name() const { return "vmul16S_reg";} |
| 40913 | #endif |
| 40914 | }; |
| 40915 | |
| 40916 | class vmul16S_memNode : public MachTypeNode { |
| 40917 | private: |
| 40918 | MachOper *_opnd_array[3]; |
| 40919 | public: |
| 40920 | MachOper *opnd_array(uint operand_index) const { |
| 40921 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40922 | return _opnd_array[operand_index]; |
| 40923 | } |
| 40924 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40925 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40926 | _opnd_array[operand_index] = operand; |
| 40927 | } |
| 40928 | private: |
| 40929 | virtual const RegMask &out_RegMask() const; |
| 40930 | virtual uint rule() const { return vmul16S_mem_rule; } |
| 40931 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40932 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40933 | virtual int reloc() const; |
| 40934 | virtual uint oper_input_base() const { return 2; } |
| 40935 | public: |
| 40936 | vmul16S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40937 | virtual uint size_of() const { return sizeof(vmul16S_memNode); } |
| 40938 | static const Pipeline *pipeline_class(); |
| 40939 | virtual const Pipeline *pipeline() const; |
| 40940 | virtual const MachOper *memory_operand() const; |
| 40941 | #ifndef PRODUCT |
| 40942 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40943 | virtual const char *Name() const { return "vmul16S_mem";} |
| 40944 | #endif |
| 40945 | }; |
| 40946 | |
| 40947 | class vmul16S_mem_0Node : public MachTypeNode { |
| 40948 | private: |
| 40949 | MachOper *_opnd_array[3]; |
| 40950 | public: |
| 40951 | MachOper *opnd_array(uint operand_index) const { |
| 40952 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40953 | return _opnd_array[operand_index]; |
| 40954 | } |
| 40955 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40957 | _opnd_array[operand_index] = operand; |
| 40958 | } |
| 40959 | private: |
| 40960 | virtual const RegMask &out_RegMask() const; |
| 40961 | virtual uint rule() const { return vmul16S_mem_0_rule; } |
| 40962 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40963 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40964 | virtual int reloc() const; |
| 40965 | virtual uint oper_input_base() const { return 2; } |
| 40966 | public: |
| 40967 | vmul16S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 40968 | virtual uint size_of() const { return sizeof(vmul16S_mem_0Node); } |
| 40969 | static const Pipeline *pipeline_class(); |
| 40970 | virtual const Pipeline *pipeline() const; |
| 40971 | virtual const MachOper *memory_operand() const; |
| 40972 | #ifndef PRODUCT |
| 40973 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 40974 | virtual const char *Name() const { return "vmul16S_mem_0";} |
| 40975 | #endif |
| 40976 | }; |
| 40977 | |
| 40978 | class vmul32S_regNode : public MachTypeNode { |
| 40979 | private: |
| 40980 | MachOper *_opnd_array[3]; |
| 40981 | public: |
| 40982 | MachOper *opnd_array(uint operand_index) const { |
| 40983 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40984 | return _opnd_array[operand_index]; |
| 40985 | } |
| 40986 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 40987 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 40988 | _opnd_array[operand_index] = operand; |
| 40989 | } |
| 40990 | private: |
| 40991 | virtual const RegMask &out_RegMask() const; |
| 40992 | virtual uint rule() const { return vmul32S_reg_rule; } |
| 40993 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 40994 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 40995 | virtual uint oper_input_base() const { return 1; } |
| 40996 | public: |
| 40997 | vmul32S_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 40998 | virtual uint size_of() const { return sizeof(vmul32S_regNode); } |
| 40999 | static const Pipeline *pipeline_class(); |
| 41000 | virtual const Pipeline *pipeline() const; |
| 41001 | #ifndef PRODUCT |
| 41002 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41003 | virtual const char *Name() const { return "vmul32S_reg";} |
| 41004 | #endif |
| 41005 | }; |
| 41006 | |
| 41007 | class vmul32S_memNode : public MachTypeNode { |
| 41008 | private: |
| 41009 | MachOper *_opnd_array[3]; |
| 41010 | public: |
| 41011 | MachOper *opnd_array(uint operand_index) const { |
| 41012 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41013 | return _opnd_array[operand_index]; |
| 41014 | } |
| 41015 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41017 | _opnd_array[operand_index] = operand; |
| 41018 | } |
| 41019 | private: |
| 41020 | virtual const RegMask &out_RegMask() const; |
| 41021 | virtual uint rule() const { return vmul32S_mem_rule; } |
| 41022 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41023 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 41024 | virtual int reloc() const; |
| 41025 | virtual uint oper_input_base() const { return 2; } |
| 41026 | public: |
| 41027 | vmul32S_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41028 | virtual uint size_of() const { return sizeof(vmul32S_memNode); } |
| 41029 | static const Pipeline *pipeline_class(); |
| 41030 | virtual const Pipeline *pipeline() const; |
| 41031 | virtual const MachOper *memory_operand() const; |
| 41032 | #ifndef PRODUCT |
| 41033 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41034 | virtual const char *Name() const { return "vmul32S_mem";} |
| 41035 | #endif |
| 41036 | }; |
| 41037 | |
| 41038 | class vmul32S_mem_0Node : public MachTypeNode { |
| 41039 | private: |
| 41040 | MachOper *_opnd_array[3]; |
| 41041 | public: |
| 41042 | MachOper *opnd_array(uint operand_index) const { |
| 41043 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41044 | return _opnd_array[operand_index]; |
| 41045 | } |
| 41046 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41047 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41048 | _opnd_array[operand_index] = operand; |
| 41049 | } |
| 41050 | private: |
| 41051 | virtual const RegMask &out_RegMask() const; |
| 41052 | virtual uint rule() const { return vmul32S_mem_0_rule; } |
| 41053 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41054 | virtual int ideal_Opcode() const { return Op_MulVS; } |
| 41055 | virtual int reloc() const; |
| 41056 | virtual uint oper_input_base() const { return 2; } |
| 41057 | public: |
| 41058 | vmul32S_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41059 | virtual uint size_of() const { return sizeof(vmul32S_mem_0Node); } |
| 41060 | static const Pipeline *pipeline_class(); |
| 41061 | virtual const Pipeline *pipeline() const; |
| 41062 | virtual const MachOper *memory_operand() const; |
| 41063 | #ifndef PRODUCT |
| 41064 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41065 | virtual const char *Name() const { return "vmul32S_mem_0";} |
| 41066 | #endif |
| 41067 | }; |
| 41068 | |
| 41069 | class vmul2INode : public MachTypeNode { |
| 41070 | private: |
| 41071 | MachOper *_opnd_array[3]; |
| 41072 | public: |
| 41073 | MachOper *opnd_array(uint operand_index) const { |
| 41074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41075 | return _opnd_array[operand_index]; |
| 41076 | } |
| 41077 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41078 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41079 | _opnd_array[operand_index] = operand; |
| 41080 | } |
| 41081 | private: |
| 41082 | virtual const RegMask &out_RegMask() const; |
| 41083 | virtual uint rule() const { return vmul2I_rule; } |
| 41084 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41085 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41086 | virtual uint two_adr() const { return oper_input_base(); } |
| 41087 | virtual uint oper_input_base() const { return 1; } |
| 41088 | public: |
| 41089 | vmul2INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41090 | virtual uint size_of() const { return sizeof(vmul2INode); } |
| 41091 | static const Pipeline *pipeline_class(); |
| 41092 | virtual const Pipeline *pipeline() const; |
| 41093 | #ifndef PRODUCT |
| 41094 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41095 | virtual const char *Name() const { return "vmul2I";} |
| 41096 | #endif |
| 41097 | }; |
| 41098 | |
| 41099 | class vmul2I_regNode : public MachTypeNode { |
| 41100 | private: |
| 41101 | MachOper *_opnd_array[3]; |
| 41102 | public: |
| 41103 | MachOper *opnd_array(uint operand_index) const { |
| 41104 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41105 | return _opnd_array[operand_index]; |
| 41106 | } |
| 41107 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41108 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41109 | _opnd_array[operand_index] = operand; |
| 41110 | } |
| 41111 | private: |
| 41112 | virtual const RegMask &out_RegMask() const; |
| 41113 | virtual uint rule() const { return vmul2I_reg_rule; } |
| 41114 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41115 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41116 | virtual uint oper_input_base() const { return 1; } |
| 41117 | public: |
| 41118 | vmul2I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41119 | virtual uint size_of() const { return sizeof(vmul2I_regNode); } |
| 41120 | static const Pipeline *pipeline_class(); |
| 41121 | virtual const Pipeline *pipeline() const; |
| 41122 | #ifndef PRODUCT |
| 41123 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41124 | virtual const char *Name() const { return "vmul2I_reg";} |
| 41125 | #endif |
| 41126 | }; |
| 41127 | |
| 41128 | class vmul2I_memNode : public MachTypeNode { |
| 41129 | private: |
| 41130 | MachOper *_opnd_array[3]; |
| 41131 | public: |
| 41132 | MachOper *opnd_array(uint operand_index) const { |
| 41133 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41134 | return _opnd_array[operand_index]; |
| 41135 | } |
| 41136 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41138 | _opnd_array[operand_index] = operand; |
| 41139 | } |
| 41140 | private: |
| 41141 | virtual const RegMask &out_RegMask() const; |
| 41142 | virtual uint rule() const { return vmul2I_mem_rule; } |
| 41143 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41144 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41145 | virtual int reloc() const; |
| 41146 | virtual uint oper_input_base() const { return 2; } |
| 41147 | public: |
| 41148 | vmul2I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41149 | virtual uint size_of() const { return sizeof(vmul2I_memNode); } |
| 41150 | static const Pipeline *pipeline_class(); |
| 41151 | virtual const Pipeline *pipeline() const; |
| 41152 | virtual const MachOper *memory_operand() const; |
| 41153 | #ifndef PRODUCT |
| 41154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41155 | virtual const char *Name() const { return "vmul2I_mem";} |
| 41156 | #endif |
| 41157 | }; |
| 41158 | |
| 41159 | class vmul2I_mem_0Node : public MachTypeNode { |
| 41160 | private: |
| 41161 | MachOper *_opnd_array[3]; |
| 41162 | public: |
| 41163 | MachOper *opnd_array(uint operand_index) const { |
| 41164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41165 | return _opnd_array[operand_index]; |
| 41166 | } |
| 41167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41169 | _opnd_array[operand_index] = operand; |
| 41170 | } |
| 41171 | private: |
| 41172 | virtual const RegMask &out_RegMask() const; |
| 41173 | virtual uint rule() const { return vmul2I_mem_0_rule; } |
| 41174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41175 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41176 | virtual int reloc() const; |
| 41177 | virtual uint oper_input_base() const { return 2; } |
| 41178 | public: |
| 41179 | vmul2I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41180 | virtual uint size_of() const { return sizeof(vmul2I_mem_0Node); } |
| 41181 | static const Pipeline *pipeline_class(); |
| 41182 | virtual const Pipeline *pipeline() const; |
| 41183 | virtual const MachOper *memory_operand() const; |
| 41184 | #ifndef PRODUCT |
| 41185 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41186 | virtual const char *Name() const { return "vmul2I_mem_0";} |
| 41187 | #endif |
| 41188 | }; |
| 41189 | |
| 41190 | class vmul4INode : public MachTypeNode { |
| 41191 | private: |
| 41192 | MachOper *_opnd_array[3]; |
| 41193 | public: |
| 41194 | MachOper *opnd_array(uint operand_index) const { |
| 41195 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41196 | return _opnd_array[operand_index]; |
| 41197 | } |
| 41198 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41200 | _opnd_array[operand_index] = operand; |
| 41201 | } |
| 41202 | private: |
| 41203 | virtual const RegMask &out_RegMask() const; |
| 41204 | virtual uint rule() const { return vmul4I_rule; } |
| 41205 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41206 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41207 | virtual uint two_adr() const { return oper_input_base(); } |
| 41208 | virtual uint oper_input_base() const { return 1; } |
| 41209 | public: |
| 41210 | vmul4INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41211 | virtual uint size_of() const { return sizeof(vmul4INode); } |
| 41212 | static const Pipeline *pipeline_class(); |
| 41213 | virtual const Pipeline *pipeline() const; |
| 41214 | #ifndef PRODUCT |
| 41215 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41216 | virtual const char *Name() const { return "vmul4I";} |
| 41217 | #endif |
| 41218 | }; |
| 41219 | |
| 41220 | class vmul4I_regNode : public MachTypeNode { |
| 41221 | private: |
| 41222 | MachOper *_opnd_array[3]; |
| 41223 | public: |
| 41224 | MachOper *opnd_array(uint operand_index) const { |
| 41225 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41226 | return _opnd_array[operand_index]; |
| 41227 | } |
| 41228 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41229 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41230 | _opnd_array[operand_index] = operand; |
| 41231 | } |
| 41232 | private: |
| 41233 | virtual const RegMask &out_RegMask() const; |
| 41234 | virtual uint rule() const { return vmul4I_reg_rule; } |
| 41235 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41236 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41237 | virtual uint oper_input_base() const { return 1; } |
| 41238 | public: |
| 41239 | vmul4I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41240 | virtual uint size_of() const { return sizeof(vmul4I_regNode); } |
| 41241 | static const Pipeline *pipeline_class(); |
| 41242 | virtual const Pipeline *pipeline() const; |
| 41243 | #ifndef PRODUCT |
| 41244 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41245 | virtual const char *Name() const { return "vmul4I_reg";} |
| 41246 | #endif |
| 41247 | }; |
| 41248 | |
| 41249 | class vmul4I_memNode : public MachTypeNode { |
| 41250 | private: |
| 41251 | MachOper *_opnd_array[3]; |
| 41252 | public: |
| 41253 | MachOper *opnd_array(uint operand_index) const { |
| 41254 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41255 | return _opnd_array[operand_index]; |
| 41256 | } |
| 41257 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41258 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41259 | _opnd_array[operand_index] = operand; |
| 41260 | } |
| 41261 | private: |
| 41262 | virtual const RegMask &out_RegMask() const; |
| 41263 | virtual uint rule() const { return vmul4I_mem_rule; } |
| 41264 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41265 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41266 | virtual int reloc() const; |
| 41267 | virtual uint oper_input_base() const { return 2; } |
| 41268 | public: |
| 41269 | vmul4I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41270 | virtual uint size_of() const { return sizeof(vmul4I_memNode); } |
| 41271 | static const Pipeline *pipeline_class(); |
| 41272 | virtual const Pipeline *pipeline() const; |
| 41273 | virtual const MachOper *memory_operand() const; |
| 41274 | #ifndef PRODUCT |
| 41275 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41276 | virtual const char *Name() const { return "vmul4I_mem";} |
| 41277 | #endif |
| 41278 | }; |
| 41279 | |
| 41280 | class vmul4I_mem_0Node : public MachTypeNode { |
| 41281 | private: |
| 41282 | MachOper *_opnd_array[3]; |
| 41283 | public: |
| 41284 | MachOper *opnd_array(uint operand_index) const { |
| 41285 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41286 | return _opnd_array[operand_index]; |
| 41287 | } |
| 41288 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41289 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41290 | _opnd_array[operand_index] = operand; |
| 41291 | } |
| 41292 | private: |
| 41293 | virtual const RegMask &out_RegMask() const; |
| 41294 | virtual uint rule() const { return vmul4I_mem_0_rule; } |
| 41295 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41296 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41297 | virtual int reloc() const; |
| 41298 | virtual uint oper_input_base() const { return 2; } |
| 41299 | public: |
| 41300 | vmul4I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41301 | virtual uint size_of() const { return sizeof(vmul4I_mem_0Node); } |
| 41302 | static const Pipeline *pipeline_class(); |
| 41303 | virtual const Pipeline *pipeline() const; |
| 41304 | virtual const MachOper *memory_operand() const; |
| 41305 | #ifndef PRODUCT |
| 41306 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41307 | virtual const char *Name() const { return "vmul4I_mem_0";} |
| 41308 | #endif |
| 41309 | }; |
| 41310 | |
| 41311 | class vmul2L_regNode : public MachTypeNode { |
| 41312 | private: |
| 41313 | MachOper *_opnd_array[3]; |
| 41314 | public: |
| 41315 | MachOper *opnd_array(uint operand_index) const { |
| 41316 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41317 | return _opnd_array[operand_index]; |
| 41318 | } |
| 41319 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41320 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41321 | _opnd_array[operand_index] = operand; |
| 41322 | } |
| 41323 | private: |
| 41324 | virtual const RegMask &out_RegMask() const; |
| 41325 | virtual uint rule() const { return vmul2L_reg_rule; } |
| 41326 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41327 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41328 | virtual uint oper_input_base() const { return 1; } |
| 41329 | public: |
| 41330 | vmul2L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41331 | virtual uint size_of() const { return sizeof(vmul2L_regNode); } |
| 41332 | static const Pipeline *pipeline_class(); |
| 41333 | virtual const Pipeline *pipeline() const; |
| 41334 | #ifndef PRODUCT |
| 41335 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41336 | virtual const char *Name() const { return "vmul2L_reg";} |
| 41337 | #endif |
| 41338 | }; |
| 41339 | |
| 41340 | class vmul2L_memNode : public MachTypeNode { |
| 41341 | private: |
| 41342 | MachOper *_opnd_array[3]; |
| 41343 | public: |
| 41344 | MachOper *opnd_array(uint operand_index) const { |
| 41345 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41346 | return _opnd_array[operand_index]; |
| 41347 | } |
| 41348 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41349 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41350 | _opnd_array[operand_index] = operand; |
| 41351 | } |
| 41352 | private: |
| 41353 | virtual const RegMask &out_RegMask() const; |
| 41354 | virtual uint rule() const { return vmul2L_mem_rule; } |
| 41355 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41356 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41357 | virtual int reloc() const; |
| 41358 | virtual uint oper_input_base() const { return 2; } |
| 41359 | public: |
| 41360 | vmul2L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41361 | virtual uint size_of() const { return sizeof(vmul2L_memNode); } |
| 41362 | static const Pipeline *pipeline_class(); |
| 41363 | virtual const Pipeline *pipeline() const; |
| 41364 | virtual const MachOper *memory_operand() const; |
| 41365 | #ifndef PRODUCT |
| 41366 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41367 | virtual const char *Name() const { return "vmul2L_mem";} |
| 41368 | #endif |
| 41369 | }; |
| 41370 | |
| 41371 | class vmul2L_mem_0Node : public MachTypeNode { |
| 41372 | private: |
| 41373 | MachOper *_opnd_array[3]; |
| 41374 | public: |
| 41375 | MachOper *opnd_array(uint operand_index) const { |
| 41376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41377 | return _opnd_array[operand_index]; |
| 41378 | } |
| 41379 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41380 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41381 | _opnd_array[operand_index] = operand; |
| 41382 | } |
| 41383 | private: |
| 41384 | virtual const RegMask &out_RegMask() const; |
| 41385 | virtual uint rule() const { return vmul2L_mem_0_rule; } |
| 41386 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41387 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41388 | virtual int reloc() const; |
| 41389 | virtual uint oper_input_base() const { return 2; } |
| 41390 | public: |
| 41391 | vmul2L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41392 | virtual uint size_of() const { return sizeof(vmul2L_mem_0Node); } |
| 41393 | static const Pipeline *pipeline_class(); |
| 41394 | virtual const Pipeline *pipeline() const; |
| 41395 | virtual const MachOper *memory_operand() const; |
| 41396 | #ifndef PRODUCT |
| 41397 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41398 | virtual const char *Name() const { return "vmul2L_mem_0";} |
| 41399 | #endif |
| 41400 | }; |
| 41401 | |
| 41402 | class vmul4L_regNode : public MachTypeNode { |
| 41403 | private: |
| 41404 | MachOper *_opnd_array[3]; |
| 41405 | public: |
| 41406 | MachOper *opnd_array(uint operand_index) const { |
| 41407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41408 | return _opnd_array[operand_index]; |
| 41409 | } |
| 41410 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41412 | _opnd_array[operand_index] = operand; |
| 41413 | } |
| 41414 | private: |
| 41415 | virtual const RegMask &out_RegMask() const; |
| 41416 | virtual uint rule() const { return vmul4L_reg_rule; } |
| 41417 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41418 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41419 | virtual uint oper_input_base() const { return 1; } |
| 41420 | public: |
| 41421 | vmul4L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41422 | virtual uint size_of() const { return sizeof(vmul4L_regNode); } |
| 41423 | static const Pipeline *pipeline_class(); |
| 41424 | virtual const Pipeline *pipeline() const; |
| 41425 | #ifndef PRODUCT |
| 41426 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41427 | virtual const char *Name() const { return "vmul4L_reg";} |
| 41428 | #endif |
| 41429 | }; |
| 41430 | |
| 41431 | class vmul4L_memNode : public MachTypeNode { |
| 41432 | private: |
| 41433 | MachOper *_opnd_array[3]; |
| 41434 | public: |
| 41435 | MachOper *opnd_array(uint operand_index) const { |
| 41436 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41437 | return _opnd_array[operand_index]; |
| 41438 | } |
| 41439 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41441 | _opnd_array[operand_index] = operand; |
| 41442 | } |
| 41443 | private: |
| 41444 | virtual const RegMask &out_RegMask() const; |
| 41445 | virtual uint rule() const { return vmul4L_mem_rule; } |
| 41446 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41447 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41448 | virtual int reloc() const; |
| 41449 | virtual uint oper_input_base() const { return 2; } |
| 41450 | public: |
| 41451 | vmul4L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41452 | virtual uint size_of() const { return sizeof(vmul4L_memNode); } |
| 41453 | static const Pipeline *pipeline_class(); |
| 41454 | virtual const Pipeline *pipeline() const; |
| 41455 | virtual const MachOper *memory_operand() const; |
| 41456 | #ifndef PRODUCT |
| 41457 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41458 | virtual const char *Name() const { return "vmul4L_mem";} |
| 41459 | #endif |
| 41460 | }; |
| 41461 | |
| 41462 | class vmul4L_mem_0Node : public MachTypeNode { |
| 41463 | private: |
| 41464 | MachOper *_opnd_array[3]; |
| 41465 | public: |
| 41466 | MachOper *opnd_array(uint operand_index) const { |
| 41467 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41468 | return _opnd_array[operand_index]; |
| 41469 | } |
| 41470 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41471 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41472 | _opnd_array[operand_index] = operand; |
| 41473 | } |
| 41474 | private: |
| 41475 | virtual const RegMask &out_RegMask() const; |
| 41476 | virtual uint rule() const { return vmul4L_mem_0_rule; } |
| 41477 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41478 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41479 | virtual int reloc() const; |
| 41480 | virtual uint oper_input_base() const { return 2; } |
| 41481 | public: |
| 41482 | vmul4L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41483 | virtual uint size_of() const { return sizeof(vmul4L_mem_0Node); } |
| 41484 | static const Pipeline *pipeline_class(); |
| 41485 | virtual const Pipeline *pipeline() const; |
| 41486 | virtual const MachOper *memory_operand() const; |
| 41487 | #ifndef PRODUCT |
| 41488 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41489 | virtual const char *Name() const { return "vmul4L_mem_0";} |
| 41490 | #endif |
| 41491 | }; |
| 41492 | |
| 41493 | class vmul8L_regNode : public MachTypeNode { |
| 41494 | private: |
| 41495 | MachOper *_opnd_array[3]; |
| 41496 | public: |
| 41497 | MachOper *opnd_array(uint operand_index) const { |
| 41498 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41499 | return _opnd_array[operand_index]; |
| 41500 | } |
| 41501 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41502 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41503 | _opnd_array[operand_index] = operand; |
| 41504 | } |
| 41505 | private: |
| 41506 | virtual const RegMask &out_RegMask() const; |
| 41507 | virtual uint rule() const { return vmul8L_reg_rule; } |
| 41508 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41509 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41510 | virtual uint oper_input_base() const { return 1; } |
| 41511 | public: |
| 41512 | vmul8L_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41513 | virtual uint size_of() const { return sizeof(vmul8L_regNode); } |
| 41514 | static const Pipeline *pipeline_class(); |
| 41515 | virtual const Pipeline *pipeline() const; |
| 41516 | #ifndef PRODUCT |
| 41517 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41518 | virtual const char *Name() const { return "vmul8L_reg";} |
| 41519 | #endif |
| 41520 | }; |
| 41521 | |
| 41522 | class vmul8L_memNode : public MachTypeNode { |
| 41523 | private: |
| 41524 | MachOper *_opnd_array[3]; |
| 41525 | public: |
| 41526 | MachOper *opnd_array(uint operand_index) const { |
| 41527 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41528 | return _opnd_array[operand_index]; |
| 41529 | } |
| 41530 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41531 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41532 | _opnd_array[operand_index] = operand; |
| 41533 | } |
| 41534 | private: |
| 41535 | virtual const RegMask &out_RegMask() const; |
| 41536 | virtual uint rule() const { return vmul8L_mem_rule; } |
| 41537 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41538 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41539 | virtual int reloc() const; |
| 41540 | virtual uint oper_input_base() const { return 2; } |
| 41541 | public: |
| 41542 | vmul8L_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41543 | virtual uint size_of() const { return sizeof(vmul8L_memNode); } |
| 41544 | static const Pipeline *pipeline_class(); |
| 41545 | virtual const Pipeline *pipeline() const; |
| 41546 | virtual const MachOper *memory_operand() const; |
| 41547 | #ifndef PRODUCT |
| 41548 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41549 | virtual const char *Name() const { return "vmul8L_mem";} |
| 41550 | #endif |
| 41551 | }; |
| 41552 | |
| 41553 | class vmul8L_mem_0Node : public MachTypeNode { |
| 41554 | private: |
| 41555 | MachOper *_opnd_array[3]; |
| 41556 | public: |
| 41557 | MachOper *opnd_array(uint operand_index) const { |
| 41558 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41559 | return _opnd_array[operand_index]; |
| 41560 | } |
| 41561 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41562 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41563 | _opnd_array[operand_index] = operand; |
| 41564 | } |
| 41565 | private: |
| 41566 | virtual const RegMask &out_RegMask() const; |
| 41567 | virtual uint rule() const { return vmul8L_mem_0_rule; } |
| 41568 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41569 | virtual int ideal_Opcode() const { return Op_MulVL; } |
| 41570 | virtual int reloc() const; |
| 41571 | virtual uint oper_input_base() const { return 2; } |
| 41572 | public: |
| 41573 | vmul8L_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41574 | virtual uint size_of() const { return sizeof(vmul8L_mem_0Node); } |
| 41575 | static const Pipeline *pipeline_class(); |
| 41576 | virtual const Pipeline *pipeline() const; |
| 41577 | virtual const MachOper *memory_operand() const; |
| 41578 | #ifndef PRODUCT |
| 41579 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41580 | virtual const char *Name() const { return "vmul8L_mem_0";} |
| 41581 | #endif |
| 41582 | }; |
| 41583 | |
| 41584 | class vmul8I_regNode : public MachTypeNode { |
| 41585 | private: |
| 41586 | MachOper *_opnd_array[3]; |
| 41587 | public: |
| 41588 | MachOper *opnd_array(uint operand_index) const { |
| 41589 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41590 | return _opnd_array[operand_index]; |
| 41591 | } |
| 41592 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41593 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41594 | _opnd_array[operand_index] = operand; |
| 41595 | } |
| 41596 | private: |
| 41597 | virtual const RegMask &out_RegMask() const; |
| 41598 | virtual uint rule() const { return vmul8I_reg_rule; } |
| 41599 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41600 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41601 | virtual uint oper_input_base() const { return 1; } |
| 41602 | public: |
| 41603 | vmul8I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41604 | virtual uint size_of() const { return sizeof(vmul8I_regNode); } |
| 41605 | static const Pipeline *pipeline_class(); |
| 41606 | virtual const Pipeline *pipeline() const; |
| 41607 | #ifndef PRODUCT |
| 41608 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41609 | virtual const char *Name() const { return "vmul8I_reg";} |
| 41610 | #endif |
| 41611 | }; |
| 41612 | |
| 41613 | class vmul8I_memNode : public MachTypeNode { |
| 41614 | private: |
| 41615 | MachOper *_opnd_array[3]; |
| 41616 | public: |
| 41617 | MachOper *opnd_array(uint operand_index) const { |
| 41618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41619 | return _opnd_array[operand_index]; |
| 41620 | } |
| 41621 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41622 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41623 | _opnd_array[operand_index] = operand; |
| 41624 | } |
| 41625 | private: |
| 41626 | virtual const RegMask &out_RegMask() const; |
| 41627 | virtual uint rule() const { return vmul8I_mem_rule; } |
| 41628 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41629 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41630 | virtual int reloc() const; |
| 41631 | virtual uint oper_input_base() const { return 2; } |
| 41632 | public: |
| 41633 | vmul8I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41634 | virtual uint size_of() const { return sizeof(vmul8I_memNode); } |
| 41635 | static const Pipeline *pipeline_class(); |
| 41636 | virtual const Pipeline *pipeline() const; |
| 41637 | virtual const MachOper *memory_operand() const; |
| 41638 | #ifndef PRODUCT |
| 41639 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41640 | virtual const char *Name() const { return "vmul8I_mem";} |
| 41641 | #endif |
| 41642 | }; |
| 41643 | |
| 41644 | class vmul8I_mem_0Node : public MachTypeNode { |
| 41645 | private: |
| 41646 | MachOper *_opnd_array[3]; |
| 41647 | public: |
| 41648 | MachOper *opnd_array(uint operand_index) const { |
| 41649 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41650 | return _opnd_array[operand_index]; |
| 41651 | } |
| 41652 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41653 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41654 | _opnd_array[operand_index] = operand; |
| 41655 | } |
| 41656 | private: |
| 41657 | virtual const RegMask &out_RegMask() const; |
| 41658 | virtual uint rule() const { return vmul8I_mem_0_rule; } |
| 41659 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41660 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41661 | virtual int reloc() const; |
| 41662 | virtual uint oper_input_base() const { return 2; } |
| 41663 | public: |
| 41664 | vmul8I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41665 | virtual uint size_of() const { return sizeof(vmul8I_mem_0Node); } |
| 41666 | static const Pipeline *pipeline_class(); |
| 41667 | virtual const Pipeline *pipeline() const; |
| 41668 | virtual const MachOper *memory_operand() const; |
| 41669 | #ifndef PRODUCT |
| 41670 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41671 | virtual const char *Name() const { return "vmul8I_mem_0";} |
| 41672 | #endif |
| 41673 | }; |
| 41674 | |
| 41675 | class vmul16I_regNode : public MachTypeNode { |
| 41676 | private: |
| 41677 | MachOper *_opnd_array[3]; |
| 41678 | public: |
| 41679 | MachOper *opnd_array(uint operand_index) const { |
| 41680 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41681 | return _opnd_array[operand_index]; |
| 41682 | } |
| 41683 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41684 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41685 | _opnd_array[operand_index] = operand; |
| 41686 | } |
| 41687 | private: |
| 41688 | virtual const RegMask &out_RegMask() const; |
| 41689 | virtual uint rule() const { return vmul16I_reg_rule; } |
| 41690 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41691 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41692 | virtual uint oper_input_base() const { return 1; } |
| 41693 | public: |
| 41694 | vmul16I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41695 | virtual uint size_of() const { return sizeof(vmul16I_regNode); } |
| 41696 | static const Pipeline *pipeline_class(); |
| 41697 | virtual const Pipeline *pipeline() const; |
| 41698 | #ifndef PRODUCT |
| 41699 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41700 | virtual const char *Name() const { return "vmul16I_reg";} |
| 41701 | #endif |
| 41702 | }; |
| 41703 | |
| 41704 | class vmul16I_memNode : public MachTypeNode { |
| 41705 | private: |
| 41706 | MachOper *_opnd_array[3]; |
| 41707 | public: |
| 41708 | MachOper *opnd_array(uint operand_index) const { |
| 41709 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41710 | return _opnd_array[operand_index]; |
| 41711 | } |
| 41712 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41713 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41714 | _opnd_array[operand_index] = operand; |
| 41715 | } |
| 41716 | private: |
| 41717 | virtual const RegMask &out_RegMask() const; |
| 41718 | virtual uint rule() const { return vmul16I_mem_rule; } |
| 41719 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41720 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41721 | virtual int reloc() const; |
| 41722 | virtual uint oper_input_base() const { return 2; } |
| 41723 | public: |
| 41724 | vmul16I_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41725 | virtual uint size_of() const { return sizeof(vmul16I_memNode); } |
| 41726 | static const Pipeline *pipeline_class(); |
| 41727 | virtual const Pipeline *pipeline() const; |
| 41728 | virtual const MachOper *memory_operand() const; |
| 41729 | #ifndef PRODUCT |
| 41730 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41731 | virtual const char *Name() const { return "vmul16I_mem";} |
| 41732 | #endif |
| 41733 | }; |
| 41734 | |
| 41735 | class vmul16I_mem_0Node : public MachTypeNode { |
| 41736 | private: |
| 41737 | MachOper *_opnd_array[3]; |
| 41738 | public: |
| 41739 | MachOper *opnd_array(uint operand_index) const { |
| 41740 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41741 | return _opnd_array[operand_index]; |
| 41742 | } |
| 41743 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41744 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41745 | _opnd_array[operand_index] = operand; |
| 41746 | } |
| 41747 | private: |
| 41748 | virtual const RegMask &out_RegMask() const; |
| 41749 | virtual uint rule() const { return vmul16I_mem_0_rule; } |
| 41750 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41751 | virtual int ideal_Opcode() const { return Op_MulVI; } |
| 41752 | virtual int reloc() const; |
| 41753 | virtual uint oper_input_base() const { return 2; } |
| 41754 | public: |
| 41755 | vmul16I_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41756 | virtual uint size_of() const { return sizeof(vmul16I_mem_0Node); } |
| 41757 | static const Pipeline *pipeline_class(); |
| 41758 | virtual const Pipeline *pipeline() const; |
| 41759 | virtual const MachOper *memory_operand() const; |
| 41760 | #ifndef PRODUCT |
| 41761 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41762 | virtual const char *Name() const { return "vmul16I_mem_0";} |
| 41763 | #endif |
| 41764 | }; |
| 41765 | |
| 41766 | class vmul2FNode : public MachTypeNode { |
| 41767 | private: |
| 41768 | MachOper *_opnd_array[3]; |
| 41769 | public: |
| 41770 | MachOper *opnd_array(uint operand_index) const { |
| 41771 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41772 | return _opnd_array[operand_index]; |
| 41773 | } |
| 41774 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41775 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41776 | _opnd_array[operand_index] = operand; |
| 41777 | } |
| 41778 | private: |
| 41779 | virtual const RegMask &out_RegMask() const; |
| 41780 | virtual uint rule() const { return vmul2F_rule; } |
| 41781 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41782 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41783 | virtual uint two_adr() const { return oper_input_base(); } |
| 41784 | virtual uint oper_input_base() const { return 1; } |
| 41785 | public: |
| 41786 | vmul2FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41787 | virtual uint size_of() const { return sizeof(vmul2FNode); } |
| 41788 | static const Pipeline *pipeline_class(); |
| 41789 | virtual const Pipeline *pipeline() const; |
| 41790 | #ifndef PRODUCT |
| 41791 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41792 | virtual const char *Name() const { return "vmul2F";} |
| 41793 | #endif |
| 41794 | }; |
| 41795 | |
| 41796 | class vmul2F_regNode : public MachTypeNode { |
| 41797 | private: |
| 41798 | MachOper *_opnd_array[3]; |
| 41799 | public: |
| 41800 | MachOper *opnd_array(uint operand_index) const { |
| 41801 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41802 | return _opnd_array[operand_index]; |
| 41803 | } |
| 41804 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41805 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41806 | _opnd_array[operand_index] = operand; |
| 41807 | } |
| 41808 | private: |
| 41809 | virtual const RegMask &out_RegMask() const; |
| 41810 | virtual uint rule() const { return vmul2F_reg_rule; } |
| 41811 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41812 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41813 | virtual uint oper_input_base() const { return 1; } |
| 41814 | public: |
| 41815 | vmul2F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41816 | virtual uint size_of() const { return sizeof(vmul2F_regNode); } |
| 41817 | static const Pipeline *pipeline_class(); |
| 41818 | virtual const Pipeline *pipeline() const; |
| 41819 | #ifndef PRODUCT |
| 41820 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41821 | virtual const char *Name() const { return "vmul2F_reg";} |
| 41822 | #endif |
| 41823 | }; |
| 41824 | |
| 41825 | class vmul2F_memNode : public MachTypeNode { |
| 41826 | private: |
| 41827 | MachOper *_opnd_array[3]; |
| 41828 | public: |
| 41829 | MachOper *opnd_array(uint operand_index) const { |
| 41830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41831 | return _opnd_array[operand_index]; |
| 41832 | } |
| 41833 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41834 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41835 | _opnd_array[operand_index] = operand; |
| 41836 | } |
| 41837 | private: |
| 41838 | virtual const RegMask &out_RegMask() const; |
| 41839 | virtual uint rule() const { return vmul2F_mem_rule; } |
| 41840 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41841 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41842 | virtual int reloc() const; |
| 41843 | virtual uint oper_input_base() const { return 2; } |
| 41844 | public: |
| 41845 | vmul2F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41846 | virtual uint size_of() const { return sizeof(vmul2F_memNode); } |
| 41847 | static const Pipeline *pipeline_class(); |
| 41848 | virtual const Pipeline *pipeline() const; |
| 41849 | virtual const MachOper *memory_operand() const; |
| 41850 | #ifndef PRODUCT |
| 41851 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41852 | virtual const char *Name() const { return "vmul2F_mem";} |
| 41853 | #endif |
| 41854 | }; |
| 41855 | |
| 41856 | class vmul2F_mem_0Node : public MachTypeNode { |
| 41857 | private: |
| 41858 | MachOper *_opnd_array[3]; |
| 41859 | public: |
| 41860 | MachOper *opnd_array(uint operand_index) const { |
| 41861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41862 | return _opnd_array[operand_index]; |
| 41863 | } |
| 41864 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41865 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41866 | _opnd_array[operand_index] = operand; |
| 41867 | } |
| 41868 | private: |
| 41869 | virtual const RegMask &out_RegMask() const; |
| 41870 | virtual uint rule() const { return vmul2F_mem_0_rule; } |
| 41871 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41872 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41873 | virtual int reloc() const; |
| 41874 | virtual uint oper_input_base() const { return 2; } |
| 41875 | public: |
| 41876 | vmul2F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41877 | virtual uint size_of() const { return sizeof(vmul2F_mem_0Node); } |
| 41878 | static const Pipeline *pipeline_class(); |
| 41879 | virtual const Pipeline *pipeline() const; |
| 41880 | virtual const MachOper *memory_operand() const; |
| 41881 | #ifndef PRODUCT |
| 41882 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41883 | virtual const char *Name() const { return "vmul2F_mem_0";} |
| 41884 | #endif |
| 41885 | }; |
| 41886 | |
| 41887 | class vmul4FNode : public MachTypeNode { |
| 41888 | private: |
| 41889 | MachOper *_opnd_array[3]; |
| 41890 | public: |
| 41891 | MachOper *opnd_array(uint operand_index) const { |
| 41892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41893 | return _opnd_array[operand_index]; |
| 41894 | } |
| 41895 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41896 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41897 | _opnd_array[operand_index] = operand; |
| 41898 | } |
| 41899 | private: |
| 41900 | virtual const RegMask &out_RegMask() const; |
| 41901 | virtual uint rule() const { return vmul4F_rule; } |
| 41902 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41903 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41904 | virtual uint two_adr() const { return oper_input_base(); } |
| 41905 | virtual uint oper_input_base() const { return 1; } |
| 41906 | public: |
| 41907 | vmul4FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41908 | virtual uint size_of() const { return sizeof(vmul4FNode); } |
| 41909 | static const Pipeline *pipeline_class(); |
| 41910 | virtual const Pipeline *pipeline() const; |
| 41911 | #ifndef PRODUCT |
| 41912 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41913 | virtual const char *Name() const { return "vmul4F";} |
| 41914 | #endif |
| 41915 | }; |
| 41916 | |
| 41917 | class vmul4F_regNode : public MachTypeNode { |
| 41918 | private: |
| 41919 | MachOper *_opnd_array[3]; |
| 41920 | public: |
| 41921 | MachOper *opnd_array(uint operand_index) const { |
| 41922 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41923 | return _opnd_array[operand_index]; |
| 41924 | } |
| 41925 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41926 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41927 | _opnd_array[operand_index] = operand; |
| 41928 | } |
| 41929 | private: |
| 41930 | virtual const RegMask &out_RegMask() const; |
| 41931 | virtual uint rule() const { return vmul4F_reg_rule; } |
| 41932 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41933 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41934 | virtual uint oper_input_base() const { return 1; } |
| 41935 | public: |
| 41936 | vmul4F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 41937 | virtual uint size_of() const { return sizeof(vmul4F_regNode); } |
| 41938 | static const Pipeline *pipeline_class(); |
| 41939 | virtual const Pipeline *pipeline() const; |
| 41940 | #ifndef PRODUCT |
| 41941 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41942 | virtual const char *Name() const { return "vmul4F_reg";} |
| 41943 | #endif |
| 41944 | }; |
| 41945 | |
| 41946 | class vmul4F_memNode : public MachTypeNode { |
| 41947 | private: |
| 41948 | MachOper *_opnd_array[3]; |
| 41949 | public: |
| 41950 | MachOper *opnd_array(uint operand_index) const { |
| 41951 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41952 | return _opnd_array[operand_index]; |
| 41953 | } |
| 41954 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41955 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41956 | _opnd_array[operand_index] = operand; |
| 41957 | } |
| 41958 | private: |
| 41959 | virtual const RegMask &out_RegMask() const; |
| 41960 | virtual uint rule() const { return vmul4F_mem_rule; } |
| 41961 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41962 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41963 | virtual int reloc() const; |
| 41964 | virtual uint oper_input_base() const { return 2; } |
| 41965 | public: |
| 41966 | vmul4F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41967 | virtual uint size_of() const { return sizeof(vmul4F_memNode); } |
| 41968 | static const Pipeline *pipeline_class(); |
| 41969 | virtual const Pipeline *pipeline() const; |
| 41970 | virtual const MachOper *memory_operand() const; |
| 41971 | #ifndef PRODUCT |
| 41972 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 41973 | virtual const char *Name() const { return "vmul4F_mem";} |
| 41974 | #endif |
| 41975 | }; |
| 41976 | |
| 41977 | class vmul4F_mem_0Node : public MachTypeNode { |
| 41978 | private: |
| 41979 | MachOper *_opnd_array[3]; |
| 41980 | public: |
| 41981 | MachOper *opnd_array(uint operand_index) const { |
| 41982 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41983 | return _opnd_array[operand_index]; |
| 41984 | } |
| 41985 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 41986 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 41987 | _opnd_array[operand_index] = operand; |
| 41988 | } |
| 41989 | private: |
| 41990 | virtual const RegMask &out_RegMask() const; |
| 41991 | virtual uint rule() const { return vmul4F_mem_0_rule; } |
| 41992 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 41993 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 41994 | virtual int reloc() const; |
| 41995 | virtual uint oper_input_base() const { return 2; } |
| 41996 | public: |
| 41997 | vmul4F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 41998 | virtual uint size_of() const { return sizeof(vmul4F_mem_0Node); } |
| 41999 | static const Pipeline *pipeline_class(); |
| 42000 | virtual const Pipeline *pipeline() const; |
| 42001 | virtual const MachOper *memory_operand() const; |
| 42002 | #ifndef PRODUCT |
| 42003 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42004 | virtual const char *Name() const { return "vmul4F_mem_0";} |
| 42005 | #endif |
| 42006 | }; |
| 42007 | |
| 42008 | class vmul8F_regNode : public MachTypeNode { |
| 42009 | private: |
| 42010 | MachOper *_opnd_array[3]; |
| 42011 | public: |
| 42012 | MachOper *opnd_array(uint operand_index) const { |
| 42013 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42014 | return _opnd_array[operand_index]; |
| 42015 | } |
| 42016 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42017 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42018 | _opnd_array[operand_index] = operand; |
| 42019 | } |
| 42020 | private: |
| 42021 | virtual const RegMask &out_RegMask() const; |
| 42022 | virtual uint rule() const { return vmul8F_reg_rule; } |
| 42023 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42024 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42025 | virtual uint oper_input_base() const { return 1; } |
| 42026 | public: |
| 42027 | vmul8F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42028 | virtual uint size_of() const { return sizeof(vmul8F_regNode); } |
| 42029 | static const Pipeline *pipeline_class(); |
| 42030 | virtual const Pipeline *pipeline() const; |
| 42031 | #ifndef PRODUCT |
| 42032 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42033 | virtual const char *Name() const { return "vmul8F_reg";} |
| 42034 | #endif |
| 42035 | }; |
| 42036 | |
| 42037 | class vmul8F_memNode : public MachTypeNode { |
| 42038 | private: |
| 42039 | MachOper *_opnd_array[3]; |
| 42040 | public: |
| 42041 | MachOper *opnd_array(uint operand_index) const { |
| 42042 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42043 | return _opnd_array[operand_index]; |
| 42044 | } |
| 42045 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42046 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42047 | _opnd_array[operand_index] = operand; |
| 42048 | } |
| 42049 | private: |
| 42050 | virtual const RegMask &out_RegMask() const; |
| 42051 | virtual uint rule() const { return vmul8F_mem_rule; } |
| 42052 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42053 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42054 | virtual int reloc() const; |
| 42055 | virtual uint oper_input_base() const { return 2; } |
| 42056 | public: |
| 42057 | vmul8F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42058 | virtual uint size_of() const { return sizeof(vmul8F_memNode); } |
| 42059 | static const Pipeline *pipeline_class(); |
| 42060 | virtual const Pipeline *pipeline() const; |
| 42061 | virtual const MachOper *memory_operand() const; |
| 42062 | #ifndef PRODUCT |
| 42063 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42064 | virtual const char *Name() const { return "vmul8F_mem";} |
| 42065 | #endif |
| 42066 | }; |
| 42067 | |
| 42068 | class vmul8F_mem_0Node : public MachTypeNode { |
| 42069 | private: |
| 42070 | MachOper *_opnd_array[3]; |
| 42071 | public: |
| 42072 | MachOper *opnd_array(uint operand_index) const { |
| 42073 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42074 | return _opnd_array[operand_index]; |
| 42075 | } |
| 42076 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42077 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42078 | _opnd_array[operand_index] = operand; |
| 42079 | } |
| 42080 | private: |
| 42081 | virtual const RegMask &out_RegMask() const; |
| 42082 | virtual uint rule() const { return vmul8F_mem_0_rule; } |
| 42083 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42084 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42085 | virtual int reloc() const; |
| 42086 | virtual uint oper_input_base() const { return 2; } |
| 42087 | public: |
| 42088 | vmul8F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42089 | virtual uint size_of() const { return sizeof(vmul8F_mem_0Node); } |
| 42090 | static const Pipeline *pipeline_class(); |
| 42091 | virtual const Pipeline *pipeline() const; |
| 42092 | virtual const MachOper *memory_operand() const; |
| 42093 | #ifndef PRODUCT |
| 42094 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42095 | virtual const char *Name() const { return "vmul8F_mem_0";} |
| 42096 | #endif |
| 42097 | }; |
| 42098 | |
| 42099 | class vmul16F_regNode : public MachTypeNode { |
| 42100 | private: |
| 42101 | MachOper *_opnd_array[3]; |
| 42102 | public: |
| 42103 | MachOper *opnd_array(uint operand_index) const { |
| 42104 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42105 | return _opnd_array[operand_index]; |
| 42106 | } |
| 42107 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42108 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42109 | _opnd_array[operand_index] = operand; |
| 42110 | } |
| 42111 | private: |
| 42112 | virtual const RegMask &out_RegMask() const; |
| 42113 | virtual uint rule() const { return vmul16F_reg_rule; } |
| 42114 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42115 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42116 | virtual uint oper_input_base() const { return 1; } |
| 42117 | public: |
| 42118 | vmul16F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42119 | virtual uint size_of() const { return sizeof(vmul16F_regNode); } |
| 42120 | static const Pipeline *pipeline_class(); |
| 42121 | virtual const Pipeline *pipeline() const; |
| 42122 | #ifndef PRODUCT |
| 42123 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42124 | virtual const char *Name() const { return "vmul16F_reg";} |
| 42125 | #endif |
| 42126 | }; |
| 42127 | |
| 42128 | class vmul16F_memNode : public MachTypeNode { |
| 42129 | private: |
| 42130 | MachOper *_opnd_array[3]; |
| 42131 | public: |
| 42132 | MachOper *opnd_array(uint operand_index) const { |
| 42133 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42134 | return _opnd_array[operand_index]; |
| 42135 | } |
| 42136 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42137 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42138 | _opnd_array[operand_index] = operand; |
| 42139 | } |
| 42140 | private: |
| 42141 | virtual const RegMask &out_RegMask() const; |
| 42142 | virtual uint rule() const { return vmul16F_mem_rule; } |
| 42143 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42144 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42145 | virtual int reloc() const; |
| 42146 | virtual uint oper_input_base() const { return 2; } |
| 42147 | public: |
| 42148 | vmul16F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42149 | virtual uint size_of() const { return sizeof(vmul16F_memNode); } |
| 42150 | static const Pipeline *pipeline_class(); |
| 42151 | virtual const Pipeline *pipeline() const; |
| 42152 | virtual const MachOper *memory_operand() const; |
| 42153 | #ifndef PRODUCT |
| 42154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42155 | virtual const char *Name() const { return "vmul16F_mem";} |
| 42156 | #endif |
| 42157 | }; |
| 42158 | |
| 42159 | class vmul16F_mem_0Node : public MachTypeNode { |
| 42160 | private: |
| 42161 | MachOper *_opnd_array[3]; |
| 42162 | public: |
| 42163 | MachOper *opnd_array(uint operand_index) const { |
| 42164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42165 | return _opnd_array[operand_index]; |
| 42166 | } |
| 42167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42169 | _opnd_array[operand_index] = operand; |
| 42170 | } |
| 42171 | private: |
| 42172 | virtual const RegMask &out_RegMask() const; |
| 42173 | virtual uint rule() const { return vmul16F_mem_0_rule; } |
| 42174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42175 | virtual int ideal_Opcode() const { return Op_MulVF; } |
| 42176 | virtual int reloc() const; |
| 42177 | virtual uint oper_input_base() const { return 2; } |
| 42178 | public: |
| 42179 | vmul16F_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42180 | virtual uint size_of() const { return sizeof(vmul16F_mem_0Node); } |
| 42181 | static const Pipeline *pipeline_class(); |
| 42182 | virtual const Pipeline *pipeline() const; |
| 42183 | virtual const MachOper *memory_operand() const; |
| 42184 | #ifndef PRODUCT |
| 42185 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42186 | virtual const char *Name() const { return "vmul16F_mem_0";} |
| 42187 | #endif |
| 42188 | }; |
| 42189 | |
| 42190 | class vmul2DNode : public MachTypeNode { |
| 42191 | private: |
| 42192 | MachOper *_opnd_array[3]; |
| 42193 | public: |
| 42194 | MachOper *opnd_array(uint operand_index) const { |
| 42195 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42196 | return _opnd_array[operand_index]; |
| 42197 | } |
| 42198 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42199 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42200 | _opnd_array[operand_index] = operand; |
| 42201 | } |
| 42202 | private: |
| 42203 | virtual const RegMask &out_RegMask() const; |
| 42204 | virtual uint rule() const { return vmul2D_rule; } |
| 42205 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42206 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42207 | virtual uint two_adr() const { return oper_input_base(); } |
| 42208 | virtual uint oper_input_base() const { return 1; } |
| 42209 | public: |
| 42210 | vmul2DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42211 | virtual uint size_of() const { return sizeof(vmul2DNode); } |
| 42212 | static const Pipeline *pipeline_class(); |
| 42213 | virtual const Pipeline *pipeline() const; |
| 42214 | #ifndef PRODUCT |
| 42215 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42216 | virtual const char *Name() const { return "vmul2D";} |
| 42217 | #endif |
| 42218 | }; |
| 42219 | |
| 42220 | class vmul2D_regNode : public MachTypeNode { |
| 42221 | private: |
| 42222 | MachOper *_opnd_array[3]; |
| 42223 | public: |
| 42224 | MachOper *opnd_array(uint operand_index) const { |
| 42225 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42226 | return _opnd_array[operand_index]; |
| 42227 | } |
| 42228 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42229 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42230 | _opnd_array[operand_index] = operand; |
| 42231 | } |
| 42232 | private: |
| 42233 | virtual const RegMask &out_RegMask() const; |
| 42234 | virtual uint rule() const { return vmul2D_reg_rule; } |
| 42235 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42236 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42237 | virtual uint oper_input_base() const { return 1; } |
| 42238 | public: |
| 42239 | vmul2D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42240 | virtual uint size_of() const { return sizeof(vmul2D_regNode); } |
| 42241 | static const Pipeline *pipeline_class(); |
| 42242 | virtual const Pipeline *pipeline() const; |
| 42243 | #ifndef PRODUCT |
| 42244 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42245 | virtual const char *Name() const { return "vmul2D_reg";} |
| 42246 | #endif |
| 42247 | }; |
| 42248 | |
| 42249 | class vmul2D_memNode : public MachTypeNode { |
| 42250 | private: |
| 42251 | MachOper *_opnd_array[3]; |
| 42252 | public: |
| 42253 | MachOper *opnd_array(uint operand_index) const { |
| 42254 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42255 | return _opnd_array[operand_index]; |
| 42256 | } |
| 42257 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42258 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42259 | _opnd_array[operand_index] = operand; |
| 42260 | } |
| 42261 | private: |
| 42262 | virtual const RegMask &out_RegMask() const; |
| 42263 | virtual uint rule() const { return vmul2D_mem_rule; } |
| 42264 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42265 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42266 | virtual int reloc() const; |
| 42267 | virtual uint oper_input_base() const { return 2; } |
| 42268 | public: |
| 42269 | vmul2D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42270 | virtual uint size_of() const { return sizeof(vmul2D_memNode); } |
| 42271 | static const Pipeline *pipeline_class(); |
| 42272 | virtual const Pipeline *pipeline() const; |
| 42273 | virtual const MachOper *memory_operand() const; |
| 42274 | #ifndef PRODUCT |
| 42275 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42276 | virtual const char *Name() const { return "vmul2D_mem";} |
| 42277 | #endif |
| 42278 | }; |
| 42279 | |
| 42280 | class vmul2D_mem_0Node : public MachTypeNode { |
| 42281 | private: |
| 42282 | MachOper *_opnd_array[3]; |
| 42283 | public: |
| 42284 | MachOper *opnd_array(uint operand_index) const { |
| 42285 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42286 | return _opnd_array[operand_index]; |
| 42287 | } |
| 42288 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42289 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42290 | _opnd_array[operand_index] = operand; |
| 42291 | } |
| 42292 | private: |
| 42293 | virtual const RegMask &out_RegMask() const; |
| 42294 | virtual uint rule() const { return vmul2D_mem_0_rule; } |
| 42295 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42296 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42297 | virtual int reloc() const; |
| 42298 | virtual uint oper_input_base() const { return 2; } |
| 42299 | public: |
| 42300 | vmul2D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42301 | virtual uint size_of() const { return sizeof(vmul2D_mem_0Node); } |
| 42302 | static const Pipeline *pipeline_class(); |
| 42303 | virtual const Pipeline *pipeline() const; |
| 42304 | virtual const MachOper *memory_operand() const; |
| 42305 | #ifndef PRODUCT |
| 42306 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42307 | virtual const char *Name() const { return "vmul2D_mem_0";} |
| 42308 | #endif |
| 42309 | }; |
| 42310 | |
| 42311 | class vmul4D_regNode : public MachTypeNode { |
| 42312 | private: |
| 42313 | MachOper *_opnd_array[3]; |
| 42314 | public: |
| 42315 | MachOper *opnd_array(uint operand_index) const { |
| 42316 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42317 | return _opnd_array[operand_index]; |
| 42318 | } |
| 42319 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42320 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42321 | _opnd_array[operand_index] = operand; |
| 42322 | } |
| 42323 | private: |
| 42324 | virtual const RegMask &out_RegMask() const; |
| 42325 | virtual uint rule() const { return vmul4D_reg_rule; } |
| 42326 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42327 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42328 | virtual uint oper_input_base() const { return 1; } |
| 42329 | public: |
| 42330 | vmul4D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42331 | virtual uint size_of() const { return sizeof(vmul4D_regNode); } |
| 42332 | static const Pipeline *pipeline_class(); |
| 42333 | virtual const Pipeline *pipeline() const; |
| 42334 | #ifndef PRODUCT |
| 42335 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42336 | virtual const char *Name() const { return "vmul4D_reg";} |
| 42337 | #endif |
| 42338 | }; |
| 42339 | |
| 42340 | class vmul4D_memNode : public MachTypeNode { |
| 42341 | private: |
| 42342 | MachOper *_opnd_array[3]; |
| 42343 | public: |
| 42344 | MachOper *opnd_array(uint operand_index) const { |
| 42345 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42346 | return _opnd_array[operand_index]; |
| 42347 | } |
| 42348 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42349 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42350 | _opnd_array[operand_index] = operand; |
| 42351 | } |
| 42352 | private: |
| 42353 | virtual const RegMask &out_RegMask() const; |
| 42354 | virtual uint rule() const { return vmul4D_mem_rule; } |
| 42355 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42356 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42357 | virtual int reloc() const; |
| 42358 | virtual uint oper_input_base() const { return 2; } |
| 42359 | public: |
| 42360 | vmul4D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42361 | virtual uint size_of() const { return sizeof(vmul4D_memNode); } |
| 42362 | static const Pipeline *pipeline_class(); |
| 42363 | virtual const Pipeline *pipeline() const; |
| 42364 | virtual const MachOper *memory_operand() const; |
| 42365 | #ifndef PRODUCT |
| 42366 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42367 | virtual const char *Name() const { return "vmul4D_mem";} |
| 42368 | #endif |
| 42369 | }; |
| 42370 | |
| 42371 | class vmul4D_mem_0Node : public MachTypeNode { |
| 42372 | private: |
| 42373 | MachOper *_opnd_array[3]; |
| 42374 | public: |
| 42375 | MachOper *opnd_array(uint operand_index) const { |
| 42376 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42377 | return _opnd_array[operand_index]; |
| 42378 | } |
| 42379 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42380 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42381 | _opnd_array[operand_index] = operand; |
| 42382 | } |
| 42383 | private: |
| 42384 | virtual const RegMask &out_RegMask() const; |
| 42385 | virtual uint rule() const { return vmul4D_mem_0_rule; } |
| 42386 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42387 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42388 | virtual int reloc() const; |
| 42389 | virtual uint oper_input_base() const { return 2; } |
| 42390 | public: |
| 42391 | vmul4D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42392 | virtual uint size_of() const { return sizeof(vmul4D_mem_0Node); } |
| 42393 | static const Pipeline *pipeline_class(); |
| 42394 | virtual const Pipeline *pipeline() const; |
| 42395 | virtual const MachOper *memory_operand() const; |
| 42396 | #ifndef PRODUCT |
| 42397 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42398 | virtual const char *Name() const { return "vmul4D_mem_0";} |
| 42399 | #endif |
| 42400 | }; |
| 42401 | |
| 42402 | class vmul8D_regNode : public MachTypeNode { |
| 42403 | private: |
| 42404 | MachOper *_opnd_array[3]; |
| 42405 | public: |
| 42406 | MachOper *opnd_array(uint operand_index) const { |
| 42407 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42408 | return _opnd_array[operand_index]; |
| 42409 | } |
| 42410 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42411 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42412 | _opnd_array[operand_index] = operand; |
| 42413 | } |
| 42414 | private: |
| 42415 | virtual const RegMask &out_RegMask() const; |
| 42416 | virtual uint rule() const { return vmul8D_reg_rule; } |
| 42417 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42418 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42419 | virtual uint oper_input_base() const { return 1; } |
| 42420 | public: |
| 42421 | vmul8D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42422 | virtual uint size_of() const { return sizeof(vmul8D_regNode); } |
| 42423 | static const Pipeline *pipeline_class(); |
| 42424 | virtual const Pipeline *pipeline() const; |
| 42425 | #ifndef PRODUCT |
| 42426 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42427 | virtual const char *Name() const { return "vmul8D_reg";} |
| 42428 | #endif |
| 42429 | }; |
| 42430 | |
| 42431 | class vmul8D_memNode : public MachTypeNode { |
| 42432 | private: |
| 42433 | MachOper *_opnd_array[3]; |
| 42434 | public: |
| 42435 | MachOper *opnd_array(uint operand_index) const { |
| 42436 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42437 | return _opnd_array[operand_index]; |
| 42438 | } |
| 42439 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42440 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42441 | _opnd_array[operand_index] = operand; |
| 42442 | } |
| 42443 | private: |
| 42444 | virtual const RegMask &out_RegMask() const; |
| 42445 | virtual uint rule() const { return vmul8D_mem_rule; } |
| 42446 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42447 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42448 | virtual int reloc() const; |
| 42449 | virtual uint oper_input_base() const { return 2; } |
| 42450 | public: |
| 42451 | vmul8D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42452 | virtual uint size_of() const { return sizeof(vmul8D_memNode); } |
| 42453 | static const Pipeline *pipeline_class(); |
| 42454 | virtual const Pipeline *pipeline() const; |
| 42455 | virtual const MachOper *memory_operand() const; |
| 42456 | #ifndef PRODUCT |
| 42457 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42458 | virtual const char *Name() const { return "vmul8D_mem";} |
| 42459 | #endif |
| 42460 | }; |
| 42461 | |
| 42462 | class vmul8D_mem_0Node : public MachTypeNode { |
| 42463 | private: |
| 42464 | MachOper *_opnd_array[3]; |
| 42465 | public: |
| 42466 | MachOper *opnd_array(uint operand_index) const { |
| 42467 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42468 | return _opnd_array[operand_index]; |
| 42469 | } |
| 42470 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42471 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42472 | _opnd_array[operand_index] = operand; |
| 42473 | } |
| 42474 | private: |
| 42475 | virtual const RegMask &out_RegMask() const; |
| 42476 | virtual uint rule() const { return vmul8D_mem_0_rule; } |
| 42477 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42478 | virtual int ideal_Opcode() const { return Op_MulVD; } |
| 42479 | virtual int reloc() const; |
| 42480 | virtual uint oper_input_base() const { return 2; } |
| 42481 | public: |
| 42482 | vmul8D_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42483 | virtual uint size_of() const { return sizeof(vmul8D_mem_0Node); } |
| 42484 | static const Pipeline *pipeline_class(); |
| 42485 | virtual const Pipeline *pipeline() const; |
| 42486 | virtual const MachOper *memory_operand() const; |
| 42487 | #ifndef PRODUCT |
| 42488 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42489 | virtual const char *Name() const { return "vmul8D_mem_0";} |
| 42490 | #endif |
| 42491 | }; |
| 42492 | |
| 42493 | class vcmov8F_regNode : public MachTypeNode { |
| 42494 | private: |
| 42495 | MachOper *_opnd_array[6]; |
| 42496 | public: |
| 42497 | MachOper *opnd_array(uint operand_index) const { |
| 42498 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42499 | return _opnd_array[operand_index]; |
| 42500 | } |
| 42501 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42502 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42503 | _opnd_array[operand_index] = operand; |
| 42504 | } |
| 42505 | private: |
| 42506 | virtual const RegMask &out_RegMask() const; |
| 42507 | virtual uint rule() const { return vcmov8F_reg_rule; } |
| 42508 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42509 | virtual int ideal_Opcode() const { return Op_CMoveVF; } |
| 42510 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges() + opnd_array(3)->num_edges() + opnd_array(4)->num_edges(); } |
| 42511 | virtual uint oper_input_base() const { return 1; } |
| 42512 | public: |
| 42513 | vcmov8F_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 42514 | virtual uint size_of() const { return sizeof(vcmov8F_regNode); } |
| 42515 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 42516 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 42517 | static const Pipeline *pipeline_class(); |
| 42518 | virtual const Pipeline *pipeline() const; |
| 42519 | #ifndef PRODUCT |
| 42520 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42521 | virtual const char *Name() const { return "vcmov8F_reg";} |
| 42522 | #endif |
| 42523 | }; |
| 42524 | |
| 42525 | class vcmov4D_regNode : public MachTypeNode { |
| 42526 | private: |
| 42527 | MachOper *_opnd_array[6]; |
| 42528 | public: |
| 42529 | MachOper *opnd_array(uint operand_index) const { |
| 42530 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42531 | return _opnd_array[operand_index]; |
| 42532 | } |
| 42533 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42534 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42535 | _opnd_array[operand_index] = operand; |
| 42536 | } |
| 42537 | private: |
| 42538 | virtual const RegMask &out_RegMask() const; |
| 42539 | virtual uint rule() const { return vcmov4D_reg_rule; } |
| 42540 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42541 | virtual int ideal_Opcode() const { return Op_CMoveVD; } |
| 42542 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges() + opnd_array(3)->num_edges() + opnd_array(4)->num_edges(); } |
| 42543 | virtual uint oper_input_base() const { return 1; } |
| 42544 | public: |
| 42545 | vcmov4D_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 42546 | virtual uint size_of() const { return sizeof(vcmov4D_regNode); } |
| 42547 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 42548 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 42549 | static const Pipeline *pipeline_class(); |
| 42550 | virtual const Pipeline *pipeline() const; |
| 42551 | #ifndef PRODUCT |
| 42552 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42553 | virtual const char *Name() const { return "vcmov4D_reg";} |
| 42554 | #endif |
| 42555 | }; |
| 42556 | |
| 42557 | class vdiv2FNode : public MachTypeNode { |
| 42558 | private: |
| 42559 | MachOper *_opnd_array[3]; |
| 42560 | public: |
| 42561 | MachOper *opnd_array(uint operand_index) const { |
| 42562 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42563 | return _opnd_array[operand_index]; |
| 42564 | } |
| 42565 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42566 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42567 | _opnd_array[operand_index] = operand; |
| 42568 | } |
| 42569 | private: |
| 42570 | virtual const RegMask &out_RegMask() const; |
| 42571 | virtual uint rule() const { return vdiv2F_rule; } |
| 42572 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42573 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42574 | virtual uint two_adr() const { return oper_input_base(); } |
| 42575 | virtual uint oper_input_base() const { return 1; } |
| 42576 | public: |
| 42577 | vdiv2FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42578 | virtual uint size_of() const { return sizeof(vdiv2FNode); } |
| 42579 | static const Pipeline *pipeline_class(); |
| 42580 | virtual const Pipeline *pipeline() const; |
| 42581 | #ifndef PRODUCT |
| 42582 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42583 | virtual const char *Name() const { return "vdiv2F";} |
| 42584 | #endif |
| 42585 | }; |
| 42586 | |
| 42587 | class vdiv2F_regNode : public MachTypeNode { |
| 42588 | private: |
| 42589 | MachOper *_opnd_array[3]; |
| 42590 | public: |
| 42591 | MachOper *opnd_array(uint operand_index) const { |
| 42592 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42593 | return _opnd_array[operand_index]; |
| 42594 | } |
| 42595 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42596 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42597 | _opnd_array[operand_index] = operand; |
| 42598 | } |
| 42599 | private: |
| 42600 | virtual const RegMask &out_RegMask() const; |
| 42601 | virtual uint rule() const { return vdiv2F_reg_rule; } |
| 42602 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42603 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42604 | virtual uint oper_input_base() const { return 1; } |
| 42605 | public: |
| 42606 | vdiv2F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42607 | virtual uint size_of() const { return sizeof(vdiv2F_regNode); } |
| 42608 | static const Pipeline *pipeline_class(); |
| 42609 | virtual const Pipeline *pipeline() const; |
| 42610 | #ifndef PRODUCT |
| 42611 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42612 | virtual const char *Name() const { return "vdiv2F_reg";} |
| 42613 | #endif |
| 42614 | }; |
| 42615 | |
| 42616 | class vdiv2F_memNode : public MachTypeNode { |
| 42617 | private: |
| 42618 | MachOper *_opnd_array[3]; |
| 42619 | public: |
| 42620 | MachOper *opnd_array(uint operand_index) const { |
| 42621 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42622 | return _opnd_array[operand_index]; |
| 42623 | } |
| 42624 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42625 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42626 | _opnd_array[operand_index] = operand; |
| 42627 | } |
| 42628 | private: |
| 42629 | virtual const RegMask &out_RegMask() const; |
| 42630 | virtual uint rule() const { return vdiv2F_mem_rule; } |
| 42631 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42632 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42633 | virtual int reloc() const; |
| 42634 | virtual uint oper_input_base() const { return 2; } |
| 42635 | public: |
| 42636 | vdiv2F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42637 | virtual uint size_of() const { return sizeof(vdiv2F_memNode); } |
| 42638 | static const Pipeline *pipeline_class(); |
| 42639 | virtual const Pipeline *pipeline() const; |
| 42640 | virtual const MachOper *memory_operand() const; |
| 42641 | #ifndef PRODUCT |
| 42642 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42643 | virtual const char *Name() const { return "vdiv2F_mem";} |
| 42644 | #endif |
| 42645 | }; |
| 42646 | |
| 42647 | class vdiv4FNode : public MachTypeNode { |
| 42648 | private: |
| 42649 | MachOper *_opnd_array[3]; |
| 42650 | public: |
| 42651 | MachOper *opnd_array(uint operand_index) const { |
| 42652 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42653 | return _opnd_array[operand_index]; |
| 42654 | } |
| 42655 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42656 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42657 | _opnd_array[operand_index] = operand; |
| 42658 | } |
| 42659 | private: |
| 42660 | virtual const RegMask &out_RegMask() const; |
| 42661 | virtual uint rule() const { return vdiv4F_rule; } |
| 42662 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42663 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42664 | virtual uint two_adr() const { return oper_input_base(); } |
| 42665 | virtual uint oper_input_base() const { return 1; } |
| 42666 | public: |
| 42667 | vdiv4FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42668 | virtual uint size_of() const { return sizeof(vdiv4FNode); } |
| 42669 | static const Pipeline *pipeline_class(); |
| 42670 | virtual const Pipeline *pipeline() const; |
| 42671 | #ifndef PRODUCT |
| 42672 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42673 | virtual const char *Name() const { return "vdiv4F";} |
| 42674 | #endif |
| 42675 | }; |
| 42676 | |
| 42677 | class vdiv4F_regNode : public MachTypeNode { |
| 42678 | private: |
| 42679 | MachOper *_opnd_array[3]; |
| 42680 | public: |
| 42681 | MachOper *opnd_array(uint operand_index) const { |
| 42682 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42683 | return _opnd_array[operand_index]; |
| 42684 | } |
| 42685 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42686 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42687 | _opnd_array[operand_index] = operand; |
| 42688 | } |
| 42689 | private: |
| 42690 | virtual const RegMask &out_RegMask() const; |
| 42691 | virtual uint rule() const { return vdiv4F_reg_rule; } |
| 42692 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42693 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42694 | virtual uint oper_input_base() const { return 1; } |
| 42695 | public: |
| 42696 | vdiv4F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42697 | virtual uint size_of() const { return sizeof(vdiv4F_regNode); } |
| 42698 | static const Pipeline *pipeline_class(); |
| 42699 | virtual const Pipeline *pipeline() const; |
| 42700 | #ifndef PRODUCT |
| 42701 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42702 | virtual const char *Name() const { return "vdiv4F_reg";} |
| 42703 | #endif |
| 42704 | }; |
| 42705 | |
| 42706 | class vdiv4F_memNode : public MachTypeNode { |
| 42707 | private: |
| 42708 | MachOper *_opnd_array[3]; |
| 42709 | public: |
| 42710 | MachOper *opnd_array(uint operand_index) const { |
| 42711 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42712 | return _opnd_array[operand_index]; |
| 42713 | } |
| 42714 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42715 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42716 | _opnd_array[operand_index] = operand; |
| 42717 | } |
| 42718 | private: |
| 42719 | virtual const RegMask &out_RegMask() const; |
| 42720 | virtual uint rule() const { return vdiv4F_mem_rule; } |
| 42721 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42722 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42723 | virtual int reloc() const; |
| 42724 | virtual uint oper_input_base() const { return 2; } |
| 42725 | public: |
| 42726 | vdiv4F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42727 | virtual uint size_of() const { return sizeof(vdiv4F_memNode); } |
| 42728 | static const Pipeline *pipeline_class(); |
| 42729 | virtual const Pipeline *pipeline() const; |
| 42730 | virtual const MachOper *memory_operand() const; |
| 42731 | #ifndef PRODUCT |
| 42732 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42733 | virtual const char *Name() const { return "vdiv4F_mem";} |
| 42734 | #endif |
| 42735 | }; |
| 42736 | |
| 42737 | class vdiv8F_regNode : public MachTypeNode { |
| 42738 | private: |
| 42739 | MachOper *_opnd_array[3]; |
| 42740 | public: |
| 42741 | MachOper *opnd_array(uint operand_index) const { |
| 42742 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42743 | return _opnd_array[operand_index]; |
| 42744 | } |
| 42745 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42746 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42747 | _opnd_array[operand_index] = operand; |
| 42748 | } |
| 42749 | private: |
| 42750 | virtual const RegMask &out_RegMask() const; |
| 42751 | virtual uint rule() const { return vdiv8F_reg_rule; } |
| 42752 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42753 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42754 | virtual uint oper_input_base() const { return 1; } |
| 42755 | public: |
| 42756 | vdiv8F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42757 | virtual uint size_of() const { return sizeof(vdiv8F_regNode); } |
| 42758 | static const Pipeline *pipeline_class(); |
| 42759 | virtual const Pipeline *pipeline() const; |
| 42760 | #ifndef PRODUCT |
| 42761 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42762 | virtual const char *Name() const { return "vdiv8F_reg";} |
| 42763 | #endif |
| 42764 | }; |
| 42765 | |
| 42766 | class vdiv8F_memNode : public MachTypeNode { |
| 42767 | private: |
| 42768 | MachOper *_opnd_array[3]; |
| 42769 | public: |
| 42770 | MachOper *opnd_array(uint operand_index) const { |
| 42771 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42772 | return _opnd_array[operand_index]; |
| 42773 | } |
| 42774 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42775 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42776 | _opnd_array[operand_index] = operand; |
| 42777 | } |
| 42778 | private: |
| 42779 | virtual const RegMask &out_RegMask() const; |
| 42780 | virtual uint rule() const { return vdiv8F_mem_rule; } |
| 42781 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42782 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42783 | virtual int reloc() const; |
| 42784 | virtual uint oper_input_base() const { return 2; } |
| 42785 | public: |
| 42786 | vdiv8F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42787 | virtual uint size_of() const { return sizeof(vdiv8F_memNode); } |
| 42788 | static const Pipeline *pipeline_class(); |
| 42789 | virtual const Pipeline *pipeline() const; |
| 42790 | virtual const MachOper *memory_operand() const; |
| 42791 | #ifndef PRODUCT |
| 42792 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42793 | virtual const char *Name() const { return "vdiv8F_mem";} |
| 42794 | #endif |
| 42795 | }; |
| 42796 | |
| 42797 | class vdiv16F_regNode : public MachTypeNode { |
| 42798 | private: |
| 42799 | MachOper *_opnd_array[3]; |
| 42800 | public: |
| 42801 | MachOper *opnd_array(uint operand_index) const { |
| 42802 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42803 | return _opnd_array[operand_index]; |
| 42804 | } |
| 42805 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42806 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42807 | _opnd_array[operand_index] = operand; |
| 42808 | } |
| 42809 | private: |
| 42810 | virtual const RegMask &out_RegMask() const; |
| 42811 | virtual uint rule() const { return vdiv16F_reg_rule; } |
| 42812 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42813 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42814 | virtual uint oper_input_base() const { return 1; } |
| 42815 | public: |
| 42816 | vdiv16F_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42817 | virtual uint size_of() const { return sizeof(vdiv16F_regNode); } |
| 42818 | static const Pipeline *pipeline_class(); |
| 42819 | virtual const Pipeline *pipeline() const; |
| 42820 | #ifndef PRODUCT |
| 42821 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42822 | virtual const char *Name() const { return "vdiv16F_reg";} |
| 42823 | #endif |
| 42824 | }; |
| 42825 | |
| 42826 | class vdiv16F_memNode : public MachTypeNode { |
| 42827 | private: |
| 42828 | MachOper *_opnd_array[3]; |
| 42829 | public: |
| 42830 | MachOper *opnd_array(uint operand_index) const { |
| 42831 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42832 | return _opnd_array[operand_index]; |
| 42833 | } |
| 42834 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42835 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42836 | _opnd_array[operand_index] = operand; |
| 42837 | } |
| 42838 | private: |
| 42839 | virtual const RegMask &out_RegMask() const; |
| 42840 | virtual uint rule() const { return vdiv16F_mem_rule; } |
| 42841 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42842 | virtual int ideal_Opcode() const { return Op_DivVF; } |
| 42843 | virtual int reloc() const; |
| 42844 | virtual uint oper_input_base() const { return 2; } |
| 42845 | public: |
| 42846 | vdiv16F_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42847 | virtual uint size_of() const { return sizeof(vdiv16F_memNode); } |
| 42848 | static const Pipeline *pipeline_class(); |
| 42849 | virtual const Pipeline *pipeline() const; |
| 42850 | virtual const MachOper *memory_operand() const; |
| 42851 | #ifndef PRODUCT |
| 42852 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42853 | virtual const char *Name() const { return "vdiv16F_mem";} |
| 42854 | #endif |
| 42855 | }; |
| 42856 | |
| 42857 | class vdiv2DNode : public MachTypeNode { |
| 42858 | private: |
| 42859 | MachOper *_opnd_array[3]; |
| 42860 | public: |
| 42861 | MachOper *opnd_array(uint operand_index) const { |
| 42862 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42863 | return _opnd_array[operand_index]; |
| 42864 | } |
| 42865 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42866 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42867 | _opnd_array[operand_index] = operand; |
| 42868 | } |
| 42869 | private: |
| 42870 | virtual const RegMask &out_RegMask() const; |
| 42871 | virtual uint rule() const { return vdiv2D_rule; } |
| 42872 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42873 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 42874 | virtual uint two_adr() const { return oper_input_base(); } |
| 42875 | virtual uint oper_input_base() const { return 1; } |
| 42876 | public: |
| 42877 | vdiv2DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42878 | virtual uint size_of() const { return sizeof(vdiv2DNode); } |
| 42879 | static const Pipeline *pipeline_class(); |
| 42880 | virtual const Pipeline *pipeline() const; |
| 42881 | #ifndef PRODUCT |
| 42882 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42883 | virtual const char *Name() const { return "vdiv2D";} |
| 42884 | #endif |
| 42885 | }; |
| 42886 | |
| 42887 | class vdiv2D_regNode : public MachTypeNode { |
| 42888 | private: |
| 42889 | MachOper *_opnd_array[3]; |
| 42890 | public: |
| 42891 | MachOper *opnd_array(uint operand_index) const { |
| 42892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42893 | return _opnd_array[operand_index]; |
| 42894 | } |
| 42895 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42896 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42897 | _opnd_array[operand_index] = operand; |
| 42898 | } |
| 42899 | private: |
| 42900 | virtual const RegMask &out_RegMask() const; |
| 42901 | virtual uint rule() const { return vdiv2D_reg_rule; } |
| 42902 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42903 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 42904 | virtual uint oper_input_base() const { return 1; } |
| 42905 | public: |
| 42906 | vdiv2D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42907 | virtual uint size_of() const { return sizeof(vdiv2D_regNode); } |
| 42908 | static const Pipeline *pipeline_class(); |
| 42909 | virtual const Pipeline *pipeline() const; |
| 42910 | #ifndef PRODUCT |
| 42911 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42912 | virtual const char *Name() const { return "vdiv2D_reg";} |
| 42913 | #endif |
| 42914 | }; |
| 42915 | |
| 42916 | class vdiv2D_memNode : public MachTypeNode { |
| 42917 | private: |
| 42918 | MachOper *_opnd_array[3]; |
| 42919 | public: |
| 42920 | MachOper *opnd_array(uint operand_index) const { |
| 42921 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42922 | return _opnd_array[operand_index]; |
| 42923 | } |
| 42924 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42925 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42926 | _opnd_array[operand_index] = operand; |
| 42927 | } |
| 42928 | private: |
| 42929 | virtual const RegMask &out_RegMask() const; |
| 42930 | virtual uint rule() const { return vdiv2D_mem_rule; } |
| 42931 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42932 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 42933 | virtual int reloc() const; |
| 42934 | virtual uint oper_input_base() const { return 2; } |
| 42935 | public: |
| 42936 | vdiv2D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42937 | virtual uint size_of() const { return sizeof(vdiv2D_memNode); } |
| 42938 | static const Pipeline *pipeline_class(); |
| 42939 | virtual const Pipeline *pipeline() const; |
| 42940 | virtual const MachOper *memory_operand() const; |
| 42941 | #ifndef PRODUCT |
| 42942 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42943 | virtual const char *Name() const { return "vdiv2D_mem";} |
| 42944 | #endif |
| 42945 | }; |
| 42946 | |
| 42947 | class vdiv4D_regNode : public MachTypeNode { |
| 42948 | private: |
| 42949 | MachOper *_opnd_array[3]; |
| 42950 | public: |
| 42951 | MachOper *opnd_array(uint operand_index) const { |
| 42952 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42953 | return _opnd_array[operand_index]; |
| 42954 | } |
| 42955 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42957 | _opnd_array[operand_index] = operand; |
| 42958 | } |
| 42959 | private: |
| 42960 | virtual const RegMask &out_RegMask() const; |
| 42961 | virtual uint rule() const { return vdiv4D_reg_rule; } |
| 42962 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42963 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 42964 | virtual uint oper_input_base() const { return 1; } |
| 42965 | public: |
| 42966 | vdiv4D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 42967 | virtual uint size_of() const { return sizeof(vdiv4D_regNode); } |
| 42968 | static const Pipeline *pipeline_class(); |
| 42969 | virtual const Pipeline *pipeline() const; |
| 42970 | #ifndef PRODUCT |
| 42971 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 42972 | virtual const char *Name() const { return "vdiv4D_reg";} |
| 42973 | #endif |
| 42974 | }; |
| 42975 | |
| 42976 | class vdiv4D_memNode : public MachTypeNode { |
| 42977 | private: |
| 42978 | MachOper *_opnd_array[3]; |
| 42979 | public: |
| 42980 | MachOper *opnd_array(uint operand_index) const { |
| 42981 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42982 | return _opnd_array[operand_index]; |
| 42983 | } |
| 42984 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 42985 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 42986 | _opnd_array[operand_index] = operand; |
| 42987 | } |
| 42988 | private: |
| 42989 | virtual const RegMask &out_RegMask() const; |
| 42990 | virtual uint rule() const { return vdiv4D_mem_rule; } |
| 42991 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 42992 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 42993 | virtual int reloc() const; |
| 42994 | virtual uint oper_input_base() const { return 2; } |
| 42995 | public: |
| 42996 | vdiv4D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 42997 | virtual uint size_of() const { return sizeof(vdiv4D_memNode); } |
| 42998 | static const Pipeline *pipeline_class(); |
| 42999 | virtual const Pipeline *pipeline() const; |
| 43000 | virtual const MachOper *memory_operand() const; |
| 43001 | #ifndef PRODUCT |
| 43002 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43003 | virtual const char *Name() const { return "vdiv4D_mem";} |
| 43004 | #endif |
| 43005 | }; |
| 43006 | |
| 43007 | class vdiv8D_regNode : public MachTypeNode { |
| 43008 | private: |
| 43009 | MachOper *_opnd_array[3]; |
| 43010 | public: |
| 43011 | MachOper *opnd_array(uint operand_index) const { |
| 43012 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43013 | return _opnd_array[operand_index]; |
| 43014 | } |
| 43015 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43017 | _opnd_array[operand_index] = operand; |
| 43018 | } |
| 43019 | private: |
| 43020 | virtual const RegMask &out_RegMask() const; |
| 43021 | virtual uint rule() const { return vdiv8D_reg_rule; } |
| 43022 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43023 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 43024 | virtual uint oper_input_base() const { return 1; } |
| 43025 | public: |
| 43026 | vdiv8D_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 43027 | virtual uint size_of() const { return sizeof(vdiv8D_regNode); } |
| 43028 | static const Pipeline *pipeline_class(); |
| 43029 | virtual const Pipeline *pipeline() const; |
| 43030 | #ifndef PRODUCT |
| 43031 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43032 | virtual const char *Name() const { return "vdiv8D_reg";} |
| 43033 | #endif |
| 43034 | }; |
| 43035 | |
| 43036 | class vdiv8D_memNode : public MachTypeNode { |
| 43037 | private: |
| 43038 | MachOper *_opnd_array[3]; |
| 43039 | public: |
| 43040 | MachOper *opnd_array(uint operand_index) const { |
| 43041 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43042 | return _opnd_array[operand_index]; |
| 43043 | } |
| 43044 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43045 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43046 | _opnd_array[operand_index] = operand; |
| 43047 | } |
| 43048 | private: |
| 43049 | virtual const RegMask &out_RegMask() const; |
| 43050 | virtual uint rule() const { return vdiv8D_mem_rule; } |
| 43051 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43052 | virtual int ideal_Opcode() const { return Op_DivVD; } |
| 43053 | virtual int reloc() const; |
| 43054 | virtual uint oper_input_base() const { return 2; } |
| 43055 | public: |
| 43056 | vdiv8D_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43057 | virtual uint size_of() const { return sizeof(vdiv8D_memNode); } |
| 43058 | static const Pipeline *pipeline_class(); |
| 43059 | virtual const Pipeline *pipeline() const; |
| 43060 | virtual const MachOper *memory_operand() const; |
| 43061 | #ifndef PRODUCT |
| 43062 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43063 | virtual const char *Name() const { return "vdiv8D_mem";} |
| 43064 | #endif |
| 43065 | }; |
| 43066 | |
| 43067 | class vsqrt2D_regNode : public MachTypeNode { |
| 43068 | private: |
| 43069 | MachOper *_opnd_array[2]; |
| 43070 | public: |
| 43071 | MachOper *opnd_array(uint operand_index) const { |
| 43072 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43073 | return _opnd_array[operand_index]; |
| 43074 | } |
| 43075 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43076 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43077 | _opnd_array[operand_index] = operand; |
| 43078 | } |
| 43079 | private: |
| 43080 | virtual const RegMask &out_RegMask() const; |
| 43081 | virtual uint rule() const { return vsqrt2D_reg_rule; } |
| 43082 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43083 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43084 | virtual uint oper_input_base() const { return 1; } |
| 43085 | public: |
| 43086 | vsqrt2D_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43087 | virtual uint size_of() const { return sizeof(vsqrt2D_regNode); } |
| 43088 | // Rematerialize vsqrt2D_reg |
| 43089 | static const Pipeline *pipeline_class(); |
| 43090 | virtual const Pipeline *pipeline() const; |
| 43091 | #ifndef PRODUCT |
| 43092 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43093 | virtual const char *Name() const { return "vsqrt2D_reg";} |
| 43094 | #endif |
| 43095 | }; |
| 43096 | |
| 43097 | class vsqrt2D_memNode : public MachTypeNode { |
| 43098 | private: |
| 43099 | MachOper *_opnd_array[2]; |
| 43100 | public: |
| 43101 | MachOper *opnd_array(uint operand_index) const { |
| 43102 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43103 | return _opnd_array[operand_index]; |
| 43104 | } |
| 43105 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43107 | _opnd_array[operand_index] = operand; |
| 43108 | } |
| 43109 | private: |
| 43110 | virtual const RegMask &out_RegMask() const; |
| 43111 | virtual uint rule() const { return vsqrt2D_mem_rule; } |
| 43112 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43113 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43114 | virtual int reloc() const; |
| 43115 | virtual uint oper_input_base() const { return 2; } |
| 43116 | public: |
| 43117 | vsqrt2D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43118 | virtual uint size_of() const { return sizeof(vsqrt2D_memNode); } |
| 43119 | // Rematerialize vsqrt2D_mem |
| 43120 | static const Pipeline *pipeline_class(); |
| 43121 | virtual const Pipeline *pipeline() const; |
| 43122 | virtual const MachOper *memory_operand() const; |
| 43123 | #ifndef PRODUCT |
| 43124 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43125 | virtual const char *Name() const { return "vsqrt2D_mem";} |
| 43126 | #endif |
| 43127 | }; |
| 43128 | |
| 43129 | class vsqrt4D_regNode : public MachTypeNode { |
| 43130 | private: |
| 43131 | MachOper *_opnd_array[2]; |
| 43132 | public: |
| 43133 | MachOper *opnd_array(uint operand_index) const { |
| 43134 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43135 | return _opnd_array[operand_index]; |
| 43136 | } |
| 43137 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43138 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43139 | _opnd_array[operand_index] = operand; |
| 43140 | } |
| 43141 | private: |
| 43142 | virtual const RegMask &out_RegMask() const; |
| 43143 | virtual uint rule() const { return vsqrt4D_reg_rule; } |
| 43144 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43145 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43146 | virtual uint oper_input_base() const { return 1; } |
| 43147 | public: |
| 43148 | vsqrt4D_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43149 | virtual uint size_of() const { return sizeof(vsqrt4D_regNode); } |
| 43150 | // Rematerialize vsqrt4D_reg |
| 43151 | static const Pipeline *pipeline_class(); |
| 43152 | virtual const Pipeline *pipeline() const; |
| 43153 | #ifndef PRODUCT |
| 43154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43155 | virtual const char *Name() const { return "vsqrt4D_reg";} |
| 43156 | #endif |
| 43157 | }; |
| 43158 | |
| 43159 | class vsqrt4D_memNode : public MachTypeNode { |
| 43160 | private: |
| 43161 | MachOper *_opnd_array[2]; |
| 43162 | public: |
| 43163 | MachOper *opnd_array(uint operand_index) const { |
| 43164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43165 | return _opnd_array[operand_index]; |
| 43166 | } |
| 43167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43169 | _opnd_array[operand_index] = operand; |
| 43170 | } |
| 43171 | private: |
| 43172 | virtual const RegMask &out_RegMask() const; |
| 43173 | virtual uint rule() const { return vsqrt4D_mem_rule; } |
| 43174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43175 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43176 | virtual int reloc() const; |
| 43177 | virtual uint oper_input_base() const { return 2; } |
| 43178 | public: |
| 43179 | vsqrt4D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43180 | virtual uint size_of() const { return sizeof(vsqrt4D_memNode); } |
| 43181 | // Rematerialize vsqrt4D_mem |
| 43182 | static const Pipeline *pipeline_class(); |
| 43183 | virtual const Pipeline *pipeline() const; |
| 43184 | virtual const MachOper *memory_operand() const; |
| 43185 | #ifndef PRODUCT |
| 43186 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43187 | virtual const char *Name() const { return "vsqrt4D_mem";} |
| 43188 | #endif |
| 43189 | }; |
| 43190 | |
| 43191 | class vsqrt8D_regNode : public MachTypeNode { |
| 43192 | private: |
| 43193 | MachOper *_opnd_array[2]; |
| 43194 | public: |
| 43195 | MachOper *opnd_array(uint operand_index) const { |
| 43196 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43197 | return _opnd_array[operand_index]; |
| 43198 | } |
| 43199 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43200 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43201 | _opnd_array[operand_index] = operand; |
| 43202 | } |
| 43203 | private: |
| 43204 | virtual const RegMask &out_RegMask() const; |
| 43205 | virtual uint rule() const { return vsqrt8D_reg_rule; } |
| 43206 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43207 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43208 | virtual uint oper_input_base() const { return 1; } |
| 43209 | public: |
| 43210 | vsqrt8D_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43211 | virtual uint size_of() const { return sizeof(vsqrt8D_regNode); } |
| 43212 | // Rematerialize vsqrt8D_reg |
| 43213 | static const Pipeline *pipeline_class(); |
| 43214 | virtual const Pipeline *pipeline() const; |
| 43215 | #ifndef PRODUCT |
| 43216 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43217 | virtual const char *Name() const { return "vsqrt8D_reg";} |
| 43218 | #endif |
| 43219 | }; |
| 43220 | |
| 43221 | class vsqrt8D_memNode : public MachTypeNode { |
| 43222 | private: |
| 43223 | MachOper *_opnd_array[2]; |
| 43224 | public: |
| 43225 | MachOper *opnd_array(uint operand_index) const { |
| 43226 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43227 | return _opnd_array[operand_index]; |
| 43228 | } |
| 43229 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43231 | _opnd_array[operand_index] = operand; |
| 43232 | } |
| 43233 | private: |
| 43234 | virtual const RegMask &out_RegMask() const; |
| 43235 | virtual uint rule() const { return vsqrt8D_mem_rule; } |
| 43236 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43237 | virtual int ideal_Opcode() const { return Op_SqrtVD; } |
| 43238 | virtual int reloc() const; |
| 43239 | virtual uint oper_input_base() const { return 2; } |
| 43240 | public: |
| 43241 | vsqrt8D_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43242 | virtual uint size_of() const { return sizeof(vsqrt8D_memNode); } |
| 43243 | // Rematerialize vsqrt8D_mem |
| 43244 | static const Pipeline *pipeline_class(); |
| 43245 | virtual const Pipeline *pipeline() const; |
| 43246 | virtual const MachOper *memory_operand() const; |
| 43247 | #ifndef PRODUCT |
| 43248 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43249 | virtual const char *Name() const { return "vsqrt8D_mem";} |
| 43250 | #endif |
| 43251 | }; |
| 43252 | |
| 43253 | class vsqrt2F_regNode : public MachTypeNode { |
| 43254 | private: |
| 43255 | MachOper *_opnd_array[2]; |
| 43256 | public: |
| 43257 | MachOper *opnd_array(uint operand_index) const { |
| 43258 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43259 | return _opnd_array[operand_index]; |
| 43260 | } |
| 43261 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43262 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43263 | _opnd_array[operand_index] = operand; |
| 43264 | } |
| 43265 | private: |
| 43266 | virtual const RegMask &out_RegMask() const; |
| 43267 | virtual uint rule() const { return vsqrt2F_reg_rule; } |
| 43268 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43269 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43270 | virtual uint oper_input_base() const { return 1; } |
| 43271 | public: |
| 43272 | vsqrt2F_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43273 | virtual uint size_of() const { return sizeof(vsqrt2F_regNode); } |
| 43274 | // Rematerialize vsqrt2F_reg |
| 43275 | static const Pipeline *pipeline_class(); |
| 43276 | virtual const Pipeline *pipeline() const; |
| 43277 | #ifndef PRODUCT |
| 43278 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43279 | virtual const char *Name() const { return "vsqrt2F_reg";} |
| 43280 | #endif |
| 43281 | }; |
| 43282 | |
| 43283 | class vsqrt2F_memNode : public MachTypeNode { |
| 43284 | private: |
| 43285 | MachOper *_opnd_array[2]; |
| 43286 | public: |
| 43287 | MachOper *opnd_array(uint operand_index) const { |
| 43288 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43289 | return _opnd_array[operand_index]; |
| 43290 | } |
| 43291 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43292 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43293 | _opnd_array[operand_index] = operand; |
| 43294 | } |
| 43295 | private: |
| 43296 | virtual const RegMask &out_RegMask() const; |
| 43297 | virtual uint rule() const { return vsqrt2F_mem_rule; } |
| 43298 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43299 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43300 | virtual int reloc() const; |
| 43301 | virtual uint oper_input_base() const { return 2; } |
| 43302 | public: |
| 43303 | vsqrt2F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43304 | virtual uint size_of() const { return sizeof(vsqrt2F_memNode); } |
| 43305 | // Rematerialize vsqrt2F_mem |
| 43306 | static const Pipeline *pipeline_class(); |
| 43307 | virtual const Pipeline *pipeline() const; |
| 43308 | virtual const MachOper *memory_operand() const; |
| 43309 | #ifndef PRODUCT |
| 43310 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43311 | virtual const char *Name() const { return "vsqrt2F_mem";} |
| 43312 | #endif |
| 43313 | }; |
| 43314 | |
| 43315 | class vsqrt4F_regNode : public MachTypeNode { |
| 43316 | private: |
| 43317 | MachOper *_opnd_array[2]; |
| 43318 | public: |
| 43319 | MachOper *opnd_array(uint operand_index) const { |
| 43320 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43321 | return _opnd_array[operand_index]; |
| 43322 | } |
| 43323 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43324 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43325 | _opnd_array[operand_index] = operand; |
| 43326 | } |
| 43327 | private: |
| 43328 | virtual const RegMask &out_RegMask() const; |
| 43329 | virtual uint rule() const { return vsqrt4F_reg_rule; } |
| 43330 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43331 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43332 | virtual uint oper_input_base() const { return 1; } |
| 43333 | public: |
| 43334 | vsqrt4F_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43335 | virtual uint size_of() const { return sizeof(vsqrt4F_regNode); } |
| 43336 | // Rematerialize vsqrt4F_reg |
| 43337 | static const Pipeline *pipeline_class(); |
| 43338 | virtual const Pipeline *pipeline() const; |
| 43339 | #ifndef PRODUCT |
| 43340 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43341 | virtual const char *Name() const { return "vsqrt4F_reg";} |
| 43342 | #endif |
| 43343 | }; |
| 43344 | |
| 43345 | class vsqrt4F_memNode : public MachTypeNode { |
| 43346 | private: |
| 43347 | MachOper *_opnd_array[2]; |
| 43348 | public: |
| 43349 | MachOper *opnd_array(uint operand_index) const { |
| 43350 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43351 | return _opnd_array[operand_index]; |
| 43352 | } |
| 43353 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43354 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43355 | _opnd_array[operand_index] = operand; |
| 43356 | } |
| 43357 | private: |
| 43358 | virtual const RegMask &out_RegMask() const; |
| 43359 | virtual uint rule() const { return vsqrt4F_mem_rule; } |
| 43360 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43361 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43362 | virtual int reloc() const; |
| 43363 | virtual uint oper_input_base() const { return 2; } |
| 43364 | public: |
| 43365 | vsqrt4F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43366 | virtual uint size_of() const { return sizeof(vsqrt4F_memNode); } |
| 43367 | // Rematerialize vsqrt4F_mem |
| 43368 | static const Pipeline *pipeline_class(); |
| 43369 | virtual const Pipeline *pipeline() const; |
| 43370 | virtual const MachOper *memory_operand() const; |
| 43371 | #ifndef PRODUCT |
| 43372 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43373 | virtual const char *Name() const { return "vsqrt4F_mem";} |
| 43374 | #endif |
| 43375 | }; |
| 43376 | |
| 43377 | class vsqrt8F_regNode : public MachTypeNode { |
| 43378 | private: |
| 43379 | MachOper *_opnd_array[2]; |
| 43380 | public: |
| 43381 | MachOper *opnd_array(uint operand_index) const { |
| 43382 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43383 | return _opnd_array[operand_index]; |
| 43384 | } |
| 43385 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43386 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43387 | _opnd_array[operand_index] = operand; |
| 43388 | } |
| 43389 | private: |
| 43390 | virtual const RegMask &out_RegMask() const; |
| 43391 | virtual uint rule() const { return vsqrt8F_reg_rule; } |
| 43392 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43393 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43394 | virtual uint oper_input_base() const { return 1; } |
| 43395 | public: |
| 43396 | vsqrt8F_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43397 | virtual uint size_of() const { return sizeof(vsqrt8F_regNode); } |
| 43398 | // Rematerialize vsqrt8F_reg |
| 43399 | static const Pipeline *pipeline_class(); |
| 43400 | virtual const Pipeline *pipeline() const; |
| 43401 | #ifndef PRODUCT |
| 43402 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43403 | virtual const char *Name() const { return "vsqrt8F_reg";} |
| 43404 | #endif |
| 43405 | }; |
| 43406 | |
| 43407 | class vsqrt8F_memNode : public MachTypeNode { |
| 43408 | private: |
| 43409 | MachOper *_opnd_array[2]; |
| 43410 | public: |
| 43411 | MachOper *opnd_array(uint operand_index) const { |
| 43412 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43413 | return _opnd_array[operand_index]; |
| 43414 | } |
| 43415 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43416 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43417 | _opnd_array[operand_index] = operand; |
| 43418 | } |
| 43419 | private: |
| 43420 | virtual const RegMask &out_RegMask() const; |
| 43421 | virtual uint rule() const { return vsqrt8F_mem_rule; } |
| 43422 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43423 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43424 | virtual int reloc() const; |
| 43425 | virtual uint oper_input_base() const { return 2; } |
| 43426 | public: |
| 43427 | vsqrt8F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43428 | virtual uint size_of() const { return sizeof(vsqrt8F_memNode); } |
| 43429 | // Rematerialize vsqrt8F_mem |
| 43430 | static const Pipeline *pipeline_class(); |
| 43431 | virtual const Pipeline *pipeline() const; |
| 43432 | virtual const MachOper *memory_operand() const; |
| 43433 | #ifndef PRODUCT |
| 43434 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43435 | virtual const char *Name() const { return "vsqrt8F_mem";} |
| 43436 | #endif |
| 43437 | }; |
| 43438 | |
| 43439 | class vsqrt16F_regNode : public MachTypeNode { |
| 43440 | private: |
| 43441 | MachOper *_opnd_array[2]; |
| 43442 | public: |
| 43443 | MachOper *opnd_array(uint operand_index) const { |
| 43444 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43445 | return _opnd_array[operand_index]; |
| 43446 | } |
| 43447 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43448 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43449 | _opnd_array[operand_index] = operand; |
| 43450 | } |
| 43451 | private: |
| 43452 | virtual const RegMask &out_RegMask() const; |
| 43453 | virtual uint rule() const { return vsqrt16F_reg_rule; } |
| 43454 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43455 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43456 | virtual uint oper_input_base() const { return 1; } |
| 43457 | public: |
| 43458 | vsqrt16F_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43459 | virtual uint size_of() const { return sizeof(vsqrt16F_regNode); } |
| 43460 | // Rematerialize vsqrt16F_reg |
| 43461 | static const Pipeline *pipeline_class(); |
| 43462 | virtual const Pipeline *pipeline() const; |
| 43463 | #ifndef PRODUCT |
| 43464 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43465 | virtual const char *Name() const { return "vsqrt16F_reg";} |
| 43466 | #endif |
| 43467 | }; |
| 43468 | |
| 43469 | class vsqrt16F_memNode : public MachTypeNode { |
| 43470 | private: |
| 43471 | MachOper *_opnd_array[2]; |
| 43472 | public: |
| 43473 | MachOper *opnd_array(uint operand_index) const { |
| 43474 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43475 | return _opnd_array[operand_index]; |
| 43476 | } |
| 43477 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43478 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43479 | _opnd_array[operand_index] = operand; |
| 43480 | } |
| 43481 | private: |
| 43482 | virtual const RegMask &out_RegMask() const; |
| 43483 | virtual uint rule() const { return vsqrt16F_mem_rule; } |
| 43484 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43485 | virtual int ideal_Opcode() const { return Op_SqrtVF; } |
| 43486 | virtual int reloc() const; |
| 43487 | virtual uint oper_input_base() const { return 2; } |
| 43488 | public: |
| 43489 | vsqrt16F_memNode() { _num_opnds = 2; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 43490 | virtual uint size_of() const { return sizeof(vsqrt16F_memNode); } |
| 43491 | // Rematerialize vsqrt16F_mem |
| 43492 | static const Pipeline *pipeline_class(); |
| 43493 | virtual const Pipeline *pipeline() const; |
| 43494 | virtual const MachOper *memory_operand() const; |
| 43495 | #ifndef PRODUCT |
| 43496 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43497 | virtual const char *Name() const { return "vsqrt16F_mem";} |
| 43498 | #endif |
| 43499 | }; |
| 43500 | |
| 43501 | class vshiftcntNode : public MachTypeNode { |
| 43502 | private: |
| 43503 | MachOper *_opnd_array[2]; |
| 43504 | public: |
| 43505 | MachOper *opnd_array(uint operand_index) const { |
| 43506 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43507 | return _opnd_array[operand_index]; |
| 43508 | } |
| 43509 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43510 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43511 | _opnd_array[operand_index] = operand; |
| 43512 | } |
| 43513 | private: |
| 43514 | virtual const RegMask &out_RegMask() const; |
| 43515 | virtual uint rule() const { return vshiftcnt_rule; } |
| 43516 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43517 | virtual int ideal_Opcode() const { return Op_LShiftCntV; } |
| 43518 | virtual uint oper_input_base() const { return 1; } |
| 43519 | public: |
| 43520 | vshiftcntNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43521 | virtual uint size_of() const { return sizeof(vshiftcntNode); } |
| 43522 | // Rematerialize vshiftcnt |
| 43523 | static const Pipeline *pipeline_class(); |
| 43524 | virtual const Pipeline *pipeline() const; |
| 43525 | #ifndef PRODUCT |
| 43526 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43527 | virtual const char *Name() const { return "vshiftcnt";} |
| 43528 | #endif |
| 43529 | }; |
| 43530 | |
| 43531 | class vshiftcnt_0Node : public MachTypeNode { |
| 43532 | private: |
| 43533 | MachOper *_opnd_array[2]; |
| 43534 | public: |
| 43535 | MachOper *opnd_array(uint operand_index) const { |
| 43536 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43537 | return _opnd_array[operand_index]; |
| 43538 | } |
| 43539 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43540 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43541 | _opnd_array[operand_index] = operand; |
| 43542 | } |
| 43543 | private: |
| 43544 | virtual const RegMask &out_RegMask() const; |
| 43545 | virtual uint rule() const { return vshiftcnt_0_rule; } |
| 43546 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43547 | virtual int ideal_Opcode() const { return Op_RShiftCntV; } |
| 43548 | virtual uint oper_input_base() const { return 1; } |
| 43549 | public: |
| 43550 | vshiftcnt_0Node() { _num_opnds = 2; _opnds = _opnd_array; } |
| 43551 | virtual uint size_of() const { return sizeof(vshiftcnt_0Node); } |
| 43552 | // Rematerialize vshiftcnt_0 |
| 43553 | static const Pipeline *pipeline_class(); |
| 43554 | virtual const Pipeline *pipeline() const; |
| 43555 | #ifndef PRODUCT |
| 43556 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43557 | virtual const char *Name() const { return "vshiftcnt_0";} |
| 43558 | #endif |
| 43559 | }; |
| 43560 | |
| 43561 | class vshiftcntimmNode : public MachNode { |
| 43562 | private: |
| 43563 | MachOper *_opnd_array[3]; |
| 43564 | public: |
| 43565 | MachOper *opnd_array(uint operand_index) const { |
| 43566 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43567 | return _opnd_array[operand_index]; |
| 43568 | } |
| 43569 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43570 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43571 | _opnd_array[operand_index] = operand; |
| 43572 | } |
| 43573 | private: |
| 43574 | virtual const RegMask &out_RegMask() const; |
| 43575 | virtual uint rule() const { return vshiftcntimm_rule; } |
| 43576 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43577 | virtual int ideal_Opcode() const { return Op_ConI; } |
| 43578 | public: |
| 43579 | vshiftcntimmNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_is_Con); } |
| 43580 | virtual uint size_of() const { return sizeof(vshiftcntimmNode); } |
| 43581 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43582 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43583 | // Rematerialize vshiftcntimm |
| 43584 | static const Pipeline *pipeline_class(); |
| 43585 | virtual const Pipeline *pipeline() const; |
| 43586 | virtual const class Type *bottom_type() const { |
| 43587 | return TypeInt::make(opnd_array(1)->constant()); |
| 43588 | }; |
| 43589 | #ifndef PRODUCT |
| 43590 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43591 | virtual const char *Name() const { return "vshiftcntimm";} |
| 43592 | #endif |
| 43593 | }; |
| 43594 | |
| 43595 | class vshift4BNode : public MachTypeNode { |
| 43596 | private: |
| 43597 | MachOper *_opnd_array[6]; |
| 43598 | public: |
| 43599 | MachOper *opnd_array(uint operand_index) const { |
| 43600 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43601 | return _opnd_array[operand_index]; |
| 43602 | } |
| 43603 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43604 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43605 | _opnd_array[operand_index] = operand; |
| 43606 | } |
| 43607 | private: |
| 43608 | virtual const RegMask &out_RegMask() const; |
| 43609 | virtual uint rule() const { return vshift4B_rule; } |
| 43610 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43611 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 43612 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43613 | virtual uint oper_input_base() const { return 1; } |
| 43614 | public: |
| 43615 | vshift4BNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43616 | virtual uint size_of() const { return sizeof(vshift4BNode); } |
| 43617 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43618 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43619 | static const Pipeline *pipeline_class(); |
| 43620 | virtual const Pipeline *pipeline() const; |
| 43621 | #ifndef PRODUCT |
| 43622 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43623 | virtual const char *Name() const { return "vshift4B";} |
| 43624 | #endif |
| 43625 | }; |
| 43626 | |
| 43627 | class vshift4B_0Node : public MachTypeNode { |
| 43628 | private: |
| 43629 | MachOper *_opnd_array[6]; |
| 43630 | public: |
| 43631 | MachOper *opnd_array(uint operand_index) const { |
| 43632 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43633 | return _opnd_array[operand_index]; |
| 43634 | } |
| 43635 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43636 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43637 | _opnd_array[operand_index] = operand; |
| 43638 | } |
| 43639 | private: |
| 43640 | virtual const RegMask &out_RegMask() const; |
| 43641 | virtual uint rule() const { return vshift4B_0_rule; } |
| 43642 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43643 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 43644 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43645 | virtual uint oper_input_base() const { return 1; } |
| 43646 | public: |
| 43647 | vshift4B_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43648 | virtual uint size_of() const { return sizeof(vshift4B_0Node); } |
| 43649 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43650 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43651 | static const Pipeline *pipeline_class(); |
| 43652 | virtual const Pipeline *pipeline() const; |
| 43653 | #ifndef PRODUCT |
| 43654 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43655 | virtual const char *Name() const { return "vshift4B_0";} |
| 43656 | #endif |
| 43657 | }; |
| 43658 | |
| 43659 | class vshift4B_1Node : public MachTypeNode { |
| 43660 | private: |
| 43661 | MachOper *_opnd_array[6]; |
| 43662 | public: |
| 43663 | MachOper *opnd_array(uint operand_index) const { |
| 43664 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43665 | return _opnd_array[operand_index]; |
| 43666 | } |
| 43667 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43668 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43669 | _opnd_array[operand_index] = operand; |
| 43670 | } |
| 43671 | private: |
| 43672 | virtual const RegMask &out_RegMask() const; |
| 43673 | virtual uint rule() const { return vshift4B_1_rule; } |
| 43674 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43675 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 43676 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43677 | virtual uint oper_input_base() const { return 1; } |
| 43678 | public: |
| 43679 | vshift4B_1Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43680 | virtual uint size_of() const { return sizeof(vshift4B_1Node); } |
| 43681 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43682 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43683 | static const Pipeline *pipeline_class(); |
| 43684 | virtual const Pipeline *pipeline() const; |
| 43685 | #ifndef PRODUCT |
| 43686 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43687 | virtual const char *Name() const { return "vshift4B_1";} |
| 43688 | #endif |
| 43689 | }; |
| 43690 | |
| 43691 | class vshift8BNode : public MachTypeNode { |
| 43692 | private: |
| 43693 | MachOper *_opnd_array[6]; |
| 43694 | public: |
| 43695 | MachOper *opnd_array(uint operand_index) const { |
| 43696 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43697 | return _opnd_array[operand_index]; |
| 43698 | } |
| 43699 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43700 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43701 | _opnd_array[operand_index] = operand; |
| 43702 | } |
| 43703 | private: |
| 43704 | virtual const RegMask &out_RegMask() const; |
| 43705 | virtual uint rule() const { return vshift8B_rule; } |
| 43706 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43707 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 43708 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43709 | virtual uint oper_input_base() const { return 1; } |
| 43710 | public: |
| 43711 | vshift8BNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43712 | virtual uint size_of() const { return sizeof(vshift8BNode); } |
| 43713 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43714 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43715 | static const Pipeline *pipeline_class(); |
| 43716 | virtual const Pipeline *pipeline() const; |
| 43717 | #ifndef PRODUCT |
| 43718 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43719 | virtual const char *Name() const { return "vshift8B";} |
| 43720 | #endif |
| 43721 | }; |
| 43722 | |
| 43723 | class vshift8B_0Node : public MachTypeNode { |
| 43724 | private: |
| 43725 | MachOper *_opnd_array[6]; |
| 43726 | public: |
| 43727 | MachOper *opnd_array(uint operand_index) const { |
| 43728 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43729 | return _opnd_array[operand_index]; |
| 43730 | } |
| 43731 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43732 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43733 | _opnd_array[operand_index] = operand; |
| 43734 | } |
| 43735 | private: |
| 43736 | virtual const RegMask &out_RegMask() const; |
| 43737 | virtual uint rule() const { return vshift8B_0_rule; } |
| 43738 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43739 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 43740 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43741 | virtual uint oper_input_base() const { return 1; } |
| 43742 | public: |
| 43743 | vshift8B_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43744 | virtual uint size_of() const { return sizeof(vshift8B_0Node); } |
| 43745 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43746 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43747 | static const Pipeline *pipeline_class(); |
| 43748 | virtual const Pipeline *pipeline() const; |
| 43749 | #ifndef PRODUCT |
| 43750 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43751 | virtual const char *Name() const { return "vshift8B_0";} |
| 43752 | #endif |
| 43753 | }; |
| 43754 | |
| 43755 | class vshift8B_1Node : public MachTypeNode { |
| 43756 | private: |
| 43757 | MachOper *_opnd_array[6]; |
| 43758 | public: |
| 43759 | MachOper *opnd_array(uint operand_index) const { |
| 43760 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43761 | return _opnd_array[operand_index]; |
| 43762 | } |
| 43763 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43765 | _opnd_array[operand_index] = operand; |
| 43766 | } |
| 43767 | private: |
| 43768 | virtual const RegMask &out_RegMask() const; |
| 43769 | virtual uint rule() const { return vshift8B_1_rule; } |
| 43770 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43771 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 43772 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43773 | virtual uint oper_input_base() const { return 1; } |
| 43774 | public: |
| 43775 | vshift8B_1Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43776 | virtual uint size_of() const { return sizeof(vshift8B_1Node); } |
| 43777 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43778 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43779 | static const Pipeline *pipeline_class(); |
| 43780 | virtual const Pipeline *pipeline() const; |
| 43781 | #ifndef PRODUCT |
| 43782 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43783 | virtual const char *Name() const { return "vshift8B_1";} |
| 43784 | #endif |
| 43785 | }; |
| 43786 | |
| 43787 | class vshift16BNode : public MachTypeNode { |
| 43788 | private: |
| 43789 | MachOper *_opnd_array[7]; |
| 43790 | public: |
| 43791 | MachOper *opnd_array(uint operand_index) const { |
| 43792 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43793 | return _opnd_array[operand_index]; |
| 43794 | } |
| 43795 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43797 | _opnd_array[operand_index] = operand; |
| 43798 | } |
| 43799 | private: |
| 43800 | virtual const RegMask &out_RegMask() const; |
| 43801 | virtual uint rule() const { return vshift16B_rule; } |
| 43802 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43803 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 43804 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43805 | virtual uint oper_input_base() const { return 1; } |
| 43806 | public: |
| 43807 | vshift16BNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 43808 | virtual uint size_of() const { return sizeof(vshift16BNode); } |
| 43809 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43810 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43811 | static const Pipeline *pipeline_class(); |
| 43812 | virtual const Pipeline *pipeline() const; |
| 43813 | #ifndef PRODUCT |
| 43814 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43815 | virtual const char *Name() const { return "vshift16B";} |
| 43816 | #endif |
| 43817 | }; |
| 43818 | |
| 43819 | class vshift16B_0Node : public MachTypeNode { |
| 43820 | private: |
| 43821 | MachOper *_opnd_array[7]; |
| 43822 | public: |
| 43823 | MachOper *opnd_array(uint operand_index) const { |
| 43824 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43825 | return _opnd_array[operand_index]; |
| 43826 | } |
| 43827 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43828 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43829 | _opnd_array[operand_index] = operand; |
| 43830 | } |
| 43831 | private: |
| 43832 | virtual const RegMask &out_RegMask() const; |
| 43833 | virtual uint rule() const { return vshift16B_0_rule; } |
| 43834 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43835 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 43836 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43837 | virtual uint oper_input_base() const { return 1; } |
| 43838 | public: |
| 43839 | vshift16B_0Node() { _num_opnds = 7; _opnds = _opnd_array; } |
| 43840 | virtual uint size_of() const { return sizeof(vshift16B_0Node); } |
| 43841 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43842 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43843 | static const Pipeline *pipeline_class(); |
| 43844 | virtual const Pipeline *pipeline() const; |
| 43845 | #ifndef PRODUCT |
| 43846 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43847 | virtual const char *Name() const { return "vshift16B_0";} |
| 43848 | #endif |
| 43849 | }; |
| 43850 | |
| 43851 | class vshift16B_1Node : public MachTypeNode { |
| 43852 | private: |
| 43853 | MachOper *_opnd_array[7]; |
| 43854 | public: |
| 43855 | MachOper *opnd_array(uint operand_index) const { |
| 43856 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43857 | return _opnd_array[operand_index]; |
| 43858 | } |
| 43859 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43860 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43861 | _opnd_array[operand_index] = operand; |
| 43862 | } |
| 43863 | private: |
| 43864 | virtual const RegMask &out_RegMask() const; |
| 43865 | virtual uint rule() const { return vshift16B_1_rule; } |
| 43866 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43867 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 43868 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43869 | virtual uint oper_input_base() const { return 1; } |
| 43870 | public: |
| 43871 | vshift16B_1Node() { _num_opnds = 7; _opnds = _opnd_array; } |
| 43872 | virtual uint size_of() const { return sizeof(vshift16B_1Node); } |
| 43873 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43874 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43875 | static const Pipeline *pipeline_class(); |
| 43876 | virtual const Pipeline *pipeline() const; |
| 43877 | #ifndef PRODUCT |
| 43878 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43879 | virtual const char *Name() const { return "vshift16B_1";} |
| 43880 | #endif |
| 43881 | }; |
| 43882 | |
| 43883 | class vshift16B_avxNode : public MachTypeNode { |
| 43884 | private: |
| 43885 | MachOper *_opnd_array[6]; |
| 43886 | public: |
| 43887 | MachOper *opnd_array(uint operand_index) const { |
| 43888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43889 | return _opnd_array[operand_index]; |
| 43890 | } |
| 43891 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43893 | _opnd_array[operand_index] = operand; |
| 43894 | } |
| 43895 | private: |
| 43896 | virtual const RegMask &out_RegMask() const; |
| 43897 | virtual uint rule() const { return vshift16B_avx_rule; } |
| 43898 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43899 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 43900 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43901 | virtual uint oper_input_base() const { return 1; } |
| 43902 | public: |
| 43903 | vshift16B_avxNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43904 | virtual uint size_of() const { return sizeof(vshift16B_avxNode); } |
| 43905 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43906 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43907 | static const Pipeline *pipeline_class(); |
| 43908 | virtual const Pipeline *pipeline() const; |
| 43909 | #ifndef PRODUCT |
| 43910 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43911 | virtual const char *Name() const { return "vshift16B_avx";} |
| 43912 | #endif |
| 43913 | }; |
| 43914 | |
| 43915 | class vshift16B_avx_0Node : public MachTypeNode { |
| 43916 | private: |
| 43917 | MachOper *_opnd_array[6]; |
| 43918 | public: |
| 43919 | MachOper *opnd_array(uint operand_index) const { |
| 43920 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43921 | return _opnd_array[operand_index]; |
| 43922 | } |
| 43923 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43924 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43925 | _opnd_array[operand_index] = operand; |
| 43926 | } |
| 43927 | private: |
| 43928 | virtual const RegMask &out_RegMask() const; |
| 43929 | virtual uint rule() const { return vshift16B_avx_0_rule; } |
| 43930 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43931 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 43932 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43933 | virtual uint oper_input_base() const { return 1; } |
| 43934 | public: |
| 43935 | vshift16B_avx_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43936 | virtual uint size_of() const { return sizeof(vshift16B_avx_0Node); } |
| 43937 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43938 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43939 | static const Pipeline *pipeline_class(); |
| 43940 | virtual const Pipeline *pipeline() const; |
| 43941 | #ifndef PRODUCT |
| 43942 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43943 | virtual const char *Name() const { return "vshift16B_avx_0";} |
| 43944 | #endif |
| 43945 | }; |
| 43946 | |
| 43947 | class vshift16B_avx_1Node : public MachTypeNode { |
| 43948 | private: |
| 43949 | MachOper *_opnd_array[6]; |
| 43950 | public: |
| 43951 | MachOper *opnd_array(uint operand_index) const { |
| 43952 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43953 | return _opnd_array[operand_index]; |
| 43954 | } |
| 43955 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43957 | _opnd_array[operand_index] = operand; |
| 43958 | } |
| 43959 | private: |
| 43960 | virtual const RegMask &out_RegMask() const; |
| 43961 | virtual uint rule() const { return vshift16B_avx_1_rule; } |
| 43962 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43963 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 43964 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43965 | virtual uint oper_input_base() const { return 1; } |
| 43966 | public: |
| 43967 | vshift16B_avx_1Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 43968 | virtual uint size_of() const { return sizeof(vshift16B_avx_1Node); } |
| 43969 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 43970 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 43971 | static const Pipeline *pipeline_class(); |
| 43972 | virtual const Pipeline *pipeline() const; |
| 43973 | #ifndef PRODUCT |
| 43974 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 43975 | virtual const char *Name() const { return "vshift16B_avx_1";} |
| 43976 | #endif |
| 43977 | }; |
| 43978 | |
| 43979 | class vshift32B_avxNode : public MachTypeNode { |
| 43980 | private: |
| 43981 | MachOper *_opnd_array[6]; |
| 43982 | public: |
| 43983 | MachOper *opnd_array(uint operand_index) const { |
| 43984 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43985 | return _opnd_array[operand_index]; |
| 43986 | } |
| 43987 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 43988 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 43989 | _opnd_array[operand_index] = operand; |
| 43990 | } |
| 43991 | private: |
| 43992 | virtual const RegMask &out_RegMask() const; |
| 43993 | virtual uint rule() const { return vshift32B_avx_rule; } |
| 43994 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 43995 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 43996 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 43997 | virtual uint oper_input_base() const { return 1; } |
| 43998 | public: |
| 43999 | vshift32B_avxNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 44000 | virtual uint size_of() const { return sizeof(vshift32B_avxNode); } |
| 44001 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44002 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44003 | static const Pipeline *pipeline_class(); |
| 44004 | virtual const Pipeline *pipeline() const; |
| 44005 | #ifndef PRODUCT |
| 44006 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44007 | virtual const char *Name() const { return "vshift32B_avx";} |
| 44008 | #endif |
| 44009 | }; |
| 44010 | |
| 44011 | class vshift32B_avx_0Node : public MachTypeNode { |
| 44012 | private: |
| 44013 | MachOper *_opnd_array[6]; |
| 44014 | public: |
| 44015 | MachOper *opnd_array(uint operand_index) const { |
| 44016 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44017 | return _opnd_array[operand_index]; |
| 44018 | } |
| 44019 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44020 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44021 | _opnd_array[operand_index] = operand; |
| 44022 | } |
| 44023 | private: |
| 44024 | virtual const RegMask &out_RegMask() const; |
| 44025 | virtual uint rule() const { return vshift32B_avx_0_rule; } |
| 44026 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44027 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 44028 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44029 | virtual uint oper_input_base() const { return 1; } |
| 44030 | public: |
| 44031 | vshift32B_avx_0Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 44032 | virtual uint size_of() const { return sizeof(vshift32B_avx_0Node); } |
| 44033 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44034 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44035 | static const Pipeline *pipeline_class(); |
| 44036 | virtual const Pipeline *pipeline() const; |
| 44037 | #ifndef PRODUCT |
| 44038 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44039 | virtual const char *Name() const { return "vshift32B_avx_0";} |
| 44040 | #endif |
| 44041 | }; |
| 44042 | |
| 44043 | class vshift32B_avx_1Node : public MachTypeNode { |
| 44044 | private: |
| 44045 | MachOper *_opnd_array[6]; |
| 44046 | public: |
| 44047 | MachOper *opnd_array(uint operand_index) const { |
| 44048 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44049 | return _opnd_array[operand_index]; |
| 44050 | } |
| 44051 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44052 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44053 | _opnd_array[operand_index] = operand; |
| 44054 | } |
| 44055 | private: |
| 44056 | virtual const RegMask &out_RegMask() const; |
| 44057 | virtual uint rule() const { return vshift32B_avx_1_rule; } |
| 44058 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44059 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 44060 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44061 | virtual uint oper_input_base() const { return 1; } |
| 44062 | public: |
| 44063 | vshift32B_avx_1Node() { _num_opnds = 6; _opnds = _opnd_array; } |
| 44064 | virtual uint size_of() const { return sizeof(vshift32B_avx_1Node); } |
| 44065 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44066 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44067 | static const Pipeline *pipeline_class(); |
| 44068 | virtual const Pipeline *pipeline() const; |
| 44069 | #ifndef PRODUCT |
| 44070 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44071 | virtual const char *Name() const { return "vshift32B_avx_1";} |
| 44072 | #endif |
| 44073 | }; |
| 44074 | |
| 44075 | class vshift64B_avxNode : public MachTypeNode { |
| 44076 | private: |
| 44077 | MachOper *_opnd_array[7]; |
| 44078 | public: |
| 44079 | MachOper *opnd_array(uint operand_index) const { |
| 44080 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44081 | return _opnd_array[operand_index]; |
| 44082 | } |
| 44083 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44084 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44085 | _opnd_array[operand_index] = operand; |
| 44086 | } |
| 44087 | private: |
| 44088 | virtual const RegMask &out_RegMask() const; |
| 44089 | virtual uint rule() const { return vshift64B_avx_rule; } |
| 44090 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44091 | virtual int ideal_Opcode() const { return Op_LShiftVB; } |
| 44092 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44093 | virtual uint oper_input_base() const { return 1; } |
| 44094 | public: |
| 44095 | vshift64B_avxNode() { _num_opnds = 7; _opnds = _opnd_array; } |
| 44096 | virtual uint size_of() const { return sizeof(vshift64B_avxNode); } |
| 44097 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44098 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44099 | static const Pipeline *pipeline_class(); |
| 44100 | virtual const Pipeline *pipeline() const; |
| 44101 | #ifndef PRODUCT |
| 44102 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44103 | virtual const char *Name() const { return "vshift64B_avx";} |
| 44104 | #endif |
| 44105 | }; |
| 44106 | |
| 44107 | class vshift64B_avx_0Node : public MachTypeNode { |
| 44108 | private: |
| 44109 | MachOper *_opnd_array[7]; |
| 44110 | public: |
| 44111 | MachOper *opnd_array(uint operand_index) const { |
| 44112 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44113 | return _opnd_array[operand_index]; |
| 44114 | } |
| 44115 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44116 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44117 | _opnd_array[operand_index] = operand; |
| 44118 | } |
| 44119 | private: |
| 44120 | virtual const RegMask &out_RegMask() const; |
| 44121 | virtual uint rule() const { return vshift64B_avx_0_rule; } |
| 44122 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44123 | virtual int ideal_Opcode() const { return Op_RShiftVB; } |
| 44124 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44125 | virtual uint oper_input_base() const { return 1; } |
| 44126 | public: |
| 44127 | vshift64B_avx_0Node() { _num_opnds = 7; _opnds = _opnd_array; } |
| 44128 | virtual uint size_of() const { return sizeof(vshift64B_avx_0Node); } |
| 44129 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44130 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44131 | static const Pipeline *pipeline_class(); |
| 44132 | virtual const Pipeline *pipeline() const; |
| 44133 | #ifndef PRODUCT |
| 44134 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44135 | virtual const char *Name() const { return "vshift64B_avx_0";} |
| 44136 | #endif |
| 44137 | }; |
| 44138 | |
| 44139 | class vshift64B_avx_1Node : public MachTypeNode { |
| 44140 | private: |
| 44141 | MachOper *_opnd_array[7]; |
| 44142 | public: |
| 44143 | MachOper *opnd_array(uint operand_index) const { |
| 44144 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44145 | return _opnd_array[operand_index]; |
| 44146 | } |
| 44147 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44148 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44149 | _opnd_array[operand_index] = operand; |
| 44150 | } |
| 44151 | private: |
| 44152 | virtual const RegMask &out_RegMask() const; |
| 44153 | virtual uint rule() const { return vshift64B_avx_1_rule; } |
| 44154 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44155 | virtual int ideal_Opcode() const { return Op_URShiftVB; } |
| 44156 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44157 | virtual uint oper_input_base() const { return 1; } |
| 44158 | public: |
| 44159 | vshift64B_avx_1Node() { _num_opnds = 7; _opnds = _opnd_array; } |
| 44160 | virtual uint size_of() const { return sizeof(vshift64B_avx_1Node); } |
| 44161 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44162 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44163 | static const Pipeline *pipeline_class(); |
| 44164 | virtual const Pipeline *pipeline() const; |
| 44165 | #ifndef PRODUCT |
| 44166 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44167 | virtual const char *Name() const { return "vshift64B_avx_1";} |
| 44168 | #endif |
| 44169 | }; |
| 44170 | |
| 44171 | class vshist2SNode : public MachTypeNode { |
| 44172 | private: |
| 44173 | MachOper *_opnd_array[4]; |
| 44174 | public: |
| 44175 | MachOper *opnd_array(uint operand_index) const { |
| 44176 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44177 | return _opnd_array[operand_index]; |
| 44178 | } |
| 44179 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44180 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44181 | _opnd_array[operand_index] = operand; |
| 44182 | } |
| 44183 | private: |
| 44184 | virtual const RegMask &out_RegMask() const; |
| 44185 | virtual uint rule() const { return vshist2S_rule; } |
| 44186 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44187 | virtual int ideal_Opcode() const { return Op_LShiftVS; } |
| 44188 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44189 | virtual uint oper_input_base() const { return 1; } |
| 44190 | public: |
| 44191 | vshist2SNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44192 | virtual uint size_of() const { return sizeof(vshist2SNode); } |
| 44193 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44194 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44195 | static const Pipeline *pipeline_class(); |
| 44196 | virtual const Pipeline *pipeline() const; |
| 44197 | #ifndef PRODUCT |
| 44198 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44199 | virtual const char *Name() const { return "vshist2S";} |
| 44200 | #endif |
| 44201 | }; |
| 44202 | |
| 44203 | class vshist2S_0Node : public MachTypeNode { |
| 44204 | private: |
| 44205 | MachOper *_opnd_array[4]; |
| 44206 | public: |
| 44207 | MachOper *opnd_array(uint operand_index) const { |
| 44208 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44209 | return _opnd_array[operand_index]; |
| 44210 | } |
| 44211 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44212 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44213 | _opnd_array[operand_index] = operand; |
| 44214 | } |
| 44215 | private: |
| 44216 | virtual const RegMask &out_RegMask() const; |
| 44217 | virtual uint rule() const { return vshist2S_0_rule; } |
| 44218 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44219 | virtual int ideal_Opcode() const { return Op_RShiftVS; } |
| 44220 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44221 | virtual uint oper_input_base() const { return 1; } |
| 44222 | public: |
| 44223 | vshist2S_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44224 | virtual uint size_of() const { return sizeof(vshist2S_0Node); } |
| 44225 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44226 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44227 | static const Pipeline *pipeline_class(); |
| 44228 | virtual const Pipeline *pipeline() const; |
| 44229 | #ifndef PRODUCT |
| 44230 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44231 | virtual const char *Name() const { return "vshist2S_0";} |
| 44232 | #endif |
| 44233 | }; |
| 44234 | |
| 44235 | class vshist2S_1Node : public MachTypeNode { |
| 44236 | private: |
| 44237 | MachOper *_opnd_array[4]; |
| 44238 | public: |
| 44239 | MachOper *opnd_array(uint operand_index) const { |
| 44240 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44241 | return _opnd_array[operand_index]; |
| 44242 | } |
| 44243 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44244 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44245 | _opnd_array[operand_index] = operand; |
| 44246 | } |
| 44247 | private: |
| 44248 | virtual const RegMask &out_RegMask() const; |
| 44249 | virtual uint rule() const { return vshist2S_1_rule; } |
| 44250 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44251 | virtual int ideal_Opcode() const { return Op_URShiftVS; } |
| 44252 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44253 | virtual uint oper_input_base() const { return 1; } |
| 44254 | public: |
| 44255 | vshist2S_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44256 | virtual uint size_of() const { return sizeof(vshist2S_1Node); } |
| 44257 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44258 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44259 | static const Pipeline *pipeline_class(); |
| 44260 | virtual const Pipeline *pipeline() const; |
| 44261 | #ifndef PRODUCT |
| 44262 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44263 | virtual const char *Name() const { return "vshist2S_1";} |
| 44264 | #endif |
| 44265 | }; |
| 44266 | |
| 44267 | class vshift4SNode : public MachTypeNode { |
| 44268 | private: |
| 44269 | MachOper *_opnd_array[4]; |
| 44270 | public: |
| 44271 | MachOper *opnd_array(uint operand_index) const { |
| 44272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44273 | return _opnd_array[operand_index]; |
| 44274 | } |
| 44275 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44276 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44277 | _opnd_array[operand_index] = operand; |
| 44278 | } |
| 44279 | private: |
| 44280 | virtual const RegMask &out_RegMask() const; |
| 44281 | virtual uint rule() const { return vshift4S_rule; } |
| 44282 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44283 | virtual int ideal_Opcode() const { return Op_LShiftVS; } |
| 44284 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44285 | virtual uint oper_input_base() const { return 1; } |
| 44286 | public: |
| 44287 | vshift4SNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44288 | virtual uint size_of() const { return sizeof(vshift4SNode); } |
| 44289 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44290 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44291 | static const Pipeline *pipeline_class(); |
| 44292 | virtual const Pipeline *pipeline() const; |
| 44293 | #ifndef PRODUCT |
| 44294 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44295 | virtual const char *Name() const { return "vshift4S";} |
| 44296 | #endif |
| 44297 | }; |
| 44298 | |
| 44299 | class vshift4S_0Node : public MachTypeNode { |
| 44300 | private: |
| 44301 | MachOper *_opnd_array[4]; |
| 44302 | public: |
| 44303 | MachOper *opnd_array(uint operand_index) const { |
| 44304 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44305 | return _opnd_array[operand_index]; |
| 44306 | } |
| 44307 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44308 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44309 | _opnd_array[operand_index] = operand; |
| 44310 | } |
| 44311 | private: |
| 44312 | virtual const RegMask &out_RegMask() const; |
| 44313 | virtual uint rule() const { return vshift4S_0_rule; } |
| 44314 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44315 | virtual int ideal_Opcode() const { return Op_RShiftVS; } |
| 44316 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44317 | virtual uint oper_input_base() const { return 1; } |
| 44318 | public: |
| 44319 | vshift4S_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44320 | virtual uint size_of() const { return sizeof(vshift4S_0Node); } |
| 44321 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44322 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44323 | static const Pipeline *pipeline_class(); |
| 44324 | virtual const Pipeline *pipeline() const; |
| 44325 | #ifndef PRODUCT |
| 44326 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44327 | virtual const char *Name() const { return "vshift4S_0";} |
| 44328 | #endif |
| 44329 | }; |
| 44330 | |
| 44331 | class vshift4S_1Node : public MachTypeNode { |
| 44332 | private: |
| 44333 | MachOper *_opnd_array[4]; |
| 44334 | public: |
| 44335 | MachOper *opnd_array(uint operand_index) const { |
| 44336 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44337 | return _opnd_array[operand_index]; |
| 44338 | } |
| 44339 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44340 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44341 | _opnd_array[operand_index] = operand; |
| 44342 | } |
| 44343 | private: |
| 44344 | virtual const RegMask &out_RegMask() const; |
| 44345 | virtual uint rule() const { return vshift4S_1_rule; } |
| 44346 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44347 | virtual int ideal_Opcode() const { return Op_URShiftVS; } |
| 44348 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44349 | virtual uint oper_input_base() const { return 1; } |
| 44350 | public: |
| 44351 | vshift4S_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44352 | virtual uint size_of() const { return sizeof(vshift4S_1Node); } |
| 44353 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44354 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44355 | static const Pipeline *pipeline_class(); |
| 44356 | virtual const Pipeline *pipeline() const; |
| 44357 | #ifndef PRODUCT |
| 44358 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44359 | virtual const char *Name() const { return "vshift4S_1";} |
| 44360 | #endif |
| 44361 | }; |
| 44362 | |
| 44363 | class vshift8SNode : public MachTypeNode { |
| 44364 | private: |
| 44365 | MachOper *_opnd_array[4]; |
| 44366 | public: |
| 44367 | MachOper *opnd_array(uint operand_index) const { |
| 44368 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44369 | return _opnd_array[operand_index]; |
| 44370 | } |
| 44371 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44372 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44373 | _opnd_array[operand_index] = operand; |
| 44374 | } |
| 44375 | private: |
| 44376 | virtual const RegMask &out_RegMask() const; |
| 44377 | virtual uint rule() const { return vshift8S_rule; } |
| 44378 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44379 | virtual int ideal_Opcode() const { return Op_LShiftVS; } |
| 44380 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44381 | virtual uint oper_input_base() const { return 1; } |
| 44382 | public: |
| 44383 | vshift8SNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44384 | virtual uint size_of() const { return sizeof(vshift8SNode); } |
| 44385 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44386 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44387 | static const Pipeline *pipeline_class(); |
| 44388 | virtual const Pipeline *pipeline() const; |
| 44389 | #ifndef PRODUCT |
| 44390 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44391 | virtual const char *Name() const { return "vshift8S";} |
| 44392 | #endif |
| 44393 | }; |
| 44394 | |
| 44395 | class vshift8S_0Node : public MachTypeNode { |
| 44396 | private: |
| 44397 | MachOper *_opnd_array[4]; |
| 44398 | public: |
| 44399 | MachOper *opnd_array(uint operand_index) const { |
| 44400 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44401 | return _opnd_array[operand_index]; |
| 44402 | } |
| 44403 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44404 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44405 | _opnd_array[operand_index] = operand; |
| 44406 | } |
| 44407 | private: |
| 44408 | virtual const RegMask &out_RegMask() const; |
| 44409 | virtual uint rule() const { return vshift8S_0_rule; } |
| 44410 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44411 | virtual int ideal_Opcode() const { return Op_RShiftVS; } |
| 44412 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44413 | virtual uint oper_input_base() const { return 1; } |
| 44414 | public: |
| 44415 | vshift8S_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44416 | virtual uint size_of() const { return sizeof(vshift8S_0Node); } |
| 44417 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44418 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44419 | static const Pipeline *pipeline_class(); |
| 44420 | virtual const Pipeline *pipeline() const; |
| 44421 | #ifndef PRODUCT |
| 44422 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44423 | virtual const char *Name() const { return "vshift8S_0";} |
| 44424 | #endif |
| 44425 | }; |
| 44426 | |
| 44427 | class vshift8S_1Node : public MachTypeNode { |
| 44428 | private: |
| 44429 | MachOper *_opnd_array[4]; |
| 44430 | public: |
| 44431 | MachOper *opnd_array(uint operand_index) const { |
| 44432 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44433 | return _opnd_array[operand_index]; |
| 44434 | } |
| 44435 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44436 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44437 | _opnd_array[operand_index] = operand; |
| 44438 | } |
| 44439 | private: |
| 44440 | virtual const RegMask &out_RegMask() const; |
| 44441 | virtual uint rule() const { return vshift8S_1_rule; } |
| 44442 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44443 | virtual int ideal_Opcode() const { return Op_URShiftVS; } |
| 44444 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44445 | virtual uint oper_input_base() const { return 1; } |
| 44446 | public: |
| 44447 | vshift8S_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44448 | virtual uint size_of() const { return sizeof(vshift8S_1Node); } |
| 44449 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44450 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44451 | static const Pipeline *pipeline_class(); |
| 44452 | virtual const Pipeline *pipeline() const; |
| 44453 | #ifndef PRODUCT |
| 44454 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44455 | virtual const char *Name() const { return "vshift8S_1";} |
| 44456 | #endif |
| 44457 | }; |
| 44458 | |
| 44459 | class vshift16SNode : public MachTypeNode { |
| 44460 | private: |
| 44461 | MachOper *_opnd_array[3]; |
| 44462 | public: |
| 44463 | MachOper *opnd_array(uint operand_index) const { |
| 44464 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44465 | return _opnd_array[operand_index]; |
| 44466 | } |
| 44467 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44468 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44469 | _opnd_array[operand_index] = operand; |
| 44470 | } |
| 44471 | private: |
| 44472 | virtual const RegMask &out_RegMask() const; |
| 44473 | virtual uint rule() const { return vshift16S_rule; } |
| 44474 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44475 | virtual int ideal_Opcode() const { return Op_LShiftVS; } |
| 44476 | virtual uint oper_input_base() const { return 1; } |
| 44477 | public: |
| 44478 | vshift16SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44479 | virtual uint size_of() const { return sizeof(vshift16SNode); } |
| 44480 | static const Pipeline *pipeline_class(); |
| 44481 | virtual const Pipeline *pipeline() const; |
| 44482 | #ifndef PRODUCT |
| 44483 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44484 | virtual const char *Name() const { return "vshift16S";} |
| 44485 | #endif |
| 44486 | }; |
| 44487 | |
| 44488 | class vshift16S_0Node : public MachTypeNode { |
| 44489 | private: |
| 44490 | MachOper *_opnd_array[3]; |
| 44491 | public: |
| 44492 | MachOper *opnd_array(uint operand_index) const { |
| 44493 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44494 | return _opnd_array[operand_index]; |
| 44495 | } |
| 44496 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44497 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44498 | _opnd_array[operand_index] = operand; |
| 44499 | } |
| 44500 | private: |
| 44501 | virtual const RegMask &out_RegMask() const; |
| 44502 | virtual uint rule() const { return vshift16S_0_rule; } |
| 44503 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44504 | virtual int ideal_Opcode() const { return Op_RShiftVS; } |
| 44505 | virtual uint oper_input_base() const { return 1; } |
| 44506 | public: |
| 44507 | vshift16S_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44508 | virtual uint size_of() const { return sizeof(vshift16S_0Node); } |
| 44509 | static const Pipeline *pipeline_class(); |
| 44510 | virtual const Pipeline *pipeline() const; |
| 44511 | #ifndef PRODUCT |
| 44512 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44513 | virtual const char *Name() const { return "vshift16S_0";} |
| 44514 | #endif |
| 44515 | }; |
| 44516 | |
| 44517 | class vshift16S_1Node : public MachTypeNode { |
| 44518 | private: |
| 44519 | MachOper *_opnd_array[3]; |
| 44520 | public: |
| 44521 | MachOper *opnd_array(uint operand_index) const { |
| 44522 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44523 | return _opnd_array[operand_index]; |
| 44524 | } |
| 44525 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44526 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44527 | _opnd_array[operand_index] = operand; |
| 44528 | } |
| 44529 | private: |
| 44530 | virtual const RegMask &out_RegMask() const; |
| 44531 | virtual uint rule() const { return vshift16S_1_rule; } |
| 44532 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44533 | virtual int ideal_Opcode() const { return Op_URShiftVS; } |
| 44534 | virtual uint oper_input_base() const { return 1; } |
| 44535 | public: |
| 44536 | vshift16S_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44537 | virtual uint size_of() const { return sizeof(vshift16S_1Node); } |
| 44538 | static const Pipeline *pipeline_class(); |
| 44539 | virtual const Pipeline *pipeline() const; |
| 44540 | #ifndef PRODUCT |
| 44541 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44542 | virtual const char *Name() const { return "vshift16S_1";} |
| 44543 | #endif |
| 44544 | }; |
| 44545 | |
| 44546 | class vshift32SNode : public MachTypeNode { |
| 44547 | private: |
| 44548 | MachOper *_opnd_array[3]; |
| 44549 | public: |
| 44550 | MachOper *opnd_array(uint operand_index) const { |
| 44551 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44552 | return _opnd_array[operand_index]; |
| 44553 | } |
| 44554 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44555 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44556 | _opnd_array[operand_index] = operand; |
| 44557 | } |
| 44558 | private: |
| 44559 | virtual const RegMask &out_RegMask() const; |
| 44560 | virtual uint rule() const { return vshift32S_rule; } |
| 44561 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44562 | virtual int ideal_Opcode() const { return Op_LShiftVS; } |
| 44563 | virtual uint oper_input_base() const { return 1; } |
| 44564 | public: |
| 44565 | vshift32SNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44566 | virtual uint size_of() const { return sizeof(vshift32SNode); } |
| 44567 | static const Pipeline *pipeline_class(); |
| 44568 | virtual const Pipeline *pipeline() const; |
| 44569 | #ifndef PRODUCT |
| 44570 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44571 | virtual const char *Name() const { return "vshift32S";} |
| 44572 | #endif |
| 44573 | }; |
| 44574 | |
| 44575 | class vshift32S_0Node : public MachTypeNode { |
| 44576 | private: |
| 44577 | MachOper *_opnd_array[3]; |
| 44578 | public: |
| 44579 | MachOper *opnd_array(uint operand_index) const { |
| 44580 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44581 | return _opnd_array[operand_index]; |
| 44582 | } |
| 44583 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44584 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44585 | _opnd_array[operand_index] = operand; |
| 44586 | } |
| 44587 | private: |
| 44588 | virtual const RegMask &out_RegMask() const; |
| 44589 | virtual uint rule() const { return vshift32S_0_rule; } |
| 44590 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44591 | virtual int ideal_Opcode() const { return Op_RShiftVS; } |
| 44592 | virtual uint oper_input_base() const { return 1; } |
| 44593 | public: |
| 44594 | vshift32S_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44595 | virtual uint size_of() const { return sizeof(vshift32S_0Node); } |
| 44596 | static const Pipeline *pipeline_class(); |
| 44597 | virtual const Pipeline *pipeline() const; |
| 44598 | #ifndef PRODUCT |
| 44599 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44600 | virtual const char *Name() const { return "vshift32S_0";} |
| 44601 | #endif |
| 44602 | }; |
| 44603 | |
| 44604 | class vshift32S_1Node : public MachTypeNode { |
| 44605 | private: |
| 44606 | MachOper *_opnd_array[3]; |
| 44607 | public: |
| 44608 | MachOper *opnd_array(uint operand_index) const { |
| 44609 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44610 | return _opnd_array[operand_index]; |
| 44611 | } |
| 44612 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44613 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44614 | _opnd_array[operand_index] = operand; |
| 44615 | } |
| 44616 | private: |
| 44617 | virtual const RegMask &out_RegMask() const; |
| 44618 | virtual uint rule() const { return vshift32S_1_rule; } |
| 44619 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44620 | virtual int ideal_Opcode() const { return Op_URShiftVS; } |
| 44621 | virtual uint oper_input_base() const { return 1; } |
| 44622 | public: |
| 44623 | vshift32S_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44624 | virtual uint size_of() const { return sizeof(vshift32S_1Node); } |
| 44625 | static const Pipeline *pipeline_class(); |
| 44626 | virtual const Pipeline *pipeline() const; |
| 44627 | #ifndef PRODUCT |
| 44628 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44629 | virtual const char *Name() const { return "vshift32S_1";} |
| 44630 | #endif |
| 44631 | }; |
| 44632 | |
| 44633 | class vshift2INode : public MachTypeNode { |
| 44634 | private: |
| 44635 | MachOper *_opnd_array[4]; |
| 44636 | public: |
| 44637 | MachOper *opnd_array(uint operand_index) const { |
| 44638 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44639 | return _opnd_array[operand_index]; |
| 44640 | } |
| 44641 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44642 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44643 | _opnd_array[operand_index] = operand; |
| 44644 | } |
| 44645 | private: |
| 44646 | virtual const RegMask &out_RegMask() const; |
| 44647 | virtual uint rule() const { return vshift2I_rule; } |
| 44648 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44649 | virtual int ideal_Opcode() const { return Op_LShiftVI; } |
| 44650 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44651 | virtual uint oper_input_base() const { return 1; } |
| 44652 | public: |
| 44653 | vshift2INode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44654 | virtual uint size_of() const { return sizeof(vshift2INode); } |
| 44655 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44656 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44657 | static const Pipeline *pipeline_class(); |
| 44658 | virtual const Pipeline *pipeline() const; |
| 44659 | #ifndef PRODUCT |
| 44660 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44661 | virtual const char *Name() const { return "vshift2I";} |
| 44662 | #endif |
| 44663 | }; |
| 44664 | |
| 44665 | class vshift2I_0Node : public MachTypeNode { |
| 44666 | private: |
| 44667 | MachOper *_opnd_array[4]; |
| 44668 | public: |
| 44669 | MachOper *opnd_array(uint operand_index) const { |
| 44670 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44671 | return _opnd_array[operand_index]; |
| 44672 | } |
| 44673 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44674 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44675 | _opnd_array[operand_index] = operand; |
| 44676 | } |
| 44677 | private: |
| 44678 | virtual const RegMask &out_RegMask() const; |
| 44679 | virtual uint rule() const { return vshift2I_0_rule; } |
| 44680 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44681 | virtual int ideal_Opcode() const { return Op_RShiftVI; } |
| 44682 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44683 | virtual uint oper_input_base() const { return 1; } |
| 44684 | public: |
| 44685 | vshift2I_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44686 | virtual uint size_of() const { return sizeof(vshift2I_0Node); } |
| 44687 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44688 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44689 | static const Pipeline *pipeline_class(); |
| 44690 | virtual const Pipeline *pipeline() const; |
| 44691 | #ifndef PRODUCT |
| 44692 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44693 | virtual const char *Name() const { return "vshift2I_0";} |
| 44694 | #endif |
| 44695 | }; |
| 44696 | |
| 44697 | class vshift2I_1Node : public MachTypeNode { |
| 44698 | private: |
| 44699 | MachOper *_opnd_array[4]; |
| 44700 | public: |
| 44701 | MachOper *opnd_array(uint operand_index) const { |
| 44702 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44703 | return _opnd_array[operand_index]; |
| 44704 | } |
| 44705 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44706 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44707 | _opnd_array[operand_index] = operand; |
| 44708 | } |
| 44709 | private: |
| 44710 | virtual const RegMask &out_RegMask() const; |
| 44711 | virtual uint rule() const { return vshift2I_1_rule; } |
| 44712 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44713 | virtual int ideal_Opcode() const { return Op_URShiftVI; } |
| 44714 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44715 | virtual uint oper_input_base() const { return 1; } |
| 44716 | public: |
| 44717 | vshift2I_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44718 | virtual uint size_of() const { return sizeof(vshift2I_1Node); } |
| 44719 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44720 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44721 | static const Pipeline *pipeline_class(); |
| 44722 | virtual const Pipeline *pipeline() const; |
| 44723 | #ifndef PRODUCT |
| 44724 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44725 | virtual const char *Name() const { return "vshift2I_1";} |
| 44726 | #endif |
| 44727 | }; |
| 44728 | |
| 44729 | class vshift4INode : public MachTypeNode { |
| 44730 | private: |
| 44731 | MachOper *_opnd_array[4]; |
| 44732 | public: |
| 44733 | MachOper *opnd_array(uint operand_index) const { |
| 44734 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44735 | return _opnd_array[operand_index]; |
| 44736 | } |
| 44737 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44738 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44739 | _opnd_array[operand_index] = operand; |
| 44740 | } |
| 44741 | private: |
| 44742 | virtual const RegMask &out_RegMask() const; |
| 44743 | virtual uint rule() const { return vshift4I_rule; } |
| 44744 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44745 | virtual int ideal_Opcode() const { return Op_LShiftVI; } |
| 44746 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44747 | virtual uint oper_input_base() const { return 1; } |
| 44748 | public: |
| 44749 | vshift4INode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44750 | virtual uint size_of() const { return sizeof(vshift4INode); } |
| 44751 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44752 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44753 | static const Pipeline *pipeline_class(); |
| 44754 | virtual const Pipeline *pipeline() const; |
| 44755 | #ifndef PRODUCT |
| 44756 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44757 | virtual const char *Name() const { return "vshift4I";} |
| 44758 | #endif |
| 44759 | }; |
| 44760 | |
| 44761 | class vshift4I_0Node : public MachTypeNode { |
| 44762 | private: |
| 44763 | MachOper *_opnd_array[4]; |
| 44764 | public: |
| 44765 | MachOper *opnd_array(uint operand_index) const { |
| 44766 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44767 | return _opnd_array[operand_index]; |
| 44768 | } |
| 44769 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44770 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44771 | _opnd_array[operand_index] = operand; |
| 44772 | } |
| 44773 | private: |
| 44774 | virtual const RegMask &out_RegMask() const; |
| 44775 | virtual uint rule() const { return vshift4I_0_rule; } |
| 44776 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44777 | virtual int ideal_Opcode() const { return Op_RShiftVI; } |
| 44778 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44779 | virtual uint oper_input_base() const { return 1; } |
| 44780 | public: |
| 44781 | vshift4I_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44782 | virtual uint size_of() const { return sizeof(vshift4I_0Node); } |
| 44783 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44784 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44785 | static const Pipeline *pipeline_class(); |
| 44786 | virtual const Pipeline *pipeline() const; |
| 44787 | #ifndef PRODUCT |
| 44788 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44789 | virtual const char *Name() const { return "vshift4I_0";} |
| 44790 | #endif |
| 44791 | }; |
| 44792 | |
| 44793 | class vshift4I_1Node : public MachTypeNode { |
| 44794 | private: |
| 44795 | MachOper *_opnd_array[4]; |
| 44796 | public: |
| 44797 | MachOper *opnd_array(uint operand_index) const { |
| 44798 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44799 | return _opnd_array[operand_index]; |
| 44800 | } |
| 44801 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44802 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44803 | _opnd_array[operand_index] = operand; |
| 44804 | } |
| 44805 | private: |
| 44806 | virtual const RegMask &out_RegMask() const; |
| 44807 | virtual uint rule() const { return vshift4I_1_rule; } |
| 44808 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44809 | virtual int ideal_Opcode() const { return Op_URShiftVI; } |
| 44810 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 44811 | virtual uint oper_input_base() const { return 1; } |
| 44812 | public: |
| 44813 | vshift4I_1Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 44814 | virtual uint size_of() const { return sizeof(vshift4I_1Node); } |
| 44815 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 44816 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 44817 | static const Pipeline *pipeline_class(); |
| 44818 | virtual const Pipeline *pipeline() const; |
| 44819 | #ifndef PRODUCT |
| 44820 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44821 | virtual const char *Name() const { return "vshift4I_1";} |
| 44822 | #endif |
| 44823 | }; |
| 44824 | |
| 44825 | class vshift8INode : public MachTypeNode { |
| 44826 | private: |
| 44827 | MachOper *_opnd_array[3]; |
| 44828 | public: |
| 44829 | MachOper *opnd_array(uint operand_index) const { |
| 44830 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44831 | return _opnd_array[operand_index]; |
| 44832 | } |
| 44833 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44834 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44835 | _opnd_array[operand_index] = operand; |
| 44836 | } |
| 44837 | private: |
| 44838 | virtual const RegMask &out_RegMask() const; |
| 44839 | virtual uint rule() const { return vshift8I_rule; } |
| 44840 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44841 | virtual int ideal_Opcode() const { return Op_LShiftVI; } |
| 44842 | virtual uint oper_input_base() const { return 1; } |
| 44843 | public: |
| 44844 | vshift8INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44845 | virtual uint size_of() const { return sizeof(vshift8INode); } |
| 44846 | static const Pipeline *pipeline_class(); |
| 44847 | virtual const Pipeline *pipeline() const; |
| 44848 | #ifndef PRODUCT |
| 44849 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44850 | virtual const char *Name() const { return "vshift8I";} |
| 44851 | #endif |
| 44852 | }; |
| 44853 | |
| 44854 | class vshift8I_0Node : public MachTypeNode { |
| 44855 | private: |
| 44856 | MachOper *_opnd_array[3]; |
| 44857 | public: |
| 44858 | MachOper *opnd_array(uint operand_index) const { |
| 44859 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44860 | return _opnd_array[operand_index]; |
| 44861 | } |
| 44862 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44863 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44864 | _opnd_array[operand_index] = operand; |
| 44865 | } |
| 44866 | private: |
| 44867 | virtual const RegMask &out_RegMask() const; |
| 44868 | virtual uint rule() const { return vshift8I_0_rule; } |
| 44869 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44870 | virtual int ideal_Opcode() const { return Op_RShiftVI; } |
| 44871 | virtual uint oper_input_base() const { return 1; } |
| 44872 | public: |
| 44873 | vshift8I_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44874 | virtual uint size_of() const { return sizeof(vshift8I_0Node); } |
| 44875 | static const Pipeline *pipeline_class(); |
| 44876 | virtual const Pipeline *pipeline() const; |
| 44877 | #ifndef PRODUCT |
| 44878 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44879 | virtual const char *Name() const { return "vshift8I_0";} |
| 44880 | #endif |
| 44881 | }; |
| 44882 | |
| 44883 | class vshift8I_1Node : public MachTypeNode { |
| 44884 | private: |
| 44885 | MachOper *_opnd_array[3]; |
| 44886 | public: |
| 44887 | MachOper *opnd_array(uint operand_index) const { |
| 44888 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44889 | return _opnd_array[operand_index]; |
| 44890 | } |
| 44891 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44892 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44893 | _opnd_array[operand_index] = operand; |
| 44894 | } |
| 44895 | private: |
| 44896 | virtual const RegMask &out_RegMask() const; |
| 44897 | virtual uint rule() const { return vshift8I_1_rule; } |
| 44898 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44899 | virtual int ideal_Opcode() const { return Op_URShiftVI; } |
| 44900 | virtual uint oper_input_base() const { return 1; } |
| 44901 | public: |
| 44902 | vshift8I_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44903 | virtual uint size_of() const { return sizeof(vshift8I_1Node); } |
| 44904 | static const Pipeline *pipeline_class(); |
| 44905 | virtual const Pipeline *pipeline() const; |
| 44906 | #ifndef PRODUCT |
| 44907 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44908 | virtual const char *Name() const { return "vshift8I_1";} |
| 44909 | #endif |
| 44910 | }; |
| 44911 | |
| 44912 | class vshift16INode : public MachTypeNode { |
| 44913 | private: |
| 44914 | MachOper *_opnd_array[3]; |
| 44915 | public: |
| 44916 | MachOper *opnd_array(uint operand_index) const { |
| 44917 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44918 | return _opnd_array[operand_index]; |
| 44919 | } |
| 44920 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44921 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44922 | _opnd_array[operand_index] = operand; |
| 44923 | } |
| 44924 | private: |
| 44925 | virtual const RegMask &out_RegMask() const; |
| 44926 | virtual uint rule() const { return vshift16I_rule; } |
| 44927 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44928 | virtual int ideal_Opcode() const { return Op_LShiftVI; } |
| 44929 | virtual uint oper_input_base() const { return 1; } |
| 44930 | public: |
| 44931 | vshift16INode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44932 | virtual uint size_of() const { return sizeof(vshift16INode); } |
| 44933 | static const Pipeline *pipeline_class(); |
| 44934 | virtual const Pipeline *pipeline() const; |
| 44935 | #ifndef PRODUCT |
| 44936 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44937 | virtual const char *Name() const { return "vshift16I";} |
| 44938 | #endif |
| 44939 | }; |
| 44940 | |
| 44941 | class vshift16I_0Node : public MachTypeNode { |
| 44942 | private: |
| 44943 | MachOper *_opnd_array[3]; |
| 44944 | public: |
| 44945 | MachOper *opnd_array(uint operand_index) const { |
| 44946 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44947 | return _opnd_array[operand_index]; |
| 44948 | } |
| 44949 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44950 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44951 | _opnd_array[operand_index] = operand; |
| 44952 | } |
| 44953 | private: |
| 44954 | virtual const RegMask &out_RegMask() const; |
| 44955 | virtual uint rule() const { return vshift16I_0_rule; } |
| 44956 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44957 | virtual int ideal_Opcode() const { return Op_RShiftVI; } |
| 44958 | virtual uint oper_input_base() const { return 1; } |
| 44959 | public: |
| 44960 | vshift16I_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44961 | virtual uint size_of() const { return sizeof(vshift16I_0Node); } |
| 44962 | static const Pipeline *pipeline_class(); |
| 44963 | virtual const Pipeline *pipeline() const; |
| 44964 | #ifndef PRODUCT |
| 44965 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44966 | virtual const char *Name() const { return "vshift16I_0";} |
| 44967 | #endif |
| 44968 | }; |
| 44969 | |
| 44970 | class vshift16I_1Node : public MachTypeNode { |
| 44971 | private: |
| 44972 | MachOper *_opnd_array[3]; |
| 44973 | public: |
| 44974 | MachOper *opnd_array(uint operand_index) const { |
| 44975 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44976 | return _opnd_array[operand_index]; |
| 44977 | } |
| 44978 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 44979 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 44980 | _opnd_array[operand_index] = operand; |
| 44981 | } |
| 44982 | private: |
| 44983 | virtual const RegMask &out_RegMask() const; |
| 44984 | virtual uint rule() const { return vshift16I_1_rule; } |
| 44985 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 44986 | virtual int ideal_Opcode() const { return Op_URShiftVI; } |
| 44987 | virtual uint oper_input_base() const { return 1; } |
| 44988 | public: |
| 44989 | vshift16I_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 44990 | virtual uint size_of() const { return sizeof(vshift16I_1Node); } |
| 44991 | static const Pipeline *pipeline_class(); |
| 44992 | virtual const Pipeline *pipeline() const; |
| 44993 | #ifndef PRODUCT |
| 44994 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 44995 | virtual const char *Name() const { return "vshift16I_1";} |
| 44996 | #endif |
| 44997 | }; |
| 44998 | |
| 44999 | class vshift2LNode : public MachTypeNode { |
| 45000 | private: |
| 45001 | MachOper *_opnd_array[4]; |
| 45002 | public: |
| 45003 | MachOper *opnd_array(uint operand_index) const { |
| 45004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45005 | return _opnd_array[operand_index]; |
| 45006 | } |
| 45007 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45008 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45009 | _opnd_array[operand_index] = operand; |
| 45010 | } |
| 45011 | private: |
| 45012 | virtual const RegMask &out_RegMask() const; |
| 45013 | virtual uint rule() const { return vshift2L_rule; } |
| 45014 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45015 | virtual int ideal_Opcode() const { return Op_LShiftVL; } |
| 45016 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 45017 | virtual uint oper_input_base() const { return 1; } |
| 45018 | public: |
| 45019 | vshift2LNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 45020 | virtual uint size_of() const { return sizeof(vshift2LNode); } |
| 45021 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 45022 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 45023 | static const Pipeline *pipeline_class(); |
| 45024 | virtual const Pipeline *pipeline() const; |
| 45025 | #ifndef PRODUCT |
| 45026 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45027 | virtual const char *Name() const { return "vshift2L";} |
| 45028 | #endif |
| 45029 | }; |
| 45030 | |
| 45031 | class vshift2L_0Node : public MachTypeNode { |
| 45032 | private: |
| 45033 | MachOper *_opnd_array[4]; |
| 45034 | public: |
| 45035 | MachOper *opnd_array(uint operand_index) const { |
| 45036 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45037 | return _opnd_array[operand_index]; |
| 45038 | } |
| 45039 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45041 | _opnd_array[operand_index] = operand; |
| 45042 | } |
| 45043 | private: |
| 45044 | virtual const RegMask &out_RegMask() const; |
| 45045 | virtual uint rule() const { return vshift2L_0_rule; } |
| 45046 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45047 | virtual int ideal_Opcode() const { return Op_URShiftVL; } |
| 45048 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 45049 | virtual uint oper_input_base() const { return 1; } |
| 45050 | public: |
| 45051 | vshift2L_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 45052 | virtual uint size_of() const { return sizeof(vshift2L_0Node); } |
| 45053 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 45054 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 45055 | static const Pipeline *pipeline_class(); |
| 45056 | virtual const Pipeline *pipeline() const; |
| 45057 | #ifndef PRODUCT |
| 45058 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45059 | virtual const char *Name() const { return "vshift2L_0";} |
| 45060 | #endif |
| 45061 | }; |
| 45062 | |
| 45063 | class vshift4LNode : public MachTypeNode { |
| 45064 | private: |
| 45065 | MachOper *_opnd_array[3]; |
| 45066 | public: |
| 45067 | MachOper *opnd_array(uint operand_index) const { |
| 45068 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45069 | return _opnd_array[operand_index]; |
| 45070 | } |
| 45071 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45072 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45073 | _opnd_array[operand_index] = operand; |
| 45074 | } |
| 45075 | private: |
| 45076 | virtual const RegMask &out_RegMask() const; |
| 45077 | virtual uint rule() const { return vshift4L_rule; } |
| 45078 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45079 | virtual int ideal_Opcode() const { return Op_LShiftVL; } |
| 45080 | virtual uint oper_input_base() const { return 1; } |
| 45081 | public: |
| 45082 | vshift4LNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45083 | virtual uint size_of() const { return sizeof(vshift4LNode); } |
| 45084 | static const Pipeline *pipeline_class(); |
| 45085 | virtual const Pipeline *pipeline() const; |
| 45086 | #ifndef PRODUCT |
| 45087 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45088 | virtual const char *Name() const { return "vshift4L";} |
| 45089 | #endif |
| 45090 | }; |
| 45091 | |
| 45092 | class vshift4L_0Node : public MachTypeNode { |
| 45093 | private: |
| 45094 | MachOper *_opnd_array[3]; |
| 45095 | public: |
| 45096 | MachOper *opnd_array(uint operand_index) const { |
| 45097 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45098 | return _opnd_array[operand_index]; |
| 45099 | } |
| 45100 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45101 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45102 | _opnd_array[operand_index] = operand; |
| 45103 | } |
| 45104 | private: |
| 45105 | virtual const RegMask &out_RegMask() const; |
| 45106 | virtual uint rule() const { return vshift4L_0_rule; } |
| 45107 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45108 | virtual int ideal_Opcode() const { return Op_URShiftVL; } |
| 45109 | virtual uint oper_input_base() const { return 1; } |
| 45110 | public: |
| 45111 | vshift4L_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45112 | virtual uint size_of() const { return sizeof(vshift4L_0Node); } |
| 45113 | static const Pipeline *pipeline_class(); |
| 45114 | virtual const Pipeline *pipeline() const; |
| 45115 | #ifndef PRODUCT |
| 45116 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45117 | virtual const char *Name() const { return "vshift4L_0";} |
| 45118 | #endif |
| 45119 | }; |
| 45120 | |
| 45121 | class vshift8LNode : public MachTypeNode { |
| 45122 | private: |
| 45123 | MachOper *_opnd_array[3]; |
| 45124 | public: |
| 45125 | MachOper *opnd_array(uint operand_index) const { |
| 45126 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45127 | return _opnd_array[operand_index]; |
| 45128 | } |
| 45129 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45130 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45131 | _opnd_array[operand_index] = operand; |
| 45132 | } |
| 45133 | private: |
| 45134 | virtual const RegMask &out_RegMask() const; |
| 45135 | virtual uint rule() const { return vshift8L_rule; } |
| 45136 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45137 | virtual int ideal_Opcode() const { return Op_LShiftVL; } |
| 45138 | virtual uint oper_input_base() const { return 1; } |
| 45139 | public: |
| 45140 | vshift8LNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45141 | virtual uint size_of() const { return sizeof(vshift8LNode); } |
| 45142 | static const Pipeline *pipeline_class(); |
| 45143 | virtual const Pipeline *pipeline() const; |
| 45144 | #ifndef PRODUCT |
| 45145 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45146 | virtual const char *Name() const { return "vshift8L";} |
| 45147 | #endif |
| 45148 | }; |
| 45149 | |
| 45150 | class vshift8L_0Node : public MachTypeNode { |
| 45151 | private: |
| 45152 | MachOper *_opnd_array[3]; |
| 45153 | public: |
| 45154 | MachOper *opnd_array(uint operand_index) const { |
| 45155 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45156 | return _opnd_array[operand_index]; |
| 45157 | } |
| 45158 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45159 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45160 | _opnd_array[operand_index] = operand; |
| 45161 | } |
| 45162 | private: |
| 45163 | virtual const RegMask &out_RegMask() const; |
| 45164 | virtual uint rule() const { return vshift8L_0_rule; } |
| 45165 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45166 | virtual int ideal_Opcode() const { return Op_RShiftVL; } |
| 45167 | virtual uint oper_input_base() const { return 1; } |
| 45168 | public: |
| 45169 | vshift8L_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45170 | virtual uint size_of() const { return sizeof(vshift8L_0Node); } |
| 45171 | static const Pipeline *pipeline_class(); |
| 45172 | virtual const Pipeline *pipeline() const; |
| 45173 | #ifndef PRODUCT |
| 45174 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45175 | virtual const char *Name() const { return "vshift8L_0";} |
| 45176 | #endif |
| 45177 | }; |
| 45178 | |
| 45179 | class vshift8L_1Node : public MachTypeNode { |
| 45180 | private: |
| 45181 | MachOper *_opnd_array[3]; |
| 45182 | public: |
| 45183 | MachOper *opnd_array(uint operand_index) const { |
| 45184 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45185 | return _opnd_array[operand_index]; |
| 45186 | } |
| 45187 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45188 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45189 | _opnd_array[operand_index] = operand; |
| 45190 | } |
| 45191 | private: |
| 45192 | virtual const RegMask &out_RegMask() const; |
| 45193 | virtual uint rule() const { return vshift8L_1_rule; } |
| 45194 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45195 | virtual int ideal_Opcode() const { return Op_URShiftVL; } |
| 45196 | virtual uint oper_input_base() const { return 1; } |
| 45197 | public: |
| 45198 | vshift8L_1Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45199 | virtual uint size_of() const { return sizeof(vshift8L_1Node); } |
| 45200 | static const Pipeline *pipeline_class(); |
| 45201 | virtual const Pipeline *pipeline() const; |
| 45202 | #ifndef PRODUCT |
| 45203 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45204 | virtual const char *Name() const { return "vshift8L_1";} |
| 45205 | #endif |
| 45206 | }; |
| 45207 | |
| 45208 | class vsra2L_regNode : public MachTypeNode { |
| 45209 | private: |
| 45210 | MachOper *_opnd_array[6]; |
| 45211 | public: |
| 45212 | MachOper *opnd_array(uint operand_index) const { |
| 45213 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45214 | return _opnd_array[operand_index]; |
| 45215 | } |
| 45216 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45217 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45218 | _opnd_array[operand_index] = operand; |
| 45219 | } |
| 45220 | private: |
| 45221 | virtual const RegMask &out_RegMask() const; |
| 45222 | virtual uint rule() const { return vsra2L_reg_rule; } |
| 45223 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45224 | virtual int ideal_Opcode() const { return Op_RShiftVL; } |
| 45225 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 45226 | virtual uint oper_input_base() const { return 1; } |
| 45227 | public: |
| 45228 | vsra2L_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 45229 | virtual uint size_of() const { return sizeof(vsra2L_regNode); } |
| 45230 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 45231 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 45232 | static const Pipeline *pipeline_class(); |
| 45233 | virtual const Pipeline *pipeline() const; |
| 45234 | #ifndef PRODUCT |
| 45235 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45236 | virtual const char *Name() const { return "vsra2L_reg";} |
| 45237 | #endif |
| 45238 | }; |
| 45239 | |
| 45240 | class vsra2L_reg_evexNode : public MachTypeNode { |
| 45241 | private: |
| 45242 | MachOper *_opnd_array[3]; |
| 45243 | public: |
| 45244 | MachOper *opnd_array(uint operand_index) const { |
| 45245 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45246 | return _opnd_array[operand_index]; |
| 45247 | } |
| 45248 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45249 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45250 | _opnd_array[operand_index] = operand; |
| 45251 | } |
| 45252 | private: |
| 45253 | virtual const RegMask &out_RegMask() const; |
| 45254 | virtual uint rule() const { return vsra2L_reg_evex_rule; } |
| 45255 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45256 | virtual int ideal_Opcode() const { return Op_RShiftVL; } |
| 45257 | virtual uint oper_input_base() const { return 1; } |
| 45258 | public: |
| 45259 | vsra2L_reg_evexNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45260 | virtual uint size_of() const { return sizeof(vsra2L_reg_evexNode); } |
| 45261 | static const Pipeline *pipeline_class(); |
| 45262 | virtual const Pipeline *pipeline() const; |
| 45263 | #ifndef PRODUCT |
| 45264 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45265 | virtual const char *Name() const { return "vsra2L_reg_evex";} |
| 45266 | #endif |
| 45267 | }; |
| 45268 | |
| 45269 | class vsra4L_regNode : public MachTypeNode { |
| 45270 | private: |
| 45271 | MachOper *_opnd_array[6]; |
| 45272 | public: |
| 45273 | MachOper *opnd_array(uint operand_index) const { |
| 45274 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45275 | return _opnd_array[operand_index]; |
| 45276 | } |
| 45277 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45278 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45279 | _opnd_array[operand_index] = operand; |
| 45280 | } |
| 45281 | private: |
| 45282 | virtual const RegMask &out_RegMask() const; |
| 45283 | virtual uint rule() const { return vsra4L_reg_rule; } |
| 45284 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45285 | virtual int ideal_Opcode() const { return Op_RShiftVL; } |
| 45286 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 45287 | virtual uint oper_input_base() const { return 1; } |
| 45288 | public: |
| 45289 | vsra4L_regNode() { _num_opnds = 6; _opnds = _opnd_array; } |
| 45290 | virtual uint size_of() const { return sizeof(vsra4L_regNode); } |
| 45291 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 45292 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 45293 | static const Pipeline *pipeline_class(); |
| 45294 | virtual const Pipeline *pipeline() const; |
| 45295 | #ifndef PRODUCT |
| 45296 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45297 | virtual const char *Name() const { return "vsra4L_reg";} |
| 45298 | #endif |
| 45299 | }; |
| 45300 | |
| 45301 | class vsra4L_reg_evexNode : public MachTypeNode { |
| 45302 | private: |
| 45303 | MachOper *_opnd_array[3]; |
| 45304 | public: |
| 45305 | MachOper *opnd_array(uint operand_index) const { |
| 45306 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45307 | return _opnd_array[operand_index]; |
| 45308 | } |
| 45309 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45310 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45311 | _opnd_array[operand_index] = operand; |
| 45312 | } |
| 45313 | private: |
| 45314 | virtual const RegMask &out_RegMask() const; |
| 45315 | virtual uint rule() const { return vsra4L_reg_evex_rule; } |
| 45316 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45317 | virtual int ideal_Opcode() const { return Op_RShiftVL; } |
| 45318 | virtual uint oper_input_base() const { return 1; } |
| 45319 | public: |
| 45320 | vsra4L_reg_evexNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45321 | virtual uint size_of() const { return sizeof(vsra4L_reg_evexNode); } |
| 45322 | static const Pipeline *pipeline_class(); |
| 45323 | virtual const Pipeline *pipeline() const; |
| 45324 | #ifndef PRODUCT |
| 45325 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45326 | virtual const char *Name() const { return "vsra4L_reg_evex";} |
| 45327 | #endif |
| 45328 | }; |
| 45329 | |
| 45330 | class vand4BNode : public MachTypeNode { |
| 45331 | private: |
| 45332 | MachOper *_opnd_array[3]; |
| 45333 | public: |
| 45334 | MachOper *opnd_array(uint operand_index) const { |
| 45335 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45336 | return _opnd_array[operand_index]; |
| 45337 | } |
| 45338 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45339 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45340 | _opnd_array[operand_index] = operand; |
| 45341 | } |
| 45342 | private: |
| 45343 | virtual const RegMask &out_RegMask() const; |
| 45344 | virtual uint rule() const { return vand4B_rule; } |
| 45345 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45346 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45347 | virtual uint two_adr() const { return oper_input_base(); } |
| 45348 | virtual uint oper_input_base() const { return 1; } |
| 45349 | public: |
| 45350 | vand4BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45351 | virtual uint size_of() const { return sizeof(vand4BNode); } |
| 45352 | static const Pipeline *pipeline_class(); |
| 45353 | virtual const Pipeline *pipeline() const; |
| 45354 | #ifndef PRODUCT |
| 45355 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45356 | virtual const char *Name() const { return "vand4B";} |
| 45357 | #endif |
| 45358 | }; |
| 45359 | |
| 45360 | class vand4B_regNode : public MachTypeNode { |
| 45361 | private: |
| 45362 | MachOper *_opnd_array[3]; |
| 45363 | public: |
| 45364 | MachOper *opnd_array(uint operand_index) const { |
| 45365 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45366 | return _opnd_array[operand_index]; |
| 45367 | } |
| 45368 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45369 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45370 | _opnd_array[operand_index] = operand; |
| 45371 | } |
| 45372 | private: |
| 45373 | virtual const RegMask &out_RegMask() const; |
| 45374 | virtual uint rule() const { return vand4B_reg_rule; } |
| 45375 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45376 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45377 | virtual uint oper_input_base() const { return 1; } |
| 45378 | public: |
| 45379 | vand4B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45380 | virtual uint size_of() const { return sizeof(vand4B_regNode); } |
| 45381 | static const Pipeline *pipeline_class(); |
| 45382 | virtual const Pipeline *pipeline() const; |
| 45383 | #ifndef PRODUCT |
| 45384 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45385 | virtual const char *Name() const { return "vand4B_reg";} |
| 45386 | #endif |
| 45387 | }; |
| 45388 | |
| 45389 | class vand4B_memNode : public MachTypeNode { |
| 45390 | private: |
| 45391 | MachOper *_opnd_array[3]; |
| 45392 | public: |
| 45393 | MachOper *opnd_array(uint operand_index) const { |
| 45394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45395 | return _opnd_array[operand_index]; |
| 45396 | } |
| 45397 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45399 | _opnd_array[operand_index] = operand; |
| 45400 | } |
| 45401 | private: |
| 45402 | virtual const RegMask &out_RegMask() const; |
| 45403 | virtual uint rule() const { return vand4B_mem_rule; } |
| 45404 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45405 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45406 | virtual int reloc() const; |
| 45407 | virtual uint oper_input_base() const { return 2; } |
| 45408 | public: |
| 45409 | vand4B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45410 | virtual uint size_of() const { return sizeof(vand4B_memNode); } |
| 45411 | static const Pipeline *pipeline_class(); |
| 45412 | virtual const Pipeline *pipeline() const; |
| 45413 | virtual const MachOper *memory_operand() const; |
| 45414 | #ifndef PRODUCT |
| 45415 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45416 | virtual const char *Name() const { return "vand4B_mem";} |
| 45417 | #endif |
| 45418 | }; |
| 45419 | |
| 45420 | class vand4B_mem_0Node : public MachTypeNode { |
| 45421 | private: |
| 45422 | MachOper *_opnd_array[3]; |
| 45423 | public: |
| 45424 | MachOper *opnd_array(uint operand_index) const { |
| 45425 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45426 | return _opnd_array[operand_index]; |
| 45427 | } |
| 45428 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45429 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45430 | _opnd_array[operand_index] = operand; |
| 45431 | } |
| 45432 | private: |
| 45433 | virtual const RegMask &out_RegMask() const; |
| 45434 | virtual uint rule() const { return vand4B_mem_0_rule; } |
| 45435 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45436 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45437 | virtual int reloc() const; |
| 45438 | virtual uint oper_input_base() const { return 2; } |
| 45439 | public: |
| 45440 | vand4B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45441 | virtual uint size_of() const { return sizeof(vand4B_mem_0Node); } |
| 45442 | static const Pipeline *pipeline_class(); |
| 45443 | virtual const Pipeline *pipeline() const; |
| 45444 | virtual const MachOper *memory_operand() const; |
| 45445 | #ifndef PRODUCT |
| 45446 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45447 | virtual const char *Name() const { return "vand4B_mem_0";} |
| 45448 | #endif |
| 45449 | }; |
| 45450 | |
| 45451 | class vand8BNode : public MachTypeNode { |
| 45452 | private: |
| 45453 | MachOper *_opnd_array[3]; |
| 45454 | public: |
| 45455 | MachOper *opnd_array(uint operand_index) const { |
| 45456 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45457 | return _opnd_array[operand_index]; |
| 45458 | } |
| 45459 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45460 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45461 | _opnd_array[operand_index] = operand; |
| 45462 | } |
| 45463 | private: |
| 45464 | virtual const RegMask &out_RegMask() const; |
| 45465 | virtual uint rule() const { return vand8B_rule; } |
| 45466 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45467 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45468 | virtual uint two_adr() const { return oper_input_base(); } |
| 45469 | virtual uint oper_input_base() const { return 1; } |
| 45470 | public: |
| 45471 | vand8BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45472 | virtual uint size_of() const { return sizeof(vand8BNode); } |
| 45473 | static const Pipeline *pipeline_class(); |
| 45474 | virtual const Pipeline *pipeline() const; |
| 45475 | #ifndef PRODUCT |
| 45476 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45477 | virtual const char *Name() const { return "vand8B";} |
| 45478 | #endif |
| 45479 | }; |
| 45480 | |
| 45481 | class vand8B_regNode : public MachTypeNode { |
| 45482 | private: |
| 45483 | MachOper *_opnd_array[3]; |
| 45484 | public: |
| 45485 | MachOper *opnd_array(uint operand_index) const { |
| 45486 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45487 | return _opnd_array[operand_index]; |
| 45488 | } |
| 45489 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45490 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45491 | _opnd_array[operand_index] = operand; |
| 45492 | } |
| 45493 | private: |
| 45494 | virtual const RegMask &out_RegMask() const; |
| 45495 | virtual uint rule() const { return vand8B_reg_rule; } |
| 45496 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45497 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45498 | virtual uint oper_input_base() const { return 1; } |
| 45499 | public: |
| 45500 | vand8B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45501 | virtual uint size_of() const { return sizeof(vand8B_regNode); } |
| 45502 | static const Pipeline *pipeline_class(); |
| 45503 | virtual const Pipeline *pipeline() const; |
| 45504 | #ifndef PRODUCT |
| 45505 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45506 | virtual const char *Name() const { return "vand8B_reg";} |
| 45507 | #endif |
| 45508 | }; |
| 45509 | |
| 45510 | class vand8B_memNode : public MachTypeNode { |
| 45511 | private: |
| 45512 | MachOper *_opnd_array[3]; |
| 45513 | public: |
| 45514 | MachOper *opnd_array(uint operand_index) const { |
| 45515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45516 | return _opnd_array[operand_index]; |
| 45517 | } |
| 45518 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45519 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45520 | _opnd_array[operand_index] = operand; |
| 45521 | } |
| 45522 | private: |
| 45523 | virtual const RegMask &out_RegMask() const; |
| 45524 | virtual uint rule() const { return vand8B_mem_rule; } |
| 45525 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45526 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45527 | virtual int reloc() const; |
| 45528 | virtual uint oper_input_base() const { return 2; } |
| 45529 | public: |
| 45530 | vand8B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45531 | virtual uint size_of() const { return sizeof(vand8B_memNode); } |
| 45532 | static const Pipeline *pipeline_class(); |
| 45533 | virtual const Pipeline *pipeline() const; |
| 45534 | virtual const MachOper *memory_operand() const; |
| 45535 | #ifndef PRODUCT |
| 45536 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45537 | virtual const char *Name() const { return "vand8B_mem";} |
| 45538 | #endif |
| 45539 | }; |
| 45540 | |
| 45541 | class vand8B_mem_0Node : public MachTypeNode { |
| 45542 | private: |
| 45543 | MachOper *_opnd_array[3]; |
| 45544 | public: |
| 45545 | MachOper *opnd_array(uint operand_index) const { |
| 45546 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45547 | return _opnd_array[operand_index]; |
| 45548 | } |
| 45549 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45550 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45551 | _opnd_array[operand_index] = operand; |
| 45552 | } |
| 45553 | private: |
| 45554 | virtual const RegMask &out_RegMask() const; |
| 45555 | virtual uint rule() const { return vand8B_mem_0_rule; } |
| 45556 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45557 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45558 | virtual int reloc() const; |
| 45559 | virtual uint oper_input_base() const { return 2; } |
| 45560 | public: |
| 45561 | vand8B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45562 | virtual uint size_of() const { return sizeof(vand8B_mem_0Node); } |
| 45563 | static const Pipeline *pipeline_class(); |
| 45564 | virtual const Pipeline *pipeline() const; |
| 45565 | virtual const MachOper *memory_operand() const; |
| 45566 | #ifndef PRODUCT |
| 45567 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45568 | virtual const char *Name() const { return "vand8B_mem_0";} |
| 45569 | #endif |
| 45570 | }; |
| 45571 | |
| 45572 | class vand16BNode : public MachTypeNode { |
| 45573 | private: |
| 45574 | MachOper *_opnd_array[3]; |
| 45575 | public: |
| 45576 | MachOper *opnd_array(uint operand_index) const { |
| 45577 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45578 | return _opnd_array[operand_index]; |
| 45579 | } |
| 45580 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45581 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45582 | _opnd_array[operand_index] = operand; |
| 45583 | } |
| 45584 | private: |
| 45585 | virtual const RegMask &out_RegMask() const; |
| 45586 | virtual uint rule() const { return vand16B_rule; } |
| 45587 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45588 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45589 | virtual uint two_adr() const { return oper_input_base(); } |
| 45590 | virtual uint oper_input_base() const { return 1; } |
| 45591 | public: |
| 45592 | vand16BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45593 | virtual uint size_of() const { return sizeof(vand16BNode); } |
| 45594 | static const Pipeline *pipeline_class(); |
| 45595 | virtual const Pipeline *pipeline() const; |
| 45596 | #ifndef PRODUCT |
| 45597 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45598 | virtual const char *Name() const { return "vand16B";} |
| 45599 | #endif |
| 45600 | }; |
| 45601 | |
| 45602 | class vand16B_regNode : public MachTypeNode { |
| 45603 | private: |
| 45604 | MachOper *_opnd_array[3]; |
| 45605 | public: |
| 45606 | MachOper *opnd_array(uint operand_index) const { |
| 45607 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45608 | return _opnd_array[operand_index]; |
| 45609 | } |
| 45610 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45611 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45612 | _opnd_array[operand_index] = operand; |
| 45613 | } |
| 45614 | private: |
| 45615 | virtual const RegMask &out_RegMask() const; |
| 45616 | virtual uint rule() const { return vand16B_reg_rule; } |
| 45617 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45618 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45619 | virtual uint oper_input_base() const { return 1; } |
| 45620 | public: |
| 45621 | vand16B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45622 | virtual uint size_of() const { return sizeof(vand16B_regNode); } |
| 45623 | static const Pipeline *pipeline_class(); |
| 45624 | virtual const Pipeline *pipeline() const; |
| 45625 | #ifndef PRODUCT |
| 45626 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45627 | virtual const char *Name() const { return "vand16B_reg";} |
| 45628 | #endif |
| 45629 | }; |
| 45630 | |
| 45631 | class vand16B_memNode : public MachTypeNode { |
| 45632 | private: |
| 45633 | MachOper *_opnd_array[3]; |
| 45634 | public: |
| 45635 | MachOper *opnd_array(uint operand_index) const { |
| 45636 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45637 | return _opnd_array[operand_index]; |
| 45638 | } |
| 45639 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45640 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45641 | _opnd_array[operand_index] = operand; |
| 45642 | } |
| 45643 | private: |
| 45644 | virtual const RegMask &out_RegMask() const; |
| 45645 | virtual uint rule() const { return vand16B_mem_rule; } |
| 45646 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45647 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45648 | virtual int reloc() const; |
| 45649 | virtual uint oper_input_base() const { return 2; } |
| 45650 | public: |
| 45651 | vand16B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45652 | virtual uint size_of() const { return sizeof(vand16B_memNode); } |
| 45653 | static const Pipeline *pipeline_class(); |
| 45654 | virtual const Pipeline *pipeline() const; |
| 45655 | virtual const MachOper *memory_operand() const; |
| 45656 | #ifndef PRODUCT |
| 45657 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45658 | virtual const char *Name() const { return "vand16B_mem";} |
| 45659 | #endif |
| 45660 | }; |
| 45661 | |
| 45662 | class vand16B_mem_0Node : public MachTypeNode { |
| 45663 | private: |
| 45664 | MachOper *_opnd_array[3]; |
| 45665 | public: |
| 45666 | MachOper *opnd_array(uint operand_index) const { |
| 45667 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45668 | return _opnd_array[operand_index]; |
| 45669 | } |
| 45670 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45671 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45672 | _opnd_array[operand_index] = operand; |
| 45673 | } |
| 45674 | private: |
| 45675 | virtual const RegMask &out_RegMask() const; |
| 45676 | virtual uint rule() const { return vand16B_mem_0_rule; } |
| 45677 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45678 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45679 | virtual int reloc() const; |
| 45680 | virtual uint oper_input_base() const { return 2; } |
| 45681 | public: |
| 45682 | vand16B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45683 | virtual uint size_of() const { return sizeof(vand16B_mem_0Node); } |
| 45684 | static const Pipeline *pipeline_class(); |
| 45685 | virtual const Pipeline *pipeline() const; |
| 45686 | virtual const MachOper *memory_operand() const; |
| 45687 | #ifndef PRODUCT |
| 45688 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45689 | virtual const char *Name() const { return "vand16B_mem_0";} |
| 45690 | #endif |
| 45691 | }; |
| 45692 | |
| 45693 | class vand32B_regNode : public MachTypeNode { |
| 45694 | private: |
| 45695 | MachOper *_opnd_array[3]; |
| 45696 | public: |
| 45697 | MachOper *opnd_array(uint operand_index) const { |
| 45698 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45699 | return _opnd_array[operand_index]; |
| 45700 | } |
| 45701 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45702 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45703 | _opnd_array[operand_index] = operand; |
| 45704 | } |
| 45705 | private: |
| 45706 | virtual const RegMask &out_RegMask() const; |
| 45707 | virtual uint rule() const { return vand32B_reg_rule; } |
| 45708 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45709 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45710 | virtual uint oper_input_base() const { return 1; } |
| 45711 | public: |
| 45712 | vand32B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45713 | virtual uint size_of() const { return sizeof(vand32B_regNode); } |
| 45714 | static const Pipeline *pipeline_class(); |
| 45715 | virtual const Pipeline *pipeline() const; |
| 45716 | #ifndef PRODUCT |
| 45717 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45718 | virtual const char *Name() const { return "vand32B_reg";} |
| 45719 | #endif |
| 45720 | }; |
| 45721 | |
| 45722 | class vand32B_memNode : public MachTypeNode { |
| 45723 | private: |
| 45724 | MachOper *_opnd_array[3]; |
| 45725 | public: |
| 45726 | MachOper *opnd_array(uint operand_index) const { |
| 45727 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45728 | return _opnd_array[operand_index]; |
| 45729 | } |
| 45730 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45731 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45732 | _opnd_array[operand_index] = operand; |
| 45733 | } |
| 45734 | private: |
| 45735 | virtual const RegMask &out_RegMask() const; |
| 45736 | virtual uint rule() const { return vand32B_mem_rule; } |
| 45737 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45738 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45739 | virtual int reloc() const; |
| 45740 | virtual uint oper_input_base() const { return 2; } |
| 45741 | public: |
| 45742 | vand32B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45743 | virtual uint size_of() const { return sizeof(vand32B_memNode); } |
| 45744 | static const Pipeline *pipeline_class(); |
| 45745 | virtual const Pipeline *pipeline() const; |
| 45746 | virtual const MachOper *memory_operand() const; |
| 45747 | #ifndef PRODUCT |
| 45748 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45749 | virtual const char *Name() const { return "vand32B_mem";} |
| 45750 | #endif |
| 45751 | }; |
| 45752 | |
| 45753 | class vand32B_mem_0Node : public MachTypeNode { |
| 45754 | private: |
| 45755 | MachOper *_opnd_array[3]; |
| 45756 | public: |
| 45757 | MachOper *opnd_array(uint operand_index) const { |
| 45758 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45759 | return _opnd_array[operand_index]; |
| 45760 | } |
| 45761 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45762 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45763 | _opnd_array[operand_index] = operand; |
| 45764 | } |
| 45765 | private: |
| 45766 | virtual const RegMask &out_RegMask() const; |
| 45767 | virtual uint rule() const { return vand32B_mem_0_rule; } |
| 45768 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45769 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45770 | virtual int reloc() const; |
| 45771 | virtual uint oper_input_base() const { return 2; } |
| 45772 | public: |
| 45773 | vand32B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45774 | virtual uint size_of() const { return sizeof(vand32B_mem_0Node); } |
| 45775 | static const Pipeline *pipeline_class(); |
| 45776 | virtual const Pipeline *pipeline() const; |
| 45777 | virtual const MachOper *memory_operand() const; |
| 45778 | #ifndef PRODUCT |
| 45779 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45780 | virtual const char *Name() const { return "vand32B_mem_0";} |
| 45781 | #endif |
| 45782 | }; |
| 45783 | |
| 45784 | class vand64B_regNode : public MachTypeNode { |
| 45785 | private: |
| 45786 | MachOper *_opnd_array[3]; |
| 45787 | public: |
| 45788 | MachOper *opnd_array(uint operand_index) const { |
| 45789 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45790 | return _opnd_array[operand_index]; |
| 45791 | } |
| 45792 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45793 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45794 | _opnd_array[operand_index] = operand; |
| 45795 | } |
| 45796 | private: |
| 45797 | virtual const RegMask &out_RegMask() const; |
| 45798 | virtual uint rule() const { return vand64B_reg_rule; } |
| 45799 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45800 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45801 | virtual uint oper_input_base() const { return 1; } |
| 45802 | public: |
| 45803 | vand64B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45804 | virtual uint size_of() const { return sizeof(vand64B_regNode); } |
| 45805 | static const Pipeline *pipeline_class(); |
| 45806 | virtual const Pipeline *pipeline() const; |
| 45807 | #ifndef PRODUCT |
| 45808 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45809 | virtual const char *Name() const { return "vand64B_reg";} |
| 45810 | #endif |
| 45811 | }; |
| 45812 | |
| 45813 | class vand64B_memNode : public MachTypeNode { |
| 45814 | private: |
| 45815 | MachOper *_opnd_array[3]; |
| 45816 | public: |
| 45817 | MachOper *opnd_array(uint operand_index) const { |
| 45818 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45819 | return _opnd_array[operand_index]; |
| 45820 | } |
| 45821 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45822 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45823 | _opnd_array[operand_index] = operand; |
| 45824 | } |
| 45825 | private: |
| 45826 | virtual const RegMask &out_RegMask() const; |
| 45827 | virtual uint rule() const { return vand64B_mem_rule; } |
| 45828 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45829 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45830 | virtual int reloc() const; |
| 45831 | virtual uint oper_input_base() const { return 2; } |
| 45832 | public: |
| 45833 | vand64B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45834 | virtual uint size_of() const { return sizeof(vand64B_memNode); } |
| 45835 | static const Pipeline *pipeline_class(); |
| 45836 | virtual const Pipeline *pipeline() const; |
| 45837 | virtual const MachOper *memory_operand() const; |
| 45838 | #ifndef PRODUCT |
| 45839 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45840 | virtual const char *Name() const { return "vand64B_mem";} |
| 45841 | #endif |
| 45842 | }; |
| 45843 | |
| 45844 | class vand64B_mem_0Node : public MachTypeNode { |
| 45845 | private: |
| 45846 | MachOper *_opnd_array[3]; |
| 45847 | public: |
| 45848 | MachOper *opnd_array(uint operand_index) const { |
| 45849 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45850 | return _opnd_array[operand_index]; |
| 45851 | } |
| 45852 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45853 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45854 | _opnd_array[operand_index] = operand; |
| 45855 | } |
| 45856 | private: |
| 45857 | virtual const RegMask &out_RegMask() const; |
| 45858 | virtual uint rule() const { return vand64B_mem_0_rule; } |
| 45859 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45860 | virtual int ideal_Opcode() const { return Op_AndV; } |
| 45861 | virtual int reloc() const; |
| 45862 | virtual uint oper_input_base() const { return 2; } |
| 45863 | public: |
| 45864 | vand64B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45865 | virtual uint size_of() const { return sizeof(vand64B_mem_0Node); } |
| 45866 | static const Pipeline *pipeline_class(); |
| 45867 | virtual const Pipeline *pipeline() const; |
| 45868 | virtual const MachOper *memory_operand() const; |
| 45869 | #ifndef PRODUCT |
| 45870 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45871 | virtual const char *Name() const { return "vand64B_mem_0";} |
| 45872 | #endif |
| 45873 | }; |
| 45874 | |
| 45875 | class vor4BNode : public MachTypeNode { |
| 45876 | private: |
| 45877 | MachOper *_opnd_array[3]; |
| 45878 | public: |
| 45879 | MachOper *opnd_array(uint operand_index) const { |
| 45880 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45881 | return _opnd_array[operand_index]; |
| 45882 | } |
| 45883 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45884 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45885 | _opnd_array[operand_index] = operand; |
| 45886 | } |
| 45887 | private: |
| 45888 | virtual const RegMask &out_RegMask() const; |
| 45889 | virtual uint rule() const { return vor4B_rule; } |
| 45890 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45891 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 45892 | virtual uint two_adr() const { return oper_input_base(); } |
| 45893 | virtual uint oper_input_base() const { return 1; } |
| 45894 | public: |
| 45895 | vor4BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45896 | virtual uint size_of() const { return sizeof(vor4BNode); } |
| 45897 | static const Pipeline *pipeline_class(); |
| 45898 | virtual const Pipeline *pipeline() const; |
| 45899 | #ifndef PRODUCT |
| 45900 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45901 | virtual const char *Name() const { return "vor4B";} |
| 45902 | #endif |
| 45903 | }; |
| 45904 | |
| 45905 | class vor4B_regNode : public MachTypeNode { |
| 45906 | private: |
| 45907 | MachOper *_opnd_array[3]; |
| 45908 | public: |
| 45909 | MachOper *opnd_array(uint operand_index) const { |
| 45910 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45911 | return _opnd_array[operand_index]; |
| 45912 | } |
| 45913 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45914 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45915 | _opnd_array[operand_index] = operand; |
| 45916 | } |
| 45917 | private: |
| 45918 | virtual const RegMask &out_RegMask() const; |
| 45919 | virtual uint rule() const { return vor4B_reg_rule; } |
| 45920 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45921 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 45922 | virtual uint oper_input_base() const { return 1; } |
| 45923 | public: |
| 45924 | vor4B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 45925 | virtual uint size_of() const { return sizeof(vor4B_regNode); } |
| 45926 | static const Pipeline *pipeline_class(); |
| 45927 | virtual const Pipeline *pipeline() const; |
| 45928 | #ifndef PRODUCT |
| 45929 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45930 | virtual const char *Name() const { return "vor4B_reg";} |
| 45931 | #endif |
| 45932 | }; |
| 45933 | |
| 45934 | class vor4B_memNode : public MachTypeNode { |
| 45935 | private: |
| 45936 | MachOper *_opnd_array[3]; |
| 45937 | public: |
| 45938 | MachOper *opnd_array(uint operand_index) const { |
| 45939 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45940 | return _opnd_array[operand_index]; |
| 45941 | } |
| 45942 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45943 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45944 | _opnd_array[operand_index] = operand; |
| 45945 | } |
| 45946 | private: |
| 45947 | virtual const RegMask &out_RegMask() const; |
| 45948 | virtual uint rule() const { return vor4B_mem_rule; } |
| 45949 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45950 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 45951 | virtual int reloc() const; |
| 45952 | virtual uint oper_input_base() const { return 2; } |
| 45953 | public: |
| 45954 | vor4B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45955 | virtual uint size_of() const { return sizeof(vor4B_memNode); } |
| 45956 | static const Pipeline *pipeline_class(); |
| 45957 | virtual const Pipeline *pipeline() const; |
| 45958 | virtual const MachOper *memory_operand() const; |
| 45959 | #ifndef PRODUCT |
| 45960 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45961 | virtual const char *Name() const { return "vor4B_mem";} |
| 45962 | #endif |
| 45963 | }; |
| 45964 | |
| 45965 | class vor4B_mem_0Node : public MachTypeNode { |
| 45966 | private: |
| 45967 | MachOper *_opnd_array[3]; |
| 45968 | public: |
| 45969 | MachOper *opnd_array(uint operand_index) const { |
| 45970 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45971 | return _opnd_array[operand_index]; |
| 45972 | } |
| 45973 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 45974 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 45975 | _opnd_array[operand_index] = operand; |
| 45976 | } |
| 45977 | private: |
| 45978 | virtual const RegMask &out_RegMask() const; |
| 45979 | virtual uint rule() const { return vor4B_mem_0_rule; } |
| 45980 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 45981 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 45982 | virtual int reloc() const; |
| 45983 | virtual uint oper_input_base() const { return 2; } |
| 45984 | public: |
| 45985 | vor4B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 45986 | virtual uint size_of() const { return sizeof(vor4B_mem_0Node); } |
| 45987 | static const Pipeline *pipeline_class(); |
| 45988 | virtual const Pipeline *pipeline() const; |
| 45989 | virtual const MachOper *memory_operand() const; |
| 45990 | #ifndef PRODUCT |
| 45991 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 45992 | virtual const char *Name() const { return "vor4B_mem_0";} |
| 45993 | #endif |
| 45994 | }; |
| 45995 | |
| 45996 | class vor8BNode : public MachTypeNode { |
| 45997 | private: |
| 45998 | MachOper *_opnd_array[3]; |
| 45999 | public: |
| 46000 | MachOper *opnd_array(uint operand_index) const { |
| 46001 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46002 | return _opnd_array[operand_index]; |
| 46003 | } |
| 46004 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46005 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46006 | _opnd_array[operand_index] = operand; |
| 46007 | } |
| 46008 | private: |
| 46009 | virtual const RegMask &out_RegMask() const; |
| 46010 | virtual uint rule() const { return vor8B_rule; } |
| 46011 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46012 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46013 | virtual uint two_adr() const { return oper_input_base(); } |
| 46014 | virtual uint oper_input_base() const { return 1; } |
| 46015 | public: |
| 46016 | vor8BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46017 | virtual uint size_of() const { return sizeof(vor8BNode); } |
| 46018 | static const Pipeline *pipeline_class(); |
| 46019 | virtual const Pipeline *pipeline() const; |
| 46020 | #ifndef PRODUCT |
| 46021 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46022 | virtual const char *Name() const { return "vor8B";} |
| 46023 | #endif |
| 46024 | }; |
| 46025 | |
| 46026 | class vor8B_regNode : public MachTypeNode { |
| 46027 | private: |
| 46028 | MachOper *_opnd_array[3]; |
| 46029 | public: |
| 46030 | MachOper *opnd_array(uint operand_index) const { |
| 46031 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46032 | return _opnd_array[operand_index]; |
| 46033 | } |
| 46034 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46035 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46036 | _opnd_array[operand_index] = operand; |
| 46037 | } |
| 46038 | private: |
| 46039 | virtual const RegMask &out_RegMask() const; |
| 46040 | virtual uint rule() const { return vor8B_reg_rule; } |
| 46041 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46042 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46043 | virtual uint oper_input_base() const { return 1; } |
| 46044 | public: |
| 46045 | vor8B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46046 | virtual uint size_of() const { return sizeof(vor8B_regNode); } |
| 46047 | static const Pipeline *pipeline_class(); |
| 46048 | virtual const Pipeline *pipeline() const; |
| 46049 | #ifndef PRODUCT |
| 46050 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46051 | virtual const char *Name() const { return "vor8B_reg";} |
| 46052 | #endif |
| 46053 | }; |
| 46054 | |
| 46055 | class vor8B_memNode : public MachTypeNode { |
| 46056 | private: |
| 46057 | MachOper *_opnd_array[3]; |
| 46058 | public: |
| 46059 | MachOper *opnd_array(uint operand_index) const { |
| 46060 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46061 | return _opnd_array[operand_index]; |
| 46062 | } |
| 46063 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46064 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46065 | _opnd_array[operand_index] = operand; |
| 46066 | } |
| 46067 | private: |
| 46068 | virtual const RegMask &out_RegMask() const; |
| 46069 | virtual uint rule() const { return vor8B_mem_rule; } |
| 46070 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46071 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46072 | virtual int reloc() const; |
| 46073 | virtual uint oper_input_base() const { return 2; } |
| 46074 | public: |
| 46075 | vor8B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46076 | virtual uint size_of() const { return sizeof(vor8B_memNode); } |
| 46077 | static const Pipeline *pipeline_class(); |
| 46078 | virtual const Pipeline *pipeline() const; |
| 46079 | virtual const MachOper *memory_operand() const; |
| 46080 | #ifndef PRODUCT |
| 46081 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46082 | virtual const char *Name() const { return "vor8B_mem";} |
| 46083 | #endif |
| 46084 | }; |
| 46085 | |
| 46086 | class vor8B_mem_0Node : public MachTypeNode { |
| 46087 | private: |
| 46088 | MachOper *_opnd_array[3]; |
| 46089 | public: |
| 46090 | MachOper *opnd_array(uint operand_index) const { |
| 46091 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46092 | return _opnd_array[operand_index]; |
| 46093 | } |
| 46094 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46095 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46096 | _opnd_array[operand_index] = operand; |
| 46097 | } |
| 46098 | private: |
| 46099 | virtual const RegMask &out_RegMask() const; |
| 46100 | virtual uint rule() const { return vor8B_mem_0_rule; } |
| 46101 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46102 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46103 | virtual int reloc() const; |
| 46104 | virtual uint oper_input_base() const { return 2; } |
| 46105 | public: |
| 46106 | vor8B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46107 | virtual uint size_of() const { return sizeof(vor8B_mem_0Node); } |
| 46108 | static const Pipeline *pipeline_class(); |
| 46109 | virtual const Pipeline *pipeline() const; |
| 46110 | virtual const MachOper *memory_operand() const; |
| 46111 | #ifndef PRODUCT |
| 46112 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46113 | virtual const char *Name() const { return "vor8B_mem_0";} |
| 46114 | #endif |
| 46115 | }; |
| 46116 | |
| 46117 | class vor16BNode : public MachTypeNode { |
| 46118 | private: |
| 46119 | MachOper *_opnd_array[3]; |
| 46120 | public: |
| 46121 | MachOper *opnd_array(uint operand_index) const { |
| 46122 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46123 | return _opnd_array[operand_index]; |
| 46124 | } |
| 46125 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46126 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46127 | _opnd_array[operand_index] = operand; |
| 46128 | } |
| 46129 | private: |
| 46130 | virtual const RegMask &out_RegMask() const; |
| 46131 | virtual uint rule() const { return vor16B_rule; } |
| 46132 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46133 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46134 | virtual uint two_adr() const { return oper_input_base(); } |
| 46135 | virtual uint oper_input_base() const { return 1; } |
| 46136 | public: |
| 46137 | vor16BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46138 | virtual uint size_of() const { return sizeof(vor16BNode); } |
| 46139 | static const Pipeline *pipeline_class(); |
| 46140 | virtual const Pipeline *pipeline() const; |
| 46141 | #ifndef PRODUCT |
| 46142 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46143 | virtual const char *Name() const { return "vor16B";} |
| 46144 | #endif |
| 46145 | }; |
| 46146 | |
| 46147 | class vor16B_regNode : public MachTypeNode { |
| 46148 | private: |
| 46149 | MachOper *_opnd_array[3]; |
| 46150 | public: |
| 46151 | MachOper *opnd_array(uint operand_index) const { |
| 46152 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46153 | return _opnd_array[operand_index]; |
| 46154 | } |
| 46155 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46156 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46157 | _opnd_array[operand_index] = operand; |
| 46158 | } |
| 46159 | private: |
| 46160 | virtual const RegMask &out_RegMask() const; |
| 46161 | virtual uint rule() const { return vor16B_reg_rule; } |
| 46162 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46163 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46164 | virtual uint oper_input_base() const { return 1; } |
| 46165 | public: |
| 46166 | vor16B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46167 | virtual uint size_of() const { return sizeof(vor16B_regNode); } |
| 46168 | static const Pipeline *pipeline_class(); |
| 46169 | virtual const Pipeline *pipeline() const; |
| 46170 | #ifndef PRODUCT |
| 46171 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46172 | virtual const char *Name() const { return "vor16B_reg";} |
| 46173 | #endif |
| 46174 | }; |
| 46175 | |
| 46176 | class vor16B_memNode : public MachTypeNode { |
| 46177 | private: |
| 46178 | MachOper *_opnd_array[3]; |
| 46179 | public: |
| 46180 | MachOper *opnd_array(uint operand_index) const { |
| 46181 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46182 | return _opnd_array[operand_index]; |
| 46183 | } |
| 46184 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46185 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46186 | _opnd_array[operand_index] = operand; |
| 46187 | } |
| 46188 | private: |
| 46189 | virtual const RegMask &out_RegMask() const; |
| 46190 | virtual uint rule() const { return vor16B_mem_rule; } |
| 46191 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46192 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46193 | virtual int reloc() const; |
| 46194 | virtual uint oper_input_base() const { return 2; } |
| 46195 | public: |
| 46196 | vor16B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46197 | virtual uint size_of() const { return sizeof(vor16B_memNode); } |
| 46198 | static const Pipeline *pipeline_class(); |
| 46199 | virtual const Pipeline *pipeline() const; |
| 46200 | virtual const MachOper *memory_operand() const; |
| 46201 | #ifndef PRODUCT |
| 46202 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46203 | virtual const char *Name() const { return "vor16B_mem";} |
| 46204 | #endif |
| 46205 | }; |
| 46206 | |
| 46207 | class vor16B_mem_0Node : public MachTypeNode { |
| 46208 | private: |
| 46209 | MachOper *_opnd_array[3]; |
| 46210 | public: |
| 46211 | MachOper *opnd_array(uint operand_index) const { |
| 46212 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46213 | return _opnd_array[operand_index]; |
| 46214 | } |
| 46215 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46216 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46217 | _opnd_array[operand_index] = operand; |
| 46218 | } |
| 46219 | private: |
| 46220 | virtual const RegMask &out_RegMask() const; |
| 46221 | virtual uint rule() const { return vor16B_mem_0_rule; } |
| 46222 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46223 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46224 | virtual int reloc() const; |
| 46225 | virtual uint oper_input_base() const { return 2; } |
| 46226 | public: |
| 46227 | vor16B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46228 | virtual uint size_of() const { return sizeof(vor16B_mem_0Node); } |
| 46229 | static const Pipeline *pipeline_class(); |
| 46230 | virtual const Pipeline *pipeline() const; |
| 46231 | virtual const MachOper *memory_operand() const; |
| 46232 | #ifndef PRODUCT |
| 46233 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46234 | virtual const char *Name() const { return "vor16B_mem_0";} |
| 46235 | #endif |
| 46236 | }; |
| 46237 | |
| 46238 | class vor32B_regNode : public MachTypeNode { |
| 46239 | private: |
| 46240 | MachOper *_opnd_array[3]; |
| 46241 | public: |
| 46242 | MachOper *opnd_array(uint operand_index) const { |
| 46243 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46244 | return _opnd_array[operand_index]; |
| 46245 | } |
| 46246 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46247 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46248 | _opnd_array[operand_index] = operand; |
| 46249 | } |
| 46250 | private: |
| 46251 | virtual const RegMask &out_RegMask() const; |
| 46252 | virtual uint rule() const { return vor32B_reg_rule; } |
| 46253 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46254 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46255 | virtual uint oper_input_base() const { return 1; } |
| 46256 | public: |
| 46257 | vor32B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46258 | virtual uint size_of() const { return sizeof(vor32B_regNode); } |
| 46259 | static const Pipeline *pipeline_class(); |
| 46260 | virtual const Pipeline *pipeline() const; |
| 46261 | #ifndef PRODUCT |
| 46262 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46263 | virtual const char *Name() const { return "vor32B_reg";} |
| 46264 | #endif |
| 46265 | }; |
| 46266 | |
| 46267 | class vor32B_memNode : public MachTypeNode { |
| 46268 | private: |
| 46269 | MachOper *_opnd_array[3]; |
| 46270 | public: |
| 46271 | MachOper *opnd_array(uint operand_index) const { |
| 46272 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46273 | return _opnd_array[operand_index]; |
| 46274 | } |
| 46275 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46276 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46277 | _opnd_array[operand_index] = operand; |
| 46278 | } |
| 46279 | private: |
| 46280 | virtual const RegMask &out_RegMask() const; |
| 46281 | virtual uint rule() const { return vor32B_mem_rule; } |
| 46282 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46283 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46284 | virtual int reloc() const; |
| 46285 | virtual uint oper_input_base() const { return 2; } |
| 46286 | public: |
| 46287 | vor32B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46288 | virtual uint size_of() const { return sizeof(vor32B_memNode); } |
| 46289 | static const Pipeline *pipeline_class(); |
| 46290 | virtual const Pipeline *pipeline() const; |
| 46291 | virtual const MachOper *memory_operand() const; |
| 46292 | #ifndef PRODUCT |
| 46293 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46294 | virtual const char *Name() const { return "vor32B_mem";} |
| 46295 | #endif |
| 46296 | }; |
| 46297 | |
| 46298 | class vor32B_mem_0Node : public MachTypeNode { |
| 46299 | private: |
| 46300 | MachOper *_opnd_array[3]; |
| 46301 | public: |
| 46302 | MachOper *opnd_array(uint operand_index) const { |
| 46303 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46304 | return _opnd_array[operand_index]; |
| 46305 | } |
| 46306 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46307 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46308 | _opnd_array[operand_index] = operand; |
| 46309 | } |
| 46310 | private: |
| 46311 | virtual const RegMask &out_RegMask() const; |
| 46312 | virtual uint rule() const { return vor32B_mem_0_rule; } |
| 46313 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46314 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46315 | virtual int reloc() const; |
| 46316 | virtual uint oper_input_base() const { return 2; } |
| 46317 | public: |
| 46318 | vor32B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46319 | virtual uint size_of() const { return sizeof(vor32B_mem_0Node); } |
| 46320 | static const Pipeline *pipeline_class(); |
| 46321 | virtual const Pipeline *pipeline() const; |
| 46322 | virtual const MachOper *memory_operand() const; |
| 46323 | #ifndef PRODUCT |
| 46324 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46325 | virtual const char *Name() const { return "vor32B_mem_0";} |
| 46326 | #endif |
| 46327 | }; |
| 46328 | |
| 46329 | class vor64B_regNode : public MachTypeNode { |
| 46330 | private: |
| 46331 | MachOper *_opnd_array[3]; |
| 46332 | public: |
| 46333 | MachOper *opnd_array(uint operand_index) const { |
| 46334 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46335 | return _opnd_array[operand_index]; |
| 46336 | } |
| 46337 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46338 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46339 | _opnd_array[operand_index] = operand; |
| 46340 | } |
| 46341 | private: |
| 46342 | virtual const RegMask &out_RegMask() const; |
| 46343 | virtual uint rule() const { return vor64B_reg_rule; } |
| 46344 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46345 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46346 | virtual uint oper_input_base() const { return 1; } |
| 46347 | public: |
| 46348 | vor64B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46349 | virtual uint size_of() const { return sizeof(vor64B_regNode); } |
| 46350 | static const Pipeline *pipeline_class(); |
| 46351 | virtual const Pipeline *pipeline() const; |
| 46352 | #ifndef PRODUCT |
| 46353 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46354 | virtual const char *Name() const { return "vor64B_reg";} |
| 46355 | #endif |
| 46356 | }; |
| 46357 | |
| 46358 | class vor64B_memNode : public MachTypeNode { |
| 46359 | private: |
| 46360 | MachOper *_opnd_array[3]; |
| 46361 | public: |
| 46362 | MachOper *opnd_array(uint operand_index) const { |
| 46363 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46364 | return _opnd_array[operand_index]; |
| 46365 | } |
| 46366 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46367 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46368 | _opnd_array[operand_index] = operand; |
| 46369 | } |
| 46370 | private: |
| 46371 | virtual const RegMask &out_RegMask() const; |
| 46372 | virtual uint rule() const { return vor64B_mem_rule; } |
| 46373 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46374 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46375 | virtual int reloc() const; |
| 46376 | virtual uint oper_input_base() const { return 2; } |
| 46377 | public: |
| 46378 | vor64B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46379 | virtual uint size_of() const { return sizeof(vor64B_memNode); } |
| 46380 | static const Pipeline *pipeline_class(); |
| 46381 | virtual const Pipeline *pipeline() const; |
| 46382 | virtual const MachOper *memory_operand() const; |
| 46383 | #ifndef PRODUCT |
| 46384 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46385 | virtual const char *Name() const { return "vor64B_mem";} |
| 46386 | #endif |
| 46387 | }; |
| 46388 | |
| 46389 | class vor64B_mem_0Node : public MachTypeNode { |
| 46390 | private: |
| 46391 | MachOper *_opnd_array[3]; |
| 46392 | public: |
| 46393 | MachOper *opnd_array(uint operand_index) const { |
| 46394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46395 | return _opnd_array[operand_index]; |
| 46396 | } |
| 46397 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46398 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46399 | _opnd_array[operand_index] = operand; |
| 46400 | } |
| 46401 | private: |
| 46402 | virtual const RegMask &out_RegMask() const; |
| 46403 | virtual uint rule() const { return vor64B_mem_0_rule; } |
| 46404 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46405 | virtual int ideal_Opcode() const { return Op_OrV; } |
| 46406 | virtual int reloc() const; |
| 46407 | virtual uint oper_input_base() const { return 2; } |
| 46408 | public: |
| 46409 | vor64B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46410 | virtual uint size_of() const { return sizeof(vor64B_mem_0Node); } |
| 46411 | static const Pipeline *pipeline_class(); |
| 46412 | virtual const Pipeline *pipeline() const; |
| 46413 | virtual const MachOper *memory_operand() const; |
| 46414 | #ifndef PRODUCT |
| 46415 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46416 | virtual const char *Name() const { return "vor64B_mem_0";} |
| 46417 | #endif |
| 46418 | }; |
| 46419 | |
| 46420 | class vxor4BNode : public MachTypeNode { |
| 46421 | private: |
| 46422 | MachOper *_opnd_array[3]; |
| 46423 | public: |
| 46424 | MachOper *opnd_array(uint operand_index) const { |
| 46425 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46426 | return _opnd_array[operand_index]; |
| 46427 | } |
| 46428 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46429 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46430 | _opnd_array[operand_index] = operand; |
| 46431 | } |
| 46432 | private: |
| 46433 | virtual const RegMask &out_RegMask() const; |
| 46434 | virtual uint rule() const { return vxor4B_rule; } |
| 46435 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46436 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46437 | virtual uint two_adr() const { return oper_input_base(); } |
| 46438 | virtual uint oper_input_base() const { return 1; } |
| 46439 | public: |
| 46440 | vxor4BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46441 | virtual uint size_of() const { return sizeof(vxor4BNode); } |
| 46442 | static const Pipeline *pipeline_class(); |
| 46443 | virtual const Pipeline *pipeline() const; |
| 46444 | #ifndef PRODUCT |
| 46445 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46446 | virtual const char *Name() const { return "vxor4B";} |
| 46447 | #endif |
| 46448 | }; |
| 46449 | |
| 46450 | class vxor4B_regNode : public MachTypeNode { |
| 46451 | private: |
| 46452 | MachOper *_opnd_array[3]; |
| 46453 | public: |
| 46454 | MachOper *opnd_array(uint operand_index) const { |
| 46455 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46456 | return _opnd_array[operand_index]; |
| 46457 | } |
| 46458 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46459 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46460 | _opnd_array[operand_index] = operand; |
| 46461 | } |
| 46462 | private: |
| 46463 | virtual const RegMask &out_RegMask() const; |
| 46464 | virtual uint rule() const { return vxor4B_reg_rule; } |
| 46465 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46466 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46467 | virtual uint oper_input_base() const { return 1; } |
| 46468 | public: |
| 46469 | vxor4B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46470 | virtual uint size_of() const { return sizeof(vxor4B_regNode); } |
| 46471 | static const Pipeline *pipeline_class(); |
| 46472 | virtual const Pipeline *pipeline() const; |
| 46473 | #ifndef PRODUCT |
| 46474 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46475 | virtual const char *Name() const { return "vxor4B_reg";} |
| 46476 | #endif |
| 46477 | }; |
| 46478 | |
| 46479 | class vxor4B_memNode : public MachTypeNode { |
| 46480 | private: |
| 46481 | MachOper *_opnd_array[3]; |
| 46482 | public: |
| 46483 | MachOper *opnd_array(uint operand_index) const { |
| 46484 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46485 | return _opnd_array[operand_index]; |
| 46486 | } |
| 46487 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46488 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46489 | _opnd_array[operand_index] = operand; |
| 46490 | } |
| 46491 | private: |
| 46492 | virtual const RegMask &out_RegMask() const; |
| 46493 | virtual uint rule() const { return vxor4B_mem_rule; } |
| 46494 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46495 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46496 | virtual int reloc() const; |
| 46497 | virtual uint oper_input_base() const { return 2; } |
| 46498 | public: |
| 46499 | vxor4B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46500 | virtual uint size_of() const { return sizeof(vxor4B_memNode); } |
| 46501 | static const Pipeline *pipeline_class(); |
| 46502 | virtual const Pipeline *pipeline() const; |
| 46503 | virtual const MachOper *memory_operand() const; |
| 46504 | #ifndef PRODUCT |
| 46505 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46506 | virtual const char *Name() const { return "vxor4B_mem";} |
| 46507 | #endif |
| 46508 | }; |
| 46509 | |
| 46510 | class vxor4B_mem_0Node : public MachTypeNode { |
| 46511 | private: |
| 46512 | MachOper *_opnd_array[3]; |
| 46513 | public: |
| 46514 | MachOper *opnd_array(uint operand_index) const { |
| 46515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46516 | return _opnd_array[operand_index]; |
| 46517 | } |
| 46518 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46519 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46520 | _opnd_array[operand_index] = operand; |
| 46521 | } |
| 46522 | private: |
| 46523 | virtual const RegMask &out_RegMask() const; |
| 46524 | virtual uint rule() const { return vxor4B_mem_0_rule; } |
| 46525 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46526 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46527 | virtual int reloc() const; |
| 46528 | virtual uint oper_input_base() const { return 2; } |
| 46529 | public: |
| 46530 | vxor4B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46531 | virtual uint size_of() const { return sizeof(vxor4B_mem_0Node); } |
| 46532 | static const Pipeline *pipeline_class(); |
| 46533 | virtual const Pipeline *pipeline() const; |
| 46534 | virtual const MachOper *memory_operand() const; |
| 46535 | #ifndef PRODUCT |
| 46536 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46537 | virtual const char *Name() const { return "vxor4B_mem_0";} |
| 46538 | #endif |
| 46539 | }; |
| 46540 | |
| 46541 | class vxor8BNode : public MachTypeNode { |
| 46542 | private: |
| 46543 | MachOper *_opnd_array[3]; |
| 46544 | public: |
| 46545 | MachOper *opnd_array(uint operand_index) const { |
| 46546 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46547 | return _opnd_array[operand_index]; |
| 46548 | } |
| 46549 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46550 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46551 | _opnd_array[operand_index] = operand; |
| 46552 | } |
| 46553 | private: |
| 46554 | virtual const RegMask &out_RegMask() const; |
| 46555 | virtual uint rule() const { return vxor8B_rule; } |
| 46556 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46557 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46558 | virtual uint two_adr() const { return oper_input_base(); } |
| 46559 | virtual uint oper_input_base() const { return 1; } |
| 46560 | public: |
| 46561 | vxor8BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46562 | virtual uint size_of() const { return sizeof(vxor8BNode); } |
| 46563 | static const Pipeline *pipeline_class(); |
| 46564 | virtual const Pipeline *pipeline() const; |
| 46565 | #ifndef PRODUCT |
| 46566 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46567 | virtual const char *Name() const { return "vxor8B";} |
| 46568 | #endif |
| 46569 | }; |
| 46570 | |
| 46571 | class vxor8B_regNode : public MachTypeNode { |
| 46572 | private: |
| 46573 | MachOper *_opnd_array[3]; |
| 46574 | public: |
| 46575 | MachOper *opnd_array(uint operand_index) const { |
| 46576 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46577 | return _opnd_array[operand_index]; |
| 46578 | } |
| 46579 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46580 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46581 | _opnd_array[operand_index] = operand; |
| 46582 | } |
| 46583 | private: |
| 46584 | virtual const RegMask &out_RegMask() const; |
| 46585 | virtual uint rule() const { return vxor8B_reg_rule; } |
| 46586 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46587 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46588 | virtual uint oper_input_base() const { return 1; } |
| 46589 | public: |
| 46590 | vxor8B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46591 | virtual uint size_of() const { return sizeof(vxor8B_regNode); } |
| 46592 | static const Pipeline *pipeline_class(); |
| 46593 | virtual const Pipeline *pipeline() const; |
| 46594 | #ifndef PRODUCT |
| 46595 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46596 | virtual const char *Name() const { return "vxor8B_reg";} |
| 46597 | #endif |
| 46598 | }; |
| 46599 | |
| 46600 | class vxor8B_memNode : public MachTypeNode { |
| 46601 | private: |
| 46602 | MachOper *_opnd_array[3]; |
| 46603 | public: |
| 46604 | MachOper *opnd_array(uint operand_index) const { |
| 46605 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46606 | return _opnd_array[operand_index]; |
| 46607 | } |
| 46608 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46609 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46610 | _opnd_array[operand_index] = operand; |
| 46611 | } |
| 46612 | private: |
| 46613 | virtual const RegMask &out_RegMask() const; |
| 46614 | virtual uint rule() const { return vxor8B_mem_rule; } |
| 46615 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46616 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46617 | virtual int reloc() const; |
| 46618 | virtual uint oper_input_base() const { return 2; } |
| 46619 | public: |
| 46620 | vxor8B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46621 | virtual uint size_of() const { return sizeof(vxor8B_memNode); } |
| 46622 | static const Pipeline *pipeline_class(); |
| 46623 | virtual const Pipeline *pipeline() const; |
| 46624 | virtual const MachOper *memory_operand() const; |
| 46625 | #ifndef PRODUCT |
| 46626 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46627 | virtual const char *Name() const { return "vxor8B_mem";} |
| 46628 | #endif |
| 46629 | }; |
| 46630 | |
| 46631 | class vxor8B_mem_0Node : public MachTypeNode { |
| 46632 | private: |
| 46633 | MachOper *_opnd_array[3]; |
| 46634 | public: |
| 46635 | MachOper *opnd_array(uint operand_index) const { |
| 46636 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46637 | return _opnd_array[operand_index]; |
| 46638 | } |
| 46639 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46640 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46641 | _opnd_array[operand_index] = operand; |
| 46642 | } |
| 46643 | private: |
| 46644 | virtual const RegMask &out_RegMask() const; |
| 46645 | virtual uint rule() const { return vxor8B_mem_0_rule; } |
| 46646 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46647 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46648 | virtual int reloc() const; |
| 46649 | virtual uint oper_input_base() const { return 2; } |
| 46650 | public: |
| 46651 | vxor8B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46652 | virtual uint size_of() const { return sizeof(vxor8B_mem_0Node); } |
| 46653 | static const Pipeline *pipeline_class(); |
| 46654 | virtual const Pipeline *pipeline() const; |
| 46655 | virtual const MachOper *memory_operand() const; |
| 46656 | #ifndef PRODUCT |
| 46657 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46658 | virtual const char *Name() const { return "vxor8B_mem_0";} |
| 46659 | #endif |
| 46660 | }; |
| 46661 | |
| 46662 | class vxor16BNode : public MachTypeNode { |
| 46663 | private: |
| 46664 | MachOper *_opnd_array[3]; |
| 46665 | public: |
| 46666 | MachOper *opnd_array(uint operand_index) const { |
| 46667 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46668 | return _opnd_array[operand_index]; |
| 46669 | } |
| 46670 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46671 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46672 | _opnd_array[operand_index] = operand; |
| 46673 | } |
| 46674 | private: |
| 46675 | virtual const RegMask &out_RegMask() const; |
| 46676 | virtual uint rule() const { return vxor16B_rule; } |
| 46677 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46678 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46679 | virtual uint two_adr() const { return oper_input_base(); } |
| 46680 | virtual uint oper_input_base() const { return 1; } |
| 46681 | public: |
| 46682 | vxor16BNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46683 | virtual uint size_of() const { return sizeof(vxor16BNode); } |
| 46684 | static const Pipeline *pipeline_class(); |
| 46685 | virtual const Pipeline *pipeline() const; |
| 46686 | #ifndef PRODUCT |
| 46687 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46688 | virtual const char *Name() const { return "vxor16B";} |
| 46689 | #endif |
| 46690 | }; |
| 46691 | |
| 46692 | class vxor16B_regNode : public MachTypeNode { |
| 46693 | private: |
| 46694 | MachOper *_opnd_array[3]; |
| 46695 | public: |
| 46696 | MachOper *opnd_array(uint operand_index) const { |
| 46697 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46698 | return _opnd_array[operand_index]; |
| 46699 | } |
| 46700 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46701 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46702 | _opnd_array[operand_index] = operand; |
| 46703 | } |
| 46704 | private: |
| 46705 | virtual const RegMask &out_RegMask() const; |
| 46706 | virtual uint rule() const { return vxor16B_reg_rule; } |
| 46707 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46708 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46709 | virtual uint oper_input_base() const { return 1; } |
| 46710 | public: |
| 46711 | vxor16B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46712 | virtual uint size_of() const { return sizeof(vxor16B_regNode); } |
| 46713 | static const Pipeline *pipeline_class(); |
| 46714 | virtual const Pipeline *pipeline() const; |
| 46715 | #ifndef PRODUCT |
| 46716 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46717 | virtual const char *Name() const { return "vxor16B_reg";} |
| 46718 | #endif |
| 46719 | }; |
| 46720 | |
| 46721 | class vxor16B_memNode : public MachTypeNode { |
| 46722 | private: |
| 46723 | MachOper *_opnd_array[3]; |
| 46724 | public: |
| 46725 | MachOper *opnd_array(uint operand_index) const { |
| 46726 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46727 | return _opnd_array[operand_index]; |
| 46728 | } |
| 46729 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46730 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46731 | _opnd_array[operand_index] = operand; |
| 46732 | } |
| 46733 | private: |
| 46734 | virtual const RegMask &out_RegMask() const; |
| 46735 | virtual uint rule() const { return vxor16B_mem_rule; } |
| 46736 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46737 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46738 | virtual int reloc() const; |
| 46739 | virtual uint oper_input_base() const { return 2; } |
| 46740 | public: |
| 46741 | vxor16B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46742 | virtual uint size_of() const { return sizeof(vxor16B_memNode); } |
| 46743 | static const Pipeline *pipeline_class(); |
| 46744 | virtual const Pipeline *pipeline() const; |
| 46745 | virtual const MachOper *memory_operand() const; |
| 46746 | #ifndef PRODUCT |
| 46747 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46748 | virtual const char *Name() const { return "vxor16B_mem";} |
| 46749 | #endif |
| 46750 | }; |
| 46751 | |
| 46752 | class vxor16B_mem_0Node : public MachTypeNode { |
| 46753 | private: |
| 46754 | MachOper *_opnd_array[3]; |
| 46755 | public: |
| 46756 | MachOper *opnd_array(uint operand_index) const { |
| 46757 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46758 | return _opnd_array[operand_index]; |
| 46759 | } |
| 46760 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46761 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46762 | _opnd_array[operand_index] = operand; |
| 46763 | } |
| 46764 | private: |
| 46765 | virtual const RegMask &out_RegMask() const; |
| 46766 | virtual uint rule() const { return vxor16B_mem_0_rule; } |
| 46767 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46768 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46769 | virtual int reloc() const; |
| 46770 | virtual uint oper_input_base() const { return 2; } |
| 46771 | public: |
| 46772 | vxor16B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46773 | virtual uint size_of() const { return sizeof(vxor16B_mem_0Node); } |
| 46774 | static const Pipeline *pipeline_class(); |
| 46775 | virtual const Pipeline *pipeline() const; |
| 46776 | virtual const MachOper *memory_operand() const; |
| 46777 | #ifndef PRODUCT |
| 46778 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46779 | virtual const char *Name() const { return "vxor16B_mem_0";} |
| 46780 | #endif |
| 46781 | }; |
| 46782 | |
| 46783 | class vxor32B_regNode : public MachTypeNode { |
| 46784 | private: |
| 46785 | MachOper *_opnd_array[3]; |
| 46786 | public: |
| 46787 | MachOper *opnd_array(uint operand_index) const { |
| 46788 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46789 | return _opnd_array[operand_index]; |
| 46790 | } |
| 46791 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46792 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46793 | _opnd_array[operand_index] = operand; |
| 46794 | } |
| 46795 | private: |
| 46796 | virtual const RegMask &out_RegMask() const; |
| 46797 | virtual uint rule() const { return vxor32B_reg_rule; } |
| 46798 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46799 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46800 | virtual uint oper_input_base() const { return 1; } |
| 46801 | public: |
| 46802 | vxor32B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46803 | virtual uint size_of() const { return sizeof(vxor32B_regNode); } |
| 46804 | static const Pipeline *pipeline_class(); |
| 46805 | virtual const Pipeline *pipeline() const; |
| 46806 | #ifndef PRODUCT |
| 46807 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46808 | virtual const char *Name() const { return "vxor32B_reg";} |
| 46809 | #endif |
| 46810 | }; |
| 46811 | |
| 46812 | class vxor32B_memNode : public MachTypeNode { |
| 46813 | private: |
| 46814 | MachOper *_opnd_array[3]; |
| 46815 | public: |
| 46816 | MachOper *opnd_array(uint operand_index) const { |
| 46817 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46818 | return _opnd_array[operand_index]; |
| 46819 | } |
| 46820 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46821 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46822 | _opnd_array[operand_index] = operand; |
| 46823 | } |
| 46824 | private: |
| 46825 | virtual const RegMask &out_RegMask() const; |
| 46826 | virtual uint rule() const { return vxor32B_mem_rule; } |
| 46827 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46828 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46829 | virtual int reloc() const; |
| 46830 | virtual uint oper_input_base() const { return 2; } |
| 46831 | public: |
| 46832 | vxor32B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46833 | virtual uint size_of() const { return sizeof(vxor32B_memNode); } |
| 46834 | static const Pipeline *pipeline_class(); |
| 46835 | virtual const Pipeline *pipeline() const; |
| 46836 | virtual const MachOper *memory_operand() const; |
| 46837 | #ifndef PRODUCT |
| 46838 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46839 | virtual const char *Name() const { return "vxor32B_mem";} |
| 46840 | #endif |
| 46841 | }; |
| 46842 | |
| 46843 | class vxor32B_mem_0Node : public MachTypeNode { |
| 46844 | private: |
| 46845 | MachOper *_opnd_array[3]; |
| 46846 | public: |
| 46847 | MachOper *opnd_array(uint operand_index) const { |
| 46848 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46849 | return _opnd_array[operand_index]; |
| 46850 | } |
| 46851 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46852 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46853 | _opnd_array[operand_index] = operand; |
| 46854 | } |
| 46855 | private: |
| 46856 | virtual const RegMask &out_RegMask() const; |
| 46857 | virtual uint rule() const { return vxor32B_mem_0_rule; } |
| 46858 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46859 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46860 | virtual int reloc() const; |
| 46861 | virtual uint oper_input_base() const { return 2; } |
| 46862 | public: |
| 46863 | vxor32B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46864 | virtual uint size_of() const { return sizeof(vxor32B_mem_0Node); } |
| 46865 | static const Pipeline *pipeline_class(); |
| 46866 | virtual const Pipeline *pipeline() const; |
| 46867 | virtual const MachOper *memory_operand() const; |
| 46868 | #ifndef PRODUCT |
| 46869 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46870 | virtual const char *Name() const { return "vxor32B_mem_0";} |
| 46871 | #endif |
| 46872 | }; |
| 46873 | |
| 46874 | class vxor64B_regNode : public MachTypeNode { |
| 46875 | private: |
| 46876 | MachOper *_opnd_array[3]; |
| 46877 | public: |
| 46878 | MachOper *opnd_array(uint operand_index) const { |
| 46879 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46880 | return _opnd_array[operand_index]; |
| 46881 | } |
| 46882 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46883 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46884 | _opnd_array[operand_index] = operand; |
| 46885 | } |
| 46886 | private: |
| 46887 | virtual const RegMask &out_RegMask() const; |
| 46888 | virtual uint rule() const { return vxor64B_reg_rule; } |
| 46889 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46890 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46891 | virtual uint oper_input_base() const { return 1; } |
| 46892 | public: |
| 46893 | vxor64B_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 46894 | virtual uint size_of() const { return sizeof(vxor64B_regNode); } |
| 46895 | static const Pipeline *pipeline_class(); |
| 46896 | virtual const Pipeline *pipeline() const; |
| 46897 | #ifndef PRODUCT |
| 46898 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46899 | virtual const char *Name() const { return "vxor64B_reg";} |
| 46900 | #endif |
| 46901 | }; |
| 46902 | |
| 46903 | class vxor64B_memNode : public MachTypeNode { |
| 46904 | private: |
| 46905 | MachOper *_opnd_array[3]; |
| 46906 | public: |
| 46907 | MachOper *opnd_array(uint operand_index) const { |
| 46908 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46909 | return _opnd_array[operand_index]; |
| 46910 | } |
| 46911 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46912 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46913 | _opnd_array[operand_index] = operand; |
| 46914 | } |
| 46915 | private: |
| 46916 | virtual const RegMask &out_RegMask() const; |
| 46917 | virtual uint rule() const { return vxor64B_mem_rule; } |
| 46918 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46919 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46920 | virtual int reloc() const; |
| 46921 | virtual uint oper_input_base() const { return 2; } |
| 46922 | public: |
| 46923 | vxor64B_memNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46924 | virtual uint size_of() const { return sizeof(vxor64B_memNode); } |
| 46925 | static const Pipeline *pipeline_class(); |
| 46926 | virtual const Pipeline *pipeline() const; |
| 46927 | virtual const MachOper *memory_operand() const; |
| 46928 | #ifndef PRODUCT |
| 46929 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46930 | virtual const char *Name() const { return "vxor64B_mem";} |
| 46931 | #endif |
| 46932 | }; |
| 46933 | |
| 46934 | class vxor64B_mem_0Node : public MachTypeNode { |
| 46935 | private: |
| 46936 | MachOper *_opnd_array[3]; |
| 46937 | public: |
| 46938 | MachOper *opnd_array(uint operand_index) const { |
| 46939 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46940 | return _opnd_array[operand_index]; |
| 46941 | } |
| 46942 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46943 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46944 | _opnd_array[operand_index] = operand; |
| 46945 | } |
| 46946 | private: |
| 46947 | virtual const RegMask &out_RegMask() const; |
| 46948 | virtual uint rule() const { return vxor64B_mem_0_rule; } |
| 46949 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46950 | virtual int ideal_Opcode() const { return Op_XorV; } |
| 46951 | virtual int reloc() const; |
| 46952 | virtual uint oper_input_base() const { return 2; } |
| 46953 | public: |
| 46954 | vxor64B_mem_0Node() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 46955 | virtual uint size_of() const { return sizeof(vxor64B_mem_0Node); } |
| 46956 | static const Pipeline *pipeline_class(); |
| 46957 | virtual const Pipeline *pipeline() const; |
| 46958 | virtual const MachOper *memory_operand() const; |
| 46959 | #ifndef PRODUCT |
| 46960 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46961 | virtual const char *Name() const { return "vxor64B_mem_0";} |
| 46962 | #endif |
| 46963 | }; |
| 46964 | |
| 46965 | class vabs4B_regNode : public MachTypeNode { |
| 46966 | private: |
| 46967 | MachOper *_opnd_array[2]; |
| 46968 | public: |
| 46969 | MachOper *opnd_array(uint operand_index) const { |
| 46970 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46971 | return _opnd_array[operand_index]; |
| 46972 | } |
| 46973 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 46974 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 46975 | _opnd_array[operand_index] = operand; |
| 46976 | } |
| 46977 | private: |
| 46978 | virtual const RegMask &out_RegMask() const; |
| 46979 | virtual uint rule() const { return vabs4B_reg_rule; } |
| 46980 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 46981 | virtual int ideal_Opcode() const { return Op_AbsVB; } |
| 46982 | virtual uint oper_input_base() const { return 1; } |
| 46983 | public: |
| 46984 | vabs4B_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 46985 | virtual uint size_of() const { return sizeof(vabs4B_regNode); } |
| 46986 | // Rematerialize vabs4B_reg |
| 46987 | static const Pipeline *pipeline_class(); |
| 46988 | virtual const Pipeline *pipeline() const; |
| 46989 | #ifndef PRODUCT |
| 46990 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 46991 | virtual const char *Name() const { return "vabs4B_reg";} |
| 46992 | #endif |
| 46993 | }; |
| 46994 | |
| 46995 | class vabs8B_regNode : public MachTypeNode { |
| 46996 | private: |
| 46997 | MachOper *_opnd_array[2]; |
| 46998 | public: |
| 46999 | MachOper *opnd_array(uint operand_index) const { |
| 47000 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47001 | return _opnd_array[operand_index]; |
| 47002 | } |
| 47003 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47004 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47005 | _opnd_array[operand_index] = operand; |
| 47006 | } |
| 47007 | private: |
| 47008 | virtual const RegMask &out_RegMask() const; |
| 47009 | virtual uint rule() const { return vabs8B_reg_rule; } |
| 47010 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47011 | virtual int ideal_Opcode() const { return Op_AbsVB; } |
| 47012 | virtual uint oper_input_base() const { return 1; } |
| 47013 | public: |
| 47014 | vabs8B_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47015 | virtual uint size_of() const { return sizeof(vabs8B_regNode); } |
| 47016 | // Rematerialize vabs8B_reg |
| 47017 | static const Pipeline *pipeline_class(); |
| 47018 | virtual const Pipeline *pipeline() const; |
| 47019 | #ifndef PRODUCT |
| 47020 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47021 | virtual const char *Name() const { return "vabs8B_reg";} |
| 47022 | #endif |
| 47023 | }; |
| 47024 | |
| 47025 | class vabs16B_regNode : public MachTypeNode { |
| 47026 | private: |
| 47027 | MachOper *_opnd_array[2]; |
| 47028 | public: |
| 47029 | MachOper *opnd_array(uint operand_index) const { |
| 47030 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47031 | return _opnd_array[operand_index]; |
| 47032 | } |
| 47033 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47034 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47035 | _opnd_array[operand_index] = operand; |
| 47036 | } |
| 47037 | private: |
| 47038 | virtual const RegMask &out_RegMask() const; |
| 47039 | virtual uint rule() const { return vabs16B_reg_rule; } |
| 47040 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47041 | virtual int ideal_Opcode() const { return Op_AbsVB; } |
| 47042 | virtual uint oper_input_base() const { return 1; } |
| 47043 | public: |
| 47044 | vabs16B_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47045 | virtual uint size_of() const { return sizeof(vabs16B_regNode); } |
| 47046 | // Rematerialize vabs16B_reg |
| 47047 | static const Pipeline *pipeline_class(); |
| 47048 | virtual const Pipeline *pipeline() const; |
| 47049 | #ifndef PRODUCT |
| 47050 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47051 | virtual const char *Name() const { return "vabs16B_reg";} |
| 47052 | #endif |
| 47053 | }; |
| 47054 | |
| 47055 | class vabs32B_regNode : public MachTypeNode { |
| 47056 | private: |
| 47057 | MachOper *_opnd_array[2]; |
| 47058 | public: |
| 47059 | MachOper *opnd_array(uint operand_index) const { |
| 47060 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47061 | return _opnd_array[operand_index]; |
| 47062 | } |
| 47063 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47064 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47065 | _opnd_array[operand_index] = operand; |
| 47066 | } |
| 47067 | private: |
| 47068 | virtual const RegMask &out_RegMask() const; |
| 47069 | virtual uint rule() const { return vabs32B_reg_rule; } |
| 47070 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47071 | virtual int ideal_Opcode() const { return Op_AbsVB; } |
| 47072 | virtual uint oper_input_base() const { return 1; } |
| 47073 | public: |
| 47074 | vabs32B_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47075 | virtual uint size_of() const { return sizeof(vabs32B_regNode); } |
| 47076 | // Rematerialize vabs32B_reg |
| 47077 | static const Pipeline *pipeline_class(); |
| 47078 | virtual const Pipeline *pipeline() const; |
| 47079 | #ifndef PRODUCT |
| 47080 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47081 | virtual const char *Name() const { return "vabs32B_reg";} |
| 47082 | #endif |
| 47083 | }; |
| 47084 | |
| 47085 | class vabs64B_regNode : public MachTypeNode { |
| 47086 | private: |
| 47087 | MachOper *_opnd_array[2]; |
| 47088 | public: |
| 47089 | MachOper *opnd_array(uint operand_index) const { |
| 47090 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47091 | return _opnd_array[operand_index]; |
| 47092 | } |
| 47093 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47094 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47095 | _opnd_array[operand_index] = operand; |
| 47096 | } |
| 47097 | private: |
| 47098 | virtual const RegMask &out_RegMask() const; |
| 47099 | virtual uint rule() const { return vabs64B_reg_rule; } |
| 47100 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47101 | virtual int ideal_Opcode() const { return Op_AbsVB; } |
| 47102 | virtual uint oper_input_base() const { return 1; } |
| 47103 | public: |
| 47104 | vabs64B_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47105 | virtual uint size_of() const { return sizeof(vabs64B_regNode); } |
| 47106 | // Rematerialize vabs64B_reg |
| 47107 | static const Pipeline *pipeline_class(); |
| 47108 | virtual const Pipeline *pipeline() const; |
| 47109 | #ifndef PRODUCT |
| 47110 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47111 | virtual const char *Name() const { return "vabs64B_reg";} |
| 47112 | #endif |
| 47113 | }; |
| 47114 | |
| 47115 | class vabs2S_regNode : public MachTypeNode { |
| 47116 | private: |
| 47117 | MachOper *_opnd_array[2]; |
| 47118 | public: |
| 47119 | MachOper *opnd_array(uint operand_index) const { |
| 47120 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47121 | return _opnd_array[operand_index]; |
| 47122 | } |
| 47123 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47124 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47125 | _opnd_array[operand_index] = operand; |
| 47126 | } |
| 47127 | private: |
| 47128 | virtual const RegMask &out_RegMask() const; |
| 47129 | virtual uint rule() const { return vabs2S_reg_rule; } |
| 47130 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47131 | virtual int ideal_Opcode() const { return Op_AbsVS; } |
| 47132 | virtual uint oper_input_base() const { return 1; } |
| 47133 | public: |
| 47134 | vabs2S_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47135 | virtual uint size_of() const { return sizeof(vabs2S_regNode); } |
| 47136 | // Rematerialize vabs2S_reg |
| 47137 | static const Pipeline *pipeline_class(); |
| 47138 | virtual const Pipeline *pipeline() const; |
| 47139 | #ifndef PRODUCT |
| 47140 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47141 | virtual const char *Name() const { return "vabs2S_reg";} |
| 47142 | #endif |
| 47143 | }; |
| 47144 | |
| 47145 | class vabs4S_regNode : public MachTypeNode { |
| 47146 | private: |
| 47147 | MachOper *_opnd_array[2]; |
| 47148 | public: |
| 47149 | MachOper *opnd_array(uint operand_index) const { |
| 47150 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47151 | return _opnd_array[operand_index]; |
| 47152 | } |
| 47153 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47154 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47155 | _opnd_array[operand_index] = operand; |
| 47156 | } |
| 47157 | private: |
| 47158 | virtual const RegMask &out_RegMask() const; |
| 47159 | virtual uint rule() const { return vabs4S_reg_rule; } |
| 47160 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47161 | virtual int ideal_Opcode() const { return Op_AbsVS; } |
| 47162 | virtual uint oper_input_base() const { return 1; } |
| 47163 | public: |
| 47164 | vabs4S_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47165 | virtual uint size_of() const { return sizeof(vabs4S_regNode); } |
| 47166 | // Rematerialize vabs4S_reg |
| 47167 | static const Pipeline *pipeline_class(); |
| 47168 | virtual const Pipeline *pipeline() const; |
| 47169 | #ifndef PRODUCT |
| 47170 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47171 | virtual const char *Name() const { return "vabs4S_reg";} |
| 47172 | #endif |
| 47173 | }; |
| 47174 | |
| 47175 | class vabs8S_regNode : public MachTypeNode { |
| 47176 | private: |
| 47177 | MachOper *_opnd_array[2]; |
| 47178 | public: |
| 47179 | MachOper *opnd_array(uint operand_index) const { |
| 47180 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47181 | return _opnd_array[operand_index]; |
| 47182 | } |
| 47183 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47184 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47185 | _opnd_array[operand_index] = operand; |
| 47186 | } |
| 47187 | private: |
| 47188 | virtual const RegMask &out_RegMask() const; |
| 47189 | virtual uint rule() const { return vabs8S_reg_rule; } |
| 47190 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47191 | virtual int ideal_Opcode() const { return Op_AbsVS; } |
| 47192 | virtual uint oper_input_base() const { return 1; } |
| 47193 | public: |
| 47194 | vabs8S_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47195 | virtual uint size_of() const { return sizeof(vabs8S_regNode); } |
| 47196 | // Rematerialize vabs8S_reg |
| 47197 | static const Pipeline *pipeline_class(); |
| 47198 | virtual const Pipeline *pipeline() const; |
| 47199 | #ifndef PRODUCT |
| 47200 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47201 | virtual const char *Name() const { return "vabs8S_reg";} |
| 47202 | #endif |
| 47203 | }; |
| 47204 | |
| 47205 | class vabs16S_regNode : public MachTypeNode { |
| 47206 | private: |
| 47207 | MachOper *_opnd_array[2]; |
| 47208 | public: |
| 47209 | MachOper *opnd_array(uint operand_index) const { |
| 47210 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47211 | return _opnd_array[operand_index]; |
| 47212 | } |
| 47213 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47214 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47215 | _opnd_array[operand_index] = operand; |
| 47216 | } |
| 47217 | private: |
| 47218 | virtual const RegMask &out_RegMask() const; |
| 47219 | virtual uint rule() const { return vabs16S_reg_rule; } |
| 47220 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47221 | virtual int ideal_Opcode() const { return Op_AbsVS; } |
| 47222 | virtual uint oper_input_base() const { return 1; } |
| 47223 | public: |
| 47224 | vabs16S_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47225 | virtual uint size_of() const { return sizeof(vabs16S_regNode); } |
| 47226 | // Rematerialize vabs16S_reg |
| 47227 | static const Pipeline *pipeline_class(); |
| 47228 | virtual const Pipeline *pipeline() const; |
| 47229 | #ifndef PRODUCT |
| 47230 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47231 | virtual const char *Name() const { return "vabs16S_reg";} |
| 47232 | #endif |
| 47233 | }; |
| 47234 | |
| 47235 | class vabs32S_regNode : public MachTypeNode { |
| 47236 | private: |
| 47237 | MachOper *_opnd_array[2]; |
| 47238 | public: |
| 47239 | MachOper *opnd_array(uint operand_index) const { |
| 47240 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47241 | return _opnd_array[operand_index]; |
| 47242 | } |
| 47243 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47244 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47245 | _opnd_array[operand_index] = operand; |
| 47246 | } |
| 47247 | private: |
| 47248 | virtual const RegMask &out_RegMask() const; |
| 47249 | virtual uint rule() const { return vabs32S_reg_rule; } |
| 47250 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47251 | virtual int ideal_Opcode() const { return Op_AbsVS; } |
| 47252 | virtual uint oper_input_base() const { return 1; } |
| 47253 | public: |
| 47254 | vabs32S_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47255 | virtual uint size_of() const { return sizeof(vabs32S_regNode); } |
| 47256 | // Rematerialize vabs32S_reg |
| 47257 | static const Pipeline *pipeline_class(); |
| 47258 | virtual const Pipeline *pipeline() const; |
| 47259 | #ifndef PRODUCT |
| 47260 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47261 | virtual const char *Name() const { return "vabs32S_reg";} |
| 47262 | #endif |
| 47263 | }; |
| 47264 | |
| 47265 | class vabs2I_regNode : public MachTypeNode { |
| 47266 | private: |
| 47267 | MachOper *_opnd_array[2]; |
| 47268 | public: |
| 47269 | MachOper *opnd_array(uint operand_index) const { |
| 47270 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47271 | return _opnd_array[operand_index]; |
| 47272 | } |
| 47273 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47274 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47275 | _opnd_array[operand_index] = operand; |
| 47276 | } |
| 47277 | private: |
| 47278 | virtual const RegMask &out_RegMask() const; |
| 47279 | virtual uint rule() const { return vabs2I_reg_rule; } |
| 47280 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47281 | virtual int ideal_Opcode() const { return Op_AbsVI; } |
| 47282 | virtual uint oper_input_base() const { return 1; } |
| 47283 | public: |
| 47284 | vabs2I_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47285 | virtual uint size_of() const { return sizeof(vabs2I_regNode); } |
| 47286 | // Rematerialize vabs2I_reg |
| 47287 | static const Pipeline *pipeline_class(); |
| 47288 | virtual const Pipeline *pipeline() const; |
| 47289 | #ifndef PRODUCT |
| 47290 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47291 | virtual const char *Name() const { return "vabs2I_reg";} |
| 47292 | #endif |
| 47293 | }; |
| 47294 | |
| 47295 | class vabs4I_regNode : public MachTypeNode { |
| 47296 | private: |
| 47297 | MachOper *_opnd_array[2]; |
| 47298 | public: |
| 47299 | MachOper *opnd_array(uint operand_index) const { |
| 47300 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47301 | return _opnd_array[operand_index]; |
| 47302 | } |
| 47303 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47304 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47305 | _opnd_array[operand_index] = operand; |
| 47306 | } |
| 47307 | private: |
| 47308 | virtual const RegMask &out_RegMask() const; |
| 47309 | virtual uint rule() const { return vabs4I_reg_rule; } |
| 47310 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47311 | virtual int ideal_Opcode() const { return Op_AbsVI; } |
| 47312 | virtual uint oper_input_base() const { return 1; } |
| 47313 | public: |
| 47314 | vabs4I_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47315 | virtual uint size_of() const { return sizeof(vabs4I_regNode); } |
| 47316 | // Rematerialize vabs4I_reg |
| 47317 | static const Pipeline *pipeline_class(); |
| 47318 | virtual const Pipeline *pipeline() const; |
| 47319 | #ifndef PRODUCT |
| 47320 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47321 | virtual const char *Name() const { return "vabs4I_reg";} |
| 47322 | #endif |
| 47323 | }; |
| 47324 | |
| 47325 | class vabs8I_regNode : public MachTypeNode { |
| 47326 | private: |
| 47327 | MachOper *_opnd_array[2]; |
| 47328 | public: |
| 47329 | MachOper *opnd_array(uint operand_index) const { |
| 47330 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47331 | return _opnd_array[operand_index]; |
| 47332 | } |
| 47333 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47334 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47335 | _opnd_array[operand_index] = operand; |
| 47336 | } |
| 47337 | private: |
| 47338 | virtual const RegMask &out_RegMask() const; |
| 47339 | virtual uint rule() const { return vabs8I_reg_rule; } |
| 47340 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47341 | virtual int ideal_Opcode() const { return Op_AbsVI; } |
| 47342 | virtual uint oper_input_base() const { return 1; } |
| 47343 | public: |
| 47344 | vabs8I_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47345 | virtual uint size_of() const { return sizeof(vabs8I_regNode); } |
| 47346 | // Rematerialize vabs8I_reg |
| 47347 | static const Pipeline *pipeline_class(); |
| 47348 | virtual const Pipeline *pipeline() const; |
| 47349 | #ifndef PRODUCT |
| 47350 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47351 | virtual const char *Name() const { return "vabs8I_reg";} |
| 47352 | #endif |
| 47353 | }; |
| 47354 | |
| 47355 | class vabs16I_regNode : public MachTypeNode { |
| 47356 | private: |
| 47357 | MachOper *_opnd_array[2]; |
| 47358 | public: |
| 47359 | MachOper *opnd_array(uint operand_index) const { |
| 47360 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47361 | return _opnd_array[operand_index]; |
| 47362 | } |
| 47363 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47364 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47365 | _opnd_array[operand_index] = operand; |
| 47366 | } |
| 47367 | private: |
| 47368 | virtual const RegMask &out_RegMask() const; |
| 47369 | virtual uint rule() const { return vabs16I_reg_rule; } |
| 47370 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47371 | virtual int ideal_Opcode() const { return Op_AbsVI; } |
| 47372 | virtual uint oper_input_base() const { return 1; } |
| 47373 | public: |
| 47374 | vabs16I_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47375 | virtual uint size_of() const { return sizeof(vabs16I_regNode); } |
| 47376 | // Rematerialize vabs16I_reg |
| 47377 | static const Pipeline *pipeline_class(); |
| 47378 | virtual const Pipeline *pipeline() const; |
| 47379 | #ifndef PRODUCT |
| 47380 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47381 | virtual const char *Name() const { return "vabs16I_reg";} |
| 47382 | #endif |
| 47383 | }; |
| 47384 | |
| 47385 | class vabs2L_regNode : public MachTypeNode { |
| 47386 | private: |
| 47387 | MachOper *_opnd_array[2]; |
| 47388 | public: |
| 47389 | MachOper *opnd_array(uint operand_index) const { |
| 47390 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47391 | return _opnd_array[operand_index]; |
| 47392 | } |
| 47393 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47394 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47395 | _opnd_array[operand_index] = operand; |
| 47396 | } |
| 47397 | private: |
| 47398 | virtual const RegMask &out_RegMask() const; |
| 47399 | virtual uint rule() const { return vabs2L_reg_rule; } |
| 47400 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47401 | virtual int ideal_Opcode() const { return Op_AbsVL; } |
| 47402 | virtual uint oper_input_base() const { return 1; } |
| 47403 | public: |
| 47404 | vabs2L_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47405 | virtual uint size_of() const { return sizeof(vabs2L_regNode); } |
| 47406 | // Rematerialize vabs2L_reg |
| 47407 | static const Pipeline *pipeline_class(); |
| 47408 | virtual const Pipeline *pipeline() const; |
| 47409 | #ifndef PRODUCT |
| 47410 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47411 | virtual const char *Name() const { return "vabs2L_reg";} |
| 47412 | #endif |
| 47413 | }; |
| 47414 | |
| 47415 | class vabs4L_regNode : public MachTypeNode { |
| 47416 | private: |
| 47417 | MachOper *_opnd_array[2]; |
| 47418 | public: |
| 47419 | MachOper *opnd_array(uint operand_index) const { |
| 47420 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47421 | return _opnd_array[operand_index]; |
| 47422 | } |
| 47423 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47424 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47425 | _opnd_array[operand_index] = operand; |
| 47426 | } |
| 47427 | private: |
| 47428 | virtual const RegMask &out_RegMask() const; |
| 47429 | virtual uint rule() const { return vabs4L_reg_rule; } |
| 47430 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47431 | virtual int ideal_Opcode() const { return Op_AbsVL; } |
| 47432 | virtual uint oper_input_base() const { return 1; } |
| 47433 | public: |
| 47434 | vabs4L_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47435 | virtual uint size_of() const { return sizeof(vabs4L_regNode); } |
| 47436 | // Rematerialize vabs4L_reg |
| 47437 | static const Pipeline *pipeline_class(); |
| 47438 | virtual const Pipeline *pipeline() const; |
| 47439 | #ifndef PRODUCT |
| 47440 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47441 | virtual const char *Name() const { return "vabs4L_reg";} |
| 47442 | #endif |
| 47443 | }; |
| 47444 | |
| 47445 | class vabs8L_regNode : public MachTypeNode { |
| 47446 | private: |
| 47447 | MachOper *_opnd_array[2]; |
| 47448 | public: |
| 47449 | MachOper *opnd_array(uint operand_index) const { |
| 47450 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47451 | return _opnd_array[operand_index]; |
| 47452 | } |
| 47453 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47454 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47455 | _opnd_array[operand_index] = operand; |
| 47456 | } |
| 47457 | private: |
| 47458 | virtual const RegMask &out_RegMask() const; |
| 47459 | virtual uint rule() const { return vabs8L_reg_rule; } |
| 47460 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47461 | virtual int ideal_Opcode() const { return Op_AbsVL; } |
| 47462 | virtual uint oper_input_base() const { return 1; } |
| 47463 | public: |
| 47464 | vabs8L_regNode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 47465 | virtual uint size_of() const { return sizeof(vabs8L_regNode); } |
| 47466 | // Rematerialize vabs8L_reg |
| 47467 | static const Pipeline *pipeline_class(); |
| 47468 | virtual const Pipeline *pipeline() const; |
| 47469 | #ifndef PRODUCT |
| 47470 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47471 | virtual const char *Name() const { return "vabs8L_reg";} |
| 47472 | #endif |
| 47473 | }; |
| 47474 | |
| 47475 | class vabsneg2DNode : public MachTypeNode { |
| 47476 | private: |
| 47477 | MachOper *_opnd_array[3]; |
| 47478 | public: |
| 47479 | MachOper *opnd_array(uint operand_index) const { |
| 47480 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47481 | return _opnd_array[operand_index]; |
| 47482 | } |
| 47483 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47484 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47485 | _opnd_array[operand_index] = operand; |
| 47486 | } |
| 47487 | private: |
| 47488 | virtual const RegMask &out_RegMask() const; |
| 47489 | virtual uint rule() const { return vabsneg2D_rule; } |
| 47490 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47491 | virtual int ideal_Opcode() const { return Op_AbsVD; } |
| 47492 | virtual uint oper_input_base() const { return 1; } |
| 47493 | public: |
| 47494 | vabsneg2DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47495 | virtual uint size_of() const { return sizeof(vabsneg2DNode); } |
| 47496 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47497 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47498 | static const Pipeline *pipeline_class(); |
| 47499 | virtual const Pipeline *pipeline() const; |
| 47500 | #ifndef PRODUCT |
| 47501 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47502 | virtual const char *Name() const { return "vabsneg2D";} |
| 47503 | #endif |
| 47504 | }; |
| 47505 | |
| 47506 | class vabsneg2D_0Node : public MachTypeNode { |
| 47507 | private: |
| 47508 | MachOper *_opnd_array[3]; |
| 47509 | public: |
| 47510 | MachOper *opnd_array(uint operand_index) const { |
| 47511 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47512 | return _opnd_array[operand_index]; |
| 47513 | } |
| 47514 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47515 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47516 | _opnd_array[operand_index] = operand; |
| 47517 | } |
| 47518 | private: |
| 47519 | virtual const RegMask &out_RegMask() const; |
| 47520 | virtual uint rule() const { return vabsneg2D_0_rule; } |
| 47521 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47522 | virtual int ideal_Opcode() const { return Op_NegVD; } |
| 47523 | virtual uint oper_input_base() const { return 1; } |
| 47524 | public: |
| 47525 | vabsneg2D_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47526 | virtual uint size_of() const { return sizeof(vabsneg2D_0Node); } |
| 47527 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47528 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47529 | static const Pipeline *pipeline_class(); |
| 47530 | virtual const Pipeline *pipeline() const; |
| 47531 | #ifndef PRODUCT |
| 47532 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47533 | virtual const char *Name() const { return "vabsneg2D_0";} |
| 47534 | #endif |
| 47535 | }; |
| 47536 | |
| 47537 | class vabsneg4DNode : public MachTypeNode { |
| 47538 | private: |
| 47539 | MachOper *_opnd_array[3]; |
| 47540 | public: |
| 47541 | MachOper *opnd_array(uint operand_index) const { |
| 47542 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47543 | return _opnd_array[operand_index]; |
| 47544 | } |
| 47545 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47546 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47547 | _opnd_array[operand_index] = operand; |
| 47548 | } |
| 47549 | private: |
| 47550 | virtual const RegMask &out_RegMask() const; |
| 47551 | virtual uint rule() const { return vabsneg4D_rule; } |
| 47552 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47553 | virtual int ideal_Opcode() const { return Op_AbsVD; } |
| 47554 | virtual uint oper_input_base() const { return 1; } |
| 47555 | public: |
| 47556 | vabsneg4DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47557 | virtual uint size_of() const { return sizeof(vabsneg4DNode); } |
| 47558 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47559 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47560 | static const Pipeline *pipeline_class(); |
| 47561 | virtual const Pipeline *pipeline() const; |
| 47562 | #ifndef PRODUCT |
| 47563 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47564 | virtual const char *Name() const { return "vabsneg4D";} |
| 47565 | #endif |
| 47566 | }; |
| 47567 | |
| 47568 | class vabsneg4D_0Node : public MachTypeNode { |
| 47569 | private: |
| 47570 | MachOper *_opnd_array[3]; |
| 47571 | public: |
| 47572 | MachOper *opnd_array(uint operand_index) const { |
| 47573 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47574 | return _opnd_array[operand_index]; |
| 47575 | } |
| 47576 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47577 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47578 | _opnd_array[operand_index] = operand; |
| 47579 | } |
| 47580 | private: |
| 47581 | virtual const RegMask &out_RegMask() const; |
| 47582 | virtual uint rule() const { return vabsneg4D_0_rule; } |
| 47583 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47584 | virtual int ideal_Opcode() const { return Op_NegVD; } |
| 47585 | virtual uint oper_input_base() const { return 1; } |
| 47586 | public: |
| 47587 | vabsneg4D_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47588 | virtual uint size_of() const { return sizeof(vabsneg4D_0Node); } |
| 47589 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47590 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47591 | static const Pipeline *pipeline_class(); |
| 47592 | virtual const Pipeline *pipeline() const; |
| 47593 | #ifndef PRODUCT |
| 47594 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47595 | virtual const char *Name() const { return "vabsneg4D_0";} |
| 47596 | #endif |
| 47597 | }; |
| 47598 | |
| 47599 | class vabsneg8DNode : public MachTypeNode { |
| 47600 | private: |
| 47601 | MachOper *_opnd_array[3]; |
| 47602 | public: |
| 47603 | MachOper *opnd_array(uint operand_index) const { |
| 47604 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47605 | return _opnd_array[operand_index]; |
| 47606 | } |
| 47607 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47608 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47609 | _opnd_array[operand_index] = operand; |
| 47610 | } |
| 47611 | private: |
| 47612 | virtual const RegMask &out_RegMask() const; |
| 47613 | virtual uint rule() const { return vabsneg8D_rule; } |
| 47614 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47615 | virtual int ideal_Opcode() const { return Op_AbsVD; } |
| 47616 | virtual uint oper_input_base() const { return 1; } |
| 47617 | public: |
| 47618 | vabsneg8DNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47619 | virtual uint size_of() const { return sizeof(vabsneg8DNode); } |
| 47620 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47621 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47622 | static const Pipeline *pipeline_class(); |
| 47623 | virtual const Pipeline *pipeline() const; |
| 47624 | #ifndef PRODUCT |
| 47625 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47626 | virtual const char *Name() const { return "vabsneg8D";} |
| 47627 | #endif |
| 47628 | }; |
| 47629 | |
| 47630 | class vabsneg8D_0Node : public MachTypeNode { |
| 47631 | private: |
| 47632 | MachOper *_opnd_array[3]; |
| 47633 | public: |
| 47634 | MachOper *opnd_array(uint operand_index) const { |
| 47635 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47636 | return _opnd_array[operand_index]; |
| 47637 | } |
| 47638 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47639 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47640 | _opnd_array[operand_index] = operand; |
| 47641 | } |
| 47642 | private: |
| 47643 | virtual const RegMask &out_RegMask() const; |
| 47644 | virtual uint rule() const { return vabsneg8D_0_rule; } |
| 47645 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47646 | virtual int ideal_Opcode() const { return Op_NegVD; } |
| 47647 | virtual uint oper_input_base() const { return 1; } |
| 47648 | public: |
| 47649 | vabsneg8D_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47650 | virtual uint size_of() const { return sizeof(vabsneg8D_0Node); } |
| 47651 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47652 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47653 | static const Pipeline *pipeline_class(); |
| 47654 | virtual const Pipeline *pipeline() const; |
| 47655 | #ifndef PRODUCT |
| 47656 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47657 | virtual const char *Name() const { return "vabsneg8D_0";} |
| 47658 | #endif |
| 47659 | }; |
| 47660 | |
| 47661 | class vabsneg2FNode : public MachTypeNode { |
| 47662 | private: |
| 47663 | MachOper *_opnd_array[3]; |
| 47664 | public: |
| 47665 | MachOper *opnd_array(uint operand_index) const { |
| 47666 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47667 | return _opnd_array[operand_index]; |
| 47668 | } |
| 47669 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47670 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47671 | _opnd_array[operand_index] = operand; |
| 47672 | } |
| 47673 | private: |
| 47674 | virtual const RegMask &out_RegMask() const; |
| 47675 | virtual uint rule() const { return vabsneg2F_rule; } |
| 47676 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47677 | virtual int ideal_Opcode() const { return Op_AbsVF; } |
| 47678 | virtual uint oper_input_base() const { return 1; } |
| 47679 | public: |
| 47680 | vabsneg2FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47681 | virtual uint size_of() const { return sizeof(vabsneg2FNode); } |
| 47682 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47683 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47684 | static const Pipeline *pipeline_class(); |
| 47685 | virtual const Pipeline *pipeline() const; |
| 47686 | #ifndef PRODUCT |
| 47687 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47688 | virtual const char *Name() const { return "vabsneg2F";} |
| 47689 | #endif |
| 47690 | }; |
| 47691 | |
| 47692 | class vabsneg2F_0Node : public MachTypeNode { |
| 47693 | private: |
| 47694 | MachOper *_opnd_array[3]; |
| 47695 | public: |
| 47696 | MachOper *opnd_array(uint operand_index) const { |
| 47697 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47698 | return _opnd_array[operand_index]; |
| 47699 | } |
| 47700 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47701 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47702 | _opnd_array[operand_index] = operand; |
| 47703 | } |
| 47704 | private: |
| 47705 | virtual const RegMask &out_RegMask() const; |
| 47706 | virtual uint rule() const { return vabsneg2F_0_rule; } |
| 47707 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47708 | virtual int ideal_Opcode() const { return Op_NegVF; } |
| 47709 | virtual uint oper_input_base() const { return 1; } |
| 47710 | public: |
| 47711 | vabsneg2F_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47712 | virtual uint size_of() const { return sizeof(vabsneg2F_0Node); } |
| 47713 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47714 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47715 | static const Pipeline *pipeline_class(); |
| 47716 | virtual const Pipeline *pipeline() const; |
| 47717 | #ifndef PRODUCT |
| 47718 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47719 | virtual const char *Name() const { return "vabsneg2F_0";} |
| 47720 | #endif |
| 47721 | }; |
| 47722 | |
| 47723 | class vabsneg4FNode : public MachTypeNode { |
| 47724 | private: |
| 47725 | MachOper *_opnd_array[3]; |
| 47726 | public: |
| 47727 | MachOper *opnd_array(uint operand_index) const { |
| 47728 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47729 | return _opnd_array[operand_index]; |
| 47730 | } |
| 47731 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47732 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47733 | _opnd_array[operand_index] = operand; |
| 47734 | } |
| 47735 | private: |
| 47736 | virtual const RegMask &out_RegMask() const; |
| 47737 | virtual uint rule() const { return vabsneg4F_rule; } |
| 47738 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47739 | virtual int ideal_Opcode() const { return Op_AbsVF; } |
| 47740 | virtual uint two_adr() const { return oper_input_base(); } |
| 47741 | virtual uint oper_input_base() const { return 1; } |
| 47742 | public: |
| 47743 | vabsneg4FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47744 | virtual uint size_of() const { return sizeof(vabsneg4FNode); } |
| 47745 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47746 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47747 | static const Pipeline *pipeline_class(); |
| 47748 | virtual const Pipeline *pipeline() const; |
| 47749 | #ifndef PRODUCT |
| 47750 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47751 | virtual const char *Name() const { return "vabsneg4F";} |
| 47752 | #endif |
| 47753 | }; |
| 47754 | |
| 47755 | class vabsneg4F_0Node : public MachTypeNode { |
| 47756 | private: |
| 47757 | MachOper *_opnd_array[3]; |
| 47758 | public: |
| 47759 | MachOper *opnd_array(uint operand_index) const { |
| 47760 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47761 | return _opnd_array[operand_index]; |
| 47762 | } |
| 47763 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47765 | _opnd_array[operand_index] = operand; |
| 47766 | } |
| 47767 | private: |
| 47768 | virtual const RegMask &out_RegMask() const; |
| 47769 | virtual uint rule() const { return vabsneg4F_0_rule; } |
| 47770 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47771 | virtual int ideal_Opcode() const { return Op_NegVF; } |
| 47772 | virtual uint two_adr() const { return oper_input_base(); } |
| 47773 | virtual uint oper_input_base() const { return 1; } |
| 47774 | public: |
| 47775 | vabsneg4F_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47776 | virtual uint size_of() const { return sizeof(vabsneg4F_0Node); } |
| 47777 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47778 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47779 | static const Pipeline *pipeline_class(); |
| 47780 | virtual const Pipeline *pipeline() const; |
| 47781 | #ifndef PRODUCT |
| 47782 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47783 | virtual const char *Name() const { return "vabsneg4F_0";} |
| 47784 | #endif |
| 47785 | }; |
| 47786 | |
| 47787 | class vabsneg8FNode : public MachTypeNode { |
| 47788 | private: |
| 47789 | MachOper *_opnd_array[3]; |
| 47790 | public: |
| 47791 | MachOper *opnd_array(uint operand_index) const { |
| 47792 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47793 | return _opnd_array[operand_index]; |
| 47794 | } |
| 47795 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47796 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47797 | _opnd_array[operand_index] = operand; |
| 47798 | } |
| 47799 | private: |
| 47800 | virtual const RegMask &out_RegMask() const; |
| 47801 | virtual uint rule() const { return vabsneg8F_rule; } |
| 47802 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47803 | virtual int ideal_Opcode() const { return Op_AbsVF; } |
| 47804 | virtual uint oper_input_base() const { return 1; } |
| 47805 | public: |
| 47806 | vabsneg8FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47807 | virtual uint size_of() const { return sizeof(vabsneg8FNode); } |
| 47808 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47809 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47810 | static const Pipeline *pipeline_class(); |
| 47811 | virtual const Pipeline *pipeline() const; |
| 47812 | #ifndef PRODUCT |
| 47813 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47814 | virtual const char *Name() const { return "vabsneg8F";} |
| 47815 | #endif |
| 47816 | }; |
| 47817 | |
| 47818 | class vabsneg8F_0Node : public MachTypeNode { |
| 47819 | private: |
| 47820 | MachOper *_opnd_array[3]; |
| 47821 | public: |
| 47822 | MachOper *opnd_array(uint operand_index) const { |
| 47823 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47824 | return _opnd_array[operand_index]; |
| 47825 | } |
| 47826 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47827 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47828 | _opnd_array[operand_index] = operand; |
| 47829 | } |
| 47830 | private: |
| 47831 | virtual const RegMask &out_RegMask() const; |
| 47832 | virtual uint rule() const { return vabsneg8F_0_rule; } |
| 47833 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47834 | virtual int ideal_Opcode() const { return Op_NegVF; } |
| 47835 | virtual uint oper_input_base() const { return 1; } |
| 47836 | public: |
| 47837 | vabsneg8F_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47838 | virtual uint size_of() const { return sizeof(vabsneg8F_0Node); } |
| 47839 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47840 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47841 | static const Pipeline *pipeline_class(); |
| 47842 | virtual const Pipeline *pipeline() const; |
| 47843 | #ifndef PRODUCT |
| 47844 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47845 | virtual const char *Name() const { return "vabsneg8F_0";} |
| 47846 | #endif |
| 47847 | }; |
| 47848 | |
| 47849 | class vabsneg16FNode : public MachTypeNode { |
| 47850 | private: |
| 47851 | MachOper *_opnd_array[3]; |
| 47852 | public: |
| 47853 | MachOper *opnd_array(uint operand_index) const { |
| 47854 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47855 | return _opnd_array[operand_index]; |
| 47856 | } |
| 47857 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47858 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47859 | _opnd_array[operand_index] = operand; |
| 47860 | } |
| 47861 | private: |
| 47862 | virtual const RegMask &out_RegMask() const; |
| 47863 | virtual uint rule() const { return vabsneg16F_rule; } |
| 47864 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47865 | virtual int ideal_Opcode() const { return Op_AbsVF; } |
| 47866 | virtual uint oper_input_base() const { return 1; } |
| 47867 | public: |
| 47868 | vabsneg16FNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47869 | virtual uint size_of() const { return sizeof(vabsneg16FNode); } |
| 47870 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47871 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47872 | static const Pipeline *pipeline_class(); |
| 47873 | virtual const Pipeline *pipeline() const; |
| 47874 | #ifndef PRODUCT |
| 47875 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47876 | virtual const char *Name() const { return "vabsneg16F";} |
| 47877 | #endif |
| 47878 | }; |
| 47879 | |
| 47880 | class vabsneg16F_0Node : public MachTypeNode { |
| 47881 | private: |
| 47882 | MachOper *_opnd_array[3]; |
| 47883 | public: |
| 47884 | MachOper *opnd_array(uint operand_index) const { |
| 47885 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47886 | return _opnd_array[operand_index]; |
| 47887 | } |
| 47888 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47889 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47890 | _opnd_array[operand_index] = operand; |
| 47891 | } |
| 47892 | private: |
| 47893 | virtual const RegMask &out_RegMask() const; |
| 47894 | virtual uint rule() const { return vabsneg16F_0_rule; } |
| 47895 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47896 | virtual int ideal_Opcode() const { return Op_NegVF; } |
| 47897 | virtual uint oper_input_base() const { return 1; } |
| 47898 | public: |
| 47899 | vabsneg16F_0Node() { _num_opnds = 3; _opnds = _opnd_array; } |
| 47900 | virtual uint size_of() const { return sizeof(vabsneg16F_0Node); } |
| 47901 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 47902 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 47903 | static const Pipeline *pipeline_class(); |
| 47904 | virtual const Pipeline *pipeline() const; |
| 47905 | #ifndef PRODUCT |
| 47906 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47907 | virtual const char *Name() const { return "vabsneg16F_0";} |
| 47908 | #endif |
| 47909 | }; |
| 47910 | |
| 47911 | class vfma2D_regNode : public MachTypeNode { |
| 47912 | private: |
| 47913 | MachOper *_opnd_array[4]; |
| 47914 | public: |
| 47915 | MachOper *opnd_array(uint operand_index) const { |
| 47916 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47917 | return _opnd_array[operand_index]; |
| 47918 | } |
| 47919 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47920 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47921 | _opnd_array[operand_index] = operand; |
| 47922 | } |
| 47923 | private: |
| 47924 | virtual const RegMask &out_RegMask() const; |
| 47925 | virtual uint rule() const { return vfma2D_reg_rule; } |
| 47926 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47927 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 47928 | virtual uint two_adr() const { return oper_input_base(); } |
| 47929 | virtual uint oper_input_base() const { return 1; } |
| 47930 | public: |
| 47931 | vfma2D_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 47932 | virtual uint size_of() const { return sizeof(vfma2D_regNode); } |
| 47933 | static const Pipeline *pipeline_class(); |
| 47934 | virtual const Pipeline *pipeline() const; |
| 47935 | #ifndef PRODUCT |
| 47936 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47937 | virtual const char *Name() const { return "vfma2D_reg";} |
| 47938 | #endif |
| 47939 | }; |
| 47940 | |
| 47941 | class vfma2D_memNode : public MachTypeNode { |
| 47942 | private: |
| 47943 | MachOper *_opnd_array[4]; |
| 47944 | public: |
| 47945 | MachOper *opnd_array(uint operand_index) const { |
| 47946 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47947 | return _opnd_array[operand_index]; |
| 47948 | } |
| 47949 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47950 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47951 | _opnd_array[operand_index] = operand; |
| 47952 | } |
| 47953 | private: |
| 47954 | virtual const RegMask &out_RegMask() const; |
| 47955 | virtual uint rule() const { return vfma2D_mem_rule; } |
| 47956 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47957 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 47958 | virtual uint two_adr() const { return oper_input_base(); } |
| 47959 | virtual int reloc() const; |
| 47960 | virtual uint oper_input_base() const { return 2; } |
| 47961 | public: |
| 47962 | vfma2D_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 47963 | virtual uint size_of() const { return sizeof(vfma2D_memNode); } |
| 47964 | static const Pipeline *pipeline_class(); |
| 47965 | virtual const Pipeline *pipeline() const; |
| 47966 | virtual const MachOper *memory_operand() const; |
| 47967 | #ifndef PRODUCT |
| 47968 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47969 | virtual const char *Name() const { return "vfma2D_mem";} |
| 47970 | #endif |
| 47971 | }; |
| 47972 | |
| 47973 | class vfma4D_regNode : public MachTypeNode { |
| 47974 | private: |
| 47975 | MachOper *_opnd_array[4]; |
| 47976 | public: |
| 47977 | MachOper *opnd_array(uint operand_index) const { |
| 47978 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47979 | return _opnd_array[operand_index]; |
| 47980 | } |
| 47981 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 47982 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 47983 | _opnd_array[operand_index] = operand; |
| 47984 | } |
| 47985 | private: |
| 47986 | virtual const RegMask &out_RegMask() const; |
| 47987 | virtual uint rule() const { return vfma4D_reg_rule; } |
| 47988 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 47989 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 47990 | virtual uint two_adr() const { return oper_input_base(); } |
| 47991 | virtual uint oper_input_base() const { return 1; } |
| 47992 | public: |
| 47993 | vfma4D_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 47994 | virtual uint size_of() const { return sizeof(vfma4D_regNode); } |
| 47995 | static const Pipeline *pipeline_class(); |
| 47996 | virtual const Pipeline *pipeline() const; |
| 47997 | #ifndef PRODUCT |
| 47998 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 47999 | virtual const char *Name() const { return "vfma4D_reg";} |
| 48000 | #endif |
| 48001 | }; |
| 48002 | |
| 48003 | class vfma4D_memNode : public MachTypeNode { |
| 48004 | private: |
| 48005 | MachOper *_opnd_array[4]; |
| 48006 | public: |
| 48007 | MachOper *opnd_array(uint operand_index) const { |
| 48008 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48009 | return _opnd_array[operand_index]; |
| 48010 | } |
| 48011 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48012 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48013 | _opnd_array[operand_index] = operand; |
| 48014 | } |
| 48015 | private: |
| 48016 | virtual const RegMask &out_RegMask() const; |
| 48017 | virtual uint rule() const { return vfma4D_mem_rule; } |
| 48018 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48019 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 48020 | virtual uint two_adr() const { return oper_input_base(); } |
| 48021 | virtual int reloc() const; |
| 48022 | virtual uint oper_input_base() const { return 2; } |
| 48023 | public: |
| 48024 | vfma4D_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48025 | virtual uint size_of() const { return sizeof(vfma4D_memNode); } |
| 48026 | static const Pipeline *pipeline_class(); |
| 48027 | virtual const Pipeline *pipeline() const; |
| 48028 | virtual const MachOper *memory_operand() const; |
| 48029 | #ifndef PRODUCT |
| 48030 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48031 | virtual const char *Name() const { return "vfma4D_mem";} |
| 48032 | #endif |
| 48033 | }; |
| 48034 | |
| 48035 | class vfma8D_regNode : public MachTypeNode { |
| 48036 | private: |
| 48037 | MachOper *_opnd_array[4]; |
| 48038 | public: |
| 48039 | MachOper *opnd_array(uint operand_index) const { |
| 48040 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48041 | return _opnd_array[operand_index]; |
| 48042 | } |
| 48043 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48044 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48045 | _opnd_array[operand_index] = operand; |
| 48046 | } |
| 48047 | private: |
| 48048 | virtual const RegMask &out_RegMask() const; |
| 48049 | virtual uint rule() const { return vfma8D_reg_rule; } |
| 48050 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48051 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 48052 | virtual uint two_adr() const { return oper_input_base(); } |
| 48053 | virtual uint oper_input_base() const { return 1; } |
| 48054 | public: |
| 48055 | vfma8D_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48056 | virtual uint size_of() const { return sizeof(vfma8D_regNode); } |
| 48057 | static const Pipeline *pipeline_class(); |
| 48058 | virtual const Pipeline *pipeline() const; |
| 48059 | #ifndef PRODUCT |
| 48060 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48061 | virtual const char *Name() const { return "vfma8D_reg";} |
| 48062 | #endif |
| 48063 | }; |
| 48064 | |
| 48065 | class vfma8D_memNode : public MachTypeNode { |
| 48066 | private: |
| 48067 | MachOper *_opnd_array[4]; |
| 48068 | public: |
| 48069 | MachOper *opnd_array(uint operand_index) const { |
| 48070 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48071 | return _opnd_array[operand_index]; |
| 48072 | } |
| 48073 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48074 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48075 | _opnd_array[operand_index] = operand; |
| 48076 | } |
| 48077 | private: |
| 48078 | virtual const RegMask &out_RegMask() const; |
| 48079 | virtual uint rule() const { return vfma8D_mem_rule; } |
| 48080 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48081 | virtual int ideal_Opcode() const { return Op_FmaVD; } |
| 48082 | virtual uint two_adr() const { return oper_input_base(); } |
| 48083 | virtual int reloc() const; |
| 48084 | virtual uint oper_input_base() const { return 2; } |
| 48085 | public: |
| 48086 | vfma8D_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48087 | virtual uint size_of() const { return sizeof(vfma8D_memNode); } |
| 48088 | static const Pipeline *pipeline_class(); |
| 48089 | virtual const Pipeline *pipeline() const; |
| 48090 | virtual const MachOper *memory_operand() const; |
| 48091 | #ifndef PRODUCT |
| 48092 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48093 | virtual const char *Name() const { return "vfma8D_mem";} |
| 48094 | #endif |
| 48095 | }; |
| 48096 | |
| 48097 | class vfma4F_regNode : public MachTypeNode { |
| 48098 | private: |
| 48099 | MachOper *_opnd_array[4]; |
| 48100 | public: |
| 48101 | MachOper *opnd_array(uint operand_index) const { |
| 48102 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48103 | return _opnd_array[operand_index]; |
| 48104 | } |
| 48105 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48106 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48107 | _opnd_array[operand_index] = operand; |
| 48108 | } |
| 48109 | private: |
| 48110 | virtual const RegMask &out_RegMask() const; |
| 48111 | virtual uint rule() const { return vfma4F_reg_rule; } |
| 48112 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48113 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48114 | virtual uint two_adr() const { return oper_input_base(); } |
| 48115 | virtual uint oper_input_base() const { return 1; } |
| 48116 | public: |
| 48117 | vfma4F_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48118 | virtual uint size_of() const { return sizeof(vfma4F_regNode); } |
| 48119 | static const Pipeline *pipeline_class(); |
| 48120 | virtual const Pipeline *pipeline() const; |
| 48121 | #ifndef PRODUCT |
| 48122 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48123 | virtual const char *Name() const { return "vfma4F_reg";} |
| 48124 | #endif |
| 48125 | }; |
| 48126 | |
| 48127 | class vfma4F_memNode : public MachTypeNode { |
| 48128 | private: |
| 48129 | MachOper *_opnd_array[4]; |
| 48130 | public: |
| 48131 | MachOper *opnd_array(uint operand_index) const { |
| 48132 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48133 | return _opnd_array[operand_index]; |
| 48134 | } |
| 48135 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48136 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48137 | _opnd_array[operand_index] = operand; |
| 48138 | } |
| 48139 | private: |
| 48140 | virtual const RegMask &out_RegMask() const; |
| 48141 | virtual uint rule() const { return vfma4F_mem_rule; } |
| 48142 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48143 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48144 | virtual uint two_adr() const { return oper_input_base(); } |
| 48145 | virtual int reloc() const; |
| 48146 | virtual uint oper_input_base() const { return 2; } |
| 48147 | public: |
| 48148 | vfma4F_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48149 | virtual uint size_of() const { return sizeof(vfma4F_memNode); } |
| 48150 | static const Pipeline *pipeline_class(); |
| 48151 | virtual const Pipeline *pipeline() const; |
| 48152 | virtual const MachOper *memory_operand() const; |
| 48153 | #ifndef PRODUCT |
| 48154 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48155 | virtual const char *Name() const { return "vfma4F_mem";} |
| 48156 | #endif |
| 48157 | }; |
| 48158 | |
| 48159 | class vfma8F_regNode : public MachTypeNode { |
| 48160 | private: |
| 48161 | MachOper *_opnd_array[4]; |
| 48162 | public: |
| 48163 | MachOper *opnd_array(uint operand_index) const { |
| 48164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48165 | return _opnd_array[operand_index]; |
| 48166 | } |
| 48167 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48168 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48169 | _opnd_array[operand_index] = operand; |
| 48170 | } |
| 48171 | private: |
| 48172 | virtual const RegMask &out_RegMask() const; |
| 48173 | virtual uint rule() const { return vfma8F_reg_rule; } |
| 48174 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48175 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48176 | virtual uint two_adr() const { return oper_input_base(); } |
| 48177 | virtual uint oper_input_base() const { return 1; } |
| 48178 | public: |
| 48179 | vfma8F_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48180 | virtual uint size_of() const { return sizeof(vfma8F_regNode); } |
| 48181 | static const Pipeline *pipeline_class(); |
| 48182 | virtual const Pipeline *pipeline() const; |
| 48183 | #ifndef PRODUCT |
| 48184 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48185 | virtual const char *Name() const { return "vfma8F_reg";} |
| 48186 | #endif |
| 48187 | }; |
| 48188 | |
| 48189 | class vfma8F_memNode : public MachTypeNode { |
| 48190 | private: |
| 48191 | MachOper *_opnd_array[4]; |
| 48192 | public: |
| 48193 | MachOper *opnd_array(uint operand_index) const { |
| 48194 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48195 | return _opnd_array[operand_index]; |
| 48196 | } |
| 48197 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48198 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48199 | _opnd_array[operand_index] = operand; |
| 48200 | } |
| 48201 | private: |
| 48202 | virtual const RegMask &out_RegMask() const; |
| 48203 | virtual uint rule() const { return vfma8F_mem_rule; } |
| 48204 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48205 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48206 | virtual uint two_adr() const { return oper_input_base(); } |
| 48207 | virtual int reloc() const; |
| 48208 | virtual uint oper_input_base() const { return 2; } |
| 48209 | public: |
| 48210 | vfma8F_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48211 | virtual uint size_of() const { return sizeof(vfma8F_memNode); } |
| 48212 | static const Pipeline *pipeline_class(); |
| 48213 | virtual const Pipeline *pipeline() const; |
| 48214 | virtual const MachOper *memory_operand() const; |
| 48215 | #ifndef PRODUCT |
| 48216 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48217 | virtual const char *Name() const { return "vfma8F_mem";} |
| 48218 | #endif |
| 48219 | }; |
| 48220 | |
| 48221 | class vfma16F_regNode : public MachTypeNode { |
| 48222 | private: |
| 48223 | MachOper *_opnd_array[4]; |
| 48224 | public: |
| 48225 | MachOper *opnd_array(uint operand_index) const { |
| 48226 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48227 | return _opnd_array[operand_index]; |
| 48228 | } |
| 48229 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48230 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48231 | _opnd_array[operand_index] = operand; |
| 48232 | } |
| 48233 | private: |
| 48234 | virtual const RegMask &out_RegMask() const; |
| 48235 | virtual uint rule() const { return vfma16F_reg_rule; } |
| 48236 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48237 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48238 | virtual uint two_adr() const { return oper_input_base(); } |
| 48239 | virtual uint oper_input_base() const { return 1; } |
| 48240 | public: |
| 48241 | vfma16F_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48242 | virtual uint size_of() const { return sizeof(vfma16F_regNode); } |
| 48243 | static const Pipeline *pipeline_class(); |
| 48244 | virtual const Pipeline *pipeline() const; |
| 48245 | #ifndef PRODUCT |
| 48246 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48247 | virtual const char *Name() const { return "vfma16F_reg";} |
| 48248 | #endif |
| 48249 | }; |
| 48250 | |
| 48251 | class vfma16F_memNode : public MachTypeNode { |
| 48252 | private: |
| 48253 | MachOper *_opnd_array[4]; |
| 48254 | public: |
| 48255 | MachOper *opnd_array(uint operand_index) const { |
| 48256 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48257 | return _opnd_array[operand_index]; |
| 48258 | } |
| 48259 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48260 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48261 | _opnd_array[operand_index] = operand; |
| 48262 | } |
| 48263 | private: |
| 48264 | virtual const RegMask &out_RegMask() const; |
| 48265 | virtual uint rule() const { return vfma16F_mem_rule; } |
| 48266 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48267 | virtual int ideal_Opcode() const { return Op_FmaVF; } |
| 48268 | virtual uint two_adr() const { return oper_input_base(); } |
| 48269 | virtual int reloc() const; |
| 48270 | virtual uint oper_input_base() const { return 2; } |
| 48271 | public: |
| 48272 | vfma16F_memNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48273 | virtual uint size_of() const { return sizeof(vfma16F_memNode); } |
| 48274 | static const Pipeline *pipeline_class(); |
| 48275 | virtual const Pipeline *pipeline() const; |
| 48276 | virtual const MachOper *memory_operand() const; |
| 48277 | #ifndef PRODUCT |
| 48278 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48279 | virtual const char *Name() const { return "vfma16F_mem";} |
| 48280 | #endif |
| 48281 | }; |
| 48282 | |
| 48283 | class smuladd4S2I_regNode : public MachTypeNode { |
| 48284 | private: |
| 48285 | MachOper *_opnd_array[3]; |
| 48286 | public: |
| 48287 | MachOper *opnd_array(uint operand_index) const { |
| 48288 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48289 | return _opnd_array[operand_index]; |
| 48290 | } |
| 48291 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48292 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48293 | _opnd_array[operand_index] = operand; |
| 48294 | } |
| 48295 | private: |
| 48296 | virtual const RegMask &out_RegMask() const; |
| 48297 | virtual uint rule() const { return smuladd4S2I_reg_rule; } |
| 48298 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48299 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48300 | virtual uint two_adr() const { return oper_input_base(); } |
| 48301 | virtual uint oper_input_base() const { return 1; } |
| 48302 | public: |
| 48303 | smuladd4S2I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48304 | virtual uint size_of() const { return sizeof(smuladd4S2I_regNode); } |
| 48305 | static const Pipeline *pipeline_class(); |
| 48306 | virtual const Pipeline *pipeline() const; |
| 48307 | #ifndef PRODUCT |
| 48308 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48309 | virtual const char *Name() const { return "smuladd4S2I_reg";} |
| 48310 | #endif |
| 48311 | }; |
| 48312 | |
| 48313 | class vmuladd4S2I_regNode : public MachTypeNode { |
| 48314 | private: |
| 48315 | MachOper *_opnd_array[3]; |
| 48316 | public: |
| 48317 | MachOper *opnd_array(uint operand_index) const { |
| 48318 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48319 | return _opnd_array[operand_index]; |
| 48320 | } |
| 48321 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48322 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48323 | _opnd_array[operand_index] = operand; |
| 48324 | } |
| 48325 | private: |
| 48326 | virtual const RegMask &out_RegMask() const; |
| 48327 | virtual uint rule() const { return vmuladd4S2I_reg_rule; } |
| 48328 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48329 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48330 | virtual uint oper_input_base() const { return 1; } |
| 48331 | public: |
| 48332 | vmuladd4S2I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48333 | virtual uint size_of() const { return sizeof(vmuladd4S2I_regNode); } |
| 48334 | static const Pipeline *pipeline_class(); |
| 48335 | virtual const Pipeline *pipeline() const; |
| 48336 | #ifndef PRODUCT |
| 48337 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48338 | virtual const char *Name() const { return "vmuladd4S2I_reg";} |
| 48339 | #endif |
| 48340 | }; |
| 48341 | |
| 48342 | class smuladd8S4I_regNode : public MachTypeNode { |
| 48343 | private: |
| 48344 | MachOper *_opnd_array[3]; |
| 48345 | public: |
| 48346 | MachOper *opnd_array(uint operand_index) const { |
| 48347 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48348 | return _opnd_array[operand_index]; |
| 48349 | } |
| 48350 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48351 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48352 | _opnd_array[operand_index] = operand; |
| 48353 | } |
| 48354 | private: |
| 48355 | virtual const RegMask &out_RegMask() const; |
| 48356 | virtual uint rule() const { return smuladd8S4I_reg_rule; } |
| 48357 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48358 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48359 | virtual uint two_adr() const { return oper_input_base(); } |
| 48360 | virtual uint oper_input_base() const { return 1; } |
| 48361 | public: |
| 48362 | smuladd8S4I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48363 | virtual uint size_of() const { return sizeof(smuladd8S4I_regNode); } |
| 48364 | static const Pipeline *pipeline_class(); |
| 48365 | virtual const Pipeline *pipeline() const; |
| 48366 | #ifndef PRODUCT |
| 48367 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48368 | virtual const char *Name() const { return "smuladd8S4I_reg";} |
| 48369 | #endif |
| 48370 | }; |
| 48371 | |
| 48372 | class vmuladd8S4I_regNode : public MachTypeNode { |
| 48373 | private: |
| 48374 | MachOper *_opnd_array[3]; |
| 48375 | public: |
| 48376 | MachOper *opnd_array(uint operand_index) const { |
| 48377 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48378 | return _opnd_array[operand_index]; |
| 48379 | } |
| 48380 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48381 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48382 | _opnd_array[operand_index] = operand; |
| 48383 | } |
| 48384 | private: |
| 48385 | virtual const RegMask &out_RegMask() const; |
| 48386 | virtual uint rule() const { return vmuladd8S4I_reg_rule; } |
| 48387 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48388 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48389 | virtual uint oper_input_base() const { return 1; } |
| 48390 | public: |
| 48391 | vmuladd8S4I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48392 | virtual uint size_of() const { return sizeof(vmuladd8S4I_regNode); } |
| 48393 | static const Pipeline *pipeline_class(); |
| 48394 | virtual const Pipeline *pipeline() const; |
| 48395 | #ifndef PRODUCT |
| 48396 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48397 | virtual const char *Name() const { return "vmuladd8S4I_reg";} |
| 48398 | #endif |
| 48399 | }; |
| 48400 | |
| 48401 | class vmuladd16S8I_regNode : public MachTypeNode { |
| 48402 | private: |
| 48403 | MachOper *_opnd_array[3]; |
| 48404 | public: |
| 48405 | MachOper *opnd_array(uint operand_index) const { |
| 48406 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48407 | return _opnd_array[operand_index]; |
| 48408 | } |
| 48409 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48410 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48411 | _opnd_array[operand_index] = operand; |
| 48412 | } |
| 48413 | private: |
| 48414 | virtual const RegMask &out_RegMask() const; |
| 48415 | virtual uint rule() const { return vmuladd16S8I_reg_rule; } |
| 48416 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48417 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48418 | virtual uint oper_input_base() const { return 1; } |
| 48419 | public: |
| 48420 | vmuladd16S8I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48421 | virtual uint size_of() const { return sizeof(vmuladd16S8I_regNode); } |
| 48422 | static const Pipeline *pipeline_class(); |
| 48423 | virtual const Pipeline *pipeline() const; |
| 48424 | #ifndef PRODUCT |
| 48425 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48426 | virtual const char *Name() const { return "vmuladd16S8I_reg";} |
| 48427 | #endif |
| 48428 | }; |
| 48429 | |
| 48430 | class vmuladd32S16I_regNode : public MachTypeNode { |
| 48431 | private: |
| 48432 | MachOper *_opnd_array[3]; |
| 48433 | public: |
| 48434 | MachOper *opnd_array(uint operand_index) const { |
| 48435 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48436 | return _opnd_array[operand_index]; |
| 48437 | } |
| 48438 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48439 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48440 | _opnd_array[operand_index] = operand; |
| 48441 | } |
| 48442 | private: |
| 48443 | virtual const RegMask &out_RegMask() const; |
| 48444 | virtual uint rule() const { return vmuladd32S16I_reg_rule; } |
| 48445 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48446 | virtual int ideal_Opcode() const { return Op_MulAddVS2VI; } |
| 48447 | virtual uint oper_input_base() const { return 1; } |
| 48448 | public: |
| 48449 | vmuladd32S16I_regNode() { _num_opnds = 3; _opnds = _opnd_array; } |
| 48450 | virtual uint size_of() const { return sizeof(vmuladd32S16I_regNode); } |
| 48451 | static const Pipeline *pipeline_class(); |
| 48452 | virtual const Pipeline *pipeline() const; |
| 48453 | #ifndef PRODUCT |
| 48454 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48455 | virtual const char *Name() const { return "vmuladd32S16I_reg";} |
| 48456 | #endif |
| 48457 | }; |
| 48458 | |
| 48459 | class vmuladdadd4S2I_regNode : public MachTypeNode { |
| 48460 | private: |
| 48461 | MachOper *_opnd_array[4]; |
| 48462 | public: |
| 48463 | MachOper *opnd_array(uint operand_index) const { |
| 48464 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48465 | return _opnd_array[operand_index]; |
| 48466 | } |
| 48467 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48468 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48469 | _opnd_array[operand_index] = operand; |
| 48470 | } |
| 48471 | private: |
| 48472 | virtual const RegMask &out_RegMask() const; |
| 48473 | virtual uint rule() const { return vmuladdadd4S2I_reg_rule; } |
| 48474 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48475 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48476 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 48477 | virtual uint oper_input_base() const { return 1; } |
| 48478 | public: |
| 48479 | vmuladdadd4S2I_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48480 | virtual uint size_of() const { return sizeof(vmuladdadd4S2I_regNode); } |
| 48481 | static const Pipeline *pipeline_class(); |
| 48482 | virtual const Pipeline *pipeline() const; |
| 48483 | #ifndef PRODUCT |
| 48484 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48485 | virtual const char *Name() const { return "vmuladdadd4S2I_reg";} |
| 48486 | #endif |
| 48487 | }; |
| 48488 | |
| 48489 | class vmuladdadd4S2I_reg_0Node : public MachTypeNode { |
| 48490 | private: |
| 48491 | MachOper *_opnd_array[4]; |
| 48492 | public: |
| 48493 | MachOper *opnd_array(uint operand_index) const { |
| 48494 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48495 | return _opnd_array[operand_index]; |
| 48496 | } |
| 48497 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48498 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48499 | _opnd_array[operand_index] = operand; |
| 48500 | } |
| 48501 | private: |
| 48502 | virtual const RegMask &out_RegMask() const; |
| 48503 | virtual uint rule() const { return vmuladdadd4S2I_reg_0_rule; } |
| 48504 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48505 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48506 | virtual uint two_adr() const { return oper_input_base(); } |
| 48507 | virtual uint oper_input_base() const { return 1; } |
| 48508 | public: |
| 48509 | vmuladdadd4S2I_reg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48510 | virtual uint size_of() const { return sizeof(vmuladdadd4S2I_reg_0Node); } |
| 48511 | static const Pipeline *pipeline_class(); |
| 48512 | virtual const Pipeline *pipeline() const; |
| 48513 | #ifndef PRODUCT |
| 48514 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48515 | virtual const char *Name() const { return "vmuladdadd4S2I_reg_0";} |
| 48516 | #endif |
| 48517 | }; |
| 48518 | |
| 48519 | class vmuladdadd8S4I_regNode : public MachTypeNode { |
| 48520 | private: |
| 48521 | MachOper *_opnd_array[4]; |
| 48522 | public: |
| 48523 | MachOper *opnd_array(uint operand_index) const { |
| 48524 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48525 | return _opnd_array[operand_index]; |
| 48526 | } |
| 48527 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48528 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48529 | _opnd_array[operand_index] = operand; |
| 48530 | } |
| 48531 | private: |
| 48532 | virtual const RegMask &out_RegMask() const; |
| 48533 | virtual uint rule() const { return vmuladdadd8S4I_reg_rule; } |
| 48534 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48535 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48536 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 48537 | virtual uint oper_input_base() const { return 1; } |
| 48538 | public: |
| 48539 | vmuladdadd8S4I_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48540 | virtual uint size_of() const { return sizeof(vmuladdadd8S4I_regNode); } |
| 48541 | static const Pipeline *pipeline_class(); |
| 48542 | virtual const Pipeline *pipeline() const; |
| 48543 | #ifndef PRODUCT |
| 48544 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48545 | virtual const char *Name() const { return "vmuladdadd8S4I_reg";} |
| 48546 | #endif |
| 48547 | }; |
| 48548 | |
| 48549 | class vmuladdadd8S4I_reg_0Node : public MachTypeNode { |
| 48550 | private: |
| 48551 | MachOper *_opnd_array[4]; |
| 48552 | public: |
| 48553 | MachOper *opnd_array(uint operand_index) const { |
| 48554 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48555 | return _opnd_array[operand_index]; |
| 48556 | } |
| 48557 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48558 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48559 | _opnd_array[operand_index] = operand; |
| 48560 | } |
| 48561 | private: |
| 48562 | virtual const RegMask &out_RegMask() const; |
| 48563 | virtual uint rule() const { return vmuladdadd8S4I_reg_0_rule; } |
| 48564 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48565 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48566 | virtual uint two_adr() const { return oper_input_base(); } |
| 48567 | virtual uint oper_input_base() const { return 1; } |
| 48568 | public: |
| 48569 | vmuladdadd8S4I_reg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48570 | virtual uint size_of() const { return sizeof(vmuladdadd8S4I_reg_0Node); } |
| 48571 | static const Pipeline *pipeline_class(); |
| 48572 | virtual const Pipeline *pipeline() const; |
| 48573 | #ifndef PRODUCT |
| 48574 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48575 | virtual const char *Name() const { return "vmuladdadd8S4I_reg_0";} |
| 48576 | #endif |
| 48577 | }; |
| 48578 | |
| 48579 | class vmuladdadd16S8I_regNode : public MachTypeNode { |
| 48580 | private: |
| 48581 | MachOper *_opnd_array[4]; |
| 48582 | public: |
| 48583 | MachOper *opnd_array(uint operand_index) const { |
| 48584 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48585 | return _opnd_array[operand_index]; |
| 48586 | } |
| 48587 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48588 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48589 | _opnd_array[operand_index] = operand; |
| 48590 | } |
| 48591 | private: |
| 48592 | virtual const RegMask &out_RegMask() const; |
| 48593 | virtual uint rule() const { return vmuladdadd16S8I_reg_rule; } |
| 48594 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48595 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48596 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 48597 | virtual uint oper_input_base() const { return 1; } |
| 48598 | public: |
| 48599 | vmuladdadd16S8I_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48600 | virtual uint size_of() const { return sizeof(vmuladdadd16S8I_regNode); } |
| 48601 | static const Pipeline *pipeline_class(); |
| 48602 | virtual const Pipeline *pipeline() const; |
| 48603 | #ifndef PRODUCT |
| 48604 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48605 | virtual const char *Name() const { return "vmuladdadd16S8I_reg";} |
| 48606 | #endif |
| 48607 | }; |
| 48608 | |
| 48609 | class vmuladdadd16S8I_reg_0Node : public MachTypeNode { |
| 48610 | private: |
| 48611 | MachOper *_opnd_array[4]; |
| 48612 | public: |
| 48613 | MachOper *opnd_array(uint operand_index) const { |
| 48614 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48615 | return _opnd_array[operand_index]; |
| 48616 | } |
| 48617 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48618 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48619 | _opnd_array[operand_index] = operand; |
| 48620 | } |
| 48621 | private: |
| 48622 | virtual const RegMask &out_RegMask() const; |
| 48623 | virtual uint rule() const { return vmuladdadd16S8I_reg_0_rule; } |
| 48624 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48625 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48626 | virtual uint two_adr() const { return oper_input_base(); } |
| 48627 | virtual uint oper_input_base() const { return 1; } |
| 48628 | public: |
| 48629 | vmuladdadd16S8I_reg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48630 | virtual uint size_of() const { return sizeof(vmuladdadd16S8I_reg_0Node); } |
| 48631 | static const Pipeline *pipeline_class(); |
| 48632 | virtual const Pipeline *pipeline() const; |
| 48633 | #ifndef PRODUCT |
| 48634 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48635 | virtual const char *Name() const { return "vmuladdadd16S8I_reg_0";} |
| 48636 | #endif |
| 48637 | }; |
| 48638 | |
| 48639 | class vmuladdadd32S16I_regNode : public MachTypeNode { |
| 48640 | private: |
| 48641 | MachOper *_opnd_array[4]; |
| 48642 | public: |
| 48643 | MachOper *opnd_array(uint operand_index) const { |
| 48644 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48645 | return _opnd_array[operand_index]; |
| 48646 | } |
| 48647 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48648 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48649 | _opnd_array[operand_index] = operand; |
| 48650 | } |
| 48651 | private: |
| 48652 | virtual const RegMask &out_RegMask() const; |
| 48653 | virtual uint rule() const { return vmuladdadd32S16I_reg_rule; } |
| 48654 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48655 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48656 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 48657 | virtual uint oper_input_base() const { return 1; } |
| 48658 | public: |
| 48659 | vmuladdadd32S16I_regNode() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48660 | virtual uint size_of() const { return sizeof(vmuladdadd32S16I_regNode); } |
| 48661 | static const Pipeline *pipeline_class(); |
| 48662 | virtual const Pipeline *pipeline() const; |
| 48663 | #ifndef PRODUCT |
| 48664 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48665 | virtual const char *Name() const { return "vmuladdadd32S16I_reg";} |
| 48666 | #endif |
| 48667 | }; |
| 48668 | |
| 48669 | class vmuladdadd32S16I_reg_0Node : public MachTypeNode { |
| 48670 | private: |
| 48671 | MachOper *_opnd_array[4]; |
| 48672 | public: |
| 48673 | MachOper *opnd_array(uint operand_index) const { |
| 48674 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48675 | return _opnd_array[operand_index]; |
| 48676 | } |
| 48677 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48678 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48679 | _opnd_array[operand_index] = operand; |
| 48680 | } |
| 48681 | private: |
| 48682 | virtual const RegMask &out_RegMask() const; |
| 48683 | virtual uint rule() const { return vmuladdadd32S16I_reg_0_rule; } |
| 48684 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48685 | virtual int ideal_Opcode() const { return Op_AddVI; } |
| 48686 | virtual uint two_adr() const { return oper_input_base(); } |
| 48687 | virtual uint oper_input_base() const { return 1; } |
| 48688 | public: |
| 48689 | vmuladdadd32S16I_reg_0Node() { _num_opnds = 4; _opnds = _opnd_array; } |
| 48690 | virtual uint size_of() const { return sizeof(vmuladdadd32S16I_reg_0Node); } |
| 48691 | static const Pipeline *pipeline_class(); |
| 48692 | virtual const Pipeline *pipeline() const; |
| 48693 | #ifndef PRODUCT |
| 48694 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48695 | virtual const char *Name() const { return "vmuladdadd32S16I_reg_0";} |
| 48696 | #endif |
| 48697 | }; |
| 48698 | |
| 48699 | class vpopcount2INode : public MachTypeNode { |
| 48700 | private: |
| 48701 | MachOper *_opnd_array[2]; |
| 48702 | public: |
| 48703 | MachOper *opnd_array(uint operand_index) const { |
| 48704 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48705 | return _opnd_array[operand_index]; |
| 48706 | } |
| 48707 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48708 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48709 | _opnd_array[operand_index] = operand; |
| 48710 | } |
| 48711 | private: |
| 48712 | virtual const RegMask &out_RegMask() const; |
| 48713 | virtual uint rule() const { return vpopcount2I_rule; } |
| 48714 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48715 | virtual int ideal_Opcode() const { return Op_PopCountVI; } |
| 48716 | virtual uint oper_input_base() const { return 1; } |
| 48717 | public: |
| 48718 | vpopcount2INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 48719 | virtual uint size_of() const { return sizeof(vpopcount2INode); } |
| 48720 | // Rematerialize vpopcount2I |
| 48721 | static const Pipeline *pipeline_class(); |
| 48722 | virtual const Pipeline *pipeline() const; |
| 48723 | #ifndef PRODUCT |
| 48724 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48725 | virtual const char *Name() const { return "vpopcount2I";} |
| 48726 | #endif |
| 48727 | }; |
| 48728 | |
| 48729 | class vpopcount4INode : public MachTypeNode { |
| 48730 | private: |
| 48731 | MachOper *_opnd_array[2]; |
| 48732 | public: |
| 48733 | MachOper *opnd_array(uint operand_index) const { |
| 48734 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48735 | return _opnd_array[operand_index]; |
| 48736 | } |
| 48737 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48738 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48739 | _opnd_array[operand_index] = operand; |
| 48740 | } |
| 48741 | private: |
| 48742 | virtual const RegMask &out_RegMask() const; |
| 48743 | virtual uint rule() const { return vpopcount4I_rule; } |
| 48744 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48745 | virtual int ideal_Opcode() const { return Op_PopCountVI; } |
| 48746 | virtual uint oper_input_base() const { return 1; } |
| 48747 | public: |
| 48748 | vpopcount4INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 48749 | virtual uint size_of() const { return sizeof(vpopcount4INode); } |
| 48750 | // Rematerialize vpopcount4I |
| 48751 | static const Pipeline *pipeline_class(); |
| 48752 | virtual const Pipeline *pipeline() const; |
| 48753 | #ifndef PRODUCT |
| 48754 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48755 | virtual const char *Name() const { return "vpopcount4I";} |
| 48756 | #endif |
| 48757 | }; |
| 48758 | |
| 48759 | class vpopcount8INode : public MachTypeNode { |
| 48760 | private: |
| 48761 | MachOper *_opnd_array[2]; |
| 48762 | public: |
| 48763 | MachOper *opnd_array(uint operand_index) const { |
| 48764 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48765 | return _opnd_array[operand_index]; |
| 48766 | } |
| 48767 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48768 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48769 | _opnd_array[operand_index] = operand; |
| 48770 | } |
| 48771 | private: |
| 48772 | virtual const RegMask &out_RegMask() const; |
| 48773 | virtual uint rule() const { return vpopcount8I_rule; } |
| 48774 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48775 | virtual int ideal_Opcode() const { return Op_PopCountVI; } |
| 48776 | virtual uint oper_input_base() const { return 1; } |
| 48777 | public: |
| 48778 | vpopcount8INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 48779 | virtual uint size_of() const { return sizeof(vpopcount8INode); } |
| 48780 | // Rematerialize vpopcount8I |
| 48781 | static const Pipeline *pipeline_class(); |
| 48782 | virtual const Pipeline *pipeline() const; |
| 48783 | #ifndef PRODUCT |
| 48784 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48785 | virtual const char *Name() const { return "vpopcount8I";} |
| 48786 | #endif |
| 48787 | }; |
| 48788 | |
| 48789 | class vpopcount16INode : public MachTypeNode { |
| 48790 | private: |
| 48791 | MachOper *_opnd_array[2]; |
| 48792 | public: |
| 48793 | MachOper *opnd_array(uint operand_index) const { |
| 48794 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48795 | return _opnd_array[operand_index]; |
| 48796 | } |
| 48797 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48798 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48799 | _opnd_array[operand_index] = operand; |
| 48800 | } |
| 48801 | private: |
| 48802 | virtual const RegMask &out_RegMask() const; |
| 48803 | virtual uint rule() const { return vpopcount16I_rule; } |
| 48804 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48805 | virtual int ideal_Opcode() const { return Op_PopCountVI; } |
| 48806 | virtual uint oper_input_base() const { return 1; } |
| 48807 | public: |
| 48808 | vpopcount16INode() { _num_opnds = 2; _opnds = _opnd_array; } |
| 48809 | virtual uint size_of() const { return sizeof(vpopcount16INode); } |
| 48810 | // Rematerialize vpopcount16I |
| 48811 | static const Pipeline *pipeline_class(); |
| 48812 | virtual const Pipeline *pipeline() const; |
| 48813 | #ifndef PRODUCT |
| 48814 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48815 | virtual const char *Name() const { return "vpopcount16I";} |
| 48816 | #endif |
| 48817 | }; |
| 48818 | |
| 48819 | class compareAndSwapP_shenandoahNode : public MachNode { |
| 48820 | private: |
| 48821 | MachOper *_opnd_array[6]; |
| 48822 | public: |
| 48823 | MachOper *opnd_array(uint operand_index) const { |
| 48824 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48825 | return _opnd_array[operand_index]; |
| 48826 | } |
| 48827 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48828 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48829 | _opnd_array[operand_index] = operand; |
| 48830 | } |
| 48831 | private: |
| 48832 | virtual const RegMask &out_RegMask() const; |
| 48833 | virtual uint rule() const { return compareAndSwapP_shenandoah_rule; } |
| 48834 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48835 | virtual int ideal_Opcode() const { return Op_ShenandoahCompareAndSwapP; } |
| 48836 | virtual int reloc() const; |
| 48837 | virtual uint oper_input_base() const { return 2; } |
| 48838 | public: |
| 48839 | compareAndSwapP_shenandoahNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48840 | virtual uint size_of() const { return sizeof(compareAndSwapP_shenandoahNode); } |
| 48841 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 48842 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 48843 | static const Pipeline *pipeline_class(); |
| 48844 | virtual const Pipeline *pipeline() const; |
| 48845 | virtual const MachOper *memory_operand() const; |
| 48846 | #ifndef PRODUCT |
| 48847 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48848 | virtual const char *Name() const { return "compareAndSwapP_shenandoah";} |
| 48849 | #endif |
| 48850 | }; |
| 48851 | |
| 48852 | class compareAndSwapP_shenandoah_0Node : public MachNode { |
| 48853 | private: |
| 48854 | MachOper *_opnd_array[6]; |
| 48855 | public: |
| 48856 | MachOper *opnd_array(uint operand_index) const { |
| 48857 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48858 | return _opnd_array[operand_index]; |
| 48859 | } |
| 48860 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48861 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48862 | _opnd_array[operand_index] = operand; |
| 48863 | } |
| 48864 | private: |
| 48865 | virtual const RegMask &out_RegMask() const; |
| 48866 | virtual uint rule() const { return compareAndSwapP_shenandoah_0_rule; } |
| 48867 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48868 | virtual int ideal_Opcode() const { return Op_ShenandoahWeakCompareAndSwapP; } |
| 48869 | virtual int reloc() const; |
| 48870 | virtual uint oper_input_base() const { return 2; } |
| 48871 | public: |
| 48872 | compareAndSwapP_shenandoah_0Node() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48873 | virtual uint size_of() const { return sizeof(compareAndSwapP_shenandoah_0Node); } |
| 48874 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 48875 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 48876 | static const Pipeline *pipeline_class(); |
| 48877 | virtual const Pipeline *pipeline() const; |
| 48878 | virtual const MachOper *memory_operand() const; |
| 48879 | #ifndef PRODUCT |
| 48880 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48881 | virtual const char *Name() const { return "compareAndSwapP_shenandoah_0";} |
| 48882 | #endif |
| 48883 | }; |
| 48884 | |
| 48885 | class compareAndSwapN_shenandoahNode : public MachNode { |
| 48886 | private: |
| 48887 | MachOper *_opnd_array[6]; |
| 48888 | public: |
| 48889 | MachOper *opnd_array(uint operand_index) const { |
| 48890 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48891 | return _opnd_array[operand_index]; |
| 48892 | } |
| 48893 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48894 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48895 | _opnd_array[operand_index] = operand; |
| 48896 | } |
| 48897 | private: |
| 48898 | virtual const RegMask &out_RegMask() const; |
| 48899 | virtual uint rule() const { return compareAndSwapN_shenandoah_rule; } |
| 48900 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48901 | virtual int ideal_Opcode() const { return Op_ShenandoahCompareAndSwapN; } |
| 48902 | virtual int reloc() const; |
| 48903 | virtual uint oper_input_base() const { return 2; } |
| 48904 | public: |
| 48905 | compareAndSwapN_shenandoahNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48906 | virtual uint size_of() const { return sizeof(compareAndSwapN_shenandoahNode); } |
| 48907 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 48908 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 48909 | static const Pipeline *pipeline_class(); |
| 48910 | virtual const Pipeline *pipeline() const; |
| 48911 | virtual const MachOper *memory_operand() const; |
| 48912 | #ifndef PRODUCT |
| 48913 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48914 | virtual const char *Name() const { return "compareAndSwapN_shenandoah";} |
| 48915 | #endif |
| 48916 | }; |
| 48917 | |
| 48918 | class compareAndSwapN_shenandoah_0Node : public MachNode { |
| 48919 | private: |
| 48920 | MachOper *_opnd_array[6]; |
| 48921 | public: |
| 48922 | MachOper *opnd_array(uint operand_index) const { |
| 48923 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48924 | return _opnd_array[operand_index]; |
| 48925 | } |
| 48926 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48927 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48928 | _opnd_array[operand_index] = operand; |
| 48929 | } |
| 48930 | private: |
| 48931 | virtual const RegMask &out_RegMask() const; |
| 48932 | virtual uint rule() const { return compareAndSwapN_shenandoah_0_rule; } |
| 48933 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48934 | virtual int ideal_Opcode() const { return Op_ShenandoahWeakCompareAndSwapN; } |
| 48935 | virtual int reloc() const; |
| 48936 | virtual uint oper_input_base() const { return 2; } |
| 48937 | public: |
| 48938 | compareAndSwapN_shenandoah_0Node() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48939 | virtual uint size_of() const { return sizeof(compareAndSwapN_shenandoah_0Node); } |
| 48940 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 48941 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 48942 | static const Pipeline *pipeline_class(); |
| 48943 | virtual const Pipeline *pipeline() const; |
| 48944 | virtual const MachOper *memory_operand() const; |
| 48945 | #ifndef PRODUCT |
| 48946 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48947 | virtual const char *Name() const { return "compareAndSwapN_shenandoah_0";} |
| 48948 | #endif |
| 48949 | }; |
| 48950 | |
| 48951 | class compareAndExchangeN_shenandoahNode : public MachTypeNode { |
| 48952 | private: |
| 48953 | MachOper *_opnd_array[6]; |
| 48954 | public: |
| 48955 | MachOper *opnd_array(uint operand_index) const { |
| 48956 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48957 | return _opnd_array[operand_index]; |
| 48958 | } |
| 48959 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48960 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48961 | _opnd_array[operand_index] = operand; |
| 48962 | } |
| 48963 | private: |
| 48964 | virtual const RegMask &out_RegMask() const; |
| 48965 | virtual uint rule() const { return compareAndExchangeN_shenandoah_rule; } |
| 48966 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 48967 | virtual int ideal_Opcode() const { return Op_ShenandoahCompareAndExchangeN; } |
| 48968 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 48969 | virtual int reloc() const; |
| 48970 | virtual uint oper_input_base() const { return 2; } |
| 48971 | public: |
| 48972 | compareAndExchangeN_shenandoahNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 48973 | virtual uint size_of() const { return sizeof(compareAndExchangeN_shenandoahNode); } |
| 48974 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 48975 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 48976 | static const Pipeline *pipeline_class(); |
| 48977 | virtual const Pipeline *pipeline() const; |
| 48978 | virtual const MachOper *memory_operand() const; |
| 48979 | #ifndef PRODUCT |
| 48980 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 48981 | virtual const char *Name() const { return "compareAndExchangeN_shenandoah";} |
| 48982 | #endif |
| 48983 | }; |
| 48984 | |
| 48985 | class compareAndExchangeP_shenandoahNode : public MachTypeNode { |
| 48986 | private: |
| 48987 | MachOper *_opnd_array[6]; |
| 48988 | public: |
| 48989 | MachOper *opnd_array(uint operand_index) const { |
| 48990 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48991 | return _opnd_array[operand_index]; |
| 48992 | } |
| 48993 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 48994 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 48995 | _opnd_array[operand_index] = operand; |
| 48996 | } |
| 48997 | private: |
| 48998 | virtual const RegMask &out_RegMask() const; |
| 48999 | virtual uint rule() const { return compareAndExchangeP_shenandoah_rule; } |
| 49000 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49001 | virtual int ideal_Opcode() const { return Op_ShenandoahCompareAndExchangeP; } |
| 49002 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49003 | virtual int reloc() const; |
| 49004 | virtual uint oper_input_base() const { return 2; } |
| 49005 | public: |
| 49006 | compareAndExchangeP_shenandoahNode() { _num_opnds = 6; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49007 | virtual uint size_of() const { return sizeof(compareAndExchangeP_shenandoahNode); } |
| 49008 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49009 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49010 | static const Pipeline *pipeline_class(); |
| 49011 | virtual const Pipeline *pipeline() const; |
| 49012 | virtual const MachOper *memory_operand() const; |
| 49013 | #ifndef PRODUCT |
| 49014 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49015 | virtual const char *Name() const { return "compareAndExchangeP_shenandoah";} |
| 49016 | #endif |
| 49017 | }; |
| 49018 | |
| 49019 | class zLoadBarrierSlowRegXmmAndYmmNode : public MachTypeNode { |
| 49020 | private: |
| 49021 | MachOper *_opnd_array[3]; |
| 49022 | public: |
| 49023 | MachOper *opnd_array(uint operand_index) const { |
| 49024 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49025 | return _opnd_array[operand_index]; |
| 49026 | } |
| 49027 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49028 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49029 | _opnd_array[operand_index] = operand; |
| 49030 | } |
| 49031 | private: |
| 49032 | virtual const RegMask &out_RegMask() const; |
| 49033 | virtual uint rule() const { return zLoadBarrierSlowRegXmmAndYmm_rule; } |
| 49034 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49035 | virtual int ideal_Opcode() const { return Op_LoadBarrierSlowReg; } |
| 49036 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49037 | virtual int reloc() const; |
| 49038 | virtual uint oper_input_base() const { return 1; } |
| 49039 | public: |
| 49040 | zLoadBarrierSlowRegXmmAndYmmNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49041 | virtual uint size_of() const { return sizeof(zLoadBarrierSlowRegXmmAndYmmNode); } |
| 49042 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49043 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49044 | static const Pipeline *pipeline_class(); |
| 49045 | virtual const Pipeline *pipeline() const; |
| 49046 | virtual const MachOper *memory_operand() const; |
| 49047 | #ifndef PRODUCT |
| 49048 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49049 | virtual const char *Name() const { return "zLoadBarrierSlowRegXmmAndYmm";} |
| 49050 | #endif |
| 49051 | }; |
| 49052 | |
| 49053 | class zLoadBarrierSlowRegZmmNode : public MachTypeNode { |
| 49054 | private: |
| 49055 | MachOper *_opnd_array[3]; |
| 49056 | public: |
| 49057 | MachOper *opnd_array(uint operand_index) const { |
| 49058 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49059 | return _opnd_array[operand_index]; |
| 49060 | } |
| 49061 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49062 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49063 | _opnd_array[operand_index] = operand; |
| 49064 | } |
| 49065 | private: |
| 49066 | virtual const RegMask &out_RegMask() const; |
| 49067 | virtual uint rule() const { return zLoadBarrierSlowRegZmm_rule; } |
| 49068 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49069 | virtual int ideal_Opcode() const { return Op_LoadBarrierSlowReg; } |
| 49070 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49071 | virtual int reloc() const; |
| 49072 | virtual uint oper_input_base() const { return 1; } |
| 49073 | public: |
| 49074 | zLoadBarrierSlowRegZmmNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49075 | virtual uint size_of() const { return sizeof(zLoadBarrierSlowRegZmmNode); } |
| 49076 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49077 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49078 | static const Pipeline *pipeline_class(); |
| 49079 | virtual const Pipeline *pipeline() const; |
| 49080 | virtual const MachOper *memory_operand() const; |
| 49081 | #ifndef PRODUCT |
| 49082 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49083 | virtual const char *Name() const { return "zLoadBarrierSlowRegZmm";} |
| 49084 | #endif |
| 49085 | }; |
| 49086 | |
| 49087 | class zLoadBarrierWeakSlowRegXmmAndYmmNode : public MachTypeNode { |
| 49088 | private: |
| 49089 | MachOper *_opnd_array[3]; |
| 49090 | public: |
| 49091 | MachOper *opnd_array(uint operand_index) const { |
| 49092 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49093 | return _opnd_array[operand_index]; |
| 49094 | } |
| 49095 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49096 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49097 | _opnd_array[operand_index] = operand; |
| 49098 | } |
| 49099 | private: |
| 49100 | virtual const RegMask &out_RegMask() const; |
| 49101 | virtual uint rule() const { return zLoadBarrierWeakSlowRegXmmAndYmm_rule; } |
| 49102 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49103 | virtual int ideal_Opcode() const { return Op_LoadBarrierSlowReg; } |
| 49104 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49105 | virtual int reloc() const; |
| 49106 | virtual uint oper_input_base() const { return 1; } |
| 49107 | public: |
| 49108 | zLoadBarrierWeakSlowRegXmmAndYmmNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49109 | virtual uint size_of() const { return sizeof(zLoadBarrierWeakSlowRegXmmAndYmmNode); } |
| 49110 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49111 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49112 | static const Pipeline *pipeline_class(); |
| 49113 | virtual const Pipeline *pipeline() const; |
| 49114 | virtual const MachOper *memory_operand() const; |
| 49115 | #ifndef PRODUCT |
| 49116 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49117 | virtual const char *Name() const { return "zLoadBarrierWeakSlowRegXmmAndYmm";} |
| 49118 | #endif |
| 49119 | }; |
| 49120 | |
| 49121 | class zLoadBarrierWeakSlowRegZmmNode : public MachTypeNode { |
| 49122 | private: |
| 49123 | MachOper *_opnd_array[3]; |
| 49124 | public: |
| 49125 | MachOper *opnd_array(uint operand_index) const { |
| 49126 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49127 | return _opnd_array[operand_index]; |
| 49128 | } |
| 49129 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49130 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49131 | _opnd_array[operand_index] = operand; |
| 49132 | } |
| 49133 | private: |
| 49134 | virtual const RegMask &out_RegMask() const; |
| 49135 | virtual uint rule() const { return zLoadBarrierWeakSlowRegZmm_rule; } |
| 49136 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49137 | virtual int ideal_Opcode() const { return Op_LoadBarrierSlowReg; } |
| 49138 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49139 | virtual int reloc() const; |
| 49140 | virtual uint oper_input_base() const { return 1; } |
| 49141 | public: |
| 49142 | zLoadBarrierWeakSlowRegZmmNode() { _num_opnds = 3; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49143 | virtual uint size_of() const { return sizeof(zLoadBarrierWeakSlowRegZmmNode); } |
| 49144 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49145 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49146 | static const Pipeline *pipeline_class(); |
| 49147 | virtual const Pipeline *pipeline() const; |
| 49148 | virtual const MachOper *memory_operand() const; |
| 49149 | #ifndef PRODUCT |
| 49150 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49151 | virtual const char *Name() const { return "zLoadBarrierWeakSlowRegZmm";} |
| 49152 | #endif |
| 49153 | }; |
| 49154 | |
| 49155 | class z_compareAndExchangePNode : public MachTypeNode { |
| 49156 | private: |
| 49157 | MachOper *_opnd_array[5]; |
| 49158 | public: |
| 49159 | MachOper *opnd_array(uint operand_index) const { |
| 49160 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49161 | return _opnd_array[operand_index]; |
| 49162 | } |
| 49163 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49164 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49165 | _opnd_array[operand_index] = operand; |
| 49166 | } |
| 49167 | private: |
| 49168 | virtual const RegMask &out_RegMask() const; |
| 49169 | virtual uint rule() const { return z_compareAndExchangeP_rule; } |
| 49170 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49171 | virtual int ideal_Opcode() const { return Op_ZCompareAndExchangeP; } |
| 49172 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges() + opnd_array(2)->num_edges(); } |
| 49173 | virtual int reloc() const; |
| 49174 | virtual uint oper_input_base() const { return 2; } |
| 49175 | public: |
| 49176 | z_compareAndExchangePNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49177 | virtual uint size_of() const { return sizeof(z_compareAndExchangePNode); } |
| 49178 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49179 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49180 | static const Pipeline *pipeline_class(); |
| 49181 | virtual const Pipeline *pipeline() const; |
| 49182 | virtual const MachOper *memory_operand() const; |
| 49183 | #ifndef PRODUCT |
| 49184 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49185 | virtual const char *Name() const { return "z_compareAndExchangeP";} |
| 49186 | #endif |
| 49187 | }; |
| 49188 | |
| 49189 | class z_compareAndSwapPNode : public MachNode { |
| 49190 | private: |
| 49191 | MachOper *_opnd_array[5]; |
| 49192 | public: |
| 49193 | MachOper *opnd_array(uint operand_index) const { |
| 49194 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49195 | return _opnd_array[operand_index]; |
| 49196 | } |
| 49197 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49198 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49199 | _opnd_array[operand_index] = operand; |
| 49200 | } |
| 49201 | private: |
| 49202 | virtual const RegMask &out_RegMask() const; |
| 49203 | virtual uint rule() const { return z_compareAndSwapP_rule; } |
| 49204 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49205 | virtual int ideal_Opcode() const { return Op_ZCompareAndSwapP; } |
| 49206 | virtual int reloc() const; |
| 49207 | virtual uint oper_input_base() const { return 2; } |
| 49208 | public: |
| 49209 | z_compareAndSwapPNode() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49210 | virtual uint size_of() const { return sizeof(z_compareAndSwapPNode); } |
| 49211 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49212 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49213 | static const Pipeline *pipeline_class(); |
| 49214 | virtual const Pipeline *pipeline() const; |
| 49215 | virtual const MachOper *memory_operand() const; |
| 49216 | #ifndef PRODUCT |
| 49217 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49218 | virtual const char *Name() const { return "z_compareAndSwapP";} |
| 49219 | #endif |
| 49220 | }; |
| 49221 | |
| 49222 | class z_compareAndSwapP_0Node : public MachNode { |
| 49223 | private: |
| 49224 | MachOper *_opnd_array[5]; |
| 49225 | public: |
| 49226 | MachOper *opnd_array(uint operand_index) const { |
| 49227 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49228 | return _opnd_array[operand_index]; |
| 49229 | } |
| 49230 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49231 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49232 | _opnd_array[operand_index] = operand; |
| 49233 | } |
| 49234 | private: |
| 49235 | virtual const RegMask &out_RegMask() const; |
| 49236 | virtual uint rule() const { return z_compareAndSwapP_0_rule; } |
| 49237 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49238 | virtual int ideal_Opcode() const { return Op_ZWeakCompareAndSwapP; } |
| 49239 | virtual int reloc() const; |
| 49240 | virtual uint oper_input_base() const { return 2; } |
| 49241 | public: |
| 49242 | z_compareAndSwapP_0Node() { _num_opnds = 5; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49243 | virtual uint size_of() const { return sizeof(z_compareAndSwapP_0Node); } |
| 49244 | virtual MachNode *Expand(State *state, Node_List &proj_list, Node* mem); |
| 49245 | friend MachNode *State::MachNodeGenerator(int opcode); |
| 49246 | static const Pipeline *pipeline_class(); |
| 49247 | virtual const Pipeline *pipeline() const; |
| 49248 | virtual const MachOper *memory_operand() const; |
| 49249 | #ifndef PRODUCT |
| 49250 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49251 | virtual const char *Name() const { return "z_compareAndSwapP_0";} |
| 49252 | #endif |
| 49253 | }; |
| 49254 | |
| 49255 | class z_xchgPNode : public MachTypeNode { |
| 49256 | private: |
| 49257 | MachOper *_opnd_array[4]; |
| 49258 | public: |
| 49259 | MachOper *opnd_array(uint operand_index) const { |
| 49260 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49261 | return _opnd_array[operand_index]; |
| 49262 | } |
| 49263 | void set_opnd_array(uint operand_index, MachOper *operand) { |
| 49264 | assert(operand_index < _num_opnds, "invalid _opnd_array index"); |
| 49265 | _opnd_array[operand_index] = operand; |
| 49266 | } |
| 49267 | private: |
| 49268 | virtual const RegMask &out_RegMask() const; |
| 49269 | virtual uint rule() const { return z_xchgP_rule; } |
| 49270 | virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; |
| 49271 | virtual int ideal_Opcode() const { return Op_ZGetAndSetP; } |
| 49272 | virtual uint two_adr() const { return oper_input_base() + opnd_array(1)->num_edges(); } |
| 49273 | virtual int reloc() const; |
| 49274 | virtual uint oper_input_base() const { return 2; } |
| 49275 | public: |
| 49276 | z_xchgPNode() { _num_opnds = 4; _opnds = _opnd_array; init_flags(Flag_needs_anti_dependence_check); } |
| 49277 | virtual uint size_of() const { return sizeof(z_xchgPNode); } |
| 49278 | static const Pipeline *pipeline_class(); |
| 49279 | virtual const Pipeline *pipeline() const; |
| 49280 | virtual const MachOper *memory_operand() const; |
| 49281 | #ifndef PRODUCT |
| 49282 | virtual void format(PhaseRegAlloc *ra, outputStream *st) const; |
| 49283 | virtual const char *Name() const { return "z_xchgP";} |
| 49284 | #endif |
| 49285 | }; |
| 49286 | |
| 49287 | //HeaderForm |
| 49288 | |
| 49289 | #line 311 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49290 | |
| 49291 | |
| 49292 | extern RegMask _ANY_REG_mask; |
| 49293 | extern RegMask _PTR_REG_mask; |
| 49294 | extern RegMask _PTR_REG_NO_RBP_mask; |
| 49295 | extern RegMask _PTR_NO_RAX_REG_mask; |
| 49296 | extern RegMask _PTR_NO_RAX_RBX_REG_mask; |
| 49297 | extern RegMask _LONG_REG_mask; |
| 49298 | extern RegMask _LONG_NO_RAX_RDX_REG_mask; |
| 49299 | extern RegMask _LONG_NO_RCX_REG_mask; |
| 49300 | extern RegMask _INT_REG_mask; |
| 49301 | extern RegMask _INT_NO_RAX_RDX_REG_mask; |
| 49302 | extern RegMask _INT_NO_RCX_REG_mask; |
| 49303 | |
| 49304 | extern RegMask _STACK_OR_PTR_REG_mask; |
| 49305 | extern RegMask _STACK_OR_LONG_REG_mask; |
| 49306 | extern RegMask _STACK_OR_INT_REG_mask; |
| 49307 | |
| 49308 | inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; } |
| 49309 | inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; } |
| 49310 | inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; } |
| 49311 | |
| 49312 | |
| 49313 | #line 49313 "ad_x86.hpp" |
| 49314 | |
| 49315 | |
| 49316 | //HeaderForm |
| 49317 | |
| 49318 | #line 1239 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49319 | |
| 49320 | // Header information of the source block. |
| 49321 | // Method declarations/definitions which are used outside |
| 49322 | // the ad-scope can conveniently be defined here. |
| 49323 | // |
| 49324 | // To keep related declarations/definitions/uses close together, |
| 49325 | // we switch between source %{ }% and source_hpp %{ }% freely as needed. |
| 49326 | |
| 49327 | class NativeJump; |
| 49328 | |
| 49329 | class CallStubImpl { |
| 49330 | |
| 49331 | //-------------------------------------------------------------- |
| 49332 | //---< Used for optimization in Compile::shorten_branches >--- |
| 49333 | //-------------------------------------------------------------- |
| 49334 | |
| 49335 | public: |
| 49336 | // Size of call trampoline stub. |
| 49337 | static uint size_call_trampoline() { |
| 49338 | return 0; // no call trampolines on this platform |
| 49339 | } |
| 49340 | |
| 49341 | // number of relocations needed by a call trampoline stub |
| 49342 | static uint reloc_call_trampoline() { |
| 49343 | return 0; // no call trampolines on this platform |
| 49344 | } |
| 49345 | }; |
| 49346 | |
| 49347 | class HandlerImpl { |
| 49348 | |
| 49349 | public: |
| 49350 | |
| 49351 | static int emit_exception_handler(CodeBuffer &cbuf); |
| 49352 | static int emit_deopt_handler(CodeBuffer& cbuf); |
| 49353 | |
| 49354 | static uint size_exception_handler() { |
| 49355 | // NativeCall instruction size is the same as NativeJump. |
| 49356 | // exception handler starts out as jump and can be patched to |
| 49357 | // a call be deoptimization. (4932387) |
| 49358 | // Note that this value is also credited (in output.cpp) to |
| 49359 | // the size of the code section. |
| 49360 | return NativeJump::instruction_size; |
| 49361 | } |
| 49362 | |
| 49363 | #ifdef _LP64 |
| 49364 | static uint size_deopt_handler() { |
| 49365 | // three 5 byte instructions plus one move for unreachable address. |
| 49366 | return 15+3; |
| 49367 | } |
| 49368 | #else |
| 49369 | static uint size_deopt_handler() { |
| 49370 | // NativeCall instruction size is the same as NativeJump. |
| 49371 | // exception handler starts out as jump and can be patched to |
| 49372 | // a call be deoptimization. (4932387) |
| 49373 | // Note that this value is also credited (in output.cpp) to |
| 49374 | // the size of the code section. |
| 49375 | return 5 + NativeJump::instruction_size; // pushl(); jmp; |
| 49376 | } |
| 49377 | #endif |
| 49378 | }; |
| 49379 | |
| 49380 | |
| 49381 | #line 49381 "ad_x86.hpp" |
| 49382 | |
| 49383 | |
| 49384 | //HeaderForm |
| 49385 | |
| 49386 | #line 24 "/workspace/jdk13/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad" |
| 49387 | |
| 49388 | #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" |
| 49389 | #include "gc/shenandoah/c2/shenandoahSupport.hpp" |
| 49390 | |
| 49391 | #line 49391 "ad_x86.hpp" |
| 49392 | |
| 49393 | |
| 49394 | //HeaderForm |
| 49395 | |
| 49396 | #line 24 "/workspace/jdk13/src/hotspot/cpu/x86/gc/z/z_x86_64.ad" |
| 49397 | |
| 49398 | |
| 49399 | #include "gc/z/c2/zBarrierSetC2.hpp" |
| 49400 | |
| 49401 | |
| 49402 | #line 49402 "ad_x86.hpp" |
| 49403 | |
| 49404 | |
| 49405 | extern const char register_save_policy[]; |
| 49406 | extern const char c_reg_save_policy[]; |
| 49407 | extern const int register_save_type[]; |
| 49408 | |
| 49409 | extern const int reduceOp[]; |
| 49410 | extern const int leftOp[]; |
| 49411 | extern const int rightOp[]; |
| 49412 | extern const char *ruleName[]; |
| 49413 | extern const bool swallowed[]; |
| 49414 | // Mapping from machine-independent opcode to boolean |
| 49415 | // Flag cases where machine needs cloned values or instructions |
| 49416 | extern const char must_clone[]; |
| 49417 | |
| 49418 | |
| 49419 | // Enumeration of register class names |
| 49420 | enum machRegisterClass { |
| 49421 | NO_REG, |
| 49422 | ALL_REG, |
| 49423 | ALL_INT_REG, |
| 49424 | ANY_REG, |
| 49425 | PTR_REG, |
| 49426 | PTR_REG_NO_RBP, |
| 49427 | PTR_NO_RAX_REG, |
| 49428 | PTR_NO_RAX_RBX_REG, |
| 49429 | LONG_REG, |
| 49430 | LONG_NO_RAX_RDX_REG, |
| 49431 | LONG_NO_RCX_REG, |
| 49432 | INT_REG, |
| 49433 | INT_NO_RAX_RDX_REG, |
| 49434 | INT_NO_RCX_REG, |
| 49435 | PTR_RAX_REG, |
| 49436 | PTR_RBX_REG, |
| 49437 | PTR_RSI_REG, |
| 49438 | PTR_RDI_REG, |
| 49439 | PTR_RSP_REG, |
| 49440 | PTR_R15_REG, |
| 49441 | LONG_RAX_REG, |
| 49442 | LONG_RCX_REG, |
| 49443 | LONG_RDX_REG, |
| 49444 | INT_RAX_REG, |
| 49445 | INT_RBX_REG, |
| 49446 | INT_RCX_REG, |
| 49447 | INT_RDX_REG, |
| 49448 | INT_RDI_REG, |
| 49449 | INT_FLAGS, |
| 49450 | FLOAT_REG_LEGACY, |
| 49451 | FLOAT_REG_EVEX, |
| 49452 | FLOAT_REG, |
| 49453 | FLOAT_REG_VL, |
| 49454 | DOUBLE_REG_LEGACY, |
| 49455 | DOUBLE_REG_EVEX, |
| 49456 | DOUBLE_REG, |
| 49457 | DOUBLE_REG_VL, |
| 49458 | VECTORS_REG_LEGACY, |
| 49459 | VECTORS_REG_EVEX, |
| 49460 | VECTORS_REG, |
| 49461 | VECTORS_REG_VLBWDQ, |
| 49462 | VECTORD_REG_LEGACY, |
| 49463 | VECTORD_REG_EVEX, |
| 49464 | VECTORD_REG, |
| 49465 | VECTORD_REG_VLBWDQ, |
| 49466 | VECTORX_REG_LEGACY, |
| 49467 | VECTORX_REG_EVEX, |
| 49468 | VECTORX_REG, |
| 49469 | VECTORX_REG_VLBWDQ, |
| 49470 | VECTORY_REG_LEGACY, |
| 49471 | VECTORY_REG_EVEX, |
| 49472 | VECTORY_REG, |
| 49473 | VECTORY_REG_VLBWDQ, |
| 49474 | VECTORZ_REG_EVEX, |
| 49475 | VECTORZ_REG_LEGACY, |
| 49476 | VECTORZ_REG, |
| 49477 | VECTORZ_REG_VL, |
| 49478 | XMM0_REG, |
| 49479 | YMM0_REG, |
| 49480 | ZMM0_REG, |
| 49481 | XMM1_REG, |
| 49482 | YMM1_REG, |
| 49483 | ZMM1_REG, |
| 49484 | XMM2_REG, |
| 49485 | YMM2_REG, |
| 49486 | ZMM2_REG, |
| 49487 | XMM3_REG, |
| 49488 | YMM3_REG, |
| 49489 | ZMM3_REG, |
| 49490 | XMM4_REG, |
| 49491 | YMM4_REG, |
| 49492 | ZMM4_REG, |
| 49493 | XMM5_REG, |
| 49494 | YMM5_REG, |
| 49495 | ZMM5_REG, |
| 49496 | XMM6_REG, |
| 49497 | YMM6_REG, |
| 49498 | ZMM6_REG, |
| 49499 | XMM7_REG, |
| 49500 | YMM7_REG, |
| 49501 | ZMM7_REG, |
| 49502 | XMM8_REG, |
| 49503 | YMM8_REG, |
| 49504 | ZMM8_REG, |
| 49505 | XMM9_REG, |
| 49506 | YMM9_REG, |
| 49507 | ZMM9_REG, |
| 49508 | XMM10_REG, |
| 49509 | YMM10_REG, |
| 49510 | ZMM10_REG, |
| 49511 | XMM11_REG, |
| 49512 | YMM11_REG, |
| 49513 | ZMM11_REG, |
| 49514 | XMM12_REG, |
| 49515 | YMM12_REG, |
| 49516 | ZMM12_REG, |
| 49517 | XMM13_REG, |
| 49518 | YMM13_REG, |
| 49519 | ZMM13_REG, |
| 49520 | XMM14_REG, |
| 49521 | YMM14_REG, |
| 49522 | ZMM14_REG, |
| 49523 | XMM15_REG, |
| 49524 | YMM15_REG, |
| 49525 | ZMM15_REG, |
| 49526 | XMM16_REG, |
| 49527 | YMM16_REG, |
| 49528 | ZMM16_REG, |
| 49529 | XMM17_REG, |
| 49530 | YMM17_REG, |
| 49531 | ZMM17_REG, |
| 49532 | XMM18_REG, |
| 49533 | YMM18_REG, |
| 49534 | ZMM18_REG, |
| 49535 | XMM19_REG, |
| 49536 | YMM19_REG, |
| 49537 | ZMM19_REG, |
| 49538 | XMM20_REG, |
| 49539 | YMM20_REG, |
| 49540 | ZMM20_REG, |
| 49541 | XMM21_REG, |
| 49542 | YMM21_REG, |
| 49543 | ZMM21_REG, |
| 49544 | XMM22_REG, |
| 49545 | YMM22_REG, |
| 49546 | ZMM22_REG, |
| 49547 | XMM23_REG, |
| 49548 | YMM23_REG, |
| 49549 | ZMM23_REG, |
| 49550 | XMM24_REG, |
| 49551 | YMM24_REG, |
| 49552 | ZMM24_REG, |
| 49553 | XMM25_REG, |
| 49554 | YMM25_REG, |
| 49555 | ZMM25_REG, |
| 49556 | XMM26_REG, |
| 49557 | YMM26_REG, |
| 49558 | ZMM26_REG, |
| 49559 | XMM27_REG, |
| 49560 | YMM27_REG, |
| 49561 | ZMM27_REG, |
| 49562 | XMM28_REG, |
| 49563 | YMM28_REG, |
| 49564 | ZMM28_REG, |
| 49565 | XMM29_REG, |
| 49566 | YMM29_REG, |
| 49567 | ZMM29_REG, |
| 49568 | XMM30_REG, |
| 49569 | YMM30_REG, |
| 49570 | ZMM30_REG, |
| 49571 | XMM31_REG, |
| 49572 | YMM31_REG, |
| 49573 | ZMM31_REG, |
| 49574 | STACK_SLOTS, |
| 49575 | _last_Mach_Reg_Class |
| 49576 | }; |
| 49577 | |
| 49578 | // Register masks, one for each register class. |
| 49579 | extern const RegMask _NO_REG_mask; |
| 49580 | inline const RegMask &NO_REG_mask() { return _NO_REG_mask; } |
| 49581 | extern const RegMask _ALL_REG_mask; |
| 49582 | inline const RegMask &ALL_REG_mask() { return _ALL_REG_mask; } |
| 49583 | extern const RegMask _ALL_INT_REG_mask; |
| 49584 | inline const RegMask &ALL_INT_REG_mask() { return _ALL_INT_REG_mask; } |
| 49585 | inline const RegMask &ANY_REG_mask() { |
| 49586 | #line 207 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49587 | |
| 49588 | return _ANY_REG_mask; |
| 49589 | |
| 49590 | #line 49590 "ad_x86.hpp" |
| 49591 | } |
| 49592 | inline const RegMask &PTR_REG_mask() { |
| 49593 | #line 212 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49594 | |
| 49595 | return _PTR_REG_mask; |
| 49596 | |
| 49597 | #line 49597 "ad_x86.hpp" |
| 49598 | } |
| 49599 | inline const RegMask &PTR_REG_NO_RBP_mask() { |
| 49600 | #line 217 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49601 | |
| 49602 | return _PTR_REG_NO_RBP_mask; |
| 49603 | |
| 49604 | #line 49604 "ad_x86.hpp" |
| 49605 | } |
| 49606 | inline const RegMask &PTR_NO_RAX_REG_mask() { |
| 49607 | #line 222 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49608 | |
| 49609 | return _PTR_NO_RAX_REG_mask; |
| 49610 | |
| 49611 | #line 49611 "ad_x86.hpp" |
| 49612 | } |
| 49613 | inline const RegMask &PTR_NO_RAX_RBX_REG_mask() { |
| 49614 | #line 227 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49615 | |
| 49616 | return _PTR_NO_RAX_RBX_REG_mask; |
| 49617 | |
| 49618 | #line 49618 "ad_x86.hpp" |
| 49619 | } |
| 49620 | inline const RegMask &LONG_REG_mask() { |
| 49621 | #line 232 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49622 | |
| 49623 | return _LONG_REG_mask; |
| 49624 | |
| 49625 | #line 49625 "ad_x86.hpp" |
| 49626 | } |
| 49627 | inline const RegMask &LONG_NO_RAX_RDX_REG_mask() { |
| 49628 | #line 237 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49629 | |
| 49630 | return _LONG_NO_RAX_RDX_REG_mask; |
| 49631 | |
| 49632 | #line 49632 "ad_x86.hpp" |
| 49633 | } |
| 49634 | inline const RegMask &LONG_NO_RCX_REG_mask() { |
| 49635 | #line 242 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49636 | |
| 49637 | return _LONG_NO_RCX_REG_mask; |
| 49638 | |
| 49639 | #line 49639 "ad_x86.hpp" |
| 49640 | } |
| 49641 | inline const RegMask &INT_REG_mask() { |
| 49642 | #line 247 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49643 | |
| 49644 | return _INT_REG_mask; |
| 49645 | |
| 49646 | #line 49646 "ad_x86.hpp" |
| 49647 | } |
| 49648 | inline const RegMask &INT_NO_RAX_RDX_REG_mask() { |
| 49649 | #line 252 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49650 | |
| 49651 | return _INT_NO_RAX_RDX_REG_mask; |
| 49652 | |
| 49653 | #line 49653 "ad_x86.hpp" |
| 49654 | } |
| 49655 | inline const RegMask &INT_NO_RCX_REG_mask() { |
| 49656 | #line 257 "/workspace/jdk13/src/hotspot/cpu/x86/x86_64.ad" |
| 49657 | |
| 49658 | return _INT_NO_RCX_REG_mask; |
| 49659 | |
| 49660 | #line 49660 "ad_x86.hpp" |
| 49661 | } |
| 49662 | extern const RegMask _PTR_RAX_REG_mask; |
| 49663 | inline const RegMask &PTR_RAX_REG_mask() { return _PTR_RAX_REG_mask; } |
| 49664 | extern const RegMask _PTR_RBX_REG_mask; |
| 49665 | inline const RegMask &PTR_RBX_REG_mask() { return _PTR_RBX_REG_mask; } |
| 49666 | extern const RegMask _PTR_RSI_REG_mask; |
| 49667 | inline const RegMask &PTR_RSI_REG_mask() { return _PTR_RSI_REG_mask; } |
| 49668 | extern const RegMask _PTR_RDI_REG_mask; |
| 49669 | inline const RegMask &PTR_RDI_REG_mask() { return _PTR_RDI_REG_mask; } |
| 49670 | extern const RegMask _PTR_RSP_REG_mask; |
| 49671 | inline const RegMask &PTR_RSP_REG_mask() { return _PTR_RSP_REG_mask; } |
| 49672 | extern const RegMask _PTR_R15_REG_mask; |
| 49673 | inline const RegMask &PTR_R15_REG_mask() { return _PTR_R15_REG_mask; } |
| 49674 | extern const RegMask _LONG_RAX_REG_mask; |
| 49675 | inline const RegMask &LONG_RAX_REG_mask() { return _LONG_RAX_REG_mask; } |
| 49676 | extern const RegMask _LONG_RCX_REG_mask; |
| 49677 | inline const RegMask &LONG_RCX_REG_mask() { return _LONG_RCX_REG_mask; } |
| 49678 | extern const RegMask _LONG_RDX_REG_mask; |
| 49679 | inline const RegMask &LONG_RDX_REG_mask() { return _LONG_RDX_REG_mask; } |
| 49680 | extern const RegMask _INT_RAX_REG_mask; |
| 49681 | inline const RegMask &INT_RAX_REG_mask() { return _INT_RAX_REG_mask; } |
| 49682 | extern const RegMask _INT_RBX_REG_mask; |
| 49683 | inline const RegMask &INT_RBX_REG_mask() { return _INT_RBX_REG_mask; } |
| 49684 | extern const RegMask _INT_RCX_REG_mask; |
| 49685 | inline const RegMask &INT_RCX_REG_mask() { return _INT_RCX_REG_mask; } |
| 49686 | extern const RegMask _INT_RDX_REG_mask; |
| 49687 | inline const RegMask &INT_RDX_REG_mask() { return _INT_RDX_REG_mask; } |
| 49688 | extern const RegMask _INT_RDI_REG_mask; |
| 49689 | inline const RegMask &INT_RDI_REG_mask() { return _INT_RDI_REG_mask; } |
| 49690 | extern const RegMask _INT_FLAGS_mask; |
| 49691 | inline const RegMask &INT_FLAGS_mask() { return _INT_FLAGS_mask; } |
| 49692 | extern const RegMask _FLOAT_REG_LEGACY_mask; |
| 49693 | inline const RegMask &FLOAT_REG_LEGACY_mask() { return _FLOAT_REG_LEGACY_mask; } |
| 49694 | extern const RegMask _STACK_OR_FLOAT_REG_LEGACY_mask; |
| 49695 | inline const RegMask &STACK_OR_FLOAT_REG_LEGACY_mask() { return _STACK_OR_FLOAT_REG_LEGACY_mask; } |
| 49696 | extern const RegMask _FLOAT_REG_EVEX_mask; |
| 49697 | inline const RegMask &FLOAT_REG_EVEX_mask() { return _FLOAT_REG_EVEX_mask; } |
| 49698 | extern const RegMask _STACK_OR_FLOAT_REG_EVEX_mask; |
| 49699 | inline const RegMask &STACK_OR_FLOAT_REG_EVEX_mask() { return _STACK_OR_FLOAT_REG_EVEX_mask; } |
| 49700 | inline const RegMask &FLOAT_REG_mask() { return ( |
| 49701 | #line 731 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49702 | VM_Version::supports_evex() |
| 49703 | #line 49703 "ad_x86.hpp" |
| 49704 | ) ? FLOAT_REG_EVEX_mask() : FLOAT_REG_LEGACY_mask(); } |
| 49705 | inline const RegMask &STACK_OR_FLOAT_REG_mask() { return ( |
| 49706 | #line 731 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49707 | VM_Version::supports_evex() |
| 49708 | #line 49708 "ad_x86.hpp" |
| 49709 | ) ? STACK_OR_FLOAT_REG_EVEX_mask() : STACK_OR_FLOAT_REG_LEGACY_mask(); } |
| 49710 | inline const RegMask &FLOAT_REG_VL_mask() { return ( |
| 49711 | #line 732 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49712 | VM_Version::supports_evex() && VM_Version::supports_avx512vl() |
| 49713 | #line 49713 "ad_x86.hpp" |
| 49714 | ) ? FLOAT_REG_EVEX_mask() : FLOAT_REG_LEGACY_mask(); } |
| 49715 | inline const RegMask &STACK_OR_FLOAT_REG_VL_mask() { return ( |
| 49716 | #line 732 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49717 | VM_Version::supports_evex() && VM_Version::supports_avx512vl() |
| 49718 | #line 49718 "ad_x86.hpp" |
| 49719 | ) ? STACK_OR_FLOAT_REG_EVEX_mask() : STACK_OR_FLOAT_REG_LEGACY_mask(); } |
| 49720 | extern const RegMask _DOUBLE_REG_LEGACY_mask; |
| 49721 | inline const RegMask &DOUBLE_REG_LEGACY_mask() { return _DOUBLE_REG_LEGACY_mask; } |
| 49722 | extern const RegMask _STACK_OR_DOUBLE_REG_LEGACY_mask; |
| 49723 | inline const RegMask &STACK_OR_DOUBLE_REG_LEGACY_mask() { return _STACK_OR_DOUBLE_REG_LEGACY_mask; } |
| 49724 | extern const RegMask _DOUBLE_REG_EVEX_mask; |
| 49725 | inline const RegMask &DOUBLE_REG_EVEX_mask() { return _DOUBLE_REG_EVEX_mask; } |
| 49726 | extern const RegMask _STACK_OR_DOUBLE_REG_EVEX_mask; |
| 49727 | inline const RegMask &STACK_OR_DOUBLE_REG_EVEX_mask() { return _STACK_OR_DOUBLE_REG_EVEX_mask; } |
| 49728 | inline const RegMask &DOUBLE_REG_mask() { return ( |
| 49729 | #line 792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49730 | VM_Version::supports_evex() |
| 49731 | #line 49731 "ad_x86.hpp" |
| 49732 | ) ? DOUBLE_REG_EVEX_mask() : DOUBLE_REG_LEGACY_mask(); } |
| 49733 | inline const RegMask &STACK_OR_DOUBLE_REG_mask() { return ( |
| 49734 | #line 792 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49735 | VM_Version::supports_evex() |
| 49736 | #line 49736 "ad_x86.hpp" |
| 49737 | ) ? STACK_OR_DOUBLE_REG_EVEX_mask() : STACK_OR_DOUBLE_REG_LEGACY_mask(); } |
| 49738 | inline const RegMask &DOUBLE_REG_VL_mask() { return ( |
| 49739 | #line 793 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49740 | VM_Version::supports_evex() && VM_Version::supports_avx512vl() |
| 49741 | #line 49741 "ad_x86.hpp" |
| 49742 | ) ? DOUBLE_REG_EVEX_mask() : DOUBLE_REG_LEGACY_mask(); } |
| 49743 | inline const RegMask &STACK_OR_DOUBLE_REG_VL_mask() { return ( |
| 49744 | #line 793 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49745 | VM_Version::supports_evex() && VM_Version::supports_avx512vl() |
| 49746 | #line 49746 "ad_x86.hpp" |
| 49747 | ) ? STACK_OR_DOUBLE_REG_EVEX_mask() : STACK_OR_DOUBLE_REG_LEGACY_mask(); } |
| 49748 | extern const RegMask _VECTORS_REG_LEGACY_mask; |
| 49749 | inline const RegMask &VECTORS_REG_LEGACY_mask() { return _VECTORS_REG_LEGACY_mask; } |
| 49750 | extern const RegMask _VECTORS_REG_EVEX_mask; |
| 49751 | inline const RegMask &VECTORS_REG_EVEX_mask() { return _VECTORS_REG_EVEX_mask; } |
| 49752 | inline const RegMask &VECTORS_REG_mask() { return ( |
| 49753 | #line 853 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49754 | VM_Version::supports_evex() |
| 49755 | #line 49755 "ad_x86.hpp" |
| 49756 | ) ? VECTORS_REG_EVEX_mask() : VECTORS_REG_LEGACY_mask(); } |
| 49757 | inline const RegMask &VECTORS_REG_VLBWDQ_mask() { return ( |
| 49758 | #line 854 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49759 | VM_Version::supports_avx512vlbwdq() |
| 49760 | #line 49760 "ad_x86.hpp" |
| 49761 | ) ? VECTORS_REG_EVEX_mask() : VECTORS_REG_LEGACY_mask(); } |
| 49762 | extern const RegMask _VECTORD_REG_LEGACY_mask; |
| 49763 | inline const RegMask &VECTORD_REG_LEGACY_mask() { return _VECTORD_REG_LEGACY_mask; } |
| 49764 | extern const RegMask _VECTORD_REG_EVEX_mask; |
| 49765 | inline const RegMask &VECTORD_REG_EVEX_mask() { return _VECTORD_REG_EVEX_mask; } |
| 49766 | inline const RegMask &VECTORD_REG_mask() { return ( |
| 49767 | #line 914 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49768 | VM_Version::supports_evex() |
| 49769 | #line 49769 "ad_x86.hpp" |
| 49770 | ) ? VECTORD_REG_EVEX_mask() : VECTORD_REG_LEGACY_mask(); } |
| 49771 | inline const RegMask &VECTORD_REG_VLBWDQ_mask() { return ( |
| 49772 | #line 915 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49773 | VM_Version::supports_avx512vlbwdq() |
| 49774 | #line 49774 "ad_x86.hpp" |
| 49775 | ) ? VECTORD_REG_EVEX_mask() : VECTORD_REG_LEGACY_mask(); } |
| 49776 | extern const RegMask _VECTORX_REG_LEGACY_mask; |
| 49777 | inline const RegMask &VECTORX_REG_LEGACY_mask() { return _VECTORX_REG_LEGACY_mask; } |
| 49778 | extern const RegMask _VECTORX_REG_EVEX_mask; |
| 49779 | inline const RegMask &VECTORX_REG_EVEX_mask() { return _VECTORX_REG_EVEX_mask; } |
| 49780 | inline const RegMask &VECTORX_REG_mask() { return ( |
| 49781 | #line 975 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49782 | VM_Version::supports_evex() |
| 49783 | #line 49783 "ad_x86.hpp" |
| 49784 | ) ? VECTORX_REG_EVEX_mask() : VECTORX_REG_LEGACY_mask(); } |
| 49785 | inline const RegMask &VECTORX_REG_VLBWDQ_mask() { return ( |
| 49786 | #line 976 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49787 | VM_Version::supports_avx512vlbwdq() |
| 49788 | #line 49788 "ad_x86.hpp" |
| 49789 | ) ? VECTORX_REG_EVEX_mask() : VECTORX_REG_LEGACY_mask(); } |
| 49790 | extern const RegMask _VECTORY_REG_LEGACY_mask; |
| 49791 | inline const RegMask &VECTORY_REG_LEGACY_mask() { return _VECTORY_REG_LEGACY_mask; } |
| 49792 | extern const RegMask _VECTORY_REG_EVEX_mask; |
| 49793 | inline const RegMask &VECTORY_REG_EVEX_mask() { return _VECTORY_REG_EVEX_mask; } |
| 49794 | inline const RegMask &VECTORY_REG_mask() { return ( |
| 49795 | #line 1036 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49796 | VM_Version::supports_evex() |
| 49797 | #line 49797 "ad_x86.hpp" |
| 49798 | ) ? VECTORY_REG_EVEX_mask() : VECTORY_REG_LEGACY_mask(); } |
| 49799 | inline const RegMask &VECTORY_REG_VLBWDQ_mask() { return ( |
| 49800 | #line 1037 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49801 | VM_Version::supports_avx512vlbwdq() |
| 49802 | #line 49802 "ad_x86.hpp" |
| 49803 | ) ? VECTORY_REG_EVEX_mask() : VECTORY_REG_LEGACY_mask(); } |
| 49804 | extern const RegMask _VECTORZ_REG_EVEX_mask; |
| 49805 | inline const RegMask &VECTORZ_REG_EVEX_mask() { return _VECTORZ_REG_EVEX_mask; } |
| 49806 | extern const RegMask _VECTORZ_REG_LEGACY_mask; |
| 49807 | inline const RegMask &VECTORZ_REG_LEGACY_mask() { return _VECTORZ_REG_LEGACY_mask; } |
| 49808 | inline const RegMask &VECTORZ_REG_mask() { return ( |
| 49809 | #line 1097 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49810 | VM_Version::supports_evex() |
| 49811 | #line 49811 "ad_x86.hpp" |
| 49812 | ) ? VECTORZ_REG_EVEX_mask() : VECTORZ_REG_LEGACY_mask(); } |
| 49813 | inline const RegMask &VECTORZ_REG_VL_mask() { return ( |
| 49814 | #line 1098 "/workspace/jdk13/src/hotspot/cpu/x86/x86.ad" |
| 49815 | VM_Version::supports_evex() && VM_Version::supports_avx512vl() |
| 49816 | #line 49816 "ad_x86.hpp" |
| 49817 | ) ? VECTORZ_REG_EVEX_mask() : VECTORZ_REG_LEGACY_mask(); } |
| 49818 | extern const RegMask _XMM0_REG_mask; |
| 49819 | inline const RegMask &XMM0_REG_mask() { return _XMM0_REG_mask; } |
| 49820 | extern const RegMask _YMM0_REG_mask; |
| 49821 | inline const RegMask &YMM0_REG_mask() { return _YMM0_REG_mask; } |
| 49822 | extern const RegMask _ZMM0_REG_mask; |
| 49823 | inline const RegMask &ZMM0_REG_mask() { return _ZMM0_REG_mask; } |
| 49824 | extern const RegMask _XMM1_REG_mask; |
| 49825 | inline const RegMask &XMM1_REG_mask() { return _XMM1_REG_mask; } |
| 49826 | extern const RegMask _YMM1_REG_mask; |
| 49827 | inline const RegMask &YMM1_REG_mask() { return _YMM1_REG_mask; } |
| 49828 | extern const RegMask _ZMM1_REG_mask; |
| 49829 | inline const RegMask &ZMM1_REG_mask() { return _ZMM1_REG_mask; } |
| 49830 | extern const RegMask _XMM2_REG_mask; |
| 49831 | inline const RegMask &XMM2_REG_mask() { return _XMM2_REG_mask; } |
| 49832 | extern const RegMask _YMM2_REG_mask; |
| 49833 | inline const RegMask &YMM2_REG_mask() { return _YMM2_REG_mask; } |
| 49834 | extern const RegMask _ZMM2_REG_mask; |
| 49835 | inline const RegMask &ZMM2_REG_mask() { return _ZMM2_REG_mask; } |
| 49836 | extern const RegMask _XMM3_REG_mask; |
| 49837 | inline const RegMask &XMM3_REG_mask() { return _XMM3_REG_mask; } |
| 49838 | extern const RegMask _YMM3_REG_mask; |
| 49839 | inline const RegMask &YMM3_REG_mask() { return _YMM3_REG_mask; } |
| 49840 | extern const RegMask _ZMM3_REG_mask; |
| 49841 | inline const RegMask &ZMM3_REG_mask() { return _ZMM3_REG_mask; } |
| 49842 | extern const RegMask _XMM4_REG_mask; |
| 49843 | inline const RegMask &XMM4_REG_mask() { return _XMM4_REG_mask; } |
| 49844 | extern const RegMask _YMM4_REG_mask; |
| 49845 | inline const RegMask &YMM4_REG_mask() { return _YMM4_REG_mask; } |
| 49846 | extern const RegMask _ZMM4_REG_mask; |
| 49847 | inline const RegMask &ZMM4_REG_mask() { return _ZMM4_REG_mask; } |
| 49848 | extern const RegMask _XMM5_REG_mask; |
| 49849 | inline const RegMask &XMM5_REG_mask() { return _XMM5_REG_mask; } |
| 49850 | extern const RegMask _YMM5_REG_mask; |
| 49851 | inline const RegMask &YMM5_REG_mask() { return _YMM5_REG_mask; } |
| 49852 | extern const RegMask _ZMM5_REG_mask; |
| 49853 | inline const RegMask &ZMM5_REG_mask() { return _ZMM5_REG_mask; } |
| 49854 | extern const RegMask _XMM6_REG_mask; |
| 49855 | inline const RegMask &XMM6_REG_mask() { return _XMM6_REG_mask; } |
| 49856 | extern const RegMask _YMM6_REG_mask; |
| 49857 | inline const RegMask &YMM6_REG_mask() { return _YMM6_REG_mask; } |
| 49858 | extern const RegMask _ZMM6_REG_mask; |
| 49859 | inline const RegMask &ZMM6_REG_mask() { return _ZMM6_REG_mask; } |
| 49860 | extern const RegMask _XMM7_REG_mask; |
| 49861 | inline const RegMask &XMM7_REG_mask() { return _XMM7_REG_mask; } |
| 49862 | extern const RegMask _YMM7_REG_mask; |
| 49863 | inline const RegMask &YMM7_REG_mask() { return _YMM7_REG_mask; } |
| 49864 | extern const RegMask _ZMM7_REG_mask; |
| 49865 | inline const RegMask &ZMM7_REG_mask() { return _ZMM7_REG_mask; } |
| 49866 | extern const RegMask _XMM8_REG_mask; |
| 49867 | inline const RegMask &XMM8_REG_mask() { return _XMM8_REG_mask; } |
| 49868 | extern const RegMask _YMM8_REG_mask; |
| 49869 | inline const RegMask &YMM8_REG_mask() { return _YMM8_REG_mask; } |
| 49870 | extern const RegMask _ZMM8_REG_mask; |
| 49871 | inline const RegMask &ZMM8_REG_mask() { return _ZMM8_REG_mask; } |
| 49872 | extern const RegMask _XMM9_REG_mask; |
| 49873 | inline const RegMask &XMM9_REG_mask() { return _XMM9_REG_mask; } |
| 49874 | extern const RegMask _YMM9_REG_mask; |
| 49875 | inline const RegMask &YMM9_REG_mask() { return _YMM9_REG_mask; } |
| 49876 | extern const RegMask _ZMM9_REG_mask; |
| 49877 | inline const RegMask &ZMM9_REG_mask() { return _ZMM9_REG_mask; } |
| 49878 | extern const RegMask _XMM10_REG_mask; |
| 49879 | inline const RegMask &XMM10_REG_mask() { return _XMM10_REG_mask; } |
| 49880 | extern const RegMask _YMM10_REG_mask; |
| 49881 | inline const RegMask &YMM10_REG_mask() { return _YMM10_REG_mask; } |
| 49882 | extern const RegMask _ZMM10_REG_mask; |
| 49883 | inline const RegMask &ZMM10_REG_mask() { return _ZMM10_REG_mask; } |
| 49884 | extern const RegMask _XMM11_REG_mask; |
| 49885 | inline const RegMask &XMM11_REG_mask() { return _XMM11_REG_mask; } |
| 49886 | extern const RegMask _YMM11_REG_mask; |
| 49887 | inline const RegMask &YMM11_REG_mask() { return _YMM11_REG_mask; } |
| 49888 | extern const RegMask _ZMM11_REG_mask; |
| 49889 | inline const RegMask &ZMM11_REG_mask() { return _ZMM11_REG_mask; } |
| 49890 | extern const RegMask _XMM12_REG_mask; |
| 49891 | inline const RegMask &XMM12_REG_mask() { return _XMM12_REG_mask; } |
| 49892 | extern const RegMask _YMM12_REG_mask; |
| 49893 | inline const RegMask &YMM12_REG_mask() { return _YMM12_REG_mask; } |
| 49894 | extern const RegMask _ZMM12_REG_mask; |
| 49895 | inline const RegMask &ZMM12_REG_mask() { return _ZMM12_REG_mask; } |
| 49896 | extern const RegMask _XMM13_REG_mask; |
| 49897 | inline const RegMask &XMM13_REG_mask() { return _XMM13_REG_mask; } |
| 49898 | extern const RegMask _YMM13_REG_mask; |
| 49899 | inline const RegMask &YMM13_REG_mask() { return _YMM13_REG_mask; } |
| 49900 | extern const RegMask _ZMM13_REG_mask; |
| 49901 | inline const RegMask &ZMM13_REG_mask() { return _ZMM13_REG_mask; } |
| 49902 | extern const RegMask _XMM14_REG_mask; |
| 49903 | inline const RegMask &XMM14_REG_mask() { return _XMM14_REG_mask; } |
| 49904 | extern const RegMask _YMM14_REG_mask; |
| 49905 | inline const RegMask &YMM14_REG_mask() { return _YMM14_REG_mask; } |
| 49906 | extern const RegMask _ZMM14_REG_mask; |
| 49907 | inline const RegMask &ZMM14_REG_mask() { return _ZMM14_REG_mask; } |
| 49908 | extern const RegMask _XMM15_REG_mask; |
| 49909 | inline const RegMask &XMM15_REG_mask() { return _XMM15_REG_mask; } |
| 49910 | extern const RegMask _YMM15_REG_mask; |
| 49911 | inline const RegMask &YMM15_REG_mask() { return _YMM15_REG_mask; } |
| 49912 | extern const RegMask _ZMM15_REG_mask; |
| 49913 | inline const RegMask &ZMM15_REG_mask() { return _ZMM15_REG_mask; } |
| 49914 | extern const RegMask _XMM16_REG_mask; |
| 49915 | inline const RegMask &XMM16_REG_mask() { return _XMM16_REG_mask; } |
| 49916 | extern const RegMask _YMM16_REG_mask; |
| 49917 | inline const RegMask &YMM16_REG_mask() { return _YMM16_REG_mask; } |
| 49918 | extern const RegMask _ZMM16_REG_mask; |
| 49919 | inline const RegMask &ZMM16_REG_mask() { return _ZMM16_REG_mask; } |
| 49920 | extern const RegMask _XMM17_REG_mask; |
| 49921 | inline const RegMask &XMM17_REG_mask() { return _XMM17_REG_mask; } |
| 49922 | extern const RegMask _YMM17_REG_mask; |
| 49923 | inline const RegMask &YMM17_REG_mask() { return _YMM17_REG_mask; } |
| 49924 | extern const RegMask _ZMM17_REG_mask; |
| 49925 | inline const RegMask &ZMM17_REG_mask() { return _ZMM17_REG_mask; } |
| 49926 | extern const RegMask _XMM18_REG_mask; |
| 49927 | inline const RegMask &XMM18_REG_mask() { return _XMM18_REG_mask; } |
| 49928 | extern const RegMask _YMM18_REG_mask; |
| 49929 | inline const RegMask &YMM18_REG_mask() { return _YMM18_REG_mask; } |
| 49930 | extern const RegMask _ZMM18_REG_mask; |
| 49931 | inline const RegMask &ZMM18_REG_mask() { return _ZMM18_REG_mask; } |
| 49932 | extern const RegMask _XMM19_REG_mask; |
| 49933 | inline const RegMask &XMM19_REG_mask() { return _XMM19_REG_mask; } |
| 49934 | extern const RegMask _YMM19_REG_mask; |
| 49935 | inline const RegMask &YMM19_REG_mask() { return _YMM19_REG_mask; } |
| 49936 | extern const RegMask _ZMM19_REG_mask; |
| 49937 | inline const RegMask &ZMM19_REG_mask() { return _ZMM19_REG_mask; } |
| 49938 | extern const RegMask _XMM20_REG_mask; |
| 49939 | inline const RegMask &XMM20_REG_mask() { return _XMM20_REG_mask; } |
| 49940 | extern const RegMask _YMM20_REG_mask; |
| 49941 | inline const RegMask &YMM20_REG_mask() { return _YMM20_REG_mask; } |
| 49942 | extern const RegMask _ZMM20_REG_mask; |
| 49943 | inline const RegMask &ZMM20_REG_mask() { return _ZMM20_REG_mask; } |
| 49944 | extern const RegMask _XMM21_REG_mask; |
| 49945 | inline const RegMask &XMM21_REG_mask() { return _XMM21_REG_mask; } |
| 49946 | extern const RegMask _YMM21_REG_mask; |
| 49947 | inline const RegMask &YMM21_REG_mask() { return _YMM21_REG_mask; } |
| 49948 | extern const RegMask _ZMM21_REG_mask; |
| 49949 | inline const RegMask &ZMM21_REG_mask() { return _ZMM21_REG_mask; } |
| 49950 | extern const RegMask _XMM22_REG_mask; |
| 49951 | inline const RegMask &XMM22_REG_mask() { return _XMM22_REG_mask; } |
| 49952 | extern const RegMask _YMM22_REG_mask; |
| 49953 | inline const RegMask &YMM22_REG_mask() { return _YMM22_REG_mask; } |
| 49954 | extern const RegMask _ZMM22_REG_mask; |
| 49955 | inline const RegMask &ZMM22_REG_mask() { return _ZMM22_REG_mask; } |
| 49956 | extern const RegMask _XMM23_REG_mask; |
| 49957 | inline const RegMask &XMM23_REG_mask() { return _XMM23_REG_mask; } |
| 49958 | extern const RegMask _YMM23_REG_mask; |
| 49959 | inline const RegMask &YMM23_REG_mask() { return _YMM23_REG_mask; } |
| 49960 | extern const RegMask _ZMM23_REG_mask; |
| 49961 | inline const RegMask &ZMM23_REG_mask() { return _ZMM23_REG_mask; } |
| 49962 | extern const RegMask _XMM24_REG_mask; |
| 49963 | inline const RegMask &XMM24_REG_mask() { return _XMM24_REG_mask; } |
| 49964 | extern const RegMask _YMM24_REG_mask; |
| 49965 | inline const RegMask &YMM24_REG_mask() { return _YMM24_REG_mask; } |
| 49966 | extern const RegMask _ZMM24_REG_mask; |
| 49967 | inline const RegMask &ZMM24_REG_mask() { return _ZMM24_REG_mask; } |
| 49968 | extern const RegMask _XMM25_REG_mask; |
| 49969 | inline const RegMask &XMM25_REG_mask() { return _XMM25_REG_mask; } |
| 49970 | extern const RegMask _YMM25_REG_mask; |
| 49971 | inline const RegMask &YMM25_REG_mask() { return _YMM25_REG_mask; } |
| 49972 | extern const RegMask _ZMM25_REG_mask; |
| 49973 | inline const RegMask &ZMM25_REG_mask() { return _ZMM25_REG_mask; } |
| 49974 | extern const RegMask _XMM26_REG_mask; |
| 49975 | inline const RegMask &XMM26_REG_mask() { return _XMM26_REG_mask; } |
| 49976 | extern const RegMask _YMM26_REG_mask; |
| 49977 | inline const RegMask &YMM26_REG_mask() { return _YMM26_REG_mask; } |
| 49978 | extern const RegMask _ZMM26_REG_mask; |
| 49979 | inline const RegMask &ZMM26_REG_mask() { return _ZMM26_REG_mask; } |
| 49980 | extern const RegMask _XMM27_REG_mask; |
| 49981 | inline const RegMask &XMM27_REG_mask() { return _XMM27_REG_mask; } |
| 49982 | extern const RegMask _YMM27_REG_mask; |
| 49983 | inline const RegMask &YMM27_REG_mask() { return _YMM27_REG_mask; } |
| 49984 | extern const RegMask _ZMM27_REG_mask; |
| 49985 | inline const RegMask &ZMM27_REG_mask() { return _ZMM27_REG_mask; } |
| 49986 | extern const RegMask _XMM28_REG_mask; |
| 49987 | inline const RegMask &XMM28_REG_mask() { return _XMM28_REG_mask; } |
| 49988 | extern const RegMask _YMM28_REG_mask; |
| 49989 | inline const RegMask &YMM28_REG_mask() { return _YMM28_REG_mask; } |
| 49990 | extern const RegMask _ZMM28_REG_mask; |
| 49991 | inline const RegMask &ZMM28_REG_mask() { return _ZMM28_REG_mask; } |
| 49992 | extern const RegMask _XMM29_REG_mask; |
| 49993 | inline const RegMask &XMM29_REG_mask() { return _XMM29_REG_mask; } |
| 49994 | extern const RegMask _YMM29_REG_mask; |
| 49995 | inline const RegMask &YMM29_REG_mask() { return _YMM29_REG_mask; } |
| 49996 | extern const RegMask _ZMM29_REG_mask; |
| 49997 | inline const RegMask &ZMM29_REG_mask() { return _ZMM29_REG_mask; } |
| 49998 | extern const RegMask _XMM30_REG_mask; |
| 49999 | inline const RegMask &XMM30_REG_mask() { return _XMM30_REG_mask; } |
| 50000 | extern const RegMask _YMM30_REG_mask; |
| 50001 | inline const RegMask &YMM30_REG_mask() { return _YMM30_REG_mask; } |
| 50002 | extern const RegMask _ZMM30_REG_mask; |
| 50003 | inline const RegMask &ZMM30_REG_mask() { return _ZMM30_REG_mask; } |
| 50004 | extern const RegMask _XMM31_REG_mask; |
| 50005 | inline const RegMask &XMM31_REG_mask() { return _XMM31_REG_mask; } |
| 50006 | extern const RegMask _YMM31_REG_mask; |
| 50007 | inline const RegMask &YMM31_REG_mask() { return _YMM31_REG_mask; } |
| 50008 | extern const RegMask _ZMM31_REG_mask; |
| 50009 | inline const RegMask &ZMM31_REG_mask() { return _ZMM31_REG_mask; } |
| 50010 | extern const RegMask _STACK_SLOTS_mask; |
| 50011 | inline const RegMask &STACK_SLOTS_mask() { return _STACK_SLOTS_mask; } |
| 50012 | extern const RegMask _STACK_OR_STACK_SLOTS_mask; |
| 50013 | inline const RegMask &STACK_OR_STACK_SLOTS_mask() { return _STACK_OR_STACK_SLOTS_mask; } |
| 50014 | |
| 50015 | #endif // GENERATED_ADFILES_AD_HPP |
| 50016 |
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