1#line 1 "ad_x86_misc.cpp"
2//
3// Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5//
6// This code is free software; you can redistribute it and/or modify it
7// under the terms of the GNU General Public License version 2 only, as
8// published by the Free Software Foundation.
9//
10// This code is distributed in the hope that it will be useful, but WITHOUT
11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13// version 2 for more details (a copy is included in the LICENSE file that
14// accompanied this code).
15//
16// You should have received a copy of the GNU General Public License version
17// 2 along with this work; if not, write to the Free Software Foundation,
18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19//
20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21// or visit www.oracle.com if you need additional information or have any
22// questions.
23//
24//
25
26// Machine Generated File. Do Not Edit!
27
28#include "precompiled.hpp"
29#include "adfiles/ad_x86.hpp"
30const RegMask &loadBNode::out_RegMask() const { return (INT_REG_mask()); }
31const RegMask &loadB2LNode::out_RegMask() const { return (LONG_REG_mask()); }
32const RegMask &loadUBNode::out_RegMask() const { return (INT_REG_mask()); }
33const RegMask &loadUB2LNode::out_RegMask() const { return (LONG_REG_mask()); }
34const RegMask &loadUB2L_immINode::out_RegMask() const { return (LONG_REG_mask()); }
35const RegMask &loadSNode::out_RegMask() const { return (INT_REG_mask()); }
36const RegMask &loadS2BNode::out_RegMask() const { return (INT_REG_mask()); }
37const RegMask &loadS2LNode::out_RegMask() const { return (LONG_REG_mask()); }
38const RegMask &loadUSNode::out_RegMask() const { return (INT_REG_mask()); }
39const RegMask &loadUS2BNode::out_RegMask() const { return (INT_REG_mask()); }
40const RegMask &loadUS2LNode::out_RegMask() const { return (LONG_REG_mask()); }
41const RegMask &loadUS2L_immI_255Node::out_RegMask() const { return (LONG_REG_mask()); }
42const RegMask &loadUS2L_immINode::out_RegMask() const { return (LONG_REG_mask()); }
43const RegMask &loadINode::out_RegMask() const { return (INT_REG_mask()); }
44const RegMask &loadI2BNode::out_RegMask() const { return (INT_REG_mask()); }
45const RegMask &loadI2UBNode::out_RegMask() const { return (INT_REG_mask()); }
46const RegMask &loadI2SNode::out_RegMask() const { return (INT_REG_mask()); }
47const RegMask &loadI2USNode::out_RegMask() const { return (INT_REG_mask()); }
48const RegMask &loadI2LNode::out_RegMask() const { return (LONG_REG_mask()); }
49const RegMask &loadI2L_immI_255Node::out_RegMask() const { return (LONG_REG_mask()); }
50const RegMask &loadI2L_immI_65535Node::out_RegMask() const { return (LONG_REG_mask()); }
51const RegMask &loadI2L_immU31Node::out_RegMask() const { return (LONG_REG_mask()); }
52const RegMask &loadUI2LNode::out_RegMask() const { return (LONG_REG_mask()); }
53const RegMask &loadLNode::out_RegMask() const { return (LONG_REG_mask()); }
54const RegMask &loadRangeNode::out_RegMask() const { return (INT_REG_mask()); }
55const RegMask &loadPNode::out_RegMask() const { return (PTR_REG_mask()); }
56const RegMask &loadNNode::out_RegMask() const { return (INT_REG_mask()); }
57const RegMask &loadKlassNode::out_RegMask() const { return (PTR_REG_mask()); }
58const RegMask &loadNKlassNode::out_RegMask() const { return (INT_REG_mask()); }
59const RegMask &loadFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
60const RegMask &MoveF2VLNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
61const RegMask &MoveF2LEGNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
62const RegMask &MoveVL2FNode::out_RegMask() const { return (FLOAT_REG_mask()); }
63const RegMask &MoveLEG2FNode::out_RegMask() const { return (FLOAT_REG_mask()); }
64const RegMask &loadD_partialNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
65const RegMask &loadDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
66const RegMask &MoveD2VLNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
67const RegMask &MoveD2LEGNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
68const RegMask &MoveVL2DNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
69const RegMask &MoveLEG2DNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
70const RegMask &maxF_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
71const RegMask &maxF_reduction_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
72const RegMask &maxD_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
73const RegMask &maxD_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
74const RegMask &minF_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
75const RegMask &minF_reduction_regNode::out_RegMask() const { return (FLOAT_REG_LEGACY_mask()); }
76const RegMask &minD_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
77const RegMask &minD_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_LEGACY_mask()); }
78const RegMask &leaP8Node::out_RegMask() const { return (PTR_REG_mask()); }
79const RegMask &leaP32Node::out_RegMask() const { return (PTR_REG_mask()); }
80const RegMask &leaPIdxOffNode::out_RegMask() const { return (PTR_REG_mask()); }
81const RegMask &leaPIdxScaleNode::out_RegMask() const { return (PTR_REG_mask()); }
82const RegMask &leaPPosIdxScaleNode::out_RegMask() const { return (PTR_REG_mask()); }
83const RegMask &leaPIdxScaleOffNode::out_RegMask() const { return (PTR_REG_mask()); }
84const RegMask &leaPPosIdxOffNode::out_RegMask() const { return (PTR_REG_mask()); }
85const RegMask &leaPPosIdxScaleOffNode::out_RegMask() const { return (PTR_REG_mask()); }
86const RegMask &leaPCompressedOopOffsetNode::out_RegMask() const { return (PTR_REG_mask()); }
87const RegMask &leaP8NarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
88const RegMask &leaP32NarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
89const RegMask &leaPIdxOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
90const RegMask &leaPIdxScaleNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
91const RegMask &leaPIdxScaleOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
92const RegMask &leaPPosIdxOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
93const RegMask &leaPPosIdxScaleOffNarrowNode::out_RegMask() const { return (PTR_REG_mask()); }
94const RegMask &loadConINode::out_RegMask() const { return (INT_REG_mask()); }
95const RegMask &loadConI0Node::out_RegMask() const { return (INT_REG_mask()); }
96const RegMask &loadConLNode::out_RegMask() const { return (LONG_REG_mask()); }
97const RegMask &loadConL0Node::out_RegMask() const { return (LONG_REG_mask()); }
98const RegMask &loadConUL32Node::out_RegMask() const { return (LONG_REG_mask()); }
99const RegMask &loadConL32Node::out_RegMask() const { return (LONG_REG_mask()); }
100const RegMask &loadConPNode::out_RegMask() const { return (PTR_REG_mask()); }
101const RegMask &loadConP0Node::out_RegMask() const { return (PTR_REG_mask()); }
102const RegMask &loadConP31Node::out_RegMask() const { return (PTR_REG_mask()); }
103const RegMask &loadConFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
104const RegMask &loadConN0Node::out_RegMask() const { return (INT_REG_mask()); }
105const RegMask &loadConNNode::out_RegMask() const { return (INT_REG_mask()); }
106const RegMask &loadConNKlassNode::out_RegMask() const { return (INT_REG_mask()); }
107const RegMask &loadConF0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
108const RegMask &loadConDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
109const RegMask &loadConD0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
110const RegMask &loadSSINode::out_RegMask() const { return (INT_REG_mask()); }
111const RegMask &loadSSLNode::out_RegMask() const { return (LONG_REG_mask()); }
112const RegMask &loadSSPNode::out_RegMask() const { return (PTR_REG_mask()); }
113const RegMask &loadSSFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
114const RegMask &loadSSDNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
115const RegMask &prefetchAllocNode::out_RegMask() const { return (RegMask::Empty); }
116const RegMask &prefetchAllocNTANode::out_RegMask() const { return (RegMask::Empty); }
117const RegMask &prefetchAllocT0Node::out_RegMask() const { return (RegMask::Empty); }
118const RegMask &prefetchAllocT2Node::out_RegMask() const { return (RegMask::Empty); }
119const RegMask &storeBNode::out_RegMask() const { return (RegMask::Empty); }
120const RegMask &storeCNode::out_RegMask() const { return (RegMask::Empty); }
121const RegMask &storeINode::out_RegMask() const { return (RegMask::Empty); }
122const RegMask &storeLNode::out_RegMask() const { return (RegMask::Empty); }
123const RegMask &storePNode::out_RegMask() const { return (RegMask::Empty); }
124const RegMask &storeImmP0Node::out_RegMask() const { return (RegMask::Empty); }
125const RegMask &storeImmPNode::out_RegMask() const { return (RegMask::Empty); }
126const RegMask &storeNNode::out_RegMask() const { return (RegMask::Empty); }
127const RegMask &storeNKlassNode::out_RegMask() const { return (RegMask::Empty); }
128const RegMask &storeImmN0Node::out_RegMask() const { return (RegMask::Empty); }
129const RegMask &storeImmNNode::out_RegMask() const { return (RegMask::Empty); }
130const RegMask &storeImmNKlassNode::out_RegMask() const { return (RegMask::Empty); }
131const RegMask &storeImmI0Node::out_RegMask() const { return (RegMask::Empty); }
132const RegMask &storeImmINode::out_RegMask() const { return (RegMask::Empty); }
133const RegMask &storeImmL0Node::out_RegMask() const { return (RegMask::Empty); }
134const RegMask &storeImmLNode::out_RegMask() const { return (RegMask::Empty); }
135const RegMask &storeImmC0Node::out_RegMask() const { return (RegMask::Empty); }
136const RegMask &storeImmI16Node::out_RegMask() const { return (RegMask::Empty); }
137const RegMask &storeImmB0Node::out_RegMask() const { return (RegMask::Empty); }
138const RegMask &storeImmBNode::out_RegMask() const { return (RegMask::Empty); }
139const RegMask &storeImmCM0_regNode::out_RegMask() const { return (RegMask::Empty); }
140const RegMask &storeImmCM0Node::out_RegMask() const { return (RegMask::Empty); }
141const RegMask &storeFNode::out_RegMask() const { return (RegMask::Empty); }
142const RegMask &storeF0Node::out_RegMask() const { return (RegMask::Empty); }
143const RegMask &storeF_immNode::out_RegMask() const { return (RegMask::Empty); }
144const RegMask &storeDNode::out_RegMask() const { return (RegMask::Empty); }
145const RegMask &storeD0_immNode::out_RegMask() const { return (RegMask::Empty); }
146const RegMask &storeD0Node::out_RegMask() const { return (RegMask::Empty); }
147const RegMask &storeSSINode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
148const RegMask &storeSSLNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
149const RegMask &storeSSPNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
150const RegMask &storeSSFNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
151const RegMask &storeSSDNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
152const RegMask &bytes_reverse_intNode::out_RegMask() const { return (INT_REG_mask()); }
153const RegMask &bytes_reverse_longNode::out_RegMask() const { return (LONG_REG_mask()); }
154const RegMask &bytes_reverse_unsigned_shortNode::out_RegMask() const { return (INT_REG_mask()); }
155const RegMask &bytes_reverse_shortNode::out_RegMask() const { return (INT_REG_mask()); }
156const RegMask &countLeadingZerosINode::out_RegMask() const { return (INT_REG_mask()); }
157const RegMask &countLeadingZerosI_bsrNode::out_RegMask() const { return (INT_REG_mask()); }
158const RegMask &countLeadingZerosLNode::out_RegMask() const { return (INT_REG_mask()); }
159const RegMask &countLeadingZerosL_bsrNode::out_RegMask() const { return (INT_REG_mask()); }
160const RegMask &countTrailingZerosINode::out_RegMask() const { return (INT_REG_mask()); }
161const RegMask &countTrailingZerosI_bsfNode::out_RegMask() const { return (INT_REG_mask()); }
162const RegMask &countTrailingZerosLNode::out_RegMask() const { return (INT_REG_mask()); }
163const RegMask &countTrailingZerosL_bsfNode::out_RegMask() const { return (INT_REG_mask()); }
164const RegMask &popCountINode::out_RegMask() const { return (INT_REG_mask()); }
165const RegMask &popCountI_memNode::out_RegMask() const { return (INT_REG_mask()); }
166const RegMask &popCountLNode::out_RegMask() const { return (INT_REG_mask()); }
167const RegMask &popCountL_memNode::out_RegMask() const { return (INT_REG_mask()); }
168const RegMask &membar_acquireNode::out_RegMask() const { return (RegMask::Empty); }
169const RegMask &membar_acquire_0Node::out_RegMask() const { return (RegMask::Empty); }
170const RegMask &membar_acquire_lockNode::out_RegMask() const { return (RegMask::Empty); }
171const RegMask &membar_releaseNode::out_RegMask() const { return (RegMask::Empty); }
172const RegMask &membar_release_0Node::out_RegMask() const { return (RegMask::Empty); }
173const RegMask &membar_release_lockNode::out_RegMask() const { return (RegMask::Empty); }
174const RegMask &membar_volatileNode::out_RegMask() const { return (RegMask::Empty); }
175const RegMask &unnecessary_membar_volatileNode::out_RegMask() const { return (RegMask::Empty); }
176const RegMask &membar_storestoreNode::out_RegMask() const { return (RegMask::Empty); }
177const RegMask &castX2PNode::out_RegMask() const { return (PTR_REG_mask()); }
178const RegMask &castP2XNode::out_RegMask() const { return (LONG_REG_mask()); }
179const RegMask &convP2INode::out_RegMask() const { return (INT_REG_mask()); }
180const RegMask &convN2INode::out_RegMask() const { return (INT_REG_mask()); }
181const RegMask &encodeHeapOopNode::out_RegMask() const { return (INT_REG_mask()); }
182const RegMask &encodeHeapOop_not_nullNode::out_RegMask() const { return (INT_REG_mask()); }
183const RegMask &decodeHeapOopNode::out_RegMask() const { return (PTR_REG_mask()); }
184const RegMask &decodeHeapOop_not_nullNode::out_RegMask() const { return (PTR_REG_mask()); }
185const RegMask &encodeKlass_not_nullNode::out_RegMask() const { return (INT_REG_mask()); }
186const RegMask &decodeKlass_not_nullNode::out_RegMask() const { return (PTR_REG_mask()); }
187const RegMask &jumpXtnd_offsetNode::out_RegMask() const { return (RegMask::Empty); }
188const RegMask &jumpXtnd_addrNode::out_RegMask() const { return (RegMask::Empty); }
189const RegMask &jumpXtndNode::out_RegMask() const { return (RegMask::Empty); }
190const RegMask &cmovI_regNode::out_RegMask() const { return (INT_REG_mask()); }
191const RegMask &cmovI_regUNode::out_RegMask() const { return (INT_REG_mask()); }
192const RegMask &cmovI_regUCFNode::out_RegMask() const { return (INT_REG_mask()); }
193const RegMask &cmovI_memNode::out_RegMask() const { return (INT_REG_mask()); }
194const RegMask &cmovI_memUNode::out_RegMask() const { return (INT_REG_mask()); }
195const RegMask &cmovI_memUCFNode::out_RegMask() const { return (INT_REG_mask()); }
196const RegMask &cmovN_regNode::out_RegMask() const { return (INT_REG_mask()); }
197const RegMask &cmovN_regUNode::out_RegMask() const { return (INT_REG_mask()); }
198const RegMask &cmovN_regUCFNode::out_RegMask() const { return (INT_REG_mask()); }
199const RegMask &cmovP_regNode::out_RegMask() const { return (PTR_REG_mask()); }
200const RegMask &cmovP_regUNode::out_RegMask() const { return (PTR_REG_mask()); }
201const RegMask &cmovP_regUCFNode::out_RegMask() const { return (PTR_REG_mask()); }
202const RegMask &cmovL_regNode::out_RegMask() const { return (LONG_REG_mask()); }
203const RegMask &cmovL_memNode::out_RegMask() const { return (LONG_REG_mask()); }
204const RegMask &cmovL_regUNode::out_RegMask() const { return (LONG_REG_mask()); }
205const RegMask &cmovL_regUCFNode::out_RegMask() const { return (LONG_REG_mask()); }
206const RegMask &cmovL_memUNode::out_RegMask() const { return (LONG_REG_mask()); }
207const RegMask &cmovL_memUCFNode::out_RegMask() const { return (LONG_REG_mask()); }
208const RegMask &cmovF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
209const RegMask &cmovF_regUNode::out_RegMask() const { return (FLOAT_REG_mask()); }
210const RegMask &cmovF_regUCFNode::out_RegMask() const { return (FLOAT_REG_mask()); }
211const RegMask &cmovD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
212const RegMask &cmovD_regUNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
213const RegMask &cmovD_regUCFNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
214const RegMask &addI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
215const RegMask &addI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
216const RegMask &addI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
217const RegMask &addI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
218const RegMask &addI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
219const RegMask &addI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
220const RegMask &addI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
221const RegMask &incI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
222const RegMask &incI_memNode::out_RegMask() const { return (RegMask::Empty); }
223const RegMask &decI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
224const RegMask &decI_memNode::out_RegMask() const { return (RegMask::Empty); }
225const RegMask &leaI_rReg_immINode::out_RegMask() const { return (INT_REG_mask()); }
226const RegMask &addL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
227const RegMask &addL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
228const RegMask &addL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
229const RegMask &addL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
230const RegMask &addL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
231const RegMask &addL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
232const RegMask &addL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
233const RegMask &incL_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
234const RegMask &incL_memNode::out_RegMask() const { return (RegMask::Empty); }
235const RegMask &decL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
236const RegMask &decL_memNode::out_RegMask() const { return (RegMask::Empty); }
237const RegMask &leaL_rReg_immLNode::out_RegMask() const { return (LONG_REG_mask()); }
238const RegMask &addP_rRegNode::out_RegMask() const { return (PTR_REG_mask()); }
239const RegMask &addP_rReg_immNode::out_RegMask() const { return (PTR_REG_mask()); }
240const RegMask &leaP_rReg_immNode::out_RegMask() const { return (PTR_REG_mask()); }
241const RegMask &checkCastPPNode::out_RegMask() const { return (PTR_REG_mask()); }
242const RegMask &castPPNode::out_RegMask() const { return (PTR_REG_mask()); }
243const RegMask &castIINode::out_RegMask() const { return (INT_REG_mask()); }
244const RegMask &loadPLockedNode::out_RegMask() const { return (PTR_REG_mask()); }
245const RegMask &storePConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
246const RegMask &storeIConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
247const RegMask &storeLConditionalNode::out_RegMask() const { return (INT_FLAGS_mask()); }
248const RegMask &compareAndSwapPNode::out_RegMask() const { return (INT_REG_mask()); }
249const RegMask &compareAndSwapP_0Node::out_RegMask() const { return (INT_REG_mask()); }
250const RegMask &compareAndSwapLNode::out_RegMask() const { return (INT_REG_mask()); }
251const RegMask &compareAndSwapL_0Node::out_RegMask() const { return (INT_REG_mask()); }
252const RegMask &compareAndSwapINode::out_RegMask() const { return (INT_REG_mask()); }
253const RegMask &compareAndSwapI_0Node::out_RegMask() const { return (INT_REG_mask()); }
254const RegMask &compareAndSwapBNode::out_RegMask() const { return (INT_REG_mask()); }
255const RegMask &compareAndSwapB_0Node::out_RegMask() const { return (INT_REG_mask()); }
256const RegMask &compareAndSwapSNode::out_RegMask() const { return (INT_REG_mask()); }
257const RegMask &compareAndSwapS_0Node::out_RegMask() const { return (INT_REG_mask()); }
258const RegMask &compareAndSwapNNode::out_RegMask() const { return (INT_REG_mask()); }
259const RegMask &compareAndSwapN_0Node::out_RegMask() const { return (INT_REG_mask()); }
260const RegMask &compareAndExchangeBNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
261const RegMask &compareAndExchangeSNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
262const RegMask &compareAndExchangeINode::out_RegMask() const { return (INT_RAX_REG_mask()); }
263const RegMask &compareAndExchangeLNode::out_RegMask() const { return (LONG_RAX_REG_mask()); }
264const RegMask &compareAndExchangeNNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
265const RegMask &compareAndExchangePNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
266const RegMask &xaddB_no_resNode::out_RegMask() const { return (RegMask::Empty); }
267const RegMask &xaddBNode::out_RegMask() const { return (INT_REG_mask()); }
268const RegMask &xaddS_no_resNode::out_RegMask() const { return (RegMask::Empty); }
269const RegMask &xaddSNode::out_RegMask() const { return (INT_REG_mask()); }
270const RegMask &xaddI_no_resNode::out_RegMask() const { return (RegMask::Empty); }
271const RegMask &xaddINode::out_RegMask() const { return (INT_REG_mask()); }
272const RegMask &xaddL_no_resNode::out_RegMask() const { return (RegMask::Empty); }
273const RegMask &xaddLNode::out_RegMask() const { return (LONG_REG_mask()); }
274const RegMask &xchgBNode::out_RegMask() const { return (INT_REG_mask()); }
275const RegMask &xchgSNode::out_RegMask() const { return (INT_REG_mask()); }
276const RegMask &xchgINode::out_RegMask() const { return (INT_REG_mask()); }
277const RegMask &xchgLNode::out_RegMask() const { return (LONG_REG_mask()); }
278const RegMask &xchgPNode::out_RegMask() const { return (PTR_REG_mask()); }
279const RegMask &xchgNNode::out_RegMask() const { return (INT_REG_mask()); }
280const RegMask &absI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
281const RegMask &absL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
282const RegMask &subI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
283const RegMask &subI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
284const RegMask &subI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
285const RegMask &subI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
286const RegMask &subI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
287const RegMask &subL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
288const RegMask &subL_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
289const RegMask &subL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
290const RegMask &subL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
291const RegMask &subL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
292const RegMask &subP_rRegNode::out_RegMask() const { return (PTR_REG_mask()); }
293const RegMask &negI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
294const RegMask &negI_memNode::out_RegMask() const { return (RegMask::Empty); }
295const RegMask &negL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
296const RegMask &negL_memNode::out_RegMask() const { return (RegMask::Empty); }
297const RegMask &mulI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
298const RegMask &mulI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
299const RegMask &mulI_memNode::out_RegMask() const { return (INT_REG_mask()); }
300const RegMask &mulI_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
301const RegMask &mulI_mem_immNode::out_RegMask() const { return (INT_REG_mask()); }
302const RegMask &mulAddS2I_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
303const RegMask &mulL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
304const RegMask &mulL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
305const RegMask &mulL_memNode::out_RegMask() const { return (LONG_REG_mask()); }
306const RegMask &mulL_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
307const RegMask &mulL_mem_immNode::out_RegMask() const { return (LONG_REG_mask()); }
308const RegMask &mulHiL_rRegNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
309const RegMask &divI_rRegNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
310const RegMask &divL_rRegNode::out_RegMask() const { return (LONG_RAX_REG_mask()); }
311const RegMask &divModI_rReg_divmodNode::out_RegMask() const { return (RegMask::Empty); }
312const RegMask &divModL_rReg_divmodNode::out_RegMask() const { return (RegMask::Empty); }
313const RegMask &loadConL_0x6666666666666667Node::out_RegMask() const { return (LONG_REG_mask()); }
314const RegMask &mul_hiNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
315const RegMask &sarL_rReg_63Node::out_RegMask() const { return (LONG_REG_mask()); }
316const RegMask &sarL_rReg_2Node::out_RegMask() const { return (LONG_REG_mask()); }
317const RegMask &divL_10Node::out_RegMask() const { return (LONG_RDX_REG_mask()); }
318const RegMask &modI_rRegNode::out_RegMask() const { return (INT_RDX_REG_mask()); }
319const RegMask &modL_rRegNode::out_RegMask() const { return (LONG_RDX_REG_mask()); }
320const RegMask &salI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
321const RegMask &salI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
322const RegMask &salI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
323const RegMask &salI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
324const RegMask &salI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
325const RegMask &salI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
326const RegMask &sarI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
327const RegMask &sarI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
328const RegMask &sarI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
329const RegMask &sarI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
330const RegMask &sarI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
331const RegMask &sarI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
332const RegMask &shrI_rReg_1Node::out_RegMask() const { return (INT_REG_mask()); }
333const RegMask &shrI_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
334const RegMask &shrI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
335const RegMask &shrI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
336const RegMask &shrI_rReg_CLNode::out_RegMask() const { return (INT_REG_mask()); }
337const RegMask &shrI_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
338const RegMask &salL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
339const RegMask &salL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
340const RegMask &salL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
341const RegMask &salL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
342const RegMask &salL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
343const RegMask &salL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
344const RegMask &sarL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
345const RegMask &sarL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
346const RegMask &sarL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
347const RegMask &sarL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
348const RegMask &sarL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
349const RegMask &sarL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
350const RegMask &shrL_rReg_1Node::out_RegMask() const { return (LONG_REG_mask()); }
351const RegMask &shrL_mem_1Node::out_RegMask() const { return (RegMask::Empty); }
352const RegMask &shrL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
353const RegMask &shrL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
354const RegMask &shrL_rReg_CLNode::out_RegMask() const { return (LONG_REG_mask()); }
355const RegMask &shrL_mem_CLNode::out_RegMask() const { return (RegMask::Empty); }
356const RegMask &i2bNode::out_RegMask() const { return (INT_REG_mask()); }
357const RegMask &i2sNode::out_RegMask() const { return (INT_REG_mask()); }
358const RegMask &rolI_rReg_imm1Node::out_RegMask() const { return (INT_REG_mask()); }
359const RegMask &rolI_rReg_imm8Node::out_RegMask() const { return (INT_REG_mask()); }
360const RegMask &rolI_rReg_CLNode::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
361const RegMask &rolI_rReg_i1Node::out_RegMask() const { return (INT_REG_mask()); }
362const RegMask &rolI_rReg_i1_0Node::out_RegMask() const { return (INT_REG_mask()); }
363const RegMask &rolI_rReg_i8Node::out_RegMask() const { return (INT_REG_mask()); }
364const RegMask &rolI_rReg_i8_0Node::out_RegMask() const { return (INT_REG_mask()); }
365const RegMask &rolI_rReg_Var_C0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
366const RegMask &rolI_rReg_Var_C0_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
367const RegMask &rolI_rReg_Var_C32Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
368const RegMask &rolI_rReg_Var_C32_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
369const RegMask &rorI_rReg_imm1Node::out_RegMask() const { return (INT_REG_mask()); }
370const RegMask &rorI_rReg_imm8Node::out_RegMask() const { return (INT_REG_mask()); }
371const RegMask &rorI_rReg_CLNode::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
372const RegMask &rorI_rReg_i1Node::out_RegMask() const { return (INT_REG_mask()); }
373const RegMask &rorI_rReg_i1_0Node::out_RegMask() const { return (INT_REG_mask()); }
374const RegMask &rorI_rReg_i8Node::out_RegMask() const { return (INT_REG_mask()); }
375const RegMask &rorI_rReg_i8_0Node::out_RegMask() const { return (INT_REG_mask()); }
376const RegMask &rorI_rReg_Var_C0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
377const RegMask &rorI_rReg_Var_C0_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
378const RegMask &rorI_rReg_Var_C32Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
379const RegMask &rorI_rReg_Var_C32_0Node::out_RegMask() const { return (INT_NO_RCX_REG_mask()); }
380const RegMask &rolL_rReg_imm1Node::out_RegMask() const { return (LONG_REG_mask()); }
381const RegMask &rolL_rReg_imm8Node::out_RegMask() const { return (LONG_REG_mask()); }
382const RegMask &rolL_rReg_CLNode::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
383const RegMask &rolL_rReg_i1Node::out_RegMask() const { return (LONG_REG_mask()); }
384const RegMask &rolL_rReg_i1_0Node::out_RegMask() const { return (LONG_REG_mask()); }
385const RegMask &rolL_rReg_i8Node::out_RegMask() const { return (LONG_REG_mask()); }
386const RegMask &rolL_rReg_i8_0Node::out_RegMask() const { return (LONG_REG_mask()); }
387const RegMask &rolL_rReg_Var_C0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
388const RegMask &rolL_rReg_Var_C0_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
389const RegMask &rolL_rReg_Var_C64Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
390const RegMask &rolL_rReg_Var_C64_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
391const RegMask &rorL_rReg_imm1Node::out_RegMask() const { return (LONG_REG_mask()); }
392const RegMask &rorL_rReg_imm8Node::out_RegMask() const { return (LONG_REG_mask()); }
393const RegMask &rorL_rReg_CLNode::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
394const RegMask &rorL_rReg_i1Node::out_RegMask() const { return (LONG_REG_mask()); }
395const RegMask &rorL_rReg_i1_0Node::out_RegMask() const { return (LONG_REG_mask()); }
396const RegMask &rorL_rReg_i8Node::out_RegMask() const { return (LONG_REG_mask()); }
397const RegMask &rorL_rReg_i8_0Node::out_RegMask() const { return (LONG_REG_mask()); }
398const RegMask &rorL_rReg_Var_C0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
399const RegMask &rorL_rReg_Var_C0_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
400const RegMask &rorL_rReg_Var_C64Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
401const RegMask &rorL_rReg_Var_C64_0Node::out_RegMask() const { return (LONG_NO_RCX_REG_mask()); }
402const RegMask &andI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
403const RegMask &andI_rReg_imm255Node::out_RegMask() const { return (INT_REG_mask()); }
404const RegMask &andI2L_rReg_imm255Node::out_RegMask() const { return (LONG_REG_mask()); }
405const RegMask &andI_rReg_imm65535Node::out_RegMask() const { return (INT_REG_mask()); }
406const RegMask &andI2L_rReg_imm65535Node::out_RegMask() const { return (LONG_REG_mask()); }
407const RegMask &andI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
408const RegMask &andI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
409const RegMask &andI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
410const RegMask &andB_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
411const RegMask &andB_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
412const RegMask &andI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
413const RegMask &andI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
414const RegMask &andI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
415const RegMask &andnI_rReg_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
416const RegMask &andnI_rReg_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
417const RegMask &andnI_rReg_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
418const RegMask &andnI_rReg_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
419const RegMask &blsiI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
420const RegMask &blsiI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
421const RegMask &blsiI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
422const RegMask &blsiI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
423const RegMask &blsmskI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
424const RegMask &blsmskI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
425const RegMask &blsmskI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
426const RegMask &blsmskI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
427const RegMask &blsrI_rReg_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
428const RegMask &blsrI_rReg_rReg_0Node::out_RegMask() const { return (INT_REG_mask()); }
429const RegMask &blsrI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
430const RegMask &blsrI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
431const RegMask &orI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
432const RegMask &orI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
433const RegMask &orI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
434const RegMask &orI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
435const RegMask &orB_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
436const RegMask &orB_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
437const RegMask &orI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
438const RegMask &orI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
439const RegMask &orI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
440const RegMask &xorI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
441const RegMask &xorI_rReg_im1Node::out_RegMask() const { return (INT_REG_mask()); }
442const RegMask &xorI_rReg_immNode::out_RegMask() const { return (INT_REG_mask()); }
443const RegMask &xorI_rReg_memNode::out_RegMask() const { return (INT_REG_mask()); }
444const RegMask &xorI_rReg_mem_0Node::out_RegMask() const { return (INT_REG_mask()); }
445const RegMask &xorB_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
446const RegMask &xorB_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
447const RegMask &xorI_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
448const RegMask &xorI_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
449const RegMask &xorI_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
450const RegMask &andL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
451const RegMask &andL_rReg_imm255Node::out_RegMask() const { return (LONG_REG_mask()); }
452const RegMask &andL_rReg_imm65535Node::out_RegMask() const { return (LONG_REG_mask()); }
453const RegMask &andL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
454const RegMask &andL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
455const RegMask &andL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
456const RegMask &andL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
457const RegMask &andL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
458const RegMask &andL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
459const RegMask &andnL_rReg_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
460const RegMask &andnL_rReg_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
461const RegMask &andnL_rReg_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
462const RegMask &andnL_rReg_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
463const RegMask &blsiL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
464const RegMask &blsiL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
465const RegMask &blsiL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
466const RegMask &blsiL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
467const RegMask &blsmskL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
468const RegMask &blsmskL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
469const RegMask &blsmskL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
470const RegMask &blsmskL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
471const RegMask &blsrL_rReg_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
472const RegMask &blsrL_rReg_rReg_0Node::out_RegMask() const { return (LONG_REG_mask()); }
473const RegMask &blsrL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
474const RegMask &blsrL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
475const RegMask &orL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
476const RegMask &orL_rReg_castP2XNode::out_RegMask() const { return (LONG_REG_mask()); }
477const RegMask &orL_rReg_castP2X_0Node::out_RegMask() const { return (LONG_REG_mask()); }
478const RegMask &orL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
479const RegMask &orL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
480const RegMask &orL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
481const RegMask &orL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
482const RegMask &orL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
483const RegMask &orL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
484const RegMask &xorL_rRegNode::out_RegMask() const { return (LONG_REG_mask()); }
485const RegMask &xorL_rReg_im1Node::out_RegMask() const { return (LONG_REG_mask()); }
486const RegMask &xorL_rReg_immNode::out_RegMask() const { return (LONG_REG_mask()); }
487const RegMask &xorL_rReg_memNode::out_RegMask() const { return (LONG_REG_mask()); }
488const RegMask &xorL_rReg_mem_0Node::out_RegMask() const { return (LONG_REG_mask()); }
489const RegMask &xorL_mem_rRegNode::out_RegMask() const { return (RegMask::Empty); }
490const RegMask &xorL_mem_rReg_0Node::out_RegMask() const { return (RegMask::Empty); }
491const RegMask &xorL_mem_immNode::out_RegMask() const { return (RegMask::Empty); }
492const RegMask &convI2BNode::out_RegMask() const { return (INT_REG_mask()); }
493const RegMask &convP2BNode::out_RegMask() const { return (INT_REG_mask()); }
494const RegMask &cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
495const RegMask &cmpLTMask0Node::out_RegMask() const { return (INT_REG_mask()); }
496const RegMask &cadd_cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
497const RegMask &cadd_cmpLTMask_1Node::out_RegMask() const { return (INT_REG_mask()); }
498const RegMask &cadd_cmpLTMask_0Node::out_RegMask() const { return (INT_REG_mask()); }
499const RegMask &cadd_cmpLTMask_2Node::out_RegMask() const { return (INT_REG_mask()); }
500const RegMask &and_cmpLTMaskNode::out_RegMask() const { return (INT_REG_mask()); }
501const RegMask &and_cmpLTMask_0Node::out_RegMask() const { return (INT_REG_mask()); }
502const RegMask &cmpF_cc_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
503const RegMask &cmpF_cc_reg_CFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
504const RegMask &cmpF_cc_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
505const RegMask &cmpF_cc_memCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
506const RegMask &cmpF_cc_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
507const RegMask &cmpF_cc_immCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
508const RegMask &cmpD_cc_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
509const RegMask &cmpD_cc_reg_CFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
510const RegMask &cmpD_cc_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
511const RegMask &cmpD_cc_memCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
512const RegMask &cmpD_cc_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
513const RegMask &cmpD_cc_immCFNode::out_RegMask() const { return (INT_FLAGS_mask()); }
514const RegMask &cmpF_regNode::out_RegMask() const { return (INT_REG_mask()); }
515const RegMask &cmpF_memNode::out_RegMask() const { return (INT_REG_mask()); }
516const RegMask &cmpF_immNode::out_RegMask() const { return (INT_REG_mask()); }
517const RegMask &cmpD_regNode::out_RegMask() const { return (INT_REG_mask()); }
518const RegMask &cmpD_memNode::out_RegMask() const { return (INT_REG_mask()); }
519const RegMask &cmpD_immNode::out_RegMask() const { return (INT_REG_mask()); }
520const RegMask &roundFloat_nopNode::out_RegMask() const { return (FLOAT_REG_mask()); }
521const RegMask &roundDouble_nopNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
522const RegMask &convF2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
523const RegMask &convF2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
524const RegMask &convD2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
525const RegMask &convD2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
526const RegMask &convF2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
527const RegMask &convF2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
528const RegMask &convD2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
529const RegMask &convD2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
530const RegMask &convI2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
531const RegMask &convI2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
532const RegMask &convI2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
533const RegMask &convI2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
534const RegMask &convXI2F_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
535const RegMask &convXI2D_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
536const RegMask &convL2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
537const RegMask &convL2F_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
538const RegMask &convL2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
539const RegMask &convL2D_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
540const RegMask &convI2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
541const RegMask &convI2L_reg_reg_zexNode::out_RegMask() const { return (LONG_REG_mask()); }
542const RegMask &convI2L_reg_mem_zexNode::out_RegMask() const { return (LONG_REG_mask()); }
543const RegMask &zerox_long_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
544const RegMask &convL2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
545const RegMask &MoveF2I_stack_regNode::out_RegMask() const { return (INT_REG_mask()); }
546const RegMask &MoveI2F_stack_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
547const RegMask &MoveD2L_stack_regNode::out_RegMask() const { return (LONG_REG_mask()); }
548const RegMask &MoveL2D_stack_reg_partialNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
549const RegMask &MoveL2D_stack_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
550const RegMask &MoveF2I_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
551const RegMask &MoveI2F_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
552const RegMask &MoveD2L_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
553const RegMask &MoveL2D_reg_stackNode::out_RegMask() const { return ((Compile::current()->FIRST_STACK_mask())); }
554const RegMask &MoveF2I_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
555const RegMask &MoveD2L_reg_regNode::out_RegMask() const { return (LONG_REG_mask()); }
556const RegMask &MoveI2F_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
557const RegMask &MoveL2D_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
558const RegMask &rep_stosNode::out_RegMask() const { return (RegMask::Empty); }
559const RegMask &rep_stos_largeNode::out_RegMask() const { return (RegMask::Empty); }
560const RegMask &string_compareLNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
561const RegMask &string_compareUNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
562const RegMask &string_compareLUNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
563const RegMask &string_compareULNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
564const RegMask &string_indexof_conLNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
565const RegMask &string_indexof_conUNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
566const RegMask &string_indexof_conULNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
567const RegMask &string_indexofLNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
568const RegMask &string_indexofUNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
569const RegMask &string_indexofULNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
570const RegMask &string_indexofU_charNode::out_RegMask() const { return (INT_RBX_REG_mask()); }
571const RegMask &string_equalsNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
572const RegMask &array_equalsBNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
573const RegMask &array_equalsCNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
574const RegMask &has_negativesNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
575const RegMask &string_compressNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
576const RegMask &string_inflateNode::out_RegMask() const { return (RegMask::Empty); }
577const RegMask &encode_iso_arrayNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
578const RegMask &overflowAddI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
579const RegMask &overflowAddI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
580const RegMask &overflowAddL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
581const RegMask &overflowAddL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
582const RegMask &overflowSubI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
583const RegMask &overflowSubI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
584const RegMask &overflowSubL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
585const RegMask &overflowSubL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
586const RegMask &overflowNegI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
587const RegMask &overflowNegL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
588const RegMask &overflowMulI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
589const RegMask &overflowMulI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
590const RegMask &overflowMulL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
591const RegMask &overflowMulL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
592const RegMask &compI_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
593const RegMask &compI_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
594const RegMask &compI_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
595const RegMask &testI_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
596const RegMask &testI_reg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
597const RegMask &testI_reg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
598const RegMask &testI_reg_mem_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
599const RegMask &compU_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
600const RegMask &compU_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
601const RegMask &compU_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
602const RegMask &testU_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
603const RegMask &compP_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
604const RegMask &compP_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
605const RegMask &compP_mem_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
606const RegMask &testP_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
607const RegMask &testP_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
608const RegMask &testP_mem_reg0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
609const RegMask &compN_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
610const RegMask &compN_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
611const RegMask &compN_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
612const RegMask &compN_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
613const RegMask &compN_rReg_imm_klassNode::out_RegMask() const { return (INT_FLAGS_mask()); }
614const RegMask &compN_mem_imm_klassNode::out_RegMask() const { return (INT_FLAGS_mask()); }
615const RegMask &testN_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
616const RegMask &testN_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
617const RegMask &testN_mem_reg0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
618const RegMask &compL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
619const RegMask &compL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
620const RegMask &compL_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
621const RegMask &testL_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
622const RegMask &testL_reg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
623const RegMask &testL_reg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
624const RegMask &testL_reg_mem_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
625const RegMask &testL_reg_mem2Node::out_RegMask() const { return (INT_FLAGS_mask()); }
626const RegMask &testL_reg_mem2_0Node::out_RegMask() const { return (INT_FLAGS_mask()); }
627const RegMask &cmpL3_reg_regNode::out_RegMask() const { return (INT_REG_mask()); }
628const RegMask &compUL_rRegNode::out_RegMask() const { return (INT_FLAGS_mask()); }
629const RegMask &compUL_rReg_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
630const RegMask &compUL_rReg_memNode::out_RegMask() const { return (INT_FLAGS_mask()); }
631const RegMask &testUL_regNode::out_RegMask() const { return (INT_FLAGS_mask()); }
632const RegMask &compB_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
633const RegMask &testUB_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
634const RegMask &testB_mem_immNode::out_RegMask() const { return (INT_FLAGS_mask()); }
635const RegMask &cmovI_reg_gNode::out_RegMask() const { return (INT_REG_mask()); }
636const RegMask &minI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
637const RegMask &cmovI_reg_lNode::out_RegMask() const { return (INT_REG_mask()); }
638const RegMask &maxI_rRegNode::out_RegMask() const { return (INT_REG_mask()); }
639const RegMask &jmpDirNode::out_RegMask() const { return (RegMask::Empty); }
640const RegMask &jmpConNode::out_RegMask() const { return (RegMask::Empty); }
641const RegMask &jmpLoopEndNode::out_RegMask() const { return (RegMask::Empty); }
642const RegMask &jmpLoopEndUNode::out_RegMask() const { return (RegMask::Empty); }
643const RegMask &jmpLoopEndUCFNode::out_RegMask() const { return (RegMask::Empty); }
644const RegMask &jmpLoopEnd_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
645const RegMask &jmpLoopEndU_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
646const RegMask &jmpLoopEndUCF_and_restoreMaskNode::out_RegMask() const { return (RegMask::Empty); }
647const RegMask &jmpConUNode::out_RegMask() const { return (RegMask::Empty); }
648const RegMask &jmpConUCFNode::out_RegMask() const { return (RegMask::Empty); }
649const RegMask &jmpConUCF2Node::out_RegMask() const { return (RegMask::Empty); }
650const RegMask &partialSubtypeCheckNode::out_RegMask() const { return (PTR_RDI_REG_mask()); }
651const RegMask &partialSubtypeCheck_vs_ZeroNode::out_RegMask() const { return (INT_FLAGS_mask()); }
652const RegMask &jmpDir_shortNode::out_RegMask() const { return (RegMask::Empty); }
653const RegMask &jmpCon_shortNode::out_RegMask() const { return (RegMask::Empty); }
654const RegMask &jmpLoopEnd_shortNode::out_RegMask() const { return (RegMask::Empty); }
655const RegMask &jmpLoopEndU_shortNode::out_RegMask() const { return (RegMask::Empty); }
656const RegMask &jmpLoopEndUCF_shortNode::out_RegMask() const { return (RegMask::Empty); }
657const RegMask &jmpConU_shortNode::out_RegMask() const { return (RegMask::Empty); }
658const RegMask &jmpConUCF_shortNode::out_RegMask() const { return (RegMask::Empty); }
659const RegMask &jmpConUCF2_shortNode::out_RegMask() const { return (RegMask::Empty); }
660const RegMask &cmpFastLockRTMNode::out_RegMask() const { return (INT_FLAGS_mask()); }
661const RegMask &cmpFastLockNode::out_RegMask() const { return (INT_FLAGS_mask()); }
662const RegMask &cmpFastUnlockNode::out_RegMask() const { return (INT_FLAGS_mask()); }
663const RegMask &safePoint_pollNode::out_RegMask() const { return (RegMask::Empty); }
664const RegMask &safePoint_poll_farNode::out_RegMask() const { return (RegMask::Empty); }
665const RegMask &safePoint_poll_tlsNode::out_RegMask() const { return (RegMask::Empty); }
666const RegMask &CallStaticJavaDirectNode::out_RegMask() const { return (RegMask::Empty); }
667const RegMask &CallDynamicJavaDirectNode::out_RegMask() const { return (RegMask::Empty); }
668const RegMask &CallRuntimeDirectNode::out_RegMask() const { return (RegMask::Empty); }
669const RegMask &CallLeafDirectNode::out_RegMask() const { return (RegMask::Empty); }
670const RegMask &CallLeafNoFPDirectNode::out_RegMask() const { return (RegMask::Empty); }
671const RegMask &RetNode::out_RegMask() const { return (RegMask::Empty); }
672const RegMask &TailCalljmpIndNode::out_RegMask() const { return (RegMask::Empty); }
673const RegMask &tailjmpIndNode::out_RegMask() const { return (RegMask::Empty); }
674const RegMask &CreateExceptionNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
675const RegMask &RethrowExceptionNode::out_RegMask() const { return (RegMask::Empty); }
676const RegMask &tlsLoadPNode::out_RegMask() const { return (PTR_R15_REG_mask()); }
677const RegMask &ShouldNotReachHereNode::out_RegMask() const { return (RegMask::Empty); }
678const RegMask &setMaskNode::out_RegMask() const { return (INT_REG_mask()); }
679const RegMask &addF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
680const RegMask &addF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
681const RegMask &addF_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
682const RegMask &addF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
683const RegMask &addF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
684const RegMask &addF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
685const RegMask &addF_reg_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
686const RegMask &addF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
687const RegMask &addD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
688const RegMask &addD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
689const RegMask &addD_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
690const RegMask &addD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
691const RegMask &addD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
692const RegMask &addD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
693const RegMask &addD_reg_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
694const RegMask &addD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
695const RegMask &subF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
696const RegMask &subF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
697const RegMask &subF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
698const RegMask &subF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
699const RegMask &subF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
700const RegMask &subF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
701const RegMask &subD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
702const RegMask &subD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
703const RegMask &subD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
704const RegMask &subD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
705const RegMask &subD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
706const RegMask &subD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
707const RegMask &mulF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
708const RegMask &mulF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
709const RegMask &mulF_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
710const RegMask &mulF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
711const RegMask &mulF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
712const RegMask &mulF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
713const RegMask &mulF_reg_mem_0Node::out_RegMask() const { return (FLOAT_REG_mask()); }
714const RegMask &mulF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
715const RegMask &mulD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
716const RegMask &mulD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
717const RegMask &mulD_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
718const RegMask &mulD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
719const RegMask &mulD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
720const RegMask &mulD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
721const RegMask &mulD_reg_mem_0Node::out_RegMask() const { return (DOUBLE_REG_mask()); }
722const RegMask &mulD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
723const RegMask &divF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
724const RegMask &divF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
725const RegMask &divF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
726const RegMask &divF_reg_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
727const RegMask &divF_reg_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
728const RegMask &divF_reg_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
729const RegMask &divD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
730const RegMask &divD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
731const RegMask &divD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
732const RegMask &divD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
733const RegMask &divD_reg_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
734const RegMask &divD_reg_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
735const RegMask &absF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
736const RegMask &absF_reg_regNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
737const RegMask &absD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
738const RegMask &absD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
739const RegMask &negF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
740const RegMask &negF_reg_regNode::out_RegMask() const { return (FLOAT_REG_VL_mask()); }
741const RegMask &negD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
742const RegMask &negD_reg_regNode::out_RegMask() const { return (DOUBLE_REG_VL_mask()); }
743const RegMask &sqrtF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
744const RegMask &sqrtF_memNode::out_RegMask() const { return (FLOAT_REG_mask()); }
745const RegMask &sqrtF_immNode::out_RegMask() const { return (FLOAT_REG_mask()); }
746const RegMask &sqrtD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
747const RegMask &sqrtD_memNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
748const RegMask &sqrtD_immNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
749const RegMask &onspinwaitNode::out_RegMask() const { return (RegMask::Empty); }
750const RegMask &fmaD_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
751const RegMask &fmaF_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
752const RegMask &loadV4Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
753const RegMask &MoveVecS2LegNode::out_RegMask() const { return (VECTORS_REG_LEGACY_mask()); }
754const RegMask &MoveLeg2VecSNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
755const RegMask &loadV8Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
756const RegMask &MoveVecD2LegNode::out_RegMask() const { return (VECTORD_REG_LEGACY_mask()); }
757const RegMask &MoveLeg2VecDNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
758const RegMask &loadV16Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
759const RegMask &MoveVecX2LegNode::out_RegMask() const { return (VECTORX_REG_LEGACY_mask()); }
760const RegMask &MoveLeg2VecXNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
761const RegMask &loadV32Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
762const RegMask &MoveVecY2LegNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
763const RegMask &MoveLeg2VecYNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
764const RegMask &loadV64_dwordNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
765const RegMask &loadV64_qwordNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
766const RegMask &MoveVecZ2LegNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
767const RegMask &MoveLeg2VecZNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
768const RegMask &storeV4Node::out_RegMask() const { return (RegMask::Empty); }
769const RegMask &storeV8Node::out_RegMask() const { return (RegMask::Empty); }
770const RegMask &storeV16Node::out_RegMask() const { return (RegMask::Empty); }
771const RegMask &storeV32Node::out_RegMask() const { return (RegMask::Empty); }
772const RegMask &storeV64_dwordNode::out_RegMask() const { return (RegMask::Empty); }
773const RegMask &storeV64_qwordNode::out_RegMask() const { return (RegMask::Empty); }
774const RegMask &Repl16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
775const RegMask &Repl32BNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
776const RegMask &Repl64BNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
777const RegMask &Repl16B_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
778const RegMask &Repl32B_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
779const RegMask &Repl64B_immNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
780const RegMask &Repl4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
781const RegMask &Repl4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
782const RegMask &Repl8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
783const RegMask &Repl8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
784const RegMask &Repl8S_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
785const RegMask &Repl16SNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
786const RegMask &Repl16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
787const RegMask &Repl16S_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
788const RegMask &Repl32SNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
789const RegMask &Repl32S_memNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
790const RegMask &Repl32S_immNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
791const RegMask &Repl4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
792const RegMask &Repl4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
793const RegMask &Repl8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
794const RegMask &Repl8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
795const RegMask &Repl16INode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
796const RegMask &Repl16I_memNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
797const RegMask &Repl4I_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
798const RegMask &Repl8I_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
799const RegMask &Repl16I_immNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
800const RegMask &Repl2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
801const RegMask &Repl4LNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
802const RegMask &Repl8LNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
803const RegMask &Repl4L_immNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
804const RegMask &Repl8L_immNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
805const RegMask &Repl4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
806const RegMask &Repl8L_memNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
807const RegMask &Repl2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
808const RegMask &Repl4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
809const RegMask &Repl8FNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
810const RegMask &Repl8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
811const RegMask &Repl16FNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
812const RegMask &Repl16F_memNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
813const RegMask &Repl2F_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
814const RegMask &Repl4F_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
815const RegMask &Repl8F_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
816const RegMask &Repl2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
817const RegMask &Repl4DNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
818const RegMask &Repl4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
819const RegMask &Repl8DNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
820const RegMask &Repl8D_memNode::out_RegMask() const { return (VECTORZ_REG_VL_mask()); }
821const RegMask &Repl2D_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
822const RegMask &Repl4D_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
823const RegMask &Repl4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
824const RegMask &Repl8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
825const RegMask &Repl4B_immNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
826const RegMask &Repl8B_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
827const RegMask &Repl4B_zeroNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
828const RegMask &Repl8B_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
829const RegMask &Repl16B_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
830const RegMask &Repl32B_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
831const RegMask &Repl2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
832const RegMask &Repl2S_immNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
833const RegMask &Repl4S_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
834const RegMask &Repl2S_zeroNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
835const RegMask &Repl4S_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
836const RegMask &Repl8S_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
837const RegMask &Repl16S_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
838const RegMask &Repl2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
839const RegMask &Repl2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
840const RegMask &Repl2I_immNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
841const RegMask &Repl2I_zeroNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
842const RegMask &Repl4I_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
843const RegMask &Repl8I_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
844const RegMask &Repl2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
845const RegMask &Repl2L_immNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
846const RegMask &Repl2L_zeroNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
847const RegMask &Repl4L_zeroNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
848const RegMask &Repl2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
849const RegMask &Repl4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
850const RegMask &Repl2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
851const RegMask &Repl4B_mem_evexNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
852const RegMask &Repl8B_mem_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
853const RegMask &Repl16B_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
854const RegMask &Repl16B_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
855const RegMask &Repl32B_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
856const RegMask &Repl32B_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
857const RegMask &Repl64B_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
858const RegMask &Repl64B_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
859const RegMask &Repl16B_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
860const RegMask &Repl32B_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
861const RegMask &Repl64B_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
862const RegMask &Repl64B_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
863const RegMask &Repl4S_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
864const RegMask &Repl4S_mem_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
865const RegMask &Repl8S_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
866const RegMask &Repl8S_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
867const RegMask &Repl16S_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
868const RegMask &Repl16S_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
869const RegMask &Repl32S_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
870const RegMask &Repl32S_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
871const RegMask &Repl8S_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
872const RegMask &Repl16S_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
873const RegMask &Repl32S_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
874const RegMask &Repl32S_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
875const RegMask &Repl4I_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
876const RegMask &Repl4I_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
877const RegMask &Repl8I_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
878const RegMask &Repl8I_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
879const RegMask &Repl16I_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
880const RegMask &Repl16I_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
881const RegMask &Repl4I_imm_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
882const RegMask &Repl8I_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
883const RegMask &Repl16I_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
884const RegMask &Repl16I_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
885const RegMask &Repl4L_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
886const RegMask &Repl8L_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
887const RegMask &Repl4L_imm_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
888const RegMask &Repl8L_imm_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
889const RegMask &Repl2L_mem_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
890const RegMask &Repl4L_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
891const RegMask &Repl8L_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
892const RegMask &Repl8L_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
893const RegMask &Repl8F_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
894const RegMask &Repl8F_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
895const RegMask &Repl16F_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
896const RegMask &Repl16F_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
897const RegMask &Repl2F_zero_evexNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
898const RegMask &Repl4F_zero_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
899const RegMask &Repl8F_zero_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
900const RegMask &Repl16F_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
901const RegMask &Repl4D_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
902const RegMask &Repl4D_mem_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
903const RegMask &Repl8D_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
904const RegMask &Repl8D_mem_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
905const RegMask &Repl2D_zero_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
906const RegMask &Repl4D_zero_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
907const RegMask &Repl8D_zero_evexNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
908const RegMask &rsadd2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
909const RegMask &rvadd2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
910const RegMask &rvadd2I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
911const RegMask &rsadd4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
912const RegMask &rvadd4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
913const RegMask &rvadd4I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
914const RegMask &rvadd8I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
915const RegMask &rvadd8I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
916const RegMask &rvadd16I_reduction_reg_evexNode::out_RegMask() const { return (INT_REG_mask()); }
917const RegMask &rvadd2L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
918const RegMask &rvadd4L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
919const RegMask &rvadd8L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
920const RegMask &rsadd2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
921const RegMask &rvadd2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
922const RegMask &rsadd4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
923const RegMask &rvadd4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
924const RegMask &radd8F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
925const RegMask &radd16F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
926const RegMask &rsadd2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
927const RegMask &rvadd2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
928const RegMask &rvadd4D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
929const RegMask &rvadd8D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
930const RegMask &rsmul2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
931const RegMask &rvmul2I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
932const RegMask &rsmul4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
933const RegMask &rvmul4I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
934const RegMask &rvmul8I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
935const RegMask &rvmul16I_reduction_regNode::out_RegMask() const { return (INT_REG_mask()); }
936const RegMask &rvmul2L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
937const RegMask &rvmul4L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
938const RegMask &rvmul8L_reduction_regNode::out_RegMask() const { return (LONG_REG_mask()); }
939const RegMask &rsmul2F_reductionNode::out_RegMask() const { return (FLOAT_REG_mask()); }
940const RegMask &rvmul2F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
941const RegMask &rsmul4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
942const RegMask &rvmul4F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
943const RegMask &rvmul8F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
944const RegMask &rvmul16F_reduction_regNode::out_RegMask() const { return (FLOAT_REG_mask()); }
945const RegMask &rsmul2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
946const RegMask &rvmul2D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
947const RegMask &rvmul4D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
948const RegMask &rvmul8D_reduction_regNode::out_RegMask() const { return (DOUBLE_REG_mask()); }
949const RegMask &vadd4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
950const RegMask &vadd4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
951const RegMask &vadd4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
952const RegMask &vadd4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
953const RegMask &vadd8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
954const RegMask &vadd8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
955const RegMask &vadd8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
956const RegMask &vadd8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
957const RegMask &vadd16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
958const RegMask &vadd16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
959const RegMask &vadd16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
960const RegMask &vadd16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
961const RegMask &vadd32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
962const RegMask &vadd32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
963const RegMask &vadd32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
964const RegMask &vadd64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
965const RegMask &vadd64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
966const RegMask &vadd64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
967const RegMask &vadd2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
968const RegMask &vadd2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
969const RegMask &vadd2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
970const RegMask &vadd2S_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
971const RegMask &vadd4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
972const RegMask &vadd4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
973const RegMask &vadd4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
974const RegMask &vadd4S_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
975const RegMask &vadd8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
976const RegMask &vadd8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
977const RegMask &vadd8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
978const RegMask &vadd8S_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
979const RegMask &vadd16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
980const RegMask &vadd16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
981const RegMask &vadd16S_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
982const RegMask &vadd32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
983const RegMask &vadd32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
984const RegMask &vadd32S_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
985const RegMask &vadd2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
986const RegMask &vadd2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
987const RegMask &vadd2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
988const RegMask &vadd2I_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
989const RegMask &vadd4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
990const RegMask &vadd4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
991const RegMask &vadd4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
992const RegMask &vadd4I_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
993const RegMask &vadd8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
994const RegMask &vadd8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
995const RegMask &vadd8I_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
996const RegMask &vadd16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
997const RegMask &vadd16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
998const RegMask &vadd16I_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
999const RegMask &vadd2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1000const RegMask &vadd2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1001const RegMask &vadd2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1002const RegMask &vadd2L_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1003const RegMask &vadd4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1004const RegMask &vadd4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1005const RegMask &vadd4L_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1006const RegMask &vadd8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1007const RegMask &vadd8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1008const RegMask &vadd8L_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1009const RegMask &vadd2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1010const RegMask &vadd2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1011const RegMask &vadd2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1012const RegMask &vadd2F_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1013const RegMask &vadd4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1014const RegMask &vadd4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1015const RegMask &vadd4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1016const RegMask &vadd4F_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1017const RegMask &vadd8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1018const RegMask &vadd8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1019const RegMask &vadd8F_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1020const RegMask &vadd16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1021const RegMask &vadd16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1022const RegMask &vadd16F_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1023const RegMask &vadd2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1024const RegMask &vadd2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1025const RegMask &vadd2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1026const RegMask &vadd2D_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1027const RegMask &vadd4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1028const RegMask &vadd4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1029const RegMask &vadd4D_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1030const RegMask &vadd8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1031const RegMask &vadd8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1032const RegMask &vadd8D_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1033const RegMask &vsub4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1034const RegMask &vsub4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1035const RegMask &vsub4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1036const RegMask &vsub8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1037const RegMask &vsub8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1038const RegMask &vsub8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1039const RegMask &vsub16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1040const RegMask &vsub16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1041const RegMask &vsub16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1042const RegMask &vsub32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1043const RegMask &vsub32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1044const RegMask &vsub64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1045const RegMask &vsub64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1046const RegMask &vsub2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1047const RegMask &vsub2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1048const RegMask &vsub2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1049const RegMask &vsub4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1050const RegMask &vsub4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1051const RegMask &vsub4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1052const RegMask &vsub8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1053const RegMask &vsub8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1054const RegMask &vsub8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1055const RegMask &vsub16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1056const RegMask &vsub16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1057const RegMask &vsub32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1058const RegMask &vsub32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1059const RegMask &vsub2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1060const RegMask &vsub2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1061const RegMask &vsub2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1062const RegMask &vsub4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1063const RegMask &vsub4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1064const RegMask &vsub4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1065const RegMask &vsub8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1066const RegMask &vsub8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1067const RegMask &vsub16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1068const RegMask &vsub16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1069const RegMask &vsub2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1070const RegMask &vsub2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1071const RegMask &vsub2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1072const RegMask &vsub4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1073const RegMask &vsub4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1074const RegMask &vsub8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1075const RegMask &vsub8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1076const RegMask &vsub2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1077const RegMask &vsub2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1078const RegMask &vsub2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1079const RegMask &vsub4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1080const RegMask &vsub4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1081const RegMask &vsub4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1082const RegMask &vsub8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1083const RegMask &vsub8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1084const RegMask &vsub16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1085const RegMask &vsub16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1086const RegMask &vsub2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1087const RegMask &vsub2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1088const RegMask &vsub2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1089const RegMask &vsub4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1090const RegMask &vsub4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1091const RegMask &vsub8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1092const RegMask &vsub8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1093const RegMask &mul4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1094const RegMask &mul8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1095const RegMask &mul16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1096const RegMask &vmul16B_reg_avxNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1097const RegMask &vmul32B_reg_avxNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1098const RegMask &vmul64B_reg_avxNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1099const RegMask &vmul2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1100const RegMask &vmul2S_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1101const RegMask &vmul2S_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1102const RegMask &vmul2S_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1103const RegMask &vmul4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1104const RegMask &vmul4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1105const RegMask &vmul4S_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1106const RegMask &vmul4S_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1107const RegMask &vmul8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1108const RegMask &vmul8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1109const RegMask &vmul8S_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1110const RegMask &vmul8S_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1111const RegMask &vmul16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1112const RegMask &vmul16S_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1113const RegMask &vmul16S_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1114const RegMask &vmul32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1115const RegMask &vmul32S_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1116const RegMask &vmul32S_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1117const RegMask &vmul2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1118const RegMask &vmul2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1119const RegMask &vmul2I_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1120const RegMask &vmul2I_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1121const RegMask &vmul4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1122const RegMask &vmul4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1123const RegMask &vmul4I_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1124const RegMask &vmul4I_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1125const RegMask &vmul2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1126const RegMask &vmul2L_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1127const RegMask &vmul2L_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1128const RegMask &vmul4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1129const RegMask &vmul4L_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1130const RegMask &vmul4L_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1131const RegMask &vmul8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1132const RegMask &vmul8L_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1133const RegMask &vmul8L_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1134const RegMask &vmul8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1135const RegMask &vmul8I_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1136const RegMask &vmul8I_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1137const RegMask &vmul16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1138const RegMask &vmul16I_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1139const RegMask &vmul16I_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1140const RegMask &vmul2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1141const RegMask &vmul2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1142const RegMask &vmul2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1143const RegMask &vmul2F_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1144const RegMask &vmul4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1145const RegMask &vmul4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1146const RegMask &vmul4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1147const RegMask &vmul4F_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1148const RegMask &vmul8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1149const RegMask &vmul8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1150const RegMask &vmul8F_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1151const RegMask &vmul16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1152const RegMask &vmul16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1153const RegMask &vmul16F_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1154const RegMask &vmul2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1155const RegMask &vmul2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1156const RegMask &vmul2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1157const RegMask &vmul2D_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1158const RegMask &vmul4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1159const RegMask &vmul4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1160const RegMask &vmul4D_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1161const RegMask &vmul8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1162const RegMask &vmul8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1163const RegMask &vmul8D_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1164const RegMask &vcmov8F_regNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
1165const RegMask &vcmov4D_regNode::out_RegMask() const { return (VECTORY_REG_LEGACY_mask()); }
1166const RegMask &vdiv2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1167const RegMask &vdiv2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1168const RegMask &vdiv2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1169const RegMask &vdiv4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1170const RegMask &vdiv4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1171const RegMask &vdiv4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1172const RegMask &vdiv8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1173const RegMask &vdiv8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1174const RegMask &vdiv16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1175const RegMask &vdiv16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1176const RegMask &vdiv2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1177const RegMask &vdiv2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1178const RegMask &vdiv2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1179const RegMask &vdiv4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1180const RegMask &vdiv4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1181const RegMask &vdiv8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1182const RegMask &vdiv8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1183const RegMask &vsqrt2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1184const RegMask &vsqrt2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1185const RegMask &vsqrt4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1186const RegMask &vsqrt4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1187const RegMask &vsqrt8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1188const RegMask &vsqrt8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1189const RegMask &vsqrt2F_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1190const RegMask &vsqrt2F_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1191const RegMask &vsqrt4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1192const RegMask &vsqrt4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1193const RegMask &vsqrt8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1194const RegMask &vsqrt8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1195const RegMask &vsqrt16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1196const RegMask &vsqrt16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1197const RegMask &vshiftcntNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1198const RegMask &vshiftcnt_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1199const RegMask &vshiftcntimmNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1200const RegMask &vshift4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1201const RegMask &vshift4B_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1202const RegMask &vshift4B_1Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1203const RegMask &vshift8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1204const RegMask &vshift8B_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1205const RegMask &vshift8B_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1206const RegMask &vshift16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1207const RegMask &vshift16B_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1208const RegMask &vshift16B_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1209const RegMask &vshift16B_avxNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1210const RegMask &vshift16B_avx_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1211const RegMask &vshift16B_avx_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1212const RegMask &vshift32B_avxNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1213const RegMask &vshift32B_avx_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1214const RegMask &vshift32B_avx_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1215const RegMask &vshift64B_avxNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1216const RegMask &vshift64B_avx_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1217const RegMask &vshift64B_avx_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1218const RegMask &vshist2SNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1219const RegMask &vshist2S_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1220const RegMask &vshist2S_1Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1221const RegMask &vshift4SNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1222const RegMask &vshift4S_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1223const RegMask &vshift4S_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1224const RegMask &vshift8SNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1225const RegMask &vshift8S_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1226const RegMask &vshift8S_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1227const RegMask &vshift16SNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1228const RegMask &vshift16S_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1229const RegMask &vshift16S_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1230const RegMask &vshift32SNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1231const RegMask &vshift32S_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1232const RegMask &vshift32S_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1233const RegMask &vshift2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1234const RegMask &vshift2I_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1235const RegMask &vshift2I_1Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1236const RegMask &vshift4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1237const RegMask &vshift4I_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1238const RegMask &vshift4I_1Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1239const RegMask &vshift8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1240const RegMask &vshift8I_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1241const RegMask &vshift8I_1Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1242const RegMask &vshift16INode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1243const RegMask &vshift16I_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1244const RegMask &vshift16I_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1245const RegMask &vshift2LNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1246const RegMask &vshift2L_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1247const RegMask &vshift4LNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1248const RegMask &vshift4L_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1249const RegMask &vshift8LNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1250const RegMask &vshift8L_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1251const RegMask &vshift8L_1Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1252const RegMask &vsra2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1253const RegMask &vsra2L_reg_evexNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1254const RegMask &vsra4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1255const RegMask &vsra4L_reg_evexNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1256const RegMask &vand4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1257const RegMask &vand4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1258const RegMask &vand4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1259const RegMask &vand4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1260const RegMask &vand8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1261const RegMask &vand8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1262const RegMask &vand8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1263const RegMask &vand8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1264const RegMask &vand16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1265const RegMask &vand16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1266const RegMask &vand16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1267const RegMask &vand16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1268const RegMask &vand32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1269const RegMask &vand32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1270const RegMask &vand32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1271const RegMask &vand64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1272const RegMask &vand64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1273const RegMask &vand64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1274const RegMask &vor4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1275const RegMask &vor4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1276const RegMask &vor4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1277const RegMask &vor4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1278const RegMask &vor8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1279const RegMask &vor8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1280const RegMask &vor8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1281const RegMask &vor8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1282const RegMask &vor16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1283const RegMask &vor16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1284const RegMask &vor16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1285const RegMask &vor16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1286const RegMask &vor32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1287const RegMask &vor32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1288const RegMask &vor32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1289const RegMask &vor64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1290const RegMask &vor64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1291const RegMask &vor64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1292const RegMask &vxor4BNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1293const RegMask &vxor4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1294const RegMask &vxor4B_memNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1295const RegMask &vxor4B_mem_0Node::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1296const RegMask &vxor8BNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1297const RegMask &vxor8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1298const RegMask &vxor8B_memNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1299const RegMask &vxor8B_mem_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1300const RegMask &vxor16BNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1301const RegMask &vxor16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1302const RegMask &vxor16B_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1303const RegMask &vxor16B_mem_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1304const RegMask &vxor32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1305const RegMask &vxor32B_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1306const RegMask &vxor32B_mem_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1307const RegMask &vxor64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1308const RegMask &vxor64B_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1309const RegMask &vxor64B_mem_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1310const RegMask &vabs4B_regNode::out_RegMask() const { return (VECTORS_REG_VLBWDQ_mask()); }
1311const RegMask &vabs8B_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1312const RegMask &vabs16B_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1313const RegMask &vabs32B_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1314const RegMask &vabs64B_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1315const RegMask &vabs2S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1316const RegMask &vabs4S_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1317const RegMask &vabs8S_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1318const RegMask &vabs16S_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1319const RegMask &vabs32S_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1320const RegMask &vabs2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1321const RegMask &vabs4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1322const RegMask &vabs8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1323const RegMask &vabs16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1324const RegMask &vabs2L_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1325const RegMask &vabs4L_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1326const RegMask &vabs8L_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1327const RegMask &vabsneg2DNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1328const RegMask &vabsneg2D_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1329const RegMask &vabsneg4DNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1330const RegMask &vabsneg4D_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1331const RegMask &vabsneg8DNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1332const RegMask &vabsneg8D_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1333const RegMask &vabsneg2FNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1334const RegMask &vabsneg2F_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1335const RegMask &vabsneg4FNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1336const RegMask &vabsneg4F_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1337const RegMask &vabsneg8FNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1338const RegMask &vabsneg8F_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1339const RegMask &vabsneg16FNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1340const RegMask &vabsneg16F_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1341const RegMask &vfma2D_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1342const RegMask &vfma2D_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1343const RegMask &vfma4D_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1344const RegMask &vfma4D_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1345const RegMask &vfma8D_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1346const RegMask &vfma8D_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1347const RegMask &vfma4F_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1348const RegMask &vfma4F_memNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1349const RegMask &vfma8F_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1350const RegMask &vfma8F_memNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1351const RegMask &vfma16F_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1352const RegMask &vfma16F_memNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1353const RegMask &smuladd4S2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1354const RegMask &vmuladd4S2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1355const RegMask &smuladd8S4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1356const RegMask &vmuladd8S4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1357const RegMask &vmuladd16S8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1358const RegMask &vmuladd32S16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1359const RegMask &vmuladdadd4S2I_regNode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1360const RegMask &vmuladdadd4S2I_reg_0Node::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1361const RegMask &vmuladdadd8S4I_regNode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1362const RegMask &vmuladdadd8S4I_reg_0Node::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1363const RegMask &vmuladdadd16S8I_regNode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1364const RegMask &vmuladdadd16S8I_reg_0Node::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1365const RegMask &vmuladdadd32S16I_regNode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1366const RegMask &vmuladdadd32S16I_reg_0Node::out_RegMask() const { return (VECTORZ_REG_mask()); }
1367const RegMask &vpopcount2INode::out_RegMask() const { return (VECTORD_REG_VLBWDQ_mask()); }
1368const RegMask &vpopcount4INode::out_RegMask() const { return (VECTORX_REG_VLBWDQ_mask()); }
1369const RegMask &vpopcount8INode::out_RegMask() const { return (VECTORY_REG_VLBWDQ_mask()); }
1370const RegMask &vpopcount16INode::out_RegMask() const { return (VECTORZ_REG_mask()); }
1371const RegMask &compareAndSwapP_shenandoahNode::out_RegMask() const { return (INT_REG_mask()); }
1372const RegMask &compareAndSwapP_shenandoah_0Node::out_RegMask() const { return (INT_REG_mask()); }
1373const RegMask &compareAndSwapN_shenandoahNode::out_RegMask() const { return (INT_REG_mask()); }
1374const RegMask &compareAndSwapN_shenandoah_0Node::out_RegMask() const { return (INT_REG_mask()); }
1375const RegMask &compareAndExchangeN_shenandoahNode::out_RegMask() const { return (INT_RAX_REG_mask()); }
1376const RegMask &compareAndExchangeP_shenandoahNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
1377const RegMask &zLoadBarrierSlowRegXmmAndYmmNode::out_RegMask() const { return (PTR_REG_mask()); }
1378const RegMask &zLoadBarrierSlowRegZmmNode::out_RegMask() const { return (PTR_REG_mask()); }
1379const RegMask &zLoadBarrierWeakSlowRegXmmAndYmmNode::out_RegMask() const { return (PTR_REG_mask()); }
1380const RegMask &zLoadBarrierWeakSlowRegZmmNode::out_RegMask() const { return (PTR_REG_mask()); }
1381const RegMask &z_compareAndExchangePNode::out_RegMask() const { return (PTR_RAX_REG_mask()); }
1382const RegMask &z_compareAndSwapPNode::out_RegMask() const { return (INT_REG_mask()); }
1383const RegMask &z_compareAndSwapP_0Node::out_RegMask() const { return (INT_REG_mask()); }
1384const RegMask &z_xchgPNode::out_RegMask() const { return (PTR_REG_mask()); }
1385// Check consistency of C++ compilation with ADLC options:
1386// Check adlc -DLINUX=1
1387#ifndef LINUX
1388# error "LINUX must be defined"
1389#endif // LINUX
1390// Check adlc -D_GNU_SOURCE=1
1391#ifndef _GNU_SOURCE
1392# error "_GNU_SOURCE must be defined"
1393#endif // _GNU_SOURCE
1394// Check adlc -DAMD64=1
1395#ifndef AMD64
1396# error "AMD64 must be defined"
1397#endif // AMD64
1398// Check adlc -D_LP64=1
1399#ifndef _LP64
1400# error "_LP64 must be defined"
1401#endif // _LP64
1402