1/* This file is autogenerated by scripts/decodetree.py. */
2
3typedef struct {
4 int A;
5 int F;
6 int I;
7 int M;
8 int imod;
9 int mode;
10} arg_cps;
11
12typedef struct {
13 int pu;
14 int rn;
15 int w;
16} arg_rfe;
17
18typedef struct {
19 int E;
20} arg_setend;
21
22typedef struct {
23 int mode;
24 int pu;
25 int w;
26} arg_srs;
27
28#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
29# pragma GCC diagnostic push
30# pragma GCC diagnostic ignored "-Wredundant-decls"
31# ifdef __clang__
32# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
33# endif
34#endif
35
36typedef arg_i arg_BLX_i;
37static bool trans_BLX_i(DisasContext *ctx, arg_BLX_i *a);
38typedef arg_rfe arg_RFE;
39static bool trans_RFE(DisasContext *ctx, arg_RFE *a);
40typedef arg_srs arg_SRS;
41static bool trans_SRS(DisasContext *ctx, arg_SRS *a);
42typedef arg_cps arg_CPS;
43static bool trans_CPS(DisasContext *ctx, arg_CPS *a);
44typedef arg_empty arg_CLREX;
45static bool trans_CLREX(DisasContext *ctx, arg_CLREX *a);
46typedef arg_empty arg_DSB;
47static bool trans_DSB(DisasContext *ctx, arg_DSB *a);
48typedef arg_empty arg_DMB;
49static bool trans_DMB(DisasContext *ctx, arg_DMB *a);
50typedef arg_empty arg_ISB;
51static bool trans_ISB(DisasContext *ctx, arg_ISB *a);
52typedef arg_empty arg_SB;
53static bool trans_SB(DisasContext *ctx, arg_SB *a);
54typedef arg_setend arg_SETEND;
55static bool trans_SETEND(DisasContext *ctx, arg_SETEND *a);
56typedef arg_empty arg_PLD;
57static bool trans_PLD(DisasContext *ctx, arg_PLD *a);
58typedef arg_empty arg_PLDW;
59static bool trans_PLDW(DisasContext *ctx, arg_PLDW *a);
60typedef arg_empty arg_PLI;
61static bool trans_PLI(DisasContext *ctx, arg_PLI *a);
62
63#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
64# pragma GCC diagnostic pop
65#endif
66
67static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_0(DisasContext *ctx, arg_i *a, uint32_t insn)
68{
69 a->imm = times_2(ctx, deposit32(extract32(insn, 24, 1), 1, 31, sextract32(insn, 0, 24)));
70}
71
72static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_1(DisasContext *ctx, arg_rfe *a, uint32_t insn)
73{
74 a->pu = extract32(insn, 23, 2);
75 a->w = extract32(insn, 21, 1);
76 a->rn = extract32(insn, 16, 4);
77}
78
79static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_2(DisasContext *ctx, arg_srs *a, uint32_t insn)
80{
81 a->pu = extract32(insn, 23, 2);
82 a->w = extract32(insn, 21, 1);
83 a->mode = extract32(insn, 0, 5);
84}
85
86static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_3(DisasContext *ctx, arg_cps *a, uint32_t insn)
87{
88 a->imod = extract32(insn, 18, 2);
89 a->M = extract32(insn, 17, 1);
90 a->A = extract32(insn, 8, 1);
91 a->I = extract32(insn, 7, 1);
92 a->F = extract32(insn, 6, 1);
93 a->mode = extract32(insn, 0, 5);
94}
95
96static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_4(DisasContext *ctx, arg_empty *a, uint32_t insn)
97{
98}
99
100static void disas_a32_uncond_extract_disas_a32_uncond_Fmt_5(DisasContext *ctx, arg_setend *a, uint32_t insn)
101{
102 a->E = extract32(insn, 9, 1);
103}
104
105static bool disas_a32_uncond(DisasContext *ctx, uint32_t insn)
106{
107 union {
108 arg_cps f_cps;
109 arg_empty f_empty;
110 arg_i f_i;
111 arg_rfe f_rfe;
112 arg_setend f_setend;
113 arg_srs f_srs;
114 } u;
115
116 switch ((insn >> 25) & 0x7f) {
117 case 0x78:
118 /* 1111000. ........ ........ ........ */
119 switch (insn & 0x01f1fc20) {
120 case 0x01000000:
121 /* 11110001 0000...0 000000.. ..0..... */
122 disas_a32_uncond_extract_disas_a32_uncond_Fmt_3(ctx, &u.f_cps, insn);
123 switch ((insn >> 9) & 0x1) {
124 case 0x0:
125 /* 11110001 0000...0 0000000. ..0..... */
126 /* /workspace/qemu/target/arm/a32-uncond.decode:43 */
127 if (trans_CPS(ctx, &u.f_cps)) return true;
128 return false;
129 }
130 return false;
131 case 0x01010000:
132 /* 11110001 0000...1 000000.. ..0..... */
133 disas_a32_uncond_extract_disas_a32_uncond_Fmt_5(ctx, &u.f_setend, insn);
134 switch (insn & 0x000e01df) {
135 case 0x00000000:
136 /* 11110001 00000001 000000.0 00000000 */
137 /* /workspace/qemu/target/arm/a32-uncond.decode:56 */
138 if (trans_SETEND(ctx, &u.f_setend)) return true;
139 return false;
140 }
141 return false;
142 }
143 return false;
144 case 0x7a:
145 /* 1111010. ........ ........ ........ */
146 disas_a32_uncond_extract_disas_a32_uncond_Fmt_4(ctx, &u.f_empty, insn);
147 switch (insn & 0x01700000) {
148 case 0x00100000:
149 /* 11110100 .001.... ........ ........ */
150 /* /workspace/qemu/target/arm/a32-uncond.decode:73 */
151 if (trans_PLDW(ctx, &u.f_empty)) return true;
152 return false;
153 case 0x00500000:
154 /* 11110100 .101.... ........ ........ */
155 switch ((insn >> 12) & 0xf) {
156 case 0xf:
157 /* 11110100 .101.... 1111.... ........ */
158 /* /workspace/qemu/target/arm/a32-uncond.decode:62 */
159 if (trans_PLI(ctx, &u.f_empty)) return true;
160 return false;
161 }
162 return false;
163 case 0x01100000:
164 /* 11110101 .001.... ........ ........ */
165 switch ((insn >> 12) & 0xf) {
166 case 0xf:
167 /* 11110101 .001.... 1111.... ........ */
168 /* /workspace/qemu/target/arm/a32-uncond.decode:61 */
169 if (trans_PLDW(ctx, &u.f_empty)) return true;
170 return false;
171 }
172 return false;
173 case 0x01500000:
174 /* 11110101 .101.... ........ ........ */
175 switch ((insn >> 12) & 0xf) {
176 case 0xf:
177 /* 11110101 .101.... 1111.... ........ */
178 /* /workspace/qemu/target/arm/a32-uncond.decode:60 */
179 if (trans_PLD(ctx, &u.f_empty)) return true;
180 return false;
181 }
182 return false;
183 case 0x01700000:
184 /* 11110101 .111.... ........ ........ */
185 switch (insn & 0x008ffff0) {
186 case 0x000ff010:
187 /* 11110101 01111111 11110000 0001.... */
188 switch (insn & 0x0000000f) {
189 case 0x0000000f:
190 /* 11110101 01111111 11110000 00011111 */
191 /* /workspace/qemu/target/arm/a32-uncond.decode:49 */
192 if (trans_CLREX(ctx, &u.f_empty)) return true;
193 return false;
194 }
195 return false;
196 case 0x000ff040:
197 /* 11110101 01111111 11110000 0100.... */
198 /* /workspace/qemu/target/arm/a32-uncond.decode:50 */
199 if (trans_DSB(ctx, &u.f_empty)) return true;
200 return false;
201 case 0x000ff050:
202 /* 11110101 01111111 11110000 0101.... */
203 /* /workspace/qemu/target/arm/a32-uncond.decode:51 */
204 if (trans_DMB(ctx, &u.f_empty)) return true;
205 return false;
206 case 0x000ff060:
207 /* 11110101 01111111 11110000 0110.... */
208 /* /workspace/qemu/target/arm/a32-uncond.decode:52 */
209 if (trans_ISB(ctx, &u.f_empty)) return true;
210 return false;
211 case 0x000ff070:
212 /* 11110101 01111111 11110000 0111.... */
213 switch (insn & 0x0000000f) {
214 case 0x00000000:
215 /* 11110101 01111111 11110000 01110000 */
216 /* /workspace/qemu/target/arm/a32-uncond.decode:53 */
217 if (trans_SB(ctx, &u.f_empty)) return true;
218 return false;
219 }
220 return false;
221 }
222 return false;
223 }
224 return false;
225 case 0x7b:
226 /* 1111011. ........ ........ ........ */
227 disas_a32_uncond_extract_disas_a32_uncond_Fmt_4(ctx, &u.f_empty, insn);
228 switch (insn & 0x01700010) {
229 case 0x00100000:
230 /* 11110110 .001.... ........ ...0.... */
231 /* /workspace/qemu/target/arm/a32-uncond.decode:74 */
232 if (trans_PLDW(ctx, &u.f_empty)) return true;
233 return false;
234 case 0x00500000:
235 /* 11110110 .101.... ........ ...0.... */
236 switch ((insn >> 12) & 0xf) {
237 case 0xf:
238 /* 11110110 .101.... 1111.... ...0.... */
239 /* /workspace/qemu/target/arm/a32-uncond.decode:66 */
240 if (trans_PLI(ctx, &u.f_empty)) return true;
241 return false;
242 }
243 return false;
244 case 0x01100000:
245 /* 11110111 .001.... ........ ...0.... */
246 switch ((insn >> 12) & 0xf) {
247 case 0xf:
248 /* 11110111 .001.... 1111.... ...0.... */
249 /* /workspace/qemu/target/arm/a32-uncond.decode:65 */
250 if (trans_PLDW(ctx, &u.f_empty)) return true;
251 return false;
252 }
253 return false;
254 case 0x01500000:
255 /* 11110111 .101.... ........ ...0.... */
256 switch ((insn >> 12) & 0xf) {
257 case 0xf:
258 /* 11110111 .101.... 1111.... ...0.... */
259 /* /workspace/qemu/target/arm/a32-uncond.decode:64 */
260 if (trans_PLD(ctx, &u.f_empty)) return true;
261 return false;
262 }
263 return false;
264 }
265 return false;
266 case 0x7c:
267 /* 1111100. ........ ........ ........ */
268 switch (insn & 0x0050ffe0) {
269 case 0x00100a00:
270 /* 1111100. .0.1.... 00001010 000..... */
271 disas_a32_uncond_extract_disas_a32_uncond_Fmt_1(ctx, &u.f_rfe, insn);
272 switch (insn & 0x0000001f) {
273 case 0x00000000:
274 /* 1111100. .0.1.... 00001010 00000000 */
275 /* /workspace/qemu/target/arm/a32-uncond.decode:41 */
276 if (trans_RFE(ctx, &u.f_rfe)) return true;
277 return false;
278 }
279 return false;
280 case 0x00400500:
281 /* 1111100. .1.0.... 00000101 000..... */
282 disas_a32_uncond_extract_disas_a32_uncond_Fmt_2(ctx, &u.f_srs, insn);
283 switch ((insn >> 16) & 0xf) {
284 case 0xd:
285 /* 1111100. .1.01101 00000101 000..... */
286 /* /workspace/qemu/target/arm/a32-uncond.decode:42 */
287 if (trans_SRS(ctx, &u.f_srs)) return true;
288 return false;
289 }
290 return false;
291 }
292 return false;
293 case 0x7d:
294 /* 1111101. ........ ........ ........ */
295 /* /workspace/qemu/target/arm/a32-uncond.decode:33 */
296 disas_a32_uncond_extract_disas_a32_uncond_Fmt_0(ctx, &u.f_i, insn);
297 if (trans_BLX_i(ctx, &u.f_i)) return true;
298 return false;
299 }
300 return false;
301}
302