1 | #ifndef TARGET_ARM_TRANSLATE_H |
2 | #define TARGET_ARM_TRANSLATE_H |
3 | |
4 | #include "exec/translator.h" |
5 | #include "internals.h" |
6 | |
7 | |
8 | /* internal defines */ |
9 | typedef struct DisasContext { |
10 | DisasContextBase base; |
11 | const ARMISARegisters *isar; |
12 | |
13 | /* The address of the current instruction being translated. */ |
14 | target_ulong pc_curr; |
15 | target_ulong page_start; |
16 | uint32_t insn; |
17 | /* Nonzero if this instruction has been conditionally skipped. */ |
18 | int condjmp; |
19 | /* The label that will be jumped to when the instruction is skipped. */ |
20 | TCGLabel *condlabel; |
21 | /* Thumb-2 conditional execution bits. */ |
22 | int condexec_mask; |
23 | int condexec_cond; |
24 | int thumb; |
25 | int sctlr_b; |
26 | MemOp be_data; |
27 | #if !defined(CONFIG_USER_ONLY) |
28 | int user; |
29 | #endif |
30 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ |
31 | uint8_t tbii; /* TBI1|TBI0 for insns */ |
32 | uint8_t tbid; /* TBI1|TBI0 for data */ |
33 | bool ns; /* Use non-secure CPREG bank on access */ |
34 | int fp_excp_el; /* FP exception EL or 0 if enabled */ |
35 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ |
36 | int sve_len; /* SVE vector length in bytes */ |
37 | /* Flag indicating that exceptions from secure mode are routed to EL3. */ |
38 | bool secure_routed_to_el3; |
39 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ |
40 | int vec_len; |
41 | int vec_stride; |
42 | bool v7m_handler_mode; |
43 | bool v8m_secure; /* true if v8M and we're in Secure mode */ |
44 | bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ |
45 | bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ |
46 | bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ |
47 | bool v7m_lspact; /* FPCCR.LSPACT set */ |
48 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI |
49 | * so that top level loop can generate correct syndrome information. |
50 | */ |
51 | uint32_t svc_imm; |
52 | int aarch64; |
53 | int current_el; |
54 | /* Debug target exception level for single-step exceptions */ |
55 | int debug_target_el; |
56 | GHashTable *cp_regs; |
57 | uint64_t features; /* CPU features bits */ |
58 | /* Because unallocated encodings generate different exception syndrome |
59 | * information from traps due to FP being disabled, we can't do a single |
60 | * "is fp access disabled" check at a high level in the decode tree. |
61 | * To help in catching bugs where the access check was forgotten in some |
62 | * code path, we set this flag when the access check is done, and assert |
63 | * that it is set at the point where we actually touch the FP regs. |
64 | */ |
65 | bool fp_access_checked; |
66 | /* ARMv8 single-step state (this is distinct from the QEMU gdbstub |
67 | * single-step support). |
68 | */ |
69 | bool ss_active; |
70 | bool pstate_ss; |
71 | /* True if the insn just emitted was a load-exclusive instruction |
72 | * (necessary for syndrome information for single step exceptions), |
73 | * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. |
74 | */ |
75 | bool is_ldex; |
76 | /* True if v8.3-PAuth is active. */ |
77 | bool pauth_active; |
78 | /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ |
79 | bool bt; |
80 | /* |
81 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. |
82 | * < 0, set by the current instruction. |
83 | */ |
84 | int8_t btype; |
85 | /* True if this page is guarded. */ |
86 | bool guarded_page; |
87 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |
88 | int c15_cpar; |
89 | /* TCG op of the current insn_start. */ |
90 | TCGOp *insn_start; |
91 | #define TMP_A64_MAX 16 |
92 | int tmp_a64_count; |
93 | TCGv_i64 tmp_a64[TMP_A64_MAX]; |
94 | } DisasContext; |
95 | |
96 | typedef struct DisasCompare { |
97 | TCGCond cond; |
98 | TCGv_i32 value; |
99 | bool value_global; |
100 | } DisasCompare; |
101 | |
102 | /* Share the TCG temporaries common between 32 and 64 bit modes. */ |
103 | extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
104 | extern TCGv_i64 cpu_exclusive_addr; |
105 | extern TCGv_i64 cpu_exclusive_val; |
106 | |
107 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
108 | { |
109 | return (dc->features & (1ULL << feature)) != 0; |
110 | } |
111 | |
112 | static inline int get_mem_index(DisasContext *s) |
113 | { |
114 | return arm_to_core_mmu_idx(s->mmu_idx); |
115 | } |
116 | |
117 | /* Function used to determine the target exception EL when otherwise not known |
118 | * or default. |
119 | */ |
120 | static inline int default_exception_el(DisasContext *s) |
121 | { |
122 | /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
123 | * there is no secure EL1, so we route exceptions to EL3. Otherwise, |
124 | * exceptions can only be routed to ELs above 1, so we target the higher of |
125 | * 1 or the current EL. |
126 | */ |
127 | return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) |
128 | ? 3 : MAX(1, s->current_el); |
129 | } |
130 | |
131 | static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) |
132 | { |
133 | /* We don't need to save all of the syndrome so we mask and shift |
134 | * out unneeded bits to help the sleb128 encoder do a better job. |
135 | */ |
136 | syn &= ARM_INSN_START_WORD2_MASK; |
137 | syn >>= ARM_INSN_START_WORD2_SHIFT; |
138 | |
139 | /* We check and clear insn_start_idx to catch multiple updates. */ |
140 | assert(s->insn_start != NULL); |
141 | tcg_set_insn_start_param(s->insn_start, 2, syn); |
142 | s->insn_start = NULL; |
143 | } |
144 | |
145 | /* is_jmp field values */ |
146 | #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ |
147 | #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ |
148 | /* These instructions trap after executing, so the A32/T32 decoder must |
149 | * defer them until after the conditional execution state has been updated. |
150 | * WFI also needs special handling when single-stepping. |
151 | */ |
152 | #define DISAS_WFI DISAS_TARGET_2 |
153 | #define DISAS_SWI DISAS_TARGET_3 |
154 | /* WFE */ |
155 | #define DISAS_WFE DISAS_TARGET_4 |
156 | #define DISAS_HVC DISAS_TARGET_5 |
157 | #define DISAS_SMC DISAS_TARGET_6 |
158 | #define DISAS_YIELD DISAS_TARGET_7 |
159 | /* M profile branch which might be an exception return (and so needs |
160 | * custom end-of-TB code) |
161 | */ |
162 | #define DISAS_BX_EXCRET DISAS_TARGET_8 |
163 | /* For instructions which want an immediate exit to the main loop, |
164 | * as opposed to attempting to use lookup_and_goto_ptr. Unlike |
165 | * DISAS_UPDATE this doesn't write the PC on exiting the translation |
166 | * loop so you need to ensure something (gen_a64_set_pc_im or runtime |
167 | * helper) has done so before we reach return from cpu_tb_exec. |
168 | */ |
169 | #define DISAS_EXIT DISAS_TARGET_9 |
170 | |
171 | #ifdef TARGET_AARCH64 |
172 | void a64_translate_init(void); |
173 | void gen_a64_set_pc_im(uint64_t val); |
174 | extern const TranslatorOps aarch64_translator_ops; |
175 | #else |
176 | static inline void a64_translate_init(void) |
177 | { |
178 | } |
179 | |
180 | static inline void gen_a64_set_pc_im(uint64_t val) |
181 | { |
182 | } |
183 | #endif |
184 | |
185 | void arm_test_cc(DisasCompare *cmp, int cc); |
186 | void arm_free_cc(DisasCompare *cmp); |
187 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); |
188 | void arm_gen_test_cc(int cc, TCGLabel *label); |
189 | |
190 | /* Return state of Alternate Half-precision flag, caller frees result */ |
191 | static inline TCGv_i32 get_ahp_flag(void) |
192 | { |
193 | TCGv_i32 ret = tcg_temp_new_i32(); |
194 | |
195 | tcg_gen_ld_i32(ret, cpu_env, |
196 | offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); |
197 | tcg_gen_extract_i32(ret, ret, 26, 1); |
198 | |
199 | return ret; |
200 | } |
201 | |
202 | /* Set bits within PSTATE. */ |
203 | static inline void set_pstate_bits(uint32_t bits) |
204 | { |
205 | TCGv_i32 p = tcg_temp_new_i32(); |
206 | |
207 | tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); |
208 | |
209 | tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); |
210 | tcg_gen_ori_i32(p, p, bits); |
211 | tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); |
212 | tcg_temp_free_i32(p); |
213 | } |
214 | |
215 | /* Clear bits within PSTATE. */ |
216 | static inline void clear_pstate_bits(uint32_t bits) |
217 | { |
218 | TCGv_i32 p = tcg_temp_new_i32(); |
219 | |
220 | tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); |
221 | |
222 | tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); |
223 | tcg_gen_andi_i32(p, p, ~bits); |
224 | tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); |
225 | tcg_temp_free_i32(p); |
226 | } |
227 | |
228 | /* If the singlestep state is Active-not-pending, advance to Active-pending. */ |
229 | static inline void gen_ss_advance(DisasContext *s) |
230 | { |
231 | if (s->ss_active) { |
232 | s->pstate_ss = 0; |
233 | clear_pstate_bits(PSTATE_SS); |
234 | } |
235 | } |
236 | |
237 | static inline void gen_exception(int excp, uint32_t syndrome, |
238 | uint32_t target_el) |
239 | { |
240 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
241 | TCGv_i32 tcg_syn = tcg_const_i32(syndrome); |
242 | TCGv_i32 tcg_el = tcg_const_i32(target_el); |
243 | |
244 | gen_helper_exception_with_syndrome(cpu_env, tcg_excp, |
245 | tcg_syn, tcg_el); |
246 | |
247 | tcg_temp_free_i32(tcg_el); |
248 | tcg_temp_free_i32(tcg_syn); |
249 | tcg_temp_free_i32(tcg_excp); |
250 | } |
251 | |
252 | /* Generate an architectural singlestep exception */ |
253 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) |
254 | { |
255 | bool same_el = (s->debug_target_el == s->current_el); |
256 | |
257 | /* |
258 | * If singlestep is targeting a lower EL than the current one, |
259 | * then s->ss_active must be false and we can never get here. |
260 | */ |
261 | assert(s->debug_target_el >= s->current_el); |
262 | |
263 | gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); |
264 | } |
265 | |
266 | /* |
267 | * Given a VFP floating point constant encoded into an 8 bit immediate in an |
268 | * instruction, expand it to the actual constant value of the specified |
269 | * size, as per the VFPExpandImm() pseudocode in the Arm ARM. |
270 | */ |
271 | uint64_t vfp_expand_imm(int size, uint8_t imm8); |
272 | |
273 | /* Vector operations shared between ARM and AArch64. */ |
274 | extern const GVecGen3 mla_op[4]; |
275 | extern const GVecGen3 mls_op[4]; |
276 | extern const GVecGen3 cmtst_op[4]; |
277 | extern const GVecGen2i ssra_op[4]; |
278 | extern const GVecGen2i usra_op[4]; |
279 | extern const GVecGen2i sri_op[4]; |
280 | extern const GVecGen2i sli_op[4]; |
281 | extern const GVecGen4 uqadd_op[4]; |
282 | extern const GVecGen4 sqadd_op[4]; |
283 | extern const GVecGen4 uqsub_op[4]; |
284 | extern const GVecGen4 sqsub_op[4]; |
285 | void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); |
286 | |
287 | /* |
288 | * Forward to the isar_feature_* tests given a DisasContext pointer. |
289 | */ |
290 | #define dc_isar_feature(name, ctx) \ |
291 | ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) |
292 | |
293 | #endif /* TARGET_ARM_TRANSLATE_H */ |
294 | |