1 | /* This file is autogenerated by tracetool, do not edit. */ |
2 | |
3 | #ifndef TRACE_HW_CHAR_GENERATED_TRACERS_H |
4 | #define TRACE_HW_CHAR_GENERATED_TRACERS_H |
5 | |
6 | #include "trace/control.h" |
7 | |
8 | extern TraceEvent _TRACE_PARALLEL_IOPORT_READ_EVENT; |
9 | extern TraceEvent _TRACE_PARALLEL_IOPORT_WRITE_EVENT; |
10 | extern TraceEvent _TRACE_SERIAL_IOPORT_READ_EVENT; |
11 | extern TraceEvent _TRACE_SERIAL_IOPORT_WRITE_EVENT; |
12 | extern TraceEvent _TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_EVENT; |
13 | extern TraceEvent _TRACE_VIRTIO_SERIAL_THROTTLE_PORT_EVENT; |
14 | extern TraceEvent _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_EVENT; |
15 | extern TraceEvent _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_EVENT; |
16 | extern TraceEvent _TRACE_VIRTIO_CONSOLE_FLUSH_BUF_EVENT; |
17 | extern TraceEvent _TRACE_VIRTIO_CONSOLE_CHR_READ_EVENT; |
18 | extern TraceEvent _TRACE_VIRTIO_CONSOLE_CHR_EVENT_EVENT; |
19 | extern TraceEvent _TRACE_GRLIB_APBUART_EVENT_EVENT; |
20 | extern TraceEvent _TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_EVENT; |
21 | extern TraceEvent _TRACE_GRLIB_APBUART_READL_UNKNOWN_EVENT; |
22 | extern TraceEvent _TRACE_LM32_JUART_GET_JTX_EVENT; |
23 | extern TraceEvent _TRACE_LM32_JUART_SET_JTX_EVENT; |
24 | extern TraceEvent _TRACE_LM32_JUART_GET_JRX_EVENT; |
25 | extern TraceEvent _TRACE_LM32_JUART_SET_JRX_EVENT; |
26 | extern TraceEvent _TRACE_LM32_UART_MEMORY_WRITE_EVENT; |
27 | extern TraceEvent _TRACE_LM32_UART_MEMORY_READ_EVENT; |
28 | extern TraceEvent _TRACE_LM32_UART_IRQ_STATE_EVENT; |
29 | extern TraceEvent _TRACE_MILKYMIST_UART_MEMORY_READ_EVENT; |
30 | extern TraceEvent _TRACE_MILKYMIST_UART_MEMORY_WRITE_EVENT; |
31 | extern TraceEvent _TRACE_MILKYMIST_UART_RAISE_IRQ_EVENT; |
32 | extern TraceEvent _TRACE_MILKYMIST_UART_LOWER_IRQ_EVENT; |
33 | extern TraceEvent _TRACE_ESCC_PUT_QUEUE_EVENT; |
34 | extern TraceEvent _TRACE_ESCC_GET_QUEUE_EVENT; |
35 | extern TraceEvent _TRACE_ESCC_UPDATE_IRQ_EVENT; |
36 | extern TraceEvent _TRACE_ESCC_UPDATE_PARAMETERS_EVENT; |
37 | extern TraceEvent _TRACE_ESCC_MEM_WRITEB_CTRL_EVENT; |
38 | extern TraceEvent _TRACE_ESCC_MEM_WRITEB_DATA_EVENT; |
39 | extern TraceEvent _TRACE_ESCC_MEM_READB_CTRL_EVENT; |
40 | extern TraceEvent _TRACE_ESCC_MEM_READB_DATA_EVENT; |
41 | extern TraceEvent _TRACE_ESCC_SERIAL_RECEIVE_BYTE_EVENT; |
42 | extern TraceEvent _TRACE_ESCC_SUNKBD_EVENT_IN_EVENT; |
43 | extern TraceEvent _TRACE_ESCC_SUNKBD_EVENT_OUT_EVENT; |
44 | extern TraceEvent _TRACE_ESCC_KBD_COMMAND_EVENT; |
45 | extern TraceEvent _TRACE_ESCC_SUNMOUSE_EVENT_EVENT; |
46 | extern TraceEvent _TRACE_PL011_IRQ_STATE_EVENT; |
47 | extern TraceEvent _TRACE_PL011_READ_EVENT; |
48 | extern TraceEvent _TRACE_PL011_READ_FIFO_EVENT; |
49 | extern TraceEvent _TRACE_PL011_WRITE_EVENT; |
50 | extern TraceEvent _TRACE_PL011_CAN_RECEIVE_EVENT; |
51 | extern TraceEvent _TRACE_PL011_PUT_FIFO_EVENT; |
52 | extern TraceEvent _TRACE_PL011_PUT_FIFO_FULL_EVENT; |
53 | extern TraceEvent _TRACE_CMSDK_APB_UART_READ_EVENT; |
54 | extern TraceEvent _TRACE_CMSDK_APB_UART_WRITE_EVENT; |
55 | extern TraceEvent _TRACE_CMSDK_APB_UART_RESET_EVENT; |
56 | extern TraceEvent _TRACE_CMSDK_APB_UART_RECEIVE_EVENT; |
57 | extern TraceEvent _TRACE_CMSDK_APB_UART_TX_PENDING_EVENT; |
58 | extern TraceEvent _TRACE_CMSDK_APB_UART_TX_EVENT; |
59 | extern TraceEvent _TRACE_CMSDK_APB_UART_SET_PARAMS_EVENT; |
60 | extern TraceEvent _TRACE_NRF51_UART_READ_EVENT; |
61 | extern TraceEvent _TRACE_NRF51_UART_WRITE_EVENT; |
62 | extern uint16_t _TRACE_PARALLEL_IOPORT_READ_DSTATE; |
63 | extern uint16_t _TRACE_PARALLEL_IOPORT_WRITE_DSTATE; |
64 | extern uint16_t _TRACE_SERIAL_IOPORT_READ_DSTATE; |
65 | extern uint16_t _TRACE_SERIAL_IOPORT_WRITE_DSTATE; |
66 | extern uint16_t _TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_DSTATE; |
67 | extern uint16_t _TRACE_VIRTIO_SERIAL_THROTTLE_PORT_DSTATE; |
68 | extern uint16_t _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_DSTATE; |
69 | extern uint16_t _TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_DSTATE; |
70 | extern uint16_t _TRACE_VIRTIO_CONSOLE_FLUSH_BUF_DSTATE; |
71 | extern uint16_t _TRACE_VIRTIO_CONSOLE_CHR_READ_DSTATE; |
72 | extern uint16_t _TRACE_VIRTIO_CONSOLE_CHR_EVENT_DSTATE; |
73 | extern uint16_t _TRACE_GRLIB_APBUART_EVENT_DSTATE; |
74 | extern uint16_t _TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_DSTATE; |
75 | extern uint16_t _TRACE_GRLIB_APBUART_READL_UNKNOWN_DSTATE; |
76 | extern uint16_t _TRACE_LM32_JUART_GET_JTX_DSTATE; |
77 | extern uint16_t _TRACE_LM32_JUART_SET_JTX_DSTATE; |
78 | extern uint16_t _TRACE_LM32_JUART_GET_JRX_DSTATE; |
79 | extern uint16_t _TRACE_LM32_JUART_SET_JRX_DSTATE; |
80 | extern uint16_t _TRACE_LM32_UART_MEMORY_WRITE_DSTATE; |
81 | extern uint16_t _TRACE_LM32_UART_MEMORY_READ_DSTATE; |
82 | extern uint16_t _TRACE_LM32_UART_IRQ_STATE_DSTATE; |
83 | extern uint16_t _TRACE_MILKYMIST_UART_MEMORY_READ_DSTATE; |
84 | extern uint16_t _TRACE_MILKYMIST_UART_MEMORY_WRITE_DSTATE; |
85 | extern uint16_t _TRACE_MILKYMIST_UART_RAISE_IRQ_DSTATE; |
86 | extern uint16_t _TRACE_MILKYMIST_UART_LOWER_IRQ_DSTATE; |
87 | extern uint16_t _TRACE_ESCC_PUT_QUEUE_DSTATE; |
88 | extern uint16_t _TRACE_ESCC_GET_QUEUE_DSTATE; |
89 | extern uint16_t _TRACE_ESCC_UPDATE_IRQ_DSTATE; |
90 | extern uint16_t _TRACE_ESCC_UPDATE_PARAMETERS_DSTATE; |
91 | extern uint16_t _TRACE_ESCC_MEM_WRITEB_CTRL_DSTATE; |
92 | extern uint16_t _TRACE_ESCC_MEM_WRITEB_DATA_DSTATE; |
93 | extern uint16_t _TRACE_ESCC_MEM_READB_CTRL_DSTATE; |
94 | extern uint16_t _TRACE_ESCC_MEM_READB_DATA_DSTATE; |
95 | extern uint16_t _TRACE_ESCC_SERIAL_RECEIVE_BYTE_DSTATE; |
96 | extern uint16_t _TRACE_ESCC_SUNKBD_EVENT_IN_DSTATE; |
97 | extern uint16_t _TRACE_ESCC_SUNKBD_EVENT_OUT_DSTATE; |
98 | extern uint16_t _TRACE_ESCC_KBD_COMMAND_DSTATE; |
99 | extern uint16_t _TRACE_ESCC_SUNMOUSE_EVENT_DSTATE; |
100 | extern uint16_t _TRACE_PL011_IRQ_STATE_DSTATE; |
101 | extern uint16_t _TRACE_PL011_READ_DSTATE; |
102 | extern uint16_t _TRACE_PL011_READ_FIFO_DSTATE; |
103 | extern uint16_t _TRACE_PL011_WRITE_DSTATE; |
104 | extern uint16_t _TRACE_PL011_CAN_RECEIVE_DSTATE; |
105 | extern uint16_t _TRACE_PL011_PUT_FIFO_DSTATE; |
106 | extern uint16_t _TRACE_PL011_PUT_FIFO_FULL_DSTATE; |
107 | extern uint16_t _TRACE_CMSDK_APB_UART_READ_DSTATE; |
108 | extern uint16_t _TRACE_CMSDK_APB_UART_WRITE_DSTATE; |
109 | extern uint16_t _TRACE_CMSDK_APB_UART_RESET_DSTATE; |
110 | extern uint16_t _TRACE_CMSDK_APB_UART_RECEIVE_DSTATE; |
111 | extern uint16_t _TRACE_CMSDK_APB_UART_TX_PENDING_DSTATE; |
112 | extern uint16_t _TRACE_CMSDK_APB_UART_TX_DSTATE; |
113 | extern uint16_t _TRACE_CMSDK_APB_UART_SET_PARAMS_DSTATE; |
114 | extern uint16_t _TRACE_NRF51_UART_READ_DSTATE; |
115 | extern uint16_t _TRACE_NRF51_UART_WRITE_DSTATE; |
116 | #define TRACE_PARALLEL_IOPORT_READ_ENABLED 1 |
117 | #define TRACE_PARALLEL_IOPORT_WRITE_ENABLED 1 |
118 | #define TRACE_SERIAL_IOPORT_READ_ENABLED 1 |
119 | #define TRACE_SERIAL_IOPORT_WRITE_ENABLED 1 |
120 | #define TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_ENABLED 1 |
121 | #define TRACE_VIRTIO_SERIAL_THROTTLE_PORT_ENABLED 1 |
122 | #define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_ENABLED 1 |
123 | #define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_ENABLED 1 |
124 | #define TRACE_VIRTIO_CONSOLE_FLUSH_BUF_ENABLED 1 |
125 | #define TRACE_VIRTIO_CONSOLE_CHR_READ_ENABLED 1 |
126 | #define TRACE_VIRTIO_CONSOLE_CHR_EVENT_ENABLED 1 |
127 | #define TRACE_GRLIB_APBUART_EVENT_ENABLED 1 |
128 | #define TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_ENABLED 1 |
129 | #define TRACE_GRLIB_APBUART_READL_UNKNOWN_ENABLED 1 |
130 | #define TRACE_LM32_JUART_GET_JTX_ENABLED 1 |
131 | #define TRACE_LM32_JUART_SET_JTX_ENABLED 1 |
132 | #define TRACE_LM32_JUART_GET_JRX_ENABLED 1 |
133 | #define TRACE_LM32_JUART_SET_JRX_ENABLED 1 |
134 | #define TRACE_LM32_UART_MEMORY_WRITE_ENABLED 1 |
135 | #define TRACE_LM32_UART_MEMORY_READ_ENABLED 1 |
136 | #define TRACE_LM32_UART_IRQ_STATE_ENABLED 1 |
137 | #define TRACE_MILKYMIST_UART_MEMORY_READ_ENABLED 1 |
138 | #define TRACE_MILKYMIST_UART_MEMORY_WRITE_ENABLED 1 |
139 | #define TRACE_MILKYMIST_UART_RAISE_IRQ_ENABLED 1 |
140 | #define TRACE_MILKYMIST_UART_LOWER_IRQ_ENABLED 1 |
141 | #define TRACE_ESCC_PUT_QUEUE_ENABLED 1 |
142 | #define TRACE_ESCC_GET_QUEUE_ENABLED 1 |
143 | #define TRACE_ESCC_UPDATE_IRQ_ENABLED 1 |
144 | #define TRACE_ESCC_UPDATE_PARAMETERS_ENABLED 1 |
145 | #define TRACE_ESCC_MEM_WRITEB_CTRL_ENABLED 1 |
146 | #define TRACE_ESCC_MEM_WRITEB_DATA_ENABLED 1 |
147 | #define TRACE_ESCC_MEM_READB_CTRL_ENABLED 1 |
148 | #define TRACE_ESCC_MEM_READB_DATA_ENABLED 1 |
149 | #define TRACE_ESCC_SERIAL_RECEIVE_BYTE_ENABLED 1 |
150 | #define TRACE_ESCC_SUNKBD_EVENT_IN_ENABLED 1 |
151 | #define TRACE_ESCC_SUNKBD_EVENT_OUT_ENABLED 1 |
152 | #define TRACE_ESCC_KBD_COMMAND_ENABLED 1 |
153 | #define TRACE_ESCC_SUNMOUSE_EVENT_ENABLED 1 |
154 | #define TRACE_PL011_IRQ_STATE_ENABLED 1 |
155 | #define TRACE_PL011_READ_ENABLED 1 |
156 | #define TRACE_PL011_READ_FIFO_ENABLED 1 |
157 | #define TRACE_PL011_WRITE_ENABLED 1 |
158 | #define TRACE_PL011_CAN_RECEIVE_ENABLED 1 |
159 | #define TRACE_PL011_PUT_FIFO_ENABLED 1 |
160 | #define TRACE_PL011_PUT_FIFO_FULL_ENABLED 1 |
161 | #define TRACE_CMSDK_APB_UART_READ_ENABLED 1 |
162 | #define TRACE_CMSDK_APB_UART_WRITE_ENABLED 1 |
163 | #define TRACE_CMSDK_APB_UART_RESET_ENABLED 1 |
164 | #define TRACE_CMSDK_APB_UART_RECEIVE_ENABLED 1 |
165 | #define TRACE_CMSDK_APB_UART_TX_PENDING_ENABLED 1 |
166 | #define TRACE_CMSDK_APB_UART_TX_ENABLED 1 |
167 | #define TRACE_CMSDK_APB_UART_SET_PARAMS_ENABLED 1 |
168 | #define TRACE_NRF51_UART_READ_ENABLED 1 |
169 | #define TRACE_NRF51_UART_WRITE_ENABLED 1 |
170 | #include "qemu/log-for-trace.h" |
171 | |
172 | |
173 | #define TRACE_PARALLEL_IOPORT_READ_BACKEND_DSTATE() ( \ |
174 | trace_event_get_state_dynamic_by_id(TRACE_PARALLEL_IOPORT_READ) || \ |
175 | false) |
176 | |
177 | static inline void _nocheck__trace_parallel_ioport_read(const char * desc, uint16_t addr, uint8_t value) |
178 | { |
179 | if (trace_event_get_state(TRACE_PARALLEL_IOPORT_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
180 | struct timeval _now; |
181 | gettimeofday(&_now, NULL); |
182 | qemu_log("%d@%zu.%06zu:parallel_ioport_read " "read [%s] addr 0x%02x val 0x%02x" "\n" , |
183 | qemu_get_thread_id(), |
184 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
185 | , desc, addr, value); |
186 | } |
187 | } |
188 | |
189 | static inline void trace_parallel_ioport_read(const char * desc, uint16_t addr, uint8_t value) |
190 | { |
191 | if (true) { |
192 | _nocheck__trace_parallel_ioport_read(desc, addr, value); |
193 | } |
194 | } |
195 | |
196 | #define TRACE_PARALLEL_IOPORT_WRITE_BACKEND_DSTATE() ( \ |
197 | trace_event_get_state_dynamic_by_id(TRACE_PARALLEL_IOPORT_WRITE) || \ |
198 | false) |
199 | |
200 | static inline void _nocheck__trace_parallel_ioport_write(const char * desc, uint16_t addr, uint8_t value) |
201 | { |
202 | if (trace_event_get_state(TRACE_PARALLEL_IOPORT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
203 | struct timeval _now; |
204 | gettimeofday(&_now, NULL); |
205 | qemu_log("%d@%zu.%06zu:parallel_ioport_write " "write [%s] addr 0x%02x val 0x%02x" "\n" , |
206 | qemu_get_thread_id(), |
207 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
208 | , desc, addr, value); |
209 | } |
210 | } |
211 | |
212 | static inline void trace_parallel_ioport_write(const char * desc, uint16_t addr, uint8_t value) |
213 | { |
214 | if (true) { |
215 | _nocheck__trace_parallel_ioport_write(desc, addr, value); |
216 | } |
217 | } |
218 | |
219 | #define TRACE_SERIAL_IOPORT_READ_BACKEND_DSTATE() ( \ |
220 | trace_event_get_state_dynamic_by_id(TRACE_SERIAL_IOPORT_READ) || \ |
221 | false) |
222 | |
223 | static inline void _nocheck__trace_serial_ioport_read(uint16_t addr, uint8_t value) |
224 | { |
225 | if (trace_event_get_state(TRACE_SERIAL_IOPORT_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
226 | struct timeval _now; |
227 | gettimeofday(&_now, NULL); |
228 | qemu_log("%d@%zu.%06zu:serial_ioport_read " "read addr 0x%02x val 0x%02x" "\n" , |
229 | qemu_get_thread_id(), |
230 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
231 | , addr, value); |
232 | } |
233 | } |
234 | |
235 | static inline void trace_serial_ioport_read(uint16_t addr, uint8_t value) |
236 | { |
237 | if (true) { |
238 | _nocheck__trace_serial_ioport_read(addr, value); |
239 | } |
240 | } |
241 | |
242 | #define TRACE_SERIAL_IOPORT_WRITE_BACKEND_DSTATE() ( \ |
243 | trace_event_get_state_dynamic_by_id(TRACE_SERIAL_IOPORT_WRITE) || \ |
244 | false) |
245 | |
246 | static inline void _nocheck__trace_serial_ioport_write(uint16_t addr, uint8_t value) |
247 | { |
248 | if (trace_event_get_state(TRACE_SERIAL_IOPORT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
249 | struct timeval _now; |
250 | gettimeofday(&_now, NULL); |
251 | qemu_log("%d@%zu.%06zu:serial_ioport_write " "write addr 0x%02x val 0x%02x" "\n" , |
252 | qemu_get_thread_id(), |
253 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
254 | , addr, value); |
255 | } |
256 | } |
257 | |
258 | static inline void trace_serial_ioport_write(uint16_t addr, uint8_t value) |
259 | { |
260 | if (true) { |
261 | _nocheck__trace_serial_ioport_write(addr, value); |
262 | } |
263 | } |
264 | |
265 | #define TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT_BACKEND_DSTATE() ( \ |
266 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT) || \ |
267 | false) |
268 | |
269 | static inline void _nocheck__trace_virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value) |
270 | { |
271 | if (trace_event_get_state(TRACE_VIRTIO_SERIAL_SEND_CONTROL_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { |
272 | struct timeval _now; |
273 | gettimeofday(&_now, NULL); |
274 | qemu_log("%d@%zu.%06zu:virtio_serial_send_control_event " "port %u, event %u, value %u" "\n" , |
275 | qemu_get_thread_id(), |
276 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
277 | , port, event, value); |
278 | } |
279 | } |
280 | |
281 | static inline void trace_virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value) |
282 | { |
283 | if (true) { |
284 | _nocheck__trace_virtio_serial_send_control_event(port, event, value); |
285 | } |
286 | } |
287 | |
288 | #define TRACE_VIRTIO_SERIAL_THROTTLE_PORT_BACKEND_DSTATE() ( \ |
289 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_THROTTLE_PORT) || \ |
290 | false) |
291 | |
292 | static inline void _nocheck__trace_virtio_serial_throttle_port(unsigned int port, bool throttle) |
293 | { |
294 | if (trace_event_get_state(TRACE_VIRTIO_SERIAL_THROTTLE_PORT) && qemu_loglevel_mask(LOG_TRACE)) { |
295 | struct timeval _now; |
296 | gettimeofday(&_now, NULL); |
297 | qemu_log("%d@%zu.%06zu:virtio_serial_throttle_port " "port %u, throttle %d" "\n" , |
298 | qemu_get_thread_id(), |
299 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
300 | , port, throttle); |
301 | } |
302 | } |
303 | |
304 | static inline void trace_virtio_serial_throttle_port(unsigned int port, bool throttle) |
305 | { |
306 | if (true) { |
307 | _nocheck__trace_virtio_serial_throttle_port(port, throttle); |
308 | } |
309 | } |
310 | |
311 | #define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_BACKEND_DSTATE() ( \ |
312 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE) || \ |
313 | false) |
314 | |
315 | static inline void _nocheck__trace_virtio_serial_handle_control_message(uint16_t event, uint16_t value) |
316 | { |
317 | if (trace_event_get_state(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE) && qemu_loglevel_mask(LOG_TRACE)) { |
318 | struct timeval _now; |
319 | gettimeofday(&_now, NULL); |
320 | qemu_log("%d@%zu.%06zu:virtio_serial_handle_control_message " "event %u, value %u" "\n" , |
321 | qemu_get_thread_id(), |
322 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
323 | , event, value); |
324 | } |
325 | } |
326 | |
327 | static inline void trace_virtio_serial_handle_control_message(uint16_t event, uint16_t value) |
328 | { |
329 | if (true) { |
330 | _nocheck__trace_virtio_serial_handle_control_message(event, value); |
331 | } |
332 | } |
333 | |
334 | #define TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT_BACKEND_DSTATE() ( \ |
335 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT) || \ |
336 | false) |
337 | |
338 | static inline void _nocheck__trace_virtio_serial_handle_control_message_port(unsigned int port) |
339 | { |
340 | if (trace_event_get_state(TRACE_VIRTIO_SERIAL_HANDLE_CONTROL_MESSAGE_PORT) && qemu_loglevel_mask(LOG_TRACE)) { |
341 | struct timeval _now; |
342 | gettimeofday(&_now, NULL); |
343 | qemu_log("%d@%zu.%06zu:virtio_serial_handle_control_message_port " "port %u" "\n" , |
344 | qemu_get_thread_id(), |
345 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
346 | , port); |
347 | } |
348 | } |
349 | |
350 | static inline void trace_virtio_serial_handle_control_message_port(unsigned int port) |
351 | { |
352 | if (true) { |
353 | _nocheck__trace_virtio_serial_handle_control_message_port(port); |
354 | } |
355 | } |
356 | |
357 | #define TRACE_VIRTIO_CONSOLE_FLUSH_BUF_BACKEND_DSTATE() ( \ |
358 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_FLUSH_BUF) || \ |
359 | false) |
360 | |
361 | static inline void _nocheck__trace_virtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret) |
362 | { |
363 | if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_FLUSH_BUF) && qemu_loglevel_mask(LOG_TRACE)) { |
364 | struct timeval _now; |
365 | gettimeofday(&_now, NULL); |
366 | qemu_log("%d@%zu.%06zu:virtio_console_flush_buf " "port %u, in_len %zu, out_len %zd" "\n" , |
367 | qemu_get_thread_id(), |
368 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
369 | , port, len, ret); |
370 | } |
371 | } |
372 | |
373 | static inline void trace_virtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret) |
374 | { |
375 | if (true) { |
376 | _nocheck__trace_virtio_console_flush_buf(port, len, ret); |
377 | } |
378 | } |
379 | |
380 | #define TRACE_VIRTIO_CONSOLE_CHR_READ_BACKEND_DSTATE() ( \ |
381 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_CHR_READ) || \ |
382 | false) |
383 | |
384 | static inline void _nocheck__trace_virtio_console_chr_read(unsigned int port, int size) |
385 | { |
386 | if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_CHR_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
387 | struct timeval _now; |
388 | gettimeofday(&_now, NULL); |
389 | qemu_log("%d@%zu.%06zu:virtio_console_chr_read " "port %u, size %d" "\n" , |
390 | qemu_get_thread_id(), |
391 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
392 | , port, size); |
393 | } |
394 | } |
395 | |
396 | static inline void trace_virtio_console_chr_read(unsigned int port, int size) |
397 | { |
398 | if (true) { |
399 | _nocheck__trace_virtio_console_chr_read(port, size); |
400 | } |
401 | } |
402 | |
403 | #define TRACE_VIRTIO_CONSOLE_CHR_EVENT_BACKEND_DSTATE() ( \ |
404 | trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_CONSOLE_CHR_EVENT) || \ |
405 | false) |
406 | |
407 | static inline void _nocheck__trace_virtio_console_chr_event(unsigned int port, int event) |
408 | { |
409 | if (trace_event_get_state(TRACE_VIRTIO_CONSOLE_CHR_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { |
410 | struct timeval _now; |
411 | gettimeofday(&_now, NULL); |
412 | qemu_log("%d@%zu.%06zu:virtio_console_chr_event " "port %u, event %d" "\n" , |
413 | qemu_get_thread_id(), |
414 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
415 | , port, event); |
416 | } |
417 | } |
418 | |
419 | static inline void trace_virtio_console_chr_event(unsigned int port, int event) |
420 | { |
421 | if (true) { |
422 | _nocheck__trace_virtio_console_chr_event(port, event); |
423 | } |
424 | } |
425 | |
426 | #define TRACE_GRLIB_APBUART_EVENT_BACKEND_DSTATE() ( \ |
427 | trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_EVENT) || \ |
428 | false) |
429 | |
430 | static inline void _nocheck__trace_grlib_apbuart_event(int event) |
431 | { |
432 | if (trace_event_get_state(TRACE_GRLIB_APBUART_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { |
433 | struct timeval _now; |
434 | gettimeofday(&_now, NULL); |
435 | qemu_log("%d@%zu.%06zu:grlib_apbuart_event " "event:%d" "\n" , |
436 | qemu_get_thread_id(), |
437 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
438 | , event); |
439 | } |
440 | } |
441 | |
442 | static inline void trace_grlib_apbuart_event(int event) |
443 | { |
444 | if (true) { |
445 | _nocheck__trace_grlib_apbuart_event(event); |
446 | } |
447 | } |
448 | |
449 | #define TRACE_GRLIB_APBUART_WRITEL_UNKNOWN_BACKEND_DSTATE() ( \ |
450 | trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_WRITEL_UNKNOWN) || \ |
451 | false) |
452 | |
453 | static inline void _nocheck__trace_grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) |
454 | { |
455 | if (trace_event_get_state(TRACE_GRLIB_APBUART_WRITEL_UNKNOWN) && qemu_loglevel_mask(LOG_TRACE)) { |
456 | struct timeval _now; |
457 | gettimeofday(&_now, NULL); |
458 | qemu_log("%d@%zu.%06zu:grlib_apbuart_writel_unknown " "addr 0x%" PRIx64" value 0x%x" "\n" , |
459 | qemu_get_thread_id(), |
460 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
461 | , addr, value); |
462 | } |
463 | } |
464 | |
465 | static inline void trace_grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) |
466 | { |
467 | if (true) { |
468 | _nocheck__trace_grlib_apbuart_writel_unknown(addr, value); |
469 | } |
470 | } |
471 | |
472 | #define TRACE_GRLIB_APBUART_READL_UNKNOWN_BACKEND_DSTATE() ( \ |
473 | trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APBUART_READL_UNKNOWN) || \ |
474 | false) |
475 | |
476 | static inline void _nocheck__trace_grlib_apbuart_readl_unknown(uint64_t addr) |
477 | { |
478 | if (trace_event_get_state(TRACE_GRLIB_APBUART_READL_UNKNOWN) && qemu_loglevel_mask(LOG_TRACE)) { |
479 | struct timeval _now; |
480 | gettimeofday(&_now, NULL); |
481 | qemu_log("%d@%zu.%06zu:grlib_apbuart_readl_unknown " "addr 0x%" PRIx64 "\n" , |
482 | qemu_get_thread_id(), |
483 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
484 | , addr); |
485 | } |
486 | } |
487 | |
488 | static inline void trace_grlib_apbuart_readl_unknown(uint64_t addr) |
489 | { |
490 | if (true) { |
491 | _nocheck__trace_grlib_apbuart_readl_unknown(addr); |
492 | } |
493 | } |
494 | |
495 | #define TRACE_LM32_JUART_GET_JTX_BACKEND_DSTATE() ( \ |
496 | trace_event_get_state_dynamic_by_id(TRACE_LM32_JUART_GET_JTX) || \ |
497 | false) |
498 | |
499 | static inline void _nocheck__trace_lm32_juart_get_jtx(uint32_t value) |
500 | { |
501 | if (trace_event_get_state(TRACE_LM32_JUART_GET_JTX) && qemu_loglevel_mask(LOG_TRACE)) { |
502 | struct timeval _now; |
503 | gettimeofday(&_now, NULL); |
504 | qemu_log("%d@%zu.%06zu:lm32_juart_get_jtx " "jtx 0x%08x" "\n" , |
505 | qemu_get_thread_id(), |
506 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
507 | , value); |
508 | } |
509 | } |
510 | |
511 | static inline void trace_lm32_juart_get_jtx(uint32_t value) |
512 | { |
513 | if (true) { |
514 | _nocheck__trace_lm32_juart_get_jtx(value); |
515 | } |
516 | } |
517 | |
518 | #define TRACE_LM32_JUART_SET_JTX_BACKEND_DSTATE() ( \ |
519 | trace_event_get_state_dynamic_by_id(TRACE_LM32_JUART_SET_JTX) || \ |
520 | false) |
521 | |
522 | static inline void _nocheck__trace_lm32_juart_set_jtx(uint32_t value) |
523 | { |
524 | if (trace_event_get_state(TRACE_LM32_JUART_SET_JTX) && qemu_loglevel_mask(LOG_TRACE)) { |
525 | struct timeval _now; |
526 | gettimeofday(&_now, NULL); |
527 | qemu_log("%d@%zu.%06zu:lm32_juart_set_jtx " "jtx 0x%08x" "\n" , |
528 | qemu_get_thread_id(), |
529 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
530 | , value); |
531 | } |
532 | } |
533 | |
534 | static inline void trace_lm32_juart_set_jtx(uint32_t value) |
535 | { |
536 | if (true) { |
537 | _nocheck__trace_lm32_juart_set_jtx(value); |
538 | } |
539 | } |
540 | |
541 | #define TRACE_LM32_JUART_GET_JRX_BACKEND_DSTATE() ( \ |
542 | trace_event_get_state_dynamic_by_id(TRACE_LM32_JUART_GET_JRX) || \ |
543 | false) |
544 | |
545 | static inline void _nocheck__trace_lm32_juart_get_jrx(uint32_t value) |
546 | { |
547 | if (trace_event_get_state(TRACE_LM32_JUART_GET_JRX) && qemu_loglevel_mask(LOG_TRACE)) { |
548 | struct timeval _now; |
549 | gettimeofday(&_now, NULL); |
550 | qemu_log("%d@%zu.%06zu:lm32_juart_get_jrx " "jrx 0x%08x" "\n" , |
551 | qemu_get_thread_id(), |
552 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
553 | , value); |
554 | } |
555 | } |
556 | |
557 | static inline void trace_lm32_juart_get_jrx(uint32_t value) |
558 | { |
559 | if (true) { |
560 | _nocheck__trace_lm32_juart_get_jrx(value); |
561 | } |
562 | } |
563 | |
564 | #define TRACE_LM32_JUART_SET_JRX_BACKEND_DSTATE() ( \ |
565 | trace_event_get_state_dynamic_by_id(TRACE_LM32_JUART_SET_JRX) || \ |
566 | false) |
567 | |
568 | static inline void _nocheck__trace_lm32_juart_set_jrx(uint32_t value) |
569 | { |
570 | if (trace_event_get_state(TRACE_LM32_JUART_SET_JRX) && qemu_loglevel_mask(LOG_TRACE)) { |
571 | struct timeval _now; |
572 | gettimeofday(&_now, NULL); |
573 | qemu_log("%d@%zu.%06zu:lm32_juart_set_jrx " "jrx 0x%08x" "\n" , |
574 | qemu_get_thread_id(), |
575 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
576 | , value); |
577 | } |
578 | } |
579 | |
580 | static inline void trace_lm32_juart_set_jrx(uint32_t value) |
581 | { |
582 | if (true) { |
583 | _nocheck__trace_lm32_juart_set_jrx(value); |
584 | } |
585 | } |
586 | |
587 | #define TRACE_LM32_UART_MEMORY_WRITE_BACKEND_DSTATE() ( \ |
588 | trace_event_get_state_dynamic_by_id(TRACE_LM32_UART_MEMORY_WRITE) || \ |
589 | false) |
590 | |
591 | static inline void _nocheck__trace_lm32_uart_memory_write(uint32_t addr, uint32_t value) |
592 | { |
593 | if (trace_event_get_state(TRACE_LM32_UART_MEMORY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
594 | struct timeval _now; |
595 | gettimeofday(&_now, NULL); |
596 | qemu_log("%d@%zu.%06zu:lm32_uart_memory_write " "addr 0x%08x value 0x%08x" "\n" , |
597 | qemu_get_thread_id(), |
598 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
599 | , addr, value); |
600 | } |
601 | } |
602 | |
603 | static inline void trace_lm32_uart_memory_write(uint32_t addr, uint32_t value) |
604 | { |
605 | if (true) { |
606 | _nocheck__trace_lm32_uart_memory_write(addr, value); |
607 | } |
608 | } |
609 | |
610 | #define TRACE_LM32_UART_MEMORY_READ_BACKEND_DSTATE() ( \ |
611 | trace_event_get_state_dynamic_by_id(TRACE_LM32_UART_MEMORY_READ) || \ |
612 | false) |
613 | |
614 | static inline void _nocheck__trace_lm32_uart_memory_read(uint32_t addr, uint32_t value) |
615 | { |
616 | if (trace_event_get_state(TRACE_LM32_UART_MEMORY_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
617 | struct timeval _now; |
618 | gettimeofday(&_now, NULL); |
619 | qemu_log("%d@%zu.%06zu:lm32_uart_memory_read " "addr 0x%08x value 0x%08x" "\n" , |
620 | qemu_get_thread_id(), |
621 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
622 | , addr, value); |
623 | } |
624 | } |
625 | |
626 | static inline void trace_lm32_uart_memory_read(uint32_t addr, uint32_t value) |
627 | { |
628 | if (true) { |
629 | _nocheck__trace_lm32_uart_memory_read(addr, value); |
630 | } |
631 | } |
632 | |
633 | #define TRACE_LM32_UART_IRQ_STATE_BACKEND_DSTATE() ( \ |
634 | trace_event_get_state_dynamic_by_id(TRACE_LM32_UART_IRQ_STATE) || \ |
635 | false) |
636 | |
637 | static inline void _nocheck__trace_lm32_uart_irq_state(int level) |
638 | { |
639 | if (trace_event_get_state(TRACE_LM32_UART_IRQ_STATE) && qemu_loglevel_mask(LOG_TRACE)) { |
640 | struct timeval _now; |
641 | gettimeofday(&_now, NULL); |
642 | qemu_log("%d@%zu.%06zu:lm32_uart_irq_state " "irq state %d" "\n" , |
643 | qemu_get_thread_id(), |
644 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
645 | , level); |
646 | } |
647 | } |
648 | |
649 | static inline void trace_lm32_uart_irq_state(int level) |
650 | { |
651 | if (true) { |
652 | _nocheck__trace_lm32_uart_irq_state(level); |
653 | } |
654 | } |
655 | |
656 | #define TRACE_MILKYMIST_UART_MEMORY_READ_BACKEND_DSTATE() ( \ |
657 | trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_UART_MEMORY_READ) || \ |
658 | false) |
659 | |
660 | static inline void _nocheck__trace_milkymist_uart_memory_read(uint32_t addr, uint32_t value) |
661 | { |
662 | if (trace_event_get_state(TRACE_MILKYMIST_UART_MEMORY_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
663 | struct timeval _now; |
664 | gettimeofday(&_now, NULL); |
665 | qemu_log("%d@%zu.%06zu:milkymist_uart_memory_read " "addr 0x%08x value 0x%08x" "\n" , |
666 | qemu_get_thread_id(), |
667 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
668 | , addr, value); |
669 | } |
670 | } |
671 | |
672 | static inline void trace_milkymist_uart_memory_read(uint32_t addr, uint32_t value) |
673 | { |
674 | if (true) { |
675 | _nocheck__trace_milkymist_uart_memory_read(addr, value); |
676 | } |
677 | } |
678 | |
679 | #define TRACE_MILKYMIST_UART_MEMORY_WRITE_BACKEND_DSTATE() ( \ |
680 | trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_UART_MEMORY_WRITE) || \ |
681 | false) |
682 | |
683 | static inline void _nocheck__trace_milkymist_uart_memory_write(uint32_t addr, uint32_t value) |
684 | { |
685 | if (trace_event_get_state(TRACE_MILKYMIST_UART_MEMORY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
686 | struct timeval _now; |
687 | gettimeofday(&_now, NULL); |
688 | qemu_log("%d@%zu.%06zu:milkymist_uart_memory_write " "addr 0x%08x value 0x%08x" "\n" , |
689 | qemu_get_thread_id(), |
690 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
691 | , addr, value); |
692 | } |
693 | } |
694 | |
695 | static inline void trace_milkymist_uart_memory_write(uint32_t addr, uint32_t value) |
696 | { |
697 | if (true) { |
698 | _nocheck__trace_milkymist_uart_memory_write(addr, value); |
699 | } |
700 | } |
701 | |
702 | #define TRACE_MILKYMIST_UART_RAISE_IRQ_BACKEND_DSTATE() ( \ |
703 | trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_UART_RAISE_IRQ) || \ |
704 | false) |
705 | |
706 | static inline void _nocheck__trace_milkymist_uart_raise_irq(void) |
707 | { |
708 | if (trace_event_get_state(TRACE_MILKYMIST_UART_RAISE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { |
709 | struct timeval _now; |
710 | gettimeofday(&_now, NULL); |
711 | qemu_log("%d@%zu.%06zu:milkymist_uart_raise_irq " "Raise IRQ" "\n" , |
712 | qemu_get_thread_id(), |
713 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
714 | ); |
715 | } |
716 | } |
717 | |
718 | static inline void trace_milkymist_uart_raise_irq(void) |
719 | { |
720 | if (true) { |
721 | _nocheck__trace_milkymist_uart_raise_irq(); |
722 | } |
723 | } |
724 | |
725 | #define TRACE_MILKYMIST_UART_LOWER_IRQ_BACKEND_DSTATE() ( \ |
726 | trace_event_get_state_dynamic_by_id(TRACE_MILKYMIST_UART_LOWER_IRQ) || \ |
727 | false) |
728 | |
729 | static inline void _nocheck__trace_milkymist_uart_lower_irq(void) |
730 | { |
731 | if (trace_event_get_state(TRACE_MILKYMIST_UART_LOWER_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { |
732 | struct timeval _now; |
733 | gettimeofday(&_now, NULL); |
734 | qemu_log("%d@%zu.%06zu:milkymist_uart_lower_irq " "Lower IRQ" "\n" , |
735 | qemu_get_thread_id(), |
736 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
737 | ); |
738 | } |
739 | } |
740 | |
741 | static inline void trace_milkymist_uart_lower_irq(void) |
742 | { |
743 | if (true) { |
744 | _nocheck__trace_milkymist_uart_lower_irq(); |
745 | } |
746 | } |
747 | |
748 | #define TRACE_ESCC_PUT_QUEUE_BACKEND_DSTATE() ( \ |
749 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_PUT_QUEUE) || \ |
750 | false) |
751 | |
752 | static inline void _nocheck__trace_escc_put_queue(char channel, int b) |
753 | { |
754 | if (trace_event_get_state(TRACE_ESCC_PUT_QUEUE) && qemu_loglevel_mask(LOG_TRACE)) { |
755 | struct timeval _now; |
756 | gettimeofday(&_now, NULL); |
757 | qemu_log("%d@%zu.%06zu:escc_put_queue " "channel %c put: 0x%02x" "\n" , |
758 | qemu_get_thread_id(), |
759 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
760 | , channel, b); |
761 | } |
762 | } |
763 | |
764 | static inline void trace_escc_put_queue(char channel, int b) |
765 | { |
766 | if (true) { |
767 | _nocheck__trace_escc_put_queue(channel, b); |
768 | } |
769 | } |
770 | |
771 | #define TRACE_ESCC_GET_QUEUE_BACKEND_DSTATE() ( \ |
772 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_GET_QUEUE) || \ |
773 | false) |
774 | |
775 | static inline void _nocheck__trace_escc_get_queue(char channel, int val) |
776 | { |
777 | if (trace_event_get_state(TRACE_ESCC_GET_QUEUE) && qemu_loglevel_mask(LOG_TRACE)) { |
778 | struct timeval _now; |
779 | gettimeofday(&_now, NULL); |
780 | qemu_log("%d@%zu.%06zu:escc_get_queue " "channel %c get 0x%02x" "\n" , |
781 | qemu_get_thread_id(), |
782 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
783 | , channel, val); |
784 | } |
785 | } |
786 | |
787 | static inline void trace_escc_get_queue(char channel, int val) |
788 | { |
789 | if (true) { |
790 | _nocheck__trace_escc_get_queue(channel, val); |
791 | } |
792 | } |
793 | |
794 | #define TRACE_ESCC_UPDATE_IRQ_BACKEND_DSTATE() ( \ |
795 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_UPDATE_IRQ) || \ |
796 | false) |
797 | |
798 | static inline void _nocheck__trace_escc_update_irq(int irq) |
799 | { |
800 | if (trace_event_get_state(TRACE_ESCC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { |
801 | struct timeval _now; |
802 | gettimeofday(&_now, NULL); |
803 | qemu_log("%d@%zu.%06zu:escc_update_irq " "IRQ = %d" "\n" , |
804 | qemu_get_thread_id(), |
805 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
806 | , irq); |
807 | } |
808 | } |
809 | |
810 | static inline void trace_escc_update_irq(int irq) |
811 | { |
812 | if (true) { |
813 | _nocheck__trace_escc_update_irq(irq); |
814 | } |
815 | } |
816 | |
817 | #define TRACE_ESCC_UPDATE_PARAMETERS_BACKEND_DSTATE() ( \ |
818 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_UPDATE_PARAMETERS) || \ |
819 | false) |
820 | |
821 | static inline void _nocheck__trace_escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) |
822 | { |
823 | if (trace_event_get_state(TRACE_ESCC_UPDATE_PARAMETERS) && qemu_loglevel_mask(LOG_TRACE)) { |
824 | struct timeval _now; |
825 | gettimeofday(&_now, NULL); |
826 | qemu_log("%d@%zu.%06zu:escc_update_parameters " "channel %c: speed=%d parity=%c data=%d stop=%d" "\n" , |
827 | qemu_get_thread_id(), |
828 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
829 | , channel, speed, parity, data_bits, stop_bits); |
830 | } |
831 | } |
832 | |
833 | static inline void trace_escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) |
834 | { |
835 | if (true) { |
836 | _nocheck__trace_escc_update_parameters(channel, speed, parity, data_bits, stop_bits); |
837 | } |
838 | } |
839 | |
840 | #define TRACE_ESCC_MEM_WRITEB_CTRL_BACKEND_DSTATE() ( \ |
841 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_WRITEB_CTRL) || \ |
842 | false) |
843 | |
844 | static inline void _nocheck__trace_escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) |
845 | { |
846 | if (trace_event_get_state(TRACE_ESCC_MEM_WRITEB_CTRL) && qemu_loglevel_mask(LOG_TRACE)) { |
847 | struct timeval _now; |
848 | gettimeofday(&_now, NULL); |
849 | qemu_log("%d@%zu.%06zu:escc_mem_writeb_ctrl " "Write channel %c, reg[%d] = 0x%2.2x" "\n" , |
850 | qemu_get_thread_id(), |
851 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
852 | , channel, reg, val); |
853 | } |
854 | } |
855 | |
856 | static inline void trace_escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) |
857 | { |
858 | if (true) { |
859 | _nocheck__trace_escc_mem_writeb_ctrl(channel, reg, val); |
860 | } |
861 | } |
862 | |
863 | #define TRACE_ESCC_MEM_WRITEB_DATA_BACKEND_DSTATE() ( \ |
864 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_WRITEB_DATA) || \ |
865 | false) |
866 | |
867 | static inline void _nocheck__trace_escc_mem_writeb_data(char channel, uint32_t val) |
868 | { |
869 | if (trace_event_get_state(TRACE_ESCC_MEM_WRITEB_DATA) && qemu_loglevel_mask(LOG_TRACE)) { |
870 | struct timeval _now; |
871 | gettimeofday(&_now, NULL); |
872 | qemu_log("%d@%zu.%06zu:escc_mem_writeb_data " "Write channel %c, ch %d" "\n" , |
873 | qemu_get_thread_id(), |
874 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
875 | , channel, val); |
876 | } |
877 | } |
878 | |
879 | static inline void trace_escc_mem_writeb_data(char channel, uint32_t val) |
880 | { |
881 | if (true) { |
882 | _nocheck__trace_escc_mem_writeb_data(channel, val); |
883 | } |
884 | } |
885 | |
886 | #define TRACE_ESCC_MEM_READB_CTRL_BACKEND_DSTATE() ( \ |
887 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_READB_CTRL) || \ |
888 | false) |
889 | |
890 | static inline void _nocheck__trace_escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) |
891 | { |
892 | if (trace_event_get_state(TRACE_ESCC_MEM_READB_CTRL) && qemu_loglevel_mask(LOG_TRACE)) { |
893 | struct timeval _now; |
894 | gettimeofday(&_now, NULL); |
895 | qemu_log("%d@%zu.%06zu:escc_mem_readb_ctrl " "Read channel %c, reg[%d] = 0x%2.2x" "\n" , |
896 | qemu_get_thread_id(), |
897 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
898 | , channel, reg, val); |
899 | } |
900 | } |
901 | |
902 | static inline void trace_escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) |
903 | { |
904 | if (true) { |
905 | _nocheck__trace_escc_mem_readb_ctrl(channel, reg, val); |
906 | } |
907 | } |
908 | |
909 | #define TRACE_ESCC_MEM_READB_DATA_BACKEND_DSTATE() ( \ |
910 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_MEM_READB_DATA) || \ |
911 | false) |
912 | |
913 | static inline void _nocheck__trace_escc_mem_readb_data(char channel, uint32_t ret) |
914 | { |
915 | if (trace_event_get_state(TRACE_ESCC_MEM_READB_DATA) && qemu_loglevel_mask(LOG_TRACE)) { |
916 | struct timeval _now; |
917 | gettimeofday(&_now, NULL); |
918 | qemu_log("%d@%zu.%06zu:escc_mem_readb_data " "Read channel %c, ch %d" "\n" , |
919 | qemu_get_thread_id(), |
920 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
921 | , channel, ret); |
922 | } |
923 | } |
924 | |
925 | static inline void trace_escc_mem_readb_data(char channel, uint32_t ret) |
926 | { |
927 | if (true) { |
928 | _nocheck__trace_escc_mem_readb_data(channel, ret); |
929 | } |
930 | } |
931 | |
932 | #define TRACE_ESCC_SERIAL_RECEIVE_BYTE_BACKEND_DSTATE() ( \ |
933 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_SERIAL_RECEIVE_BYTE) || \ |
934 | false) |
935 | |
936 | static inline void _nocheck__trace_escc_serial_receive_byte(char channel, int ch) |
937 | { |
938 | if (trace_event_get_state(TRACE_ESCC_SERIAL_RECEIVE_BYTE) && qemu_loglevel_mask(LOG_TRACE)) { |
939 | struct timeval _now; |
940 | gettimeofday(&_now, NULL); |
941 | qemu_log("%d@%zu.%06zu:escc_serial_receive_byte " "channel %c put ch %d" "\n" , |
942 | qemu_get_thread_id(), |
943 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
944 | , channel, ch); |
945 | } |
946 | } |
947 | |
948 | static inline void trace_escc_serial_receive_byte(char channel, int ch) |
949 | { |
950 | if (true) { |
951 | _nocheck__trace_escc_serial_receive_byte(channel, ch); |
952 | } |
953 | } |
954 | |
955 | #define TRACE_ESCC_SUNKBD_EVENT_IN_BACKEND_DSTATE() ( \ |
956 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNKBD_EVENT_IN) || \ |
957 | false) |
958 | |
959 | static inline void _nocheck__trace_escc_sunkbd_event_in(int ch, const char * name, int down) |
960 | { |
961 | if (trace_event_get_state(TRACE_ESCC_SUNKBD_EVENT_IN) && qemu_loglevel_mask(LOG_TRACE)) { |
962 | struct timeval _now; |
963 | gettimeofday(&_now, NULL); |
964 | qemu_log("%d@%zu.%06zu:escc_sunkbd_event_in " "QKeyCode 0x%2.2x [%s], down %d" "\n" , |
965 | qemu_get_thread_id(), |
966 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
967 | , ch, name, down); |
968 | } |
969 | } |
970 | |
971 | static inline void trace_escc_sunkbd_event_in(int ch, const char * name, int down) |
972 | { |
973 | if (true) { |
974 | _nocheck__trace_escc_sunkbd_event_in(ch, name, down); |
975 | } |
976 | } |
977 | |
978 | #define TRACE_ESCC_SUNKBD_EVENT_OUT_BACKEND_DSTATE() ( \ |
979 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNKBD_EVENT_OUT) || \ |
980 | false) |
981 | |
982 | static inline void _nocheck__trace_escc_sunkbd_event_out(int ch) |
983 | { |
984 | if (trace_event_get_state(TRACE_ESCC_SUNKBD_EVENT_OUT) && qemu_loglevel_mask(LOG_TRACE)) { |
985 | struct timeval _now; |
986 | gettimeofday(&_now, NULL); |
987 | qemu_log("%d@%zu.%06zu:escc_sunkbd_event_out " "Translated keycode 0x%2.2x" "\n" , |
988 | qemu_get_thread_id(), |
989 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
990 | , ch); |
991 | } |
992 | } |
993 | |
994 | static inline void trace_escc_sunkbd_event_out(int ch) |
995 | { |
996 | if (true) { |
997 | _nocheck__trace_escc_sunkbd_event_out(ch); |
998 | } |
999 | } |
1000 | |
1001 | #define TRACE_ESCC_KBD_COMMAND_BACKEND_DSTATE() ( \ |
1002 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_KBD_COMMAND) || \ |
1003 | false) |
1004 | |
1005 | static inline void _nocheck__trace_escc_kbd_command(int val) |
1006 | { |
1007 | if (trace_event_get_state(TRACE_ESCC_KBD_COMMAND) && qemu_loglevel_mask(LOG_TRACE)) { |
1008 | struct timeval _now; |
1009 | gettimeofday(&_now, NULL); |
1010 | qemu_log("%d@%zu.%06zu:escc_kbd_command " "Command %d" "\n" , |
1011 | qemu_get_thread_id(), |
1012 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1013 | , val); |
1014 | } |
1015 | } |
1016 | |
1017 | static inline void trace_escc_kbd_command(int val) |
1018 | { |
1019 | if (true) { |
1020 | _nocheck__trace_escc_kbd_command(val); |
1021 | } |
1022 | } |
1023 | |
1024 | #define TRACE_ESCC_SUNMOUSE_EVENT_BACKEND_DSTATE() ( \ |
1025 | trace_event_get_state_dynamic_by_id(TRACE_ESCC_SUNMOUSE_EVENT) || \ |
1026 | false) |
1027 | |
1028 | static inline void _nocheck__trace_escc_sunmouse_event(int dx, int dy, int buttons_state) |
1029 | { |
1030 | if (trace_event_get_state(TRACE_ESCC_SUNMOUSE_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { |
1031 | struct timeval _now; |
1032 | gettimeofday(&_now, NULL); |
1033 | qemu_log("%d@%zu.%06zu:escc_sunmouse_event " "dx=%d dy=%d buttons=0x%01x" "\n" , |
1034 | qemu_get_thread_id(), |
1035 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1036 | , dx, dy, buttons_state); |
1037 | } |
1038 | } |
1039 | |
1040 | static inline void trace_escc_sunmouse_event(int dx, int dy, int buttons_state) |
1041 | { |
1042 | if (true) { |
1043 | _nocheck__trace_escc_sunmouse_event(dx, dy, buttons_state); |
1044 | } |
1045 | } |
1046 | |
1047 | #define TRACE_PL011_IRQ_STATE_BACKEND_DSTATE() ( \ |
1048 | trace_event_get_state_dynamic_by_id(TRACE_PL011_IRQ_STATE) || \ |
1049 | false) |
1050 | |
1051 | static inline void _nocheck__trace_pl011_irq_state(int level) |
1052 | { |
1053 | if (trace_event_get_state(TRACE_PL011_IRQ_STATE) && qemu_loglevel_mask(LOG_TRACE)) { |
1054 | struct timeval _now; |
1055 | gettimeofday(&_now, NULL); |
1056 | qemu_log("%d@%zu.%06zu:pl011_irq_state " "irq state %d" "\n" , |
1057 | qemu_get_thread_id(), |
1058 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1059 | , level); |
1060 | } |
1061 | } |
1062 | |
1063 | static inline void trace_pl011_irq_state(int level) |
1064 | { |
1065 | if (true) { |
1066 | _nocheck__trace_pl011_irq_state(level); |
1067 | } |
1068 | } |
1069 | |
1070 | #define TRACE_PL011_READ_BACKEND_DSTATE() ( \ |
1071 | trace_event_get_state_dynamic_by_id(TRACE_PL011_READ) || \ |
1072 | false) |
1073 | |
1074 | static inline void _nocheck__trace_pl011_read(uint32_t addr, uint32_t value) |
1075 | { |
1076 | if (trace_event_get_state(TRACE_PL011_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
1077 | struct timeval _now; |
1078 | gettimeofday(&_now, NULL); |
1079 | qemu_log("%d@%zu.%06zu:pl011_read " "addr 0x%08x value 0x%08x" "\n" , |
1080 | qemu_get_thread_id(), |
1081 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1082 | , addr, value); |
1083 | } |
1084 | } |
1085 | |
1086 | static inline void trace_pl011_read(uint32_t addr, uint32_t value) |
1087 | { |
1088 | if (true) { |
1089 | _nocheck__trace_pl011_read(addr, value); |
1090 | } |
1091 | } |
1092 | |
1093 | #define TRACE_PL011_READ_FIFO_BACKEND_DSTATE() ( \ |
1094 | trace_event_get_state_dynamic_by_id(TRACE_PL011_READ_FIFO) || \ |
1095 | false) |
1096 | |
1097 | static inline void _nocheck__trace_pl011_read_fifo(int read_count) |
1098 | { |
1099 | if (trace_event_get_state(TRACE_PL011_READ_FIFO) && qemu_loglevel_mask(LOG_TRACE)) { |
1100 | struct timeval _now; |
1101 | gettimeofday(&_now, NULL); |
1102 | qemu_log("%d@%zu.%06zu:pl011_read_fifo " "FIFO read, read_count now %d" "\n" , |
1103 | qemu_get_thread_id(), |
1104 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1105 | , read_count); |
1106 | } |
1107 | } |
1108 | |
1109 | static inline void trace_pl011_read_fifo(int read_count) |
1110 | { |
1111 | if (true) { |
1112 | _nocheck__trace_pl011_read_fifo(read_count); |
1113 | } |
1114 | } |
1115 | |
1116 | #define TRACE_PL011_WRITE_BACKEND_DSTATE() ( \ |
1117 | trace_event_get_state_dynamic_by_id(TRACE_PL011_WRITE) || \ |
1118 | false) |
1119 | |
1120 | static inline void _nocheck__trace_pl011_write(uint32_t addr, uint32_t value) |
1121 | { |
1122 | if (trace_event_get_state(TRACE_PL011_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
1123 | struct timeval _now; |
1124 | gettimeofday(&_now, NULL); |
1125 | qemu_log("%d@%zu.%06zu:pl011_write " "addr 0x%08x value 0x%08x" "\n" , |
1126 | qemu_get_thread_id(), |
1127 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1128 | , addr, value); |
1129 | } |
1130 | } |
1131 | |
1132 | static inline void trace_pl011_write(uint32_t addr, uint32_t value) |
1133 | { |
1134 | if (true) { |
1135 | _nocheck__trace_pl011_write(addr, value); |
1136 | } |
1137 | } |
1138 | |
1139 | #define TRACE_PL011_CAN_RECEIVE_BACKEND_DSTATE() ( \ |
1140 | trace_event_get_state_dynamic_by_id(TRACE_PL011_CAN_RECEIVE) || \ |
1141 | false) |
1142 | |
1143 | static inline void _nocheck__trace_pl011_can_receive(uint32_t lcr, int read_count, int r) |
1144 | { |
1145 | if (trace_event_get_state(TRACE_PL011_CAN_RECEIVE) && qemu_loglevel_mask(LOG_TRACE)) { |
1146 | struct timeval _now; |
1147 | gettimeofday(&_now, NULL); |
1148 | qemu_log("%d@%zu.%06zu:pl011_can_receive " "LCR 0x%08x read_count %d returning %d" "\n" , |
1149 | qemu_get_thread_id(), |
1150 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1151 | , lcr, read_count, r); |
1152 | } |
1153 | } |
1154 | |
1155 | static inline void trace_pl011_can_receive(uint32_t lcr, int read_count, int r) |
1156 | { |
1157 | if (true) { |
1158 | _nocheck__trace_pl011_can_receive(lcr, read_count, r); |
1159 | } |
1160 | } |
1161 | |
1162 | #define TRACE_PL011_PUT_FIFO_BACKEND_DSTATE() ( \ |
1163 | trace_event_get_state_dynamic_by_id(TRACE_PL011_PUT_FIFO) || \ |
1164 | false) |
1165 | |
1166 | static inline void _nocheck__trace_pl011_put_fifo(uint32_t c, int read_count) |
1167 | { |
1168 | if (trace_event_get_state(TRACE_PL011_PUT_FIFO) && qemu_loglevel_mask(LOG_TRACE)) { |
1169 | struct timeval _now; |
1170 | gettimeofday(&_now, NULL); |
1171 | qemu_log("%d@%zu.%06zu:pl011_put_fifo " "new char 0x%x read_count now %d" "\n" , |
1172 | qemu_get_thread_id(), |
1173 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1174 | , c, read_count); |
1175 | } |
1176 | } |
1177 | |
1178 | static inline void trace_pl011_put_fifo(uint32_t c, int read_count) |
1179 | { |
1180 | if (true) { |
1181 | _nocheck__trace_pl011_put_fifo(c, read_count); |
1182 | } |
1183 | } |
1184 | |
1185 | #define TRACE_PL011_PUT_FIFO_FULL_BACKEND_DSTATE() ( \ |
1186 | trace_event_get_state_dynamic_by_id(TRACE_PL011_PUT_FIFO_FULL) || \ |
1187 | false) |
1188 | |
1189 | static inline void _nocheck__trace_pl011_put_fifo_full(void) |
1190 | { |
1191 | if (trace_event_get_state(TRACE_PL011_PUT_FIFO_FULL) && qemu_loglevel_mask(LOG_TRACE)) { |
1192 | struct timeval _now; |
1193 | gettimeofday(&_now, NULL); |
1194 | qemu_log("%d@%zu.%06zu:pl011_put_fifo_full " "FIFO now full, RXFF set" "\n" , |
1195 | qemu_get_thread_id(), |
1196 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1197 | ); |
1198 | } |
1199 | } |
1200 | |
1201 | static inline void trace_pl011_put_fifo_full(void) |
1202 | { |
1203 | if (true) { |
1204 | _nocheck__trace_pl011_put_fifo_full(); |
1205 | } |
1206 | } |
1207 | |
1208 | #define TRACE_CMSDK_APB_UART_READ_BACKEND_DSTATE() ( \ |
1209 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_READ) || \ |
1210 | false) |
1211 | |
1212 | static inline void _nocheck__trace_cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) |
1213 | { |
1214 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
1215 | struct timeval _now; |
1216 | gettimeofday(&_now, NULL); |
1217 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_read " "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n" , |
1218 | qemu_get_thread_id(), |
1219 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1220 | , offset, data, size); |
1221 | } |
1222 | } |
1223 | |
1224 | static inline void trace_cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) |
1225 | { |
1226 | if (true) { |
1227 | _nocheck__trace_cmsdk_apb_uart_read(offset, data, size); |
1228 | } |
1229 | } |
1230 | |
1231 | #define TRACE_CMSDK_APB_UART_WRITE_BACKEND_DSTATE() ( \ |
1232 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_WRITE) || \ |
1233 | false) |
1234 | |
1235 | static inline void _nocheck__trace_cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) |
1236 | { |
1237 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
1238 | struct timeval _now; |
1239 | gettimeofday(&_now, NULL); |
1240 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_write " "CMSDK APB UART write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n" , |
1241 | qemu_get_thread_id(), |
1242 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1243 | , offset, data, size); |
1244 | } |
1245 | } |
1246 | |
1247 | static inline void trace_cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) |
1248 | { |
1249 | if (true) { |
1250 | _nocheck__trace_cmsdk_apb_uart_write(offset, data, size); |
1251 | } |
1252 | } |
1253 | |
1254 | #define TRACE_CMSDK_APB_UART_RESET_BACKEND_DSTATE() ( \ |
1255 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_RESET) || \ |
1256 | false) |
1257 | |
1258 | static inline void _nocheck__trace_cmsdk_apb_uart_reset(void) |
1259 | { |
1260 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_RESET) && qemu_loglevel_mask(LOG_TRACE)) { |
1261 | struct timeval _now; |
1262 | gettimeofday(&_now, NULL); |
1263 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_reset " "CMSDK APB UART: reset" "\n" , |
1264 | qemu_get_thread_id(), |
1265 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1266 | ); |
1267 | } |
1268 | } |
1269 | |
1270 | static inline void trace_cmsdk_apb_uart_reset(void) |
1271 | { |
1272 | if (true) { |
1273 | _nocheck__trace_cmsdk_apb_uart_reset(); |
1274 | } |
1275 | } |
1276 | |
1277 | #define TRACE_CMSDK_APB_UART_RECEIVE_BACKEND_DSTATE() ( \ |
1278 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_RECEIVE) || \ |
1279 | false) |
1280 | |
1281 | static inline void _nocheck__trace_cmsdk_apb_uart_receive(uint8_t c) |
1282 | { |
1283 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_RECEIVE) && qemu_loglevel_mask(LOG_TRACE)) { |
1284 | struct timeval _now; |
1285 | gettimeofday(&_now, NULL); |
1286 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_receive " "CMSDK APB UART: got character 0x%x from backend" "\n" , |
1287 | qemu_get_thread_id(), |
1288 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1289 | , c); |
1290 | } |
1291 | } |
1292 | |
1293 | static inline void trace_cmsdk_apb_uart_receive(uint8_t c) |
1294 | { |
1295 | if (true) { |
1296 | _nocheck__trace_cmsdk_apb_uart_receive(c); |
1297 | } |
1298 | } |
1299 | |
1300 | #define TRACE_CMSDK_APB_UART_TX_PENDING_BACKEND_DSTATE() ( \ |
1301 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_TX_PENDING) || \ |
1302 | false) |
1303 | |
1304 | static inline void _nocheck__trace_cmsdk_apb_uart_tx_pending(void) |
1305 | { |
1306 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_TX_PENDING) && qemu_loglevel_mask(LOG_TRACE)) { |
1307 | struct timeval _now; |
1308 | gettimeofday(&_now, NULL); |
1309 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_tx_pending " "CMSDK APB UART: character send to backend pending" "\n" , |
1310 | qemu_get_thread_id(), |
1311 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1312 | ); |
1313 | } |
1314 | } |
1315 | |
1316 | static inline void trace_cmsdk_apb_uart_tx_pending(void) |
1317 | { |
1318 | if (true) { |
1319 | _nocheck__trace_cmsdk_apb_uart_tx_pending(); |
1320 | } |
1321 | } |
1322 | |
1323 | #define TRACE_CMSDK_APB_UART_TX_BACKEND_DSTATE() ( \ |
1324 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_TX) || \ |
1325 | false) |
1326 | |
1327 | static inline void _nocheck__trace_cmsdk_apb_uart_tx(uint8_t c) |
1328 | { |
1329 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_TX) && qemu_loglevel_mask(LOG_TRACE)) { |
1330 | struct timeval _now; |
1331 | gettimeofday(&_now, NULL); |
1332 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_tx " "CMSDK APB UART: character 0x%x sent to backend" "\n" , |
1333 | qemu_get_thread_id(), |
1334 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1335 | , c); |
1336 | } |
1337 | } |
1338 | |
1339 | static inline void trace_cmsdk_apb_uart_tx(uint8_t c) |
1340 | { |
1341 | if (true) { |
1342 | _nocheck__trace_cmsdk_apb_uart_tx(c); |
1343 | } |
1344 | } |
1345 | |
1346 | #define TRACE_CMSDK_APB_UART_SET_PARAMS_BACKEND_DSTATE() ( \ |
1347 | trace_event_get_state_dynamic_by_id(TRACE_CMSDK_APB_UART_SET_PARAMS) || \ |
1348 | false) |
1349 | |
1350 | static inline void _nocheck__trace_cmsdk_apb_uart_set_params(int speed) |
1351 | { |
1352 | if (trace_event_get_state(TRACE_CMSDK_APB_UART_SET_PARAMS) && qemu_loglevel_mask(LOG_TRACE)) { |
1353 | struct timeval _now; |
1354 | gettimeofday(&_now, NULL); |
1355 | qemu_log("%d@%zu.%06zu:cmsdk_apb_uart_set_params " "CMSDK APB UART: params set to %d 8N1" "\n" , |
1356 | qemu_get_thread_id(), |
1357 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1358 | , speed); |
1359 | } |
1360 | } |
1361 | |
1362 | static inline void trace_cmsdk_apb_uart_set_params(int speed) |
1363 | { |
1364 | if (true) { |
1365 | _nocheck__trace_cmsdk_apb_uart_set_params(speed); |
1366 | } |
1367 | } |
1368 | |
1369 | #define TRACE_NRF51_UART_READ_BACKEND_DSTATE() ( \ |
1370 | trace_event_get_state_dynamic_by_id(TRACE_NRF51_UART_READ) || \ |
1371 | false) |
1372 | |
1373 | static inline void _nocheck__trace_nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) |
1374 | { |
1375 | if (trace_event_get_state(TRACE_NRF51_UART_READ) && qemu_loglevel_mask(LOG_TRACE)) { |
1376 | struct timeval _now; |
1377 | gettimeofday(&_now, NULL); |
1378 | qemu_log("%d@%zu.%06zu:nrf51_uart_read " "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u" "\n" , |
1379 | qemu_get_thread_id(), |
1380 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1381 | , addr, r, size); |
1382 | } |
1383 | } |
1384 | |
1385 | static inline void trace_nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) |
1386 | { |
1387 | if (true) { |
1388 | _nocheck__trace_nrf51_uart_read(addr, r, size); |
1389 | } |
1390 | } |
1391 | |
1392 | #define TRACE_NRF51_UART_WRITE_BACKEND_DSTATE() ( \ |
1393 | trace_event_get_state_dynamic_by_id(TRACE_NRF51_UART_WRITE) || \ |
1394 | false) |
1395 | |
1396 | static inline void _nocheck__trace_nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) |
1397 | { |
1398 | if (trace_event_get_state(TRACE_NRF51_UART_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { |
1399 | struct timeval _now; |
1400 | gettimeofday(&_now, NULL); |
1401 | qemu_log("%d@%zu.%06zu:nrf51_uart_write " "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u" "\n" , |
1402 | qemu_get_thread_id(), |
1403 | (size_t)_now.tv_sec, (size_t)_now.tv_usec |
1404 | , addr, value, size); |
1405 | } |
1406 | } |
1407 | |
1408 | static inline void trace_nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) |
1409 | { |
1410 | if (true) { |
1411 | _nocheck__trace_nrf51_uart_write(addr, value, size); |
1412 | } |
1413 | } |
1414 | #endif /* TRACE_HW_CHAR_GENERATED_TRACERS_H */ |
1415 | |