1 | /* This file is autogenerated by tracetool, do not edit. */ |
2 | |
3 | #include "qemu/osdep.h" |
4 | #include "qemu/module.h" |
5 | #include "trace.h" |
6 | |
7 | uint16_t _TRACE_EBUS_ISA_IRQ_HANDLER_DSTATE; |
8 | uint16_t _TRACE_SUN4U_IOMMU_MEM_READ_DSTATE; |
9 | uint16_t _TRACE_SUN4U_IOMMU_MEM_WRITE_DSTATE; |
10 | uint16_t _TRACE_SUN4U_IOMMU_TRANSLATE_DSTATE; |
11 | uint16_t _TRACE_SPARC64_CPU_CHECK_IRQS_RESET_IRQ_DSTATE; |
12 | uint16_t _TRACE_SPARC64_CPU_CHECK_IRQS_NOSET_IRQ_DSTATE; |
13 | uint16_t _TRACE_SPARC64_CPU_CHECK_IRQS_SET_IRQ_DSTATE; |
14 | uint16_t _TRACE_SPARC64_CPU_CHECK_IRQS_DISABLED_DSTATE; |
15 | uint16_t _TRACE_SPARC64_CPU_IVEC_RAISE_IRQ_DSTATE; |
16 | uint16_t _TRACE_SPARC64_CPU_IVEC_LOWER_IRQ_DSTATE; |
17 | uint16_t _TRACE_SPARC64_CPU_TICK_IRQ_DISABLED_DSTATE; |
18 | uint16_t _TRACE_SPARC64_CPU_TICK_IRQ_FIRE_DSTATE; |
19 | uint16_t _TRACE_SPARC64_CPU_STICK_IRQ_DISABLED_DSTATE; |
20 | uint16_t _TRACE_SPARC64_CPU_STICK_IRQ_FIRE_DSTATE; |
21 | uint16_t _TRACE_SPARC64_CPU_HSTICK_IRQ_DISABLED_DSTATE; |
22 | uint16_t _TRACE_SPARC64_CPU_HSTICK_IRQ_FIRE_DSTATE; |
23 | uint16_t _TRACE_SPARC64_CPU_TICK_SET_COUNT_DSTATE; |
24 | uint16_t _TRACE_SPARC64_CPU_TICK_GET_COUNT_DSTATE; |
25 | uint16_t _TRACE_SPARC64_CPU_TICK_SET_LIMIT_DSTATE; |
26 | uint16_t _TRACE_SPARC64_CPU_TICK_SET_LIMIT_ZERO_DSTATE; |
27 | TraceEvent _TRACE_EBUS_ISA_IRQ_HANDLER_EVENT = { |
28 | .id = 0, |
29 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
30 | .name = "ebus_isa_irq_handler" , |
31 | .sstate = TRACE_EBUS_ISA_IRQ_HANDLER_ENABLED, |
32 | .dstate = &_TRACE_EBUS_ISA_IRQ_HANDLER_DSTATE |
33 | }; |
34 | TraceEvent _TRACE_SUN4U_IOMMU_MEM_READ_EVENT = { |
35 | .id = 0, |
36 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
37 | .name = "sun4u_iommu_mem_read" , |
38 | .sstate = TRACE_SUN4U_IOMMU_MEM_READ_ENABLED, |
39 | .dstate = &_TRACE_SUN4U_IOMMU_MEM_READ_DSTATE |
40 | }; |
41 | TraceEvent _TRACE_SUN4U_IOMMU_MEM_WRITE_EVENT = { |
42 | .id = 0, |
43 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
44 | .name = "sun4u_iommu_mem_write" , |
45 | .sstate = TRACE_SUN4U_IOMMU_MEM_WRITE_ENABLED, |
46 | .dstate = &_TRACE_SUN4U_IOMMU_MEM_WRITE_DSTATE |
47 | }; |
48 | TraceEvent _TRACE_SUN4U_IOMMU_TRANSLATE_EVENT = { |
49 | .id = 0, |
50 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
51 | .name = "sun4u_iommu_translate" , |
52 | .sstate = TRACE_SUN4U_IOMMU_TRANSLATE_ENABLED, |
53 | .dstate = &_TRACE_SUN4U_IOMMU_TRANSLATE_DSTATE |
54 | }; |
55 | TraceEvent _TRACE_SPARC64_CPU_CHECK_IRQS_RESET_IRQ_EVENT = { |
56 | .id = 0, |
57 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
58 | .name = "sparc64_cpu_check_irqs_reset_irq" , |
59 | .sstate = TRACE_SPARC64_CPU_CHECK_IRQS_RESET_IRQ_ENABLED, |
60 | .dstate = &_TRACE_SPARC64_CPU_CHECK_IRQS_RESET_IRQ_DSTATE |
61 | }; |
62 | TraceEvent _TRACE_SPARC64_CPU_CHECK_IRQS_NOSET_IRQ_EVENT = { |
63 | .id = 0, |
64 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
65 | .name = "sparc64_cpu_check_irqs_noset_irq" , |
66 | .sstate = TRACE_SPARC64_CPU_CHECK_IRQS_NOSET_IRQ_ENABLED, |
67 | .dstate = &_TRACE_SPARC64_CPU_CHECK_IRQS_NOSET_IRQ_DSTATE |
68 | }; |
69 | TraceEvent _TRACE_SPARC64_CPU_CHECK_IRQS_SET_IRQ_EVENT = { |
70 | .id = 0, |
71 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
72 | .name = "sparc64_cpu_check_irqs_set_irq" , |
73 | .sstate = TRACE_SPARC64_CPU_CHECK_IRQS_SET_IRQ_ENABLED, |
74 | .dstate = &_TRACE_SPARC64_CPU_CHECK_IRQS_SET_IRQ_DSTATE |
75 | }; |
76 | TraceEvent _TRACE_SPARC64_CPU_CHECK_IRQS_DISABLED_EVENT = { |
77 | .id = 0, |
78 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
79 | .name = "sparc64_cpu_check_irqs_disabled" , |
80 | .sstate = TRACE_SPARC64_CPU_CHECK_IRQS_DISABLED_ENABLED, |
81 | .dstate = &_TRACE_SPARC64_CPU_CHECK_IRQS_DISABLED_DSTATE |
82 | }; |
83 | TraceEvent _TRACE_SPARC64_CPU_IVEC_RAISE_IRQ_EVENT = { |
84 | .id = 0, |
85 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
86 | .name = "sparc64_cpu_ivec_raise_irq" , |
87 | .sstate = TRACE_SPARC64_CPU_IVEC_RAISE_IRQ_ENABLED, |
88 | .dstate = &_TRACE_SPARC64_CPU_IVEC_RAISE_IRQ_DSTATE |
89 | }; |
90 | TraceEvent _TRACE_SPARC64_CPU_IVEC_LOWER_IRQ_EVENT = { |
91 | .id = 0, |
92 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
93 | .name = "sparc64_cpu_ivec_lower_irq" , |
94 | .sstate = TRACE_SPARC64_CPU_IVEC_LOWER_IRQ_ENABLED, |
95 | .dstate = &_TRACE_SPARC64_CPU_IVEC_LOWER_IRQ_DSTATE |
96 | }; |
97 | TraceEvent _TRACE_SPARC64_CPU_TICK_IRQ_DISABLED_EVENT = { |
98 | .id = 0, |
99 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
100 | .name = "sparc64_cpu_tick_irq_disabled" , |
101 | .sstate = TRACE_SPARC64_CPU_TICK_IRQ_DISABLED_ENABLED, |
102 | .dstate = &_TRACE_SPARC64_CPU_TICK_IRQ_DISABLED_DSTATE |
103 | }; |
104 | TraceEvent _TRACE_SPARC64_CPU_TICK_IRQ_FIRE_EVENT = { |
105 | .id = 0, |
106 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
107 | .name = "sparc64_cpu_tick_irq_fire" , |
108 | .sstate = TRACE_SPARC64_CPU_TICK_IRQ_FIRE_ENABLED, |
109 | .dstate = &_TRACE_SPARC64_CPU_TICK_IRQ_FIRE_DSTATE |
110 | }; |
111 | TraceEvent _TRACE_SPARC64_CPU_STICK_IRQ_DISABLED_EVENT = { |
112 | .id = 0, |
113 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
114 | .name = "sparc64_cpu_stick_irq_disabled" , |
115 | .sstate = TRACE_SPARC64_CPU_STICK_IRQ_DISABLED_ENABLED, |
116 | .dstate = &_TRACE_SPARC64_CPU_STICK_IRQ_DISABLED_DSTATE |
117 | }; |
118 | TraceEvent _TRACE_SPARC64_CPU_STICK_IRQ_FIRE_EVENT = { |
119 | .id = 0, |
120 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
121 | .name = "sparc64_cpu_stick_irq_fire" , |
122 | .sstate = TRACE_SPARC64_CPU_STICK_IRQ_FIRE_ENABLED, |
123 | .dstate = &_TRACE_SPARC64_CPU_STICK_IRQ_FIRE_DSTATE |
124 | }; |
125 | TraceEvent _TRACE_SPARC64_CPU_HSTICK_IRQ_DISABLED_EVENT = { |
126 | .id = 0, |
127 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
128 | .name = "sparc64_cpu_hstick_irq_disabled" , |
129 | .sstate = TRACE_SPARC64_CPU_HSTICK_IRQ_DISABLED_ENABLED, |
130 | .dstate = &_TRACE_SPARC64_CPU_HSTICK_IRQ_DISABLED_DSTATE |
131 | }; |
132 | TraceEvent _TRACE_SPARC64_CPU_HSTICK_IRQ_FIRE_EVENT = { |
133 | .id = 0, |
134 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
135 | .name = "sparc64_cpu_hstick_irq_fire" , |
136 | .sstate = TRACE_SPARC64_CPU_HSTICK_IRQ_FIRE_ENABLED, |
137 | .dstate = &_TRACE_SPARC64_CPU_HSTICK_IRQ_FIRE_DSTATE |
138 | }; |
139 | TraceEvent _TRACE_SPARC64_CPU_TICK_SET_COUNT_EVENT = { |
140 | .id = 0, |
141 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
142 | .name = "sparc64_cpu_tick_set_count" , |
143 | .sstate = TRACE_SPARC64_CPU_TICK_SET_COUNT_ENABLED, |
144 | .dstate = &_TRACE_SPARC64_CPU_TICK_SET_COUNT_DSTATE |
145 | }; |
146 | TraceEvent _TRACE_SPARC64_CPU_TICK_GET_COUNT_EVENT = { |
147 | .id = 0, |
148 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
149 | .name = "sparc64_cpu_tick_get_count" , |
150 | .sstate = TRACE_SPARC64_CPU_TICK_GET_COUNT_ENABLED, |
151 | .dstate = &_TRACE_SPARC64_CPU_TICK_GET_COUNT_DSTATE |
152 | }; |
153 | TraceEvent _TRACE_SPARC64_CPU_TICK_SET_LIMIT_EVENT = { |
154 | .id = 0, |
155 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
156 | .name = "sparc64_cpu_tick_set_limit" , |
157 | .sstate = TRACE_SPARC64_CPU_TICK_SET_LIMIT_ENABLED, |
158 | .dstate = &_TRACE_SPARC64_CPU_TICK_SET_LIMIT_DSTATE |
159 | }; |
160 | TraceEvent _TRACE_SPARC64_CPU_TICK_SET_LIMIT_ZERO_EVENT = { |
161 | .id = 0, |
162 | .vcpu_id = TRACE_VCPU_EVENT_NONE, |
163 | .name = "sparc64_cpu_tick_set_limit_zero" , |
164 | .sstate = TRACE_SPARC64_CPU_TICK_SET_LIMIT_ZERO_ENABLED, |
165 | .dstate = &_TRACE_SPARC64_CPU_TICK_SET_LIMIT_ZERO_DSTATE |
166 | }; |
167 | TraceEvent *hw_sparc64_trace_events[] = { |
168 | &_TRACE_EBUS_ISA_IRQ_HANDLER_EVENT, |
169 | &_TRACE_SUN4U_IOMMU_MEM_READ_EVENT, |
170 | &_TRACE_SUN4U_IOMMU_MEM_WRITE_EVENT, |
171 | &_TRACE_SUN4U_IOMMU_TRANSLATE_EVENT, |
172 | &_TRACE_SPARC64_CPU_CHECK_IRQS_RESET_IRQ_EVENT, |
173 | &_TRACE_SPARC64_CPU_CHECK_IRQS_NOSET_IRQ_EVENT, |
174 | &_TRACE_SPARC64_CPU_CHECK_IRQS_SET_IRQ_EVENT, |
175 | &_TRACE_SPARC64_CPU_CHECK_IRQS_DISABLED_EVENT, |
176 | &_TRACE_SPARC64_CPU_IVEC_RAISE_IRQ_EVENT, |
177 | &_TRACE_SPARC64_CPU_IVEC_LOWER_IRQ_EVENT, |
178 | &_TRACE_SPARC64_CPU_TICK_IRQ_DISABLED_EVENT, |
179 | &_TRACE_SPARC64_CPU_TICK_IRQ_FIRE_EVENT, |
180 | &_TRACE_SPARC64_CPU_STICK_IRQ_DISABLED_EVENT, |
181 | &_TRACE_SPARC64_CPU_STICK_IRQ_FIRE_EVENT, |
182 | &_TRACE_SPARC64_CPU_HSTICK_IRQ_DISABLED_EVENT, |
183 | &_TRACE_SPARC64_CPU_HSTICK_IRQ_FIRE_EVENT, |
184 | &_TRACE_SPARC64_CPU_TICK_SET_COUNT_EVENT, |
185 | &_TRACE_SPARC64_CPU_TICK_GET_COUNT_EVENT, |
186 | &_TRACE_SPARC64_CPU_TICK_SET_LIMIT_EVENT, |
187 | &_TRACE_SPARC64_CPU_TICK_SET_LIMIT_ZERO_EVENT, |
188 | NULL, |
189 | }; |
190 | |
191 | static void trace_hw_sparc64_register_events(void) |
192 | { |
193 | trace_event_register_group(hw_sparc64_trace_events); |
194 | } |
195 | trace_init(trace_hw_sparc64_register_events) |
196 | |