1/*
2 * Calxeda Highbank SoC emulation
3 *
4 * Copyright (c) 2010-2012 Calxeda
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qapi/error.h"
23#include "hw/sysbus.h"
24#include "migration/vmstate.h"
25#include "hw/arm/boot.h"
26#include "hw/loader.h"
27#include "net/net.h"
28#include "sysemu/kvm.h"
29#include "sysemu/runstate.h"
30#include "sysemu/sysemu.h"
31#include "hw/boards.h"
32#include "exec/address-spaces.h"
33#include "qemu/error-report.h"
34#include "hw/char/pl011.h"
35#include "hw/ide/ahci.h"
36#include "hw/cpu/a9mpcore.h"
37#include "hw/cpu/a15mpcore.h"
38#include "qemu/log.h"
39
40#define SMP_BOOT_ADDR 0x100
41#define SMP_BOOT_REG 0x40
42#define MPCORE_PERIPHBASE 0xfff10000
43
44#define MVBAR_ADDR 0x200
45#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
46
47#define NIRQ_GIC 160
48
49/* Board init. */
50
51static void hb_write_board_setup(ARMCPU *cpu,
52 const struct arm_boot_info *info)
53{
54 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
55}
56
57static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
58{
59 int n;
60 uint32_t smpboot[] = {
61 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
62 0xe210000f, /* ands r0, r0, #0x0f */
63 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
64 0xe0830200, /* add r0, r3, r0, lsl #4 */
65 0xe59f2024, /* ldr r2, privbase */
66 0xe3a01001, /* mov r1, #1 */
67 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
68 0xe3a010ff, /* mov r1, #0xff */
69 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
70 0xf57ff04f, /* dsb */
71 0xe320f003, /* wfi */
72 0xe5901000, /* ldr r1, [r0] */
73 0xe1110001, /* tst r1, r1 */
74 0x0afffffb, /* beq <wfi> */
75 0xe12fff11, /* bx r1 */
76 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
77 };
78 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
79 smpboot[n] = tswap32(smpboot[n]);
80 }
81 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
82}
83
84static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
85{
86 CPUARMState *env = &cpu->env;
87
88 switch (info->nb_cpus) {
89 case 4:
90 address_space_stl_notdirty(&address_space_memory,
91 SMP_BOOT_REG + 0x30, 0,
92 MEMTXATTRS_UNSPECIFIED, NULL);
93 case 3:
94 address_space_stl_notdirty(&address_space_memory,
95 SMP_BOOT_REG + 0x20, 0,
96 MEMTXATTRS_UNSPECIFIED, NULL);
97 case 2:
98 address_space_stl_notdirty(&address_space_memory,
99 SMP_BOOT_REG + 0x10, 0,
100 MEMTXATTRS_UNSPECIFIED, NULL);
101 env->regs[15] = SMP_BOOT_ADDR;
102 break;
103 default:
104 break;
105 }
106}
107
108#define NUM_REGS 0x200
109static void hb_regs_write(void *opaque, hwaddr offset,
110 uint64_t value, unsigned size)
111{
112 uint32_t *regs = opaque;
113
114 if (offset == 0xf00) {
115 if (value == 1 || value == 2) {
116 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
117 } else if (value == 3) {
118 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
119 }
120 }
121
122 if (offset / 4 >= NUM_REGS) {
123 qemu_log_mask(LOG_GUEST_ERROR,
124 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
125 return;
126 }
127 regs[offset / 4] = value;
128}
129
130static uint64_t hb_regs_read(void *opaque, hwaddr offset,
131 unsigned size)
132{
133 uint32_t value;
134 uint32_t *regs = opaque;
135
136 if (offset / 4 >= NUM_REGS) {
137 qemu_log_mask(LOG_GUEST_ERROR,
138 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
139 return 0;
140 }
141 value = regs[offset / 4];
142
143 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
144 value |= 0x30000000;
145 }
146
147 return value;
148}
149
150static const MemoryRegionOps hb_mem_ops = {
151 .read = hb_regs_read,
152 .write = hb_regs_write,
153 .endianness = DEVICE_NATIVE_ENDIAN,
154};
155
156#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
157#define HIGHBANK_REGISTERS(obj) \
158 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
159
160typedef struct {
161 /*< private >*/
162 SysBusDevice parent_obj;
163 /*< public >*/
164
165 MemoryRegion iomem;
166 uint32_t regs[NUM_REGS];
167} HighbankRegsState;
168
169static VMStateDescription vmstate_highbank_regs = {
170 .name = "highbank-regs",
171 .version_id = 0,
172 .minimum_version_id = 0,
173 .fields = (VMStateField[]) {
174 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
175 VMSTATE_END_OF_LIST(),
176 },
177};
178
179static void highbank_regs_reset(DeviceState *dev)
180{
181 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
182
183 s->regs[0x40] = 0x05F20121;
184 s->regs[0x41] = 0x2;
185 s->regs[0x42] = 0x05F30121;
186 s->regs[0x43] = 0x05F40121;
187}
188
189static void highbank_regs_init(Object *obj)
190{
191 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
192 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
193
194 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
195 "highbank_regs", 0x1000);
196 sysbus_init_mmio(dev, &s->iomem);
197}
198
199static void highbank_regs_class_init(ObjectClass *klass, void *data)
200{
201 DeviceClass *dc = DEVICE_CLASS(klass);
202
203 dc->desc = "Calxeda Highbank registers";
204 dc->vmsd = &vmstate_highbank_regs;
205 dc->reset = highbank_regs_reset;
206}
207
208static const TypeInfo highbank_regs_info = {
209 .name = TYPE_HIGHBANK_REGISTERS,
210 .parent = TYPE_SYS_BUS_DEVICE,
211 .instance_size = sizeof(HighbankRegsState),
212 .instance_init = highbank_regs_init,
213 .class_init = highbank_regs_class_init,
214};
215
216static void highbank_regs_register_types(void)
217{
218 type_register_static(&highbank_regs_info);
219}
220
221type_init(highbank_regs_register_types)
222
223static struct arm_boot_info highbank_binfo;
224
225enum cxmachines {
226 CALXEDA_HIGHBANK,
227 CALXEDA_MIDWAY,
228};
229
230/* ram_size must be set to match the upper bound of memory in the
231 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
232 * normally 0xff900000 or -m 4089. When running this board on a
233 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
234 * device tree and pass -m 2047 to QEMU.
235 */
236static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
237{
238 ram_addr_t ram_size = machine->ram_size;
239 DeviceState *dev = NULL;
240 SysBusDevice *busdev;
241 qemu_irq pic[128];
242 int n;
243 unsigned int smp_cpus = machine->smp.cpus;
244 qemu_irq cpu_irq[4];
245 qemu_irq cpu_fiq[4];
246 qemu_irq cpu_virq[4];
247 qemu_irq cpu_vfiq[4];
248 MemoryRegion *sysram;
249 MemoryRegion *dram;
250 MemoryRegion *sysmem;
251 char *sysboot_filename;
252
253 switch (machine_id) {
254 case CALXEDA_HIGHBANK:
255 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
256 break;
257 case CALXEDA_MIDWAY:
258 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
259 break;
260 default:
261 assert(0);
262 }
263
264 for (n = 0; n < smp_cpus; n++) {
265 Object *cpuobj;
266 ARMCPU *cpu;
267
268 cpuobj = object_new(machine->cpu_type);
269 cpu = ARM_CPU(cpuobj);
270
271 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
272 "psci-conduit", &error_abort);
273
274 if (n) {
275 /* Secondary CPUs start in PSCI powered-down state */
276 object_property_set_bool(cpuobj, true,
277 "start-powered-off", &error_abort);
278 }
279
280 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
281 object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
282 "reset-cbar", &error_abort);
283 }
284 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
285 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
286 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
287 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
288 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
289 }
290
291 sysmem = get_system_memory();
292 dram = g_new(MemoryRegion, 1);
293 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
294 /* SDRAM at address zero. */
295 memory_region_add_subregion(sysmem, 0, dram);
296
297 sysram = g_new(MemoryRegion, 1);
298 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
299 &error_fatal);
300 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
301 if (bios_name != NULL) {
302 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
303 if (sysboot_filename != NULL) {
304 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
305 error_report("Unable to load %s", bios_name);
306 exit(1);
307 }
308 g_free(sysboot_filename);
309 } else {
310 error_report("Unable to find %s", bios_name);
311 exit(1);
312 }
313 }
314
315 switch (machine_id) {
316 case CALXEDA_HIGHBANK:
317 dev = qdev_create(NULL, "l2x0");
318 qdev_init_nofail(dev);
319 busdev = SYS_BUS_DEVICE(dev);
320 sysbus_mmio_map(busdev, 0, 0xfff12000);
321
322 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
323 break;
324 case CALXEDA_MIDWAY:
325 dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
326 break;
327 }
328 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
329 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
330 qdev_init_nofail(dev);
331 busdev = SYS_BUS_DEVICE(dev);
332 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
333 for (n = 0; n < smp_cpus; n++) {
334 sysbus_connect_irq(busdev, n, cpu_irq[n]);
335 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
336 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
337 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
338 }
339
340 for (n = 0; n < 128; n++) {
341 pic[n] = qdev_get_gpio_in(dev, n);
342 }
343
344 dev = qdev_create(NULL, "sp804");
345 qdev_prop_set_uint32(dev, "freq0", 150000000);
346 qdev_prop_set_uint32(dev, "freq1", 150000000);
347 qdev_init_nofail(dev);
348 busdev = SYS_BUS_DEVICE(dev);
349 sysbus_mmio_map(busdev, 0, 0xfff34000);
350 sysbus_connect_irq(busdev, 0, pic[18]);
351 pl011_create(0xfff36000, pic[20], serial_hd(0));
352
353 dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
354 qdev_init_nofail(dev);
355 busdev = SYS_BUS_DEVICE(dev);
356 sysbus_mmio_map(busdev, 0, 0xfff3c000);
357
358 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
359 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
360 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
361 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
362 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
363 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
364
365 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
366
367 if (nd_table[0].used) {
368 qemu_check_nic_model(&nd_table[0], "xgmac");
369 dev = qdev_create(NULL, "xgmac");
370 qdev_set_nic_properties(dev, &nd_table[0]);
371 qdev_init_nofail(dev);
372 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
373 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
374 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
376
377 qemu_check_nic_model(&nd_table[1], "xgmac");
378 dev = qdev_create(NULL, "xgmac");
379 qdev_set_nic_properties(dev, &nd_table[1]);
380 qdev_init_nofail(dev);
381 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
382 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
385 }
386
387 /* TODO create and connect IDE devices for ide_drive_get() */
388
389 highbank_binfo.ram_size = ram_size;
390 /* highbank requires a dtb in order to boot, and the dtb will override
391 * the board ID. The following value is ignored, so set it to -1 to be
392 * clear that the value is meaningless.
393 */
394 highbank_binfo.board_id = -1;
395 highbank_binfo.nb_cpus = smp_cpus;
396 highbank_binfo.loader_start = 0;
397 highbank_binfo.write_secondary_boot = hb_write_secondary;
398 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
399 if (!kvm_enabled()) {
400 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
401 highbank_binfo.write_board_setup = hb_write_board_setup;
402 highbank_binfo.secure_board_setup = true;
403 } else {
404 warn_report("cannot load built-in Monitor support "
405 "if KVM is enabled. Some guests (such as Linux) "
406 "may not boot.");
407 }
408
409 arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
410}
411
412static void highbank_init(MachineState *machine)
413{
414 calxeda_init(machine, CALXEDA_HIGHBANK);
415}
416
417static void midway_init(MachineState *machine)
418{
419 calxeda_init(machine, CALXEDA_MIDWAY);
420}
421
422static void highbank_class_init(ObjectClass *oc, void *data)
423{
424 MachineClass *mc = MACHINE_CLASS(oc);
425
426 mc->desc = "Calxeda Highbank (ECX-1000)";
427 mc->init = highbank_init;
428 mc->block_default_type = IF_IDE;
429 mc->units_per_default_bus = 1;
430 mc->max_cpus = 4;
431 mc->ignore_memory_transaction_failures = true;
432}
433
434static const TypeInfo highbank_type = {
435 .name = MACHINE_TYPE_NAME("highbank"),
436 .parent = TYPE_MACHINE,
437 .class_init = highbank_class_init,
438};
439
440static void midway_class_init(ObjectClass *oc, void *data)
441{
442 MachineClass *mc = MACHINE_CLASS(oc);
443
444 mc->desc = "Calxeda Midway (ECX-2000)";
445 mc->init = midway_init;
446 mc->block_default_type = IF_IDE;
447 mc->units_per_default_bus = 1;
448 mc->max_cpus = 4;
449 mc->ignore_memory_transaction_failures = true;
450}
451
452static const TypeInfo midway_type = {
453 .name = MACHINE_TYPE_NAME("midway"),
454 .parent = TYPE_MACHINE,
455 .class_init = midway_class_init,
456};
457
458static void calxeda_machines_init(void)
459{
460 type_register_static(&highbank_type);
461 type_register_static(&midway_type);
462}
463
464type_init(calxeda_machines_init)
465