1 | /* |
2 | * Nordic Semiconductor nRF51 SoC |
3 | * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf |
4 | * |
5 | * Copyright 2018 Joel Stanley <joel@jms.id.au> |
6 | * |
7 | * This code is licensed under the GPL version 2 or later. See |
8 | * the COPYING file in the top-level directory. |
9 | */ |
10 | |
11 | #include "qemu/osdep.h" |
12 | #include "qapi/error.h" |
13 | #include "hw/arm/boot.h" |
14 | #include "hw/sysbus.h" |
15 | #include "hw/misc/unimp.h" |
16 | #include "exec/address-spaces.h" |
17 | #include "qemu/log.h" |
18 | #include "cpu.h" |
19 | |
20 | #include "hw/arm/nrf51.h" |
21 | #include "hw/arm/nrf51_soc.h" |
22 | |
23 | /* |
24 | * The size and base is for the NRF51822 part. If other parts |
25 | * are supported in the future, add a sub-class of NRF51SoC for |
26 | * the specific variants |
27 | */ |
28 | #define NRF51822_FLASH_PAGES 256 |
29 | #define NRF51822_SRAM_PAGES 16 |
30 | #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) |
31 | #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) |
32 | |
33 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) |
34 | |
35 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) |
36 | { |
37 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n" , |
38 | __func__, addr, size); |
39 | return 1; |
40 | } |
41 | |
42 | static void clock_write(void *opaque, hwaddr addr, uint64_t data, |
43 | unsigned int size) |
44 | { |
45 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n" , |
46 | __func__, addr, data, size); |
47 | } |
48 | |
49 | static const MemoryRegionOps clock_ops = { |
50 | .read = clock_read, |
51 | .write = clock_write |
52 | }; |
53 | |
54 | |
55 | static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) |
56 | { |
57 | NRF51State *s = NRF51_SOC(dev_soc); |
58 | MemoryRegion *mr; |
59 | Error *err = NULL; |
60 | uint8_t i = 0; |
61 | hwaddr base_addr = 0; |
62 | |
63 | if (!s->board_memory) { |
64 | error_setg(errp, "memory property was not set" ); |
65 | return; |
66 | } |
67 | |
68 | object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory" , |
69 | &err); |
70 | if (err) { |
71 | error_propagate(errp, err); |
72 | return; |
73 | } |
74 | object_property_set_bool(OBJECT(&s->cpu), true, "realized" , &err); |
75 | if (err) { |
76 | error_propagate(errp, err); |
77 | return; |
78 | } |
79 | |
80 | memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); |
81 | |
82 | memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram" , s->sram_size, |
83 | &err); |
84 | if (err) { |
85 | error_propagate(errp, err); |
86 | return; |
87 | } |
88 | memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); |
89 | |
90 | /* UART */ |
91 | object_property_set_bool(OBJECT(&s->uart), true, "realized" , &err); |
92 | if (err) { |
93 | error_propagate(errp, err); |
94 | return; |
95 | } |
96 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); |
97 | memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); |
98 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, |
99 | qdev_get_gpio_in(DEVICE(&s->cpu), |
100 | BASE_TO_IRQ(NRF51_UART_BASE))); |
101 | |
102 | /* RNG */ |
103 | object_property_set_bool(OBJECT(&s->rng), true, "realized" , &err); |
104 | if (err) { |
105 | error_propagate(errp, err); |
106 | return; |
107 | } |
108 | |
109 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); |
110 | memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); |
111 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, |
112 | qdev_get_gpio_in(DEVICE(&s->cpu), |
113 | BASE_TO_IRQ(NRF51_RNG_BASE))); |
114 | |
115 | /* UICR, FICR, NVMC, FLASH */ |
116 | object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size" , |
117 | &err); |
118 | if (err) { |
119 | error_propagate(errp, err); |
120 | return; |
121 | } |
122 | |
123 | object_property_set_bool(OBJECT(&s->nvm), true, "realized" , &err); |
124 | if (err) { |
125 | error_propagate(errp, err); |
126 | return; |
127 | } |
128 | |
129 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); |
130 | memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); |
131 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); |
132 | memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); |
133 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); |
134 | memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); |
135 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); |
136 | memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); |
137 | |
138 | /* GPIO */ |
139 | object_property_set_bool(OBJECT(&s->gpio), true, "realized" , &err); |
140 | if (err) { |
141 | error_propagate(errp, err); |
142 | return; |
143 | } |
144 | |
145 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); |
146 | memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); |
147 | |
148 | /* Pass all GPIOs to the SOC layer so they are available to the board */ |
149 | qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); |
150 | |
151 | /* TIMER */ |
152 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { |
153 | object_property_set_bool(OBJECT(&s->timer[i]), true, "realized" , &err); |
154 | if (err) { |
155 | error_propagate(errp, err); |
156 | return; |
157 | } |
158 | |
159 | base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; |
160 | |
161 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); |
162 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, |
163 | qdev_get_gpio_in(DEVICE(&s->cpu), |
164 | BASE_TO_IRQ(base_addr))); |
165 | } |
166 | |
167 | /* STUB Peripherals */ |
168 | memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, |
169 | "nrf51_soc.clock" , 0x1000); |
170 | memory_region_add_subregion_overlap(&s->container, |
171 | NRF51_IOMEM_BASE, &s->clock, -1); |
172 | |
173 | create_unimplemented_device("nrf51_soc.io" , NRF51_IOMEM_BASE, |
174 | NRF51_IOMEM_SIZE); |
175 | create_unimplemented_device("nrf51_soc.private" , |
176 | NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); |
177 | } |
178 | |
179 | static void nrf51_soc_init(Object *obj) |
180 | { |
181 | uint8_t i = 0; |
182 | |
183 | NRF51State *s = NRF51_SOC(obj); |
184 | |
185 | memory_region_init(&s->container, obj, "nrf51-container" , UINT64_MAX); |
186 | |
187 | sysbus_init_child_obj(OBJECT(s), "armv6m" , OBJECT(&s->cpu), sizeof(s->cpu), |
188 | TYPE_ARMV7M); |
189 | qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type" , |
190 | ARM_CPU_TYPE_NAME("cortex-m0" )); |
191 | qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq" , 32); |
192 | |
193 | sysbus_init_child_obj(obj, "uart" , &s->uart, sizeof(s->uart), |
194 | TYPE_NRF51_UART); |
195 | object_property_add_alias(obj, "serial0" , OBJECT(&s->uart), "chardev" , |
196 | &error_abort); |
197 | |
198 | sysbus_init_child_obj(obj, "rng" , &s->rng, sizeof(s->rng), |
199 | TYPE_NRF51_RNG); |
200 | |
201 | sysbus_init_child_obj(obj, "nvm" , &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM); |
202 | |
203 | sysbus_init_child_obj(obj, "gpio" , &s->gpio, sizeof(s->gpio), |
204 | TYPE_NRF51_GPIO); |
205 | |
206 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { |
207 | sysbus_init_child_obj(obj, "timer[*]" , &s->timer[i], |
208 | sizeof(s->timer[i]), TYPE_NRF51_TIMER); |
209 | |
210 | } |
211 | } |
212 | |
213 | static Property nrf51_soc_properties[] = { |
214 | DEFINE_PROP_LINK("memory" , NRF51State, board_memory, TYPE_MEMORY_REGION, |
215 | MemoryRegion *), |
216 | DEFINE_PROP_UINT32("sram-size" , NRF51State, sram_size, NRF51822_SRAM_SIZE), |
217 | DEFINE_PROP_UINT32("flash-size" , NRF51State, flash_size, |
218 | NRF51822_FLASH_SIZE), |
219 | DEFINE_PROP_END_OF_LIST(), |
220 | }; |
221 | |
222 | static void nrf51_soc_class_init(ObjectClass *klass, void *data) |
223 | { |
224 | DeviceClass *dc = DEVICE_CLASS(klass); |
225 | |
226 | dc->realize = nrf51_soc_realize; |
227 | dc->props = nrf51_soc_properties; |
228 | } |
229 | |
230 | static const TypeInfo nrf51_soc_info = { |
231 | .name = TYPE_NRF51_SOC, |
232 | .parent = TYPE_SYS_BUS_DEVICE, |
233 | .instance_size = sizeof(NRF51State), |
234 | .instance_init = nrf51_soc_init, |
235 | .class_init = nrf51_soc_class_init, |
236 | }; |
237 | |
238 | static void nrf51_soc_types(void) |
239 | { |
240 | type_register_static(&nrf51_soc_info); |
241 | } |
242 | type_init(nrf51_soc_types) |
243 | |