1/*
2 * Intel XScale PXA Programmable Interrupt Controller.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
6 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 *
8 * This code is licensed under the GPL.
9 */
10
11#include "qemu/osdep.h"
12#include "qemu/module.h"
13#include "cpu.h"
14#include "hw/arm/pxa.h"
15#include "hw/sysbus.h"
16#include "migration/vmstate.h"
17
18#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
19#define ICMR 0x04 /* Interrupt Controller Mask register */
20#define ICLR 0x08 /* Interrupt Controller Level register */
21#define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
22#define ICPR 0x10 /* Interrupt Controller Pending register */
23#define ICCR 0x14 /* Interrupt Controller Control register */
24#define ICHP 0x18 /* Interrupt Controller Highest Priority register */
25#define IPR0 0x1c /* Interrupt Controller Priority register 0 */
26#define IPR31 0x98 /* Interrupt Controller Priority register 31 */
27#define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
28#define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
29#define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
30#define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
31#define ICPR2 0xac /* Interrupt Controller Pending register 2 */
32#define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
33#define IPR39 0xcc /* Interrupt Controller Priority register 39 */
34
35#define PXA2XX_PIC_SRCS 40
36
37#define TYPE_PXA2XX_PIC "pxa2xx_pic"
38#define PXA2XX_PIC(obj) \
39 OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
40
41typedef struct {
42 /*< private >*/
43 SysBusDevice parent_obj;
44 /*< public >*/
45
46 MemoryRegion iomem;
47 ARMCPU *cpu;
48 uint32_t int_enabled[2];
49 uint32_t int_pending[2];
50 uint32_t is_fiq[2];
51 uint32_t int_idle;
52 uint32_t priority[PXA2XX_PIC_SRCS];
53} PXA2xxPICState;
54
55static void pxa2xx_pic_update(void *opaque)
56{
57 uint32_t mask[2];
58 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
59 CPUState *cpu = CPU(s->cpu);
60
61 if (cpu->halted) {
62 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
63 mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
64 if (mask[0] || mask[1]) {
65 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
66 }
67 }
68
69 mask[0] = s->int_pending[0] & s->int_enabled[0];
70 mask[1] = s->int_pending[1] & s->int_enabled[1];
71
72 if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
73 cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
74 } else {
75 cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
76 }
77
78 if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
79 cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
80 } else {
81 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
82 }
83}
84
85/* Note: Here level means state of the signal on a pin, not
86 * IRQ/FIQ distinction as in PXA Developer Manual. */
87static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
88{
89 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
90 int int_set = (irq >= 32);
91 irq &= 31;
92
93 if (level)
94 s->int_pending[int_set] |= 1 << irq;
95 else
96 s->int_pending[int_set] &= ~(1 << irq);
97
98 pxa2xx_pic_update(opaque);
99}
100
101static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
102 int i, int_set, irq;
103 uint32_t bit, mask[2];
104 uint32_t ichp = 0x003f003f; /* Both IDs invalid */
105
106 mask[0] = s->int_pending[0] & s->int_enabled[0];
107 mask[1] = s->int_pending[1] & s->int_enabled[1];
108
109 for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
110 irq = s->priority[i] & 0x3f;
111 if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
112 /* Source peripheral ID is valid. */
113 bit = 1 << (irq & 31);
114 int_set = (irq >= 32);
115
116 if (mask[int_set] & bit & s->is_fiq[int_set]) {
117 /* FIQ asserted */
118 ichp &= 0xffff0000;
119 ichp |= (1 << 15) | irq;
120 }
121
122 if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
123 /* IRQ asserted */
124 ichp &= 0x0000ffff;
125 ichp |= (1U << 31) | (irq << 16);
126 }
127 }
128 }
129
130 return ichp;
131}
132
133static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
134 unsigned size)
135{
136 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
137
138 switch (offset) {
139 case ICIP: /* IRQ Pending register */
140 return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
141 case ICIP2: /* IRQ Pending register 2 */
142 return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
143 case ICMR: /* Mask register */
144 return s->int_enabled[0];
145 case ICMR2: /* Mask register 2 */
146 return s->int_enabled[1];
147 case ICLR: /* Level register */
148 return s->is_fiq[0];
149 case ICLR2: /* Level register 2 */
150 return s->is_fiq[1];
151 case ICCR: /* Idle mask */
152 return (s->int_idle == 0);
153 case ICFP: /* FIQ Pending register */
154 return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
155 case ICFP2: /* FIQ Pending register 2 */
156 return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
157 case ICPR: /* Pending register */
158 return s->int_pending[0];
159 case ICPR2: /* Pending register 2 */
160 return s->int_pending[1];
161 case IPR0 ... IPR31:
162 return s->priority[0 + ((offset - IPR0 ) >> 2)];
163 case IPR32 ... IPR39:
164 return s->priority[32 + ((offset - IPR32) >> 2)];
165 case ICHP: /* Highest Priority register */
166 return pxa2xx_pic_highest(s);
167 default:
168 printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
169 return 0;
170 }
171}
172
173static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
174 uint64_t value, unsigned size)
175{
176 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
177
178 switch (offset) {
179 case ICMR: /* Mask register */
180 s->int_enabled[0] = value;
181 break;
182 case ICMR2: /* Mask register 2 */
183 s->int_enabled[1] = value;
184 break;
185 case ICLR: /* Level register */
186 s->is_fiq[0] = value;
187 break;
188 case ICLR2: /* Level register 2 */
189 s->is_fiq[1] = value;
190 break;
191 case ICCR: /* Idle mask */
192 s->int_idle = (value & 1) ? 0 : ~0;
193 break;
194 case IPR0 ... IPR31:
195 s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
196 break;
197 case IPR32 ... IPR39:
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
199 break;
200 default:
201 printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
202 return;
203 }
204 pxa2xx_pic_update(opaque);
205}
206
207/* Interrupt Controller Coprocessor Space Register Mapping */
208static const int pxa2xx_cp_reg_map[0x10] = {
209 [0x0 ... 0xf] = -1,
210 [0x0] = ICIP,
211 [0x1] = ICMR,
212 [0x2] = ICLR,
213 [0x3] = ICFP,
214 [0x4] = ICPR,
215 [0x5] = ICHP,
216 [0x6] = ICIP2,
217 [0x7] = ICMR2,
218 [0x8] = ICLR2,
219 [0x9] = ICFP2,
220 [0xa] = ICPR2,
221};
222
223static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
224{
225 int offset = pxa2xx_cp_reg_map[ri->crn];
226 return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
227}
228
229static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
230 uint64_t value)
231{
232 int offset = pxa2xx_cp_reg_map[ri->crn];
233 pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
234}
235
236#define REGINFO_FOR_PIC_CP(NAME, CRN) \
237 { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
238 .access = PL1_RW, .type = ARM_CP_IO, \
239 .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
240
241static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
242 REGINFO_FOR_PIC_CP("ICIP", 0),
243 REGINFO_FOR_PIC_CP("ICMR", 1),
244 REGINFO_FOR_PIC_CP("ICLR", 2),
245 REGINFO_FOR_PIC_CP("ICFP", 3),
246 REGINFO_FOR_PIC_CP("ICPR", 4),
247 REGINFO_FOR_PIC_CP("ICHP", 5),
248 REGINFO_FOR_PIC_CP("ICIP2", 6),
249 REGINFO_FOR_PIC_CP("ICMR2", 7),
250 REGINFO_FOR_PIC_CP("ICLR2", 8),
251 REGINFO_FOR_PIC_CP("ICFP2", 9),
252 REGINFO_FOR_PIC_CP("ICPR2", 0xa),
253 REGINFO_SENTINEL
254};
255
256static const MemoryRegionOps pxa2xx_pic_ops = {
257 .read = pxa2xx_pic_mem_read,
258 .write = pxa2xx_pic_mem_write,
259 .endianness = DEVICE_NATIVE_ENDIAN,
260};
261
262static int pxa2xx_pic_post_load(void *opaque, int version_id)
263{
264 pxa2xx_pic_update(opaque);
265 return 0;
266}
267
268DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
269{
270 DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
271 PXA2xxPICState *s = PXA2XX_PIC(dev);
272
273 s->cpu = cpu;
274
275 s->int_pending[0] = 0;
276 s->int_pending[1] = 0;
277 s->int_enabled[0] = 0;
278 s->int_enabled[1] = 0;
279 s->is_fiq[0] = 0;
280 s->is_fiq[1] = 0;
281
282 qdev_init_nofail(dev);
283
284 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
285
286 /* Enable IC memory-mapped registers access. */
287 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
288 "pxa2xx-pic", 0x00100000);
289 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
290 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
291
292 /* Enable IC coprocessor access. */
293 define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
294
295 return dev;
296}
297
298static VMStateDescription vmstate_pxa2xx_pic_regs = {
299 .name = "pxa2xx_pic",
300 .version_id = 0,
301 .minimum_version_id = 0,
302 .post_load = pxa2xx_pic_post_load,
303 .fields = (VMStateField[]) {
304 VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
305 VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
306 VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
307 VMSTATE_UINT32(int_idle, PXA2xxPICState),
308 VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
309 VMSTATE_END_OF_LIST(),
310 },
311};
312
313static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
314{
315 DeviceClass *dc = DEVICE_CLASS(klass);
316
317 dc->desc = "PXA2xx PIC";
318 dc->vmsd = &vmstate_pxa2xx_pic_regs;
319}
320
321static const TypeInfo pxa2xx_pic_info = {
322 .name = TYPE_PXA2XX_PIC,
323 .parent = TYPE_SYS_BUS_DEVICE,
324 .instance_size = sizeof(PXA2xxPICState),
325 .class_init = pxa2xx_pic_class_init,
326};
327
328static void pxa2xx_pic_register_types(void)
329{
330 type_register_static(&pxa2xx_pic_info);
331}
332
333type_init(pxa2xx_pic_register_types)
334