1/*
2 * SABRELITE Board System emulation.
3 *
4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This code is licensed under the GPL, version 2 or later.
7 * See the file `COPYING' in the top level directory.
8 *
9 * It (partially) emulates a sabrelite board, with a Freescale
10 * i.MX6 SoC
11 */
12
13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "hw/arm/fsl-imx6.h"
16#include "hw/boards.h"
17#include "hw/qdev-properties.h"
18#include "sysemu/sysemu.h"
19#include "qemu/error-report.h"
20#include "sysemu/qtest.h"
21
22typedef struct IMX6Sabrelite {
23 FslIMX6State soc;
24 MemoryRegion ram;
25} IMX6Sabrelite;
26
27static struct arm_boot_info sabrelite_binfo = {
28 /* DDR memory start */
29 .loader_start = FSL_IMX6_MMDC_ADDR,
30 /* No board ID, we boot from DT tree */
31 .board_id = -1,
32};
33
34/* No need to do any particular setup for secondary boot */
35static void sabrelite_write_secondary(ARMCPU *cpu,
36 const struct arm_boot_info *info)
37{
38}
39
40/* Secondary cores are reset through SRC device */
41static void sabrelite_reset_secondary(ARMCPU *cpu,
42 const struct arm_boot_info *info)
43{
44}
45
46static void sabrelite_init(MachineState *machine)
47{
48 IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
49 Error *err = NULL;
50
51 /* Check the amount of memory is compatible with the SOC */
52 if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
53 error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
54 machine->ram_size, FSL_IMX6_MMDC_SIZE);
55 exit(1);
56 }
57
58 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
59 TYPE_FSL_IMX6, &error_abort, NULL);
60
61 object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
62 if (err != NULL) {
63 error_report("%s", error_get_pretty(err));
64 exit(1);
65 }
66
67 memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
68 machine->ram_size);
69 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
70 &s->ram);
71
72 {
73 /*
74 * TODO: Ideally we would expose the chip select and spi bus on the
75 * SoC object using alias properties; then we would not need to
76 * directly access the underlying spi device object.
77 */
78 /* Add the sst25vf016b NOR FLASH memory to first SPI */
79 Object *spi_dev;
80
81 spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
82 if (spi_dev) {
83 SSIBus *spi_bus;
84
85 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
86 if (spi_bus) {
87 DeviceState *flash_dev;
88 qemu_irq cs_line;
89 DriveInfo *dinfo = drive_get_next(IF_MTD);
90
91 flash_dev = ssi_create_slave_no_init(spi_bus, "sst25vf016b");
92 if (dinfo) {
93 qdev_prop_set_drive(flash_dev, "drive",
94 blk_by_legacy_dinfo(dinfo),
95 &error_fatal);
96 }
97 qdev_init_nofail(flash_dev);
98
99 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
100 sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
101 }
102 }
103 }
104
105 sabrelite_binfo.ram_size = machine->ram_size;
106 sabrelite_binfo.nb_cpus = machine->smp.cpus;
107 sabrelite_binfo.secure_boot = true;
108 sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
109 sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
110
111 if (!qtest_enabled()) {
112 arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo);
113 }
114}
115
116static void sabrelite_machine_init(MachineClass *mc)
117{
118 mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
119 mc->init = sabrelite_init;
120 mc->max_cpus = FSL_IMX6_NUM_CPUS;
121 mc->ignore_memory_transaction_failures = true;
122}
123
124DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
125