1 | /* |
2 | * Luminary Micro Stellaris peripherals |
3 | * |
4 | * Copyright (c) 2006 CodeSourcery. |
5 | * Written by Paul Brook |
6 | * |
7 | * This code is licensed under the GPL. |
8 | */ |
9 | |
10 | #include "qemu/osdep.h" |
11 | #include "qapi/error.h" |
12 | #include "hw/sysbus.h" |
13 | #include "hw/ssi/ssi.h" |
14 | #include "hw/arm/boot.h" |
15 | #include "qemu/timer.h" |
16 | #include "hw/i2c/i2c.h" |
17 | #include "net/net.h" |
18 | #include "hw/boards.h" |
19 | #include "qemu/log.h" |
20 | #include "exec/address-spaces.h" |
21 | #include "sysemu/runstate.h" |
22 | #include "sysemu/sysemu.h" |
23 | #include "hw/arm/armv7m.h" |
24 | #include "hw/char/pl011.h" |
25 | #include "hw/input/gamepad.h" |
26 | #include "hw/irq.h" |
27 | #include "hw/watchdog/cmsdk-apb-watchdog.h" |
28 | #include "migration/vmstate.h" |
29 | #include "hw/misc/unimp.h" |
30 | #include "cpu.h" |
31 | |
32 | #define GPIO_A 0 |
33 | #define GPIO_B 1 |
34 | #define GPIO_C 2 |
35 | #define GPIO_D 3 |
36 | #define GPIO_E 4 |
37 | #define GPIO_F 5 |
38 | #define GPIO_G 6 |
39 | |
40 | #define BP_OLED_I2C 0x01 |
41 | #define BP_OLED_SSI 0x02 |
42 | #define BP_GAMEPAD 0x04 |
43 | |
44 | #define NUM_IRQ_LINES 64 |
45 | |
46 | typedef const struct { |
47 | const char *name; |
48 | uint32_t did0; |
49 | uint32_t did1; |
50 | uint32_t dc0; |
51 | uint32_t dc1; |
52 | uint32_t dc2; |
53 | uint32_t dc3; |
54 | uint32_t dc4; |
55 | uint32_t peripherals; |
56 | } stellaris_board_info; |
57 | |
58 | /* General purpose timer module. */ |
59 | |
60 | #define TYPE_STELLARIS_GPTM "stellaris-gptm" |
61 | #define STELLARIS_GPTM(obj) \ |
62 | OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) |
63 | |
64 | typedef struct gptm_state { |
65 | SysBusDevice parent_obj; |
66 | |
67 | MemoryRegion iomem; |
68 | uint32_t config; |
69 | uint32_t mode[2]; |
70 | uint32_t control; |
71 | uint32_t state; |
72 | uint32_t mask; |
73 | uint32_t load[2]; |
74 | uint32_t match[2]; |
75 | uint32_t prescale[2]; |
76 | uint32_t match_prescale[2]; |
77 | uint32_t rtc; |
78 | int64_t tick[2]; |
79 | struct gptm_state *opaque[2]; |
80 | QEMUTimer *timer[2]; |
81 | /* The timers have an alternate output used to trigger the ADC. */ |
82 | qemu_irq trigger; |
83 | qemu_irq irq; |
84 | } gptm_state; |
85 | |
86 | static void gptm_update_irq(gptm_state *s) |
87 | { |
88 | int level; |
89 | level = (s->state & s->mask) != 0; |
90 | qemu_set_irq(s->irq, level); |
91 | } |
92 | |
93 | static void gptm_stop(gptm_state *s, int n) |
94 | { |
95 | timer_del(s->timer[n]); |
96 | } |
97 | |
98 | static void gptm_reload(gptm_state *s, int n, int reset) |
99 | { |
100 | int64_t tick; |
101 | if (reset) |
102 | tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
103 | else |
104 | tick = s->tick[n]; |
105 | |
106 | if (s->config == 0) { |
107 | /* 32-bit CountDown. */ |
108 | uint32_t count; |
109 | count = s->load[0] | (s->load[1] << 16); |
110 | tick += (int64_t)count * system_clock_scale; |
111 | } else if (s->config == 1) { |
112 | /* 32-bit RTC. 1Hz tick. */ |
113 | tick += NANOSECONDS_PER_SECOND; |
114 | } else if (s->mode[n] == 0xa) { |
115 | /* PWM mode. Not implemented. */ |
116 | } else { |
117 | qemu_log_mask(LOG_UNIMP, |
118 | "GPTM: 16-bit timer mode unimplemented: 0x%x\n" , |
119 | s->mode[n]); |
120 | return; |
121 | } |
122 | s->tick[n] = tick; |
123 | timer_mod(s->timer[n], tick); |
124 | } |
125 | |
126 | static void gptm_tick(void *opaque) |
127 | { |
128 | gptm_state **p = (gptm_state **)opaque; |
129 | gptm_state *s; |
130 | int n; |
131 | |
132 | s = *p; |
133 | n = p - s->opaque; |
134 | if (s->config == 0) { |
135 | s->state |= 1; |
136 | if ((s->control & 0x20)) { |
137 | /* Output trigger. */ |
138 | qemu_irq_pulse(s->trigger); |
139 | } |
140 | if (s->mode[0] & 1) { |
141 | /* One-shot. */ |
142 | s->control &= ~1; |
143 | } else { |
144 | /* Periodic. */ |
145 | gptm_reload(s, 0, 0); |
146 | } |
147 | } else if (s->config == 1) { |
148 | /* RTC. */ |
149 | uint32_t match; |
150 | s->rtc++; |
151 | match = s->match[0] | (s->match[1] << 16); |
152 | if (s->rtc > match) |
153 | s->rtc = 0; |
154 | if (s->rtc == 0) { |
155 | s->state |= 8; |
156 | } |
157 | gptm_reload(s, 0, 0); |
158 | } else if (s->mode[n] == 0xa) { |
159 | /* PWM mode. Not implemented. */ |
160 | } else { |
161 | qemu_log_mask(LOG_UNIMP, |
162 | "GPTM: 16-bit timer mode unimplemented: 0x%x\n" , |
163 | s->mode[n]); |
164 | } |
165 | gptm_update_irq(s); |
166 | } |
167 | |
168 | static uint64_t gptm_read(void *opaque, hwaddr offset, |
169 | unsigned size) |
170 | { |
171 | gptm_state *s = (gptm_state *)opaque; |
172 | |
173 | switch (offset) { |
174 | case 0x00: /* CFG */ |
175 | return s->config; |
176 | case 0x04: /* TAMR */ |
177 | return s->mode[0]; |
178 | case 0x08: /* TBMR */ |
179 | return s->mode[1]; |
180 | case 0x0c: /* CTL */ |
181 | return s->control; |
182 | case 0x18: /* IMR */ |
183 | return s->mask; |
184 | case 0x1c: /* RIS */ |
185 | return s->state; |
186 | case 0x20: /* MIS */ |
187 | return s->state & s->mask; |
188 | case 0x24: /* CR */ |
189 | return 0; |
190 | case 0x28: /* TAILR */ |
191 | return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); |
192 | case 0x2c: /* TBILR */ |
193 | return s->load[1]; |
194 | case 0x30: /* TAMARCHR */ |
195 | return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); |
196 | case 0x34: /* TBMATCHR */ |
197 | return s->match[1]; |
198 | case 0x38: /* TAPR */ |
199 | return s->prescale[0]; |
200 | case 0x3c: /* TBPR */ |
201 | return s->prescale[1]; |
202 | case 0x40: /* TAPMR */ |
203 | return s->match_prescale[0]; |
204 | case 0x44: /* TBPMR */ |
205 | return s->match_prescale[1]; |
206 | case 0x48: /* TAR */ |
207 | if (s->config == 1) { |
208 | return s->rtc; |
209 | } |
210 | qemu_log_mask(LOG_UNIMP, |
211 | "GPTM: read of TAR but timer read not supported\n" ); |
212 | return 0; |
213 | case 0x4c: /* TBR */ |
214 | qemu_log_mask(LOG_UNIMP, |
215 | "GPTM: read of TBR but timer read not supported\n" ); |
216 | return 0; |
217 | default: |
218 | qemu_log_mask(LOG_GUEST_ERROR, |
219 | "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n" , |
220 | offset); |
221 | return 0; |
222 | } |
223 | } |
224 | |
225 | static void gptm_write(void *opaque, hwaddr offset, |
226 | uint64_t value, unsigned size) |
227 | { |
228 | gptm_state *s = (gptm_state *)opaque; |
229 | uint32_t oldval; |
230 | |
231 | /* The timers should be disabled before changing the configuration. |
232 | We take advantage of this and defer everything until the timer |
233 | is enabled. */ |
234 | switch (offset) { |
235 | case 0x00: /* CFG */ |
236 | s->config = value; |
237 | break; |
238 | case 0x04: /* TAMR */ |
239 | s->mode[0] = value; |
240 | break; |
241 | case 0x08: /* TBMR */ |
242 | s->mode[1] = value; |
243 | break; |
244 | case 0x0c: /* CTL */ |
245 | oldval = s->control; |
246 | s->control = value; |
247 | /* TODO: Implement pause. */ |
248 | if ((oldval ^ value) & 1) { |
249 | if (value & 1) { |
250 | gptm_reload(s, 0, 1); |
251 | } else { |
252 | gptm_stop(s, 0); |
253 | } |
254 | } |
255 | if (((oldval ^ value) & 0x100) && s->config >= 4) { |
256 | if (value & 0x100) { |
257 | gptm_reload(s, 1, 1); |
258 | } else { |
259 | gptm_stop(s, 1); |
260 | } |
261 | } |
262 | break; |
263 | case 0x18: /* IMR */ |
264 | s->mask = value & 0x77; |
265 | gptm_update_irq(s); |
266 | break; |
267 | case 0x24: /* CR */ |
268 | s->state &= ~value; |
269 | break; |
270 | case 0x28: /* TAILR */ |
271 | s->load[0] = value & 0xffff; |
272 | if (s->config < 4) { |
273 | s->load[1] = value >> 16; |
274 | } |
275 | break; |
276 | case 0x2c: /* TBILR */ |
277 | s->load[1] = value & 0xffff; |
278 | break; |
279 | case 0x30: /* TAMARCHR */ |
280 | s->match[0] = value & 0xffff; |
281 | if (s->config < 4) { |
282 | s->match[1] = value >> 16; |
283 | } |
284 | break; |
285 | case 0x34: /* TBMATCHR */ |
286 | s->match[1] = value >> 16; |
287 | break; |
288 | case 0x38: /* TAPR */ |
289 | s->prescale[0] = value; |
290 | break; |
291 | case 0x3c: /* TBPR */ |
292 | s->prescale[1] = value; |
293 | break; |
294 | case 0x40: /* TAPMR */ |
295 | s->match_prescale[0] = value; |
296 | break; |
297 | case 0x44: /* TBPMR */ |
298 | s->match_prescale[0] = value; |
299 | break; |
300 | default: |
301 | qemu_log_mask(LOG_GUEST_ERROR, |
302 | "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n" , |
303 | offset); |
304 | } |
305 | gptm_update_irq(s); |
306 | } |
307 | |
308 | static const MemoryRegionOps gptm_ops = { |
309 | .read = gptm_read, |
310 | .write = gptm_write, |
311 | .endianness = DEVICE_NATIVE_ENDIAN, |
312 | }; |
313 | |
314 | static const VMStateDescription vmstate_stellaris_gptm = { |
315 | .name = "stellaris_gptm" , |
316 | .version_id = 1, |
317 | .minimum_version_id = 1, |
318 | .fields = (VMStateField[]) { |
319 | VMSTATE_UINT32(config, gptm_state), |
320 | VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), |
321 | VMSTATE_UINT32(control, gptm_state), |
322 | VMSTATE_UINT32(state, gptm_state), |
323 | VMSTATE_UINT32(mask, gptm_state), |
324 | VMSTATE_UNUSED(8), |
325 | VMSTATE_UINT32_ARRAY(load, gptm_state, 2), |
326 | VMSTATE_UINT32_ARRAY(match, gptm_state, 2), |
327 | VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), |
328 | VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), |
329 | VMSTATE_UINT32(rtc, gptm_state), |
330 | VMSTATE_INT64_ARRAY(tick, gptm_state, 2), |
331 | VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), |
332 | VMSTATE_END_OF_LIST() |
333 | } |
334 | }; |
335 | |
336 | static void stellaris_gptm_init(Object *obj) |
337 | { |
338 | DeviceState *dev = DEVICE(obj); |
339 | gptm_state *s = STELLARIS_GPTM(obj); |
340 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
341 | |
342 | sysbus_init_irq(sbd, &s->irq); |
343 | qdev_init_gpio_out(dev, &s->trigger, 1); |
344 | |
345 | memory_region_init_io(&s->iomem, obj, &gptm_ops, s, |
346 | "gptm" , 0x1000); |
347 | sysbus_init_mmio(sbd, &s->iomem); |
348 | |
349 | s->opaque[0] = s->opaque[1] = s; |
350 | s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); |
351 | s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); |
352 | } |
353 | |
354 | |
355 | /* System controller. */ |
356 | |
357 | typedef struct { |
358 | MemoryRegion iomem; |
359 | uint32_t pborctl; |
360 | uint32_t ldopctl; |
361 | uint32_t int_status; |
362 | uint32_t int_mask; |
363 | uint32_t resc; |
364 | uint32_t rcc; |
365 | uint32_t rcc2; |
366 | uint32_t rcgc[3]; |
367 | uint32_t scgc[3]; |
368 | uint32_t dcgc[3]; |
369 | uint32_t clkvclr; |
370 | uint32_t ldoarst; |
371 | uint32_t user0; |
372 | uint32_t user1; |
373 | qemu_irq irq; |
374 | stellaris_board_info *board; |
375 | } ssys_state; |
376 | |
377 | static void ssys_update(ssys_state *s) |
378 | { |
379 | qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); |
380 | } |
381 | |
382 | static uint32_t pllcfg_sandstorm[16] = { |
383 | 0x31c0, /* 1 Mhz */ |
384 | 0x1ae0, /* 1.8432 Mhz */ |
385 | 0x18c0, /* 2 Mhz */ |
386 | 0xd573, /* 2.4576 Mhz */ |
387 | 0x37a6, /* 3.57954 Mhz */ |
388 | 0x1ae2, /* 3.6864 Mhz */ |
389 | 0x0c40, /* 4 Mhz */ |
390 | 0x98bc, /* 4.906 Mhz */ |
391 | 0x935b, /* 4.9152 Mhz */ |
392 | 0x09c0, /* 5 Mhz */ |
393 | 0x4dee, /* 5.12 Mhz */ |
394 | 0x0c41, /* 6 Mhz */ |
395 | 0x75db, /* 6.144 Mhz */ |
396 | 0x1ae6, /* 7.3728 Mhz */ |
397 | 0x0600, /* 8 Mhz */ |
398 | 0x585b /* 8.192 Mhz */ |
399 | }; |
400 | |
401 | static uint32_t pllcfg_fury[16] = { |
402 | 0x3200, /* 1 Mhz */ |
403 | 0x1b20, /* 1.8432 Mhz */ |
404 | 0x1900, /* 2 Mhz */ |
405 | 0xf42b, /* 2.4576 Mhz */ |
406 | 0x37e3, /* 3.57954 Mhz */ |
407 | 0x1b21, /* 3.6864 Mhz */ |
408 | 0x0c80, /* 4 Mhz */ |
409 | 0x98ee, /* 4.906 Mhz */ |
410 | 0xd5b4, /* 4.9152 Mhz */ |
411 | 0x0a00, /* 5 Mhz */ |
412 | 0x4e27, /* 5.12 Mhz */ |
413 | 0x1902, /* 6 Mhz */ |
414 | 0xec1c, /* 6.144 Mhz */ |
415 | 0x1b23, /* 7.3728 Mhz */ |
416 | 0x0640, /* 8 Mhz */ |
417 | 0xb11c /* 8.192 Mhz */ |
418 | }; |
419 | |
420 | #define DID0_VER_MASK 0x70000000 |
421 | #define DID0_VER_0 0x00000000 |
422 | #define DID0_VER_1 0x10000000 |
423 | |
424 | #define DID0_CLASS_MASK 0x00FF0000 |
425 | #define DID0_CLASS_SANDSTORM 0x00000000 |
426 | #define DID0_CLASS_FURY 0x00010000 |
427 | |
428 | static int ssys_board_class(const ssys_state *s) |
429 | { |
430 | uint32_t did0 = s->board->did0; |
431 | switch (did0 & DID0_VER_MASK) { |
432 | case DID0_VER_0: |
433 | return DID0_CLASS_SANDSTORM; |
434 | case DID0_VER_1: |
435 | switch (did0 & DID0_CLASS_MASK) { |
436 | case DID0_CLASS_SANDSTORM: |
437 | case DID0_CLASS_FURY: |
438 | return did0 & DID0_CLASS_MASK; |
439 | } |
440 | /* for unknown classes, fall through */ |
441 | default: |
442 | /* This can only happen if the hardwired constant did0 value |
443 | * in this board's stellaris_board_info struct is wrong. |
444 | */ |
445 | g_assert_not_reached(); |
446 | } |
447 | } |
448 | |
449 | static uint64_t ssys_read(void *opaque, hwaddr offset, |
450 | unsigned size) |
451 | { |
452 | ssys_state *s = (ssys_state *)opaque; |
453 | |
454 | switch (offset) { |
455 | case 0x000: /* DID0 */ |
456 | return s->board->did0; |
457 | case 0x004: /* DID1 */ |
458 | return s->board->did1; |
459 | case 0x008: /* DC0 */ |
460 | return s->board->dc0; |
461 | case 0x010: /* DC1 */ |
462 | return s->board->dc1; |
463 | case 0x014: /* DC2 */ |
464 | return s->board->dc2; |
465 | case 0x018: /* DC3 */ |
466 | return s->board->dc3; |
467 | case 0x01c: /* DC4 */ |
468 | return s->board->dc4; |
469 | case 0x030: /* PBORCTL */ |
470 | return s->pborctl; |
471 | case 0x034: /* LDOPCTL */ |
472 | return s->ldopctl; |
473 | case 0x040: /* SRCR0 */ |
474 | return 0; |
475 | case 0x044: /* SRCR1 */ |
476 | return 0; |
477 | case 0x048: /* SRCR2 */ |
478 | return 0; |
479 | case 0x050: /* RIS */ |
480 | return s->int_status; |
481 | case 0x054: /* IMC */ |
482 | return s->int_mask; |
483 | case 0x058: /* MISC */ |
484 | return s->int_status & s->int_mask; |
485 | case 0x05c: /* RESC */ |
486 | return s->resc; |
487 | case 0x060: /* RCC */ |
488 | return s->rcc; |
489 | case 0x064: /* PLLCFG */ |
490 | { |
491 | int xtal; |
492 | xtal = (s->rcc >> 6) & 0xf; |
493 | switch (ssys_board_class(s)) { |
494 | case DID0_CLASS_FURY: |
495 | return pllcfg_fury[xtal]; |
496 | case DID0_CLASS_SANDSTORM: |
497 | return pllcfg_sandstorm[xtal]; |
498 | default: |
499 | g_assert_not_reached(); |
500 | } |
501 | } |
502 | case 0x070: /* RCC2 */ |
503 | return s->rcc2; |
504 | case 0x100: /* RCGC0 */ |
505 | return s->rcgc[0]; |
506 | case 0x104: /* RCGC1 */ |
507 | return s->rcgc[1]; |
508 | case 0x108: /* RCGC2 */ |
509 | return s->rcgc[2]; |
510 | case 0x110: /* SCGC0 */ |
511 | return s->scgc[0]; |
512 | case 0x114: /* SCGC1 */ |
513 | return s->scgc[1]; |
514 | case 0x118: /* SCGC2 */ |
515 | return s->scgc[2]; |
516 | case 0x120: /* DCGC0 */ |
517 | return s->dcgc[0]; |
518 | case 0x124: /* DCGC1 */ |
519 | return s->dcgc[1]; |
520 | case 0x128: /* DCGC2 */ |
521 | return s->dcgc[2]; |
522 | case 0x150: /* CLKVCLR */ |
523 | return s->clkvclr; |
524 | case 0x160: /* LDOARST */ |
525 | return s->ldoarst; |
526 | case 0x1e0: /* USER0 */ |
527 | return s->user0; |
528 | case 0x1e4: /* USER1 */ |
529 | return s->user1; |
530 | default: |
531 | qemu_log_mask(LOG_GUEST_ERROR, |
532 | "SSYS: read at bad offset 0x%x\n" , (int)offset); |
533 | return 0; |
534 | } |
535 | } |
536 | |
537 | static bool ssys_use_rcc2(ssys_state *s) |
538 | { |
539 | return (s->rcc2 >> 31) & 0x1; |
540 | } |
541 | |
542 | /* |
543 | * Caculate the sys. clock period in ms. |
544 | */ |
545 | static void ssys_calculate_system_clock(ssys_state *s) |
546 | { |
547 | if (ssys_use_rcc2(s)) { |
548 | system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); |
549 | } else { |
550 | system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); |
551 | } |
552 | } |
553 | |
554 | static void ssys_write(void *opaque, hwaddr offset, |
555 | uint64_t value, unsigned size) |
556 | { |
557 | ssys_state *s = (ssys_state *)opaque; |
558 | |
559 | switch (offset) { |
560 | case 0x030: /* PBORCTL */ |
561 | s->pborctl = value & 0xffff; |
562 | break; |
563 | case 0x034: /* LDOPCTL */ |
564 | s->ldopctl = value & 0x1f; |
565 | break; |
566 | case 0x040: /* SRCR0 */ |
567 | case 0x044: /* SRCR1 */ |
568 | case 0x048: /* SRCR2 */ |
569 | qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n" ); |
570 | break; |
571 | case 0x054: /* IMC */ |
572 | s->int_mask = value & 0x7f; |
573 | break; |
574 | case 0x058: /* MISC */ |
575 | s->int_status &= ~value; |
576 | break; |
577 | case 0x05c: /* RESC */ |
578 | s->resc = value & 0x3f; |
579 | break; |
580 | case 0x060: /* RCC */ |
581 | if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
582 | /* PLL enable. */ |
583 | s->int_status |= (1 << 6); |
584 | } |
585 | s->rcc = value; |
586 | ssys_calculate_system_clock(s); |
587 | break; |
588 | case 0x070: /* RCC2 */ |
589 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { |
590 | break; |
591 | } |
592 | |
593 | if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
594 | /* PLL enable. */ |
595 | s->int_status |= (1 << 6); |
596 | } |
597 | s->rcc2 = value; |
598 | ssys_calculate_system_clock(s); |
599 | break; |
600 | case 0x100: /* RCGC0 */ |
601 | s->rcgc[0] = value; |
602 | break; |
603 | case 0x104: /* RCGC1 */ |
604 | s->rcgc[1] = value; |
605 | break; |
606 | case 0x108: /* RCGC2 */ |
607 | s->rcgc[2] = value; |
608 | break; |
609 | case 0x110: /* SCGC0 */ |
610 | s->scgc[0] = value; |
611 | break; |
612 | case 0x114: /* SCGC1 */ |
613 | s->scgc[1] = value; |
614 | break; |
615 | case 0x118: /* SCGC2 */ |
616 | s->scgc[2] = value; |
617 | break; |
618 | case 0x120: /* DCGC0 */ |
619 | s->dcgc[0] = value; |
620 | break; |
621 | case 0x124: /* DCGC1 */ |
622 | s->dcgc[1] = value; |
623 | break; |
624 | case 0x128: /* DCGC2 */ |
625 | s->dcgc[2] = value; |
626 | break; |
627 | case 0x150: /* CLKVCLR */ |
628 | s->clkvclr = value; |
629 | break; |
630 | case 0x160: /* LDOARST */ |
631 | s->ldoarst = value; |
632 | break; |
633 | default: |
634 | qemu_log_mask(LOG_GUEST_ERROR, |
635 | "SSYS: write at bad offset 0x%x\n" , (int)offset); |
636 | } |
637 | ssys_update(s); |
638 | } |
639 | |
640 | static const MemoryRegionOps ssys_ops = { |
641 | .read = ssys_read, |
642 | .write = ssys_write, |
643 | .endianness = DEVICE_NATIVE_ENDIAN, |
644 | }; |
645 | |
646 | static void ssys_reset(void *opaque) |
647 | { |
648 | ssys_state *s = (ssys_state *)opaque; |
649 | |
650 | s->pborctl = 0x7ffd; |
651 | s->rcc = 0x078e3ac0; |
652 | |
653 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { |
654 | s->rcc2 = 0; |
655 | } else { |
656 | s->rcc2 = 0x07802810; |
657 | } |
658 | s->rcgc[0] = 1; |
659 | s->scgc[0] = 1; |
660 | s->dcgc[0] = 1; |
661 | ssys_calculate_system_clock(s); |
662 | } |
663 | |
664 | static int stellaris_sys_post_load(void *opaque, int version_id) |
665 | { |
666 | ssys_state *s = opaque; |
667 | |
668 | ssys_calculate_system_clock(s); |
669 | |
670 | return 0; |
671 | } |
672 | |
673 | static const VMStateDescription vmstate_stellaris_sys = { |
674 | .name = "stellaris_sys" , |
675 | .version_id = 2, |
676 | .minimum_version_id = 1, |
677 | .post_load = stellaris_sys_post_load, |
678 | .fields = (VMStateField[]) { |
679 | VMSTATE_UINT32(pborctl, ssys_state), |
680 | VMSTATE_UINT32(ldopctl, ssys_state), |
681 | VMSTATE_UINT32(int_mask, ssys_state), |
682 | VMSTATE_UINT32(int_status, ssys_state), |
683 | VMSTATE_UINT32(resc, ssys_state), |
684 | VMSTATE_UINT32(rcc, ssys_state), |
685 | VMSTATE_UINT32_V(rcc2, ssys_state, 2), |
686 | VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), |
687 | VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), |
688 | VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), |
689 | VMSTATE_UINT32(clkvclr, ssys_state), |
690 | VMSTATE_UINT32(ldoarst, ssys_state), |
691 | VMSTATE_END_OF_LIST() |
692 | } |
693 | }; |
694 | |
695 | static int stellaris_sys_init(uint32_t base, qemu_irq irq, |
696 | stellaris_board_info * board, |
697 | uint8_t *macaddr) |
698 | { |
699 | ssys_state *s; |
700 | |
701 | s = g_new0(ssys_state, 1); |
702 | s->irq = irq; |
703 | s->board = board; |
704 | /* Most devices come preprogrammed with a MAC address in the user data. */ |
705 | s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); |
706 | s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); |
707 | |
708 | memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys" , 0x00001000); |
709 | memory_region_add_subregion(get_system_memory(), base, &s->iomem); |
710 | ssys_reset(s); |
711 | vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); |
712 | return 0; |
713 | } |
714 | |
715 | |
716 | /* I2C controller. */ |
717 | |
718 | #define TYPE_STELLARIS_I2C "stellaris-i2c" |
719 | #define STELLARIS_I2C(obj) \ |
720 | OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) |
721 | |
722 | typedef struct { |
723 | SysBusDevice parent_obj; |
724 | |
725 | I2CBus *bus; |
726 | qemu_irq irq; |
727 | MemoryRegion iomem; |
728 | uint32_t msa; |
729 | uint32_t mcs; |
730 | uint32_t mdr; |
731 | uint32_t mtpr; |
732 | uint32_t mimr; |
733 | uint32_t mris; |
734 | uint32_t mcr; |
735 | } stellaris_i2c_state; |
736 | |
737 | #define STELLARIS_I2C_MCS_BUSY 0x01 |
738 | #define STELLARIS_I2C_MCS_ERROR 0x02 |
739 | #define STELLARIS_I2C_MCS_ADRACK 0x04 |
740 | #define STELLARIS_I2C_MCS_DATACK 0x08 |
741 | #define STELLARIS_I2C_MCS_ARBLST 0x10 |
742 | #define STELLARIS_I2C_MCS_IDLE 0x20 |
743 | #define STELLARIS_I2C_MCS_BUSBSY 0x40 |
744 | |
745 | static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, |
746 | unsigned size) |
747 | { |
748 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
749 | |
750 | switch (offset) { |
751 | case 0x00: /* MSA */ |
752 | return s->msa; |
753 | case 0x04: /* MCS */ |
754 | /* We don't emulate timing, so the controller is never busy. */ |
755 | return s->mcs | STELLARIS_I2C_MCS_IDLE; |
756 | case 0x08: /* MDR */ |
757 | return s->mdr; |
758 | case 0x0c: /* MTPR */ |
759 | return s->mtpr; |
760 | case 0x10: /* MIMR */ |
761 | return s->mimr; |
762 | case 0x14: /* MRIS */ |
763 | return s->mris; |
764 | case 0x18: /* MMIS */ |
765 | return s->mris & s->mimr; |
766 | case 0x20: /* MCR */ |
767 | return s->mcr; |
768 | default: |
769 | qemu_log_mask(LOG_GUEST_ERROR, |
770 | "stellaris_i2c: read at bad offset 0x%x\n" , (int)offset); |
771 | return 0; |
772 | } |
773 | } |
774 | |
775 | static void stellaris_i2c_update(stellaris_i2c_state *s) |
776 | { |
777 | int level; |
778 | |
779 | level = (s->mris & s->mimr) != 0; |
780 | qemu_set_irq(s->irq, level); |
781 | } |
782 | |
783 | static void stellaris_i2c_write(void *opaque, hwaddr offset, |
784 | uint64_t value, unsigned size) |
785 | { |
786 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
787 | |
788 | switch (offset) { |
789 | case 0x00: /* MSA */ |
790 | s->msa = value & 0xff; |
791 | break; |
792 | case 0x04: /* MCS */ |
793 | if ((s->mcr & 0x10) == 0) { |
794 | /* Disabled. Do nothing. */ |
795 | break; |
796 | } |
797 | /* Grab the bus if this is starting a transfer. */ |
798 | if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
799 | if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { |
800 | s->mcs |= STELLARIS_I2C_MCS_ARBLST; |
801 | } else { |
802 | s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; |
803 | s->mcs |= STELLARIS_I2C_MCS_BUSBSY; |
804 | } |
805 | } |
806 | /* If we don't have the bus then indicate an error. */ |
807 | if (!i2c_bus_busy(s->bus) |
808 | || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
809 | s->mcs |= STELLARIS_I2C_MCS_ERROR; |
810 | break; |
811 | } |
812 | s->mcs &= ~STELLARIS_I2C_MCS_ERROR; |
813 | if (value & 1) { |
814 | /* Transfer a byte. */ |
815 | /* TODO: Handle errors. */ |
816 | if (s->msa & 1) { |
817 | /* Recv */ |
818 | s->mdr = i2c_recv(s->bus); |
819 | } else { |
820 | /* Send */ |
821 | i2c_send(s->bus, s->mdr); |
822 | } |
823 | /* Raise an interrupt. */ |
824 | s->mris |= 1; |
825 | } |
826 | if (value & 4) { |
827 | /* Finish transfer. */ |
828 | i2c_end_transfer(s->bus); |
829 | s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; |
830 | } |
831 | break; |
832 | case 0x08: /* MDR */ |
833 | s->mdr = value & 0xff; |
834 | break; |
835 | case 0x0c: /* MTPR */ |
836 | s->mtpr = value & 0xff; |
837 | break; |
838 | case 0x10: /* MIMR */ |
839 | s->mimr = 1; |
840 | break; |
841 | case 0x1c: /* MICR */ |
842 | s->mris &= ~value; |
843 | break; |
844 | case 0x20: /* MCR */ |
845 | if (value & 1) { |
846 | qemu_log_mask(LOG_UNIMP, |
847 | "stellaris_i2c: Loopback not implemented\n" ); |
848 | } |
849 | if (value & 0x20) { |
850 | qemu_log_mask(LOG_UNIMP, |
851 | "stellaris_i2c: Slave mode not implemented\n" ); |
852 | } |
853 | s->mcr = value & 0x31; |
854 | break; |
855 | default: |
856 | qemu_log_mask(LOG_GUEST_ERROR, |
857 | "stellaris_i2c: write at bad offset 0x%x\n" , (int)offset); |
858 | } |
859 | stellaris_i2c_update(s); |
860 | } |
861 | |
862 | static void stellaris_i2c_reset(stellaris_i2c_state *s) |
863 | { |
864 | if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) |
865 | i2c_end_transfer(s->bus); |
866 | |
867 | s->msa = 0; |
868 | s->mcs = 0; |
869 | s->mdr = 0; |
870 | s->mtpr = 1; |
871 | s->mimr = 0; |
872 | s->mris = 0; |
873 | s->mcr = 0; |
874 | stellaris_i2c_update(s); |
875 | } |
876 | |
877 | static const MemoryRegionOps stellaris_i2c_ops = { |
878 | .read = stellaris_i2c_read, |
879 | .write = stellaris_i2c_write, |
880 | .endianness = DEVICE_NATIVE_ENDIAN, |
881 | }; |
882 | |
883 | static const VMStateDescription vmstate_stellaris_i2c = { |
884 | .name = "stellaris_i2c" , |
885 | .version_id = 1, |
886 | .minimum_version_id = 1, |
887 | .fields = (VMStateField[]) { |
888 | VMSTATE_UINT32(msa, stellaris_i2c_state), |
889 | VMSTATE_UINT32(mcs, stellaris_i2c_state), |
890 | VMSTATE_UINT32(mdr, stellaris_i2c_state), |
891 | VMSTATE_UINT32(mtpr, stellaris_i2c_state), |
892 | VMSTATE_UINT32(mimr, stellaris_i2c_state), |
893 | VMSTATE_UINT32(mris, stellaris_i2c_state), |
894 | VMSTATE_UINT32(mcr, stellaris_i2c_state), |
895 | VMSTATE_END_OF_LIST() |
896 | } |
897 | }; |
898 | |
899 | static void stellaris_i2c_init(Object *obj) |
900 | { |
901 | DeviceState *dev = DEVICE(obj); |
902 | stellaris_i2c_state *s = STELLARIS_I2C(obj); |
903 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
904 | I2CBus *bus; |
905 | |
906 | sysbus_init_irq(sbd, &s->irq); |
907 | bus = i2c_init_bus(dev, "i2c" ); |
908 | s->bus = bus; |
909 | |
910 | memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, |
911 | "i2c" , 0x1000); |
912 | sysbus_init_mmio(sbd, &s->iomem); |
913 | /* ??? For now we only implement the master interface. */ |
914 | stellaris_i2c_reset(s); |
915 | } |
916 | |
917 | /* Analogue to Digital Converter. This is only partially implemented, |
918 | enough for applications that use a combined ADC and timer tick. */ |
919 | |
920 | #define STELLARIS_ADC_EM_CONTROLLER 0 |
921 | #define STELLARIS_ADC_EM_COMP 1 |
922 | #define STELLARIS_ADC_EM_EXTERNAL 4 |
923 | #define STELLARIS_ADC_EM_TIMER 5 |
924 | #define STELLARIS_ADC_EM_PWM0 6 |
925 | #define STELLARIS_ADC_EM_PWM1 7 |
926 | #define STELLARIS_ADC_EM_PWM2 8 |
927 | |
928 | #define STELLARIS_ADC_FIFO_EMPTY 0x0100 |
929 | #define STELLARIS_ADC_FIFO_FULL 0x1000 |
930 | |
931 | #define TYPE_STELLARIS_ADC "stellaris-adc" |
932 | #define STELLARIS_ADC(obj) \ |
933 | OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) |
934 | |
935 | typedef struct StellarisADCState { |
936 | SysBusDevice parent_obj; |
937 | |
938 | MemoryRegion iomem; |
939 | uint32_t actss; |
940 | uint32_t ris; |
941 | uint32_t im; |
942 | uint32_t emux; |
943 | uint32_t ostat; |
944 | uint32_t ustat; |
945 | uint32_t sspri; |
946 | uint32_t sac; |
947 | struct { |
948 | uint32_t state; |
949 | uint32_t data[16]; |
950 | } fifo[4]; |
951 | uint32_t ssmux[4]; |
952 | uint32_t ssctl[4]; |
953 | uint32_t noise; |
954 | qemu_irq irq[4]; |
955 | } stellaris_adc_state; |
956 | |
957 | static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) |
958 | { |
959 | int tail; |
960 | |
961 | tail = s->fifo[n].state & 0xf; |
962 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { |
963 | s->ustat |= 1 << n; |
964 | } else { |
965 | s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); |
966 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; |
967 | if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) |
968 | s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; |
969 | } |
970 | return s->fifo[n].data[tail]; |
971 | } |
972 | |
973 | static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, |
974 | uint32_t value) |
975 | { |
976 | int head; |
977 | |
978 | /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry |
979 | FIFO fir each sequencer. */ |
980 | head = (s->fifo[n].state >> 4) & 0xf; |
981 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { |
982 | s->ostat |= 1 << n; |
983 | return; |
984 | } |
985 | s->fifo[n].data[head] = value; |
986 | head = (head + 1) & 0xf; |
987 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; |
988 | s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); |
989 | if ((s->fifo[n].state & 0xf) == head) |
990 | s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; |
991 | } |
992 | |
993 | static void stellaris_adc_update(stellaris_adc_state *s) |
994 | { |
995 | int level; |
996 | int n; |
997 | |
998 | for (n = 0; n < 4; n++) { |
999 | level = (s->ris & s->im & (1 << n)) != 0; |
1000 | qemu_set_irq(s->irq[n], level); |
1001 | } |
1002 | } |
1003 | |
1004 | static void stellaris_adc_trigger(void *opaque, int irq, int level) |
1005 | { |
1006 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
1007 | int n; |
1008 | |
1009 | for (n = 0; n < 4; n++) { |
1010 | if ((s->actss & (1 << n)) == 0) { |
1011 | continue; |
1012 | } |
1013 | |
1014 | if (((s->emux >> (n * 4)) & 0xff) != 5) { |
1015 | continue; |
1016 | } |
1017 | |
1018 | /* Some applications use the ADC as a random number source, so introduce |
1019 | some variation into the signal. */ |
1020 | s->noise = s->noise * 314159 + 1; |
1021 | /* ??? actual inputs not implemented. Return an arbitrary value. */ |
1022 | stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); |
1023 | s->ris |= (1 << n); |
1024 | stellaris_adc_update(s); |
1025 | } |
1026 | } |
1027 | |
1028 | static void stellaris_adc_reset(stellaris_adc_state *s) |
1029 | { |
1030 | int n; |
1031 | |
1032 | for (n = 0; n < 4; n++) { |
1033 | s->ssmux[n] = 0; |
1034 | s->ssctl[n] = 0; |
1035 | s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; |
1036 | } |
1037 | } |
1038 | |
1039 | static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, |
1040 | unsigned size) |
1041 | { |
1042 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
1043 | |
1044 | /* TODO: Implement this. */ |
1045 | if (offset >= 0x40 && offset < 0xc0) { |
1046 | int n; |
1047 | n = (offset - 0x40) >> 5; |
1048 | switch (offset & 0x1f) { |
1049 | case 0x00: /* SSMUX */ |
1050 | return s->ssmux[n]; |
1051 | case 0x04: /* SSCTL */ |
1052 | return s->ssctl[n]; |
1053 | case 0x08: /* SSFIFO */ |
1054 | return stellaris_adc_fifo_read(s, n); |
1055 | case 0x0c: /* SSFSTAT */ |
1056 | return s->fifo[n].state; |
1057 | default: |
1058 | break; |
1059 | } |
1060 | } |
1061 | switch (offset) { |
1062 | case 0x00: /* ACTSS */ |
1063 | return s->actss; |
1064 | case 0x04: /* RIS */ |
1065 | return s->ris; |
1066 | case 0x08: /* IM */ |
1067 | return s->im; |
1068 | case 0x0c: /* ISC */ |
1069 | return s->ris & s->im; |
1070 | case 0x10: /* OSTAT */ |
1071 | return s->ostat; |
1072 | case 0x14: /* EMUX */ |
1073 | return s->emux; |
1074 | case 0x18: /* USTAT */ |
1075 | return s->ustat; |
1076 | case 0x20: /* SSPRI */ |
1077 | return s->sspri; |
1078 | case 0x30: /* SAC */ |
1079 | return s->sac; |
1080 | default: |
1081 | qemu_log_mask(LOG_GUEST_ERROR, |
1082 | "stellaris_adc: read at bad offset 0x%x\n" , (int)offset); |
1083 | return 0; |
1084 | } |
1085 | } |
1086 | |
1087 | static void stellaris_adc_write(void *opaque, hwaddr offset, |
1088 | uint64_t value, unsigned size) |
1089 | { |
1090 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
1091 | |
1092 | /* TODO: Implement this. */ |
1093 | if (offset >= 0x40 && offset < 0xc0) { |
1094 | int n; |
1095 | n = (offset - 0x40) >> 5; |
1096 | switch (offset & 0x1f) { |
1097 | case 0x00: /* SSMUX */ |
1098 | s->ssmux[n] = value & 0x33333333; |
1099 | return; |
1100 | case 0x04: /* SSCTL */ |
1101 | if (value != 6) { |
1102 | qemu_log_mask(LOG_UNIMP, |
1103 | "ADC: Unimplemented sequence %" PRIx64 "\n" , |
1104 | value); |
1105 | } |
1106 | s->ssctl[n] = value; |
1107 | return; |
1108 | default: |
1109 | break; |
1110 | } |
1111 | } |
1112 | switch (offset) { |
1113 | case 0x00: /* ACTSS */ |
1114 | s->actss = value & 0xf; |
1115 | break; |
1116 | case 0x08: /* IM */ |
1117 | s->im = value; |
1118 | break; |
1119 | case 0x0c: /* ISC */ |
1120 | s->ris &= ~value; |
1121 | break; |
1122 | case 0x10: /* OSTAT */ |
1123 | s->ostat &= ~value; |
1124 | break; |
1125 | case 0x14: /* EMUX */ |
1126 | s->emux = value; |
1127 | break; |
1128 | case 0x18: /* USTAT */ |
1129 | s->ustat &= ~value; |
1130 | break; |
1131 | case 0x20: /* SSPRI */ |
1132 | s->sspri = value; |
1133 | break; |
1134 | case 0x28: /* PSSI */ |
1135 | qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n" ); |
1136 | break; |
1137 | case 0x30: /* SAC */ |
1138 | s->sac = value; |
1139 | break; |
1140 | default: |
1141 | qemu_log_mask(LOG_GUEST_ERROR, |
1142 | "stellaris_adc: write at bad offset 0x%x\n" , (int)offset); |
1143 | } |
1144 | stellaris_adc_update(s); |
1145 | } |
1146 | |
1147 | static const MemoryRegionOps stellaris_adc_ops = { |
1148 | .read = stellaris_adc_read, |
1149 | .write = stellaris_adc_write, |
1150 | .endianness = DEVICE_NATIVE_ENDIAN, |
1151 | }; |
1152 | |
1153 | static const VMStateDescription vmstate_stellaris_adc = { |
1154 | .name = "stellaris_adc" , |
1155 | .version_id = 1, |
1156 | .minimum_version_id = 1, |
1157 | .fields = (VMStateField[]) { |
1158 | VMSTATE_UINT32(actss, stellaris_adc_state), |
1159 | VMSTATE_UINT32(ris, stellaris_adc_state), |
1160 | VMSTATE_UINT32(im, stellaris_adc_state), |
1161 | VMSTATE_UINT32(emux, stellaris_adc_state), |
1162 | VMSTATE_UINT32(ostat, stellaris_adc_state), |
1163 | VMSTATE_UINT32(ustat, stellaris_adc_state), |
1164 | VMSTATE_UINT32(sspri, stellaris_adc_state), |
1165 | VMSTATE_UINT32(sac, stellaris_adc_state), |
1166 | VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), |
1167 | VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), |
1168 | VMSTATE_UINT32(ssmux[0], stellaris_adc_state), |
1169 | VMSTATE_UINT32(ssctl[0], stellaris_adc_state), |
1170 | VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), |
1171 | VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), |
1172 | VMSTATE_UINT32(ssmux[1], stellaris_adc_state), |
1173 | VMSTATE_UINT32(ssctl[1], stellaris_adc_state), |
1174 | VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), |
1175 | VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), |
1176 | VMSTATE_UINT32(ssmux[2], stellaris_adc_state), |
1177 | VMSTATE_UINT32(ssctl[2], stellaris_adc_state), |
1178 | VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), |
1179 | VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), |
1180 | VMSTATE_UINT32(ssmux[3], stellaris_adc_state), |
1181 | VMSTATE_UINT32(ssctl[3], stellaris_adc_state), |
1182 | VMSTATE_UINT32(noise, stellaris_adc_state), |
1183 | VMSTATE_END_OF_LIST() |
1184 | } |
1185 | }; |
1186 | |
1187 | static void stellaris_adc_init(Object *obj) |
1188 | { |
1189 | DeviceState *dev = DEVICE(obj); |
1190 | stellaris_adc_state *s = STELLARIS_ADC(obj); |
1191 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
1192 | int n; |
1193 | |
1194 | for (n = 0; n < 4; n++) { |
1195 | sysbus_init_irq(sbd, &s->irq[n]); |
1196 | } |
1197 | |
1198 | memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, |
1199 | "adc" , 0x1000); |
1200 | sysbus_init_mmio(sbd, &s->iomem); |
1201 | stellaris_adc_reset(s); |
1202 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); |
1203 | } |
1204 | |
1205 | static |
1206 | void do_sys_reset(void *opaque, int n, int level) |
1207 | { |
1208 | if (level) { |
1209 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
1210 | } |
1211 | } |
1212 | |
1213 | /* Board init. */ |
1214 | static stellaris_board_info stellaris_boards[] = { |
1215 | { "LM3S811EVB" , |
1216 | 0, |
1217 | 0x0032000e, |
1218 | 0x001f001f, /* dc0 */ |
1219 | 0x001132bf, |
1220 | 0x01071013, |
1221 | 0x3f0f01ff, |
1222 | 0x0000001f, |
1223 | BP_OLED_I2C |
1224 | }, |
1225 | { "LM3S6965EVB" , |
1226 | 0x10010002, |
1227 | 0x1073402e, |
1228 | 0x00ff007f, /* dc0 */ |
1229 | 0x001133ff, |
1230 | 0x030f5317, |
1231 | 0x0f0f87ff, |
1232 | 0x5000007f, |
1233 | BP_OLED_SSI | BP_GAMEPAD |
1234 | } |
1235 | }; |
1236 | |
1237 | static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
1238 | { |
1239 | static const int uart_irq[] = {5, 6, 33, 34}; |
1240 | static const int timer_irq[] = {19, 21, 23, 35}; |
1241 | static const uint32_t gpio_addr[7] = |
1242 | { 0x40004000, 0x40005000, 0x40006000, 0x40007000, |
1243 | 0x40024000, 0x40025000, 0x40026000}; |
1244 | static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; |
1245 | |
1246 | /* Memory map of SoC devices, from |
1247 | * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) |
1248 | * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf |
1249 | * |
1250 | * 40000000 wdtimer |
1251 | * 40002000 i2c (unimplemented) |
1252 | * 40004000 GPIO |
1253 | * 40005000 GPIO |
1254 | * 40006000 GPIO |
1255 | * 40007000 GPIO |
1256 | * 40008000 SSI |
1257 | * 4000c000 UART |
1258 | * 4000d000 UART |
1259 | * 4000e000 UART |
1260 | * 40020000 i2c |
1261 | * 40021000 i2c (unimplemented) |
1262 | * 40024000 GPIO |
1263 | * 40025000 GPIO |
1264 | * 40026000 GPIO |
1265 | * 40028000 PWM (unimplemented) |
1266 | * 4002c000 QEI (unimplemented) |
1267 | * 4002d000 QEI (unimplemented) |
1268 | * 40030000 gptimer |
1269 | * 40031000 gptimer |
1270 | * 40032000 gptimer |
1271 | * 40033000 gptimer |
1272 | * 40038000 ADC |
1273 | * 4003c000 analogue comparator (unimplemented) |
1274 | * 40048000 ethernet |
1275 | * 400fc000 hibernation module (unimplemented) |
1276 | * 400fd000 flash memory control (unimplemented) |
1277 | * 400fe000 system control |
1278 | */ |
1279 | |
1280 | DeviceState *gpio_dev[7], *nvic; |
1281 | qemu_irq gpio_in[7][8]; |
1282 | qemu_irq gpio_out[7][8]; |
1283 | qemu_irq adc; |
1284 | int sram_size; |
1285 | int flash_size; |
1286 | I2CBus *i2c; |
1287 | DeviceState *dev; |
1288 | int i; |
1289 | int j; |
1290 | |
1291 | MemoryRegion *sram = g_new(MemoryRegion, 1); |
1292 | MemoryRegion *flash = g_new(MemoryRegion, 1); |
1293 | MemoryRegion *system_memory = get_system_memory(); |
1294 | |
1295 | flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; |
1296 | sram_size = ((board->dc0 >> 18) + 1) * 1024; |
1297 | |
1298 | /* Flash programming is done via the SCU, so pretend it is ROM. */ |
1299 | memory_region_init_ram(flash, NULL, "stellaris.flash" , flash_size, |
1300 | &error_fatal); |
1301 | memory_region_set_readonly(flash, true); |
1302 | memory_region_add_subregion(system_memory, 0, flash); |
1303 | |
1304 | memory_region_init_ram(sram, NULL, "stellaris.sram" , sram_size, |
1305 | &error_fatal); |
1306 | memory_region_add_subregion(system_memory, 0x20000000, sram); |
1307 | |
1308 | nvic = qdev_create(NULL, TYPE_ARMV7M); |
1309 | qdev_prop_set_uint32(nvic, "num-irq" , NUM_IRQ_LINES); |
1310 | qdev_prop_set_string(nvic, "cpu-type" , ms->cpu_type); |
1311 | qdev_prop_set_bit(nvic, "enable-bitband" , true); |
1312 | object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), |
1313 | "memory" , &error_abort); |
1314 | /* This will exit with an error if the user passed us a bad cpu_type */ |
1315 | qdev_init_nofail(nvic); |
1316 | |
1317 | qdev_connect_gpio_out_named(nvic, "SYSRESETREQ" , 0, |
1318 | qemu_allocate_irq(&do_sys_reset, NULL, 0)); |
1319 | |
1320 | if (board->dc1 & (1 << 16)) { |
1321 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, |
1322 | qdev_get_gpio_in(nvic, 14), |
1323 | qdev_get_gpio_in(nvic, 15), |
1324 | qdev_get_gpio_in(nvic, 16), |
1325 | qdev_get_gpio_in(nvic, 17), |
1326 | NULL); |
1327 | adc = qdev_get_gpio_in(dev, 0); |
1328 | } else { |
1329 | adc = NULL; |
1330 | } |
1331 | for (i = 0; i < 4; i++) { |
1332 | if (board->dc2 & (0x10000 << i)) { |
1333 | dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, |
1334 | 0x40030000 + i * 0x1000, |
1335 | qdev_get_gpio_in(nvic, timer_irq[i])); |
1336 | /* TODO: This is incorrect, but we get away with it because |
1337 | the ADC output is only ever pulsed. */ |
1338 | qdev_connect_gpio_out(dev, 0, adc); |
1339 | } |
1340 | } |
1341 | |
1342 | stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), |
1343 | board, nd_table[0].macaddr.a); |
1344 | |
1345 | |
1346 | if (board->dc1 & (1 << 3)) { /* watchdog present */ |
1347 | dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); |
1348 | |
1349 | /* system_clock_scale is valid now */ |
1350 | uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; |
1351 | qdev_prop_set_uint32(dev, "wdogclk-frq" , mainclk); |
1352 | |
1353 | qdev_init_nofail(dev); |
1354 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), |
1355 | 0, |
1356 | 0x40000000u); |
1357 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), |
1358 | 0, |
1359 | qdev_get_gpio_in(nvic, 18)); |
1360 | } |
1361 | |
1362 | |
1363 | for (i = 0; i < 7; i++) { |
1364 | if (board->dc4 & (1 << i)) { |
1365 | gpio_dev[i] = sysbus_create_simple("pl061_luminary" , gpio_addr[i], |
1366 | qdev_get_gpio_in(nvic, |
1367 | gpio_irq[i])); |
1368 | for (j = 0; j < 8; j++) { |
1369 | gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); |
1370 | gpio_out[i][j] = NULL; |
1371 | } |
1372 | } |
1373 | } |
1374 | |
1375 | if (board->dc2 & (1 << 12)) { |
1376 | dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, |
1377 | qdev_get_gpio_in(nvic, 8)); |
1378 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c" ); |
1379 | if (board->peripherals & BP_OLED_I2C) { |
1380 | i2c_create_slave(i2c, "ssd0303" , 0x3d); |
1381 | } |
1382 | } |
1383 | |
1384 | for (i = 0; i < 4; i++) { |
1385 | if (board->dc2 & (1 << i)) { |
1386 | pl011_luminary_create(0x4000c000 + i * 0x1000, |
1387 | qdev_get_gpio_in(nvic, uart_irq[i]), |
1388 | serial_hd(i)); |
1389 | } |
1390 | } |
1391 | if (board->dc2 & (1 << 4)) { |
1392 | dev = sysbus_create_simple("pl022" , 0x40008000, |
1393 | qdev_get_gpio_in(nvic, 7)); |
1394 | if (board->peripherals & BP_OLED_SSI) { |
1395 | void *bus; |
1396 | DeviceState *sddev; |
1397 | DeviceState *ssddev; |
1398 | |
1399 | /* Some boards have both an OLED controller and SD card connected to |
1400 | * the same SSI port, with the SD card chip select connected to a |
1401 | * GPIO pin. Technically the OLED chip select is connected to the |
1402 | * SSI Fss pin. We do not bother emulating that as both devices |
1403 | * should never be selected simultaneously, and our OLED controller |
1404 | * ignores stray 0xff commands that occur when deselecting the SD |
1405 | * card. |
1406 | */ |
1407 | bus = qdev_get_child_bus(dev, "ssi" ); |
1408 | |
1409 | sddev = ssi_create_slave(bus, "ssi-sd" ); |
1410 | ssddev = ssi_create_slave(bus, "ssd0323" ); |
1411 | gpio_out[GPIO_D][0] = qemu_irq_split( |
1412 | qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), |
1413 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); |
1414 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); |
1415 | |
1416 | /* Make sure the select pin is high. */ |
1417 | qemu_irq_raise(gpio_out[GPIO_D][0]); |
1418 | } |
1419 | } |
1420 | if (board->dc4 & (1 << 28)) { |
1421 | DeviceState *enet; |
1422 | |
1423 | qemu_check_nic_model(&nd_table[0], "stellaris" ); |
1424 | |
1425 | enet = qdev_create(NULL, "stellaris_enet" ); |
1426 | qdev_set_nic_properties(enet, &nd_table[0]); |
1427 | qdev_init_nofail(enet); |
1428 | sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); |
1429 | sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); |
1430 | } |
1431 | if (board->peripherals & BP_GAMEPAD) { |
1432 | qemu_irq gpad_irq[5]; |
1433 | static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; |
1434 | |
1435 | gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ |
1436 | gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ |
1437 | gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ |
1438 | gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ |
1439 | gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ |
1440 | |
1441 | stellaris_gamepad_init(5, gpad_irq, gpad_keycode); |
1442 | } |
1443 | for (i = 0; i < 7; i++) { |
1444 | if (board->dc4 & (1 << i)) { |
1445 | for (j = 0; j < 8; j++) { |
1446 | if (gpio_out[i][j]) { |
1447 | qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); |
1448 | } |
1449 | } |
1450 | } |
1451 | } |
1452 | |
1453 | /* Add dummy regions for the devices we don't implement yet, |
1454 | * so guest accesses don't cause unlogged crashes. |
1455 | */ |
1456 | create_unimplemented_device("i2c-0" , 0x40002000, 0x1000); |
1457 | create_unimplemented_device("i2c-2" , 0x40021000, 0x1000); |
1458 | create_unimplemented_device("PWM" , 0x40028000, 0x1000); |
1459 | create_unimplemented_device("QEI-0" , 0x4002c000, 0x1000); |
1460 | create_unimplemented_device("QEI-1" , 0x4002d000, 0x1000); |
1461 | create_unimplemented_device("analogue-comparator" , 0x4003c000, 0x1000); |
1462 | create_unimplemented_device("hibernation" , 0x400fc000, 0x1000); |
1463 | create_unimplemented_device("flash-control" , 0x400fd000, 0x1000); |
1464 | |
1465 | armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); |
1466 | } |
1467 | |
1468 | /* FIXME: Figure out how to generate these from stellaris_boards. */ |
1469 | static void lm3s811evb_init(MachineState *machine) |
1470 | { |
1471 | stellaris_init(machine, &stellaris_boards[0]); |
1472 | } |
1473 | |
1474 | static void lm3s6965evb_init(MachineState *machine) |
1475 | { |
1476 | stellaris_init(machine, &stellaris_boards[1]); |
1477 | } |
1478 | |
1479 | static void lm3s811evb_class_init(ObjectClass *oc, void *data) |
1480 | { |
1481 | MachineClass *mc = MACHINE_CLASS(oc); |
1482 | |
1483 | mc->desc = "Stellaris LM3S811EVB" ; |
1484 | mc->init = lm3s811evb_init; |
1485 | mc->ignore_memory_transaction_failures = true; |
1486 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3" ); |
1487 | } |
1488 | |
1489 | static const TypeInfo lm3s811evb_type = { |
1490 | .name = MACHINE_TYPE_NAME("lm3s811evb" ), |
1491 | .parent = TYPE_MACHINE, |
1492 | .class_init = lm3s811evb_class_init, |
1493 | }; |
1494 | |
1495 | static void lm3s6965evb_class_init(ObjectClass *oc, void *data) |
1496 | { |
1497 | MachineClass *mc = MACHINE_CLASS(oc); |
1498 | |
1499 | mc->desc = "Stellaris LM3S6965EVB" ; |
1500 | mc->init = lm3s6965evb_init; |
1501 | mc->ignore_memory_transaction_failures = true; |
1502 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3" ); |
1503 | } |
1504 | |
1505 | static const TypeInfo lm3s6965evb_type = { |
1506 | .name = MACHINE_TYPE_NAME("lm3s6965evb" ), |
1507 | .parent = TYPE_MACHINE, |
1508 | .class_init = lm3s6965evb_class_init, |
1509 | }; |
1510 | |
1511 | static void stellaris_machine_init(void) |
1512 | { |
1513 | type_register_static(&lm3s811evb_type); |
1514 | type_register_static(&lm3s6965evb_type); |
1515 | } |
1516 | |
1517 | type_init(stellaris_machine_init) |
1518 | |
1519 | static void stellaris_i2c_class_init(ObjectClass *klass, void *data) |
1520 | { |
1521 | DeviceClass *dc = DEVICE_CLASS(klass); |
1522 | |
1523 | dc->vmsd = &vmstate_stellaris_i2c; |
1524 | } |
1525 | |
1526 | static const TypeInfo stellaris_i2c_info = { |
1527 | .name = TYPE_STELLARIS_I2C, |
1528 | .parent = TYPE_SYS_BUS_DEVICE, |
1529 | .instance_size = sizeof(stellaris_i2c_state), |
1530 | .instance_init = stellaris_i2c_init, |
1531 | .class_init = stellaris_i2c_class_init, |
1532 | }; |
1533 | |
1534 | static void stellaris_gptm_class_init(ObjectClass *klass, void *data) |
1535 | { |
1536 | DeviceClass *dc = DEVICE_CLASS(klass); |
1537 | |
1538 | dc->vmsd = &vmstate_stellaris_gptm; |
1539 | } |
1540 | |
1541 | static const TypeInfo stellaris_gptm_info = { |
1542 | .name = TYPE_STELLARIS_GPTM, |
1543 | .parent = TYPE_SYS_BUS_DEVICE, |
1544 | .instance_size = sizeof(gptm_state), |
1545 | .instance_init = stellaris_gptm_init, |
1546 | .class_init = stellaris_gptm_class_init, |
1547 | }; |
1548 | |
1549 | static void stellaris_adc_class_init(ObjectClass *klass, void *data) |
1550 | { |
1551 | DeviceClass *dc = DEVICE_CLASS(klass); |
1552 | |
1553 | dc->vmsd = &vmstate_stellaris_adc; |
1554 | } |
1555 | |
1556 | static const TypeInfo stellaris_adc_info = { |
1557 | .name = TYPE_STELLARIS_ADC, |
1558 | .parent = TYPE_SYS_BUS_DEVICE, |
1559 | .instance_size = sizeof(stellaris_adc_state), |
1560 | .instance_init = stellaris_adc_init, |
1561 | .class_init = stellaris_adc_class_init, |
1562 | }; |
1563 | |
1564 | static void stellaris_register_types(void) |
1565 | { |
1566 | type_register_static(&stellaris_i2c_info); |
1567 | type_register_static(&stellaris_gptm_info); |
1568 | type_register_static(&stellaris_adc_info); |
1569 | } |
1570 | |
1571 | type_init(stellaris_register_types) |
1572 | |