1/*
2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 * Based on pl011.c, copyright terms below:
6 *
7 * Arm PrimeCell PL011 UART
8 *
9 * Copyright (c) 2006 CodeSourcery.
10 * Written by Paul Brook
11 *
12 * This code is licensed under the GPL.
13 *
14 * At present only the core UART functions (data path for tx/rx) are
15 * implemented. The following features/registers are unimplemented:
16 * - Line/modem control
17 * - Scratch register
18 * - Extra control
19 * - Baudrate
20 * - SPI interfaces
21 */
22
23#include "qemu/osdep.h"
24#include "hw/char/bcm2835_aux.h"
25#include "hw/irq.h"
26#include "hw/qdev-properties.h"
27#include "migration/vmstate.h"
28#include "qemu/log.h"
29#include "qemu/module.h"
30
31#define AUX_IRQ 0x0
32#define AUX_ENABLES 0x4
33#define AUX_MU_IO_REG 0x40
34#define AUX_MU_IER_REG 0x44
35#define AUX_MU_IIR_REG 0x48
36#define AUX_MU_LCR_REG 0x4c
37#define AUX_MU_MCR_REG 0x50
38#define AUX_MU_LSR_REG 0x54
39#define AUX_MU_MSR_REG 0x58
40#define AUX_MU_SCRATCH 0x5c
41#define AUX_MU_CNTL_REG 0x60
42#define AUX_MU_STAT_REG 0x64
43#define AUX_MU_BAUD_REG 0x68
44
45/* bits in IER/IIR registers */
46#define RX_INT 0x1
47#define TX_INT 0x2
48
49static void bcm2835_aux_update(BCM2835AuxState *s)
50{
51 /* signal an interrupt if either:
52 * 1. rx interrupt is enabled and we have a non-empty rx fifo, or
53 * 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
54 */
55 s->iir = 0;
56 if ((s->ier & RX_INT) && s->read_count != 0) {
57 s->iir |= RX_INT;
58 }
59 if (s->ier & TX_INT) {
60 s->iir |= TX_INT;
61 }
62 qemu_set_irq(s->irq, s->iir != 0);
63}
64
65static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
66{
67 BCM2835AuxState *s = opaque;
68 uint32_t c, res;
69
70 switch (offset) {
71 case AUX_IRQ:
72 return s->iir != 0;
73
74 case AUX_ENABLES:
75 return 1; /* mini UART permanently enabled */
76
77 case AUX_MU_IO_REG:
78 /* "DLAB bit set means access baudrate register" is NYI */
79 c = s->read_fifo[s->read_pos];
80 if (s->read_count > 0) {
81 s->read_count--;
82 if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
83 s->read_pos = 0;
84 }
85 }
86 qemu_chr_fe_accept_input(&s->chr);
87 bcm2835_aux_update(s);
88 return c;
89
90 case AUX_MU_IER_REG:
91 /* "DLAB bit set means access baudrate register" is NYI */
92 return 0xc0 | s->ier; /* FIFO enables always read 1 */
93
94 case AUX_MU_IIR_REG:
95 res = 0xc0; /* FIFO enables */
96 /* The spec is unclear on what happens when both tx and rx
97 * interrupts are active, besides that this cannot occur. At
98 * present, we choose to prioritise the rx interrupt, since
99 * the tx fifo is always empty. */
100 if (s->read_count != 0) {
101 res |= 0x4;
102 } else {
103 res |= 0x2;
104 }
105 if (s->iir == 0) {
106 res |= 0x1;
107 }
108 return res;
109
110 case AUX_MU_LCR_REG:
111 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
112 return 0;
113
114 case AUX_MU_MCR_REG:
115 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
116 return 0;
117
118 case AUX_MU_LSR_REG:
119 res = 0x60; /* tx idle, empty */
120 if (s->read_count != 0) {
121 res |= 0x1;
122 }
123 return res;
124
125 case AUX_MU_MSR_REG:
126 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
127 return 0;
128
129 case AUX_MU_SCRATCH:
130 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
131 return 0;
132
133 case AUX_MU_CNTL_REG:
134 return 0x3; /* tx, rx enabled */
135
136 case AUX_MU_STAT_REG:
137 res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
138 if (s->read_count > 0) {
139 res |= 0x1; /* data in input buffer */
140 assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
141 res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
142 }
143 return res;
144
145 case AUX_MU_BAUD_REG:
146 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
147 return 0;
148
149 default:
150 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
151 __func__, offset);
152 return 0;
153 }
154}
155
156static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
157 unsigned size)
158{
159 BCM2835AuxState *s = opaque;
160 unsigned char ch;
161
162 switch (offset) {
163 case AUX_ENABLES:
164 if (value != 1) {
165 qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
166 "or disable UART\n", __func__);
167 }
168 break;
169
170 case AUX_MU_IO_REG:
171 /* "DLAB bit set means access baudrate register" is NYI */
172 ch = value;
173 /* XXX this blocks entire thread. Rewrite to use
174 * qemu_chr_fe_write and background I/O callbacks */
175 qemu_chr_fe_write_all(&s->chr, &ch, 1);
176 break;
177
178 case AUX_MU_IER_REG:
179 /* "DLAB bit set means access baudrate register" is NYI */
180 s->ier = value & (TX_INT | RX_INT);
181 bcm2835_aux_update(s);
182 break;
183
184 case AUX_MU_IIR_REG:
185 if (value & 0x2) {
186 s->read_count = 0;
187 }
188 break;
189
190 case AUX_MU_LCR_REG:
191 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
192 break;
193
194 case AUX_MU_MCR_REG:
195 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
196 break;
197
198 case AUX_MU_SCRATCH:
199 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
200 break;
201
202 case AUX_MU_CNTL_REG:
203 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
204 break;
205
206 case AUX_MU_BAUD_REG:
207 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
208 break;
209
210 default:
211 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
212 __func__, offset);
213 }
214
215 bcm2835_aux_update(s);
216}
217
218static int bcm2835_aux_can_receive(void *opaque)
219{
220 BCM2835AuxState *s = opaque;
221
222 return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
223}
224
225static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
226{
227 BCM2835AuxState *s = opaque;
228 int slot;
229
230 slot = s->read_pos + s->read_count;
231 if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
232 slot -= BCM2835_AUX_RX_FIFO_LEN;
233 }
234 s->read_fifo[slot] = value;
235 s->read_count++;
236 if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
237 /* buffer full */
238 }
239 bcm2835_aux_update(s);
240}
241
242static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
243{
244 bcm2835_aux_put_fifo(opaque, *buf);
245}
246
247static const MemoryRegionOps bcm2835_aux_ops = {
248 .read = bcm2835_aux_read,
249 .write = bcm2835_aux_write,
250 .endianness = DEVICE_NATIVE_ENDIAN,
251 .valid.min_access_size = 4,
252 .valid.max_access_size = 4,
253};
254
255static const VMStateDescription vmstate_bcm2835_aux = {
256 .name = TYPE_BCM2835_AUX,
257 .version_id = 1,
258 .minimum_version_id = 1,
259 .fields = (VMStateField[]) {
260 VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
261 BCM2835_AUX_RX_FIFO_LEN),
262 VMSTATE_UINT8(read_pos, BCM2835AuxState),
263 VMSTATE_UINT8(read_count, BCM2835AuxState),
264 VMSTATE_UINT8(ier, BCM2835AuxState),
265 VMSTATE_UINT8(iir, BCM2835AuxState),
266 VMSTATE_END_OF_LIST()
267 }
268};
269
270static void bcm2835_aux_init(Object *obj)
271{
272 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
273 BCM2835AuxState *s = BCM2835_AUX(obj);
274
275 memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
276 TYPE_BCM2835_AUX, 0x100);
277 sysbus_init_mmio(sbd, &s->iomem);
278 sysbus_init_irq(sbd, &s->irq);
279}
280
281static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
282{
283 BCM2835AuxState *s = BCM2835_AUX(dev);
284
285 qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
286 bcm2835_aux_receive, NULL, NULL, s, NULL, true);
287}
288
289static Property bcm2835_aux_props[] = {
290 DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
291 DEFINE_PROP_END_OF_LIST(),
292};
293
294static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
295{
296 DeviceClass *dc = DEVICE_CLASS(oc);
297
298 dc->realize = bcm2835_aux_realize;
299 dc->vmsd = &vmstate_bcm2835_aux;
300 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
301 dc->props = bcm2835_aux_props;
302}
303
304static const TypeInfo bcm2835_aux_info = {
305 .name = TYPE_BCM2835_AUX,
306 .parent = TYPE_SYS_BUS_DEVICE,
307 .instance_size = sizeof(BCM2835AuxState),
308 .instance_init = bcm2835_aux_init,
309 .class_init = bcm2835_aux_class_init,
310};
311
312static void bcm2835_aux_register_types(void)
313{
314 type_register_static(&bcm2835_aux_info);
315}
316
317type_init(bcm2835_aux_register_types)
318