1 | /* |
2 | * QEMU ETRAX System Emulator |
3 | * |
4 | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "hw/irq.h" |
27 | #include "hw/qdev-properties.h" |
28 | #include "hw/sysbus.h" |
29 | #include "chardev/char-fe.h" |
30 | #include "qemu/log.h" |
31 | #include "qemu/module.h" |
32 | |
33 | #define D(x) |
34 | |
35 | #define RW_TR_CTRL (0x00 / 4) |
36 | #define RW_TR_DMA_EN (0x04 / 4) |
37 | #define RW_REC_CTRL (0x08 / 4) |
38 | #define RW_DOUT (0x1c / 4) |
39 | #define RS_STAT_DIN (0x20 / 4) |
40 | #define R_STAT_DIN (0x24 / 4) |
41 | #define RW_INTR_MASK (0x2c / 4) |
42 | #define RW_ACK_INTR (0x30 / 4) |
43 | #define R_INTR (0x34 / 4) |
44 | #define R_MASKED_INTR (0x38 / 4) |
45 | #define R_MAX (0x3c / 4) |
46 | |
47 | #define STAT_DAV 16 |
48 | #define STAT_TR_IDLE 22 |
49 | #define STAT_TR_RDY 24 |
50 | |
51 | #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial" |
52 | #define ETRAX_SERIAL(obj) \ |
53 | OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL) |
54 | |
55 | typedef struct ETRAXSerial { |
56 | SysBusDevice parent_obj; |
57 | |
58 | MemoryRegion mmio; |
59 | CharBackend chr; |
60 | qemu_irq irq; |
61 | |
62 | int pending_tx; |
63 | |
64 | uint8_t rx_fifo[16]; |
65 | unsigned int rx_fifo_pos; |
66 | unsigned int rx_fifo_len; |
67 | |
68 | /* Control registers. */ |
69 | uint32_t regs[R_MAX]; |
70 | } ETRAXSerial; |
71 | |
72 | static void ser_update_irq(ETRAXSerial *s) |
73 | { |
74 | |
75 | if (s->rx_fifo_len) { |
76 | s->regs[R_INTR] |= 8; |
77 | } else { |
78 | s->regs[R_INTR] &= ~8; |
79 | } |
80 | |
81 | s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; |
82 | qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]); |
83 | } |
84 | |
85 | static uint64_t |
86 | ser_read(void *opaque, hwaddr addr, unsigned int size) |
87 | { |
88 | ETRAXSerial *s = opaque; |
89 | uint32_t r = 0; |
90 | |
91 | addr >>= 2; |
92 | switch (addr) |
93 | { |
94 | case R_STAT_DIN: |
95 | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; |
96 | if (s->rx_fifo_len) { |
97 | r |= 1 << STAT_DAV; |
98 | } |
99 | r |= 1 << STAT_TR_RDY; |
100 | r |= 1 << STAT_TR_IDLE; |
101 | break; |
102 | case RS_STAT_DIN: |
103 | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; |
104 | if (s->rx_fifo_len) { |
105 | r |= 1 << STAT_DAV; |
106 | s->rx_fifo_len--; |
107 | } |
108 | r |= 1 << STAT_TR_RDY; |
109 | r |= 1 << STAT_TR_IDLE; |
110 | break; |
111 | default: |
112 | r = s->regs[addr]; |
113 | D(qemu_log("%s " TARGET_FMT_plx "=%x\n" , __func__, addr, r)); |
114 | break; |
115 | } |
116 | return r; |
117 | } |
118 | |
119 | static void |
120 | ser_write(void *opaque, hwaddr addr, |
121 | uint64_t val64, unsigned int size) |
122 | { |
123 | ETRAXSerial *s = opaque; |
124 | uint32_t value = val64; |
125 | unsigned char ch = val64; |
126 | |
127 | D(qemu_log("%s " TARGET_FMT_plx "=%x\n" , __func__, addr, value)); |
128 | addr >>= 2; |
129 | switch (addr) |
130 | { |
131 | case RW_DOUT: |
132 | /* XXX this blocks entire thread. Rewrite to use |
133 | * qemu_chr_fe_write and background I/O callbacks */ |
134 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
135 | s->regs[R_INTR] |= 3; |
136 | s->pending_tx = 1; |
137 | s->regs[addr] = value; |
138 | break; |
139 | case RW_ACK_INTR: |
140 | if (s->pending_tx) { |
141 | value &= ~1; |
142 | s->pending_tx = 0; |
143 | D(qemu_log("fixedup value=%x r_intr=%x\n" , |
144 | value, s->regs[R_INTR])); |
145 | } |
146 | s->regs[addr] = value; |
147 | s->regs[R_INTR] &= ~value; |
148 | D(printf("r_intr=%x\n" , s->regs[R_INTR])); |
149 | break; |
150 | default: |
151 | s->regs[addr] = value; |
152 | break; |
153 | } |
154 | ser_update_irq(s); |
155 | } |
156 | |
157 | static const MemoryRegionOps ser_ops = { |
158 | .read = ser_read, |
159 | .write = ser_write, |
160 | .endianness = DEVICE_NATIVE_ENDIAN, |
161 | .valid = { |
162 | .min_access_size = 4, |
163 | .max_access_size = 4 |
164 | } |
165 | }; |
166 | |
167 | static Property etraxfs_ser_properties[] = { |
168 | DEFINE_PROP_CHR("chardev" , ETRAXSerial, chr), |
169 | DEFINE_PROP_END_OF_LIST(), |
170 | }; |
171 | |
172 | static void serial_receive(void *opaque, const uint8_t *buf, int size) |
173 | { |
174 | ETRAXSerial *s = opaque; |
175 | int i; |
176 | |
177 | /* Got a byte. */ |
178 | if (s->rx_fifo_len >= 16) { |
179 | D(qemu_log("WARNING: UART dropped char.\n" )); |
180 | return; |
181 | } |
182 | |
183 | for (i = 0; i < size; i++) { |
184 | s->rx_fifo[s->rx_fifo_pos] = buf[i]; |
185 | s->rx_fifo_pos++; |
186 | s->rx_fifo_pos &= 15; |
187 | s->rx_fifo_len++; |
188 | } |
189 | |
190 | ser_update_irq(s); |
191 | } |
192 | |
193 | static int serial_can_receive(void *opaque) |
194 | { |
195 | ETRAXSerial *s = opaque; |
196 | |
197 | /* Is the receiver enabled? */ |
198 | if (!(s->regs[RW_REC_CTRL] & (1 << 3))) { |
199 | return 0; |
200 | } |
201 | |
202 | return sizeof(s->rx_fifo) - s->rx_fifo_len; |
203 | } |
204 | |
205 | static void serial_event(void *opaque, int event) |
206 | { |
207 | |
208 | } |
209 | |
210 | static void etraxfs_ser_reset(DeviceState *d) |
211 | { |
212 | ETRAXSerial *s = ETRAX_SERIAL(d); |
213 | |
214 | /* transmitter begins ready and idle. */ |
215 | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY); |
216 | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); |
217 | |
218 | s->regs[RW_REC_CTRL] = 0x10000; |
219 | |
220 | } |
221 | |
222 | static void etraxfs_ser_init(Object *obj) |
223 | { |
224 | ETRAXSerial *s = ETRAX_SERIAL(obj); |
225 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
226 | |
227 | sysbus_init_irq(dev, &s->irq); |
228 | memory_region_init_io(&s->mmio, obj, &ser_ops, s, |
229 | "etraxfs-serial" , R_MAX * 4); |
230 | sysbus_init_mmio(dev, &s->mmio); |
231 | } |
232 | |
233 | static void etraxfs_ser_realize(DeviceState *dev, Error **errp) |
234 | { |
235 | ETRAXSerial *s = ETRAX_SERIAL(dev); |
236 | |
237 | qemu_chr_fe_set_handlers(&s->chr, |
238 | serial_can_receive, serial_receive, |
239 | serial_event, NULL, s, NULL, true); |
240 | } |
241 | |
242 | static void etraxfs_ser_class_init(ObjectClass *klass, void *data) |
243 | { |
244 | DeviceClass *dc = DEVICE_CLASS(klass); |
245 | |
246 | dc->reset = etraxfs_ser_reset; |
247 | dc->props = etraxfs_ser_properties; |
248 | dc->realize = etraxfs_ser_realize; |
249 | } |
250 | |
251 | static const TypeInfo etraxfs_ser_info = { |
252 | .name = TYPE_ETRAX_FS_SERIAL, |
253 | .parent = TYPE_SYS_BUS_DEVICE, |
254 | .instance_size = sizeof(ETRAXSerial), |
255 | .instance_init = etraxfs_ser_init, |
256 | .class_init = etraxfs_ser_class_init, |
257 | }; |
258 | |
259 | static void etraxfs_serial_register_types(void) |
260 | { |
261 | type_register_static(&etraxfs_ser_info); |
262 | } |
263 | |
264 | type_init(etraxfs_serial_register_types) |
265 | |