1/*
2 * Cortex-A9MPCore internal peripheral emulation.
3 *
4 * Copyright (c) 2009 CodeSourcery.
5 * Copyright (c) 2011 Linaro Limited.
6 * Written by Paul Brook, Peter Maydell.
7 *
8 * This code is licensed under the GPL.
9 */
10
11#include "qemu/osdep.h"
12#include "qapi/error.h"
13#include "qemu/module.h"
14#include "hw/cpu/a9mpcore.h"
15#include "hw/irq.h"
16#include "hw/qdev-properties.h"
17#include "hw/core/cpu.h"
18
19static void a9mp_priv_set_irq(void *opaque, int irq, int level)
20{
21 A9MPPrivState *s = (A9MPPrivState *)opaque;
22
23 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
24}
25
26static void a9mp_priv_initfn(Object *obj)
27{
28 A9MPPrivState *s = A9MPCORE_PRIV(obj);
29
30 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
31 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
32
33 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU);
34
35 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
36
37 sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer),
38 TYPE_A9_GTIMER);
39
40 sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
41 TYPE_ARM_MPTIMER);
42
43 sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt),
44 TYPE_ARM_MPTIMER);
45}
46
47static void a9mp_priv_realize(DeviceState *dev, Error **errp)
48{
49 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
50 A9MPPrivState *s = A9MPCORE_PRIV(dev);
51 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
52 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
53 *wdtbusdev;
54 Error *err = NULL;
55 int i;
56 bool has_el3;
57 Object *cpuobj;
58
59 scudev = DEVICE(&s->scu);
60 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
61 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
62 if (err != NULL) {
63 error_propagate(errp, err);
64 return;
65 }
66 scubusdev = SYS_BUS_DEVICE(&s->scu);
67
68 gicdev = DEVICE(&s->gic);
69 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
70 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
71
72 /* Make the GIC's TZ support match the CPUs. We assume that
73 * either all the CPUs have TZ, or none do.
74 */
75 cpuobj = OBJECT(qemu_get_cpu(0));
76 has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
77 object_property_get_bool(cpuobj, "has_el3", &error_abort);
78 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
79
80 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
81 if (err != NULL) {
82 error_propagate(errp, err);
83 return;
84 }
85 gicbusdev = SYS_BUS_DEVICE(&s->gic);
86
87 /* Pass through outbound IRQ lines from the GIC */
88 sysbus_pass_irq(sbd, gicbusdev);
89
90 /* Pass through inbound GPIO lines to the GIC */
91 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
92
93 gtimerdev = DEVICE(&s->gtimer);
94 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
95 object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
96 if (err != NULL) {
97 error_propagate(errp, err);
98 return;
99 }
100 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
101
102 mptimerdev = DEVICE(&s->mptimer);
103 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
104 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
105 if (err != NULL) {
106 error_propagate(errp, err);
107 return;
108 }
109 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
110
111 wdtdev = DEVICE(&s->wdt);
112 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
113 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
114 if (err != NULL) {
115 error_propagate(errp, err);
116 return;
117 }
118 wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
119
120 /* Memory map (addresses are offsets from PERIPHBASE):
121 * 0x0000-0x00ff -- Snoop Control Unit
122 * 0x0100-0x01ff -- GIC CPU interface
123 * 0x0200-0x02ff -- Global Timer
124 * 0x0300-0x05ff -- nothing
125 * 0x0600-0x06ff -- private timers and watchdogs
126 * 0x0700-0x0fff -- nothing
127 * 0x1000-0x1fff -- GIC Distributor
128 */
129 memory_region_add_subregion(&s->container, 0,
130 sysbus_mmio_get_region(scubusdev, 0));
131 /* GIC CPU interface */
132 memory_region_add_subregion(&s->container, 0x100,
133 sysbus_mmio_get_region(gicbusdev, 1));
134 memory_region_add_subregion(&s->container, 0x200,
135 sysbus_mmio_get_region(gtimerbusdev, 0));
136 /* Note that the A9 exposes only the "timer/watchdog for this core"
137 * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
138 */
139 memory_region_add_subregion(&s->container, 0x600,
140 sysbus_mmio_get_region(mptimerbusdev, 0));
141 memory_region_add_subregion(&s->container, 0x620,
142 sysbus_mmio_get_region(wdtbusdev, 0));
143 memory_region_add_subregion(&s->container, 0x1000,
144 sysbus_mmio_get_region(gicbusdev, 0));
145
146 /* Wire up the interrupt from each watchdog and timer.
147 * For each core the global timer is PPI 27, the private
148 * timer is PPI 29 and the watchdog PPI 30.
149 */
150 for (i = 0; i < s->num_cpu; i++) {
151 int ppibase = (s->num_irq - 32) + i * 32;
152 sysbus_connect_irq(gtimerbusdev, i,
153 qdev_get_gpio_in(gicdev, ppibase + 27));
154 sysbus_connect_irq(mptimerbusdev, i,
155 qdev_get_gpio_in(gicdev, ppibase + 29));
156 sysbus_connect_irq(wdtbusdev, i,
157 qdev_get_gpio_in(gicdev, ppibase + 30));
158 }
159}
160
161static Property a9mp_priv_properties[] = {
162 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
163 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
164 * IRQ lines (with another 32 internal). We default to 64+32, which
165 * is the number provided by the Cortex-A9MP test chip in the
166 * Realview PBX-A9 and Versatile Express A9 development boards.
167 * Other boards may differ and should set this property appropriately.
168 */
169 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
170 DEFINE_PROP_END_OF_LIST(),
171};
172
173static void a9mp_priv_class_init(ObjectClass *klass, void *data)
174{
175 DeviceClass *dc = DEVICE_CLASS(klass);
176
177 dc->realize = a9mp_priv_realize;
178 dc->props = a9mp_priv_properties;
179}
180
181static const TypeInfo a9mp_priv_info = {
182 .name = TYPE_A9MPCORE_PRIV,
183 .parent = TYPE_SYS_BUS_DEVICE,
184 .instance_size = sizeof(A9MPPrivState),
185 .instance_init = a9mp_priv_initfn,
186 .class_init = a9mp_priv_class_init,
187};
188
189static void a9mp_register_types(void)
190{
191 type_register_static(&a9mp_priv_info);
192}
193
194type_init(a9mp_register_types)
195