1 | /* |
2 | * ARM11MPCore internal peripheral emulation. |
3 | * |
4 | * Copyright (c) 2006-2007 CodeSourcery. |
5 | * Written by Paul Brook |
6 | * |
7 | * This code is licensed under the GPL. |
8 | */ |
9 | |
10 | #include "qemu/osdep.h" |
11 | #include "qapi/error.h" |
12 | #include "qemu/module.h" |
13 | #include "hw/cpu/arm11mpcore.h" |
14 | #include "hw/intc/realview_gic.h" |
15 | #include "hw/irq.h" |
16 | #include "hw/qdev-properties.h" |
17 | |
18 | |
19 | static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
20 | { |
21 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
22 | |
23 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); |
24 | } |
25 | |
26 | static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
27 | { |
28 | int i; |
29 | SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); |
30 | DeviceState *gicdev = DEVICE(&s->gic); |
31 | SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); |
32 | SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); |
33 | SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); |
34 | |
35 | memory_region_add_subregion(&s->container, 0, |
36 | sysbus_mmio_get_region(scubusdev, 0)); |
37 | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs |
38 | * at 0x200, 0x300... |
39 | */ |
40 | for (i = 0; i < (s->num_cpu + 1); i++) { |
41 | hwaddr offset = 0x100 + (i * 0x100); |
42 | memory_region_add_subregion(&s->container, offset, |
43 | sysbus_mmio_get_region(gicbusdev, i + 1)); |
44 | } |
45 | /* Add the regions for timer and watchdog for "current CPU" and |
46 | * for each specific CPU. |
47 | */ |
48 | for (i = 0; i < (s->num_cpu + 1); i++) { |
49 | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
50 | hwaddr offset = 0x600 + i * 0x100; |
51 | memory_region_add_subregion(&s->container, offset, |
52 | sysbus_mmio_get_region(timerbusdev, i)); |
53 | memory_region_add_subregion(&s->container, offset + 0x20, |
54 | sysbus_mmio_get_region(wdtbusdev, i)); |
55 | } |
56 | memory_region_add_subregion(&s->container, 0x1000, |
57 | sysbus_mmio_get_region(gicbusdev, 0)); |
58 | /* Wire up the interrupt from each watchdog and timer. |
59 | * For each core the timer is PPI 29 and the watchdog PPI 30. |
60 | */ |
61 | for (i = 0; i < s->num_cpu; i++) { |
62 | int ppibase = (s->num_irq - 32) + i * 32; |
63 | sysbus_connect_irq(timerbusdev, i, |
64 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
65 | sysbus_connect_irq(wdtbusdev, i, |
66 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
67 | } |
68 | } |
69 | |
70 | static void mpcore_priv_realize(DeviceState *dev, Error **errp) |
71 | { |
72 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
73 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); |
74 | DeviceState *scudev = DEVICE(&s->scu); |
75 | DeviceState *gicdev = DEVICE(&s->gic); |
76 | DeviceState *mptimerdev = DEVICE(&s->mptimer); |
77 | DeviceState *wdtimerdev = DEVICE(&s->wdtimer); |
78 | Error *err = NULL; |
79 | |
80 | qdev_prop_set_uint32(scudev, "num-cpu" , s->num_cpu); |
81 | object_property_set_bool(OBJECT(&s->scu), true, "realized" , &err); |
82 | if (err != NULL) { |
83 | error_propagate(errp, err); |
84 | return; |
85 | } |
86 | |
87 | qdev_prop_set_uint32(gicdev, "num-cpu" , s->num_cpu); |
88 | qdev_prop_set_uint32(gicdev, "num-irq" , s->num_irq); |
89 | object_property_set_bool(OBJECT(&s->gic), true, "realized" , &err); |
90 | if (err != NULL) { |
91 | error_propagate(errp, err); |
92 | return; |
93 | } |
94 | |
95 | /* Pass through outbound IRQ lines from the GIC */ |
96 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); |
97 | |
98 | /* Pass through inbound GPIO lines to the GIC */ |
99 | qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); |
100 | |
101 | qdev_prop_set_uint32(mptimerdev, "num-cpu" , s->num_cpu); |
102 | object_property_set_bool(OBJECT(&s->mptimer), true, "realized" , &err); |
103 | if (err != NULL) { |
104 | error_propagate(errp, err); |
105 | return; |
106 | } |
107 | |
108 | qdev_prop_set_uint32(wdtimerdev, "num-cpu" , s->num_cpu); |
109 | object_property_set_bool(OBJECT(&s->wdtimer), true, "realized" , &err); |
110 | if (err != NULL) { |
111 | error_propagate(errp, err); |
112 | return; |
113 | } |
114 | |
115 | mpcore_priv_map_setup(s); |
116 | } |
117 | |
118 | static void mpcore_priv_initfn(Object *obj) |
119 | { |
120 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
121 | ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); |
122 | |
123 | memory_region_init(&s->container, OBJECT(s), |
124 | "mpcore-priv-container" , 0x2000); |
125 | sysbus_init_mmio(sbd, &s->container); |
126 | |
127 | sysbus_init_child_obj(obj, "scu" , &s->scu, sizeof(s->scu), TYPE_ARM11_SCU); |
128 | |
129 | sysbus_init_child_obj(obj, "gic" , &s->gic, sizeof(s->gic), TYPE_ARM_GIC); |
130 | /* Request the legacy 11MPCore GIC behaviour: */ |
131 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision" , 0); |
132 | |
133 | sysbus_init_child_obj(obj, "mptimer" , &s->mptimer, sizeof(s->mptimer), |
134 | TYPE_ARM_MPTIMER); |
135 | |
136 | sysbus_init_child_obj(obj, "wdtimer" , &s->wdtimer, sizeof(s->wdtimer), |
137 | TYPE_ARM_MPTIMER); |
138 | } |
139 | |
140 | static Property mpcore_priv_properties[] = { |
141 | DEFINE_PROP_UINT32("num-cpu" , ARM11MPCorePriveState, num_cpu, 1), |
142 | /* The ARM11 MPCORE TRM says the on-chip controller may have |
143 | * anything from 0 to 224 external interrupt IRQ lines (with another |
144 | * 32 internal). We default to 32+32, which is the number provided by |
145 | * the ARM11 MPCore test chip in the Realview Versatile Express |
146 | * coretile. Other boards may differ and should set this property |
147 | * appropriately. Some Linux kernels may not boot if the hardware |
148 | * has more IRQ lines than the kernel expects. |
149 | */ |
150 | DEFINE_PROP_UINT32("num-irq" , ARM11MPCorePriveState, num_irq, 64), |
151 | DEFINE_PROP_END_OF_LIST(), |
152 | }; |
153 | |
154 | static void mpcore_priv_class_init(ObjectClass *klass, void *data) |
155 | { |
156 | DeviceClass *dc = DEVICE_CLASS(klass); |
157 | |
158 | dc->realize = mpcore_priv_realize; |
159 | dc->props = mpcore_priv_properties; |
160 | } |
161 | |
162 | static const TypeInfo mpcore_priv_info = { |
163 | .name = TYPE_ARM11MPCORE_PRIV, |
164 | .parent = TYPE_SYS_BUS_DEVICE, |
165 | .instance_size = sizeof(ARM11MPCorePriveState), |
166 | .instance_init = mpcore_priv_initfn, |
167 | .class_init = mpcore_priv_class_init, |
168 | }; |
169 | |
170 | static void arm11mpcore_register_types(void) |
171 | { |
172 | type_register_static(&mpcore_priv_info); |
173 | } |
174 | |
175 | type_init(arm11mpcore_register_types) |
176 | |