1 | /* |
2 | * QEMU G364 framebuffer Emulator. |
3 | * |
4 | * Copyright (c) 2007-2011 Herve Poussineau |
5 | * |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License as |
8 | * published by the Free Software Foundation; either version 2 of |
9 | * the License, or (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License along |
17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #include "qemu/osdep.h" |
21 | #include "qemu/units.h" |
22 | #include "hw/hw.h" |
23 | #include "hw/irq.h" |
24 | #include "hw/qdev-properties.h" |
25 | #include "qemu/error-report.h" |
26 | #include "qemu/module.h" |
27 | #include "ui/console.h" |
28 | #include "ui/pixel_ops.h" |
29 | #include "trace.h" |
30 | #include "hw/sysbus.h" |
31 | #include "migration/vmstate.h" |
32 | |
33 | typedef struct G364State { |
34 | /* hardware */ |
35 | uint8_t *vram; |
36 | uint32_t vram_size; |
37 | qemu_irq irq; |
38 | MemoryRegion mem_vram; |
39 | MemoryRegion mem_ctrl; |
40 | /* registers */ |
41 | uint8_t color_palette[256][3]; |
42 | uint8_t cursor_palette[3][3]; |
43 | uint16_t cursor[512]; |
44 | uint32_t cursor_position; |
45 | uint32_t ctla; |
46 | uint32_t top_of_screen; |
47 | uint32_t width, height; /* in pixels */ |
48 | /* display refresh support */ |
49 | QemuConsole *con; |
50 | int depth; |
51 | int blanked; |
52 | } G364State; |
53 | |
54 | #define REG_BOOT 0x000000 |
55 | #define REG_DISPLAY 0x000118 |
56 | #define REG_VDISPLAY 0x000150 |
57 | #define REG_CTLA 0x000300 |
58 | #define REG_TOP 0x000400 |
59 | #define REG_CURS_PAL 0x000508 |
60 | #define REG_CURS_POS 0x000638 |
61 | #define REG_CLR_PAL 0x000800 |
62 | #define REG_CURS_PAT 0x001000 |
63 | #define REG_RESET 0x100000 |
64 | |
65 | #define CTLA_FORCE_BLANK 0x00000400 |
66 | #define CTLA_NO_CURSOR 0x00800000 |
67 | |
68 | #define G364_PAGE_SIZE 4096 |
69 | |
70 | static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page) |
71 | { |
72 | return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE); |
73 | } |
74 | |
75 | static void g364fb_draw_graphic8(G364State *s) |
76 | { |
77 | DisplaySurface *surface = qemu_console_surface(s->con); |
78 | DirtyBitmapSnapshot *snap; |
79 | int i, w; |
80 | uint8_t *vram; |
81 | uint8_t *data_display, *dd; |
82 | ram_addr_t page; |
83 | int x, y; |
84 | int xmin, xmax; |
85 | int ymin, ymax; |
86 | int xcursor, ycursor; |
87 | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); |
88 | |
89 | switch (surface_bits_per_pixel(surface)) { |
90 | case 8: |
91 | rgb_to_pixel = rgb_to_pixel8; |
92 | w = 1; |
93 | break; |
94 | case 15: |
95 | rgb_to_pixel = rgb_to_pixel15; |
96 | w = 2; |
97 | break; |
98 | case 16: |
99 | rgb_to_pixel = rgb_to_pixel16; |
100 | w = 2; |
101 | break; |
102 | case 32: |
103 | rgb_to_pixel = rgb_to_pixel32; |
104 | w = 4; |
105 | break; |
106 | default: |
107 | hw_error("g364: unknown host depth %d" , |
108 | surface_bits_per_pixel(surface)); |
109 | return; |
110 | } |
111 | |
112 | page = 0; |
113 | |
114 | x = y = 0; |
115 | xmin = s->width; |
116 | xmax = 0; |
117 | ymin = s->height; |
118 | ymax = 0; |
119 | |
120 | if (!(s->ctla & CTLA_NO_CURSOR)) { |
121 | xcursor = s->cursor_position >> 12; |
122 | ycursor = s->cursor_position & 0xfff; |
123 | } else { |
124 | xcursor = ycursor = -65; |
125 | } |
126 | |
127 | vram = s->vram + s->top_of_screen; |
128 | /* XXX: out of range in vram? */ |
129 | data_display = dd = surface_data(surface); |
130 | snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size, |
131 | DIRTY_MEMORY_VGA); |
132 | while (y < s->height) { |
133 | if (check_dirty(s, snap, page)) { |
134 | if (y < ymin) |
135 | ymin = ymax = y; |
136 | if (x < xmin) |
137 | xmin = x; |
138 | for (i = 0; i < G364_PAGE_SIZE; i++) { |
139 | uint8_t index; |
140 | unsigned int color; |
141 | if (unlikely((y >= ycursor && y < ycursor + 64) && |
142 | (x >= xcursor && x < xcursor + 64))) { |
143 | /* pointer area */ |
144 | int xdiff = x - xcursor; |
145 | uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; |
146 | int op = (curs >> ((xdiff & 7) * 2)) & 3; |
147 | if (likely(op == 0)) { |
148 | /* transparent */ |
149 | index = *vram; |
150 | color = (*rgb_to_pixel)( |
151 | s->color_palette[index][0], |
152 | s->color_palette[index][1], |
153 | s->color_palette[index][2]); |
154 | } else { |
155 | /* get cursor color */ |
156 | index = op - 1; |
157 | color = (*rgb_to_pixel)( |
158 | s->cursor_palette[index][0], |
159 | s->cursor_palette[index][1], |
160 | s->cursor_palette[index][2]); |
161 | } |
162 | } else { |
163 | /* normal area */ |
164 | index = *vram; |
165 | color = (*rgb_to_pixel)( |
166 | s->color_palette[index][0], |
167 | s->color_palette[index][1], |
168 | s->color_palette[index][2]); |
169 | } |
170 | memcpy(dd, &color, w); |
171 | dd += w; |
172 | x++; |
173 | vram++; |
174 | if (x == s->width) { |
175 | xmax = s->width - 1; |
176 | y++; |
177 | if (y == s->height) { |
178 | ymax = s->height - 1; |
179 | goto done; |
180 | } |
181 | data_display = dd = data_display + surface_stride(surface); |
182 | xmin = 0; |
183 | x = 0; |
184 | } |
185 | } |
186 | if (x > xmax) |
187 | xmax = x; |
188 | if (y > ymax) |
189 | ymax = y; |
190 | } else { |
191 | int dy; |
192 | if (xmax || ymax) { |
193 | dpy_gfx_update(s->con, xmin, ymin, |
194 | xmax - xmin + 1, ymax - ymin + 1); |
195 | xmin = s->width; |
196 | xmax = 0; |
197 | ymin = s->height; |
198 | ymax = 0; |
199 | } |
200 | x += G364_PAGE_SIZE; |
201 | dy = x / s->width; |
202 | x = x % s->width; |
203 | y += dy; |
204 | vram += G364_PAGE_SIZE; |
205 | data_display += dy * surface_stride(surface); |
206 | dd = data_display + x * w; |
207 | } |
208 | page += G364_PAGE_SIZE; |
209 | } |
210 | |
211 | done: |
212 | if (xmax || ymax) { |
213 | dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
214 | } |
215 | g_free(snap); |
216 | } |
217 | |
218 | static void g364fb_draw_blank(G364State *s) |
219 | { |
220 | DisplaySurface *surface = qemu_console_surface(s->con); |
221 | int i, w; |
222 | uint8_t *d; |
223 | |
224 | if (s->blanked) { |
225 | /* Screen is already blank. No need to redraw it */ |
226 | return; |
227 | } |
228 | |
229 | w = s->width * surface_bytes_per_pixel(surface); |
230 | d = surface_data(surface); |
231 | for (i = 0; i < s->height; i++) { |
232 | memset(d, 0, w); |
233 | d += surface_stride(surface); |
234 | } |
235 | |
236 | dpy_gfx_update_full(s->con); |
237 | s->blanked = 1; |
238 | } |
239 | |
240 | static void g364fb_update_display(void *opaque) |
241 | { |
242 | G364State *s = opaque; |
243 | DisplaySurface *surface = qemu_console_surface(s->con); |
244 | |
245 | qemu_flush_coalesced_mmio_buffer(); |
246 | |
247 | if (s->width == 0 || s->height == 0) |
248 | return; |
249 | |
250 | if (s->width != surface_width(surface) || |
251 | s->height != surface_height(surface)) { |
252 | qemu_console_resize(s->con, s->width, s->height); |
253 | } |
254 | |
255 | if (s->ctla & CTLA_FORCE_BLANK) { |
256 | g364fb_draw_blank(s); |
257 | } else if (s->depth == 8) { |
258 | g364fb_draw_graphic8(s); |
259 | } else { |
260 | error_report("g364: unknown guest depth %d" , s->depth); |
261 | } |
262 | |
263 | qemu_irq_raise(s->irq); |
264 | } |
265 | |
266 | static inline void g364fb_invalidate_display(void *opaque) |
267 | { |
268 | G364State *s = opaque; |
269 | |
270 | s->blanked = 0; |
271 | memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); |
272 | } |
273 | |
274 | static void g364fb_reset(G364State *s) |
275 | { |
276 | qemu_irq_lower(s->irq); |
277 | |
278 | memset(s->color_palette, 0, sizeof(s->color_palette)); |
279 | memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); |
280 | memset(s->cursor, 0, sizeof(s->cursor)); |
281 | s->cursor_position = 0; |
282 | s->ctla = 0; |
283 | s->top_of_screen = 0; |
284 | s->width = s->height = 0; |
285 | memset(s->vram, 0, s->vram_size); |
286 | g364fb_invalidate_display(s); |
287 | } |
288 | |
289 | /* called for accesses to io ports */ |
290 | static uint64_t g364fb_ctrl_read(void *opaque, |
291 | hwaddr addr, |
292 | unsigned int size) |
293 | { |
294 | G364State *s = opaque; |
295 | uint32_t val; |
296 | |
297 | if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
298 | /* cursor pattern */ |
299 | int idx = (addr - REG_CURS_PAT) >> 3; |
300 | val = s->cursor[idx]; |
301 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
302 | /* cursor palette */ |
303 | int idx = (addr - REG_CURS_PAL) >> 3; |
304 | val = ((uint32_t)s->cursor_palette[idx][0] << 16); |
305 | val |= ((uint32_t)s->cursor_palette[idx][1] << 8); |
306 | val |= ((uint32_t)s->cursor_palette[idx][2] << 0); |
307 | } else { |
308 | switch (addr) { |
309 | case REG_DISPLAY: |
310 | val = s->width / 4; |
311 | break; |
312 | case REG_VDISPLAY: |
313 | val = s->height * 2; |
314 | break; |
315 | case REG_CTLA: |
316 | val = s->ctla; |
317 | break; |
318 | default: |
319 | { |
320 | error_report("g364: invalid read at [" TARGET_FMT_plx "]" , |
321 | addr); |
322 | val = 0; |
323 | break; |
324 | } |
325 | } |
326 | } |
327 | |
328 | trace_g364fb_read(addr, val); |
329 | |
330 | return val; |
331 | } |
332 | |
333 | static void g364fb_update_depth(G364State *s) |
334 | { |
335 | static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; |
336 | s->depth = depths[(s->ctla & 0x00700000) >> 20]; |
337 | } |
338 | |
339 | static void g364_invalidate_cursor_position(G364State *s) |
340 | { |
341 | DisplaySurface *surface = qemu_console_surface(s->con); |
342 | int ymin, ymax, start, end; |
343 | |
344 | /* invalidate only near the cursor */ |
345 | ymin = s->cursor_position & 0xfff; |
346 | ymax = MIN(s->height, ymin + 64); |
347 | start = ymin * surface_stride(surface); |
348 | end = (ymax + 1) * surface_stride(surface); |
349 | |
350 | memory_region_set_dirty(&s->mem_vram, start, end - start); |
351 | } |
352 | |
353 | static void g364fb_ctrl_write(void *opaque, |
354 | hwaddr addr, |
355 | uint64_t val, |
356 | unsigned int size) |
357 | { |
358 | G364State *s = opaque; |
359 | |
360 | trace_g364fb_write(addr, val); |
361 | |
362 | if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { |
363 | /* color palette */ |
364 | int idx = (addr - REG_CLR_PAL) >> 3; |
365 | s->color_palette[idx][0] = (val >> 16) & 0xff; |
366 | s->color_palette[idx][1] = (val >> 8) & 0xff; |
367 | s->color_palette[idx][2] = val & 0xff; |
368 | g364fb_invalidate_display(s); |
369 | } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
370 | /* cursor pattern */ |
371 | int idx = (addr - REG_CURS_PAT) >> 3; |
372 | s->cursor[idx] = val; |
373 | g364fb_invalidate_display(s); |
374 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
375 | /* cursor palette */ |
376 | int idx = (addr - REG_CURS_PAL) >> 3; |
377 | s->cursor_palette[idx][0] = (val >> 16) & 0xff; |
378 | s->cursor_palette[idx][1] = (val >> 8) & 0xff; |
379 | s->cursor_palette[idx][2] = val & 0xff; |
380 | g364fb_invalidate_display(s); |
381 | } else { |
382 | switch (addr) { |
383 | case REG_BOOT: /* Boot timing */ |
384 | case 0x00108: /* Line timing: half sync */ |
385 | case 0x00110: /* Line timing: back porch */ |
386 | case 0x00120: /* Line timing: short display */ |
387 | case 0x00128: /* Frame timing: broad pulse */ |
388 | case 0x00130: /* Frame timing: v sync */ |
389 | case 0x00138: /* Frame timing: v preequalise */ |
390 | case 0x00140: /* Frame timing: v postequalise */ |
391 | case 0x00148: /* Frame timing: v blank */ |
392 | case 0x00158: /* Line timing: line time */ |
393 | case 0x00160: /* Frame store: line start */ |
394 | case 0x00168: /* vram cycle: mem init */ |
395 | case 0x00170: /* vram cycle: transfer delay */ |
396 | case 0x00200: /* vram cycle: mask register */ |
397 | /* ignore */ |
398 | break; |
399 | case REG_TOP: |
400 | s->top_of_screen = val; |
401 | g364fb_invalidate_display(s); |
402 | break; |
403 | case REG_DISPLAY: |
404 | s->width = val * 4; |
405 | break; |
406 | case REG_VDISPLAY: |
407 | s->height = val / 2; |
408 | break; |
409 | case REG_CTLA: |
410 | s->ctla = val; |
411 | g364fb_update_depth(s); |
412 | g364fb_invalidate_display(s); |
413 | break; |
414 | case REG_CURS_POS: |
415 | g364_invalidate_cursor_position(s); |
416 | s->cursor_position = val; |
417 | g364_invalidate_cursor_position(s); |
418 | break; |
419 | case REG_RESET: |
420 | g364fb_reset(s); |
421 | break; |
422 | default: |
423 | error_report("g364: invalid write of 0x%" PRIx64 |
424 | " at [" TARGET_FMT_plx "]" , val, addr); |
425 | break; |
426 | } |
427 | } |
428 | qemu_irq_lower(s->irq); |
429 | } |
430 | |
431 | static const MemoryRegionOps g364fb_ctrl_ops = { |
432 | .read = g364fb_ctrl_read, |
433 | .write = g364fb_ctrl_write, |
434 | .endianness = DEVICE_LITTLE_ENDIAN, |
435 | .impl.min_access_size = 4, |
436 | .impl.max_access_size = 4, |
437 | }; |
438 | |
439 | static int g364fb_post_load(void *opaque, int version_id) |
440 | { |
441 | G364State *s = opaque; |
442 | |
443 | /* force refresh */ |
444 | g364fb_update_depth(s); |
445 | g364fb_invalidate_display(s); |
446 | |
447 | return 0; |
448 | } |
449 | |
450 | static const VMStateDescription vmstate_g364fb = { |
451 | .name = "g364fb" , |
452 | .version_id = 1, |
453 | .minimum_version_id = 1, |
454 | .post_load = g364fb_post_load, |
455 | .fields = (VMStateField[]) { |
456 | VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size), |
457 | VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), |
458 | VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), |
459 | VMSTATE_UINT16_ARRAY(cursor, G364State, 512), |
460 | VMSTATE_UINT32(cursor_position, G364State), |
461 | VMSTATE_UINT32(ctla, G364State), |
462 | VMSTATE_UINT32(top_of_screen, G364State), |
463 | VMSTATE_UINT32(width, G364State), |
464 | VMSTATE_UINT32(height, G364State), |
465 | VMSTATE_END_OF_LIST() |
466 | } |
467 | }; |
468 | |
469 | static const GraphicHwOps g364fb_ops = { |
470 | .invalidate = g364fb_invalidate_display, |
471 | .gfx_update = g364fb_update_display, |
472 | }; |
473 | |
474 | static void g364fb_init(DeviceState *dev, G364State *s) |
475 | { |
476 | s->vram = g_malloc0(s->vram_size); |
477 | |
478 | s->con = graphic_console_init(dev, 0, &g364fb_ops, s); |
479 | |
480 | memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl" , 0x180000); |
481 | memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram" , |
482 | s->vram_size, s->vram); |
483 | vmstate_register_ram(&s->mem_vram, dev); |
484 | memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA); |
485 | } |
486 | |
487 | #define TYPE_G364 "sysbus-g364" |
488 | #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) |
489 | |
490 | typedef struct { |
491 | SysBusDevice parent_obj; |
492 | |
493 | G364State g364; |
494 | } G364SysBusState; |
495 | |
496 | static void g364fb_sysbus_realize(DeviceState *dev, Error **errp) |
497 | { |
498 | G364SysBusState *sbs = G364(dev); |
499 | G364State *s = &sbs->g364; |
500 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
501 | |
502 | g364fb_init(dev, s); |
503 | sysbus_init_irq(sbd, &s->irq); |
504 | sysbus_init_mmio(sbd, &s->mem_ctrl); |
505 | sysbus_init_mmio(sbd, &s->mem_vram); |
506 | } |
507 | |
508 | static void g364fb_sysbus_reset(DeviceState *d) |
509 | { |
510 | G364SysBusState *s = G364(d); |
511 | |
512 | g364fb_reset(&s->g364); |
513 | } |
514 | |
515 | static Property g364fb_sysbus_properties[] = { |
516 | DEFINE_PROP_UINT32("vram_size" , G364SysBusState, g364.vram_size, 8 * MiB), |
517 | DEFINE_PROP_END_OF_LIST(), |
518 | }; |
519 | |
520 | static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) |
521 | { |
522 | DeviceClass *dc = DEVICE_CLASS(klass); |
523 | |
524 | dc->realize = g364fb_sysbus_realize; |
525 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
526 | dc->desc = "G364 framebuffer" ; |
527 | dc->reset = g364fb_sysbus_reset; |
528 | dc->vmsd = &vmstate_g364fb; |
529 | dc->props = g364fb_sysbus_properties; |
530 | } |
531 | |
532 | static const TypeInfo g364fb_sysbus_info = { |
533 | .name = TYPE_G364, |
534 | .parent = TYPE_SYS_BUS_DEVICE, |
535 | .instance_size = sizeof(G364SysBusState), |
536 | .class_init = g364fb_sysbus_class_init, |
537 | }; |
538 | |
539 | static void g364fb_register_types(void) |
540 | { |
541 | type_register_static(&g364fb_sysbus_info); |
542 | } |
543 | |
544 | type_init(g364fb_register_types) |
545 | |