1 | /* |
2 | * xlnx_dp.c |
3 | * |
4 | * Copyright (C) 2015 : GreenSocs Ltd |
5 | * http://www.greensocs.com/ , email: info@greensocs.com |
6 | * |
7 | * Developed by : |
8 | * Frederic Konrad <fred.konrad@greensocs.com> |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by |
12 | * the Free Software Foundation, either version 2 of the License, or |
13 | * (at your option)any later version. |
14 | * |
15 | * This program is distributed in the hope that it will be useful, |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
18 | * GNU General Public License for more details. |
19 | * |
20 | * You should have received a copy of the GNU General Public License along |
21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
22 | * |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qapi/error.h" |
27 | #include "qemu/log.h" |
28 | #include "qemu/module.h" |
29 | #include "hw/display/xlnx_dp.h" |
30 | #include "hw/irq.h" |
31 | #include "migration/vmstate.h" |
32 | |
33 | #ifndef DEBUG_DP |
34 | #define DEBUG_DP 0 |
35 | #endif |
36 | |
37 | #define DPRINTF(fmt, ...) do { \ |
38 | if (DEBUG_DP) { \ |
39 | qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \ |
40 | } \ |
41 | } while (0) |
42 | |
43 | /* |
44 | * Register offset for DP. |
45 | */ |
46 | #define DP_LINK_BW_SET (0x0000 >> 2) |
47 | #define DP_LANE_COUNT_SET (0x0004 >> 2) |
48 | #define DP_ENHANCED_FRAME_EN (0x0008 >> 2) |
49 | #define DP_TRAINING_PATTERN_SET (0x000C >> 2) |
50 | #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2) |
51 | #define DP_SCRAMBLING_DISABLE (0x0014 >> 2) |
52 | #define DP_DOWNSPREAD_CTRL (0x0018 >> 2) |
53 | #define DP_SOFTWARE_RESET (0x001C >> 2) |
54 | #define DP_TRANSMITTER_ENABLE (0x0080 >> 2) |
55 | #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2) |
56 | #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2) |
57 | #define DP_VERSION_REGISTER (0x00F8 >> 2) |
58 | #define DP_CORE_ID (0x00FC >> 2) |
59 | |
60 | #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2) |
61 | #define AUX_ADDR_ONLY_MASK (0x1000) |
62 | #define AUX_COMMAND_MASK (0x0F00) |
63 | #define AUX_COMMAND_SHIFT (8) |
64 | #define AUX_COMMAND_NBYTES (0x000F) |
65 | |
66 | #define DP_AUX_WRITE_FIFO (0x0104 >> 2) |
67 | #define DP_AUX_ADDRESS (0x0108 >> 2) |
68 | #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2) |
69 | #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2) |
70 | #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2) |
71 | #define DP_AUX_REPLY_DATA (0x0134 >> 2) |
72 | #define DP_AUX_REPLY_CODE (0x0138 >> 2) |
73 | #define DP_AUX_REPLY_COUNT (0x013C >> 2) |
74 | #define DP_REPLY_DATA_COUNT (0x0148 >> 2) |
75 | #define DP_REPLY_STATUS (0x014C >> 2) |
76 | #define DP_HPD_DURATION (0x0150 >> 2) |
77 | #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2) |
78 | #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2) |
79 | #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2) |
80 | #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2) |
81 | #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2) |
82 | #define DP_MAIN_STREAM_HRES (0x0194 >> 2) |
83 | #define DP_MAIN_STREAM_VRES (0x0198 >> 2) |
84 | #define DP_MAIN_STREAM_HSTART (0x019C >> 2) |
85 | #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2) |
86 | #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2) |
87 | #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2) |
88 | #define DP_MAIN_STREAM_M_VID (0x01AC >> 2) |
89 | #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2) |
90 | #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2) |
91 | #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2) |
92 | #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2) |
93 | #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2) |
94 | #define DP_INIT_WAIT (0x01CC >> 2) |
95 | #define DP_PHY_RESET (0x0200 >> 2) |
96 | #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2) |
97 | #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2) |
98 | #define DP_TRANSMIT_PRBS7 (0x0230 >> 2) |
99 | #define DP_PHY_CLOCK_SELECT (0x0234 >> 2) |
100 | #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2) |
101 | #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2) |
102 | #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2) |
103 | #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2) |
104 | #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2) |
105 | #define DP_PHY_STATUS (0x0280 >> 2) |
106 | |
107 | #define DP_TX_AUDIO_CONTROL (0x0300 >> 2) |
108 | #define DP_TX_AUD_CTRL (1) |
109 | |
110 | #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2) |
111 | #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2) |
112 | #define DP_TX_M_AUD (0x0328 >> 2) |
113 | #define DP_TX_N_AUD (0x032C >> 2) |
114 | #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) |
115 | #define DP_INT_STATUS (0x03A0 >> 2) |
116 | #define DP_INT_MASK (0x03A4 >> 2) |
117 | #define DP_INT_EN (0x03A8 >> 2) |
118 | #define DP_INT_DS (0x03AC >> 2) |
119 | |
120 | /* |
121 | * Registers offset for Audio Video Buffer configuration. |
122 | */ |
123 | #define V_BLEND_OFFSET (0xA000) |
124 | #define V_BLEND_BG_CLR_0 (0x0000 >> 2) |
125 | #define V_BLEND_BG_CLR_1 (0x0004 >> 2) |
126 | #define V_BLEND_BG_CLR_2 (0x0008 >> 2) |
127 | #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2) |
128 | #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2) |
129 | #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2) |
130 | #define V_BLEND_LAYER1_CONTROL (0x001C >> 2) |
131 | |
132 | #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2) |
133 | #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2) |
134 | |
135 | #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2) |
136 | #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2) |
137 | #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2) |
138 | #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2) |
139 | #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2) |
140 | #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2) |
141 | |
142 | #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2) |
143 | |
144 | #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2) |
145 | #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2) |
146 | #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2) |
147 | #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2) |
148 | #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2) |
149 | #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2) |
150 | #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2) |
151 | |
152 | /* |
153 | * Registers offset for Audio Video Buffer configuration. |
154 | */ |
155 | #define AV_BUF_MANAGER_OFFSET (0xB000) |
156 | #define AV_BUF_FORMAT (0x0000 >> 2) |
157 | #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2) |
158 | #define AV_CHBUF0 (0x0010 >> 2) |
159 | #define AV_CHBUF1 (0x0014 >> 2) |
160 | #define AV_CHBUF2 (0x0018 >> 2) |
161 | #define AV_CHBUF3 (0x001C >> 2) |
162 | #define AV_CHBUF4 (0x0020 >> 2) |
163 | #define AV_CHBUF5 (0x0024 >> 2) |
164 | #define AV_BUF_STC_CONTROL (0x002C >> 2) |
165 | #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2) |
166 | #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2) |
167 | #define AV_BUF_STC_ADJ (0x0038 >> 2) |
168 | #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2) |
169 | #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2) |
170 | #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2) |
171 | #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2) |
172 | #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2) |
173 | #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2) |
174 | #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2) |
175 | #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2) |
176 | #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2) |
177 | #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2) |
178 | #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2) |
179 | #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2) |
180 | #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2) |
181 | #define AV_BUF_DITHER_CONFIG (0x007C >> 2) |
182 | #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2) |
183 | #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2) |
184 | #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2) |
185 | #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2) |
186 | #define AV_BUF_SRST_REG (0x0124 >> 2) |
187 | #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2) |
188 | #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2) |
189 | |
190 | #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2) |
191 | |
192 | #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2) |
193 | |
194 | #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2) |
195 | |
196 | #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2) |
197 | |
198 | #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2) |
199 | |
200 | #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2) |
201 | |
202 | #define AUDIO_MIXER_REGISTER_OFFSET (0xC000) |
203 | #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2) |
204 | #define AUDIO_MIXER_META_DATA (0x0004 >> 2) |
205 | #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2) |
206 | #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2) |
207 | #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2) |
208 | |
209 | #define DP_AUDIO_DMA_CHANNEL(n) (4 + n) |
210 | #define DP_GRAPHIC_DMA_CHANNEL (3) |
211 | #define DP_VIDEO_DMA_CHANNEL (0) |
212 | |
213 | enum DPGraphicFmt { |
214 | DP_GRAPHIC_RGBA8888 = 0 << 8, |
215 | DP_GRAPHIC_ABGR8888 = 1 << 8, |
216 | DP_GRAPHIC_RGB888 = 2 << 8, |
217 | DP_GRAPHIC_BGR888 = 3 << 8, |
218 | DP_GRAPHIC_RGBA5551 = 4 << 8, |
219 | DP_GRAPHIC_RGBA4444 = 5 << 8, |
220 | DP_GRAPHIC_RGB565 = 6 << 8, |
221 | DP_GRAPHIC_8BPP = 7 << 8, |
222 | DP_GRAPHIC_4BPP = 8 << 8, |
223 | DP_GRAPHIC_2BPP = 9 << 8, |
224 | DP_GRAPHIC_1BPP = 10 << 8, |
225 | DP_GRAPHIC_MASK = 0xF << 8 |
226 | }; |
227 | |
228 | enum DPVideoFmt { |
229 | DP_NL_VID_CB_Y0_CR_Y1 = 0, |
230 | DP_NL_VID_CR_Y0_CB_Y1 = 1, |
231 | DP_NL_VID_Y0_CR_Y1_CB = 2, |
232 | DP_NL_VID_Y0_CB_Y1_CR = 3, |
233 | DP_NL_VID_YV16 = 4, |
234 | DP_NL_VID_YV24 = 5, |
235 | DP_NL_VID_YV16CL = 6, |
236 | DP_NL_VID_MONO = 7, |
237 | DP_NL_VID_YV16CL2 = 8, |
238 | DP_NL_VID_YUV444 = 9, |
239 | DP_NL_VID_RGB888 = 10, |
240 | DP_NL_VID_RGBA8880 = 11, |
241 | DP_NL_VID_RGB888_10BPC = 12, |
242 | DP_NL_VID_YUV444_10BPC = 13, |
243 | DP_NL_VID_YV16CL2_10BPC = 14, |
244 | DP_NL_VID_YV16CL_10BPC = 15, |
245 | DP_NL_VID_YV16_10BPC = 16, |
246 | DP_NL_VID_YV24_10BPC = 17, |
247 | DP_NL_VID_Y_ONLY_10BPC = 18, |
248 | DP_NL_VID_YV16_420 = 19, |
249 | DP_NL_VID_YV16CL_420 = 20, |
250 | DP_NL_VID_YV16CL2_420 = 21, |
251 | DP_NL_VID_YV16_420_10BPC = 22, |
252 | DP_NL_VID_YV16CL_420_10BPC = 23, |
253 | DP_NL_VID_YV16CL2_420_10BPC = 24, |
254 | DP_NL_VID_FMT_MASK = 0x1F |
255 | }; |
256 | |
257 | typedef enum DPGraphicFmt DPGraphicFmt; |
258 | typedef enum DPVideoFmt DPVideoFmt; |
259 | |
260 | static const VMStateDescription vmstate_dp = { |
261 | .name = TYPE_XLNX_DP, |
262 | .version_id = 1, |
263 | .fields = (VMStateField[]){ |
264 | VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, |
265 | DP_CORE_REG_ARRAY_SIZE), |
266 | VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState, |
267 | DP_AVBUF_REG_ARRAY_SIZE), |
268 | VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState, |
269 | DP_VBLEND_REG_ARRAY_SIZE), |
270 | VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, |
271 | DP_AUDIO_REG_ARRAY_SIZE), |
272 | VMSTATE_END_OF_LIST() |
273 | } |
274 | }; |
275 | |
276 | static void xlnx_dp_update_irq(XlnxDPState *s); |
277 | |
278 | static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) |
279 | { |
280 | XlnxDPState *s = XLNX_DP(opaque); |
281 | |
282 | offset = offset >> 2; |
283 | return s->audio_registers[offset]; |
284 | } |
285 | |
286 | static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value, |
287 | unsigned size) |
288 | { |
289 | XlnxDPState *s = XLNX_DP(opaque); |
290 | |
291 | offset = offset >> 2; |
292 | |
293 | switch (offset) { |
294 | case AUDIO_MIXER_META_DATA: |
295 | s->audio_registers[offset] = value & 0x00000001; |
296 | break; |
297 | default: |
298 | s->audio_registers[offset] = value; |
299 | break; |
300 | } |
301 | } |
302 | |
303 | static const MemoryRegionOps audio_ops = { |
304 | .read = xlnx_dp_audio_read, |
305 | .write = xlnx_dp_audio_write, |
306 | .endianness = DEVICE_NATIVE_ENDIAN, |
307 | }; |
308 | |
309 | static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, |
310 | uint8_t channel) |
311 | { |
312 | switch (channel) { |
313 | case 0: |
314 | return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16); |
315 | case 1: |
316 | return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16, |
317 | 16); |
318 | default: |
319 | return 0; |
320 | } |
321 | } |
322 | |
323 | static inline void xlnx_dp_audio_activate(XlnxDPState *s) |
324 | { |
325 | bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] |
326 | & DP_TX_AUD_CTRL) != 0); |
327 | AUD_set_active_out(s->amixer_output_stream, activated); |
328 | xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0), |
329 | &s->audio_buffer_0); |
330 | xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1), |
331 | &s->audio_buffer_1); |
332 | } |
333 | |
334 | static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) |
335 | { |
336 | /* |
337 | * Audio packets are signed and have this shape: |
338 | * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | |
339 | * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 | |
340 | * |
341 | * Output audio is 16bits saturated. |
342 | */ |
343 | int i; |
344 | |
345 | if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) { |
346 | for (i = 0; i < s->audio_data_available[0] / 2; i++) { |
347 | s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) |
348 | * xlnx_dp_audio_get_volume(s, 0) / 8192; |
349 | } |
350 | s->byte_left = s->audio_data_available[0]; |
351 | } else { |
352 | memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); |
353 | } |
354 | |
355 | if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) { |
356 | if ((s->audio_data_available[0] == 0) |
357 | || (s->audio_data_available[1] == s->audio_data_available[0])) { |
358 | for (i = 0; i < s->audio_data_available[1] / 2; i++) { |
359 | s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) |
360 | * xlnx_dp_audio_get_volume(s, 1) / 8192; |
361 | } |
362 | s->byte_left = s->audio_data_available[1]; |
363 | } |
364 | } |
365 | |
366 | for (i = 0; i < s->byte_left / 2; i++) { |
367 | s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767)); |
368 | } |
369 | |
370 | s->data_ptr = 0; |
371 | } |
372 | |
373 | static void xlnx_dp_audio_callback(void *opaque, int avail) |
374 | { |
375 | /* |
376 | * Get some data from the DPDMA and compute these datas. |
377 | * Then wait for QEMU's audio subsystem to call this callback. |
378 | */ |
379 | XlnxDPState *s = XLNX_DP(opaque); |
380 | size_t written = 0; |
381 | |
382 | /* If there are already some data don't get more data. */ |
383 | if (s->byte_left == 0) { |
384 | s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4, |
385 | true); |
386 | s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5, |
387 | true); |
388 | xlnx_dp_audio_mix_buffer(s); |
389 | } |
390 | |
391 | /* Send the buffer through the audio. */ |
392 | if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) { |
393 | if (s->byte_left != 0) { |
394 | written = AUD_write(s->amixer_output_stream, |
395 | &s->out_buffer[s->data_ptr], s->byte_left); |
396 | } else { |
397 | /* |
398 | * There is nothing to play.. We don't have any data! Fill the |
399 | * buffer with zero's and send it. |
400 | */ |
401 | written = 0; |
402 | memset(s->out_buffer, 0, 1024); |
403 | AUD_write(s->amixer_output_stream, s->out_buffer, 1024); |
404 | } |
405 | } else { |
406 | written = AUD_write(s->amixer_output_stream, |
407 | &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE); |
408 | } |
409 | s->byte_left -= written; |
410 | s->data_ptr += written; |
411 | } |
412 | |
413 | /* |
414 | * AUX channel related function. |
415 | */ |
416 | static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s) |
417 | { |
418 | fifo8_reset(&s->rx_fifo); |
419 | } |
420 | |
421 | static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) |
422 | { |
423 | DPRINTF("Push %u data in rx_fifo\n" , (unsigned)len); |
424 | fifo8_push_all(&s->rx_fifo, buf, len); |
425 | } |
426 | |
427 | static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) |
428 | { |
429 | uint8_t ret; |
430 | |
431 | if (fifo8_is_empty(&s->rx_fifo)) { |
432 | qemu_log_mask(LOG_GUEST_ERROR, |
433 | "%s: Reading empty RX_FIFO\n" , |
434 | __func__); |
435 | /* |
436 | * The datasheet is not clear about the reset value, it seems |
437 | * to be unspecified. We choose to return '0'. |
438 | */ |
439 | ret = 0; |
440 | } else { |
441 | ret = fifo8_pop(&s->rx_fifo); |
442 | DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n" , ret); |
443 | } |
444 | return ret; |
445 | } |
446 | |
447 | static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s) |
448 | { |
449 | fifo8_reset(&s->tx_fifo); |
450 | } |
451 | |
452 | static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) |
453 | { |
454 | DPRINTF("Push %u data in tx_fifo\n" , (unsigned)len); |
455 | fifo8_push_all(&s->tx_fifo, buf, len); |
456 | } |
457 | |
458 | static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s) |
459 | { |
460 | uint8_t ret; |
461 | |
462 | if (fifo8_is_empty(&s->tx_fifo)) { |
463 | DPRINTF("tx_fifo underflow..\n" ); |
464 | abort(); |
465 | } |
466 | ret = fifo8_pop(&s->tx_fifo); |
467 | DPRINTF("pop 0x%2.2X from tx_fifo.\n" , ret); |
468 | return ret; |
469 | } |
470 | |
471 | static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s) |
472 | { |
473 | return s->core_registers[DP_AUX_ADDRESS]; |
474 | } |
475 | |
476 | /* |
477 | * Get command from the register. |
478 | */ |
479 | static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value) |
480 | { |
481 | bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0; |
482 | AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT; |
483 | uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1; |
484 | uint8_t buf[16]; |
485 | int i; |
486 | |
487 | /* |
488 | * When an address_only command is executed nothing happen to the fifo, so |
489 | * just make nbytes = 0. |
490 | */ |
491 | if (address_only) { |
492 | nbytes = 0; |
493 | } |
494 | |
495 | switch (cmd) { |
496 | case READ_AUX: |
497 | case READ_I2C: |
498 | case READ_I2C_MOT: |
499 | s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, |
500 | xlnx_dp_aux_get_address(s), |
501 | nbytes, buf); |
502 | s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; |
503 | |
504 | if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { |
505 | xlnx_dp_aux_push_rx_fifo(s, buf, nbytes); |
506 | } |
507 | break; |
508 | case WRITE_AUX: |
509 | case WRITE_I2C: |
510 | case WRITE_I2C_MOT: |
511 | for (i = 0; i < nbytes; i++) { |
512 | buf[i] = xlnx_dp_aux_pop_tx_fifo(s); |
513 | } |
514 | s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, |
515 | xlnx_dp_aux_get_address(s), |
516 | nbytes, buf); |
517 | xlnx_dp_aux_clear_tx_fifo(s); |
518 | break; |
519 | case WRITE_I2C_STATUS: |
520 | qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n" ); |
521 | break; |
522 | default: |
523 | abort(); |
524 | } |
525 | |
526 | s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; |
527 | } |
528 | |
529 | static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val, |
530 | Error **errp) |
531 | { |
532 | XlnxDPState *s = XLNX_DP(obj); |
533 | if (s->console) { |
534 | DisplaySurface *surface = qemu_console_surface(s->console); |
535 | XlnxDPDMAState *dma = XLNX_DPDMA(val); |
536 | xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL, |
537 | surface_data(surface)); |
538 | } |
539 | } |
540 | |
541 | static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s) |
542 | { |
543 | return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1; |
544 | } |
545 | |
546 | static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s) |
547 | { |
548 | /* |
549 | * If the alpha is totally opaque (255) we consider the alpha is disabled to |
550 | * reduce CPU consumption. |
551 | */ |
552 | return ((xlnx_dp_global_alpha_value(s) != 0xFF) && |
553 | ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0)); |
554 | } |
555 | |
556 | static void xlnx_dp_recreate_surface(XlnxDPState *s) |
557 | { |
558 | /* |
559 | * Two possibilities, if blending is enabled the console displays |
560 | * bout_plane, if not g_plane is displayed. |
561 | */ |
562 | uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; |
563 | uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; |
564 | DisplaySurface *current_console_surface = qemu_console_surface(s->console); |
565 | |
566 | if ((width != 0) && (height != 0)) { |
567 | /* |
568 | * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the |
569 | * surface we need to be careful and don't free the surface associated |
570 | * to the console or double free will happen. |
571 | */ |
572 | if (s->bout_plane.surface != current_console_surface) { |
573 | qemu_free_displaysurface(s->bout_plane.surface); |
574 | } |
575 | if (s->v_plane.surface != current_console_surface) { |
576 | qemu_free_displaysurface(s->v_plane.surface); |
577 | } |
578 | if (s->g_plane.surface != current_console_surface) { |
579 | qemu_free_displaysurface(s->g_plane.surface); |
580 | } |
581 | |
582 | s->g_plane.surface |
583 | = qemu_create_displaysurface_from(width, height, |
584 | s->g_plane.format, 0, NULL); |
585 | s->v_plane.surface |
586 | = qemu_create_displaysurface_from(width, height, |
587 | s->v_plane.format, 0, NULL); |
588 | if (xlnx_dp_global_alpha_enabled(s)) { |
589 | s->bout_plane.surface = |
590 | qemu_create_displaysurface_from(width, |
591 | height, |
592 | s->g_plane.format, |
593 | 0, NULL); |
594 | dpy_gfx_replace_surface(s->console, s->bout_plane.surface); |
595 | } else { |
596 | s->bout_plane.surface = NULL; |
597 | dpy_gfx_replace_surface(s->console, s->g_plane.surface); |
598 | } |
599 | |
600 | xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, |
601 | surface_data(s->g_plane.surface)); |
602 | xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL, |
603 | surface_data(s->v_plane.surface)); |
604 | } |
605 | } |
606 | |
607 | /* |
608 | * Change the graphic format of the surface. |
609 | */ |
610 | static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) |
611 | { |
612 | switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) { |
613 | case DP_GRAPHIC_RGBA8888: |
614 | s->g_plane.format = PIXMAN_r8g8b8a8; |
615 | break; |
616 | case DP_GRAPHIC_ABGR8888: |
617 | s->g_plane.format = PIXMAN_a8b8g8r8; |
618 | break; |
619 | case DP_GRAPHIC_RGB565: |
620 | s->g_plane.format = PIXMAN_r5g6b5; |
621 | break; |
622 | case DP_GRAPHIC_RGB888: |
623 | s->g_plane.format = PIXMAN_r8g8b8; |
624 | break; |
625 | case DP_GRAPHIC_BGR888: |
626 | s->g_plane.format = PIXMAN_b8g8r8; |
627 | break; |
628 | default: |
629 | DPRINTF("error: unsupported graphic format %u.\n" , |
630 | s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); |
631 | abort(); |
632 | } |
633 | |
634 | switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) { |
635 | case 0: |
636 | s->v_plane.format = PIXMAN_x8b8g8r8; |
637 | break; |
638 | case DP_NL_VID_Y0_CB_Y1_CR: |
639 | s->v_plane.format = PIXMAN_yuy2; |
640 | break; |
641 | case DP_NL_VID_RGBA8880: |
642 | s->v_plane.format = PIXMAN_x8b8g8r8; |
643 | break; |
644 | default: |
645 | DPRINTF("error: unsupported video format %u.\n" , |
646 | s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); |
647 | abort(); |
648 | } |
649 | |
650 | xlnx_dp_recreate_surface(s); |
651 | } |
652 | |
653 | static void xlnx_dp_update_irq(XlnxDPState *s) |
654 | { |
655 | uint32_t flags; |
656 | |
657 | flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; |
658 | DPRINTF("update IRQ value = %" PRIx32 "\n" , flags); |
659 | qemu_set_irq(s->irq, flags != 0); |
660 | } |
661 | |
662 | static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size) |
663 | { |
664 | XlnxDPState *s = XLNX_DP(opaque); |
665 | uint64_t ret = 0; |
666 | |
667 | offset = offset >> 2; |
668 | |
669 | switch (offset) { |
670 | case DP_TX_USER_FIFO_OVERFLOW: |
671 | /* This register is cleared after a read */ |
672 | ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; |
673 | s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; |
674 | break; |
675 | case DP_AUX_REPLY_DATA: |
676 | ret = xlnx_dp_aux_pop_rx_fifo(s); |
677 | break; |
678 | case DP_INTERRUPT_SIGNAL_STATE: |
679 | /* |
680 | * XXX: Not sure it is the right thing to do actually. |
681 | * The register is not written by the device driver so it's stuck |
682 | * to 0x04. |
683 | */ |
684 | ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; |
685 | s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; |
686 | break; |
687 | case DP_AUX_WRITE_FIFO: |
688 | case DP_TX_AUDIO_INFO_DATA(0): |
689 | case DP_TX_AUDIO_INFO_DATA(1): |
690 | case DP_TX_AUDIO_INFO_DATA(2): |
691 | case DP_TX_AUDIO_INFO_DATA(3): |
692 | case DP_TX_AUDIO_INFO_DATA(4): |
693 | case DP_TX_AUDIO_INFO_DATA(5): |
694 | case DP_TX_AUDIO_INFO_DATA(6): |
695 | case DP_TX_AUDIO_INFO_DATA(7): |
696 | case DP_TX_AUDIO_EXT_DATA(0): |
697 | case DP_TX_AUDIO_EXT_DATA(1): |
698 | case DP_TX_AUDIO_EXT_DATA(2): |
699 | case DP_TX_AUDIO_EXT_DATA(3): |
700 | case DP_TX_AUDIO_EXT_DATA(4): |
701 | case DP_TX_AUDIO_EXT_DATA(5): |
702 | case DP_TX_AUDIO_EXT_DATA(6): |
703 | case DP_TX_AUDIO_EXT_DATA(7): |
704 | case DP_TX_AUDIO_EXT_DATA(8): |
705 | /* write only registers */ |
706 | ret = 0; |
707 | break; |
708 | default: |
709 | assert(offset <= (0x3AC >> 2)); |
710 | ret = s->core_registers[offset]; |
711 | break; |
712 | } |
713 | |
714 | DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n" , offset << 2, ret); |
715 | return ret; |
716 | } |
717 | |
718 | static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, |
719 | unsigned size) |
720 | { |
721 | XlnxDPState *s = XLNX_DP(opaque); |
722 | |
723 | DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n" , offset, value); |
724 | |
725 | offset = offset >> 2; |
726 | |
727 | switch (offset) { |
728 | /* |
729 | * Only special write case are handled. |
730 | */ |
731 | case DP_LINK_BW_SET: |
732 | s->core_registers[offset] = value & 0x000000FF; |
733 | break; |
734 | case DP_LANE_COUNT_SET: |
735 | case DP_MAIN_STREAM_MISC0: |
736 | s->core_registers[offset] = value & 0x0000000F; |
737 | break; |
738 | case DP_TRAINING_PATTERN_SET: |
739 | case DP_LINK_QUAL_PATTERN_SET: |
740 | case DP_MAIN_STREAM_POLARITY: |
741 | case DP_PHY_VOLTAGE_DIFF_LANE_0: |
742 | case DP_PHY_VOLTAGE_DIFF_LANE_1: |
743 | s->core_registers[offset] = value & 0x00000003; |
744 | break; |
745 | case DP_ENHANCED_FRAME_EN: |
746 | case DP_SCRAMBLING_DISABLE: |
747 | case DP_DOWNSPREAD_CTRL: |
748 | case DP_MAIN_STREAM_ENABLE: |
749 | case DP_TRANSMIT_PRBS7: |
750 | s->core_registers[offset] = value & 0x00000001; |
751 | break; |
752 | case DP_PHY_CLOCK_SELECT: |
753 | s->core_registers[offset] = value & 0x00000007; |
754 | break; |
755 | case DP_SOFTWARE_RESET: |
756 | /* |
757 | * No need to update this bit as it's read '0'. |
758 | */ |
759 | /* |
760 | * TODO: reset IP. |
761 | */ |
762 | break; |
763 | case DP_TRANSMITTER_ENABLE: |
764 | s->core_registers[offset] = value & 0x01; |
765 | break; |
766 | case DP_FORCE_SCRAMBLER_RESET: |
767 | /* |
768 | * No need to update this bit as it's read '0'. |
769 | */ |
770 | /* |
771 | * TODO: force a scrambler reset?? |
772 | */ |
773 | break; |
774 | case DP_AUX_COMMAND_REGISTER: |
775 | s->core_registers[offset] = value & 0x00001F0F; |
776 | xlnx_dp_aux_set_command(s, s->core_registers[offset]); |
777 | break; |
778 | case DP_MAIN_STREAM_HTOTAL: |
779 | case DP_MAIN_STREAM_VTOTAL: |
780 | case DP_MAIN_STREAM_HSTART: |
781 | case DP_MAIN_STREAM_VSTART: |
782 | s->core_registers[offset] = value & 0x0000FFFF; |
783 | break; |
784 | case DP_MAIN_STREAM_HRES: |
785 | case DP_MAIN_STREAM_VRES: |
786 | s->core_registers[offset] = value & 0x0000FFFF; |
787 | xlnx_dp_recreate_surface(s); |
788 | break; |
789 | case DP_MAIN_STREAM_HSWIDTH: |
790 | case DP_MAIN_STREAM_VSWIDTH: |
791 | s->core_registers[offset] = value & 0x00007FFF; |
792 | break; |
793 | case DP_MAIN_STREAM_MISC1: |
794 | s->core_registers[offset] = value & 0x00000086; |
795 | break; |
796 | case DP_MAIN_STREAM_M_VID: |
797 | case DP_MAIN_STREAM_N_VID: |
798 | s->core_registers[offset] = value & 0x00FFFFFF; |
799 | break; |
800 | case DP_MSA_TRANSFER_UNIT_SIZE: |
801 | case DP_MIN_BYTES_PER_TU: |
802 | case DP_INIT_WAIT: |
803 | s->core_registers[offset] = value & 0x00000007; |
804 | break; |
805 | case DP_USER_DATA_COUNT_PER_LANE: |
806 | s->core_registers[offset] = value & 0x0003FFFF; |
807 | break; |
808 | case DP_FRAC_BYTES_PER_TU: |
809 | s->core_registers[offset] = value & 0x000003FF; |
810 | break; |
811 | case DP_PHY_RESET: |
812 | s->core_registers[offset] = value & 0x00010003; |
813 | /* |
814 | * TODO: Reset something? |
815 | */ |
816 | break; |
817 | case DP_TX_PHY_POWER_DOWN: |
818 | s->core_registers[offset] = value & 0x0000000F; |
819 | /* |
820 | * TODO: Power down things? |
821 | */ |
822 | break; |
823 | case DP_AUX_WRITE_FIFO: { |
824 | uint8_t c = value; |
825 | xlnx_dp_aux_push_tx_fifo(s, &c, 1); |
826 | break; |
827 | } |
828 | case DP_AUX_CLOCK_DIVIDER: |
829 | break; |
830 | case DP_AUX_REPLY_COUNT: |
831 | /* |
832 | * Writing to this register clear the counter. |
833 | */ |
834 | s->core_registers[offset] = 0x00000000; |
835 | break; |
836 | case DP_AUX_ADDRESS: |
837 | s->core_registers[offset] = value & 0x000FFFFF; |
838 | break; |
839 | case DP_VERSION_REGISTER: |
840 | case DP_CORE_ID: |
841 | case DP_TX_USER_FIFO_OVERFLOW: |
842 | case DP_AUX_REPLY_DATA: |
843 | case DP_AUX_REPLY_CODE: |
844 | case DP_REPLY_DATA_COUNT: |
845 | case DP_REPLY_STATUS: |
846 | case DP_HPD_DURATION: |
847 | /* |
848 | * Write to read only location.. |
849 | */ |
850 | break; |
851 | case DP_TX_AUDIO_CONTROL: |
852 | s->core_registers[offset] = value & 0x00000001; |
853 | xlnx_dp_audio_activate(s); |
854 | break; |
855 | case DP_TX_AUDIO_CHANNELS: |
856 | s->core_registers[offset] = value & 0x00000007; |
857 | xlnx_dp_audio_activate(s); |
858 | break; |
859 | case DP_INT_STATUS: |
860 | s->core_registers[DP_INT_STATUS] &= ~value; |
861 | xlnx_dp_update_irq(s); |
862 | break; |
863 | case DP_INT_EN: |
864 | s->core_registers[DP_INT_MASK] &= ~value; |
865 | xlnx_dp_update_irq(s); |
866 | break; |
867 | case DP_INT_DS: |
868 | s->core_registers[DP_INT_MASK] |= ~value; |
869 | xlnx_dp_update_irq(s); |
870 | break; |
871 | default: |
872 | assert(offset <= (0x504C >> 2)); |
873 | s->core_registers[offset] = value; |
874 | break; |
875 | } |
876 | } |
877 | |
878 | static const MemoryRegionOps dp_ops = { |
879 | .read = xlnx_dp_read, |
880 | .write = xlnx_dp_write, |
881 | .endianness = DEVICE_NATIVE_ENDIAN, |
882 | .valid = { |
883 | .min_access_size = 4, |
884 | .max_access_size = 4, |
885 | }, |
886 | .impl = { |
887 | .min_access_size = 4, |
888 | .max_access_size = 4, |
889 | }, |
890 | }; |
891 | |
892 | /* |
893 | * This is to handle Read/Write to the Video Blender. |
894 | */ |
895 | static void xlnx_dp_vblend_write(void *opaque, hwaddr offset, |
896 | uint64_t value, unsigned size) |
897 | { |
898 | XlnxDPState *s = XLNX_DP(opaque); |
899 | bool alpha_was_enabled; |
900 | |
901 | DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n" , offset, |
902 | (uint32_t)value); |
903 | offset = offset >> 2; |
904 | |
905 | switch (offset) { |
906 | case V_BLEND_BG_CLR_0: |
907 | case V_BLEND_BG_CLR_1: |
908 | case V_BLEND_BG_CLR_2: |
909 | s->vblend_registers[offset] = value & 0x00000FFF; |
910 | break; |
911 | case V_BLEND_SET_GLOBAL_ALPHA_REG: |
912 | /* |
913 | * A write to this register can enable or disable blending. Thus we need |
914 | * to recreate the surfaces. |
915 | */ |
916 | alpha_was_enabled = xlnx_dp_global_alpha_enabled(s); |
917 | s->vblend_registers[offset] = value & 0x000001FF; |
918 | if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) { |
919 | xlnx_dp_recreate_surface(s); |
920 | } |
921 | break; |
922 | case V_BLEND_OUTPUT_VID_FORMAT: |
923 | s->vblend_registers[offset] = value & 0x00000017; |
924 | break; |
925 | case V_BLEND_LAYER0_CONTROL: |
926 | case V_BLEND_LAYER1_CONTROL: |
927 | s->vblend_registers[offset] = value & 0x00000103; |
928 | break; |
929 | case V_BLEND_RGB2YCBCR_COEFF(0): |
930 | case V_BLEND_RGB2YCBCR_COEFF(1): |
931 | case V_BLEND_RGB2YCBCR_COEFF(2): |
932 | case V_BLEND_RGB2YCBCR_COEFF(3): |
933 | case V_BLEND_RGB2YCBCR_COEFF(4): |
934 | case V_BLEND_RGB2YCBCR_COEFF(5): |
935 | case V_BLEND_RGB2YCBCR_COEFF(6): |
936 | case V_BLEND_RGB2YCBCR_COEFF(7): |
937 | case V_BLEND_RGB2YCBCR_COEFF(8): |
938 | case V_BLEND_IN1CSC_COEFF(0): |
939 | case V_BLEND_IN1CSC_COEFF(1): |
940 | case V_BLEND_IN1CSC_COEFF(2): |
941 | case V_BLEND_IN1CSC_COEFF(3): |
942 | case V_BLEND_IN1CSC_COEFF(4): |
943 | case V_BLEND_IN1CSC_COEFF(5): |
944 | case V_BLEND_IN1CSC_COEFF(6): |
945 | case V_BLEND_IN1CSC_COEFF(7): |
946 | case V_BLEND_IN1CSC_COEFF(8): |
947 | case V_BLEND_IN2CSC_COEFF(0): |
948 | case V_BLEND_IN2CSC_COEFF(1): |
949 | case V_BLEND_IN2CSC_COEFF(2): |
950 | case V_BLEND_IN2CSC_COEFF(3): |
951 | case V_BLEND_IN2CSC_COEFF(4): |
952 | case V_BLEND_IN2CSC_COEFF(5): |
953 | case V_BLEND_IN2CSC_COEFF(6): |
954 | case V_BLEND_IN2CSC_COEFF(7): |
955 | case V_BLEND_IN2CSC_COEFF(8): |
956 | s->vblend_registers[offset] = value & 0x0000FFFF; |
957 | break; |
958 | case V_BLEND_LUMA_IN1CSC_OFFSET: |
959 | case V_BLEND_CR_IN1CSC_OFFSET: |
960 | case V_BLEND_CB_IN1CSC_OFFSET: |
961 | case V_BLEND_LUMA_IN2CSC_OFFSET: |
962 | case V_BLEND_CR_IN2CSC_OFFSET: |
963 | case V_BLEND_CB_IN2CSC_OFFSET: |
964 | case V_BLEND_LUMA_OUTCSC_OFFSET: |
965 | case V_BLEND_CR_OUTCSC_OFFSET: |
966 | case V_BLEND_CB_OUTCSC_OFFSET: |
967 | s->vblend_registers[offset] = value & 0x3FFF7FFF; |
968 | break; |
969 | case V_BLEND_CHROMA_KEY_ENABLE: |
970 | s->vblend_registers[offset] = value & 0x00000003; |
971 | break; |
972 | case V_BLEND_CHROMA_KEY_COMP1: |
973 | case V_BLEND_CHROMA_KEY_COMP2: |
974 | case V_BLEND_CHROMA_KEY_COMP3: |
975 | s->vblend_registers[offset] = value & 0x0FFF0FFF; |
976 | break; |
977 | default: |
978 | s->vblend_registers[offset] = value; |
979 | break; |
980 | } |
981 | } |
982 | |
983 | static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset, |
984 | unsigned size) |
985 | { |
986 | XlnxDPState *s = XLNX_DP(opaque); |
987 | |
988 | DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n" , offset, |
989 | s->vblend_registers[offset >> 2]); |
990 | return s->vblend_registers[offset >> 2]; |
991 | } |
992 | |
993 | static const MemoryRegionOps vblend_ops = { |
994 | .read = xlnx_dp_vblend_read, |
995 | .write = xlnx_dp_vblend_write, |
996 | .endianness = DEVICE_NATIVE_ENDIAN, |
997 | .valid = { |
998 | .min_access_size = 4, |
999 | .max_access_size = 4, |
1000 | }, |
1001 | .impl = { |
1002 | .min_access_size = 4, |
1003 | .max_access_size = 4, |
1004 | }, |
1005 | }; |
1006 | |
1007 | /* |
1008 | * This is to handle Read/Write to the Audio Video buffer manager. |
1009 | */ |
1010 | static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value, |
1011 | unsigned size) |
1012 | { |
1013 | XlnxDPState *s = XLNX_DP(opaque); |
1014 | |
1015 | DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n" , offset, |
1016 | (uint32_t)value); |
1017 | offset = offset >> 2; |
1018 | |
1019 | switch (offset) { |
1020 | case AV_BUF_FORMAT: |
1021 | s->avbufm_registers[offset] = value & 0x00000FFF; |
1022 | xlnx_dp_change_graphic_fmt(s); |
1023 | break; |
1024 | case AV_CHBUF0: |
1025 | case AV_CHBUF1: |
1026 | case AV_CHBUF2: |
1027 | case AV_CHBUF3: |
1028 | case AV_CHBUF4: |
1029 | case AV_CHBUF5: |
1030 | s->avbufm_registers[offset] = value & 0x0000007F; |
1031 | break; |
1032 | case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: |
1033 | s->avbufm_registers[offset] = value & 0x0000007F; |
1034 | break; |
1035 | case AV_BUF_DITHER_CONFIG: |
1036 | s->avbufm_registers[offset] = value & 0x000007FF; |
1037 | break; |
1038 | case AV_BUF_DITHER_CONFIG_MAX: |
1039 | case AV_BUF_DITHER_CONFIG_MIN: |
1040 | s->avbufm_registers[offset] = value & 0x00000FFF; |
1041 | break; |
1042 | case AV_BUF_PATTERN_GEN_SELECT: |
1043 | s->avbufm_registers[offset] = value & 0xFFFFFF03; |
1044 | break; |
1045 | case AV_BUF_AUD_VID_CLK_SOURCE: |
1046 | s->avbufm_registers[offset] = value & 0x00000007; |
1047 | break; |
1048 | case AV_BUF_SRST_REG: |
1049 | s->avbufm_registers[offset] = value & 0x00000002; |
1050 | break; |
1051 | case AV_BUF_AUDIO_CH_CONFIG: |
1052 | s->avbufm_registers[offset] = value & 0x00000003; |
1053 | break; |
1054 | case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0): |
1055 | case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1): |
1056 | case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2): |
1057 | case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0): |
1058 | case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1): |
1059 | case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2): |
1060 | s->avbufm_registers[offset] = value & 0x0000FFFF; |
1061 | break; |
1062 | case AV_BUF_LIVE_VIDEO_COMP_SF(0): |
1063 | case AV_BUF_LIVE_VIDEO_COMP_SF(1): |
1064 | case AV_BUF_LIVE_VIDEO_COMP_SF(2): |
1065 | case AV_BUF_LIVE_VID_CONFIG: |
1066 | case AV_BUF_LIVE_GFX_COMP_SF(0): |
1067 | case AV_BUF_LIVE_GFX_COMP_SF(1): |
1068 | case AV_BUF_LIVE_GFX_COMP_SF(2): |
1069 | case AV_BUF_LIVE_GFX_CONFIG: |
1070 | case AV_BUF_NON_LIVE_LATENCY: |
1071 | case AV_BUF_STC_CONTROL: |
1072 | case AV_BUF_STC_INIT_VALUE0: |
1073 | case AV_BUF_STC_INIT_VALUE1: |
1074 | case AV_BUF_STC_ADJ: |
1075 | case AV_BUF_STC_VIDEO_VSYNC_TS_REG0: |
1076 | case AV_BUF_STC_VIDEO_VSYNC_TS_REG1: |
1077 | case AV_BUF_STC_EXT_VSYNC_TS_REG0: |
1078 | case AV_BUF_STC_EXT_VSYNC_TS_REG1: |
1079 | case AV_BUF_STC_CUSTOM_EVENT_TS_REG0: |
1080 | case AV_BUF_STC_CUSTOM_EVENT_TS_REG1: |
1081 | case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: |
1082 | case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: |
1083 | case AV_BUF_STC_SNAPSHOT0: |
1084 | case AV_BUF_STC_SNAPSHOT1: |
1085 | case AV_BUF_HCOUNT_VCOUNT_INT0: |
1086 | case AV_BUF_HCOUNT_VCOUNT_INT1: |
1087 | qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04" |
1088 | PRIx64 "\n" , |
1089 | offset << 2); |
1090 | break; |
1091 | default: |
1092 | s->avbufm_registers[offset] = value; |
1093 | break; |
1094 | } |
1095 | } |
1096 | |
1097 | static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset, |
1098 | unsigned size) |
1099 | { |
1100 | XlnxDPState *s = XLNX_DP(opaque); |
1101 | |
1102 | offset = offset >> 2; |
1103 | return s->avbufm_registers[offset]; |
1104 | } |
1105 | |
1106 | static const MemoryRegionOps avbufm_ops = { |
1107 | .read = xlnx_dp_avbufm_read, |
1108 | .write = xlnx_dp_avbufm_write, |
1109 | .endianness = DEVICE_NATIVE_ENDIAN, |
1110 | .valid = { |
1111 | .min_access_size = 4, |
1112 | .max_access_size = 4, |
1113 | }, |
1114 | .impl = { |
1115 | .min_access_size = 4, |
1116 | .max_access_size = 4, |
1117 | }, |
1118 | }; |
1119 | |
1120 | /* |
1121 | * This is a global alpha blending using pixman. |
1122 | * Both graphic and video planes are multiplied with the global alpha |
1123 | * coefficient and added. |
1124 | */ |
1125 | static inline void xlnx_dp_blend_surface(XlnxDPState *s) |
1126 | { |
1127 | pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1), |
1128 | pixman_double_to_fixed(1), |
1129 | pixman_double_to_fixed(1.0) }; |
1130 | pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1), |
1131 | pixman_double_to_fixed(1), |
1132 | pixman_double_to_fixed(1.0) }; |
1133 | |
1134 | if ((surface_width(s->g_plane.surface) |
1135 | != surface_width(s->v_plane.surface)) || |
1136 | (surface_height(s->g_plane.surface) |
1137 | != surface_height(s->v_plane.surface))) { |
1138 | return; |
1139 | } |
1140 | |
1141 | alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s)) |
1142 | / 256.0); |
1143 | alpha2[2] = pixman_double_to_fixed((255.0 |
1144 | - (double)xlnx_dp_global_alpha_value(s)) |
1145 | / 256.0); |
1146 | |
1147 | pixman_image_set_filter(s->g_plane.surface->image, |
1148 | PIXMAN_FILTER_CONVOLUTION, alpha1, 3); |
1149 | pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0, |
1150 | s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, |
1151 | surface_width(s->g_plane.surface), |
1152 | surface_height(s->g_plane.surface)); |
1153 | pixman_image_set_filter(s->v_plane.surface->image, |
1154 | PIXMAN_FILTER_CONVOLUTION, alpha2, 3); |
1155 | pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0, |
1156 | s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, |
1157 | surface_width(s->g_plane.surface), |
1158 | surface_height(s->g_plane.surface)); |
1159 | } |
1160 | |
1161 | static void xlnx_dp_update_display(void *opaque) |
1162 | { |
1163 | XlnxDPState *s = XLNX_DP(opaque); |
1164 | |
1165 | if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { |
1166 | return; |
1167 | } |
1168 | |
1169 | s->core_registers[DP_INT_STATUS] |= (1 << 13); |
1170 | xlnx_dp_update_irq(s); |
1171 | |
1172 | xlnx_dpdma_trigger_vsync_irq(s->dpdma); |
1173 | |
1174 | /* |
1175 | * Trigger the DMA channel. |
1176 | */ |
1177 | if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) { |
1178 | /* |
1179 | * An error occurred don't do anything with the data.. |
1180 | * Trigger an underflow interrupt. |
1181 | */ |
1182 | s->core_registers[DP_INT_STATUS] |= (1 << 21); |
1183 | xlnx_dp_update_irq(s); |
1184 | return; |
1185 | } |
1186 | |
1187 | if (xlnx_dp_global_alpha_enabled(s)) { |
1188 | if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { |
1189 | s->core_registers[DP_INT_STATUS] |= (1 << 21); |
1190 | xlnx_dp_update_irq(s); |
1191 | return; |
1192 | } |
1193 | xlnx_dp_blend_surface(s); |
1194 | } |
1195 | |
1196 | /* |
1197 | * XXX: We might want to update only what changed. |
1198 | */ |
1199 | dpy_gfx_update_full(s->console); |
1200 | } |
1201 | |
1202 | static const GraphicHwOps xlnx_dp_gfx_ops = { |
1203 | .gfx_update = xlnx_dp_update_display, |
1204 | }; |
1205 | |
1206 | static void xlnx_dp_init(Object *obj) |
1207 | { |
1208 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
1209 | XlnxDPState *s = XLNX_DP(obj); |
1210 | |
1211 | memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050); |
1212 | |
1213 | memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP |
1214 | ".core" , 0x3AF); |
1215 | memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem); |
1216 | |
1217 | memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP |
1218 | ".v_blend" , 0x1DF); |
1219 | memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem); |
1220 | |
1221 | memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP |
1222 | ".av_buffer_manager" , 0x238); |
1223 | memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem); |
1224 | |
1225 | memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP |
1226 | ".audio" , sizeof(s->audio_registers)); |
1227 | memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem); |
1228 | |
1229 | sysbus_init_mmio(sbd, &s->container); |
1230 | sysbus_init_irq(sbd, &s->irq); |
1231 | |
1232 | object_property_add_link(obj, "dpdma" , TYPE_XLNX_DPDMA, |
1233 | (Object **) &s->dpdma, |
1234 | xlnx_dp_set_dpdma, |
1235 | OBJ_PROP_LINK_STRONG, |
1236 | &error_abort); |
1237 | |
1238 | /* |
1239 | * Initialize AUX Bus. |
1240 | */ |
1241 | s->aux_bus = aux_init_bus(DEVICE(obj), "aux" ); |
1242 | |
1243 | /* |
1244 | * Initialize DPCD and EDID.. |
1245 | */ |
1246 | s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd" )); |
1247 | object_property_add_child(OBJECT(s), "dpcd" , OBJECT(s->dpcd), NULL); |
1248 | |
1249 | s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc" )); |
1250 | i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50); |
1251 | object_property_add_child(OBJECT(s), "edid" , OBJECT(s->edid), NULL); |
1252 | |
1253 | fifo8_create(&s->rx_fifo, 16); |
1254 | fifo8_create(&s->tx_fifo, 16); |
1255 | } |
1256 | |
1257 | static void xlnx_dp_realize(DeviceState *dev, Error **errp) |
1258 | { |
1259 | XlnxDPState *s = XLNX_DP(dev); |
1260 | DisplaySurface *surface; |
1261 | struct audsettings as; |
1262 | |
1263 | qdev_init_nofail(DEVICE(s->dpcd)); |
1264 | aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000); |
1265 | |
1266 | s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s); |
1267 | surface = qemu_console_surface(s->console); |
1268 | xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, |
1269 | surface_data(surface)); |
1270 | |
1271 | as.freq = 44100; |
1272 | as.nchannels = 2; |
1273 | as.fmt = AUDIO_FORMAT_S16; |
1274 | as.endianness = 0; |
1275 | |
1276 | AUD_register_card("xlnx_dp.audio" , &s->aud_card); |
1277 | |
1278 | s->amixer_output_stream = AUD_open_out(&s->aud_card, |
1279 | s->amixer_output_stream, |
1280 | "xlnx_dp.audio.out" , |
1281 | s, |
1282 | xlnx_dp_audio_callback, |
1283 | &as); |
1284 | AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); |
1285 | xlnx_dp_audio_activate(s); |
1286 | } |
1287 | |
1288 | static void xlnx_dp_reset(DeviceState *dev) |
1289 | { |
1290 | XlnxDPState *s = XLNX_DP(dev); |
1291 | |
1292 | memset(s->core_registers, 0, sizeof(s->core_registers)); |
1293 | s->core_registers[DP_VERSION_REGISTER] = 0x04010000; |
1294 | s->core_registers[DP_CORE_ID] = 0x01020000; |
1295 | s->core_registers[DP_REPLY_STATUS] = 0x00000010; |
1296 | s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; |
1297 | s->core_registers[DP_INIT_WAIT] = 0x00000020; |
1298 | s->core_registers[DP_PHY_RESET] = 0x00010003; |
1299 | s->core_registers[DP_INT_MASK] = 0xFFFFF03F; |
1300 | s->core_registers[DP_PHY_STATUS] = 0x00000043; |
1301 | s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; |
1302 | |
1303 | s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000; |
1304 | s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000; |
1305 | s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000; |
1306 | s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000; |
1307 | s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000; |
1308 | s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000; |
1309 | s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000; |
1310 | s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000; |
1311 | s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000; |
1312 | |
1313 | s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180; |
1314 | s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008; |
1315 | s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF; |
1316 | s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101; |
1317 | s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101; |
1318 | s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101; |
1319 | s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101; |
1320 | s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101; |
1321 | s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101; |
1322 | s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101; |
1323 | s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101; |
1324 | s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101; |
1325 | s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101; |
1326 | s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101; |
1327 | s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101; |
1328 | |
1329 | memset(s->audio_registers, 0, sizeof(s->audio_registers)); |
1330 | s->byte_left = 0; |
1331 | |
1332 | xlnx_dp_aux_clear_rx_fifo(s); |
1333 | xlnx_dp_change_graphic_fmt(s); |
1334 | xlnx_dp_update_irq(s); |
1335 | } |
1336 | |
1337 | static void xlnx_dp_class_init(ObjectClass *oc, void *data) |
1338 | { |
1339 | DeviceClass *dc = DEVICE_CLASS(oc); |
1340 | |
1341 | dc->realize = xlnx_dp_realize; |
1342 | dc->vmsd = &vmstate_dp; |
1343 | dc->reset = xlnx_dp_reset; |
1344 | } |
1345 | |
1346 | static const TypeInfo xlnx_dp_info = { |
1347 | .name = TYPE_XLNX_DP, |
1348 | .parent = TYPE_SYS_BUS_DEVICE, |
1349 | .instance_size = sizeof(XlnxDPState), |
1350 | .instance_init = xlnx_dp_init, |
1351 | .class_init = xlnx_dp_class_init, |
1352 | }; |
1353 | |
1354 | static void xlnx_dp_register_types(void) |
1355 | { |
1356 | type_register_static(&xlnx_dp_info); |
1357 | } |
1358 | |
1359 | type_init(xlnx_dp_register_types) |
1360 | |