1/*
2 * ARM PrimeCell PL330 DMA Controller
3 *
4 * Copyright (c) 2009 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
7 * Copyright (c) 2012 PetaLogix Pty Ltd.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 or later.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "qemu/osdep.h"
18#include "qemu-common.h"
19#include "hw/irq.h"
20#include "hw/qdev-properties.h"
21#include "hw/sysbus.h"
22#include "migration/vmstate.h"
23#include "qapi/error.h"
24#include "qemu/timer.h"
25#include "sysemu/dma.h"
26#include "qemu/log.h"
27#include "qemu/module.h"
28
29#ifndef PL330_ERR_DEBUG
30#define PL330_ERR_DEBUG 0
31#endif
32
33#define DB_PRINT_L(lvl, fmt, args...) do {\
34 if (PL330_ERR_DEBUG >= lvl) {\
35 fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\
36 } \
37} while (0)
38
39#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
40
41#define PL330_PERIPH_NUM 32
42#define PL330_MAX_BURST_LEN 128
43#define PL330_INSN_MAXSIZE 6
44
45#define PL330_FIFO_OK 0
46#define PL330_FIFO_STALL 1
47#define PL330_FIFO_ERR (-1)
48
49#define PL330_FAULT_UNDEF_INSTR (1 << 0)
50#define PL330_FAULT_OPERAND_INVALID (1 << 1)
51#define PL330_FAULT_DMAGO_ERR (1 << 4)
52#define PL330_FAULT_EVENT_ERR (1 << 5)
53#define PL330_FAULT_CH_PERIPH_ERR (1 << 6)
54#define PL330_FAULT_CH_RDWR_ERR (1 << 7)
55#define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12)
56#define PL330_FAULT_FIFOEMPTY_ERR (1 << 13)
57#define PL330_FAULT_INSTR_FETCH_ERR (1 << 16)
58#define PL330_FAULT_DATA_WRITE_ERR (1 << 17)
59#define PL330_FAULT_DATA_READ_ERR (1 << 18)
60#define PL330_FAULT_DBG_INSTR (1 << 30)
61#define PL330_FAULT_LOCKUP_ERR (1 << 31)
62
63#define PL330_UNTAGGED 0xff
64
65#define PL330_SINGLE 0x0
66#define PL330_BURST 0x1
67
68#define PL330_WATCHDOG_LIMIT 1024
69
70/* IOMEM mapped registers */
71#define PL330_REG_DSR 0x000
72#define PL330_REG_DPC 0x004
73#define PL330_REG_INTEN 0x020
74#define PL330_REG_INT_EVENT_RIS 0x024
75#define PL330_REG_INTMIS 0x028
76#define PL330_REG_INTCLR 0x02C
77#define PL330_REG_FSRD 0x030
78#define PL330_REG_FSRC 0x034
79#define PL330_REG_FTRD 0x038
80#define PL330_REG_FTR_BASE 0x040
81#define PL330_REG_CSR_BASE 0x100
82#define PL330_REG_CPC_BASE 0x104
83#define PL330_REG_CHANCTRL 0x400
84#define PL330_REG_DBGSTATUS 0xD00
85#define PL330_REG_DBGCMD 0xD04
86#define PL330_REG_DBGINST0 0xD08
87#define PL330_REG_DBGINST1 0xD0C
88#define PL330_REG_CR0_BASE 0xE00
89#define PL330_REG_PERIPH_ID 0xFE0
90
91#define PL330_IOMEM_SIZE 0x1000
92
93#define CFG_BOOT_ADDR 2
94#define CFG_INS 3
95#define CFG_PNS 4
96#define CFG_CRD 5
97
98static const uint32_t pl330_id[] = {
99 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1
100};
101
102/* DMA channel states as they are described in PL330 Technical Reference Manual
103 * Most of them will not be used in emulation.
104 */
105typedef enum {
106 pl330_chan_stopped = 0,
107 pl330_chan_executing = 1,
108 pl330_chan_cache_miss = 2,
109 pl330_chan_updating_pc = 3,
110 pl330_chan_waiting_event = 4,
111 pl330_chan_at_barrier = 5,
112 pl330_chan_queue_busy = 6,
113 pl330_chan_waiting_periph = 7,
114 pl330_chan_killing = 8,
115 pl330_chan_completing = 9,
116 pl330_chan_fault_completing = 14,
117 pl330_chan_fault = 15,
118} PL330ChanState;
119
120typedef struct PL330State PL330State;
121
122typedef struct PL330Chan {
123 uint32_t src;
124 uint32_t dst;
125 uint32_t pc;
126 uint32_t control;
127 uint32_t status;
128 uint32_t lc[2];
129 uint32_t fault_type;
130 uint32_t watchdog_timer;
131
132 bool ns;
133 uint8_t request_flag;
134 uint8_t wakeup;
135 uint8_t wfp_sbp;
136
137 uint8_t state;
138 uint8_t stall;
139
140 bool is_manager;
141 PL330State *parent;
142 uint8_t tag;
143} PL330Chan;
144
145static const VMStateDescription vmstate_pl330_chan = {
146 .name = "pl330_chan",
147 .version_id = 1,
148 .minimum_version_id = 1,
149 .fields = (VMStateField[]) {
150 VMSTATE_UINT32(src, PL330Chan),
151 VMSTATE_UINT32(dst, PL330Chan),
152 VMSTATE_UINT32(pc, PL330Chan),
153 VMSTATE_UINT32(control, PL330Chan),
154 VMSTATE_UINT32(status, PL330Chan),
155 VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2),
156 VMSTATE_UINT32(fault_type, PL330Chan),
157 VMSTATE_UINT32(watchdog_timer, PL330Chan),
158 VMSTATE_BOOL(ns, PL330Chan),
159 VMSTATE_UINT8(request_flag, PL330Chan),
160 VMSTATE_UINT8(wakeup, PL330Chan),
161 VMSTATE_UINT8(wfp_sbp, PL330Chan),
162 VMSTATE_UINT8(state, PL330Chan),
163 VMSTATE_UINT8(stall, PL330Chan),
164 VMSTATE_END_OF_LIST()
165 }
166};
167
168typedef struct PL330Fifo {
169 uint8_t *buf;
170 uint8_t *tag;
171 uint32_t head;
172 uint32_t num;
173 uint32_t buf_size;
174} PL330Fifo;
175
176static const VMStateDescription vmstate_pl330_fifo = {
177 .name = "pl330_chan",
178 .version_id = 1,
179 .minimum_version_id = 1,
180 .fields = (VMStateField[]) {
181 VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, buf_size),
182 VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, buf_size),
183 VMSTATE_UINT32(head, PL330Fifo),
184 VMSTATE_UINT32(num, PL330Fifo),
185 VMSTATE_UINT32(buf_size, PL330Fifo),
186 VMSTATE_END_OF_LIST()
187 }
188};
189
190typedef struct PL330QueueEntry {
191 uint32_t addr;
192 uint32_t len;
193 uint8_t n;
194 bool inc;
195 bool z;
196 uint8_t tag;
197 uint8_t seqn;
198} PL330QueueEntry;
199
200static const VMStateDescription vmstate_pl330_queue_entry = {
201 .name = "pl330_queue_entry",
202 .version_id = 1,
203 .minimum_version_id = 1,
204 .fields = (VMStateField[]) {
205 VMSTATE_UINT32(addr, PL330QueueEntry),
206 VMSTATE_UINT32(len, PL330QueueEntry),
207 VMSTATE_UINT8(n, PL330QueueEntry),
208 VMSTATE_BOOL(inc, PL330QueueEntry),
209 VMSTATE_BOOL(z, PL330QueueEntry),
210 VMSTATE_UINT8(tag, PL330QueueEntry),
211 VMSTATE_UINT8(seqn, PL330QueueEntry),
212 VMSTATE_END_OF_LIST()
213 }
214};
215
216typedef struct PL330Queue {
217 PL330State *parent;
218 PL330QueueEntry *queue;
219 uint32_t queue_size;
220} PL330Queue;
221
222static const VMStateDescription vmstate_pl330_queue = {
223 .name = "pl330_queue",
224 .version_id = 2,
225 .minimum_version_id = 2,
226 .fields = (VMStateField[]) {
227 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(queue, PL330Queue, queue_size,
228 vmstate_pl330_queue_entry,
229 PL330QueueEntry),
230 VMSTATE_END_OF_LIST()
231 }
232};
233
234struct PL330State {
235 SysBusDevice parent_obj;
236
237 MemoryRegion iomem;
238 qemu_irq irq_abort;
239 qemu_irq *irq;
240
241 /* Config registers. cfg[5] = CfgDn. */
242 uint32_t cfg[6];
243#define EVENT_SEC_STATE 3
244#define PERIPH_SEC_STATE 4
245 /* cfg 0 bits and pieces */
246 uint32_t num_chnls;
247 uint8_t num_periph_req;
248 uint8_t num_events;
249 uint8_t mgr_ns_at_rst;
250 /* cfg 1 bits and pieces */
251 uint8_t i_cache_len;
252 uint8_t num_i_cache_lines;
253 /* CRD bits and pieces */
254 uint8_t data_width;
255 uint8_t wr_cap;
256 uint8_t wr_q_dep;
257 uint8_t rd_cap;
258 uint8_t rd_q_dep;
259 uint16_t data_buffer_dep;
260
261 PL330Chan manager;
262 PL330Chan *chan;
263 PL330Fifo fifo;
264 PL330Queue read_queue;
265 PL330Queue write_queue;
266 uint8_t *lo_seqn;
267 uint8_t *hi_seqn;
268 QEMUTimer *timer; /* is used for restore dma. */
269
270 uint32_t inten;
271 uint32_t int_status;
272 uint32_t ev_status;
273 uint32_t dbg[2];
274 uint8_t debug_status;
275 uint8_t num_faulting;
276 uint8_t periph_busy[PL330_PERIPH_NUM];
277
278};
279
280#define TYPE_PL330 "pl330"
281#define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330)
282
283static const VMStateDescription vmstate_pl330 = {
284 .name = "pl330",
285 .version_id = 2,
286 .minimum_version_id = 2,
287 .fields = (VMStateField[]) {
288 VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
289 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(chan, PL330State, num_chnls,
290 vmstate_pl330_chan, PL330Chan),
291 VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, num_chnls),
292 VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, num_chnls),
293 VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
294 VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue,
295 PL330Queue),
296 VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
297 PL330Queue),
298 VMSTATE_TIMER_PTR(timer, PL330State),
299 VMSTATE_UINT32(inten, PL330State),
300 VMSTATE_UINT32(int_status, PL330State),
301 VMSTATE_UINT32(ev_status, PL330State),
302 VMSTATE_UINT32_ARRAY(dbg, PL330State, 2),
303 VMSTATE_UINT8(debug_status, PL330State),
304 VMSTATE_UINT8(num_faulting, PL330State),
305 VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM),
306 VMSTATE_END_OF_LIST()
307 }
308};
309
310typedef struct PL330InsnDesc {
311 /* OPCODE of the instruction */
312 uint8_t opcode;
313 /* Mask so we can select several sibling instructions, such as
314 DMALD, DMALDS and DMALDB */
315 uint8_t opmask;
316 /* Size of instruction in bytes */
317 uint8_t size;
318 /* Interpreter */
319 void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len);
320} PL330InsnDesc;
321
322
323/* MFIFO Implementation
324 *
325 * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are
326 * stored in this buffer. Data is stored in BUF field, tags - in the
327 * corresponding array elements of TAG field.
328 */
329
330/* Initialize queue. */
331
332static void pl330_fifo_init(PL330Fifo *s, uint32_t size)
333{
334 s->buf = g_malloc0(size);
335 s->tag = g_malloc0(size);
336 s->buf_size = size;
337}
338
339/* Cyclic increment */
340
341static inline int pl330_fifo_inc(PL330Fifo *s, int x)
342{
343 return (x + 1) % s->buf_size;
344}
345
346/* Number of empty bytes in MFIFO */
347
348static inline int pl330_fifo_num_free(PL330Fifo *s)
349{
350 return s->buf_size - s->num;
351}
352
353/* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG.
354 * Zero returned on success, PL330_FIFO_STALL if there is no enough free
355 * space in MFIFO to store requested amount of data. If push was unsuccessful
356 * no data is stored to MFIFO.
357 */
358
359static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
360{
361 int i;
362
363 if (s->buf_size - s->num < len) {
364 return PL330_FIFO_STALL;
365 }
366 for (i = 0; i < len; i++) {
367 int push_idx = (s->head + s->num + i) % s->buf_size;
368 s->buf[push_idx] = buf[i];
369 s->tag[push_idx] = tag;
370 }
371 s->num += len;
372 return PL330_FIFO_OK;
373}
374
375/* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each
376 * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch
377 * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was
378 * unsuccessful no data is removed from MFIFO.
379 */
380
381static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
382{
383 int i;
384
385 if (s->num < len) {
386 return PL330_FIFO_STALL;
387 }
388 for (i = 0; i < len; i++) {
389 if (s->tag[s->head] == tag) {
390 int get_idx = (s->head + i) % s->buf_size;
391 buf[i] = s->buf[get_idx];
392 } else { /* Tag mismatch - Rollback transaction */
393 return PL330_FIFO_ERR;
394 }
395 }
396 s->head = (s->head + len) % s->buf_size;
397 s->num -= len;
398 return PL330_FIFO_OK;
399}
400
401/* Reset MFIFO. This completely erases all data in it. */
402
403static inline void pl330_fifo_reset(PL330Fifo *s)
404{
405 s->head = 0;
406 s->num = 0;
407}
408
409/* Return tag of the first byte stored in MFIFO. If MFIFO is empty
410 * PL330_UNTAGGED is returned.
411 */
412
413static inline uint8_t pl330_fifo_tag(PL330Fifo *s)
414{
415 return (!s->num) ? PL330_UNTAGGED : s->tag[s->head];
416}
417
418/* Returns non-zero if tag TAG is present in fifo or zero otherwise */
419
420static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag)
421{
422 int i, n;
423
424 i = s->head;
425 for (n = 0; n < s->num; n++) {
426 if (s->tag[i] == tag) {
427 return 1;
428 }
429 i = pl330_fifo_inc(s, i);
430 }
431 return 0;
432}
433
434/* Remove all entry tagged with TAG from MFIFO */
435
436static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag)
437{
438 int i, t, n;
439
440 t = i = s->head;
441 for (n = 0; n < s->num; n++) {
442 if (s->tag[i] != tag) {
443 s->buf[t] = s->buf[i];
444 s->tag[t] = s->tag[i];
445 t = pl330_fifo_inc(s, t);
446 } else {
447 s->num = s->num - 1;
448 }
449 i = pl330_fifo_inc(s, i);
450 }
451}
452
453/* Read-Write Queue implementation
454 *
455 * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores).
456 * Each instruction is described by source (for loads) or destination (for
457 * stores) address ADDR, width of data to be loaded/stored LEN, number of
458 * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel
459 * this instruction belongs to. Queue does not store any information about
460 * nature of the instruction: is it load or store. PL330 has different queues
461 * for loads and stores so this is already known at the top level where it
462 * matters.
463 *
464 * Queue works as FIFO for instructions with equivalent tags, but can issue
465 * instructions with different tags in arbitrary order. SEQN field attached to
466 * each instruction helps to achieve this. For each TAG queue contains
467 * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to
468 * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is
469 * followed by SEQN=0.
470 *
471 * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed
472 * in this case.
473 */
474
475static void pl330_queue_reset(PL330Queue *s)
476{
477 int i;
478
479 for (i = 0; i < s->queue_size; i++) {
480 s->queue[i].tag = PL330_UNTAGGED;
481 }
482}
483
484/* Initialize queue */
485static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent)
486{
487 s->parent = parent;
488 s->queue = g_new0(PL330QueueEntry, size);
489 s->queue_size = size;
490}
491
492/* Returns pointer to an empty slot or NULL if queue is full */
493static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s)
494{
495 int i;
496
497 for (i = 0; i < s->queue_size; i++) {
498 if (s->queue[i].tag == PL330_UNTAGGED) {
499 return &s->queue[i];
500 }
501 }
502 return NULL;
503}
504
505/* Put instruction in queue.
506 * Return value:
507 * - zero - OK
508 * - non-zero - queue is full
509 */
510
511static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr,
512 int len, int n, bool inc, bool z, uint8_t tag)
513{
514 PL330QueueEntry *entry = pl330_queue_find_empty(s);
515
516 if (!entry) {
517 return 1;
518 }
519 entry->tag = tag;
520 entry->addr = addr;
521 entry->len = len;
522 entry->n = n;
523 entry->z = z;
524 entry->inc = inc;
525 entry->seqn = s->parent->hi_seqn[tag];
526 s->parent->hi_seqn[tag]++;
527 return 0;
528}
529
530/* Returns a pointer to queue slot containing instruction which satisfies
531 * following conditions:
532 * - it has valid tag value (not PL330_UNTAGGED)
533 * - if enforce_seq is set it has to be issuable without violating queue
534 * logic (see above)
535 * - if TAG argument is not PL330_UNTAGGED this instruction has tag value
536 * equivalent to the argument TAG value.
537 * If such instruction cannot be found NULL is returned.
538 */
539
540static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag,
541 bool enforce_seq)
542{
543 int i;
544
545 for (i = 0; i < s->queue_size; i++) {
546 if (s->queue[i].tag != PL330_UNTAGGED) {
547 if ((!enforce_seq ||
548 s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) &&
549 (s->queue[i].tag == tag || tag == PL330_UNTAGGED ||
550 s->queue[i].z)) {
551 return &s->queue[i];
552 }
553 }
554 }
555 return NULL;
556}
557
558/* Removes instruction from queue. */
559
560static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e)
561{
562 s->parent->lo_seqn[e->tag]++;
563 e->tag = PL330_UNTAGGED;
564}
565
566/* Removes all instructions tagged with TAG from queue. */
567
568static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag)
569{
570 int i;
571
572 for (i = 0; i < s->queue_size; i++) {
573 if (s->queue[i].tag == tag) {
574 s->queue[i].tag = PL330_UNTAGGED;
575 }
576 }
577}
578
579/* DMA instruction execution engine */
580
581/* Moves DMA channel to the FAULT state and updates it's status. */
582
583static inline void pl330_fault(PL330Chan *ch, uint32_t flags)
584{
585 DB_PRINT("ch: %p, flags: %" PRIx32 "\n", ch, flags);
586 ch->fault_type |= flags;
587 if (ch->state == pl330_chan_fault) {
588 return;
589 }
590 ch->state = pl330_chan_fault;
591 ch->parent->num_faulting++;
592 if (ch->parent->num_faulting == 1) {
593 DB_PRINT("abort interrupt raised\n");
594 qemu_irq_raise(ch->parent->irq_abort);
595 }
596}
597
598/*
599 * For information about instructions see PL330 Technical Reference Manual.
600 *
601 * Arguments:
602 * CH - channel executing the instruction
603 * OPCODE - opcode
604 * ARGS - array of 8-bit arguments
605 * LEN - number of elements in ARGS array
606 */
607
608static void pl330_dmaadxh(PL330Chan *ch, uint8_t *args, bool ra, bool neg)
609{
610 uint32_t im = (args[1] << 8) | args[0];
611 if (neg) {
612 im |= 0xffffu << 16;
613 }
614
615 if (ch->is_manager) {
616 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
617 return;
618 }
619 if (ra) {
620 ch->dst += im;
621 } else {
622 ch->src += im;
623 }
624}
625
626static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
627{
628 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), false);
629}
630
631static void pl330_dmaadnh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
632{
633 pl330_dmaadxh(ch, args, extract32(opcode, 1, 1), true);
634}
635
636static void pl330_dmaend(PL330Chan *ch, uint8_t opcode,
637 uint8_t *args, int len)
638{
639 PL330State *s = ch->parent;
640
641 if (ch->state == pl330_chan_executing && !ch->is_manager) {
642 /* Wait for all transfers to complete */
643 if (pl330_fifo_has_tag(&s->fifo, ch->tag) ||
644 pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL ||
645 pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) {
646
647 ch->stall = 1;
648 return;
649 }
650 }
651 DB_PRINT("DMA ending!\n");
652 pl330_fifo_tagged_remove(&s->fifo, ch->tag);
653 pl330_queue_remove_tagged(&s->read_queue, ch->tag);
654 pl330_queue_remove_tagged(&s->write_queue, ch->tag);
655 ch->state = pl330_chan_stopped;
656}
657
658static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode,
659 uint8_t *args, int len)
660{
661 uint8_t periph_id;
662
663 if (args[0] & 7) {
664 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
665 return;
666 }
667 periph_id = (args[0] >> 3) & 0x1f;
668 if (periph_id >= ch->parent->num_periph_req) {
669 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
670 return;
671 }
672 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
673 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
674 return;
675 }
676 /* Do nothing */
677}
678
679static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
680{
681 uint8_t chan_id;
682 uint8_t ns;
683 uint32_t pc;
684 PL330Chan *s;
685
686 DB_PRINT("\n");
687
688 if (!ch->is_manager) {
689 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
690 return;
691 }
692 ns = !!(opcode & 2);
693 chan_id = args[0] & 7;
694 if ((args[0] >> 3)) {
695 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
696 return;
697 }
698 if (chan_id >= ch->parent->num_chnls) {
699 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
700 return;
701 }
702 pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
703 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
704 if (ch->parent->chan[chan_id].state != pl330_chan_stopped) {
705 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
706 return;
707 }
708 if (ch->ns && !ns) {
709 pl330_fault(ch, PL330_FAULT_DMAGO_ERR);
710 return;
711 }
712 s = &ch->parent->chan[chan_id];
713 s->ns = ns;
714 s->pc = pc;
715 s->state = pl330_chan_executing;
716}
717
718static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
719{
720 uint8_t bs = opcode & 3;
721 uint32_t size, num;
722 bool inc;
723
724 if (bs == 2) {
725 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
726 return;
727 }
728 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
729 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
730 /* Perform NOP */
731 return;
732 }
733 if (bs == 1 && ch->request_flag == PL330_SINGLE) {
734 num = 1;
735 } else {
736 num = ((ch->control >> 4) & 0xf) + 1;
737 }
738 size = (uint32_t)1 << ((ch->control >> 1) & 0x7);
739 inc = !!(ch->control & 1);
740 ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src,
741 size, num, inc, 0, ch->tag);
742 if (!ch->stall) {
743 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32
744 " num:%" PRId32 " %c\n",
745 ch->tag, ch->src, size, num, inc ? 'Y' : 'N');
746 ch->src += inc ? size * num - (ch->src & (size - 1)) : 0;
747 }
748}
749
750static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
751{
752 uint8_t periph_id;
753
754 if (args[0] & 7) {
755 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
756 return;
757 }
758 periph_id = (args[0] >> 3) & 0x1f;
759 if (periph_id >= ch->parent->num_periph_req) {
760 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
761 return;
762 }
763 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
764 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
765 return;
766 }
767 pl330_dmald(ch, opcode, args, len);
768}
769
770static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
771{
772 uint8_t lc = (opcode & 2) >> 1;
773
774 ch->lc[lc] = args[0];
775}
776
777static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
778{
779 if (ch->state == pl330_chan_fault ||
780 ch->state == pl330_chan_fault_completing) {
781 /* This is the only way for a channel to leave the faulting state */
782 ch->fault_type = 0;
783 ch->parent->num_faulting--;
784 if (ch->parent->num_faulting == 0) {
785 DB_PRINT("abort interrupt lowered\n");
786 qemu_irq_lower(ch->parent->irq_abort);
787 }
788 }
789 ch->state = pl330_chan_killing;
790 pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag);
791 pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag);
792 pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag);
793 ch->state = pl330_chan_stopped;
794}
795
796static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode,
797 uint8_t *args, int len)
798{
799 uint8_t nf = (opcode & 0x10) >> 4;
800 uint8_t bs = opcode & 3;
801 uint8_t lc = (opcode & 4) >> 2;
802
803 if (bs == 2) {
804 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
805 return;
806 }
807 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
808 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
809 /* Perform NOP */
810 return;
811 }
812 if (!nf || ch->lc[lc]) {
813 if (nf) {
814 ch->lc[lc]--;
815 }
816 DB_PRINT("loop reiteration\n");
817 ch->pc -= args[0];
818 ch->pc -= len + 1;
819 /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */
820 } else {
821 DB_PRINT("loop fallthrough\n");
822 }
823}
824
825
826static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
827{
828 uint8_t rd = args[0] & 7;
829 uint32_t im;
830
831 if ((args[0] >> 3)) {
832 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
833 return;
834 }
835 im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
836 (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
837 switch (rd) {
838 case 0:
839 ch->src = im;
840 break;
841 case 1:
842 ch->control = im;
843 break;
844 case 2:
845 ch->dst = im;
846 break;
847 default:
848 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
849 return;
850 }
851}
852
853static void pl330_dmanop(PL330Chan *ch, uint8_t opcode,
854 uint8_t *args, int len)
855{
856 /* NOP is NOP. */
857}
858
859static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
860{
861 if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) {
862 ch->state = pl330_chan_at_barrier;
863 ch->stall = 1;
864 return;
865 } else {
866 ch->state = pl330_chan_executing;
867 }
868}
869
870static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
871{
872 uint8_t ev_id;
873
874 if (args[0] & 7) {
875 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
876 return;
877 }
878 ev_id = (args[0] >> 3) & 0x1f;
879 if (ev_id >= ch->parent->num_events) {
880 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
881 return;
882 }
883 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
884 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
885 return;
886 }
887 if (ch->parent->inten & (1 << ev_id)) {
888 ch->parent->int_status |= (1 << ev_id);
889 DB_PRINT("event interrupt raised %" PRId8 "\n", ev_id);
890 qemu_irq_raise(ch->parent->irq[ev_id]);
891 }
892 DB_PRINT("event raised %" PRId8 "\n", ev_id);
893 ch->parent->ev_status |= (1 << ev_id);
894}
895
896static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
897{
898 uint8_t bs = opcode & 3;
899 uint32_t size, num;
900 bool inc;
901
902 if (bs == 2) {
903 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
904 return;
905 }
906 if ((bs == 1 && ch->request_flag == PL330_BURST) ||
907 (bs == 3 && ch->request_flag == PL330_SINGLE)) {
908 /* Perform NOP */
909 return;
910 }
911 num = ((ch->control >> 18) & 0xf) + 1;
912 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
913 inc = !!((ch->control >> 14) & 1);
914 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
915 size, num, inc, 0, ch->tag);
916 if (!ch->stall) {
917 DB_PRINT("channel:%" PRId8 " address:%08" PRIx32 " size:%" PRIx32
918 " num:%" PRId32 " %c\n",
919 ch->tag, ch->dst, size, num, inc ? 'Y' : 'N');
920 ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0;
921 }
922}
923
924static void pl330_dmastp(PL330Chan *ch, uint8_t opcode,
925 uint8_t *args, int len)
926{
927 uint8_t periph_id;
928
929 if (args[0] & 7) {
930 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
931 return;
932 }
933 periph_id = (args[0] >> 3) & 0x1f;
934 if (periph_id >= ch->parent->num_periph_req) {
935 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
936 return;
937 }
938 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
939 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
940 return;
941 }
942 pl330_dmast(ch, opcode, args, len);
943}
944
945static void pl330_dmastz(PL330Chan *ch, uint8_t opcode,
946 uint8_t *args, int len)
947{
948 uint32_t size, num;
949 bool inc;
950
951 num = ((ch->control >> 18) & 0xf) + 1;
952 size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
953 inc = !!((ch->control >> 14) & 1);
954 ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
955 size, num, inc, 1, ch->tag);
956 if (inc) {
957 ch->dst += size * num;
958 }
959}
960
961static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode,
962 uint8_t *args, int len)
963{
964 uint8_t ev_id;
965 int i;
966
967 if (args[0] & 5) {
968 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
969 return;
970 }
971 ev_id = (args[0] >> 3) & 0x1f;
972 if (ev_id >= ch->parent->num_events) {
973 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
974 return;
975 }
976 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
977 pl330_fault(ch, PL330_FAULT_EVENT_ERR);
978 return;
979 }
980 ch->wakeup = ev_id;
981 ch->state = pl330_chan_waiting_event;
982 if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) {
983 ch->state = pl330_chan_executing;
984 /* If anyone else is currently waiting on the same event, let them
985 * clear the ev_status so they pick up event as well
986 */
987 for (i = 0; i < ch->parent->num_chnls; ++i) {
988 PL330Chan *peer = &ch->parent->chan[i];
989 if (peer->state == pl330_chan_waiting_event &&
990 peer->wakeup == ev_id) {
991 return;
992 }
993 }
994 ch->parent->ev_status &= ~(1 << ev_id);
995 DB_PRINT("event lowered %" PRIx8 "\n", ev_id);
996 } else {
997 ch->stall = 1;
998 }
999}
1000
1001static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode,
1002 uint8_t *args, int len)
1003{
1004 uint8_t bs = opcode & 3;
1005 uint8_t periph_id;
1006
1007 if (args[0] & 7) {
1008 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1009 return;
1010 }
1011 periph_id = (args[0] >> 3) & 0x1f;
1012 if (periph_id >= ch->parent->num_periph_req) {
1013 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1014 return;
1015 }
1016 if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
1017 pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
1018 return;
1019 }
1020 switch (bs) {
1021 case 0: /* S */
1022 ch->request_flag = PL330_SINGLE;
1023 ch->wfp_sbp = 0;
1024 break;
1025 case 1: /* P */
1026 ch->request_flag = PL330_BURST;
1027 ch->wfp_sbp = 2;
1028 break;
1029 case 2: /* B */
1030 ch->request_flag = PL330_BURST;
1031 ch->wfp_sbp = 1;
1032 break;
1033 default:
1034 pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
1035 return;
1036 }
1037
1038 if (ch->parent->periph_busy[periph_id]) {
1039 ch->state = pl330_chan_waiting_periph;
1040 ch->stall = 1;
1041 } else if (ch->state == pl330_chan_waiting_periph) {
1042 ch->state = pl330_chan_executing;
1043 }
1044}
1045
1046static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode,
1047 uint8_t *args, int len)
1048{
1049 if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) {
1050 ch->state = pl330_chan_at_barrier;
1051 ch->stall = 1;
1052 return;
1053 } else {
1054 ch->state = pl330_chan_executing;
1055 }
1056}
1057
1058/* NULL terminated array of the instruction descriptions. */
1059static const PL330InsnDesc insn_desc[] = {
1060 { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, },
1061 { .opcode = 0x5c, .opmask = 0xFD, .size = 3, .exec = pl330_dmaadnh, },
1062 { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, },
1063 { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, },
1064 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1065 { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, },
1066 { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, },
1067 { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, },
1068 /* dmastp must be before dmalpend in this list, because their maps
1069 * are overlapping
1070 */
1071 { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, },
1072 { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, },
1073 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1074 { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, },
1075 { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, },
1076 { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, },
1077 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1078 { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, },
1079 { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, },
1080 { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, },
1081 { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, },
1082 { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, },
1083 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1084};
1085
1086/* Instructions which can be issued via debug registers. */
1087static const PL330InsnDesc debug_insn_desc[] = {
1088 { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
1089 { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
1090 { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
1091 { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
1092};
1093
1094static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)
1095{
1096 uint8_t opcode;
1097 int i;
1098
1099 dma_memory_read(&address_space_memory, ch->pc, &opcode, 1);
1100 for (i = 0; insn_desc[i].size; i++) {
1101 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
1102 return &insn_desc[i];
1103 }
1104 }
1105 return NULL;
1106}
1107
1108static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)
1109{
1110 uint8_t buf[PL330_INSN_MAXSIZE];
1111
1112 assert(insn->size <= PL330_INSN_MAXSIZE);
1113 dma_memory_read(&address_space_memory, ch->pc, buf, insn->size);
1114 insn->exec(ch, buf[0], &buf[1], insn->size - 1);
1115}
1116
1117static inline void pl330_update_pc(PL330Chan *ch,
1118 const PL330InsnDesc *insn)
1119{
1120 ch->pc += insn->size;
1121}
1122
1123/* Try to execute current instruction in channel CH. Number of executed
1124 instructions is returned (0 or 1). */
1125static int pl330_chan_exec(PL330Chan *ch)
1126{
1127 const PL330InsnDesc *insn;
1128
1129 if (ch->state != pl330_chan_executing &&
1130 ch->state != pl330_chan_waiting_periph &&
1131 ch->state != pl330_chan_at_barrier &&
1132 ch->state != pl330_chan_waiting_event) {
1133 return 0;
1134 }
1135 ch->stall = 0;
1136 insn = pl330_fetch_insn(ch);
1137 if (!insn) {
1138 DB_PRINT("pl330 undefined instruction\n");
1139 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
1140 return 0;
1141 }
1142 pl330_exec_insn(ch, insn);
1143 if (!ch->stall) {
1144 pl330_update_pc(ch, insn);
1145 ch->watchdog_timer = 0;
1146 return 1;
1147 /* WDT only active in exec state */
1148 } else if (ch->state == pl330_chan_executing) {
1149 ch->watchdog_timer++;
1150 if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) {
1151 pl330_fault(ch, PL330_FAULT_LOCKUP_ERR);
1152 }
1153 }
1154 return 0;
1155}
1156
1157/* Try to execute 1 instruction in each channel, one instruction from read
1158 queue and one instruction from write queue. Number of successfully executed
1159 instructions is returned. */
1160static int pl330_exec_cycle(PL330Chan *channel)
1161{
1162 PL330State *s = channel->parent;
1163 PL330QueueEntry *q;
1164 int i;
1165 int num_exec = 0;
1166 int fifo_res = 0;
1167 uint8_t buf[PL330_MAX_BURST_LEN];
1168
1169 /* Execute one instruction in each channel */
1170 num_exec += pl330_chan_exec(channel);
1171
1172 /* Execute one instruction from read queue */
1173 q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true);
1174 if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) {
1175 int len = q->len - (q->addr & (q->len - 1));
1176
1177 dma_memory_read(&address_space_memory, q->addr, buf, len);
1178 if (PL330_ERR_DEBUG > 1) {
1179 DB_PRINT("PL330 read from memory @%08" PRIx32 " (size = %08x):\n",
1180 q->addr, len);
1181 qemu_hexdump((char *)buf, stderr, "", len);
1182 }
1183 fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag);
1184 if (fifo_res == PL330_FIFO_OK) {
1185 if (q->inc) {
1186 q->addr += len;
1187 }
1188 q->n--;
1189 if (!q->n) {
1190 pl330_queue_remove_insn(&s->read_queue, q);
1191 }
1192 num_exec++;
1193 }
1194 }
1195
1196 /* Execute one instruction from write queue. */
1197 q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true);
1198 if (q != NULL) {
1199 int len = q->len - (q->addr & (q->len - 1));
1200
1201 if (q->z) {
1202 for (i = 0; i < len; i++) {
1203 buf[i] = 0;
1204 }
1205 } else {
1206 fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag);
1207 }
1208 if (fifo_res == PL330_FIFO_OK || q->z) {
1209 dma_memory_write(&address_space_memory, q->addr, buf, len);
1210 if (PL330_ERR_DEBUG > 1) {
1211 DB_PRINT("PL330 read from memory @%08" PRIx32
1212 " (size = %08x):\n", q->addr, len);
1213 qemu_hexdump((char *)buf, stderr, "", len);
1214 }
1215 if (q->inc) {
1216 q->addr += len;
1217 }
1218 num_exec++;
1219 } else if (fifo_res == PL330_FIFO_STALL) {
1220 pl330_fault(&channel->parent->chan[q->tag],
1221 PL330_FAULT_FIFOEMPTY_ERR);
1222 }
1223 q->n--;
1224 if (!q->n) {
1225 pl330_queue_remove_insn(&s->write_queue, q);
1226 }
1227 }
1228
1229 return num_exec;
1230}
1231
1232static int pl330_exec_channel(PL330Chan *channel)
1233{
1234 int insr_exec = 0;
1235
1236 /* TODO: Is it all right to execute everything or should we do per-cycle
1237 simulation? */
1238 while (pl330_exec_cycle(channel)) {
1239 insr_exec++;
1240 }
1241
1242 /* Detect deadlock */
1243 if (channel->state == pl330_chan_executing) {
1244 pl330_fault(channel, PL330_FAULT_LOCKUP_ERR);
1245 }
1246 /* Situation when one of the queues has deadlocked but all channels
1247 * have finished their programs should be impossible.
1248 */
1249
1250 return insr_exec;
1251}
1252
1253static inline void pl330_exec(PL330State *s)
1254{
1255 DB_PRINT("\n");
1256 int i, insr_exec;
1257 do {
1258 insr_exec = pl330_exec_channel(&s->manager);
1259
1260 for (i = 0; i < s->num_chnls; i++) {
1261 insr_exec += pl330_exec_channel(&s->chan[i]);
1262 }
1263 } while (insr_exec);
1264}
1265
1266static void pl330_exec_cycle_timer(void *opaque)
1267{
1268 PL330State *s = (PL330State *)opaque;
1269 pl330_exec(s);
1270}
1271
1272/* Stop or restore dma operations */
1273
1274static void pl330_dma_stop_irq(void *opaque, int irq, int level)
1275{
1276 PL330State *s = (PL330State *)opaque;
1277
1278 if (s->periph_busy[irq] != level) {
1279 s->periph_busy[irq] = level;
1280 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
1281 }
1282}
1283
1284static void pl330_debug_exec(PL330State *s)
1285{
1286 uint8_t args[5];
1287 uint8_t opcode;
1288 uint8_t chan_id;
1289 int i;
1290 PL330Chan *ch;
1291 const PL330InsnDesc *insn;
1292
1293 s->debug_status = 1;
1294 chan_id = (s->dbg[0] >> 8) & 0x07;
1295 opcode = (s->dbg[0] >> 16) & 0xff;
1296 args[0] = (s->dbg[0] >> 24) & 0xff;
1297 args[1] = (s->dbg[1] >> 0) & 0xff;
1298 args[2] = (s->dbg[1] >> 8) & 0xff;
1299 args[3] = (s->dbg[1] >> 16) & 0xff;
1300 args[4] = (s->dbg[1] >> 24) & 0xff;
1301 DB_PRINT("chan id: %" PRIx8 "\n", chan_id);
1302 if (s->dbg[0] & 1) {
1303 ch = &s->chan[chan_id];
1304 } else {
1305 ch = &s->manager;
1306 }
1307 insn = NULL;
1308 for (i = 0; debug_insn_desc[i].size; i++) {
1309 if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) {
1310 insn = &debug_insn_desc[i];
1311 }
1312 }
1313 if (!insn) {
1314 pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR);
1315 return ;
1316 }
1317 ch->stall = 0;
1318 insn->exec(ch, opcode, args, insn->size - 1);
1319 if (ch->fault_type) {
1320 ch->fault_type |= PL330_FAULT_DBG_INSTR;
1321 }
1322 if (ch->stall) {
1323 qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not "
1324 "implemented\n");
1325 }
1326 s->debug_status = 0;
1327}
1328
1329/* IOMEM mapped registers */
1330
1331static void pl330_iomem_write(void *opaque, hwaddr offset,
1332 uint64_t value, unsigned size)
1333{
1334 PL330State *s = (PL330State *) opaque;
1335 int i;
1336
1337 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)value);
1338
1339 switch (offset) {
1340 case PL330_REG_INTEN:
1341 s->inten = value;
1342 break;
1343 case PL330_REG_INTCLR:
1344 for (i = 0; i < s->num_events; i++) {
1345 if (s->int_status & s->inten & value & (1 << i)) {
1346 DB_PRINT("event interrupt lowered %d\n", i);
1347 qemu_irq_lower(s->irq[i]);
1348 }
1349 }
1350 s->ev_status &= ~(value & s->inten);
1351 s->int_status &= ~(value & s->inten);
1352 break;
1353 case PL330_REG_DBGCMD:
1354 if ((value & 3) == 0) {
1355 pl330_debug_exec(s);
1356 pl330_exec(s);
1357 } else {
1358 qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
1359 "for offset " TARGET_FMT_plx "\n", (unsigned)value,
1360 offset);
1361 }
1362 break;
1363 case PL330_REG_DBGINST0:
1364 DB_PRINT("s->dbg[0] = %08x\n", (unsigned)value);
1365 s->dbg[0] = value;
1366 break;
1367 case PL330_REG_DBGINST1:
1368 DB_PRINT("s->dbg[1] = %08x\n", (unsigned)value);
1369 s->dbg[1] = value;
1370 break;
1371 default:
1372 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx
1373 "\n", offset);
1374 break;
1375 }
1376}
1377
1378static inline uint32_t pl330_iomem_read_imp(void *opaque,
1379 hwaddr offset)
1380{
1381 PL330State *s = (PL330State *)opaque;
1382 int chan_id;
1383 int i;
1384 uint32_t res;
1385
1386 if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) {
1387 return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2];
1388 }
1389 if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) {
1390 return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2];
1391 }
1392 if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) {
1393 offset -= PL330_REG_CHANCTRL;
1394 chan_id = offset >> 5;
1395 if (chan_id >= s->num_chnls) {
1396 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1397 TARGET_FMT_plx "\n", offset);
1398 return 0;
1399 }
1400 switch (offset & 0x1f) {
1401 case 0x00:
1402 return s->chan[chan_id].src;
1403 case 0x04:
1404 return s->chan[chan_id].dst;
1405 case 0x08:
1406 return s->chan[chan_id].control;
1407 case 0x0C:
1408 return s->chan[chan_id].lc[0];
1409 case 0x10:
1410 return s->chan[chan_id].lc[1];
1411 default:
1412 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1413 TARGET_FMT_plx "\n", offset);
1414 return 0;
1415 }
1416 }
1417 if (offset >= PL330_REG_CSR_BASE && offset < 0x400) {
1418 offset -= PL330_REG_CSR_BASE;
1419 chan_id = offset >> 3;
1420 if (chan_id >= s->num_chnls) {
1421 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1422 TARGET_FMT_plx "\n", offset);
1423 return 0;
1424 }
1425 switch ((offset >> 2) & 1) {
1426 case 0x0:
1427 res = (s->chan[chan_id].ns << 21) |
1428 (s->chan[chan_id].wakeup << 4) |
1429 (s->chan[chan_id].state) |
1430 (s->chan[chan_id].wfp_sbp << 14);
1431 return res;
1432 case 0x1:
1433 return s->chan[chan_id].pc;
1434 default:
1435 qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n");
1436 return 0;
1437 }
1438 }
1439 if (offset >= PL330_REG_FTR_BASE && offset < 0x100) {
1440 offset -= PL330_REG_FTR_BASE;
1441 chan_id = offset >> 2;
1442 if (chan_id >= s->num_chnls) {
1443 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1444 TARGET_FMT_plx "\n", offset);
1445 return 0;
1446 }
1447 return s->chan[chan_id].fault_type;
1448 }
1449 switch (offset) {
1450 case PL330_REG_DSR:
1451 return (s->manager.ns << 9) | (s->manager.wakeup << 4) |
1452 (s->manager.state & 0xf);
1453 case PL330_REG_DPC:
1454 return s->manager.pc;
1455 case PL330_REG_INTEN:
1456 return s->inten;
1457 case PL330_REG_INT_EVENT_RIS:
1458 return s->ev_status;
1459 case PL330_REG_INTMIS:
1460 return s->int_status;
1461 case PL330_REG_INTCLR:
1462 /* Documentation says that we can't read this register
1463 * but linux kernel does it
1464 */
1465 return 0;
1466 case PL330_REG_FSRD:
1467 return s->manager.state ? 1 : 0;
1468 case PL330_REG_FSRC:
1469 res = 0;
1470 for (i = 0; i < s->num_chnls; i++) {
1471 if (s->chan[i].state == pl330_chan_fault ||
1472 s->chan[i].state == pl330_chan_fault_completing) {
1473 res |= 1 << i;
1474 }
1475 }
1476 return res;
1477 case PL330_REG_FTRD:
1478 return s->manager.fault_type;
1479 case PL330_REG_DBGSTATUS:
1480 return s->debug_status;
1481 default:
1482 qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
1483 TARGET_FMT_plx "\n", offset);
1484 }
1485 return 0;
1486}
1487
1488static uint64_t pl330_iomem_read(void *opaque, hwaddr offset,
1489 unsigned size)
1490{
1491 uint32_t ret = pl330_iomem_read_imp(opaque, offset);
1492 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset, ret);
1493 return ret;
1494}
1495
1496static const MemoryRegionOps pl330_ops = {
1497 .read = pl330_iomem_read,
1498 .write = pl330_iomem_write,
1499 .endianness = DEVICE_NATIVE_ENDIAN,
1500 .impl = {
1501 .min_access_size = 4,
1502 .max_access_size = 4,
1503 }
1504};
1505
1506/* Controller logic and initialization */
1507
1508static void pl330_chan_reset(PL330Chan *ch)
1509{
1510 ch->src = 0;
1511 ch->dst = 0;
1512 ch->pc = 0;
1513 ch->state = pl330_chan_stopped;
1514 ch->watchdog_timer = 0;
1515 ch->stall = 0;
1516 ch->control = 0;
1517 ch->status = 0;
1518 ch->fault_type = 0;
1519}
1520
1521static void pl330_reset(DeviceState *d)
1522{
1523 int i;
1524 PL330State *s = PL330(d);
1525
1526 s->inten = 0;
1527 s->int_status = 0;
1528 s->ev_status = 0;
1529 s->debug_status = 0;
1530 s->num_faulting = 0;
1531 s->manager.ns = s->mgr_ns_at_rst;
1532 pl330_fifo_reset(&s->fifo);
1533 pl330_queue_reset(&s->read_queue);
1534 pl330_queue_reset(&s->write_queue);
1535
1536 for (i = 0; i < s->num_chnls; i++) {
1537 pl330_chan_reset(&s->chan[i]);
1538 }
1539 for (i = 0; i < s->num_periph_req; i++) {
1540 s->periph_busy[i] = 0;
1541 }
1542
1543 timer_del(s->timer);
1544}
1545
1546static void pl330_realize(DeviceState *dev, Error **errp)
1547{
1548 int i;
1549 PL330State *s = PL330(dev);
1550
1551 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
1552 memory_region_init_io(&s->iomem, OBJECT(s), &pl330_ops, s,
1553 "dma", PL330_IOMEM_SIZE);
1554 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1555
1556 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);
1557
1558 s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
1559 (s->num_periph_req > 0 ? 1 : 0) |
1560 ((s->num_chnls - 1) & 0x7) << 4 |
1561 ((s->num_periph_req - 1) & 0x1f) << 12 |
1562 ((s->num_events - 1) & 0x1f) << 17;
1563
1564 switch (s->i_cache_len) {
1565 case (4):
1566 s->cfg[1] |= 2;
1567 break;
1568 case (8):
1569 s->cfg[1] |= 3;
1570 break;
1571 case (16):
1572 s->cfg[1] |= 4;
1573 break;
1574 case (32):
1575 s->cfg[1] |= 5;
1576 break;
1577 default:
1578 error_setg(errp, "Bad value for i-cache_len property: %" PRIx8,
1579 s->i_cache_len);
1580 return;
1581 }
1582 s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4;
1583
1584 s->chan = g_new0(PL330Chan, s->num_chnls);
1585 s->hi_seqn = g_new0(uint8_t, s->num_chnls);
1586 s->lo_seqn = g_new0(uint8_t, s->num_chnls);
1587 for (i = 0; i < s->num_chnls; i++) {
1588 s->chan[i].parent = s;
1589 s->chan[i].tag = (uint8_t)i;
1590 }
1591 s->manager.parent = s;
1592 s->manager.tag = s->num_chnls;
1593 s->manager.is_manager = true;
1594
1595 s->irq = g_new0(qemu_irq, s->num_events);
1596 for (i = 0; i < s->num_events; i++) {
1597 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1598 }
1599
1600 qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM);
1601
1602 switch (s->data_width) {
1603 case (32):
1604 s->cfg[CFG_CRD] |= 0x2;
1605 break;
1606 case (64):
1607 s->cfg[CFG_CRD] |= 0x3;
1608 break;
1609 case (128):
1610 s->cfg[CFG_CRD] |= 0x4;
1611 break;
1612 default:
1613 error_setg(errp, "Bad value for data_width property: %" PRIx8,
1614 s->data_width);
1615 return;
1616 }
1617
1618 s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 |
1619 ((s->wr_q_dep - 1) & 0xf) << 8 |
1620 ((s->rd_cap - 1) & 0x7) << 12 |
1621 ((s->rd_q_dep - 1) & 0xf) << 16 |
1622 ((s->data_buffer_dep - 1) & 0x1ff) << 20;
1623
1624 pl330_queue_init(&s->read_queue, s->rd_q_dep, s);
1625 pl330_queue_init(&s->write_queue, s->wr_q_dep, s);
1626 pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep);
1627}
1628
1629static Property pl330_properties[] = {
1630 /* CR0 */
1631 DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8),
1632 DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4),
1633 DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16),
1634 DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0),
1635 /* CR1 */
1636 DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4),
1637 DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8),
1638 /* CR2-4 */
1639 DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0),
1640 DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0),
1641 DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0),
1642 /* CRD */
1643 DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64),
1644 DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8),
1645 DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16),
1646 DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8),
1647 DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),
1648 DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256),
1649
1650 DEFINE_PROP_END_OF_LIST(),
1651};
1652
1653static void pl330_class_init(ObjectClass *klass, void *data)
1654{
1655 DeviceClass *dc = DEVICE_CLASS(klass);
1656
1657 dc->realize = pl330_realize;
1658 dc->reset = pl330_reset;
1659 dc->props = pl330_properties;
1660 dc->vmsd = &vmstate_pl330;
1661}
1662
1663static const TypeInfo pl330_type_info = {
1664 .name = TYPE_PL330,
1665 .parent = TYPE_SYS_BUS_DEVICE,
1666 .instance_size = sizeof(PL330State),
1667 .class_init = pl330_class_init,
1668};
1669
1670static void pl330_register_types(void)
1671{
1672 type_register_static(&pl330_type_info);
1673}
1674
1675type_init(pl330_register_types)
1676