1 | /* |
2 | * DMA device simulation in PKUnity SoC |
3 | * |
4 | * Copyright (C) 2010-2012 Guan Xuetao |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as |
8 | * published by the Free Software Foundation, or any later version. |
9 | * See the COPYING file in the top-level directory. |
10 | */ |
11 | |
12 | #include "qemu/osdep.h" |
13 | #include "hw/sysbus.h" |
14 | |
15 | #undef DEBUG_PUV3 |
16 | #include "hw/unicore32/puv3.h" |
17 | #include "qemu/module.h" |
18 | |
19 | #define PUV3_DMA_CH_NR (6) |
20 | #define PUV3_DMA_CH_MASK (0xff) |
21 | #define PUV3_DMA_CH(offset) ((offset) >> 8) |
22 | |
23 | #define TYPE_PUV3_DMA "puv3_dma" |
24 | #define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA) |
25 | |
26 | typedef struct PUV3DMAState { |
27 | SysBusDevice parent_obj; |
28 | |
29 | MemoryRegion iomem; |
30 | uint32_t reg_CFG[PUV3_DMA_CH_NR]; |
31 | } PUV3DMAState; |
32 | |
33 | static uint64_t puv3_dma_read(void *opaque, hwaddr offset, |
34 | unsigned size) |
35 | { |
36 | PUV3DMAState *s = opaque; |
37 | uint32_t ret = 0; |
38 | |
39 | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); |
40 | |
41 | switch (offset & PUV3_DMA_CH_MASK) { |
42 | case 0x10: |
43 | ret = s->reg_CFG[PUV3_DMA_CH(offset)]; |
44 | break; |
45 | default: |
46 | DPRINTF("Bad offset 0x%x\n" , offset); |
47 | } |
48 | DPRINTF("offset 0x%x, value 0x%x\n" , offset, ret); |
49 | |
50 | return ret; |
51 | } |
52 | |
53 | static void puv3_dma_write(void *opaque, hwaddr offset, |
54 | uint64_t value, unsigned size) |
55 | { |
56 | PUV3DMAState *s = opaque; |
57 | |
58 | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); |
59 | |
60 | switch (offset & PUV3_DMA_CH_MASK) { |
61 | case 0x10: |
62 | s->reg_CFG[PUV3_DMA_CH(offset)] = value; |
63 | break; |
64 | default: |
65 | DPRINTF("Bad offset 0x%x\n" , offset); |
66 | } |
67 | DPRINTF("offset 0x%x, value 0x%x\n" , offset, value); |
68 | } |
69 | |
70 | static const MemoryRegionOps puv3_dma_ops = { |
71 | .read = puv3_dma_read, |
72 | .write = puv3_dma_write, |
73 | .impl = { |
74 | .min_access_size = 4, |
75 | .max_access_size = 4, |
76 | }, |
77 | .endianness = DEVICE_NATIVE_ENDIAN, |
78 | }; |
79 | |
80 | static void puv3_dma_realize(DeviceState *dev, Error **errp) |
81 | { |
82 | PUV3DMAState *s = PUV3_DMA(dev); |
83 | int i; |
84 | |
85 | for (i = 0; i < PUV3_DMA_CH_NR; i++) { |
86 | s->reg_CFG[i] = 0x0; |
87 | } |
88 | |
89 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma" , |
90 | PUV3_REGS_OFFSET); |
91 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
92 | } |
93 | |
94 | static void puv3_dma_class_init(ObjectClass *klass, void *data) |
95 | { |
96 | DeviceClass *dc = DEVICE_CLASS(klass); |
97 | |
98 | dc->realize = puv3_dma_realize; |
99 | } |
100 | |
101 | static const TypeInfo puv3_dma_info = { |
102 | .name = TYPE_PUV3_DMA, |
103 | .parent = TYPE_SYS_BUS_DEVICE, |
104 | .instance_size = sizeof(PUV3DMAState), |
105 | .class_init = puv3_dma_class_init, |
106 | }; |
107 | |
108 | static void puv3_dma_register_type(void) |
109 | { |
110 | type_register_static(&puv3_dma_info); |
111 | } |
112 | |
113 | type_init(puv3_dma_register_type) |
114 | |