1/*
2 * ARM Aspeed I2C controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "migration/vmstate.h"
24#include "qemu/log.h"
25#include "qemu/module.h"
26#include "hw/i2c/aspeed_i2c.h"
27#include "hw/irq.h"
28
29/* I2C Global Register */
30
31#define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */
32#define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target
33 Assignment */
34
35/* I2C Device (Bus) Register */
36
37#define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */
38#define I2CD_BUFF_SEL_MASK (0x7 << 20)
39#define I2CD_BUFF_SEL(x) (x << 20)
40#define I2CD_M_SDA_LOCK_EN (0x1 << 16)
41#define I2CD_MULTI_MASTER_DIS (0x1 << 15)
42#define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
43#define I2CD_MSB_STS (0x1 << 9)
44#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
45#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
46#define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
47#define I2CD_DEF_ADDR_EN (0x1 << 5)
48#define I2CD_DEF_ALERT_EN (0x1 << 4)
49#define I2CD_DEF_ARP_EN (0x1 << 3)
50#define I2CD_DEF_GCALL_EN (0x1 << 2)
51#define I2CD_SLAVE_EN (0x1 << 1)
52#define I2CD_MASTER_EN (0x1)
53
54#define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */
55#define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */
56#define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
57#define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
58
59#define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */
60#define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30)
61/* bits[19-16] Reserved */
62
63/* All bits below are cleared by writing 1 */
64#define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
65#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
66#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
67#define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
68#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */
69#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
70#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
71#define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
72#define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */
73#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
74#define I2CD_INTR_ABNORMAL (0x1 << 5)
75#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
76#define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
77#define I2CD_INTR_RX_DONE (0x1 << 2)
78#define I2CD_INTR_TX_NAK (0x1 << 1)
79#define I2CD_INTR_TX_ACK (0x1 << 0)
80
81#define I2CD_CMD_REG 0x14 /* I2CD Command/Status */
82#define I2CD_SDA_OE (0x1 << 28)
83#define I2CD_SDA_O (0x1 << 27)
84#define I2CD_SCL_OE (0x1 << 26)
85#define I2CD_SCL_O (0x1 << 25)
86#define I2CD_TX_TIMING (0x1 << 24)
87#define I2CD_TX_STATUS (0x1 << 23)
88
89#define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */
90#define I2CD_TX_STATE_MASK 0xf
91#define I2CD_IDLE 0x0
92#define I2CD_MACTIVE 0x8
93#define I2CD_MSTART 0x9
94#define I2CD_MSTARTR 0xa
95#define I2CD_MSTOP 0xb
96#define I2CD_MTXD 0xc
97#define I2CD_MRXACK 0xd
98#define I2CD_MRXD 0xe
99#define I2CD_MTXACK 0xf
100#define I2CD_SWAIT 0x1
101#define I2CD_SRXD 0x4
102#define I2CD_STXACK 0x5
103#define I2CD_STXD 0x6
104#define I2CD_SRXACK 0x7
105#define I2CD_RECOVER 0x3
106
107#define I2CD_SCL_LINE_STS (0x1 << 18)
108#define I2CD_SDA_LINE_STS (0x1 << 17)
109#define I2CD_BUS_BUSY_STS (0x1 << 16)
110#define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
111#define I2CD_SDA_O_OUT_DIR (0x1 << 14)
112#define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
113#define I2CD_SCL_O_OUT_DIR (0x1 << 12)
114#define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11)
115#define I2CD_S_ALT_EN (0x1 << 10)
116#define I2CD_RX_DMA_ENABLE (0x1 << 9)
117#define I2CD_TX_DMA_ENABLE (0x1 << 8)
118
119/* Command Bit */
120#define I2CD_M_STOP_CMD (0x1 << 5)
121#define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
122#define I2CD_M_RX_CMD (0x1 << 3)
123#define I2CD_S_TX_CMD (0x1 << 2)
124#define I2CD_M_TX_CMD (0x1 << 1)
125#define I2CD_M_START_CMD (0x1)
126
127#define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */
128#define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */
129#define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */
130#define I2CD_BYTE_BUF_TX_SHIFT 0
131#define I2CD_BYTE_BUF_TX_MASK 0xff
132#define I2CD_BYTE_BUF_RX_SHIFT 8
133#define I2CD_BYTE_BUF_RX_MASK 0xff
134
135
136static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
137{
138 return bus->ctrl & I2CD_MASTER_EN;
139}
140
141static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
142{
143 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
144}
145
146static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
147{
148 bus->intr_status &= bus->intr_ctrl;
149 if (bus->intr_status) {
150 bus->controller->intr_status |= 1 << bus->id;
151 qemu_irq_raise(bus->controller->irq);
152 }
153}
154
155static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
156 unsigned size)
157{
158 AspeedI2CBus *bus = opaque;
159
160 switch (offset) {
161 case I2CD_FUN_CTRL_REG:
162 return bus->ctrl;
163 case I2CD_AC_TIMING_REG1:
164 return bus->timing[0];
165 case I2CD_AC_TIMING_REG2:
166 return bus->timing[1];
167 case I2CD_INTR_CTRL_REG:
168 return bus->intr_ctrl;
169 case I2CD_INTR_STS_REG:
170 return bus->intr_status;
171 case I2CD_BYTE_BUF_REG:
172 return bus->buf;
173 case I2CD_CMD_REG:
174 return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
175 default:
176 qemu_log_mask(LOG_GUEST_ERROR,
177 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
178 return -1;
179 }
180}
181
182static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
183{
184 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
185 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
186}
187
188static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
189{
190 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
191}
192
193static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
194{
195 uint8_t ret;
196
197 aspeed_i2c_set_state(bus, I2CD_MRXD);
198 ret = i2c_recv(bus->bus);
199 bus->intr_status |= I2CD_INTR_RX_DONE;
200 bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
201 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
202 i2c_nack(bus->bus);
203 }
204 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
205 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
206}
207
208/*
209 * The state machine needs some refinement. It is only used to track
210 * invalid STOP commands for the moment.
211 */
212static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
213{
214 bus->cmd &= ~0xFFFF;
215 bus->cmd |= value & 0xFFFF;
216
217 if (bus->cmd & I2CD_M_START_CMD) {
218 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
219 I2CD_MSTARTR : I2CD_MSTART;
220
221 aspeed_i2c_set_state(bus, state);
222
223 if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
224 extract32(bus->buf, 0, 1))) {
225 bus->intr_status |= I2CD_INTR_TX_NAK;
226 } else {
227 bus->intr_status |= I2CD_INTR_TX_ACK;
228 }
229
230 /* START command is also a TX command, as the slave address is
231 * sent on the bus */
232 bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
233
234 /* No slave found */
235 if (!i2c_bus_busy(bus->bus)) {
236 return;
237 }
238 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
239 }
240
241 if (bus->cmd & I2CD_M_TX_CMD) {
242 aspeed_i2c_set_state(bus, I2CD_MTXD);
243 if (i2c_send(bus->bus, bus->buf)) {
244 bus->intr_status |= (I2CD_INTR_TX_NAK);
245 i2c_end_transfer(bus->bus);
246 } else {
247 bus->intr_status |= I2CD_INTR_TX_ACK;
248 }
249 bus->cmd &= ~I2CD_M_TX_CMD;
250 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
251 }
252
253 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
254 !(bus->intr_status & I2CD_INTR_RX_DONE)) {
255 aspeed_i2c_handle_rx_cmd(bus);
256 }
257
258 if (bus->cmd & I2CD_M_STOP_CMD) {
259 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
260 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
261 bus->intr_status |= I2CD_INTR_ABNORMAL;
262 } else {
263 aspeed_i2c_set_state(bus, I2CD_MSTOP);
264 i2c_end_transfer(bus->bus);
265 bus->intr_status |= I2CD_INTR_NORMAL_STOP;
266 }
267 bus->cmd &= ~I2CD_M_STOP_CMD;
268 aspeed_i2c_set_state(bus, I2CD_IDLE);
269 }
270}
271
272static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
273 uint64_t value, unsigned size)
274{
275 AspeedI2CBus *bus = opaque;
276 bool handle_rx;
277
278 switch (offset) {
279 case I2CD_FUN_CTRL_REG:
280 if (value & I2CD_SLAVE_EN) {
281 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
282 __func__);
283 break;
284 }
285 bus->ctrl = value & 0x0071C3FF;
286 break;
287 case I2CD_AC_TIMING_REG1:
288 bus->timing[0] = value & 0xFFFFF0F;
289 break;
290 case I2CD_AC_TIMING_REG2:
291 bus->timing[1] = value & 0x7;
292 break;
293 case I2CD_INTR_CTRL_REG:
294 bus->intr_ctrl = value & 0x7FFF;
295 break;
296 case I2CD_INTR_STS_REG:
297 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
298 (value & I2CD_INTR_RX_DONE);
299 bus->intr_status &= ~(value & 0x7FFF);
300 if (!bus->intr_status) {
301 bus->controller->intr_status &= ~(1 << bus->id);
302 qemu_irq_lower(bus->controller->irq);
303 }
304 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
305 aspeed_i2c_handle_rx_cmd(bus);
306 aspeed_i2c_bus_raise_interrupt(bus);
307 }
308 break;
309 case I2CD_DEV_ADDR_REG:
310 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
311 __func__);
312 break;
313 case I2CD_BYTE_BUF_REG:
314 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
315 break;
316 case I2CD_CMD_REG:
317 if (!aspeed_i2c_bus_is_enabled(bus)) {
318 break;
319 }
320
321 if (!aspeed_i2c_bus_is_master(bus)) {
322 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
323 __func__);
324 break;
325 }
326
327 aspeed_i2c_bus_handle_cmd(bus, value);
328 aspeed_i2c_bus_raise_interrupt(bus);
329 break;
330
331 default:
332 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
333 __func__, offset);
334 }
335}
336
337static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
338 unsigned size)
339{
340 AspeedI2CState *s = opaque;
341
342 switch (offset) {
343 case I2C_CTRL_STATUS:
344 return s->intr_status;
345 default:
346 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
347 __func__, offset);
348 break;
349 }
350
351 return -1;
352}
353
354static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
355 uint64_t value, unsigned size)
356{
357 switch (offset) {
358 case I2C_CTRL_STATUS:
359 default:
360 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
361 __func__, offset);
362 break;
363 }
364}
365
366static const MemoryRegionOps aspeed_i2c_bus_ops = {
367 .read = aspeed_i2c_bus_read,
368 .write = aspeed_i2c_bus_write,
369 .endianness = DEVICE_LITTLE_ENDIAN,
370};
371
372static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
373 .read = aspeed_i2c_ctrl_read,
374 .write = aspeed_i2c_ctrl_write,
375 .endianness = DEVICE_LITTLE_ENDIAN,
376};
377
378static const VMStateDescription aspeed_i2c_bus_vmstate = {
379 .name = TYPE_ASPEED_I2C,
380 .version_id = 1,
381 .minimum_version_id = 1,
382 .fields = (VMStateField[]) {
383 VMSTATE_UINT8(id, AspeedI2CBus),
384 VMSTATE_UINT32(ctrl, AspeedI2CBus),
385 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
386 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
387 VMSTATE_UINT32(intr_status, AspeedI2CBus),
388 VMSTATE_UINT32(cmd, AspeedI2CBus),
389 VMSTATE_UINT32(buf, AspeedI2CBus),
390 VMSTATE_END_OF_LIST()
391 }
392};
393
394static const VMStateDescription aspeed_i2c_vmstate = {
395 .name = TYPE_ASPEED_I2C,
396 .version_id = 1,
397 .minimum_version_id = 1,
398 .fields = (VMStateField[]) {
399 VMSTATE_UINT32(intr_status, AspeedI2CState),
400 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
401 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
402 AspeedI2CBus),
403 VMSTATE_END_OF_LIST()
404 }
405};
406
407static void aspeed_i2c_reset(DeviceState *dev)
408{
409 int i;
410 AspeedI2CState *s = ASPEED_I2C(dev);
411
412 s->intr_status = 0;
413
414 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
415 s->busses[i].intr_ctrl = 0;
416 s->busses[i].intr_status = 0;
417 s->busses[i].cmd = 0;
418 s->busses[i].buf = 0;
419 i2c_end_transfer(s->busses[i].bus);
420 }
421}
422
423/*
424 * Address Definitions
425 *
426 * 0x000 ... 0x03F: Global Register
427 * 0x040 ... 0x07F: Device 1
428 * 0x080 ... 0x0BF: Device 2
429 * 0x0C0 ... 0x0FF: Device 3
430 * 0x100 ... 0x13F: Device 4
431 * 0x140 ... 0x17F: Device 5
432 * 0x180 ... 0x1BF: Device 6
433 * 0x1C0 ... 0x1FF: Device 7
434 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver)
435 * 0x300 ... 0x33F: Device 8
436 * 0x340 ... 0x37F: Device 9
437 * 0x380 ... 0x3BF: Device 10
438 * 0x3C0 ... 0x3FF: Device 11
439 * 0x400 ... 0x43F: Device 12
440 * 0x440 ... 0x47F: Device 13
441 * 0x480 ... 0x4BF: Device 14
442 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver)
443 */
444static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
445{
446 int i;
447 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
448 AspeedI2CState *s = ASPEED_I2C(dev);
449
450 sysbus_init_irq(sbd, &s->irq);
451 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
452 "aspeed.i2c", 0x1000);
453 sysbus_init_mmio(sbd, &s->iomem);
454
455 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
456 char name[16];
457 int offset = i < 7 ? 1 : 5;
458 snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
459 s->busses[i].controller = s;
460 s->busses[i].id = i;
461 s->busses[i].bus = i2c_init_bus(dev, name);
462 memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
463 &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
464 memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
465 &s->busses[i].mr);
466 }
467}
468
469static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
470{
471 DeviceClass *dc = DEVICE_CLASS(klass);
472
473 dc->vmsd = &aspeed_i2c_vmstate;
474 dc->reset = aspeed_i2c_reset;
475 dc->realize = aspeed_i2c_realize;
476 dc->desc = "Aspeed I2C Controller";
477}
478
479static const TypeInfo aspeed_i2c_info = {
480 .name = TYPE_ASPEED_I2C,
481 .parent = TYPE_SYS_BUS_DEVICE,
482 .instance_size = sizeof(AspeedI2CState),
483 .class_init = aspeed_i2c_class_init,
484};
485
486static void aspeed_i2c_register_types(void)
487{
488 type_register_static(&aspeed_i2c_info);
489}
490
491type_init(aspeed_i2c_register_types)
492
493
494I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
495{
496 AspeedI2CState *s = ASPEED_I2C(dev);
497 I2CBus *bus = NULL;
498
499 if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
500 bus = s->busses[busnr].bus;
501 }
502
503 return bus;
504}
505