1 | /* |
2 | * QEMU PC keyboard emulation |
3 | * |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qemu/log.h" |
27 | #include "hw/isa/isa.h" |
28 | #include "migration/vmstate.h" |
29 | #include "hw/i386/pc.h" |
30 | #include "hw/input/ps2.h" |
31 | #include "hw/irq.h" |
32 | #include "hw/input/i8042.h" |
33 | #include "sysemu/reset.h" |
34 | #include "sysemu/runstate.h" |
35 | |
36 | #include "trace.h" |
37 | |
38 | /* Keyboard Controller Commands */ |
39 | #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ |
40 | #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ |
41 | #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ |
42 | #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ |
43 | #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ |
44 | #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ |
45 | #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ |
46 | #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ |
47 | #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ |
48 | #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ |
49 | #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ |
50 | #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ |
51 | #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ |
52 | #define KBD_CCMD_WRITE_OBUF 0xD2 |
53 | #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if |
54 | initiated by the auxiliary device */ |
55 | #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ |
56 | #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ |
57 | #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ |
58 | #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */ |
59 | #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */ |
60 | #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */ |
61 | |
62 | /* Keyboard Commands */ |
63 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
64 | #define KBD_CMD_ECHO 0xEE |
65 | #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ |
66 | #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ |
67 | #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ |
68 | #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ |
69 | #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ |
70 | #define KBD_CMD_RESET 0xFF /* Reset */ |
71 | |
72 | /* Keyboard Replies */ |
73 | #define KBD_REPLY_POR 0xAA /* Power on reset */ |
74 | #define KBD_REPLY_ACK 0xFA /* Command ACK */ |
75 | #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ |
76 | |
77 | /* Status Register Bits */ |
78 | #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ |
79 | #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ |
80 | #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ |
81 | #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ |
82 | #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ |
83 | #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ |
84 | #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ |
85 | #define KBD_STAT_PERR 0x80 /* Parity error */ |
86 | |
87 | /* Controller Mode Register Bits */ |
88 | #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ |
89 | #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ |
90 | #define KBD_MODE_SYS 0x04 /* The system flag (?) */ |
91 | #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ |
92 | #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ |
93 | #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ |
94 | #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ |
95 | #define KBD_MODE_RFU 0x80 |
96 | |
97 | /* Output Port Bits */ |
98 | #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */ |
99 | #define KBD_OUT_A20 0x02 /* x86 only */ |
100 | #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ |
101 | #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ |
102 | |
103 | /* OSes typically write 0xdd/0xdf to turn the A20 line off and on. |
104 | * We make the default value of the outport include these four bits, |
105 | * so that the subsection is rarely necessary. |
106 | */ |
107 | #define KBD_OUT_ONES 0xcc |
108 | |
109 | /* Mouse Commands */ |
110 | #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ |
111 | #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ |
112 | #define AUX_SET_RES 0xE8 /* Set resolution */ |
113 | #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ |
114 | #define AUX_SET_STREAM 0xEA /* Set stream mode */ |
115 | #define AUX_POLL 0xEB /* Poll */ |
116 | #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ |
117 | #define AUX_SET_WRAP 0xEE /* Set wrap mode */ |
118 | #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ |
119 | #define AUX_GET_TYPE 0xF2 /* Get type */ |
120 | #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ |
121 | #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ |
122 | #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ |
123 | #define AUX_SET_DEFAULT 0xF6 |
124 | #define AUX_RESET 0xFF /* Reset aux device */ |
125 | #define AUX_ACK 0xFA /* Command byte ACK. */ |
126 | |
127 | #define MOUSE_STATUS_REMOTE 0x40 |
128 | #define MOUSE_STATUS_ENABLED 0x20 |
129 | #define MOUSE_STATUS_SCALE21 0x10 |
130 | |
131 | #define KBD_PENDING_KBD 1 |
132 | #define KBD_PENDING_AUX 2 |
133 | |
134 | typedef struct KBDState { |
135 | uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ |
136 | uint8_t status; |
137 | uint8_t mode; |
138 | uint8_t outport; |
139 | bool outport_present; |
140 | /* Bitmask of devices with data available. */ |
141 | uint8_t pending; |
142 | void *kbd; |
143 | void *mouse; |
144 | |
145 | qemu_irq irq_kbd; |
146 | qemu_irq irq_mouse; |
147 | qemu_irq a20_out; |
148 | hwaddr mask; |
149 | } KBDState; |
150 | |
151 | /* update irq and KBD_STAT_[MOUSE_]OBF */ |
152 | /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be |
153 | incorrect, but it avoids having to simulate exact delays */ |
154 | static void kbd_update_irq(KBDState *s) |
155 | { |
156 | int irq_kbd_level, irq_mouse_level; |
157 | |
158 | irq_kbd_level = 0; |
159 | irq_mouse_level = 0; |
160 | s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); |
161 | s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF); |
162 | if (s->pending) { |
163 | s->status |= KBD_STAT_OBF; |
164 | s->outport |= KBD_OUT_OBF; |
165 | /* kbd data takes priority over aux data. */ |
166 | if (s->pending == KBD_PENDING_AUX) { |
167 | s->status |= KBD_STAT_MOUSE_OBF; |
168 | s->outport |= KBD_OUT_MOUSE_OBF; |
169 | if (s->mode & KBD_MODE_MOUSE_INT) |
170 | irq_mouse_level = 1; |
171 | } else { |
172 | if ((s->mode & KBD_MODE_KBD_INT) && |
173 | !(s->mode & KBD_MODE_DISABLE_KBD)) |
174 | irq_kbd_level = 1; |
175 | } |
176 | } |
177 | qemu_set_irq(s->irq_kbd, irq_kbd_level); |
178 | qemu_set_irq(s->irq_mouse, irq_mouse_level); |
179 | } |
180 | |
181 | static void kbd_update_kbd_irq(void *opaque, int level) |
182 | { |
183 | KBDState *s = (KBDState *)opaque; |
184 | |
185 | if (level) |
186 | s->pending |= KBD_PENDING_KBD; |
187 | else |
188 | s->pending &= ~KBD_PENDING_KBD; |
189 | kbd_update_irq(s); |
190 | } |
191 | |
192 | static void kbd_update_aux_irq(void *opaque, int level) |
193 | { |
194 | KBDState *s = (KBDState *)opaque; |
195 | |
196 | if (level) |
197 | s->pending |= KBD_PENDING_AUX; |
198 | else |
199 | s->pending &= ~KBD_PENDING_AUX; |
200 | kbd_update_irq(s); |
201 | } |
202 | |
203 | static uint64_t kbd_read_status(void *opaque, hwaddr addr, |
204 | unsigned size) |
205 | { |
206 | KBDState *s = opaque; |
207 | int val; |
208 | val = s->status; |
209 | trace_pckbd_kbd_read_status(val); |
210 | return val; |
211 | } |
212 | |
213 | static void kbd_queue(KBDState *s, int b, int aux) |
214 | { |
215 | if (aux) |
216 | ps2_queue(s->mouse, b); |
217 | else |
218 | ps2_queue(s->kbd, b); |
219 | } |
220 | |
221 | static void outport_write(KBDState *s, uint32_t val) |
222 | { |
223 | trace_pckbd_outport_write(val); |
224 | s->outport = val; |
225 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
226 | if (!(val & 1)) { |
227 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
228 | } |
229 | } |
230 | |
231 | static void kbd_write_command(void *opaque, hwaddr addr, |
232 | uint64_t val, unsigned size) |
233 | { |
234 | KBDState *s = opaque; |
235 | |
236 | trace_pckbd_kbd_write_command(val); |
237 | |
238 | /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed |
239 | * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE |
240 | * command specify the output port bits to be pulsed. |
241 | * 0: Bit should be pulsed. 1: Bit should not be modified. |
242 | * The only useful version of this command is pulsing bit 0, |
243 | * which does a CPU reset. |
244 | */ |
245 | if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) { |
246 | if(!(val & 1)) |
247 | val = KBD_CCMD_RESET; |
248 | else |
249 | val = KBD_CCMD_NO_OP; |
250 | } |
251 | |
252 | switch(val) { |
253 | case KBD_CCMD_READ_MODE: |
254 | kbd_queue(s, s->mode, 0); |
255 | break; |
256 | case KBD_CCMD_WRITE_MODE: |
257 | case KBD_CCMD_WRITE_OBUF: |
258 | case KBD_CCMD_WRITE_AUX_OBUF: |
259 | case KBD_CCMD_WRITE_MOUSE: |
260 | case KBD_CCMD_WRITE_OUTPORT: |
261 | s->write_cmd = val; |
262 | break; |
263 | case KBD_CCMD_MOUSE_DISABLE: |
264 | s->mode |= KBD_MODE_DISABLE_MOUSE; |
265 | break; |
266 | case KBD_CCMD_MOUSE_ENABLE: |
267 | s->mode &= ~KBD_MODE_DISABLE_MOUSE; |
268 | break; |
269 | case KBD_CCMD_TEST_MOUSE: |
270 | kbd_queue(s, 0x00, 0); |
271 | break; |
272 | case KBD_CCMD_SELF_TEST: |
273 | s->status |= KBD_STAT_SELFTEST; |
274 | kbd_queue(s, 0x55, 0); |
275 | break; |
276 | case KBD_CCMD_KBD_TEST: |
277 | kbd_queue(s, 0x00, 0); |
278 | break; |
279 | case KBD_CCMD_KBD_DISABLE: |
280 | s->mode |= KBD_MODE_DISABLE_KBD; |
281 | kbd_update_irq(s); |
282 | break; |
283 | case KBD_CCMD_KBD_ENABLE: |
284 | s->mode &= ~KBD_MODE_DISABLE_KBD; |
285 | kbd_update_irq(s); |
286 | break; |
287 | case KBD_CCMD_READ_INPORT: |
288 | kbd_queue(s, 0x80, 0); |
289 | break; |
290 | case KBD_CCMD_READ_OUTPORT: |
291 | kbd_queue(s, s->outport, 0); |
292 | break; |
293 | case KBD_CCMD_ENABLE_A20: |
294 | qemu_irq_raise(s->a20_out); |
295 | s->outport |= KBD_OUT_A20; |
296 | break; |
297 | case KBD_CCMD_DISABLE_A20: |
298 | qemu_irq_lower(s->a20_out); |
299 | s->outport &= ~KBD_OUT_A20; |
300 | break; |
301 | case KBD_CCMD_RESET: |
302 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
303 | break; |
304 | case KBD_CCMD_NO_OP: |
305 | /* ignore that */ |
306 | break; |
307 | default: |
308 | qemu_log_mask(LOG_GUEST_ERROR, |
309 | "unsupported keyboard cmd=0x%02" PRIx64 "\n" , val); |
310 | break; |
311 | } |
312 | } |
313 | |
314 | static uint64_t kbd_read_data(void *opaque, hwaddr addr, |
315 | unsigned size) |
316 | { |
317 | KBDState *s = opaque; |
318 | uint32_t val; |
319 | |
320 | if (s->pending == KBD_PENDING_AUX) |
321 | val = ps2_read_data(s->mouse); |
322 | else |
323 | val = ps2_read_data(s->kbd); |
324 | |
325 | trace_pckbd_kbd_read_data(val); |
326 | return val; |
327 | } |
328 | |
329 | static void kbd_write_data(void *opaque, hwaddr addr, |
330 | uint64_t val, unsigned size) |
331 | { |
332 | KBDState *s = opaque; |
333 | |
334 | trace_pckbd_kbd_write_data(val); |
335 | |
336 | switch(s->write_cmd) { |
337 | case 0: |
338 | ps2_write_keyboard(s->kbd, val); |
339 | break; |
340 | case KBD_CCMD_WRITE_MODE: |
341 | s->mode = val; |
342 | ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0); |
343 | /* ??? */ |
344 | kbd_update_irq(s); |
345 | break; |
346 | case KBD_CCMD_WRITE_OBUF: |
347 | kbd_queue(s, val, 0); |
348 | break; |
349 | case KBD_CCMD_WRITE_AUX_OBUF: |
350 | kbd_queue(s, val, 1); |
351 | break; |
352 | case KBD_CCMD_WRITE_OUTPORT: |
353 | outport_write(s, val); |
354 | break; |
355 | case KBD_CCMD_WRITE_MOUSE: |
356 | ps2_write_mouse(s->mouse, val); |
357 | break; |
358 | default: |
359 | break; |
360 | } |
361 | s->write_cmd = 0; |
362 | } |
363 | |
364 | static void kbd_reset(void *opaque) |
365 | { |
366 | KBDState *s = opaque; |
367 | |
368 | s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
369 | s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; |
370 | s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES; |
371 | s->outport_present = false; |
372 | } |
373 | |
374 | static uint8_t kbd_outport_default(KBDState *s) |
375 | { |
376 | return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES |
377 | | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) |
378 | | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); |
379 | } |
380 | |
381 | static int kbd_outport_post_load(void *opaque, int version_id) |
382 | { |
383 | KBDState *s = opaque; |
384 | s->outport_present = true; |
385 | return 0; |
386 | } |
387 | |
388 | static bool kbd_outport_needed(void *opaque) |
389 | { |
390 | KBDState *s = opaque; |
391 | return s->outport != kbd_outport_default(s); |
392 | } |
393 | |
394 | static const VMStateDescription vmstate_kbd_outport = { |
395 | .name = "pckbd_outport" , |
396 | .version_id = 1, |
397 | .minimum_version_id = 1, |
398 | .post_load = kbd_outport_post_load, |
399 | .needed = kbd_outport_needed, |
400 | .fields = (VMStateField[]) { |
401 | VMSTATE_UINT8(outport, KBDState), |
402 | VMSTATE_END_OF_LIST() |
403 | } |
404 | }; |
405 | |
406 | static int kbd_post_load(void *opaque, int version_id) |
407 | { |
408 | KBDState *s = opaque; |
409 | if (!s->outport_present) { |
410 | s->outport = kbd_outport_default(s); |
411 | } |
412 | s->outport_present = false; |
413 | return 0; |
414 | } |
415 | |
416 | static const VMStateDescription vmstate_kbd = { |
417 | .name = "pckbd" , |
418 | .version_id = 3, |
419 | .minimum_version_id = 3, |
420 | .post_load = kbd_post_load, |
421 | .fields = (VMStateField[]) { |
422 | VMSTATE_UINT8(write_cmd, KBDState), |
423 | VMSTATE_UINT8(status, KBDState), |
424 | VMSTATE_UINT8(mode, KBDState), |
425 | VMSTATE_UINT8(pending, KBDState), |
426 | VMSTATE_END_OF_LIST() |
427 | }, |
428 | .subsections = (const VMStateDescription*[]) { |
429 | &vmstate_kbd_outport, |
430 | NULL |
431 | } |
432 | }; |
433 | |
434 | /* Memory mapped interface */ |
435 | static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size) |
436 | { |
437 | KBDState *s = opaque; |
438 | |
439 | if (addr & s->mask) |
440 | return kbd_read_status(s, 0, 1) & 0xff; |
441 | else |
442 | return kbd_read_data(s, 0, 1) & 0xff; |
443 | } |
444 | |
445 | static void kbd_mm_writefn(void *opaque, hwaddr addr, |
446 | uint64_t value, unsigned size) |
447 | { |
448 | KBDState *s = opaque; |
449 | |
450 | if (addr & s->mask) |
451 | kbd_write_command(s, 0, value & 0xff, 1); |
452 | else |
453 | kbd_write_data(s, 0, value & 0xff, 1); |
454 | } |
455 | |
456 | |
457 | static const MemoryRegionOps i8042_mmio_ops = { |
458 | .read = kbd_mm_readfn, |
459 | .write = kbd_mm_writefn, |
460 | .valid.min_access_size = 1, |
461 | .valid.max_access_size = 4, |
462 | .endianness = DEVICE_NATIVE_ENDIAN, |
463 | }; |
464 | |
465 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, |
466 | MemoryRegion *region, ram_addr_t size, |
467 | hwaddr mask) |
468 | { |
469 | KBDState *s = g_malloc0(sizeof(KBDState)); |
470 | |
471 | s->irq_kbd = kbd_irq; |
472 | s->irq_mouse = mouse_irq; |
473 | s->mask = mask; |
474 | |
475 | vmstate_register(NULL, 0, &vmstate_kbd, s); |
476 | |
477 | memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042" , size); |
478 | |
479 | s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); |
480 | s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); |
481 | qemu_register_reset(kbd_reset, s); |
482 | } |
483 | |
484 | #define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042) |
485 | |
486 | typedef struct ISAKBDState { |
487 | ISADevice parent_obj; |
488 | |
489 | KBDState kbd; |
490 | MemoryRegion io[2]; |
491 | } ISAKBDState; |
492 | |
493 | void i8042_isa_mouse_fake_event(void *opaque) |
494 | { |
495 | ISADevice *dev = opaque; |
496 | ISAKBDState *isa = I8042(dev); |
497 | KBDState *s = &isa->kbd; |
498 | |
499 | ps2_mouse_fake_event(s->mouse); |
500 | } |
501 | |
502 | void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out) |
503 | { |
504 | qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out); |
505 | } |
506 | |
507 | static const VMStateDescription vmstate_kbd_isa = { |
508 | .name = "pckbd" , |
509 | .version_id = 3, |
510 | .minimum_version_id = 3, |
511 | .fields = (VMStateField[]) { |
512 | VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState), |
513 | VMSTATE_END_OF_LIST() |
514 | } |
515 | }; |
516 | |
517 | static const MemoryRegionOps i8042_data_ops = { |
518 | .read = kbd_read_data, |
519 | .write = kbd_write_data, |
520 | .impl = { |
521 | .min_access_size = 1, |
522 | .max_access_size = 1, |
523 | }, |
524 | .endianness = DEVICE_LITTLE_ENDIAN, |
525 | }; |
526 | |
527 | static const MemoryRegionOps i8042_cmd_ops = { |
528 | .read = kbd_read_status, |
529 | .write = kbd_write_command, |
530 | .impl = { |
531 | .min_access_size = 1, |
532 | .max_access_size = 1, |
533 | }, |
534 | .endianness = DEVICE_LITTLE_ENDIAN, |
535 | }; |
536 | |
537 | static void i8042_initfn(Object *obj) |
538 | { |
539 | ISAKBDState *isa_s = I8042(obj); |
540 | KBDState *s = &isa_s->kbd; |
541 | |
542 | memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s, |
543 | "i8042-data" , 1); |
544 | memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s, |
545 | "i8042-cmd" , 1); |
546 | |
547 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1); |
548 | } |
549 | |
550 | static void i8042_realizefn(DeviceState *dev, Error **errp) |
551 | { |
552 | ISADevice *isadev = ISA_DEVICE(dev); |
553 | ISAKBDState *isa_s = I8042(dev); |
554 | KBDState *s = &isa_s->kbd; |
555 | |
556 | isa_init_irq(isadev, &s->irq_kbd, 1); |
557 | isa_init_irq(isadev, &s->irq_mouse, 12); |
558 | |
559 | isa_register_ioport(isadev, isa_s->io + 0, 0x60); |
560 | isa_register_ioport(isadev, isa_s->io + 1, 0x64); |
561 | |
562 | s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); |
563 | s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); |
564 | qemu_register_reset(kbd_reset, s); |
565 | } |
566 | |
567 | static void i8042_class_initfn(ObjectClass *klass, void *data) |
568 | { |
569 | DeviceClass *dc = DEVICE_CLASS(klass); |
570 | |
571 | dc->realize = i8042_realizefn; |
572 | dc->vmsd = &vmstate_kbd_isa; |
573 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
574 | } |
575 | |
576 | static const TypeInfo i8042_info = { |
577 | .name = TYPE_I8042, |
578 | .parent = TYPE_ISA_DEVICE, |
579 | .instance_size = sizeof(ISAKBDState), |
580 | .instance_init = i8042_initfn, |
581 | .class_init = i8042_class_initfn, |
582 | }; |
583 | |
584 | static void i8042_register_types(void) |
585 | { |
586 | type_register_static(&i8042_info); |
587 | } |
588 | |
589 | type_init(i8042_register_types) |
590 | |