1 | /* |
2 | * Allwinner A10 interrupt controller device emulation |
3 | * |
4 | * Copyright (C) 2013 Li Guang |
5 | * Written by Li Guang <lig.fnst@cn.fujitsu.com> |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License as published by the |
9 | * Free Software Foundation; either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
15 | * for more details. |
16 | */ |
17 | |
18 | #include "qemu/osdep.h" |
19 | #include "hw/sysbus.h" |
20 | #include "migration/vmstate.h" |
21 | #include "hw/intc/allwinner-a10-pic.h" |
22 | #include "hw/irq.h" |
23 | #include "qemu/log.h" |
24 | #include "qemu/module.h" |
25 | |
26 | static void aw_a10_pic_update(AwA10PICState *s) |
27 | { |
28 | uint8_t i; |
29 | int irq = 0, fiq = 0, zeroes; |
30 | |
31 | s->vector = 0; |
32 | |
33 | for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { |
34 | irq |= s->irq_pending[i] & ~s->mask[i]; |
35 | fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; |
36 | |
37 | if (!s->vector) { |
38 | zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]); |
39 | if (zeroes != 32) { |
40 | s->vector = (i * 32 + zeroes) * 4; |
41 | } |
42 | } |
43 | } |
44 | |
45 | qemu_set_irq(s->parent_irq, !!irq); |
46 | qemu_set_irq(s->parent_fiq, !!fiq); |
47 | } |
48 | |
49 | static void aw_a10_pic_set_irq(void *opaque, int irq, int level) |
50 | { |
51 | AwA10PICState *s = opaque; |
52 | |
53 | if (level) { |
54 | set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); |
55 | } else { |
56 | clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); |
57 | } |
58 | aw_a10_pic_update(s); |
59 | } |
60 | |
61 | static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size) |
62 | { |
63 | AwA10PICState *s = opaque; |
64 | uint8_t index = (offset & 0xc) / 4; |
65 | |
66 | switch (offset) { |
67 | case AW_A10_PIC_VECTOR: |
68 | return s->vector; |
69 | case AW_A10_PIC_BASE_ADDR: |
70 | return s->base_addr; |
71 | case AW_A10_PIC_PROTECT: |
72 | return s->protect; |
73 | case AW_A10_PIC_NMI: |
74 | return s->nmi; |
75 | case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: |
76 | return s->irq_pending[index]; |
77 | case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: |
78 | return s->fiq_pending[index]; |
79 | case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: |
80 | return s->select[index]; |
81 | case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: |
82 | return s->enable[index]; |
83 | case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: |
84 | return s->mask[index]; |
85 | default: |
86 | qemu_log_mask(LOG_GUEST_ERROR, |
87 | "%s: Bad offset 0x%x\n" , __func__, (int)offset); |
88 | break; |
89 | } |
90 | |
91 | return 0; |
92 | } |
93 | |
94 | static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, |
95 | unsigned size) |
96 | { |
97 | AwA10PICState *s = opaque; |
98 | uint8_t index = (offset & 0xc) / 4; |
99 | |
100 | switch (offset) { |
101 | case AW_A10_PIC_BASE_ADDR: |
102 | s->base_addr = value & ~0x3; |
103 | break; |
104 | case AW_A10_PIC_PROTECT: |
105 | s->protect = value; |
106 | break; |
107 | case AW_A10_PIC_NMI: |
108 | s->nmi = value; |
109 | break; |
110 | case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: |
111 | /* |
112 | * The register is read-only; nevertheless, Linux (including |
113 | * the version originally shipped by Allwinner) pretends to |
114 | * write to the register. Just ignore it. |
115 | */ |
116 | break; |
117 | case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: |
118 | s->fiq_pending[index] &= ~value; |
119 | break; |
120 | case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8: |
121 | s->select[index] = value; |
122 | break; |
123 | case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8: |
124 | s->enable[index] = value; |
125 | break; |
126 | case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8: |
127 | s->mask[index] = value; |
128 | break; |
129 | default: |
130 | qemu_log_mask(LOG_GUEST_ERROR, |
131 | "%s: Bad offset 0x%x\n" , __func__, (int)offset); |
132 | break; |
133 | } |
134 | |
135 | aw_a10_pic_update(s); |
136 | } |
137 | |
138 | static const MemoryRegionOps aw_a10_pic_ops = { |
139 | .read = aw_a10_pic_read, |
140 | .write = aw_a10_pic_write, |
141 | .endianness = DEVICE_NATIVE_ENDIAN, |
142 | }; |
143 | |
144 | static const VMStateDescription vmstate_aw_a10_pic = { |
145 | .name = "a10.pic" , |
146 | .version_id = 1, |
147 | .minimum_version_id = 1, |
148 | .fields = (VMStateField[]) { |
149 | VMSTATE_UINT32(vector, AwA10PICState), |
150 | VMSTATE_UINT32(base_addr, AwA10PICState), |
151 | VMSTATE_UINT32(protect, AwA10PICState), |
152 | VMSTATE_UINT32(nmi, AwA10PICState), |
153 | VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), |
154 | VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM), |
155 | VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM), |
156 | VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM), |
157 | VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM), |
158 | VMSTATE_END_OF_LIST() |
159 | } |
160 | }; |
161 | |
162 | static void aw_a10_pic_init(Object *obj) |
163 | { |
164 | AwA10PICState *s = AW_A10_PIC(obj); |
165 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
166 | |
167 | qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR); |
168 | sysbus_init_irq(dev, &s->parent_irq); |
169 | sysbus_init_irq(dev, &s->parent_fiq); |
170 | memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s, |
171 | TYPE_AW_A10_PIC, 0x400); |
172 | sysbus_init_mmio(dev, &s->iomem); |
173 | } |
174 | |
175 | static void aw_a10_pic_reset(DeviceState *d) |
176 | { |
177 | AwA10PICState *s = AW_A10_PIC(d); |
178 | uint8_t i; |
179 | |
180 | s->base_addr = 0; |
181 | s->protect = 0; |
182 | s->nmi = 0; |
183 | s->vector = 0; |
184 | for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { |
185 | s->irq_pending[i] = 0; |
186 | s->fiq_pending[i] = 0; |
187 | s->select[i] = 0; |
188 | s->enable[i] = 0; |
189 | s->mask[i] = 0; |
190 | } |
191 | } |
192 | |
193 | static void aw_a10_pic_class_init(ObjectClass *klass, void *data) |
194 | { |
195 | DeviceClass *dc = DEVICE_CLASS(klass); |
196 | |
197 | dc->reset = aw_a10_pic_reset; |
198 | dc->desc = "allwinner a10 pic" ; |
199 | dc->vmsd = &vmstate_aw_a10_pic; |
200 | } |
201 | |
202 | static const TypeInfo aw_a10_pic_info = { |
203 | .name = TYPE_AW_A10_PIC, |
204 | .parent = TYPE_SYS_BUS_DEVICE, |
205 | .instance_size = sizeof(AwA10PICState), |
206 | .instance_init = aw_a10_pic_init, |
207 | .class_init = aw_a10_pic_class_init, |
208 | }; |
209 | |
210 | static void aw_a10_register_types(void) |
211 | { |
212 | type_register_static(&aw_a10_pic_info); |
213 | } |
214 | |
215 | type_init(aw_a10_register_types); |
216 | |