1 | /* |
2 | * ITS base class for a GICv3-based system |
3 | * |
4 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
5 | * Written by Pavel Fedin |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by |
9 | * the Free Software Foundation, either version 2 of the License, or |
10 | * (at your option) any later version. |
11 | * |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
15 | * GNU General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU General Public License along |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
19 | */ |
20 | |
21 | #include "qemu/osdep.h" |
22 | #include "hw/pci/msi.h" |
23 | #include "migration/vmstate.h" |
24 | #include "hw/intc/arm_gicv3_its_common.h" |
25 | #include "qemu/log.h" |
26 | #include "qemu/module.h" |
27 | |
28 | static int gicv3_its_pre_save(void *opaque) |
29 | { |
30 | GICv3ITSState *s = (GICv3ITSState *)opaque; |
31 | GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); |
32 | |
33 | if (c->pre_save) { |
34 | c->pre_save(s); |
35 | } |
36 | |
37 | return 0; |
38 | } |
39 | |
40 | static int gicv3_its_post_load(void *opaque, int version_id) |
41 | { |
42 | GICv3ITSState *s = (GICv3ITSState *)opaque; |
43 | GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); |
44 | |
45 | if (c->post_load) { |
46 | c->post_load(s); |
47 | } |
48 | return 0; |
49 | } |
50 | |
51 | static const VMStateDescription vmstate_its = { |
52 | .name = "arm_gicv3_its" , |
53 | .pre_save = gicv3_its_pre_save, |
54 | .post_load = gicv3_its_post_load, |
55 | .priority = MIG_PRI_GICV3_ITS, |
56 | .fields = (VMStateField[]) { |
57 | VMSTATE_UINT32(ctlr, GICv3ITSState), |
58 | VMSTATE_UINT32(iidr, GICv3ITSState), |
59 | VMSTATE_UINT64(cbaser, GICv3ITSState), |
60 | VMSTATE_UINT64(cwriter, GICv3ITSState), |
61 | VMSTATE_UINT64(creadr, GICv3ITSState), |
62 | VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), |
63 | VMSTATE_END_OF_LIST() |
64 | }, |
65 | }; |
66 | |
67 | static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, |
68 | uint64_t *data, unsigned size, |
69 | MemTxAttrs attrs) |
70 | { |
71 | qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%" PRIx64"\n" , offset); |
72 | *data = 0; |
73 | return MEMTX_OK; |
74 | } |
75 | |
76 | static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, |
77 | uint64_t value, unsigned size, |
78 | MemTxAttrs attrs) |
79 | { |
80 | if (offset == 0x0040 && ((size == 2) || (size == 4))) { |
81 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque); |
82 | GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s); |
83 | int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id); |
84 | |
85 | if (ret <= 0) { |
86 | qemu_log_mask(LOG_GUEST_ERROR, |
87 | "ITS: Error sending MSI: %s\n" , strerror(-ret)); |
88 | } |
89 | } else { |
90 | qemu_log_mask(LOG_GUEST_ERROR, |
91 | "ITS write at bad offset 0x%" PRIx64"\n" , offset); |
92 | } |
93 | return MEMTX_OK; |
94 | } |
95 | |
96 | static const MemoryRegionOps gicv3_its_trans_ops = { |
97 | .read_with_attrs = gicv3_its_trans_read, |
98 | .write_with_attrs = gicv3_its_trans_write, |
99 | .endianness = DEVICE_NATIVE_ENDIAN, |
100 | }; |
101 | |
102 | void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops) |
103 | { |
104 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); |
105 | |
106 | memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s, |
107 | "control" , ITS_CONTROL_SIZE); |
108 | memory_region_init_io(&s->iomem_its_translation, OBJECT(s), |
109 | &gicv3_its_trans_ops, s, |
110 | "translation" , ITS_TRANS_SIZE); |
111 | |
112 | /* Our two regions are always adjacent, therefore we now combine them |
113 | * into a single one in order to make our users' life easier. |
114 | */ |
115 | memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its" , ITS_SIZE); |
116 | memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl); |
117 | memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE, |
118 | &s->iomem_its_translation); |
119 | sysbus_init_mmio(sbd, &s->iomem_main); |
120 | |
121 | msi_nonbroken = true; |
122 | } |
123 | |
124 | static void gicv3_its_common_reset(DeviceState *dev) |
125 | { |
126 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); |
127 | |
128 | s->ctlr = 0; |
129 | s->cbaser = 0; |
130 | s->cwriter = 0; |
131 | s->creadr = 0; |
132 | s->iidr = 0; |
133 | memset(&s->baser, 0, sizeof(s->baser)); |
134 | } |
135 | |
136 | static void gicv3_its_common_class_init(ObjectClass *klass, void *data) |
137 | { |
138 | DeviceClass *dc = DEVICE_CLASS(klass); |
139 | |
140 | dc->reset = gicv3_its_common_reset; |
141 | dc->vmsd = &vmstate_its; |
142 | } |
143 | |
144 | static const TypeInfo gicv3_its_common_info = { |
145 | .name = TYPE_ARM_GICV3_ITS_COMMON, |
146 | .parent = TYPE_SYS_BUS_DEVICE, |
147 | .instance_size = sizeof(GICv3ITSState), |
148 | .class_size = sizeof(GICv3ITSCommonClass), |
149 | .class_init = gicv3_its_common_class_init, |
150 | .abstract = true, |
151 | }; |
152 | |
153 | static void gicv3_its_common_register_types(void) |
154 | { |
155 | type_register_static(&gicv3_its_common_info); |
156 | } |
157 | |
158 | type_init(gicv3_its_common_register_types) |
159 | |