1 | /* |
2 | * Arm PrimeCell PL190 Vector Interrupt Controller |
3 | * |
4 | * Copyright (c) 2006 CodeSourcery. |
5 | * Written by Paul Brook |
6 | * |
7 | * This code is licensed under the GPL. |
8 | */ |
9 | |
10 | #include "qemu/osdep.h" |
11 | #include "hw/irq.h" |
12 | #include "hw/sysbus.h" |
13 | #include "migration/vmstate.h" |
14 | #include "qemu/log.h" |
15 | #include "qemu/module.h" |
16 | |
17 | /* The number of virtual priority levels. 16 user vectors plus the |
18 | unvectored IRQ. Chained interrupts would require an additional level |
19 | if implemented. */ |
20 | |
21 | #define PL190_NUM_PRIO 17 |
22 | |
23 | #define TYPE_PL190 "pl190" |
24 | #define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190) |
25 | |
26 | typedef struct PL190State { |
27 | SysBusDevice parent_obj; |
28 | |
29 | MemoryRegion iomem; |
30 | uint32_t level; |
31 | uint32_t soft_level; |
32 | uint32_t irq_enable; |
33 | uint32_t fiq_select; |
34 | uint8_t vect_control[16]; |
35 | uint32_t vect_addr[PL190_NUM_PRIO]; |
36 | /* Mask containing interrupts with higher priority than this one. */ |
37 | uint32_t prio_mask[PL190_NUM_PRIO + 1]; |
38 | int protected; |
39 | /* Current priority level. */ |
40 | int priority; |
41 | int prev_prio[PL190_NUM_PRIO]; |
42 | qemu_irq irq; |
43 | qemu_irq fiq; |
44 | } PL190State; |
45 | |
46 | static const unsigned char pl190_id[] = |
47 | { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; |
48 | |
49 | static inline uint32_t pl190_irq_level(PL190State *s) |
50 | { |
51 | return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select; |
52 | } |
53 | |
54 | /* Update interrupts. */ |
55 | static void pl190_update(PL190State *s) |
56 | { |
57 | uint32_t level = pl190_irq_level(s); |
58 | int set; |
59 | |
60 | set = (level & s->prio_mask[s->priority]) != 0; |
61 | qemu_set_irq(s->irq, set); |
62 | set = ((s->level | s->soft_level) & s->fiq_select) != 0; |
63 | qemu_set_irq(s->fiq, set); |
64 | } |
65 | |
66 | static void pl190_set_irq(void *opaque, int irq, int level) |
67 | { |
68 | PL190State *s = (PL190State *)opaque; |
69 | |
70 | if (level) |
71 | s->level |= 1u << irq; |
72 | else |
73 | s->level &= ~(1u << irq); |
74 | pl190_update(s); |
75 | } |
76 | |
77 | static void pl190_update_vectors(PL190State *s) |
78 | { |
79 | uint32_t mask; |
80 | int i; |
81 | int n; |
82 | |
83 | mask = 0; |
84 | for (i = 0; i < 16; i++) |
85 | { |
86 | s->prio_mask[i] = mask; |
87 | if (s->vect_control[i] & 0x20) |
88 | { |
89 | n = s->vect_control[i] & 0x1f; |
90 | mask |= 1 << n; |
91 | } |
92 | } |
93 | s->prio_mask[16] = mask; |
94 | pl190_update(s); |
95 | } |
96 | |
97 | static uint64_t pl190_read(void *opaque, hwaddr offset, |
98 | unsigned size) |
99 | { |
100 | PL190State *s = (PL190State *)opaque; |
101 | int i; |
102 | |
103 | if (offset >= 0xfe0 && offset < 0x1000) { |
104 | return pl190_id[(offset - 0xfe0) >> 2]; |
105 | } |
106 | if (offset >= 0x100 && offset < 0x140) { |
107 | return s->vect_addr[(offset - 0x100) >> 2]; |
108 | } |
109 | if (offset >= 0x200 && offset < 0x240) { |
110 | return s->vect_control[(offset - 0x200) >> 2]; |
111 | } |
112 | switch (offset >> 2) { |
113 | case 0: /* IRQSTATUS */ |
114 | return pl190_irq_level(s); |
115 | case 1: /* FIQSATUS */ |
116 | return (s->level | s->soft_level) & s->fiq_select; |
117 | case 2: /* RAWINTR */ |
118 | return s->level | s->soft_level; |
119 | case 3: /* INTSELECT */ |
120 | return s->fiq_select; |
121 | case 4: /* INTENABLE */ |
122 | return s->irq_enable; |
123 | case 6: /* SOFTINT */ |
124 | return s->soft_level; |
125 | case 8: /* PROTECTION */ |
126 | return s->protected; |
127 | case 12: /* VECTADDR */ |
128 | /* Read vector address at the start of an ISR. Increases the |
129 | * current priority level to that of the current interrupt. |
130 | * |
131 | * Since an enabled interrupt X at priority P causes prio_mask[Y] |
132 | * to have bit X set for all Y > P, this loop will stop with |
133 | * i == the priority of the highest priority set interrupt. |
134 | */ |
135 | for (i = 0; i < s->priority; i++) { |
136 | if ((s->level | s->soft_level) & s->prio_mask[i + 1]) { |
137 | break; |
138 | } |
139 | } |
140 | |
141 | /* Reading this value with no pending interrupts is undefined. |
142 | We return the default address. */ |
143 | if (i == PL190_NUM_PRIO) |
144 | return s->vect_addr[16]; |
145 | if (i < s->priority) |
146 | { |
147 | s->prev_prio[i] = s->priority; |
148 | s->priority = i; |
149 | pl190_update(s); |
150 | } |
151 | return s->vect_addr[s->priority]; |
152 | case 13: /* DEFVECTADDR */ |
153 | return s->vect_addr[16]; |
154 | default: |
155 | qemu_log_mask(LOG_GUEST_ERROR, |
156 | "pl190_read: Bad offset %x\n" , (int)offset); |
157 | return 0; |
158 | } |
159 | } |
160 | |
161 | static void pl190_write(void *opaque, hwaddr offset, |
162 | uint64_t val, unsigned size) |
163 | { |
164 | PL190State *s = (PL190State *)opaque; |
165 | |
166 | if (offset >= 0x100 && offset < 0x140) { |
167 | s->vect_addr[(offset - 0x100) >> 2] = val; |
168 | pl190_update_vectors(s); |
169 | return; |
170 | } |
171 | if (offset >= 0x200 && offset < 0x240) { |
172 | s->vect_control[(offset - 0x200) >> 2] = val; |
173 | pl190_update_vectors(s); |
174 | return; |
175 | } |
176 | switch (offset >> 2) { |
177 | case 0: /* SELECT */ |
178 | /* This is a readonly register, but linux tries to write to it |
179 | anyway. Ignore the write. */ |
180 | break; |
181 | case 3: /* INTSELECT */ |
182 | s->fiq_select = val; |
183 | break; |
184 | case 4: /* INTENABLE */ |
185 | s->irq_enable |= val; |
186 | break; |
187 | case 5: /* INTENCLEAR */ |
188 | s->irq_enable &= ~val; |
189 | break; |
190 | case 6: /* SOFTINT */ |
191 | s->soft_level |= val; |
192 | break; |
193 | case 7: /* SOFTINTCLEAR */ |
194 | s->soft_level &= ~val; |
195 | break; |
196 | case 8: /* PROTECTION */ |
197 | /* TODO: Protection (supervisor only access) is not implemented. */ |
198 | s->protected = val & 1; |
199 | break; |
200 | case 12: /* VECTADDR */ |
201 | /* Restore the previous priority level. The value written is |
202 | ignored. */ |
203 | if (s->priority < PL190_NUM_PRIO) |
204 | s->priority = s->prev_prio[s->priority]; |
205 | break; |
206 | case 13: /* DEFVECTADDR */ |
207 | s->vect_addr[16] = val; |
208 | break; |
209 | case 0xc0: /* ITCR */ |
210 | if (val) { |
211 | qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n" ); |
212 | } |
213 | break; |
214 | default: |
215 | qemu_log_mask(LOG_GUEST_ERROR, |
216 | "pl190_write: Bad offset %x\n" , (int)offset); |
217 | return; |
218 | } |
219 | pl190_update(s); |
220 | } |
221 | |
222 | static const MemoryRegionOps pl190_ops = { |
223 | .read = pl190_read, |
224 | .write = pl190_write, |
225 | .endianness = DEVICE_NATIVE_ENDIAN, |
226 | }; |
227 | |
228 | static void pl190_reset(DeviceState *d) |
229 | { |
230 | PL190State *s = PL190(d); |
231 | int i; |
232 | |
233 | for (i = 0; i < 16; i++) { |
234 | s->vect_addr[i] = 0; |
235 | s->vect_control[i] = 0; |
236 | } |
237 | s->vect_addr[16] = 0; |
238 | s->prio_mask[17] = 0xffffffff; |
239 | s->priority = PL190_NUM_PRIO; |
240 | pl190_update_vectors(s); |
241 | } |
242 | |
243 | static void pl190_init(Object *obj) |
244 | { |
245 | DeviceState *dev = DEVICE(obj); |
246 | PL190State *s = PL190(obj); |
247 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
248 | |
249 | memory_region_init_io(&s->iomem, obj, &pl190_ops, s, "pl190" , 0x1000); |
250 | sysbus_init_mmio(sbd, &s->iomem); |
251 | qdev_init_gpio_in(dev, pl190_set_irq, 32); |
252 | sysbus_init_irq(sbd, &s->irq); |
253 | sysbus_init_irq(sbd, &s->fiq); |
254 | } |
255 | |
256 | static const VMStateDescription vmstate_pl190 = { |
257 | .name = "pl190" , |
258 | .version_id = 1, |
259 | .minimum_version_id = 1, |
260 | .fields = (VMStateField[]) { |
261 | VMSTATE_UINT32(level, PL190State), |
262 | VMSTATE_UINT32(soft_level, PL190State), |
263 | VMSTATE_UINT32(irq_enable, PL190State), |
264 | VMSTATE_UINT32(fiq_select, PL190State), |
265 | VMSTATE_UINT8_ARRAY(vect_control, PL190State, 16), |
266 | VMSTATE_UINT32_ARRAY(vect_addr, PL190State, PL190_NUM_PRIO), |
267 | VMSTATE_UINT32_ARRAY(prio_mask, PL190State, PL190_NUM_PRIO+1), |
268 | VMSTATE_INT32(protected, PL190State), |
269 | VMSTATE_INT32(priority, PL190State), |
270 | VMSTATE_INT32_ARRAY(prev_prio, PL190State, PL190_NUM_PRIO), |
271 | VMSTATE_END_OF_LIST() |
272 | } |
273 | }; |
274 | |
275 | static void pl190_class_init(ObjectClass *klass, void *data) |
276 | { |
277 | DeviceClass *dc = DEVICE_CLASS(klass); |
278 | |
279 | dc->reset = pl190_reset; |
280 | dc->vmsd = &vmstate_pl190; |
281 | } |
282 | |
283 | static const TypeInfo pl190_info = { |
284 | .name = TYPE_PL190, |
285 | .parent = TYPE_SYS_BUS_DEVICE, |
286 | .instance_size = sizeof(PL190State), |
287 | .instance_init = pl190_init, |
288 | .class_init = pl190_class_init, |
289 | }; |
290 | |
291 | static void pl190_register_types(void) |
292 | { |
293 | type_register_static(&pl190_info); |
294 | } |
295 | |
296 | type_init(pl190_register_types) |
297 | |