1 | /* |
2 | * INTC device simulation in PKUnity SoC |
3 | * |
4 | * Copyright (C) 2010-2012 Guan Xuetao |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as |
8 | * published by the Free Software Foundation, or any later version. |
9 | * See the COPYING file in the top-level directory. |
10 | */ |
11 | |
12 | #include "qemu/osdep.h" |
13 | #include "hw/irq.h" |
14 | #include "hw/sysbus.h" |
15 | |
16 | #undef DEBUG_PUV3 |
17 | #include "hw/unicore32/puv3.h" |
18 | #include "qemu/module.h" |
19 | |
20 | #define TYPE_PUV3_INTC "puv3_intc" |
21 | #define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC) |
22 | |
23 | typedef struct PUV3INTCState { |
24 | SysBusDevice parent_obj; |
25 | |
26 | MemoryRegion iomem; |
27 | qemu_irq parent_irq; |
28 | |
29 | uint32_t reg_ICMR; |
30 | uint32_t reg_ICPR; |
31 | } PUV3INTCState; |
32 | |
33 | /* Update interrupt status after enabled or pending bits have been changed. */ |
34 | static void puv3_intc_update(PUV3INTCState *s) |
35 | { |
36 | if (s->reg_ICMR & s->reg_ICPR) { |
37 | qemu_irq_raise(s->parent_irq); |
38 | } else { |
39 | qemu_irq_lower(s->parent_irq); |
40 | } |
41 | } |
42 | |
43 | /* Process a change in an external INTC input. */ |
44 | static void puv3_intc_handler(void *opaque, int irq, int level) |
45 | { |
46 | PUV3INTCState *s = opaque; |
47 | |
48 | DPRINTF("irq 0x%x, level 0x%x\n" , irq, level); |
49 | if (level) { |
50 | s->reg_ICPR |= (1 << irq); |
51 | } else { |
52 | s->reg_ICPR &= ~(1 << irq); |
53 | } |
54 | puv3_intc_update(s); |
55 | } |
56 | |
57 | static uint64_t puv3_intc_read(void *opaque, hwaddr offset, |
58 | unsigned size) |
59 | { |
60 | PUV3INTCState *s = opaque; |
61 | uint32_t ret = 0; |
62 | |
63 | switch (offset) { |
64 | case 0x04: /* INTC_ICMR */ |
65 | ret = s->reg_ICMR; |
66 | break; |
67 | case 0x0c: /* INTC_ICIP */ |
68 | ret = s->reg_ICPR; /* the same value with ICPR */ |
69 | break; |
70 | default: |
71 | DPRINTF("Bad offset %x\n" , (int)offset); |
72 | } |
73 | DPRINTF("offset 0x%x, value 0x%x\n" , offset, ret); |
74 | return ret; |
75 | } |
76 | |
77 | static void puv3_intc_write(void *opaque, hwaddr offset, |
78 | uint64_t value, unsigned size) |
79 | { |
80 | PUV3INTCState *s = opaque; |
81 | |
82 | DPRINTF("offset 0x%x, value 0x%x\n" , offset, value); |
83 | switch (offset) { |
84 | case 0x00: /* INTC_ICLR */ |
85 | case 0x14: /* INTC_ICCR */ |
86 | break; |
87 | case 0x04: /* INTC_ICMR */ |
88 | s->reg_ICMR = value; |
89 | break; |
90 | default: |
91 | DPRINTF("Bad offset 0x%x\n" , (int)offset); |
92 | return; |
93 | } |
94 | puv3_intc_update(s); |
95 | } |
96 | |
97 | static const MemoryRegionOps puv3_intc_ops = { |
98 | .read = puv3_intc_read, |
99 | .write = puv3_intc_write, |
100 | .impl = { |
101 | .min_access_size = 4, |
102 | .max_access_size = 4, |
103 | }, |
104 | .endianness = DEVICE_NATIVE_ENDIAN, |
105 | }; |
106 | |
107 | static void puv3_intc_realize(DeviceState *dev, Error **errp) |
108 | { |
109 | PUV3INTCState *s = PUV3_INTC(dev); |
110 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
111 | |
112 | qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR); |
113 | sysbus_init_irq(sbd, &s->parent_irq); |
114 | |
115 | s->reg_ICMR = 0; |
116 | s->reg_ICPR = 0; |
117 | |
118 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc" , |
119 | PUV3_REGS_OFFSET); |
120 | sysbus_init_mmio(sbd, &s->iomem); |
121 | } |
122 | |
123 | static void puv3_intc_class_init(ObjectClass *klass, void *data) |
124 | { |
125 | DeviceClass *dc = DEVICE_CLASS(klass); |
126 | dc->realize = puv3_intc_realize; |
127 | } |
128 | |
129 | static const TypeInfo puv3_intc_info = { |
130 | .name = TYPE_PUV3_INTC, |
131 | .parent = TYPE_SYS_BUS_DEVICE, |
132 | .instance_size = sizeof(PUV3INTCState), |
133 | .class_init = puv3_intc_class_init, |
134 | }; |
135 | |
136 | static void puv3_intc_register_type(void) |
137 | { |
138 | type_register_static(&puv3_intc_info); |
139 | } |
140 | |
141 | type_init(puv3_intc_register_type) |
142 | |