1 | /* |
2 | * Generic ISA Super I/O |
3 | * |
4 | * Copyright (c) 2010-2012 Herve Poussineau |
5 | * Copyright (c) 2011-2012 Andreas Färber |
6 | * Copyright (c) 2018 Philippe Mathieu-Daudé |
7 | * |
8 | * This code is licensed under the GNU GPLv2 and later. |
9 | * See the COPYING file in the top-level directory. |
10 | * SPDX-License-Identifier: GPL-2.0-or-later |
11 | */ |
12 | |
13 | #include "qemu/osdep.h" |
14 | #include "qemu/error-report.h" |
15 | #include "qemu/module.h" |
16 | #include "qapi/error.h" |
17 | #include "sysemu/sysemu.h" |
18 | #include "sysemu/blockdev.h" |
19 | #include "chardev/char.h" |
20 | #include "hw/isa/superio.h" |
21 | #include "hw/qdev-properties.h" |
22 | #include "hw/input/i8042.h" |
23 | #include "hw/char/serial.h" |
24 | #include "trace.h" |
25 | |
26 | static void isa_superio_realize(DeviceState *dev, Error **errp) |
27 | { |
28 | ISASuperIODevice *sio = ISA_SUPERIO(dev); |
29 | ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio); |
30 | ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev)); |
31 | ISADevice *isa; |
32 | DeviceState *d; |
33 | Chardev *chr; |
34 | DriveInfo *drive; |
35 | char *name; |
36 | int i; |
37 | |
38 | /* Parallel port */ |
39 | for (i = 0; i < k->parallel.count; i++) { |
40 | if (i >= ARRAY_SIZE(sio->parallel)) { |
41 | warn_report("superio: ignoring %td parallel controllers" , |
42 | k->parallel.count - ARRAY_SIZE(sio->parallel)); |
43 | break; |
44 | } |
45 | if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) { |
46 | /* FIXME use a qdev chardev prop instead of parallel_hds[] */ |
47 | chr = parallel_hds[i]; |
48 | if (chr == NULL) { |
49 | name = g_strdup_printf("discarding-parallel%d" , i); |
50 | chr = qemu_chr_new(name, "null" , NULL); |
51 | } else { |
52 | name = g_strdup_printf("parallel%d" , i); |
53 | } |
54 | isa = isa_create(bus, "isa-parallel" ); |
55 | d = DEVICE(isa); |
56 | qdev_prop_set_uint32(d, "index" , i); |
57 | if (k->parallel.get_iobase) { |
58 | qdev_prop_set_uint32(d, "iobase" , |
59 | k->parallel.get_iobase(sio, i)); |
60 | } |
61 | if (k->parallel.get_irq) { |
62 | qdev_prop_set_uint32(d, "irq" , k->parallel.get_irq(sio, i)); |
63 | } |
64 | qdev_prop_set_chr(d, "chardev" , chr); |
65 | qdev_init_nofail(d); |
66 | sio->parallel[i] = isa; |
67 | trace_superio_create_parallel(i, |
68 | k->parallel.get_iobase ? |
69 | k->parallel.get_iobase(sio, i) : -1, |
70 | k->parallel.get_irq ? |
71 | k->parallel.get_irq(sio, i) : -1); |
72 | object_property_add_child(OBJECT(dev), name, |
73 | OBJECT(sio->parallel[i]), NULL); |
74 | g_free(name); |
75 | } |
76 | } |
77 | |
78 | /* Serial */ |
79 | for (i = 0; i < k->serial.count; i++) { |
80 | if (i >= ARRAY_SIZE(sio->serial)) { |
81 | warn_report("superio: ignoring %td serial controllers" , |
82 | k->serial.count - ARRAY_SIZE(sio->serial)); |
83 | break; |
84 | } |
85 | if (!k->serial.is_enabled || k->serial.is_enabled(sio, i)) { |
86 | /* FIXME use a qdev chardev prop instead of serial_hd() */ |
87 | chr = serial_hd(i); |
88 | if (chr == NULL) { |
89 | name = g_strdup_printf("discarding-serial%d" , i); |
90 | chr = qemu_chr_new(name, "null" , NULL); |
91 | } else { |
92 | name = g_strdup_printf("serial%d" , i); |
93 | } |
94 | isa = isa_create(bus, TYPE_ISA_SERIAL); |
95 | d = DEVICE(isa); |
96 | qdev_prop_set_uint32(d, "index" , i); |
97 | if (k->serial.get_iobase) { |
98 | qdev_prop_set_uint32(d, "iobase" , |
99 | k->serial.get_iobase(sio, i)); |
100 | } |
101 | if (k->serial.get_irq) { |
102 | qdev_prop_set_uint32(d, "irq" , k->serial.get_irq(sio, i)); |
103 | } |
104 | qdev_prop_set_chr(d, "chardev" , chr); |
105 | qdev_init_nofail(d); |
106 | sio->serial[i] = isa; |
107 | trace_superio_create_serial(i, |
108 | k->serial.get_iobase ? |
109 | k->serial.get_iobase(sio, i) : -1, |
110 | k->serial.get_irq ? |
111 | k->serial.get_irq(sio, i) : -1); |
112 | object_property_add_child(OBJECT(dev), name, |
113 | OBJECT(sio->serial[0]), NULL); |
114 | g_free(name); |
115 | } |
116 | } |
117 | |
118 | /* Floppy disc */ |
119 | if (!k->floppy.is_enabled || k->floppy.is_enabled(sio, 0)) { |
120 | isa = isa_create(bus, "isa-fdc" ); |
121 | d = DEVICE(isa); |
122 | if (k->floppy.get_iobase) { |
123 | qdev_prop_set_uint32(d, "iobase" , k->floppy.get_iobase(sio, 0)); |
124 | } |
125 | if (k->floppy.get_irq) { |
126 | qdev_prop_set_uint32(d, "irq" , k->floppy.get_irq(sio, 0)); |
127 | } |
128 | /* FIXME use a qdev drive property instead of drive_get() */ |
129 | drive = drive_get(IF_FLOPPY, 0, 0); |
130 | if (drive != NULL) { |
131 | qdev_prop_set_drive(d, "driveA" , blk_by_legacy_dinfo(drive), |
132 | &error_fatal); |
133 | } |
134 | /* FIXME use a qdev drive property instead of drive_get() */ |
135 | drive = drive_get(IF_FLOPPY, 0, 1); |
136 | if (drive != NULL) { |
137 | qdev_prop_set_drive(d, "driveB" , blk_by_legacy_dinfo(drive), |
138 | &error_fatal); |
139 | } |
140 | qdev_init_nofail(d); |
141 | sio->floppy = isa; |
142 | trace_superio_create_floppy(0, |
143 | k->floppy.get_iobase ? |
144 | k->floppy.get_iobase(sio, 0) : -1, |
145 | k->floppy.get_irq ? |
146 | k->floppy.get_irq(sio, 0) : -1); |
147 | } |
148 | |
149 | /* Keyboard, mouse */ |
150 | sio->kbc = isa_create_simple(bus, TYPE_I8042); |
151 | |
152 | /* IDE */ |
153 | if (k->ide.count && (!k->ide.is_enabled || k->ide.is_enabled(sio, 0))) { |
154 | isa = isa_create(bus, "isa-ide" ); |
155 | d = DEVICE(isa); |
156 | if (k->ide.get_iobase) { |
157 | qdev_prop_set_uint32(d, "iobase" , k->ide.get_iobase(sio, 0)); |
158 | } |
159 | if (k->ide.get_iobase) { |
160 | qdev_prop_set_uint32(d, "iobase2" , k->ide.get_iobase(sio, 1)); |
161 | } |
162 | if (k->ide.get_irq) { |
163 | qdev_prop_set_uint32(d, "irq" , k->ide.get_irq(sio, 0)); |
164 | } |
165 | qdev_init_nofail(d); |
166 | sio->ide = isa; |
167 | trace_superio_create_ide(0, |
168 | k->ide.get_iobase ? |
169 | k->ide.get_iobase(sio, 0) : -1, |
170 | k->ide.get_irq ? |
171 | k->ide.get_irq(sio, 0) : -1); |
172 | } |
173 | } |
174 | |
175 | static void isa_superio_class_init(ObjectClass *oc, void *data) |
176 | { |
177 | DeviceClass *dc = DEVICE_CLASS(oc); |
178 | |
179 | dc->realize = isa_superio_realize; |
180 | /* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */ |
181 | dc->user_creatable = false; |
182 | } |
183 | |
184 | static const TypeInfo isa_superio_type_info = { |
185 | .name = TYPE_ISA_SUPERIO, |
186 | .parent = TYPE_ISA_DEVICE, |
187 | .abstract = true, |
188 | .class_size = sizeof(ISASuperIOClass), |
189 | .class_init = isa_superio_class_init, |
190 | }; |
191 | |
192 | /* SMS FDC37M817 Super I/O */ |
193 | static void fdc37m81x_class_init(ObjectClass *klass, void *data) |
194 | { |
195 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
196 | |
197 | sc->serial.count = 2; /* NS16C550A */ |
198 | sc->parallel.count = 1; |
199 | sc->floppy.count = 1; /* SMSC 82077AA Compatible */ |
200 | sc->ide.count = 0; |
201 | } |
202 | |
203 | static const TypeInfo fdc37m81x_type_info = { |
204 | .name = TYPE_FDC37M81X_SUPERIO, |
205 | .parent = TYPE_ISA_SUPERIO, |
206 | .instance_size = sizeof(ISASuperIODevice), |
207 | .class_init = fdc37m81x_class_init, |
208 | }; |
209 | |
210 | static void isa_superio_register_types(void) |
211 | { |
212 | type_register_static(&isa_superio_type_info); |
213 | type_register_static(&fdc37m81x_type_info); |
214 | } |
215 | |
216 | type_init(isa_superio_register_types) |
217 | |