1/*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26#ifndef HW_SERIAL_H
27#define HW_SERIAL_H
28
29#include "chardev/char-fe.h"
30#include "exec/memory.h"
31#include "qemu/fifo8.h"
32#include "chardev/char.h"
33
34#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
35
36typedef struct SerialState {
37 uint16_t divider;
38 uint8_t rbr; /* receive register */
39 uint8_t thr; /* transmit holding register */
40 uint8_t tsr; /* transmit shift register */
41 uint8_t ier;
42 uint8_t iir; /* read only */
43 uint8_t lcr;
44 uint8_t mcr;
45 uint8_t lsr; /* read only */
46 uint8_t msr; /* read only */
47 uint8_t scr;
48 uint8_t fcr;
49 uint8_t fcr_vmstate; /* we can't write directly this value
50 it has side effects */
51 /* NOTE: this hidden state is necessary for tx irq generation as
52 it can be reset while reading iir */
53 int thr_ipending;
54 qemu_irq irq;
55 CharBackend chr;
56 int last_break_enable;
57 int it_shift;
58 int baudbase;
59 uint32_t tsr_retry;
60 guint watch_tag;
61 uint32_t wakeup;
62
63 /* Time when the last byte was successfully sent out of the tsr */
64 uint64_t last_xmit_ts;
65 Fifo8 recv_fifo;
66 Fifo8 xmit_fifo;
67 /* Interrupt trigger level for recv_fifo */
68 uint8_t recv_fifo_itl;
69
70 QEMUTimer *fifo_timeout_timer;
71 int timeout_ipending; /* timeout interrupt pending state */
72
73 uint64_t char_transmit_time; /* time to transmit a char in ticks */
74 int poll_msl;
75
76 QEMUTimer *modem_status_poll;
77 MemoryRegion io;
78} SerialState;
79
80extern const VMStateDescription vmstate_serial;
81extern const MemoryRegionOps serial_io_ops;
82
83void serial_realize_core(SerialState *s, Error **errp);
84void serial_exit_core(SerialState *s);
85void serial_set_frequency(SerialState *s, uint32_t frequency);
86
87/* legacy pre qom */
88SerialState *serial_init(int base, qemu_irq irq, int baudbase,
89 Chardev *chr, MemoryRegion *system_io);
90SerialState *serial_mm_init(MemoryRegion *address_space,
91 hwaddr base, int it_shift,
92 qemu_irq irq, int baudbase,
93 Chardev *chr, enum device_endian end);
94
95/* serial-isa.c */
96
97#define MAX_ISA_SERIAL_PORTS 4
98
99#define TYPE_ISA_SERIAL "isa-serial"
100void serial_hds_isa_init(ISABus *bus, int from, int to);
101
102#endif
103