1 | /* |
2 | * QEMU PIIX4 PCI Bridge Emulation |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "hw/i386/pc.h" |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/isa/isa.h" |
29 | #include "hw/sysbus.h" |
30 | #include "migration/vmstate.h" |
31 | #include "sysemu/reset.h" |
32 | |
33 | PCIDevice *piix4_dev; |
34 | |
35 | typedef struct PIIX4State { |
36 | PCIDevice dev; |
37 | } PIIX4State; |
38 | |
39 | #define TYPE_PIIX4_PCI_DEVICE "PIIX4" |
40 | #define PIIX4_PCI_DEVICE(obj) \ |
41 | OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) |
42 | |
43 | static void piix4_reset(void *opaque) |
44 | { |
45 | PIIX4State *d = opaque; |
46 | uint8_t *pci_conf = d->dev.config; |
47 | |
48 | pci_conf[0x04] = 0x07; // master, memory and I/O |
49 | pci_conf[0x05] = 0x00; |
50 | pci_conf[0x06] = 0x00; |
51 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
52 | pci_conf[0x4c] = 0x4d; |
53 | pci_conf[0x4e] = 0x03; |
54 | pci_conf[0x4f] = 0x00; |
55 | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 |
56 | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 |
57 | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 |
58 | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 |
59 | pci_conf[0x69] = 0x02; |
60 | pci_conf[0x70] = 0x80; |
61 | pci_conf[0x76] = 0x0c; |
62 | pci_conf[0x77] = 0x0c; |
63 | pci_conf[0x78] = 0x02; |
64 | pci_conf[0x79] = 0x00; |
65 | pci_conf[0x80] = 0x00; |
66 | pci_conf[0x82] = 0x00; |
67 | pci_conf[0xa0] = 0x08; |
68 | pci_conf[0xa2] = 0x00; |
69 | pci_conf[0xa3] = 0x00; |
70 | pci_conf[0xa4] = 0x00; |
71 | pci_conf[0xa5] = 0x00; |
72 | pci_conf[0xa6] = 0x00; |
73 | pci_conf[0xa7] = 0x00; |
74 | pci_conf[0xa8] = 0x0f; |
75 | pci_conf[0xaa] = 0x00; |
76 | pci_conf[0xab] = 0x00; |
77 | pci_conf[0xac] = 0x00; |
78 | pci_conf[0xae] = 0x00; |
79 | } |
80 | |
81 | static const VMStateDescription vmstate_piix4 = { |
82 | .name = "PIIX4" , |
83 | .version_id = 2, |
84 | .minimum_version_id = 2, |
85 | .fields = (VMStateField[]) { |
86 | VMSTATE_PCI_DEVICE(dev, PIIX4State), |
87 | VMSTATE_END_OF_LIST() |
88 | } |
89 | }; |
90 | |
91 | static void piix4_realize(PCIDevice *dev, Error **errp) |
92 | { |
93 | PIIX4State *d = PIIX4_PCI_DEVICE(dev); |
94 | |
95 | if (!isa_bus_new(DEVICE(d), pci_address_space(dev), |
96 | pci_address_space_io(dev), errp)) { |
97 | return; |
98 | } |
99 | piix4_dev = &d->dev; |
100 | qemu_register_reset(piix4_reset, d); |
101 | } |
102 | |
103 | int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) |
104 | { |
105 | PCIDevice *d; |
106 | |
107 | d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4" ); |
108 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0" )); |
109 | return d->devfn; |
110 | } |
111 | |
112 | static void piix4_class_init(ObjectClass *klass, void *data) |
113 | { |
114 | DeviceClass *dc = DEVICE_CLASS(klass); |
115 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
116 | |
117 | k->realize = piix4_realize; |
118 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
119 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; |
120 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
121 | dc->desc = "ISA bridge" ; |
122 | dc->vmsd = &vmstate_piix4; |
123 | /* |
124 | * Reason: part of PIIX4 southbridge, needs to be wired up, |
125 | * e.g. by mips_malta_init() |
126 | */ |
127 | dc->user_creatable = false; |
128 | dc->hotpluggable = false; |
129 | } |
130 | |
131 | static const TypeInfo piix4_info = { |
132 | .name = TYPE_PIIX4_PCI_DEVICE, |
133 | .parent = TYPE_PCI_DEVICE, |
134 | .instance_size = sizeof(PIIX4State), |
135 | .class_init = piix4_class_init, |
136 | .interfaces = (InterfaceInfo[]) { |
137 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
138 | { }, |
139 | }, |
140 | }; |
141 | |
142 | static void piix4_register_types(void) |
143 | { |
144 | type_register_static(&piix4_info); |
145 | } |
146 | |
147 | type_init(piix4_register_types) |
148 | |