1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H |
3 | |
4 | #include "exec/memory.h" |
5 | #include "sysemu/dma.h" |
6 | |
7 | /* PCI includes legacy ISA access. */ |
8 | #include "hw/isa/isa.h" |
9 | |
10 | #include "hw/pci/pcie.h" |
11 | |
12 | extern bool pci_available; |
13 | |
14 | /* PCI bus */ |
15 | |
16 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
17 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
18 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
20 | #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) |
21 | #define PCI_BUS_MAX 256 |
22 | #define PCI_DEVFN_MAX 256 |
23 | #define PCI_SLOT_MAX 32 |
24 | #define PCI_FUNC_MAX 8 |
25 | |
26 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
27 | #include "hw/pci/pci_ids.h" |
28 | |
29 | /* QEMU-specific Vendor and Device ID definitions */ |
30 | |
31 | /* IBM (0x1014) */ |
32 | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
33 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
34 | |
35 | /* Hitachi (0x1054) */ |
36 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
37 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
38 | |
39 | /* Apple (0x106b) */ |
40 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
41 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
42 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
43 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
44 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
45 | |
46 | /* Realtek (0x10ec) */ |
47 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
48 | |
49 | /* Xilinx (0x10ee) */ |
50 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
51 | |
52 | /* Marvell (0x11ab) */ |
53 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
54 | |
55 | /* QEMU/Bochs VGA (0x1234) */ |
56 | #define PCI_VENDOR_ID_QEMU 0x1234 |
57 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
58 | |
59 | /* VMWare (0x15ad) */ |
60 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
61 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
62 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
63 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
64 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
65 | #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 |
66 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
67 | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
68 | |
69 | /* Intel (0x8086) */ |
70 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
71 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
72 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
73 | |
74 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
75 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
76 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
77 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
78 | |
79 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
80 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
81 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
82 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
83 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
84 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
85 | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
86 | #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 |
87 | #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013 |
88 | |
89 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
90 | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 |
91 | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 |
92 | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 |
93 | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 |
94 | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
95 | #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 |
96 | #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 |
97 | #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 |
98 | #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 |
99 | #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a |
100 | #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b |
101 | #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c |
102 | #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d |
103 | #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e |
104 | #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f |
105 | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
106 | |
107 | #define FMT_PCIBUS PRIx64 |
108 | |
109 | typedef uint64_t pcibus_t; |
110 | |
111 | struct PCIHostDeviceAddress { |
112 | unsigned int domain; |
113 | unsigned int bus; |
114 | unsigned int slot; |
115 | unsigned int function; |
116 | }; |
117 | |
118 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
119 | uint32_t address, uint32_t data, int len); |
120 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, |
121 | uint32_t address, int len); |
122 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
123 | pcibus_t addr, pcibus_t size, int type); |
124 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
125 | |
126 | typedef struct PCIIORegion { |
127 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
128 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
129 | pcibus_t size; |
130 | uint8_t type; |
131 | MemoryRegion *memory; |
132 | MemoryRegion *address_space; |
133 | } PCIIORegion; |
134 | |
135 | #define PCI_ROM_SLOT 6 |
136 | #define PCI_NUM_REGIONS 7 |
137 | |
138 | enum { |
139 | QEMU_PCI_VGA_MEM, |
140 | QEMU_PCI_VGA_IO_LO, |
141 | QEMU_PCI_VGA_IO_HI, |
142 | QEMU_PCI_VGA_NUM_REGIONS, |
143 | }; |
144 | |
145 | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 |
146 | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 |
147 | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 |
148 | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc |
149 | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 |
150 | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 |
151 | |
152 | #include "hw/pci/pci_regs.h" |
153 | |
154 | /* PCI HEADER_TYPE */ |
155 | #define 0x80 |
156 | |
157 | /* Size of the standard PCI config header */ |
158 | #define 0x40 |
159 | /* Size of the standard PCI config space */ |
160 | #define PCI_CONFIG_SPACE_SIZE 0x100 |
161 | /* Size of the standard PCIe config space: 4KB */ |
162 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
163 | |
164 | #define PCI_NUM_PINS 4 /* A-D */ |
165 | |
166 | /* Bits in cap_present field. */ |
167 | enum { |
168 | QEMU_PCI_CAP_MSI = 0x1, |
169 | QEMU_PCI_CAP_MSIX = 0x2, |
170 | QEMU_PCI_CAP_EXPRESS = 0x4, |
171 | |
172 | /* multifunction capable device */ |
173 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
174 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
175 | |
176 | /* command register SERR bit enabled */ |
177 | #define QEMU_PCI_CAP_SERR_BITNR 4 |
178 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), |
179 | /* Standard hot plug controller. */ |
180 | #define QEMU_PCI_SHPC_BITNR 5 |
181 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), |
182 | #define QEMU_PCI_SLOTID_BITNR 6 |
183 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), |
184 | /* PCI Express capability - Power Controller Present */ |
185 | #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 |
186 | QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), |
187 | /* Link active status in endpoint capability is always set */ |
188 | #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 |
189 | QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), |
190 | #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 |
191 | QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), |
192 | }; |
193 | |
194 | #define TYPE_PCI_DEVICE "pci-device" |
195 | #define PCI_DEVICE(obj) \ |
196 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) |
197 | #define PCI_DEVICE_CLASS(klass) \ |
198 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) |
199 | #define PCI_DEVICE_GET_CLASS(obj) \ |
200 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) |
201 | |
202 | /* Implemented by devices that can be plugged on PCI Express buses */ |
203 | #define INTERFACE_PCIE_DEVICE "pci-express-device" |
204 | |
205 | /* Implemented by devices that can be plugged on Conventional PCI buses */ |
206 | #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" |
207 | |
208 | typedef struct PCIINTxRoute { |
209 | enum { |
210 | PCI_INTX_ENABLED, |
211 | PCI_INTX_INVERTED, |
212 | PCI_INTX_DISABLED, |
213 | } mode; |
214 | int irq; |
215 | } PCIINTxRoute; |
216 | |
217 | typedef struct PCIDeviceClass { |
218 | DeviceClass parent_class; |
219 | |
220 | void (*realize)(PCIDevice *dev, Error **errp); |
221 | PCIUnregisterFunc *exit; |
222 | PCIConfigReadFunc *config_read; |
223 | PCIConfigWriteFunc *config_write; |
224 | |
225 | uint16_t vendor_id; |
226 | uint16_t device_id; |
227 | uint8_t revision; |
228 | uint16_t class_id; |
229 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ |
230 | uint16_t subsystem_id; /* only for header type = 0 */ |
231 | |
232 | /* |
233 | * pci-to-pci bridge or normal device. |
234 | * This doesn't mean pci host switch. |
235 | * When card bus bridge is supported, this would be enhanced. |
236 | */ |
237 | bool is_bridge; |
238 | |
239 | /* rom bar */ |
240 | const char *romfile; |
241 | } PCIDeviceClass; |
242 | |
243 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
244 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
245 | MSIMessage msg); |
246 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); |
247 | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
248 | unsigned int vector_start, |
249 | unsigned int vector_end); |
250 | |
251 | enum PCIReqIDType { |
252 | PCI_REQ_ID_INVALID = 0, |
253 | PCI_REQ_ID_BDF, |
254 | PCI_REQ_ID_SECONDARY_BUS, |
255 | PCI_REQ_ID_MAX, |
256 | }; |
257 | typedef enum PCIReqIDType PCIReqIDType; |
258 | |
259 | struct PCIReqIDCache { |
260 | PCIDevice *dev; |
261 | PCIReqIDType type; |
262 | }; |
263 | typedef struct PCIReqIDCache PCIReqIDCache; |
264 | |
265 | struct PCIDevice { |
266 | DeviceState qdev; |
267 | |
268 | /* PCI config space */ |
269 | uint8_t *config; |
270 | |
271 | /* Used to enable config checks on load. Note that writable bits are |
272 | * never checked even if set in cmask. */ |
273 | uint8_t *cmask; |
274 | |
275 | /* Used to implement R/W bytes */ |
276 | uint8_t *wmask; |
277 | |
278 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
279 | uint8_t *w1cmask; |
280 | |
281 | /* Used to allocate config space for capabilities. */ |
282 | uint8_t *used; |
283 | |
284 | /* the following fields are read only */ |
285 | int32_t devfn; |
286 | /* Cached device to fetch requester ID from, to avoid the PCI |
287 | * tree walking every time we invoke PCI request (e.g., |
288 | * MSI). For conventional PCI root complex, this field is |
289 | * meaningless. */ |
290 | PCIReqIDCache requester_id_cache; |
291 | char name[64]; |
292 | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
293 | AddressSpace bus_master_as; |
294 | MemoryRegion bus_master_container_region; |
295 | MemoryRegion bus_master_enable_region; |
296 | |
297 | /* do not access the following fields */ |
298 | PCIConfigReadFunc *config_read; |
299 | PCIConfigWriteFunc *config_write; |
300 | |
301 | /* Legacy PCI VGA regions */ |
302 | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; |
303 | bool has_vga; |
304 | |
305 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
306 | uint8_t irq_state; |
307 | |
308 | /* Capability bits */ |
309 | uint32_t cap_present; |
310 | |
311 | /* Offset of MSI-X capability in config space */ |
312 | uint8_t msix_cap; |
313 | |
314 | /* MSI-X entries */ |
315 | int msix_entries_nr; |
316 | |
317 | /* Space to store MSIX table & pending bit array */ |
318 | uint8_t *msix_table; |
319 | uint8_t *msix_pba; |
320 | /* MemoryRegion container for msix exclusive BAR setup */ |
321 | MemoryRegion msix_exclusive_bar; |
322 | /* Memory Regions for MSIX table and pending bit entries. */ |
323 | MemoryRegion msix_table_mmio; |
324 | MemoryRegion msix_pba_mmio; |
325 | /* Reference-count for entries actually in use by driver. */ |
326 | unsigned *msix_entry_used; |
327 | /* MSIX function mask set or MSIX disabled */ |
328 | bool msix_function_masked; |
329 | /* Version id needed for VMState */ |
330 | int32_t version_id; |
331 | |
332 | /* Offset of MSI capability in config space */ |
333 | uint8_t msi_cap; |
334 | |
335 | /* PCI Express */ |
336 | PCIExpressDevice exp; |
337 | |
338 | /* SHPC */ |
339 | SHPCDevice *shpc; |
340 | |
341 | /* Location of option rom */ |
342 | char *romfile; |
343 | bool has_rom; |
344 | MemoryRegion rom; |
345 | uint32_t rom_bar; |
346 | |
347 | /* INTx routing notifier */ |
348 | PCIINTxRoutingNotifier intx_routing_notifier; |
349 | |
350 | /* MSI-X notifiers */ |
351 | MSIVectorUseNotifier msix_vector_use_notifier; |
352 | MSIVectorReleaseNotifier msix_vector_release_notifier; |
353 | MSIVectorPollNotifier msix_vector_poll_notifier; |
354 | }; |
355 | |
356 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
357 | uint8_t attr, MemoryRegion *memory); |
358 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
359 | MemoryRegion *io_lo, MemoryRegion *io_hi); |
360 | void pci_unregister_vga(PCIDevice *pci_dev); |
361 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
362 | |
363 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
364 | uint8_t offset, uint8_t size, |
365 | Error **errp); |
366 | |
367 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); |
368 | |
369 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
370 | |
371 | |
372 | uint32_t pci_default_read_config(PCIDevice *d, |
373 | uint32_t address, int len); |
374 | void pci_default_write_config(PCIDevice *d, |
375 | uint32_t address, uint32_t val, int len); |
376 | void pci_device_save(PCIDevice *s, QEMUFile *f); |
377 | int pci_device_load(PCIDevice *s, QEMUFile *f); |
378 | MemoryRegion *pci_address_space(PCIDevice *dev); |
379 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
380 | |
381 | /* |
382 | * Should not normally be used by devices. For use by sPAPR target |
383 | * where QEMU emulates firmware. |
384 | */ |
385 | int pci_bar(PCIDevice *d, int reg); |
386 | |
387 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
388 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
389 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
390 | |
391 | #define TYPE_PCI_BUS "PCI" |
392 | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) |
393 | #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) |
394 | #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) |
395 | #define TYPE_PCIE_BUS "PCIE" |
396 | |
397 | bool pci_bus_is_express(PCIBus *bus); |
398 | |
399 | void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
400 | const char *name, |
401 | MemoryRegion *address_space_mem, |
402 | MemoryRegion *address_space_io, |
403 | uint8_t devfn_min, const char *typename); |
404 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, |
405 | MemoryRegion *address_space_mem, |
406 | MemoryRegion *address_space_io, |
407 | uint8_t devfn_min, const char *typename); |
408 | void pci_root_bus_cleanup(PCIBus *bus); |
409 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
410 | void *irq_opaque, int nirq); |
411 | void pci_bus_irqs_cleanup(PCIBus *bus); |
412 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
413 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
414 | static inline int pci_swizzle(int slot, int pin) |
415 | { |
416 | return (slot + pin) % PCI_NUM_PINS; |
417 | } |
418 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); |
419 | PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, |
420 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
421 | void *irq_opaque, |
422 | MemoryRegion *address_space_mem, |
423 | MemoryRegion *address_space_io, |
424 | uint8_t devfn_min, int nirq, |
425 | const char *typename); |
426 | void pci_unregister_root_bus(PCIBus *bus); |
427 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
428 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); |
429 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
430 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
431 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, |
432 | PCIINTxRoutingNotifier notifier); |
433 | void pci_device_reset(PCIDevice *dev); |
434 | |
435 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
436 | const char *default_model, |
437 | const char *default_devaddr); |
438 | |
439 | PCIDevice *pci_vga_init(PCIBus *bus); |
440 | |
441 | static inline PCIBus *pci_get_bus(const PCIDevice *dev) |
442 | { |
443 | return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); |
444 | } |
445 | int pci_bus_num(PCIBus *s); |
446 | static inline int pci_dev_bus_num(const PCIDevice *dev) |
447 | { |
448 | return pci_bus_num(pci_get_bus(dev)); |
449 | } |
450 | |
451 | int pci_bus_numa_node(PCIBus *bus); |
452 | void pci_for_each_device(PCIBus *bus, int bus_num, |
453 | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), |
454 | void *opaque); |
455 | void pci_for_each_device_reverse(PCIBus *bus, int bus_num, |
456 | void (*fn)(PCIBus *bus, PCIDevice *d, |
457 | void *opaque), |
458 | void *opaque); |
459 | void pci_for_each_bus_depth_first(PCIBus *bus, |
460 | void *(*begin)(PCIBus *bus, void *parent_state), |
461 | void (*end)(PCIBus *bus, void *state), |
462 | void *parent_state); |
463 | PCIDevice *pci_get_function_0(PCIDevice *pci_dev); |
464 | |
465 | /* Use this wrapper when specific scan order is not required. */ |
466 | static inline |
467 | void pci_for_each_bus(PCIBus *bus, |
468 | void (*fn)(PCIBus *bus, void *opaque), |
469 | void *opaque) |
470 | { |
471 | pci_for_each_bus_depth_first(bus, NULL, fn, opaque); |
472 | } |
473 | |
474 | PCIBus *pci_device_root_bus(const PCIDevice *d); |
475 | const char *pci_root_bus_path(PCIDevice *dev); |
476 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
477 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
478 | void pci_bus_get_w64_range(PCIBus *bus, Range *range); |
479 | |
480 | void pci_device_deassert_intx(PCIDevice *dev); |
481 | |
482 | typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); |
483 | |
484 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); |
485 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); |
486 | |
487 | static inline void |
488 | pci_set_byte(uint8_t *config, uint8_t val) |
489 | { |
490 | *config = val; |
491 | } |
492 | |
493 | static inline uint8_t |
494 | pci_get_byte(const uint8_t *config) |
495 | { |
496 | return *config; |
497 | } |
498 | |
499 | static inline void |
500 | pci_set_word(uint8_t *config, uint16_t val) |
501 | { |
502 | stw_le_p(config, val); |
503 | } |
504 | |
505 | static inline uint16_t |
506 | pci_get_word(const uint8_t *config) |
507 | { |
508 | return lduw_le_p(config); |
509 | } |
510 | |
511 | static inline void |
512 | pci_set_long(uint8_t *config, uint32_t val) |
513 | { |
514 | stl_le_p(config, val); |
515 | } |
516 | |
517 | static inline uint32_t |
518 | pci_get_long(const uint8_t *config) |
519 | { |
520 | return ldl_le_p(config); |
521 | } |
522 | |
523 | /* |
524 | * PCI capabilities and/or their fields |
525 | * are generally DWORD aligned only so |
526 | * mechanism used by pci_set/get_quad() |
527 | * must be tolerant to unaligned pointers |
528 | * |
529 | */ |
530 | static inline void |
531 | pci_set_quad(uint8_t *config, uint64_t val) |
532 | { |
533 | stq_le_p(config, val); |
534 | } |
535 | |
536 | static inline uint64_t |
537 | pci_get_quad(const uint8_t *config) |
538 | { |
539 | return ldq_le_p(config); |
540 | } |
541 | |
542 | static inline void |
543 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
544 | { |
545 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
546 | } |
547 | |
548 | static inline void |
549 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
550 | { |
551 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
552 | } |
553 | |
554 | static inline void |
555 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
556 | { |
557 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
558 | } |
559 | |
560 | static inline void |
561 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
562 | { |
563 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
564 | } |
565 | |
566 | static inline void |
567 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
568 | { |
569 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
570 | } |
571 | |
572 | static inline void |
573 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
574 | { |
575 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
576 | } |
577 | |
578 | /* |
579 | * helper functions to do bit mask operation on configuration space. |
580 | * Just to set bit, use test-and-set and discard returned value. |
581 | * Just to clear bit, use test-and-clear and discard returned value. |
582 | * NOTE: They aren't atomic. |
583 | */ |
584 | static inline uint8_t |
585 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
586 | { |
587 | uint8_t val = pci_get_byte(config); |
588 | pci_set_byte(config, val & ~mask); |
589 | return val & mask; |
590 | } |
591 | |
592 | static inline uint8_t |
593 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
594 | { |
595 | uint8_t val = pci_get_byte(config); |
596 | pci_set_byte(config, val | mask); |
597 | return val & mask; |
598 | } |
599 | |
600 | static inline uint16_t |
601 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
602 | { |
603 | uint16_t val = pci_get_word(config); |
604 | pci_set_word(config, val & ~mask); |
605 | return val & mask; |
606 | } |
607 | |
608 | static inline uint16_t |
609 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
610 | { |
611 | uint16_t val = pci_get_word(config); |
612 | pci_set_word(config, val | mask); |
613 | return val & mask; |
614 | } |
615 | |
616 | static inline uint32_t |
617 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
618 | { |
619 | uint32_t val = pci_get_long(config); |
620 | pci_set_long(config, val & ~mask); |
621 | return val & mask; |
622 | } |
623 | |
624 | static inline uint32_t |
625 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
626 | { |
627 | uint32_t val = pci_get_long(config); |
628 | pci_set_long(config, val | mask); |
629 | return val & mask; |
630 | } |
631 | |
632 | static inline uint64_t |
633 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
634 | { |
635 | uint64_t val = pci_get_quad(config); |
636 | pci_set_quad(config, val & ~mask); |
637 | return val & mask; |
638 | } |
639 | |
640 | static inline uint64_t |
641 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
642 | { |
643 | uint64_t val = pci_get_quad(config); |
644 | pci_set_quad(config, val | mask); |
645 | return val & mask; |
646 | } |
647 | |
648 | /* Access a register specified by a mask */ |
649 | static inline void |
650 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
651 | { |
652 | uint8_t val = pci_get_byte(config); |
653 | uint8_t rval = reg << ctz32(mask); |
654 | pci_set_byte(config, (~mask & val) | (mask & rval)); |
655 | } |
656 | |
657 | static inline uint8_t |
658 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) |
659 | { |
660 | uint8_t val = pci_get_byte(config); |
661 | return (val & mask) >> ctz32(mask); |
662 | } |
663 | |
664 | static inline void |
665 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
666 | { |
667 | uint16_t val = pci_get_word(config); |
668 | uint16_t rval = reg << ctz32(mask); |
669 | pci_set_word(config, (~mask & val) | (mask & rval)); |
670 | } |
671 | |
672 | static inline uint16_t |
673 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) |
674 | { |
675 | uint16_t val = pci_get_word(config); |
676 | return (val & mask) >> ctz32(mask); |
677 | } |
678 | |
679 | static inline void |
680 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
681 | { |
682 | uint32_t val = pci_get_long(config); |
683 | uint32_t rval = reg << ctz32(mask); |
684 | pci_set_long(config, (~mask & val) | (mask & rval)); |
685 | } |
686 | |
687 | static inline uint32_t |
688 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) |
689 | { |
690 | uint32_t val = pci_get_long(config); |
691 | return (val & mask) >> ctz32(mask); |
692 | } |
693 | |
694 | static inline void |
695 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
696 | { |
697 | uint64_t val = pci_get_quad(config); |
698 | uint64_t rval = reg << ctz32(mask); |
699 | pci_set_quad(config, (~mask & val) | (mask & rval)); |
700 | } |
701 | |
702 | static inline uint64_t |
703 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) |
704 | { |
705 | uint64_t val = pci_get_quad(config); |
706 | return (val & mask) >> ctz32(mask); |
707 | } |
708 | |
709 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
710 | const char *name); |
711 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
712 | bool multifunction, |
713 | const char *name); |
714 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
715 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
716 | |
717 | void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); |
718 | |
719 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev); |
720 | void pci_set_irq(PCIDevice *pci_dev, int level); |
721 | |
722 | static inline void pci_irq_assert(PCIDevice *pci_dev) |
723 | { |
724 | pci_set_irq(pci_dev, 1); |
725 | } |
726 | |
727 | static inline void pci_irq_deassert(PCIDevice *pci_dev) |
728 | { |
729 | pci_set_irq(pci_dev, 0); |
730 | } |
731 | |
732 | /* |
733 | * FIXME: PCI does not work this way. |
734 | * All the callers to this method should be fixed. |
735 | */ |
736 | static inline void pci_irq_pulse(PCIDevice *pci_dev) |
737 | { |
738 | pci_irq_assert(pci_dev); |
739 | pci_irq_deassert(pci_dev); |
740 | } |
741 | |
742 | static inline int pci_is_express(const PCIDevice *d) |
743 | { |
744 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; |
745 | } |
746 | |
747 | static inline int pci_is_express_downstream_port(const PCIDevice *d) |
748 | { |
749 | uint8_t type; |
750 | |
751 | if (!pci_is_express(d) || !d->exp.exp_cap) { |
752 | return 0; |
753 | } |
754 | |
755 | type = pcie_cap_get_type(d); |
756 | |
757 | return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; |
758 | } |
759 | |
760 | static inline uint32_t pci_config_size(const PCIDevice *d) |
761 | { |
762 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; |
763 | } |
764 | |
765 | static inline uint16_t pci_get_bdf(PCIDevice *dev) |
766 | { |
767 | return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); |
768 | } |
769 | |
770 | uint16_t pci_requester_id(PCIDevice *dev); |
771 | |
772 | /* DMA access functions */ |
773 | static inline AddressSpace *pci_get_address_space(PCIDevice *dev) |
774 | { |
775 | return &dev->bus_master_as; |
776 | } |
777 | |
778 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
779 | void *buf, dma_addr_t len, DMADirection dir) |
780 | { |
781 | dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); |
782 | return 0; |
783 | } |
784 | |
785 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
786 | void *buf, dma_addr_t len) |
787 | { |
788 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
789 | } |
790 | |
791 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
792 | const void *buf, dma_addr_t len) |
793 | { |
794 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); |
795 | } |
796 | |
797 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ |
798 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ |
799 | dma_addr_t addr) \ |
800 | { \ |
801 | return ld##_l##_dma(pci_get_address_space(dev), addr); \ |
802 | } \ |
803 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ |
804 | dma_addr_t addr, uint##_bits##_t val) \ |
805 | { \ |
806 | st##_s##_dma(pci_get_address_space(dev), addr, val); \ |
807 | } |
808 | |
809 | PCI_DMA_DEFINE_LDST(ub, b, 8); |
810 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) |
811 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); |
812 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); |
813 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) |
814 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); |
815 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); |
816 | |
817 | #undef PCI_DMA_DEFINE_LDST |
818 | |
819 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
820 | dma_addr_t *plen, DMADirection dir) |
821 | { |
822 | void *buf; |
823 | |
824 | buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); |
825 | return buf; |
826 | } |
827 | |
828 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
829 | DMADirection dir, dma_addr_t access_len) |
830 | { |
831 | dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); |
832 | } |
833 | |
834 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
835 | int alloc_hint) |
836 | { |
837 | qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); |
838 | } |
839 | |
840 | extern const VMStateDescription vmstate_pci_device; |
841 | |
842 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ |
843 | .name = (stringify(_field)), \ |
844 | .size = sizeof(PCIDevice), \ |
845 | .vmsd = &vmstate_pci_device, \ |
846 | .flags = VMS_STRUCT, \ |
847 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
848 | } |
849 | |
850 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ |
851 | .name = (stringify(_field)), \ |
852 | .size = sizeof(PCIDevice), \ |
853 | .vmsd = &vmstate_pci_device, \ |
854 | .flags = VMS_STRUCT|VMS_POINTER, \ |
855 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
856 | } |
857 | |
858 | MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); |
859 | |
860 | #endif |
861 | |