1 | /* |
2 | * ColdFire Interrupt Controller emulation. |
3 | * |
4 | * Copyright (c) 2007 CodeSourcery. |
5 | * |
6 | * This code is licensed under the GPL |
7 | */ |
8 | |
9 | #include "qemu/osdep.h" |
10 | #include "qemu/module.h" |
11 | #include "cpu.h" |
12 | #include "hw/hw.h" |
13 | #include "hw/irq.h" |
14 | #include "hw/sysbus.h" |
15 | #include "hw/m68k/mcf.h" |
16 | |
17 | #define TYPE_MCF_INTC "mcf-intc" |
18 | #define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC) |
19 | |
20 | typedef struct { |
21 | SysBusDevice parent_obj; |
22 | |
23 | MemoryRegion iomem; |
24 | uint64_t ipr; |
25 | uint64_t imr; |
26 | uint64_t ifr; |
27 | uint64_t enabled; |
28 | uint8_t icr[64]; |
29 | M68kCPU *cpu; |
30 | int active_vector; |
31 | } mcf_intc_state; |
32 | |
33 | static void mcf_intc_update(mcf_intc_state *s) |
34 | { |
35 | uint64_t active; |
36 | int i; |
37 | int best; |
38 | int best_level; |
39 | |
40 | active = (s->ipr | s->ifr) & s->enabled & ~s->imr; |
41 | best_level = 0; |
42 | best = 64; |
43 | if (active) { |
44 | for (i = 0; i < 64; i++) { |
45 | if ((active & 1) != 0 && s->icr[i] >= best_level) { |
46 | best_level = s->icr[i]; |
47 | best = i; |
48 | } |
49 | active >>= 1; |
50 | } |
51 | } |
52 | s->active_vector = ((best == 64) ? 24 : (best + 64)); |
53 | m68k_set_irq_level(s->cpu, best_level, s->active_vector); |
54 | } |
55 | |
56 | static uint64_t mcf_intc_read(void *opaque, hwaddr addr, |
57 | unsigned size) |
58 | { |
59 | int offset; |
60 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
61 | offset = addr & 0xff; |
62 | if (offset >= 0x40 && offset < 0x80) { |
63 | return s->icr[offset - 0x40]; |
64 | } |
65 | switch (offset) { |
66 | case 0x00: |
67 | return (uint32_t)(s->ipr >> 32); |
68 | case 0x04: |
69 | return (uint32_t)s->ipr; |
70 | case 0x08: |
71 | return (uint32_t)(s->imr >> 32); |
72 | case 0x0c: |
73 | return (uint32_t)s->imr; |
74 | case 0x10: |
75 | return (uint32_t)(s->ifr >> 32); |
76 | case 0x14: |
77 | return (uint32_t)s->ifr; |
78 | case 0xe0: /* SWIACK. */ |
79 | return s->active_vector; |
80 | case 0xe1: case 0xe2: case 0xe3: case 0xe4: |
81 | case 0xe5: case 0xe6: case 0xe7: |
82 | /* LnIACK */ |
83 | hw_error("mcf_intc_read: LnIACK not implemented\n" ); |
84 | default: |
85 | return 0; |
86 | } |
87 | } |
88 | |
89 | static void mcf_intc_write(void *opaque, hwaddr addr, |
90 | uint64_t val, unsigned size) |
91 | { |
92 | int offset; |
93 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
94 | offset = addr & 0xff; |
95 | if (offset >= 0x40 && offset < 0x80) { |
96 | int n = offset - 0x40; |
97 | s->icr[n] = val; |
98 | if (val == 0) |
99 | s->enabled &= ~(1ull << n); |
100 | else |
101 | s->enabled |= (1ull << n); |
102 | mcf_intc_update(s); |
103 | return; |
104 | } |
105 | switch (offset) { |
106 | case 0x00: case 0x04: |
107 | /* Ignore IPR writes. */ |
108 | return; |
109 | case 0x08: |
110 | s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); |
111 | break; |
112 | case 0x0c: |
113 | s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; |
114 | break; |
115 | case 0x1c: |
116 | if (val & 0x40) { |
117 | s->imr = ~0ull; |
118 | } else { |
119 | s->imr |= (0x1ull << (val & 0x3f)); |
120 | } |
121 | break; |
122 | case 0x1d: |
123 | if (val & 0x40) { |
124 | s->imr = 0ull; |
125 | } else { |
126 | s->imr &= ~(0x1ull << (val & 0x3f)); |
127 | } |
128 | break; |
129 | default: |
130 | hw_error("mcf_intc_write: Bad write offset %d\n" , offset); |
131 | break; |
132 | } |
133 | mcf_intc_update(s); |
134 | } |
135 | |
136 | static void mcf_intc_set_irq(void *opaque, int irq, int level) |
137 | { |
138 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
139 | if (irq >= 64) |
140 | return; |
141 | if (level) |
142 | s->ipr |= 1ull << irq; |
143 | else |
144 | s->ipr &= ~(1ull << irq); |
145 | mcf_intc_update(s); |
146 | } |
147 | |
148 | static void mcf_intc_reset(DeviceState *dev) |
149 | { |
150 | mcf_intc_state *s = MCF_INTC(dev); |
151 | |
152 | s->imr = ~0ull; |
153 | s->ipr = 0; |
154 | s->ifr = 0; |
155 | s->enabled = 0; |
156 | memset(s->icr, 0, 64); |
157 | s->active_vector = 24; |
158 | } |
159 | |
160 | static const MemoryRegionOps mcf_intc_ops = { |
161 | .read = mcf_intc_read, |
162 | .write = mcf_intc_write, |
163 | .endianness = DEVICE_NATIVE_ENDIAN, |
164 | }; |
165 | |
166 | static void mcf_intc_instance_init(Object *obj) |
167 | { |
168 | mcf_intc_state *s = MCF_INTC(obj); |
169 | |
170 | memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf" , 0x100); |
171 | } |
172 | |
173 | static void mcf_intc_class_init(ObjectClass *oc, void *data) |
174 | { |
175 | DeviceClass *dc = DEVICE_CLASS(oc); |
176 | |
177 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
178 | dc->reset = mcf_intc_reset; |
179 | } |
180 | |
181 | static const TypeInfo mcf_intc_gate_info = { |
182 | .name = TYPE_MCF_INTC, |
183 | .parent = TYPE_SYS_BUS_DEVICE, |
184 | .instance_size = sizeof(mcf_intc_state), |
185 | .instance_init = mcf_intc_instance_init, |
186 | .class_init = mcf_intc_class_init, |
187 | }; |
188 | |
189 | static void mcf_intc_register_types(void) |
190 | { |
191 | type_register_static(&mcf_intc_gate_info); |
192 | } |
193 | |
194 | type_init(mcf_intc_register_types) |
195 | |
196 | qemu_irq *mcf_intc_init(MemoryRegion *sysmem, |
197 | hwaddr base, |
198 | M68kCPU *cpu) |
199 | { |
200 | DeviceState *dev; |
201 | mcf_intc_state *s; |
202 | |
203 | dev = qdev_create(NULL, TYPE_MCF_INTC); |
204 | qdev_init_nofail(dev); |
205 | |
206 | s = MCF_INTC(dev); |
207 | s->cpu = cpu; |
208 | |
209 | memory_region_add_subregion(sysmem, base, &s->iomem); |
210 | |
211 | return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); |
212 | } |
213 | |